⚝
One Hat Cyber Team
⚝
Your IP:
216.73.216.144
Server IP:
157.245.143.252
Server:
Linux www 6.11.0-9-generic #9-Ubuntu SMP PREEMPT_DYNAMIC Mon Oct 14 13:19:59 UTC 2024 x86_64
Server Software:
nginx/1.26.0
PHP Version:
8.3.11
Buat File
|
Buat Folder
Eksekusi
Dir :
~
/
lib
/
linux-tools
/
6.11.0-29-generic
/
lib
/
View File Name :
perf.cpython-312-x86_64-linux-gnu.so
ELF > @ Ҝ @ 8 @ ( ' Yi Yi & & & (f (f h_ Ս 8 8 8 Ptd 8 8 8 4 4 Qtd Rtd x x GNU ?JENQF!P \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} \ ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"6.11.0-29.29","architecture":"amd64"} ^ `(! DC "P@ & % @ $A P ( @ ` Ё!! `@@J@#i @P !L"BPR@ dDB A ! B D"(P B@ @Q @e "@P 9 Q J B @ P` P @ ` 8$M$D @ A( H AC @ "CD P " C H D6 D( X 8%@D " \ ! @D @f@ "@ B@ H 0 <! % @ @ F A@ ` 0 GBFDcH0E @U D !LE ! $ H D$ D c( D A !@ B H" (I @: b PXh P@@ @! B @ @ H MPA (D@ ". @! !$ 5 8 0 0 fA @@ 䁀HA(ʖ @ @ P AB C Zp @ F AP @DRC & C "P @ P t J B @ $PEPHi `@ (@ 0LH2! !L R B D A$ ( $ @` G$A (R " B B *$@ J @ @ ! ` @Bd $ ( 0HK A" $%A (DB9 ` D @ 2 ( LHAXc80Q[d @ Bj 3 H D3(! @B P )R PHD`@ @ (0 "ap D0 9 149(@H $ I ) A J@ @ @ E*a " , !H Q " @P $ H R @2 BRҤ( B * P A1 h ( @ F 0D B ( (0@ QQ !P (" H@ 0 H`T DP2 y EP#,b (B @L @k b D"B B % @ L B@@%b$ @ A)! p @ ` "H@@ HJ @% " @ L " ` $Mh 1 c H Ā! $P@ $ " ( ! @r Ѐ i E( A 0" H BFD D R " A dD KJ`r` X$ H B J # 4P0@ 0A 2 ( @ @R (h P $ qCPNM@HD% "D @ BDE2 H b H @ @ f1hAP J" *@ @hB Y@ ] (@ P ! P H #EH `@ 0.( @@ Q= A @D L @ A YI( 9 h@b ! @D@@ @`FHb`L @&@n@ !`$ ( @ d@ P @ hQA * ! @ C1$ L T @ V)BD0T!!~ A`F A B # % $ @ B@ ! 9g f D! b P"AH @ @ <$i pCB& @ & @ " " @D @@ H A R T$Qp0H f $ @ ! $ ` # @B 0@ ) $ !8$ D ( @ K@ U 0 @ `B BXHBɠ. B PY " @ D 4D@`68 % D (9a @ B7 `dX.0Ġ &J @H @ @`ޡ $ R*h00 I HA D T "`<$B@ G C @ $ *R` @ p a J @ 0IA 6A @" D $ @ *X@ H * @ @C 0" C $@ )0 a @ B@P`0 0 @# Ɇ % A 2 $ B D (J @ D H p (< @ B" H @ `( e`Љ %DD e 1 A@X) @ "@ A `ā " ( ) A @ $ ! @H @@ E @ " @ B D %8F)@D@ " !"T @ h D q ! ( @ X H!` : @ D(h H R! ( 9 $ @ X4 0 "P ! (P0 ^ _ ` d f j l o p q r u w z { # % ) - 1 5 6 : ; < > ? B D H I J L M N P R V Y Z ] ` b c d f g j m n p r u v x z { | } ~ ! # % & ) * + . 1 3 5 6 8 ; < = > ? @ A C E F H I M O T U W Z \ ] a b d e f i m n o r s u x { } ! # $ ) - 0 1 3 5 6 7 9 : = > ? A B D F H J L M N P R V W X [ \ ] ^ ` a b d e f k l o r t v x z } ! # & ' ( * + , / 3 4 5 6 : < > @ B C F H I K L O R S T U X Y \ ` b e g h i j k l m o p s w x { | } ~ # % ( ) , . 1 4 7 : < = > ? A B C H I K L N O P S V W X [ \ ^ _ ` d e h l m o r s v z | } ~ ! % ' ) * . 0 1 4 5 : ? @ A B D E G H J K L N O P R T U W X \ ] ^ ` b c f h k n p q s u x { | } ~ " % ( ) * , . 4 5 6 7 : < = ? @ A D E F G I K L N Q S T X Z [ _ ` d f g j k o p s w y { | ! " % ' ) * + , - . 0 3 6 : < > C I K M N P S V Y \ ^ _ a c f j m o q s x y { # & ' ( + - / 0 1 2 5 7 9 < = > @ A C E K L N O R T X Y Z ^ a b e f h l m q s t v x y z { | ~ ! " $ % & ( ) + , - . 0 1 2 3 5 6 9 < > ? E F G L M O P R S V Z \ _ d g h k l o p q t u v w y z } ~ $ % & ( ) + - / 1 4 6 8 ; = > ? @ B C E F I L O U X \ _ ` a b d f g i m n q s t v | ~ ! # & ( + , - 0 2 3 4 5 8 9 : < = @ A C E G I J K L N Q R U W X Z [ ^ ` b c e g i l m n p r t v y { | ~ V`iK^V1H ;x ~̒$emXx ~Lz ~_.\8EiwWEc{ ~֛G ܂oً`|XvC[67 -@p>6TO&F)]/}myӕ4nTmD`>jfu0B+\bVD'$0ݩ S2 Ϗ{+pkJn̓COޘZOMS5Ȣ ~kO= Kd@Ë DOĭs'-u2o oxPh'ӾcYԄqO-R}$ yDƦH!740#K\v sKqɮ y+'ZL-;xe%!6N)։ Ɗ}Dy %ekrÖc(!;g4l vosܵ8%gEWd2YogFN0Lu}ܒ XTTwV^=JCrb=PhiO5m&~7HZA_ */~"(آjOwR"=#jC/9ؗ \qI @Θ 3 GL s>|7{橭$ l7aerяW(RfMc&N<.F1B˱:ND*ܽt|qd i`nn% 7 cZ}slL' ,ߛMͨ JngRP hVU N 5d'^nuBXt4!MCf g6'D%E-5\UQsvդ@ T.1 A@~&r20 ? H9EW&ax8 2qR| [d,+[P?u;\:]!Ja\106=Lѩ<̊u*Wt;jl+\Gky䤬+Ȋz[5ݫKrV1c)}x #ϋ~ ;LJpBO JB $IV1=1Qp 9,E jzYf# M h|M;892M':<d_7CvcLt] E߹T;hȾd2V"uxL{|L6 Nz) #;9FaEPO! Vc+ +b:䤀; +} Ss#d` xdMX]M qA A^h' P2kܛud_V>/jMW$)n`X0Z9L ?zH@x©\*aBlSa] Jh&hF_P,2_}<Q2>Jh# v0l ٛ 4+bkjMx}r6%D2כK5 GeoZP iE\q AZ-O#3tw=!W{h%OKr)~8Dg7vq9tX'JDq7/V P ѤDcWJ*MX= ~n _e襘Xj UlV żvTdIG#"l$-X6r.'ey<MAf?<G'[5C dq<]_" CpxY sf;jbb(;L^,2=!X xp ( b-] ? kԷ" ƾYf˶Uu+q{} {t`m.n8 |?^ .`g<!wc0ADYm(؞2686Lp'd?YHqϗan/()7Z u KrO ( hfW ZGZ_H'Q D sHZ9?<S-Uv[欴Oi}+%_؛WjF$nbظW'>:2% /z%`($zzw W~W`w+1L&& EDD;ÇRKTAޏ(I9BkBt &vf91ijs8 ,BǃL֒HlNBB*VRp4CROr3fB.KV ~e0r ؟ܷ:6 %B u+E;HNn=>$ej6KfYֶ) tgͯ@<A5<Bc`JD^bՖ6"5AXa]X -:k= 4+ Pޚ-iPNU !>&"|Us4Ka f tT ~9һG*yM)8#.e Bz Qs|!]$!N=/(nǞ4T1unHs AF!צb{@ɨT5jU"E`pmm+]uҿD` |tQMmvfbk O\sQB<DP|*U'Rdm0s(Į \ >;&߇Wʱu 1rnZMKxYs__zO[b 2LߧO/0G:k.?gI];ɭ sq{x[I^dԀ[fꁏ{^hu D (hl@sn\T1B걱KA uof/ DW\C6> >e!A!UČD-gh8 3xpR\q_qr-L?XbK8ڔDǓi|8Z<p;U&A+kﻉ3:(b85 O58:bbCVZF }T!KW9r0@_N7 z Og 8*sZQzV0Sda˜Bozqzpz/.y]%=W 0f& _e=Cq1(`Y(3Ր6V=&ì8_>r#Hp 9&4CG k : 0/ )&af CX܄ {z]y]!m]4FV+>@d,}8^ŧqss$`n9sl"`V4. fڒ1O~x)ojCJS'?K :RJS'0LS' UW>xoFX̯<Z\ LVyē O}&k4d5v"[ :۬ɸm#}Cްf2.Q©U$QoD rwDJ? F ]WeنGgzaϱ]n!^ clEN#Fk <n:{GjR @YD< ͞S(-y? NG Fх#NJDfɝMSg+(;H~ ,UMb4abk/>#Acd9D9~jxܚN01WrD@<o;=i&n=#%rg㎏,(nѩks?jQ9d.L5LHJvM/|y©`i fYwiTQ W^9Wv\" '46@ 弘'^6"]C5u \*/ƾFsj$ s oF Ys7`/h]5ϔeIV52J<ቃY0`h랙v^o9oZHy87gV!жI*k *39 i+_sڮde? WQ9$a۪S i PyŁQQQ(SѲ;LdTI' -U|v .`{x6f['we['M@?-Z-KPK W [quzHߟZF؍nOC(_,[n*éTgr:AR^ ɩvTQyYcRHyH3|F̛7goDCc7Sf?_1ڭ/Ksʖ!EE9 S#M~rMf,U= Lv[Գ<~TAL:e,B9`zIla?baWR@DY)®R <E k?zT=^̰ `0XgpQd8!0=^ 9ZsÀJK7Ղ47Yȓ ]8Zȓ/u< [ȓ]ȓ01} olƺœ-el\qE!5;Y-3]x}bt^Νd/96e#5t& NL(=Q+M}_MP ?Y\,Fa$CKNuL76ÉQؘEl^$/>4f60ͦ2*w|XAxZGsIvP"G Y ,` E[L]Z""ƪʺJYtXveOZXͥxQavvbR=Ó[[ќLf z1>t!it#LxHm*G'<b pYv Cl_L$AVV#mIUS:V2}iŁSf@_רԺ<ltd`brdG|\t9}L#g;?A} fpp%xd) c(j zaKT=>< +.I/0'7|yҍ,3N+J&[nR"( d*(y Jt2auHewW 3$-z{r٨E|CR- Seߧ87-SLhoVV]K}w}2Am>yNb4@&raN~ Ԫ DNCE<F4gi`K ͑{I 4'gUw7np@"%?j#;ywԌV-S3HIZN40><J jCcdz =eJ[JwF 40QUzX0F%Br X,g; Pr}rsFolMւNظЊ;gbB-8edrX`A~= pvH C @s2aHZ][ˌ>iE# .b ~Ҍ2ww(QTC.oik\@訍1cl]C n<iP騍1먍1ƏT# hQ3L\}tt"?ibA<f ~$%5͢6}-m'!q ?$-pvStsQ@; FqĀπu gubL%ȵr~ș@|7>N N@h5 rނ:{ gnL"fjhdYu̓/tFʑNըUW.rPFl+;[U H1"ag5" #ʬOkLP1ܵ6p G<`"<;?n&uut[AiDh}s ob۪jPC^fm{[c'fW >#@c.CgO SH8((D@ ChZ((NLpoG"/xDvς@ ]D}b%;4AN!#E d6E΅Nūbk NڈSΈN<N ^NoeNA܊N8+",DāHቑqM"aƊK y8k')?B<'Y{0DMMfĆ>͆t$z ](ܻ _nD$wMF␅3h>lBK%EQn!~Ud {lu'<3Nӥ)I NS HnNɃɪN+mNnI3<T|@0 "+:Mk1~@*k1l1v謣+Ƀr?#2SćsKFfN"O] 4P+(z:j6Eo9+e4ń0Rz#{)1{Mr sOC5'~m<48s,*&)( Q2ؼ4so9[=K 2=-1Cf^9<ٮ$wU//Ag 'QhdHj/(; Ž8kf}Ŧg-4gg\|u~I9-3a~! dNwj`=1ɛpQV-/7 if>G / U c'jtT 3Y i7dA`{$ lX=! 7zaIJ'{jf !KIɉ fPK"-wrhNwjuoi{6;]c[Q̴+y&Rj 1 _N h z*GdWV qCi }E. ] E`4 H7-H|]hR]jcv(O &$f%0 -}pA:HX7|&np~ )}H}UXx/ tܔwF7N;op[ FdLA.Qk2~$R-? i`Oe&{6n}A3{c2(6e{AǨ/G~daS=x IX 5Mǂ:OsV9PgxИ)&2x͇ȻxxCڼx,tgE c5v' <~D%(w@[@>s:_#jJtcӜ&/ nLmpZ:s[u/`qc\)8H M!T7t#)J$K&C28mG ϟ8ɞdD($-KPd{ܩE=fx GQXX?` R ['o' y=(1z!̵"t@(uU1C}:K]'`)aTQYXcrdoގ[# -m(ـj imQ\oRb9{fՆ+JLo*i lcC~pH_1+O$Ę k ໕ g ũ]Z=Zwf| }A'AY`u o$Ȳ`Ӱ͊'jކ c <^ Ճ=t8M FRFQ =֩::Z:&r *?g_j8vN̍^Nkaޓ+q-!n s d&zZQ2,¿ &n~ې9 ol¥!EPb>"?7NfjB zX" QZ" #q R j,L#$\4jCa&Ft6@dd6~{( NlC'~pƽj I&o4Ё;iW#;</0؎~DڗNFƲU,G JE YsFtwW E dr=(ٻuLx% -8Wr5> bԜJUYJJ$\ O<1(l`z,8 ܍=h\[ń:$jd ! ]ܻ8sm*O]f p ?7ky`dak6V ̙He[wUîd: d340p釛{q9ո萁IV56iʀ ;k i5C yP4yaZ{e ;^?y9eT0USR1%sJsOaR%)1@{4CZ}( ds^2@@z7R 5K=pr) rB/Jj '[9 d&VT%&]*N8 tFDeİ긟js/ Q}Ԓp ۧ=eφ| jV8΅/;պJiuT\ƀ0őFnT+l%Õ<8^T""VK#/|ms i $<* c`IB(3IAbv raZv e &(\'O^Oo+;^su|pp -ރUQ-& ,29me@ u EF96sʋص ۦXr)ژOpAރUc;xk.j ;mI|jfS< =5 hЂ8gu=\鹑\<>:DRPEe^o( 20 ά5ׂS)<j>Gp ,%f|Rm*Ϲ VVxDYKeۇ5«-( \yIx\[/G}vl ߃<pscguq$uWSroCN;O)B/[<038H#2hYٻ0s1 06 NT1<O' eyOFQdP O' O'<n?~!{ .*kDm"x%͙''0=VM1_ne!G ɑ!u7HV}xh F< O_ =@]`s.<"CRBEb wL =2 zuȺB$*.hΟ(rCHŌBy RG(saa'?o< TW4u=G#sa{ؽ|t'5vެ ڄ^ne^ +p04[8"/5rF~+^[gg3}ΖHI l)'W ; (Agء EPȗA/4&bc- +!N6j=lz b1Etѳ6[|¹M7 #3r쓥kc$ygRSQg"HEd> ="1GBvF\3HLlB- . o'k,@K_>Cp~84Ns e[q, (ݲSQ9["L!s&Ra؟M&`nROTlӈQٓmơXNN%Fo BZt_3H)yijrG aY).pe7M[s;ɈC4lX 2:ȝCQq?6 ᴻ&p/rRd4R5`>o߿XeJF̂ .VL "+ԱѾGN~"[J[InW'pW''erSPW'LiP oR >(+:F aL-dH@TU!EĮ 7gJ;Eh.ajN?(!9+s{#+k+p$Bڧ]gC!?EeÃ^8Y?Ko=< }oLPt( MX͙i$;Hw)!I)y SbTLbqGqGtXVo0$G&?9/(k""/8uҰscI+:.'៑]Ɏ5T[[=oߥ:UW [%t.ϼ[GdD]ۓ~т·B*;`t xΜVk63E w פej~rh8s pFzCށ.ZKa_Fr W:jrs5 dslP k8q #xo""*\(iJm5UX˪qy;59+KY4 eNz5D( 0Wpo9=kYѽk r7a[f 3x!2[`iI؍.̷"дxV3:Ι*<ެا͋ӍQDA"}o@sF]yϨ?]Eoʸ\Ovi]0C۠Q.7| J`YN/3BlyeSπv %@tO~XI)y<v\S{>M5tqvf)5W`>-R]Q^قy {KH[n0swASLB ^24VUlC#tF_T~%+s-Lw/ns^+".'=u;֧&ZnzTχB`F `6xH閘,"D0 tVaڼ#F5WEmpxx y;7 GE o;4 \'RaYYt;z 9 ԴL*f,R 1{6bT Ըȱ3եAm]diA{ȯ5 m^P0 j d`_*\ǘU / cӧ^9!`#TɕYZ 0-NpK uC6eۗ\9M?溜*)LgrW 偅|eFM;+ѥxfB~]["G\4_j/+ξ3=u} ,GVF 4v oTZD(ThID J, %|O*|nсR *!5l_i Np,g:zR>& 'f7" Ta֚-pv }W|1Wv3Ssa̶Ţ79 (yHEK.vۦp e)OڟO=I<y*r}c̅~!aV! =d+s8 I'ߣ-O,[Gӷ ֪3j xSѶݶGΕwu )"r8p+?'üA0s0^R0Մ6> P?lG"ndCcIJ:ᘿݴĿEd2??#"x0#<Ec!pƛֺ۵ I9 8gl@ Ktcqq!ᲞNW'LF*OF_-Yѡua~UtX22*_+-Sr@1h=ܳ̽ N"m oÐqcfMl+rq@Nw(@'kCFǻu5=\=;xIyn`*5?%P7.ߢuaլX<dܤ.U 24 y t>m~ą2wP?e6GL 3Vs ^-d}*xv1LW > JQrlWd.)g"M!ửD!j ~'QɄ {&~4mA*J DCKDPӺ~(K\{+]ZA[w(1GJ<zmp5Y}V>{ b2;C t?h}πAã> ؇ ̕|!v(1lg +1+1$!xǝ=[w\~U<{M d8~ XOP.6qz3#NڍRLec @ m , 1 E 44 G0 q : - " ? \* K * @ 6 l b 0 T } y f Z + l |0 u / * - =b uy 'q g 6 F " kL p _ { ɀ 4 g f | \ W 4y 91 _/ s ql y 0" [ G ; N+ u u Z g n = - 3 WB > Z -3 $ G/ * p 1 ` U 56 2 .7 '[ 3 9V W y) o d I ګ t , Y@ { i - 4- M b2 ` K5 3a l* r i a I { !/ W: 1 I M i 6 f 2 ) R R 1 z 4b . u e a ] / ! i G d f Vr _q >( L 4 3 # } # B 0 - d w |x R 6 T/ L [c E~ \ g g 2 N v0 n - J1 0 # N6 J 7 < ?0 c & n/ U4 ' X - / o ߮ _ L g% [ M R\ y ) N 1 n% 6 a 9 3 z 3 <2 4 + o $9 6 x2 =w ; a H J 9 \- w ٬ 7 H p ٍ 0 + " 4 < 0 Y a Q , K " % v h - / J m P | !& @ h i ] g c I* %7 '5 u Q* O Qj t H 7k [ v (i E\ y 3 v t '4 + j I3 , N @ , < & !\ W6 n ^ 0 Y ] ֵ h U : Ѥ | l0 y @ Z . B ] u k & C ] _ Ԃ c : | i_ gc 7i ~ D 1 p0 8 ? - 3 " i- - Y . Z K # p5 Z Z ] : G^ \ 2 ) ~ ( g ~ % V Y 0 ș v4 lN @ ` 0 ; , 3 F @ @ ;y p vq : ]B l f @ + ! " A U / ^ ! P l @* 1 y @* f = Ͳ g ` @ A p @- Q 4" I Pe Y T @ K + A { z H# P T7 `! . 0 0 q P 0 d 8 w P5 n " 0 s .. Н = # . 8 _ h 8 0 p - h ~ J l " 2 X1 _ q N 4 4T @ p 0H ` E 7@ p 2 Q T F Xw A R a 8 P eT 8" : @ >< 0 P" : . @ }D в G p F t * T h a ` z L ` @ k ] } p ` +# o +L D V 7 @ = ~ 3 s% Q ) T 0 ` 2 c 9 Y [ ; S n 0 T { w ` m G Q3 X @ & RJ @ } > O vG p O ڎ @ { ! Q O # [ 5 D# b 5 % PZ g ; o m9 p L Ŏ $_ C ` 3 P r k o G p + t ؍ H c Y $ = s p p 5 8 l f 7 0P x v Y #_ @ ` * e 0 m r o 5 0 I , 7 U x 7 @| [ i LP 0 3 @ 2 = k 0 R` N 3 b | s V ` '` R v * H ` h * 1 ! t v r \ o `* & p : = =" b F < pg! > : @ @O Ud 1 { 8 @ ^ Q L 1 o ) @ d :d . z ` p 31 R t P lv " " y p @ 7 " 6 c d M 0W% 'z E + p @ h < 0 }b p T * c R * n p = U * 2 ; | 6 + P" > p * '~ u ` f ཌྷ p * `g J /W н i T * K> 7 ' `A < ` # p \ V " P 5 F V 7 & 3 % Q * o ,m h A k s ɻ u Ys P } a e3 " & rB @ێ @ d ` U O ` * } B 8 l) 1 0 dY U - + o d + B ] p , 3 n j U Q . ` @ 0 _o Pk V X F u n Ԑ < 0 " 4 @x" y T 9 j , f \ [ )p l , 3 ` ` М P `W P ! K ` a x $ ? @ 9 U ) O P V * G # % # s & 3 к 2 P Z P 6 Ë 6 W ` ` ; x ~ PS# S .I ~ ` m [ ? $ O Ї ! o ` 8 >y 2 ] P ( w : 3 Q @ e L ~ 0 3 ` # s rh ]" x `# ޮ U h 9 \ ' ޒ \ p! f ! ` a ! ! ^ + l @ BK 0i X 0 & m : U ([ k bV `Ȏ R @ X = @ Z ) 3 e G An h e g @|% O 9 K 06 ` H i p . & p- k # B6 & r A ( þ F Da R q# ( m ` H 3 Й 8 #0 7 X . : \ л ! &\ Y ) g C `# t ( u !V 9 * #c - J ] % j I + = l 8 6 3 @ " k 0 3 ^ EO D n Z b! ST w t ( ` f w s > ? H & b < ~ P , p | 5q 6 2 p 8 N ) c D9 0 X s > ` @ x P 4 ` o k @ T N ! w B % p @ Z @ w ? t V > S 0 ຍ r @ 9 ˘ `" ] " p # 1 @ a ! I ݎ @ Y f 5 I 5 [m @ ` n$ x1 / d 4 ך @= Q W Џ R B ) X ! Z %n 0 1- @i M Y X 09 @ L @ ; Ɇ b % B y} 3 } M ` `c% O % l ` ` > # N/ Q ` G ; o O c `? u :B о * \ 5 B3 & s ` { G& + g pO v `, ` I @ / ] `[ h S ߎ @ f (d [ W i : L v Pl 4 x rL 7 @ } 0f &o EQ @ X ~% = ৎ e o a A } F 7 P M & 1 &\ & c7 KN ! ; I @ N . _ v 5 % 1 7u 3 9 @| ( pc 8 " a PE Z :" c q S T P+ g @ '% G 5 ]( W X M $ C L kb P K ~ < ˹ y ^ ` / R p b @ E o < \ \ d * q * S " \ t { yp ~ < {A { B zR ! < P } Y : n 6 `/ i [ ! \ # R fU n U 6" Z ed B 8 3 ` Y R R ] p# pq" s V 7 = # Ж Y X T Q e 0 P # t% I" & R 0k c 5 V @ w@ L C y 2 o y ` B 6 p Q Z 6 t / Q E Ъ V 6: F% L { F _ S b . `K _ Y h | c x6 ` @ M s $D `ʎ 0" b [ " " _ U # : IF p wK D O | ( a[ l ( s 8 " # 0E 6 : G . r 0 ' >! i z * @0 I _ @ l f i ZO Q K P p ! @ R g N t p I ߑ `* > pK Q j @ y } s O @ 8 #. % / ' ) ҆ } B A x < @ 6 0 I % P )U > Q vs 5 sJ M ! H ^ ` >m Y 8 l ! ; |e ~ `% _ \ M pa H ; " r ` l 8 pH" W> @Ŏ { V ێ @ Kv # a ۀ @! 5 uw F ; t | q r " HI % ` be v ` 0 S s Q v t f 7 @ H C `^ 8 @ j c " e _ j ! 5 7 @# D8 @ x P ^ J # f B # ^ _ ` 5 Ot `E } p" s S Ϝ 6 M a> { o W ? F q 5 0 4 ؎ v A 9 T @ X _? p ) z f p ˒ D 8 0k! U ` D ȯ ` @ S 9 o E; `ˎ L H 0c < / L P } g P Y " < c# P л j / T ^ 5 9 6 ` 8 W ! 5 _f = 9 j # @ d/ 0 @ 0 ( z >+ 3 1 _ m I : @ ' s P!# 0 { 9 ` 0# \ P % 9 T+ ]F 2c P g k @ 6 6 ގ @ Ǎ a < p b - p t Y% q d w P @ 2 *a P 0M < m8 ! H q 7 $ Ö P& 3 ` h ? ~ ~ 7 r |! Y R 0E Z ! $ u x 4 % % a { :" w/ ` @" A % E @ n ' ( @ 3 r Q T p 6 G 0 6 : r Q g ƥ E % + g ) N 8 w I R Î 8 k ) Q 0: X G * h Y ) ) = = Ɏ Q `j P 6" '3 ` P! $ * P) I n F g ^ \A )@ 0;" U W ; " % ^- Z !" q 3 9S s W & 6 `" P Ps x F ` 7 { 9 p% p 2 x D P > p% t P p * u ` J ! " 4 3 ` w # P 8 # B W j 8 % R )^ D 4 @: % d ܥ @* T c D M @* ̓ B L 5 @* ay @ l ` " z Pp k * } * U =" q m" K - 0 H Zv d D j `! P _ 8 @ F @z " y% 6 m P F | R} ] q PD m ) @ o ` p Q [ n д ? W 0# b f d gU ; . K P<" g { " p f E ;" vN @ 8s f Q A `! 8 M O ' ` c `H q ` P i ! 99 ; 8 K `I 5 P h d 5 S @H < ; \ k r Z l P 6 ` ! 2 ? Î @ b Z V * N n `4 O Hc < 9 ` L ( V 8 / 6# Y P) 3? 0G% * t O i O & 3 ` 3 _ C$ [ ` h "e f s P I ; T % I9 `z r 1C c H? H e `r E V @ =5 i ̓ @ Q E2 @ n ! 6 d 7 m ݍ @ = y p ; 6 Q 5* b r ? d " : L} @V n N p H 3 [ R W G a 0$ t % i } p K @ 6 ` w @ [ F \ ? B u s ` @ T# ` 0 ` 8 P 1 Ew p a I 0 j k - * &1 o" Y ~i V 0k : B 6 5 Z Y V p ] ^ " | # ^ = W ` ! T ( T # d a J `( $ V_ W @ . >4 | 9 N j v" P" 5 u m > # g % W 0 S L ) 0 W PQ e 8 8 &A ] > W N pb I @ J @* 1 j @* H 2 h% $ k 3 i @ ; P j i \ %# b 3 z C TN P% B F t y$ ' H ^ S < D = I 2 9 0 b n # d 0 F7 0 3 Ƣ | y @ Q Ol ! T ! S = & q v! pz m H 0 c yo p m: 2 ! н 5 $ >G M) ; O { w w w 0 W; e @, I Ψ " d 9" ? p% G [ y ` @ <# i j n `` 8 R # } i * - / p S R " 5 @# ` X^ S X @ ` * ^ t H nX 6 y v v3 C 4Y U pp" s q 5 5 L & 4) l H p T @ 2 E P m > F 5 t p C " H (w 5 7I @ 7 `C m # N t E j 6 D ્ o @* q ! @* ! ` k i ~ @* S @ @ @* e [ m 6 y BW > ! < : g :k P P _ > z ( | ! v m d6 @ G s } ` S w p7# h s < ` . g4 Ü E 6 Z . P l Ч! %! v `@ 0 3 3 Z , p > @ # n\ / 8 0f# P& 3 < M XS p ' 9 > I 0 Ng $ O = @ p C ^ } ( R к 5 u* h p C M [ _ 0 ` n ] y \K @ J } Px ; 7 ` @ U % d K N s? 0% z o :h " [P M K P% Y 1 v H " yU 7t R 4 < J s I q , eT 0 p _ ' G z ` U Y | p P X Z # " [ R ` 7 h` @R * %G 0 b d 3 h O K 0 j @ S 0C <% S " 7 ` m _% ` G W @ 0 K } L @ C T v y f =# T / n @M B ! 4 S + E @ < # @ ԍ XZ & L H E @ q& hQ hp ` | Pu! i @ b U ? o$ b { Ѕ < 7 ? 6 x; U y c 0 v : $ R j ? o m Z `# X t Z E e = Z 7 O HW % t C 4 ` 7 ] H[ * 5 # ; hM ( j F :! ` 8 s i ; ` @ <_ ` @ Vn K 0 [ C p f R K g 0 @A p] V f K \ Ky w &b 0 ~ s D D fJ p < 7 `" d @r R @ 0 P L % X T p& v @! _ x Z : ] @k ` k" u ' . 7 b : , K x Pc C ]a ( & & 1 !> @ގ @ ! ! @= թ L : UV 8 &% W P ,& = ^ ` I ^ Z @ P# c \ / F I 'Z ` pW < ` 9 T @h" j = 0 6 # ;, s 3 l { X! 2o \ < 0 , [ G 9 } i \ T + @ @ = 6 D Ȏ @ $X p N% X G. 1 B C F , Y K 4 @ J > K 10 2 z q 3 ! { ;} @G" ' o Р" ? % ؞ Y 4 U a a z l _ 4 \ ] | @ @+ }C ɛ ` G > P @+ @ + H 0 Z # vg C @ J: p m YQ ^ 8 hd . ^) u G nH @ S 0 P " k S ~ @ $c i Q @ k~ ! pn% n + T C ( s ` ` @ w @" 5 L Z ( R I @ S 3 0 8 " 7 c / '! 0$ c \9 0 o 6 % % p% & 1 @ 5 aP T d" : + . Ї & 6 " . @i ? i D k ] N L ^h Q K i @ ` ( i \ T | 5 n )u w" w p = ƣ ^ 8 } V M 3 ?^ % r J p }{ b @! 5 1 P " +z 9 U :> m W S Ȑ Y ! > D @ A 3 P ^ ~ - n V ` 4 @ & 1 G @ ` F < * S W H @ O P 'M # Y ? Y B % `! 2 M p h :- ^ _ Q k ( ` G 1 ^: ?" k t V ` 3 = { b J P ~ 0 ) * e 0 + u 5 02 m| `* b# X [ @* o= K )/ @ - * E ! o `* Ğ ) 5 y * ߅ 0 @* (t " { ) I * ! `* + J Wu E 6 < pa 5 ! [ . ) < Z P * ># 1 .g `l b} N ݎ @ ] < 1 = M `\ S b - pu !< l ] 6 0 c j n 8 `" : < ` @ Y + ˎ K J % Ȏ q C = P + dz > ~ 0 ( L . * T 0" ` * F 5 * $ j * 3 pp X y * ,f o * S P E q (R ! @ 8 ˟ ! ` ( @* m x% 8 $ +O ) @* l @* ֧ ( 5 C J P j[ > h 6 g *2 6 8F | 0! ¤ P ^ ` ' _ q L 2 s" Y } R HJ `^ & % % I d ~ ~\ = x e z[ ( T b! " $ p pY V k 5 j U D i ~F 0 Ю M % , P k ! d d yQ 3_ Z 4 Р }t C B @Ǝ C " N ` | > Ke 4 * h' ۥ E i x w % I p ` ? `L # Q3 1 r @ " 5 0 g ^ @ ] n V $ ; 3 aM Hm C æ 7" c { e F K J 7 @ 0& S f ) & 4d o D 0 \ p m | g 7 _ U " L l 0 k @ o 0 | l S - @* % @ G l P! <K 8 , K N 7 u( ( > ( O ` ; P Д M Q 0[ 4 ^ vT > z P' q `a v 2 p * _U P n `! 2 G M 4 6 $K A Q в X )# A= p !S z ! T 0 *B ` # ! U j R k O ! Q$ - $ = n 5 ݸ @g G `t ( C C L & k ! 3 P i % e 0 p 8 y # JS [ po E @ q # O , FZ @U @ p V ! 9 @ D t 8 @S O & 3 N Z ? 9 a P? < F% g 0 @V S pS ] cR | p r & J I( ~ 8" v 9 \& 6 1 < ! c p >f Ѕ `O% 8 J י ` N 0 0 ?V `Ď X 0 N @ { I > F y v t x p ~ : ^ : ގ @ % r ` Զ @ z_ P ) P& 3 ~ ` Z = P _ b W > ϝ v 0 0# ގ pd 0 b 0 @ ໍ 0 y 0 - V " ' 7 ! i Ί `" 6 ߎ @ 6{ @B# @" : # `I 2 ҭ Q \ V C k> m z И * ! r 0 ; `Ɏ @ d g% F { ~ ! 5 J 0 @ XO # J X # 0$ oi P x 9 ) h W T E p ) @ p ; ] i " : zf 0! l v ` m "A p a 0d" v U ! ` к x 8C 8 E H " : 0( } ̼ = T ; Y 0 8 4Q K v TC GE @ \ % i d F, 9 + 8 + J = 2 7 ! z l x l 5 / > K @ | E u L # P p0 h ˧ D X W ( 0% z p R Z g @+ > l P X pN [ @ , #Q q J ` @ " 6 ' [ ; [ ` r @ 8 0 < w 6 ) 0 0; p 5 4 P p ~ Ѻ u 5 Q E @ g Р + 1 9 m 0 a Q p ` p m ) ! H * U 0< W P { @ X pk ; % a > ` ! $ h b pr" C , @ `` H @ " k i _ [ e^ @ a5 p $ 1 P @ P! m p J a k M W - ` 2 " ) U @" 9 [ pK \ " Y / @ 8 `6 u =z * ! Q < * z 3 Z P V {" @3 } h D 5j e " M = 0 M g O n 2Z o I i г ] E % - >k 0 ! p ! Q Z / J [ K _ P s P M r u -K P < 6 P y E" 葏 3 j } I T 5 o đ \ A 8 5 `m% 42 ` > 1 4 E ! ; . " z # . P c 0& w P e B п $ d gt < @ ! > 5 Я ^ - c @ I p " ~ "$ r p X P 0 c Ț ! 4 P# B @ U > 4 ~ < c Eh p CN t PV Ў 0 @ 7 ͗ # D Y Te @ @* DO j ) ) 6 z h $ = f F? H n { P p Y % F Y 0$ Y 0 Ц `x @ + oz ( E , B J U Q < $ pg " @ v } D $: 5J $ ?] P D % X8 @ h { > b / M C J @ Y H ~ qS n P" z pv" s j 5 n N : d M # 7 # $ % v t : > Z 9 L ` $N 5" p + s @" < ( 7 9 P p c 0 7 ` > 1, 6 1 HQ u @ ό u! 5 l | x N < u ;< 0 F * i 2 k A vT ގ @ B s ) b d] C @ 0 w D @ @ v 7 R # . " _ W k , ! 6 @ Q l b ,T Xj FH ǎ i 3 uE @ L z% Q# 6 @ k \> @ ' a 8 # R Z pX w ! @ g PT x % * K ? O T `, t 6 6 Z h x L \~ gU H % G- 0F 0N A ^ C 'h @ q 7 P u $ p$ = 1 M pT$ MM a ^ " 0 j 4 ` t E" )l ! ik 3 : 3 B I' } k @% 3 - $ 1 # }K Ɏ @ 0 < > I p t z r S j 3 a; @ 3A t ? 2 X ! n [ y o $ ? b ` ` I UK @ z ( @ RR | ( : < Q bi P& 6 E Ǝ @ < ! @ 4 f p% > FY H ` ~ 1 Y - R \ P h z C" V L ? l ػ ? ! 2 ` J C | @ `! 5 ܗ Q 4 + R # r N `u z + \ B * 6 @ q 8 > o + X B 0 fD _ Б Z ] # r :[ P & % Џ $ 1 4 ` > & S 2 B i @ 2 & K O / a pS Q o Q 2 D 0 R$ K P L 6 `; M R T ! XC # m @* nn 5 W fQ Ɏ @ [g p @* \ @* }P - 5 `F p aW Y PL N Fl Ї @ m x% b Є Z L p I | ; *O Ď 0A# ! l # : y 8 p @ ` ` B a 5 H ʎ @ , e ` @ GC Pg G .4 ^ X 9 4 P > o ; # J ^ < 5T 0 ɪ P X h n D _ R$ Ƶ k `S b \ ~ Q Jx @ 6 "U ` @ `0 }> @ E n 0\ l j F 1 { p ` ( cE @ : h ` h ^ b M 5 Xk P&# g : l # R p ! 3 n 2 < h" 9 F F @ Q] U < T P% F p a ` g! { | . 7 # O _ h " o Eo ` $P H% x! V ? i f ` /| 5 ܡ `c l @" * a p { ` @ @ 1 ; . ' c # Φ e Y 2 ` Q @ h " / 6 / l O R @ 7 $ = # I M _ q p n ` `" : ` q s ` @ " M S i v 6 !E 5 zQ v E@ P i ı @ ҄ $ % D ~ `" l ' | n H `e tS H T y x u ' : > < V 5 G W D| u І 7 A @ T 8 B " 6 @ 8 a\ ! I 6 m% ? o ` 6U P 0 sr v 3 c .% | 9 * ,7 7 ^ R ? @ I 0 & J @F & qs A P b 4 \ N O C 3 { . ' < O h t9 { @ & 3 S Ў V A o ` @ e h < G 4 Gq p< k Y ! T # - ` Je f H sX ` @ $ P R 0 P 6 k 6 < F `U - j" + " @l 9 +r @* ` @* @ pu" s 0 F C @* R `7 8 i & p 5 4 } z P! R " ж Z @ g I k 0w U % [ F B Q 8 X 6 P e 8 +v f 5 : " @ WJ Î u : ` 9 T 5 mW b Z o q" @ 0 ; ) xO O ) [ = @ ~ y p# q i u R D + h P o B : 9 n И 8 > @ ݁ 3 j R @ 0 ` 7 @ ; j ; j Q ( _ P O Ѝ% # c V ; N @ , m i 1 A wj " PT# 1 @+ t. k :\ $ 9 0 } # B E } n X u X c 蘏 ) 8Q ox P 5 . X ?R 9 T Mb 0 2 l I o> a Q o # q p 8 M ǎ @ З !$ +M h Ϸ i ? P = ^ 02 C 2 p `p$ b ) @ ! 8 Y ) : 0 A Ы o x 3 4 p& ) # X p t 3X ; c } ~ H! 6 8 y' 6 ` } h & j # V Rp @ 6 ( 0 ? X : x `! ` R | P% : ED V" p 9L @ @ z F SG Ѝ b Z g P @ o `" < Z ` 7 ; P j " 9 e 0 W 7 5 TX a J 0 h 7 J . p R j a 8 $ p н p `R J ; . 5 hs * C _ 8 K V |v & 3 @ O ?u ! Cj P Q I h" q ${ ` 2 Ӡ 0A $8 0 G `7" 8 r 1' I " a 3 * 7 ! E 0y # F F V @ l pd Z 0 @ Z x fS P P - p7 o [ p ` ` W /D w @ 0 n{ 2 l @ G k # i 0 | , ` q @ { D 4 @ ` P P R 0 I a @j" ~ x ` = + e j p 9 f $ f ! P" 2 Ŀ 0: Sz % U b 4 p$ I F b t" s tV F P# I Q c @ 0 a. 8 >r T \ `_ 8 # S F cO ` @ \x I [ Ed < Z y } % t S pj 6 d# F 2 & s 4 % JQ 9P 阏 `A t ! vW H m / H 5 j =; $ r xc u є , W w . p X 57 `^ L v x P k pc # { f# * P| -= @ L 0 d$ 1 0 x O f q Z, < W N x+ T g 0j zI p4" U i% [ P# . D f Z Y Q r C F \ : iI W 88 @ pu t P F 0 0 u " p 3 4 i @! % . 0% ~ + z H # ơ @ 8 0 0 { E P 7 6X ߎ @ ~ ]% 4 W g 0 Q # A Q # W ̕ ` $ } A < 4 & 6 H ! ? @ b G м 8 z% K ٤ " , P T t 7 ` * z 5 p 6 I L > Q 5 |% g + ! x 0S < Y P ] ]{ " @" 1 d PW# e< `ǎ P# M p l + l7 쎏 H { H ! d ˅ ~ # Z w o @ h, { -x P } \ n N A" ` @ r q @* k u h= 0 G * ) i ) ) % km ` 0 j o u" s ! -y k @ n< 0 y: @ @ p y d h l Ь V [ o K d H c k R 8 G pt @ ƴ F n `) D }] P @ * P k Y # F , rZ `W . m ͈ G V% { 0 g1 @ ` a@ ` @ S g% $ P " , y { I F" p F A IU @ߎ @ \ $ : P T p# 4$ . _ Р Ұ p\# Z M{ N & e 8 Z l c @- = T @> ` @ ; F Po X R% 4 W } e l D Pi q L[ ` $ 0 ್ V IT @# @ Pr 1} ` @ k @$ / (F n ' N :n ( C X e P p " p` 7 W o F | - 2 0 f * ] 4 p$ j B p f% J @ 5` O | T @ ) { ! ? F J T v ; 0 D * J Ď @ ^ ` O 0 $ " p + 8U / ~ , W ݯ H Cg H h n 0 j p ` a 0 `% / + _ / d C ` g \ S > p$ U p Y U @| m @} B HL $ : ` J 0 c ` . ) Vn g `^ q }n " & # $ P} V {8 Ď @ # d pS _ " < R k " O # bQ # o V eK ^ _ 8 ,+ ` { Z 7# > ) T< ` s f ! > u % r ͱ < N + L 6 # y 2 * ^ # . @ ' Mf , N ` c O U w ` @ o 0 * N c M ` @ " kC 4 O ( ! a Н Oi ` 8 b ; r : `w 5 < $ &# 0E = @ ˆ G C ێ @ 5 @G a +e ` UQ 5 > @ 8 Z V V ` n d 3 q 0 y 0 % P G R + F 5 ` # @* |= O ~ - d % t @* A @* ! 0t t 9 5 " 6 V ; 5 ܍ ] J o $ L FA ێ @ @ @ w [ % y C % `n __gmon_start__ _ITM_deregisterTMCloneTable _ITM_registerTMCloneTable __cxa_finalize __pr_debug sysfs__read_bool fdarray__poll strcpy scandir64 tracefs__configured sysfs__read_int fdarray__fprintf statfs64 alphasort64 getenv sysfs__write_int filename__read_str hugetlbfs__mountpoint debugfs__mountpoint __xpg_strerror_r fdarray__delete procfs__mountpoint get_tracing_file bpf_fs__mount procfs__read_str sysfs__read_ull fdarray__new get_events_file sysfs__mount tracing_path_mount filename__write_int __stack_chk_fail filename__read_int bpf_fs__configured calloc tracing_path__strerror_open_tp hugetlbfs__configured pthread_once tracefs__mountpoint sysfs__read_str strstr fdarray__init fdarray__grow __pr_warn strncmp sysfs__mountpoint strncpy tracing_events__scandir_alphasort debugfs__mount hugetlbfs__mount tracing_path_set debugfs__configured cgroupfs_find_mountpoint tracing_events__opendir strdup __pr_info put_tracing_file fclose filename__read_xll procfs__mount __assert_fail strcmp pthread_mutex_unlock tracefs__mount asprintf cpu__get_max_freq stderr fdarray__dup_entry_from filename__read_ull procfs__configured bpf_fs__mountpoint pthread_mutex_lock __errno_location put_events_file __isoc99_fscanf atoi fdarray__exit getline strlen toupper sysctl__read_int strchr libapi_set_print sysfs__read_xll str_error_r sysfs__configured fopen64 perf_cpu_map__new ioctl perf_cpu_map__is_any_cpu_or_is_empty perf_evlist__disable perf_evlist__remove perf_evsel__munmap libperf_init perf_evlist__close perf_thread_map__put perf_thread_map__new_array qsort perf_evlist__open perf_mmap__read_done perf_evsel__enable_thread perf_evlist__add perf_thread_map__set_pid malloc perf_thread_map__pid perf_cpu_map__read perf_cpu_map__has_any_cpu_or_is_empty perf_cpu_map__max perf_evsel__close perf_evsel__delete perf_cpu_map__new_any_cpu perf_evsel__enable perf_evsel__cpus perf_evsel__open perf_evlist__set_maps perf_thread_map__get perf_mmap__read_event perf_cpu_map__equal perf_cpu_map__is_empty perf_mmap__read_init perf_evsel__read perf_evlist__set_leader perf_evsel__attr perf_evlist__new perf_evsel__disable perf_evlist__enable perf_evlist__next perf_cpu_map__min perf_evsel__mmap_base fopen perf_evlist__filter_pollfd perf_thread_map__comm perf_evsel__mmap perf_cpu_map__merge perf_thread_map__new_dummy perf_evsel__threads perf_evlist__mmap perf_cpu_map__get perf_counts_values__scale perf_evlist__nr_groups perf_evsel__disable_cpu __ctype_b_loc pread perf_evlist__next_mmap perf_mmap__consume perf_cpu_map__new_online_cpus fwrite perf_evlist__delete perf_evlist__munmap perf_evlist__poll perf_cpu_map__nr perf_cpu_map__put perf_thread_map__nr perf_evsel__enable_cpu perf_evsel__close_cpu perf_cpu_map__has fcntl perf_evsel__new perf_cpu_map__intersect perf_cpu_map__cpu perf_cpu_map__has_any_cpu check_if_command_finished list_commands unsetenv waitpid stdout run_command strndup set_argv_exec_path sigchain_pop exec_cmd_init memmove finish_command setup_pager __fprintf_chk dup2 setup_path __isoc23_strtol isatty start_command error_buf set_option_flag subcmd_config __isoc23_strtoul load_command_list uniq select fflush __isoc23_strtoull putenv parse_opt_verbosity_cb __ctype_tolower_loc sigchain_push_common set_option_nobuild pager_init chdir __printf_chk usage_with_options strcasestr clean_cmdnames strlcpy parse_options readdir64 run_command_v_opt __asprintf_chk execl_cmd execv_cmd force_pager is_in_cmdlist __snprintf_chk __memcpy_chk system_path usage_with_options_msg getcwd extract_argv0_path get_argv_exec_path add_cmdname pager_in_use fputc parse_options_subcommand cmdname_compare __vsnprintf_chk pager_get_columns execvp closedir exclude_cmds __vasprintf_chk raise parse_options_usage kallsyms__is_function kallsyms2elf_type _ctype kallsyms__parse bpf_program__log_buf libbpf_num_possible_cpus clock_gettime bpf_linker__free btf__free epoll_create1 setrlimit64 bpf_program__attach_uprobe_multi bpf_prog_get_next_id bpf_object__pin btf__new bpf_xdp_attach bpf_object__attach_skeleton btf__load_from_kernel_by_id bpf_map_get_next_id elf_strptr bpf_map__set_autocreate bpf_object__destroy_skeleton bpf_program__attach_tracepoint ring_buffer__poll libbpf_register_prog_handler btf__new_empty bpf_map_lookup_batch bpf_obj_get_info_by_fd elf_newscn bpf_map__unpin bpf_program__set_type bpf_prog_attach_opts bpf_program__attach_perf_event bpf_map__autocreate bpf_program__flags btf__add_var bpf_link_get_fd_by_id_opts bpf_program__attach_freplace elf_getshdrnum geteuid bpf_program__set_autoload bpf_object__gen_loader btf__dedup bpf_link_create __xpg_basename btf__add_restrict bpf_object__open_file btf__add_const bpf_map__value_size bpf_program__attach_trace btf__new_empty_split bpf_program__attach_ksyscall bpf_map__max_entries elf_rawdata faccessat bpf_map__pin bpf_map_lookup_and_delete_batch bpf_object__find_map_by_name ring__consume btf__find_by_name_kind bpf_prog_get_fd_by_id ring_buffer__add btf__parse btf_dump__new bpf_program__attach_uprobe bpf_program__unload bpf_prog_get_fd_by_id_opts btf_ext__free bpf_object__set_kversion bsearch bpf_object__unpin_programs bpf_btf_load btf__add_str bpf_program__fd bpf_prog_linfo__lfind bpf_program__expected_attach_type getpagesize getpid btf__parse_raw gelf_getehdr fgets bpf_tc_hook_create bpf_map__autoattach bpf_map__set_key_size dirname user_ring_buffer__new bpf_object__find_program_by_name fcntl64 getrlimit64 elf_begin bpf_map__initial_value bpf_obj_pin btf__add_func_proto btf__raw_data bpf_program__autoload ring__consume_n bpf_map__key_size libbpf_bpf_map_type_str btf__distill_base bpf_obj_get perf_buffer__buffer_fd libbpf_set_print bpf_link__fd bpf_obj_pin_opts perf_buffer__new_raw bpf_map__is_internal feof bpf_object__close bpf_enable_stats bpf_map__delete_elem ring__avail_data_size bpf_link__update_program ring_buffer__consume bpf_map__name bpf_program__name bpf_tc_hook_destroy bpf_link__pin_path bpf_object__unpin_maps bpf_program__get_type btf_dump__dump_type btf__pointer_size bpf_map_get_fd_by_id_opts bpf_program__attach_usdt bpf_program__attach_trace_opts elf64_newehdr bpf_program__set_log_level btf__find_by_name bpf_map__is_pinned bpf_program__get_expected_attach_type bpf_map__set_inner_map_fd bpf_prog_attach bpf_link__detach btf__add_func_param gelf_getclass bpf_object__btf_fd send bpf_object__pin_maps bpf_program__attach_netns bpf_prog_linfo__new bpf_link_detach user_ring_buffer__reserve bpf_program__insns bpf_program__section_name bpf_map__set_map_flags bpf_xdp_query_id bpf_link__disconnect ring__map_fd bpf_map_freeze bpf_map__set_map_extra btf__get_raw_data uname gelf_getsym btf__parse_split strrchr elf_nextscn bpf_link_get_next_id btf__add_datasec perf_buffer__buffer_cnt perf_buffer__consume bpf_object__prev_program bpf_token_create bpf_program__set_expected_attach_type bpf_raw_tracepoint_open_opts user_ring_buffer__reserve_blocking btf__add_field libbpf_unregister_prog_handler bpf_map__set_numa_node bpf_map_get_next_key bpf_program__attach_cgroup bpf_map_create bpf_program__set_log_buf btf__resolve_type bpf_map__attach_struct_ops bpf_object__find_map_fd_by_name libbpf_set_memlock_rlim bpf_map_lookup_elem_flags strcat bpf_object__open bpf_prog_bind_map bpf_program__attach_iter btf__add_fwd bpf_object__open_skeleton btf_ext__get_raw_data bpf_object__name bpf_map_lookup_and_delete_elem setsockopt elf_getshdrstrndx fseek bpf_map__get_next_key user_ring_buffer__discard bpf_program__attach_lsm bpf_prog_get_info_by_fd btf__str_by_offset memchr elf_getscn bpf_map_lookup_and_delete_elem_flags bpf_map__inner_map bpf_map__reuse_fd bpf_map_delete_elem_flags bpf_map__get_pin_path libbpf_attach_type_by_name gelf_getverdef libbpf_probe_bpf_helper bpf_object__kversion bpf_program__set_autoattach bpf_program__unpin perf_buffer__free bpf_program__set_flags libbpf_bpf_attach_type_str bpf_link__unpin bpf_program__attach_xdp bpf_xdp_query bpf_link_get_info_by_fd bpf_map__update_elem bpf_raw_tracepoint_open perf_buffer__consume_buffer libbpf_bpf_link_type_str bpf_linker__new btf_ext__raw_data bpf_prog_query bpf_object__next_map elf_getdata strcasecmp gelf_getversym bpf_program__attach_kprobe_opts btf__add_array btf__fd btf__type_by_id btf__add_volatile bpf_map__lookup_elem bpf_prog_detach2 libbpf_minor_version libbpf_major_version memcmp libbpf_find_vmlinux_btf_id bpf_map__fd btf__add_enum64_value elf_version libbpf_get_error gzopen64 elf_newdata bpf_object__detach_skeleton bpf_object__load btf_dump__dump_type_data bpf_link__pin bpf_program__attach_netkit fread libbpf_prog_type_by_name bpf_program__attach_perf_event_opts bpf_program__insn_cnt libbpf_probe_bpf_map_type btf__add_enum64 btf__add_decl_tag bpf_map__numa_node libbpf_probe_bpf_prog_type bpf_map_update_elem btf__set_pointer_size btf__add_btf gzclose btf__parse_elf ftell bpf_program__attach_uprobe_opts btf__load_module_btf bpf_object__btf btf_dump__emit_type_decl bpf_map_get_info_by_fd user_ring_buffer__free bpf_map_delete_batch bpf_object__prev_map gelf_getnote elf_getphdrnum ring__producer_pos bpf_iter_create bpf_program__attach_kprobe_multi_opts btf__new_split bpf_obj_get_opts btf__add_type bpf_object__open_subskeleton bpf_map__set_initial_value btf__base_btf btf__add_union btf__add_float bpf_map_update_batch elf_end ring__size btf__load_into_kernel ring__consumer_pos bpf_xdp_detach btf_dump__free bpf_object__unpin btf__parse_raw_split bpf_prog_linfo__lfind_addr_func bpf_program__set_insns bpf_btf_get_fd_by_id bpf_program__log_level gelf_getshdr bpf_map__ifindex bpf_task_fd_query btf__add_int gelf_getphdr btf__load_vmlinux_btf bpf_link_get_fd_by_id bpf_linker__finalize mmap64 elf64_getshdr bpf_prog_detach btf__find_str bpf_tc_query btf__type_cnt bpf_map__set_type bpf_object__open_mem bpf_map_delete_elem bpf_btf_get_fd_by_id_opts ring_buffer__consume_n elf_errmsg bpf_program__attach_kprobe bpf_prog_linfo__free btf__parse_elf_split libbpf_version_string bpf_link__destroy ring_buffer__ring bpf_map__btf_value_type_id elf64_getehdr bpf_program__attach_raw_tracepoint_opts btf__add_enum_value btf__set_fd bpf_link__update_map bpf_map__set_autoattach bpf_program__set_attach_target bpf_program__pin btf__endianness bpf_program__attach_netfilter btf__add_type_tag htons libbpf_strerror bpf_map__set_ifindex bpf_map__map_flags bpf_map__lookup_and_delete_elem bpf_object__pin_programs btf__align_of elf_ndxscn bpf_map_lookup_elem bpf_map__set_value_size bpf_link_update bpf_map__set_pin_path bpf_map__pin_path bpf_program__attach_raw_tracepoint btf__relocate perf_buffer__buffer libbpf_bpf_prog_type_str btf__resolve_size libbpf_set_strict_mode bpf_map__set_max_entries btf__add_typedef bpf_tc_attach btf__add_ptr gzgets bpf_linker__add_file btf__set_endianness btf__name_by_offset bpf_object__destroy_subskeleton bpf_map_get_fd_by_id bpf_map__type gelf_getverdaux btf__add_enum bpf_prog_test_run_opts bpf_program__attach lseek64 elf_memory __isoc99_sscanf elf_kind bpf_prog_load libbpf_find_kernel_btf perf_buffer__poll bpf_object__next_program bpf_map__btf_key_type_id bpf_map__map_extra bpf_tc_detach recvmsg bpf_link__open perf_buffer__epoll_fd bpf_program__type btf__add_struct mkdir bpf_program__attach_tracepoint_opts bpf_program__attach_tcx ring_buffer__epoll_fd bpf_program__autoattach btf_ext__new bpf_btf_get_info_by_fd user_ring_buffer__submit elf_update perf_buffer__new btf__add_datasec_var_info bpf_prog_detach_opts bpf_btf_get_next_id btf__add_func bpf_object__load_skeleton fmemopen bpf_prog_query_opts btf__load_from_kernel_by_id_split bpf_program__attach_sockmap getsockname bpf_program__set_ifindex putchar strbuf_release pthread_barrier_destroy p0 warnx bench_format perf_session__delete __strcpy_chk random perf_pmus__scan_core bench_kallsyms_parse pthread_attr_destroy numa_node_to_cpus pthread_create quiet numa_bitmask_setbit set_mempolicy pthread_attr_init cgroup__put pthread_exit bench_numa parse_events_error__init bench_futex_wake_parallel bench_uprobe_empty bench_synthesize _find_first_bit bench_futex_lock_pi numa_nodes_ptr bench_futex_wake usleep strbuf_init memcpy_orig bench__end update_stats prctl verbose perf_pmus__destroy setvbuf perf_event__synthesize_sample perror bench_epoll_wait errx cmd_bench openat64 bench__start bench_mem_memcpy parse_events_error__print cpu__max_cpu perf_event__sample_event_size bench_evlist_open_close parse_events_error__exit nftw64 bench_sched_pipe strbuf_detach bench_syscall_getpgid numa_num_configured_cpus cgroup__new nanosleep wait4 numa_bitmask_free strtod bench_syscall_execve numa_allocate_nodemask kill madvise perf_atoll perf_set_singlethreaded bench_uprobe_trace_printk_ret numa_num_possible_cpus mutex_init_pshared numa_node_of_cpu numa_max_node bench__runtime memcpy_functions bench_syscall_fork pthread_attr_setstacksize getrusage bench_futex_requeue __sched_cpualloc strbuf_addch epoll_create _find_next_bit perf_pmus__find sigfillset cond_init_pshared avg_stats target__strerror perf_event_open_cloexec_flag numa_bitmask_clearall sigaction bench_repeat bench_uprobe_baseline bench_breakpoint_enable perf_header__write_pipe bench_syscall_basic gettimeofday __memset srand bench_mem_find_bit perf_pmu__num_events pthread_barrier_init MEMSET getppid evlist__create_maps bench_futex_hash is_cpu_online pthread_barrier_wait bench_uprobe_empty_ret sched_getcpu thread_params bench_breakpoint_thread setlocale target__validate sched_getaffinity thread_map__new_by_pid strsep bench_epoll_ctl perf_set_multithreaded sched_setaffinity bench_pmu_scan socketpair MEMCPY bench_sched_messaging rel_stddev_stats strbuf_add cmd_inject bench_mem_memset __sysconf symbol__init __sched_cpufree bench_inject_build_id __perf_session__new numa_allocate_cpumask enable_params numa_bitmask_isbitset evlist__config pthread_attr_setaffinity_np filename__read_build_id bench_uprobe_trace_printk bench_sched_seccomp_notify perf_pmus__scan __machine__synthesize_threads target__parse_uid pthread_attr_setdetachstate pthread_join memset_orig mlockall __memset_chk metricgroup__lookup __thread__set_comm rdtsc machine__findnew_thread maps__for_each_map mkstemp64 sqrt tests__switch_tracking tests__kmod_path__parse test_dwarf_unwind__compare print_hists_out __isoc23_sscanf aggr_cpu_id__cpu maps__machine perf_mem__snp_scnprintf dwarf_callchain_users popen tests__event_times suite__event_groups perf_event__synthesize_mmap_events parse_events_terms__init suite__pe_file_parsing suite__perf_hooks test_attr__open suite__code_reading perf_config tests__dwarf_unwind tests__bp_accounting mem_info__new tests__bp_modify perf_event__synthesize_event_update_scale evlist__alloc_aggr_stats strreplace_chars aggr_cpu_id__die find_sys_events_table machine__delete __strcat_chk sigemptyset tests__event_update suite__kmod_path__parse suite__sdt_event perf_event__synthesize_stat hist_iter_cumulative symbol__fprintf machine__process_mmap2_event machine__for_each_dso suite__backward_ring_buffer dump_trace pclose tests__jit_write_elf maps__find_symbol perf_hooks__recover aggr_cpu_id__socket expr__find_ids suite__attr suite__dwarf_unwind leaf machine__process_mmap_event tests__mmap_thread_lookup metricgroup__parse_groups_test test_dwarf_unwind__krava_3 suite__fdarray__filter thread_map__new_by_tid maps__refcnt rb_next suite__pmu_events suite__wp tests__pe_file_parsing maps__find_symbol_by_name workload__leafloop data1 tests__perf_evsel__roundtrip_name_test data2 metricgroup__rblist_exit strbuf_slopbuf tests__bitmap_print test__hybrid create_script_test_suites perf_read_tsc_conversion evsel__newtp_idx suite__openat_syscall_event sysctl_perf_event_max_stack mem2node__exit perf_mem__lvl_scnprintf rblist__init suite__thread_map __getdelim perf_hooks__invoke machine__process_event suite__bp_accounting evlist__new_default suite__perf_evsel__roundtrip_name_test suite__fdarray__add test_attr__init perf_event__process test__bp_modify tests__api_io workload__datasym suite__PERF_RECORD offsets parse_events_terms__exit readlink unwind__get_entries tests__thread_maps_share thread__find_map maps__equal suite__parse_events aggr_cpu_id__node tests__is_printable_array perf_pmus__find_by_type perf_pmu__fake evsel__output_resort suite__hybrid tests__synthesize_stat hists__filter_by_socket __evsel__hw_cache_type_op_res_name perf_hooks__set_hook hists__collapse_resort suite__bitmap_print pmu_events_table__find_event perf_pmus__add_test_pmu tests__amd_ibs_via_core_pmu is_pmu_core suite__sample_parsing callchain_register_param setup_fake_machine suite__synthesize_stat expr__ctx_new maps__nr_maps suite__hists_output creat64 tests__maps__merge_in evsel__name_is symbol__new evsel__name tests__event_groups suite__jit_write_elf suite__event_update evsel__field intlist__find dso_to_test suite__parse_metric callchain_param maps__insert test__dwarf_unwind tests__hists_cumulate perf_event__synthesize_cpu_map perf_event__synthesize_thread_map perf_event__synthesize_event_update_name test_dwarf_unwind__thread perf_time__parse_for_ranges evlist__set_tracking_event suite__event_times suite__intel_pt suite__thread_map_synthesize alarm evsel__set_sample_id tests__hists_output machine__create_kernel_maps suite__pfm evsel__open_per_cpu machine__resolve evlist__expand_cgroup find_core_events_table suite__dso_data parse_events__decode_legacy_cache suite__maps__merge_in hists__match perf_event__synthesize_event_update_cpus suite__unit_number__scnprint perf_regs_load evlist__strerror_open tests__python_use suite__symbols tests__synthesize_stat_config workload__brstack perf_event__fprintf suite__pmu dso__needs_decompress suite__perf_evsel__tp_sched_test cpu__setup_cpunode_map pmu_name_cmp tests__expand_cgroup_events thread_map__new_str callchain_param_default tests__syscall_openat_tp_fields __sw_hweight64 tests__mem machine__findnew_dso machines__exit evsel__open_per_thread tests__backward_ring_buffer tests__perf_hooks tests__time_utils java_demangle_sym intel_pt_upd_pkt_ctx expr__ctx_clear machine__load_kallsyms suite__keep_tracking tests__attr dso__data_close machine__fprintf dso__data_put_fd suite__dlfilter is_kernel_module evlist__start_workload suite__parse_no_sample_id_all symbol_conf tests__bp_signal_overflow aggr_cpu_id__core tests__mem2node thread_map__read_comms thread_map__fprintf evlist__add_sched_switch test_dwarf_unwind__krava_2 perf_pmus__num_core_pmus suite__sw_clock_freq perf_record_cpu_map_data__test_bit pmu_name_len_no_suffix evlist__new_dummy __perf_hook_desc_test bitmap_scnprintf suite__hists_cumulate evlist__can_select_event perf_session__write_header dso__new_map thread_map__remove perf_header__set_feat suite__openat_syscall_event_on_all_cpus test__intel_pt_pkt_decoder perf_pmu__have_event evsel__sw_names tests__thread_map_remove tests__util tests__fdarray__filter intel_pt_pkt_desc rb_erase __evsel__read_on_cpu addr_location__init dso__put tests__bp_signal pmu_events_table__for_each_event test_attr__ready ids__new parse_events_error__contains suite__sigtrap map__load suite__demangle_java evsel__free_counts tests__task_exit suite__util tests__unit_number__scnprint tests__x86_sample_parsing ocaml_demangle_sym file_available suite__amd_ibs_via_core_pmu evsel__find_pmu dso__fprintf lstat64 suite__bp_signal perf_env dso__data_read_offset suite__cpu_map hists__filter_by_symbol cpu__get_node mkdirat machines__find suite__mem2node cmd_test reset_fd_limit map__find_symbol_by_name thread_map__new hists__filter_by_thread tests__perf_evsel__tp_sched_test field_order cpu_map__snprint expr__ctx_free getsid evsel__hw_names scandirat64 suite__expr dsos__init walltime_nsecs_stats test_objdump_path test__intel_pt_hybrid_compat perf_event__synthesize_thread_map2 ptrace hists__add_entry suite__task_exit __test_function find_core_metrics_table evsel__has_leader suite__vmlinux_matches_kallsyms test__arch_unwind_sample tests__vmlinux_matches_kallsyms rb_first machine__for_each_kernel_map pmu_add_sys_aliases perf_event__synthesize_stat_config pmu_add_cpu_aliases_table hists__filter_by_dso parse_nsec_time tests__symbols thread_map__new_event perf_event__name print_hists_in perf_event__synthesize_attr ids__insert workload__sqrtloop tsc_to_perf_time pmu_for_each_sys_metric fstatat64 map__rip_2objdump evlist__parse_sample evlist__prepare_workload perf_pmu__find_event tests__sw_clock_freq perf_event__process_attr suite__thread_map_remove suite__perf_time_to_tsc suite__x86_sample_parsing test_generic_metric maps__find tests__demangle_java test__amd_ibs_via_core_pmu suite__synthesize_stat_round perf_pmu__has_format tests__hists_link mem_info__put evlist__to_front machine__init suite__syscall_openat_tp_fields perf_hooks__get_hook test_attr__enabled rlimit__bump_memlock suite__expand_cgroup_events test__x86_sample_parsing dso__decompress_kmodule_path perf_time__parse_str addr_location__exit hists__link perf_pmu__getcpuid workload__noploop tests__demangle_ocaml thread__comm_str perf_pmu__delete tests__dlfilter workload__thloop tests__fdarray__add thread__put evlist__event2evsel perf_event__read_stat_config evlist__alloc_stats __evsel__set_sample_bit dso__load evsel__new_idx ids__free mkdtemp suite__bp_signal_overflow unit_number__scnprintf maps__find_by_name hist_iter_normal suite__switch_tracking get_filter_desc evsel__parse_sample dso__new arch_tests suite__mmap_thread_lookup perf_pmus__supports_extended_type hex dso__data_get_fd maps__new dsos__exit perf_exe suite__session_topology evlist__id2evsel evsel__intval machine__exit setup_sorting suite__synthesize_stat_config machine__load_vmlinux_path tests__thread_map_synthesize maps__put machine__new_host suite__mem tests__code_reading hist_entry_iter__add tests__thread_map the_var __evsel__sample_size test_loop suite__time_utils expr__add_id_val tests__keep_tracking mem2node__init evsel__config mem2node__node evsel__is_cache_op_valid machine__remove_thread test_dwarf_unwind__krava_1 __ctype_toupper_loc expr__parse tests__parse_metric parse_events_terms tests__sample_parsing suite__is_printable_array suite__hists_filter suite__python_use perf_time__ranges_skip_sample hist_entry__delete ids__union perf_pmu__config_terms intel_pt_get_packet arch__compare_symbol_names machine__delete_threads fputs suite__bp_modify cpu_map__new_data suite__basic_mmap cpu__get_socket_id tests__sdt_event suite__demangle_ocaml machine__find_thread tests__hists_filter perf_pmus__find_core_pmu tests__synthesize_stat_round tests__sigtrap evlist__free_stats suite__thread_maps_share pmu_for_each_core_metric thread__get __evsel__reset_sample_bit perf_event__synthesize_event_update_unit perf_event__synthesize_stat_round machines__init intlist__new suite__api_io perf_pmu__match tests__session_topology suite__hists_link tests__parse_no_sample_id_all perf_event__synthesize_threads tests__expr ui_browser__write_nstring ui_browser__help_window perf_hpp_list__register_sort_field vscnprintf ui_browser__dialog_yesno attr_to_script ins__is_lock callchain_node__scnprintf_value res_sample_browse ui_browser__list_head_refresh perf_hpp_list__prepend_sort_field SLutf8_enable SLtt_set_cursor_visibility ui_browser__refresh perf_hpp__append_sort_keys perf_hpp__reset_width rb_last strim use_browser perf_gtk_handle ui_progress__finish hists__total_period ui_helpline__push perf_header__fprintf_info ui_helpline__printf callchain_list__sym_name ins__is_fused ui_progress__update SLang_getkey ui_browser__input_window SLkp_init SLsmg_write_string hist_entry__has_hierarchy_children SLkp_define_keysym script_browse map_symbol__tui_annotate ui__lock res_sample_init skip_spaces perf_hpp__set_elide annotation__lock SLsmg_write_char ui_browser__vprintf hist_entry__snprintf_alignment ui_helpline__last_msg SLsmg_draw_box ui_helpline__puts __ui_progress__init sort__mode SLsmg_gotorc open_memstream pstack__peek ui_browser__run perf_hpp__is_sort_entry rb_insert_color hist_browser__new perf_hpp_fmt__dup __rb_hierarchy_next ui_browser__show __ui__info_window SLtt_set_color SLang_init_tty perf_top__reset_sample_counters evsel__group_name ui_helpline__vpush ui_browser__gotorc_title ui_browser__argv_refresh rb_hierarchy_last disasm_line__is_valid_local_jump SLsmg_vprintf SLsmg_refresh sigaddset ui_browser__update_nr_entries annotate_opts symbol__hists ui_browser__set_color rb_prev SLang_TT_Read_FD exit_browser __hpp__slsmg_color_printf events_stats__fprintf pstack__new perf_tui_eops callchain_node__fprintf_value __map__is_kernel ui_browser__gotorc perf_hpp__cancel_cumulate hist_entry__sym_snprintf ui__popup_menu ui__exit hpp_dimension__add_output ui_helpline__vshow SLtt_Screen_Cols ui_browser__init backtrace annotation_line__write hist_browser__run SLang_reset_tty perf_hpp__reset_sort_width run_script pthread__unblock_sigwinch perf_env__lookup_objdump setup_browser annotation__toggle_full_addr evlist__toggle_enable map_symbol__annotation_dump ui__question_window dots ui_browser__reset_index perf_use_color_default SLsmg_set_char_set perf_hpp_list__column_register hists__sort_list_width backtrace_symbols_fd ui__init SLsmg_reinit_smg perf_hpp__set_user_width tui__header_window hist_browser__delete dso__insert_symbol psignal ui_browser__rb_tree_seek pstack__empty convert_unit timestamp__scnprintf_usec callchain_list_counts__printf_value ui_browser__warning __hist_entry__snprintf pthread_sigmask perf_hpp__setup_hists_formats ui_helpline__init tui_helpline_fns SLtt_get_terminfo callchain_node__make_parent_list ui__error hpp_color_scnprintf tui_progress__init ui_helpline__pop perf_guest symbol__calc_percent perf_hpp__init perf_config_colorbool annotation__unlock SLkp_getkey SLsmg_draw_vline ui_browser__list_head_seek hists__fprintf pstack__delete annotated_source__get_line ui_browser__mark_fused __vfprintf_chk SLsmg_write_nstring tcgetattr ui_browser__write_graph ui__warning map__find_symbol is_strict_order perf_config_u64 perf_hpp__defined_dynamic_entry pthread__block_sigwinch perf_hpp__setup_output_field hist_entry__tui_annotate perf_hpp__format SLsmg_draw_hline hist_browser__init ui_browser__handle_resize hpp__fmt ui_browser__refresh_dimensions ui__getch perf_hpp_list hists__reset_column_width __ui_browser__vline __ui_browser__line_arrow hists__fprintf_headers ui_progress__ops ui_browser__argv_seek annotated_source__purge symbol__strerror_disassemble ui__help_window tui_helpline__set block_info__total_cycles_percent perf_hpp__is_dynamic_entry timestamp__scnprintf_nsec ui_browser__is_current_entry SLsmg_fill_region SLsmg_set_color evlist__tui_browse_hists symbol__annotate_decay_histogram pstack__remove rb_hierarchy_prev ui_helpline__current input_name ins__is_jump percent_color_len_snprintf map__browse ui_browser__rb_tree_refresh __sprintf_chk annotation__update_column_widths hpp__fmt_acc perf_hpp__reset_output_field symbol__annotate2 graph_dotted_line ins__is_ret ui_browser__set_percent_color __hists__scnprintf_title stdio__config_color hist_browser__init_hpp perf_hpp_list__init evlist__set_selected ui__dialog_yesno pstack__push SLsmg_reset_smg hists__overhead_width block_hists_tui_browse SLsmg_write_wrapped_string SLsmg_init_smg SLtty_set_suspend_state ui_browser__printf find_scripts symbol__delete ui_helpline__fpush perf_error__register perf_error__unregister SLtt_get_screen_size SLtt_Screen_Rows __ui_browser__show_title tcsetattr ui_browser__hide hist_entry__annotate_data_tui is_perf_magic maps__fprintf SLang_ungetkey ui__refresh_dimensions arch__fix_tev_from_maps expr_set_out srcline_full_filename thread_stack__free auxtrace_queues__add_sample perf_event__synth_time_conv inat_group_table_26 dump_printf annotate_get_basic_blocks stpcpy perf_pmu_pop_buffer_state line_range__init __intel_pt_log_insn_no_data call_return_processor__free sort_mem_daddr_dso evlist__parse_sample_timestamp mem_info__get svg_time_grid get_arch_regnum die_get_type sysctl__nmi_watchdog_enabled perf_mem_events__record_args svg_fbox perf_pmu__mem_events_num_mem_pmus _Ux86_64_is_signal_frame rm_rf_perf_data perf_event__synthesize_cgroups parse_user_regs dso__data_status_seen die_get_linkage_name die_get_call_file ZSTD_createDStream inat_avx_table_4_1 evsel__set_filter read_size intel_pt_insn_type perf_mem_events evlist__toggle_bkw_mmap arch__intr_reg_mask arch__sample_reg_masks auxtrace_mmap__read_snapshot perf_header__clear_feat perf_read_values_display parse_events_get_lloc perf_pmu_get_extra machine__process_comm_event hybrid_topology__new perf_pmu__delete_buffer intlist__entry symsrc__init ordered_events__flush_time mem_bswap_32 expr__delete_buffer event_enable_timer__start __cxa_demangle shash parse_events_free symbol__validate_sym_arguments svg_blocked evsel__hw_cache_op parse_events_term__delete perf_session__peek_events inat_get_escape_attribute sort_parent sparc_triplets inat_group_table_21_3 pthread_cond_signal writev elf__needs_adjust_symbols parse_events_add_tool thread_stack__sample_late sysctl_perf_event_max_contexts_per_stack parse_events_get_text __rb_erase_color rm_rf cap_get_flag raw_field_value evlist__set_tp_filter_pid strtok_r dwarf_bitoffset expr_get_lineno itrace_do_parse_synth_opts parse_events_term__term is_perf_pid_map_name PyMem_RawFree __perf_reg_ip_arm metricgroup__has_metric tep_set_file_bigendian strbuf_addf strdup_esc parse_events_parse dso__loaded parse_events__set_default_name __perf_reg_name_arm64 arm_spe_decode evlist__valid_sample_id_all hisi_ptt_process_auxtrace_info inat_avx_table_6_1 parse_events_set_lineno fdopendir intel_pt__strerror srcline__tree_delete perf_data__update_dir expr_free auxtrace_record__find_snapshot parent_regex dso__set_short_name debug_peo_args probe_file__add_event symsrc__has_symtab callchain_branch_counts perf_event__fprintf_itrace_start modules__parse cpu_topology__core_wide sort_global_p_stage_cyc dso__find_symbol_by_name setup_intlist ungetc evlist__valid_read_format print_tool_events show_available_vars hists__output_resort thread__comm ins__scnprintf perf_env__arch_strerrno symbol__annotate_printf perf_session__fprintf hists__decay_entries evlist__parse_control intel_pt_get_insn cgrp_event_expanded debug_ordered_events inat_group_tables perf_color_default_config evlist__ctlfd_initialized sharded_mutex__delete perf_mem__lck_scnprintf perf_read_values_destroy online_topology dwarf_getsrclines perf_session__dsos_hit_all pthread_getspecific block_info__process_sym sort_srcline_from pthread_rwlock_rdlock kvm_events_tp __sw_hweight16 insn_get_sib perf_pmu__supports_legacy_cache die_get_scopes get_percent_color file__read_maps exit_event_end dso__symtab_origin cgroup__get insn_get_modrm evswitch__init strglobmatch dwarf_bitsize __perf_reg_sp_powerpc dwfl_module_getdwarf inat_get_opcode_attribute parse_events_set_out memrchr evlist__find_evsel perf_session__read_build_ids perf_header__has_feat arm64_unwind_libunwind_ops perf_quiet_option die_match_name ordered_events__first_time perf_probe_event_need_dwarf evlist__append_tp_filter_pid dso__first_symbol auxtrace_buffer__get_data_rw __perf_reg_sp_x86 perf_env__raw_arch nsinfo__need_setns has_kcore_dir evsel__is_aux_event perf_cap__capable __intel_pt_log_insn evlist__valid_sample_type perf_data__size vcpu_id_str dso__next_symbol_by_name inat_escape_table_3 hists__unlink db_export__comm perf_pmu__format_type auxtrace_cache__add pthread_rwlock_init init_probe_symbol_maps machine__findnew_guest_code sort_dso dwarf_attr perf_event__fprintf_cpu_map map__init svg_cpu_box auxtrace_cache__new cpu_map__fprintf perf_data__create_dir inat_group_table_24_1 perf_pmu__find_events_table disasm_line__new evlist__append_tp_filter parse_tag_value show_perf_probe_event percent_color_snprintf _Ux86_64_get_reg thread__find_symbol_fb format_field__intval perf_pmu_restart perf_pmu_get_leng perf_probe_event__copy intlist__delete arch__sym_update nsinfo__nstgid eval_flag kvm_reg_events_ops is_executable_file callchain_total_hits perf_env__kernel_is_64_bit evsel__read_counter compat_auxtrace_mmap__read_head arch_evsel__set_sample_weight perf_pmu_set_out set_buildid_dir perf_event_mlock_kb_in_pages inat_group_table_11 perf_stat__reset_shadow_stats arm_spe_decoder_new event_enable_timer__exit pthread_condattr_setpshared symbol__disassemble print_symbol_events perf_event__synthesize_id_sample sort_type branch_type_name evsel_streams__report db_export__call_return parse_events_get_in regs_query_register_offset tep_load_plugins perf_config__refresh evlist_streams__delete perf_event__fprintf_aux perf_event__synthesize_build_id comm__new auxtrace_parse_sample_options dwarf_getlocation_addr perf_pmu_parse expr__create_buffer machine__findnew_dso_id parse_events_option_new_evlist show_perf_probe_events build_id_cache__linkname __bitmap_weight EVP_DigestFinal_ex thread_stack__flush perf_pmu__config build_id_cache__list_build_ids zfree_srcline symbol__annotate_zero_histogram parse_events__scan_bytes perf_env__find_bpf_prog_info machine__fprintf_dsos_buildid dwarf_getsrcfiles sample_addr_correlates_sym sysfs__read_build_id arch__post_evsel_config perf_pmu_get_lval sort_global_weight thread__resolve pwrite64 fchmod die_entrypc sample__fprintf_insn_asm thread__set_namespaces _Py_NoneStruct is_regular_file dwarf_formref_die parse_callchain_record_opt evlist__reset_aggr_stats script_fetch_insn probe_cache__scan_sdt symbol__disassemble_bpf arch_perf_header_entry rust_is_mangled hists__col_len perf_event__synthesize_namespaces intel_pt_enable_logging synthesize_perf_probe_command __sw_hweight32 machines__create_guest_kernel_maps tep_set_local_bigendian perf_event__process_text_poke argv_split inat_escape_table_1_2 auxtrace_buffer__drop_data __perf_env__find_btf perf_event__process_itrace_start perf_session__process_events PyImport_AppendInittab ZSTD_flushStream _sort__sym_cmp expr_id_data__source_count elf_getident auxtrace_mmap__munmap parse_events_multi_pmu_add dso__set_nsinfo hists__add_entry_ops debug_set_file iostat_print_header_prefix sample__resolve_callchain callchain_cnode_matched expr__scan_buffer unshare inflate memmem probe_file__open perf_event__process_auxtrace_error probe_cache__purge libunwind__arch_reg_id perf_session__data_offset tracing_data_put cgroup_is_v2 perf_pmu__open_file_at evlist__findnew_cgroup color_fwrite_lines tep_find_common_field backtrace_symbols perf_event__fprintf_stat_config inat_group_table_11_2 die_find_variable_by_reg dso__load_vmlinux_path aggr_cpu_id__is_empty pthread_condattr_init x86_triplets debuginfo__delete write_padded evsel__alloc_counts machine__idle_thread PyImport_AddModule dso__sort_by_name stackop_type perf_stat__set_big_num machine__normalized_is sort_addr_from parse_events__set_leader sort_srcline svg_ubox inat_group_table_21_2 __map__is_ool inat_escape_tables __dso__build_id_filename nsinfo__clear_need_setns ZSTD_isError dso__set_module_info block_info__create_report expr_wrap db_export__dso build_id__mark_dso_hit_ops perf_event__fprintf_thread_map dwfl_module_build_id die_get_data_member_location probe_event_dry_run script_spec_register auxtrace_index__free dwarf_getscopes_die perf_pmu_get_debug _find_first_zero_bit show_available_funcs evsel__config_callchain callchain_merge thread_map__has db_export__exit maps__set_unwind_libunwind_ops build_id_cache__complement perf_pmu_lex_destroy filename__decompress perf_session__set_id_hdr_size svg_close build_id__is_defined vmlinux_path__nr_entries record_opts__config clockid_name perf_more_info_string parse_events_set_debug dso__set_long_name debug_file parse_events_pop_buffer_state sort_socket clear_perf_probe_event inat_escape_table_3_1 sort_addr PyTuple_SetItem machine__findnew_vdso PyDict_SetItemString dsos__fprintf perf_pmu__for_each_format perf_event_attr__fprintf inat_avx_table_5 dsos__find parse_events_add_tracepoint dso__synthesize_plt_symbols __intel_pt_log_packet sort_type_offset parse_events_multi_pmu_add_or_add_pmu exit_event_begin branch_name perf_event__fprintf_ksymbol perf_pmu__convert_scale inat_group_table_17 dwarf_cu_die pthread_mutexattr_destroy __perf_reg_sp_csky unwind__prepare_access lzma_decompress_to_file iostat_mode kallsyms__get_symbol_start machines__destroy_kernel_maps thread_stack__set_trace_nr sort__dcacheline_cmp expr__has_event metricgroups__topdown_max_level tep_read_number_field dwarf_bytesize build_id_cache__kallsyms_path addr_map_symbol__account_cycles perf_time__percent_parse_str threads__remove block_info__delete perf_event__synthesize_comm perf_pmu__caps_parse perf_pmu_get_lineno perf_event__process_cgroup trace_event__tp_format_id parse_ftrace_file EVP_md5 Py_Finalize dso__read_binary_type_filename perf_event__fprintf_text_poke insn_get_prefixes arm_spe_pkt_name perf_debug_setup auxtrace_parse_filters iostat_prefix gelf_getrela perf_env__numa_node evlist__init_trace_event_sample_raw perf_session__findnew perf_can_sample_identifier rewinddir ZSTD_getErrorName hist_entry__collapse __bitmap_and lzma_stream_decoder dso__filename_with_chroot auxtrace_heap__free inat_group_table_16 perf_tool_event__to_str lzma_end sharded_mutex__new trace_seq_init bt_convert__perf2json have_ignore_callees help_unknown_cmd tracing_data_get Py_DecodeLocale _PyTuple_Resize hist_entry__srcline sort_in_tx namespaces__free maps__find_ams evsel__match_bpf_counter_events map__objdump_2mem dso__data_write_cache_addr nsinfo__get perf_session__fprintf_dsos evlist__id_hdr_size default_diff_sort_order perf_can_aux_sample perf_hpp__is_comm_entry insn_get_opcode dwarf_onesrcline arch_get_runtimeparam free_callchain map__has_symbols inat_avx_table_6_3 hist_entry__filter report__browse_block_hists inat_group_table_16_1 disasm__fprintf expr__strcmp_cpuid_str evlist__copy_res_stats dwarf_formudata parse_events_set_column PyUnicode_FromString perf_pmu_get_column tep_set_page_size tep_get_events_count addr_filters__parse_bare_filter intel_pt_set_first_timestamp machine__is_lock_function s390_triplets tep_print_event perf_event__synthesize_stat_events dwarf_formsdata get_cpuid perf_config_u8 maps__fixup_overlap_and_insert perf_pmu__event_source_devices_fd synthesize_probe_trace_command perf_hpp__is_dso_entry riscv32_triplets dwarf_child pthread_rwlock_destroy clear_probe_trace_event dwarf_formblock sort_dso_from inat_avx_table_5_2 arm_spe_get_packet dso__sorted_by_name perf_session__find_first_evtype branch_type_stat_display symbol__elf_init machine__fprintf_vmlinux_path arch__compare_symbol_names_n annotation_options__exit intel_pt_recording_init map__find_symbol_by_name_idx evlist__add_dummy inat_escape_table_3_3 exit_probe_symbol_maps perf_event__process_switch evlist__s390_sample_raw global_var_type__tree_delete svg_legenda perf_config_int perf_config_set__load_file symsrc__destroy annotated_data_type__update_samples inat_group_table_9 machine__create_extra_kernel_maps compare_proc_modules debug_data_convert sort_sym_ipc_null arch_syscalls__strerrno_function perf_event_header__bswap debuginfo__find_probe_point strfilter__new dso__data_read_addr debuginfo__get_text_offset path__join3 expr_parse thread__fork expr__subset_of_ids symbol__disassemble_bpf_image perf_session__fprintf_nr_events get_target_map parse_events_get_lineno maps__find_next_entry evlist__enable_non_dummy threads__findnew annotate_get_insn_location clock_getres inat_avx_table_4_3 die_get_varname PyLong_FromLong dsos__for_each_dso inat_primary_table addr_map_symbol__exit filename__has_section cleanup_sdt_note_list machines__add tep_get_first_event evlist__set_tp_filter_pids __evlist__combined_sample_type compat_auxtrace_mmap__write_tail mbind dwarf_cfi_addrframe annotation__trylock evsel__fallback pthread_rwlock_unlock PyErr_Occurred dump_insn auxtrace_cache__free_entry parse_filter rmdir intel_pt_pmu_default_config dso__type_fd get_branch_type tep_register_comm sort_mem_phys_daddr nsinfo__is_in_root_namespace dso__delete_symbol numa_topology__delete perf_default_config expr_set_debug metricgroup__copy_metric_events inline_node__delete die_get_call_lineno thread__resolve_callchain perf_pmu__file_exists annotate_check_args trace_event__tp_format list_available_dlfilters strbuf_grow insn_get_immediate annotation__get_branch evsel__parse_sample_timestamp sort_dimension__add arch_evsel__hw_name perf_pmu__cpu_slots_per_cycle find_data_type machines__find_guest fopencookie svg_page_width db_export__thread bpil_addr_to_offs perf_pmu__format_bits perf_event__process_id_index evsel__exit __perf_reg_ip_arm64 __bitmap_equal syscalltbl__id iostat_parse arm_spe_pkt_desc svg_pstate hex_width perf_tool_event__from_str perf_pmu__create_placeholder_core_pmu cpu_topology__new sort_mem_dcacheline sort_addr_to parse_ftrace_printk sample__fprintf_sym parse_events__scan_buffer dlfilter__start srcline__unknown perf_env__read_cpuid arch_evlist__cmp auxtrace_record__init auxtrace_record__snapshot_start perf_mem__tlb_scnprintf sort_sym_to probe_cache__commit copyfile_offset dwarf_lineprologueend perf_version_string thread__new perf_pmu__event_source_devices_scnprintf perf_env__read_pmu_mappings map__kmaps __evlist__set_tracepoints_handlers machine__new_kallsyms db_export__machine evlist__cancel_workload strlist__remove callchain_append disasm_line__free cs_etm__process_auxtrace_info syscalltbl__delete _Ux86_64_create_addr_space local_unwind_libunwind_ops get_cpuid_str trace_event__init arch__choose_best_symbol expr_get_out perf_event__process_tracing_data inat_group_table_15_2 strfilter__or evlist__add_aux_dummy callchain_param_setup maps__remove_maps unwind__finish_access perf_pmu_format__set_value gelf_fsize dlfilter__new svg_wakeline value_color_snprintf dso__new_id db_export__branch_type perf_read_values_init sort_dso_to probe_cache__find_by_name parse_events_set_lloc annotate_calc_pcrel probe_cache__find perf_pmu__open_file die_get_member_type evlist__apply_filters setup_perl_scripting inat_group_table_6 tep_get_long_size strpbrk_esc ZSTD_freeCStream dwfl_build_id_find_elf dso__set_sorted_by_name perf_pmu__switch_to_buffer arch__fix_module_text_start thread__comm_len parse_events_get_out nsinfo__mountns_enter iostat_list evlist__disable_evsel strncasecmp strfilter__delete tep_unload_plugins uprobe_ref_ctr_is_supported multiprobe_event_is_supported perf_event__process_namespaces parse_events_term__str machine__create_extra_kernel_map copyfile_ns pmu_metrics_table__for_each_metric perf_singlethreaded intel_pt_log_disable common_flags perf_pmus__have_event inat_escape_table_1_1 perf_pmu_set_column dso__data_size dlclose kcore_copy tep_parse_event mkdir_p intel_pt_process_auxtrace_info sort_time inat_group_table_26_1 dwarf_getcfi __dsos__add inat_group_table_4 ZSTD_freeDStream debug_type_profile perf_event__process_lost perf_session__write_buildid_table perf_env__set_cmdline inat_avx_table_5_1 perf_event__process_event_update sort_sym_offset evsel__common_field intel_pt_insn_name evlist__add_bpf_sb_event inat_group_table_24 dwfl_standard_find_debuginfo inat_avx_tables perf_session__deliver_synth_event expr__add_id_val_source_count inat_escape_table_2_2 dwfl_end thread_stack__br_sample_late syscalltbl__name expr_lex debuginfo__find_trace_events evsel__taskstate distro_dwarf_types perf_session__queue_event mem_bswap_64 map__clone die_find_func_rettype parse_events_set_lval create_perf_stat_counter expr__del_id perf_can_record_switch_events arch_topdown_sample_read auxtrace_queue_data dso__next_symbol fstat64 parse_events_lex expr_lex_init machines__findnew_guest_code perf_pmu__name_from_config parse_events_add_cache probe_type_is_available trace_event__cleanup dwfl_report_end expr_set_extra dso__fprintf_symbols_by_name evlist__add_sb_event Py_Initialize sort_mem_snoop perf_pmu_push_buffer_state tep_set_loglevel thread__exec_comm nsinfo__new dwarf_ranges die_find_variable_at cpu__max_present_cpu config_exclusive_filename machine__process_text_poke expr_pop_buffer_state perf_counts__new default_mem_sort_order dwarf_lineaddr inat_escape_table_2 __sigsetjmp perf_pmu__scan_string PyBytes_FromStringAndSize block_ranges machine__nr_cpus_avail expr_set_lval perf_tip parse_callchain_report_opt perf_top__header_snprintf parse_events__switch_to_buffer evlist__add_pollfd hist_iter_mem probe_file__get_events zstd_fini branch_spec_desc expr_get_in scripting_max_stack machine__process_fork_event dwfl_offline_section_address expr__get_literal sighandler_dump_stack die_walk_instances strbuf_read intel_pt_insn_desc evlist__init cpu_map__online evsel__is_function_event perf_session__fprintf_info srcline__tree_find perf_time__parse_for_ranges_reltime __open64_2 evsel__hw_cache __perf_reg_name_arm dwfl_report_offline symsrc__possibly_runtime arch_get_tsc_freq dwarf_getlocation expr_set_lineno expr__flush_buffer hists__inc_nr_lost_samples unwind__flush_access rename auxtrace_queues__process_index perf_hpp__is_srcfile_entry sdt_notes__get_count cu_get_comp_dir branch_type_str arch__user_reg_mask call_path_root__free perf_pmu_lex_init __intel_pt_log svg_build_topology_map perf_pmu__arch_init dwarf_getlocations evsel_streams__match perf_env__read_cpu_topology_map cap_get_proc ZSTD_compressStream filename__sprintf_build_id evlist_cpu_iterator__end perf_config_system hists__calc_col_len auxtrace_mmap_params__set_idx evlist__add_wakeup_eventfd perf_stat__skip_metric_event perf_time__range_alloc map__fprintf_dsoname thread_stack__depth inat_avx_table_4_2 PyObject_GetAttrString block_info__free_report cpu_isa_init unknown_type perf_config_bool db_export__init perf_event__fprintf_comm addr_map_symbol__inc_samples perf_can_record_cpu_wide evlist__enable_evsel apply_perf_probe_events zstd_compress_stream_to_records perf_event__fprintf_aux_output_hw_id annotation_line__add ru_stats svg_box PyByteArray_FromStringAndSize kvm_entry_event perf_pmu_set_debug itrace_parse_synth_opts percent_color_fprintf sort_cpu evlist__sample_id_all get_sdt_note_list auxtrace__evsel_is_auxtrace levenshtein pthread_condattr_destroy maps__empty auxtrace_buffer__free arch_is_branch perf_pmus__print_raw_pmu_events threads__find syscalltbl__id_at_idx EVP_MD_CTX_free evsel__set_leader perf_event_paranoid_check dso__data_write_cache_offs e_snprintf perf_pmu__is_software dso_id__empty convert_unit_double perf_stat_process_percore parse_events_set_extra auxtrace_cache__alloc_entry parse_cgroups affinity__setup cxx_demangle_sym perf_script__meminfo_scnprintf perf_parse_sublevel_options strfilter__and die_walk_lines parse_events_add_breakpoint svg_highlight_name elf64_newphdr perf_stat__print_shadow_stats_metricgroup ctime srcline__tree_insert perf_event__process_lost_samples veprintf perf_pmus__default_pmu_name exit_event_decode_key PyCallable_Check perf_session__has_traces evsel__metric_id set_term_quiet_input gelf_newehdr machine__process_aux_output_hw_id_event nsinfo__stat rblist__entry arch_perf_synthesize_sample_weight map__fprintf_dsoname_dsoff _Py_BuildValue_SizeT inat_avx_table_7_3 build_id__mark_dso_hit chk_double_cl print_spark tep_register_print_string inat_group_table_18 arch__post_process_probe_trace_events ordered_events__delete map__delete die_skip_prologue hist_entry__transaction_len sort_sym_from pthread_cond_broadcast debuginfo__find_available_vars_at sample__resolve_mem strlist__add inat_group_table_24_2 die_get_var_range evsel__env __map__is_bpf_image config_error_nonbool perf_pmu__pathname_fd perf_session__create_kernel_maps perf_can_record_text_poke_events expr__scan_bytes evlist__exit rblist__delete tracepoint_id_to_name perf_pmu__check_alias perf_read_values_add_value show_bootconfig_events perf_pmu__mem_events_ptr die_is_func_def evlist__initialize_ctlfd auxtrace_record__info_priv_size pmu__name_match sort_local_ins_lat dso__cmp_id inat_get_avx_attribute arch_sdt_arg_parse_op perf_event__fprintf_mmap2 get_page_size_name arch__is build_id_cache__add machine__process_cgroup_event color_vfprintf auxtrace_synth_guest_error pstack__pop perf_event__process_ksymbol down_write svg_running __evsel__get_config_term perf_missing_features perf_session__cpu_bitmap PyLong_FromUnsignedLongLong up_write evlist__has_amd_ibs perf_etc_perfconfig __evlist__parse_mmap_pages setup_python_scripting hybrid_topology__delete disasm_line__scnprintf hists__inc_nr_samples cpu_topology__delete __map__is_bpf_prog die_find_child parse_events_alloc memchr_inv die_get_decl_file dso__is_object_file dwfl_begin binary__fprintf auxtrace_record__read_finish mmap_cpu_mask__scnprintf perf_pid_map_tid perf_config_set__new die_find_tailfunc pthread_key_create parse_events_get_leng __evlist__add_default_attrs perf_pmu_alloc __sw_hweight8 nsinfo__set_in_pidns sh_regstr_tbl iostat_release auxtrace_queues__sample_queue perf_session__inject_header comm__free sort_mem_blocked intel_pt_pkt_name lsdir_no_dot_filter evlist__mmap_size s390_cpumsf_process_auxtrace_info perf_mmap__push machine__thread_list __perf_reg_ip_s390 stdin tep_parse_header_page evlist__reset_prev_raw_counts _find_next_and_bit tep_read_number evlist__force_leader sort_local_p_stage_cyc die_collect_vars perf_event__process_mmap perf_event__fprintf_task aggr_cpu_id__equal machine__process_lost_samples_event parse_events_term__clone tep_print_fields cpu__get_cluster_id evlist__set_cb machine__hit_all_dsos c2c_decode_stats symbol__restricted_filename thread_list__delete parse_events_get_lval auxtrace_queues__init_nr kvm_entry_trace PyUnicode_AsUTF8 hists__output_resort_cb trace_event__register_resolver hist_entry__inc_addr_samples perf_pmus__pmu_for_pmu_filter PyObject_IsTrue evlist__disable_non_dummy threads__init sort_sym_size auxtrace__free debuginfo__find_line_range metricgroup__parse_groups mips_triplets parse_events_get_debug __perf_reg_sp_loongarch auxtrace__process_event perf_pmu__auto_merge_stats machine__get_current_tid sh_triplets ferror auxtrace_synth_error ordered_events__init output_field_add __longjmp_chk pmu_uncore_identifier_match rblist__exit thread__main_thread hist_entry__append_callchain evlist__close_control parse_events_term__num perf_env__exit get_arch_regstr perf_event__synthesize_for_pipe bpf_map__fprintf perf_pmu__mem_events_list machine__destroy_kernel_maps sort__daddr_cmp evlist__mmap_ex thread__set_priv_destructor fill_callchain_info machine__process_aux_event hisi_ptt_pkt_desc dlfilter__do_filter_event del_perf_probe_events x86_32_unwind_libunwind_ops dso__decompress_kmodule_fd evsel__init machines__create_kernel_maps canary_type do_write block_range__coverage __rb_insert_augmented dirfd dwarf_linesrc dsos__find_kernel_dso do_realloc_array_as_needed expr_lex_init_extra PyDict_New sort_comm kvm_skip_events evsel__set_config_if_unset perf_data__write gelf_newphdr get_current_dir_name dlfilter__cleanup perf_pmu__mem_events_init build_id_cache__cached perf_event__process_bpf tep_parse_format sort_mem_lvl pread64 perf_pmu_set_lval dso__get threads__for_each_thread arch_perf_parse_sample_weight __perf_reg_name_riscv kcore_extract__delete event_symbols_hw pmu_for_each_sys_event dlopen parse_events__flush_buffer _Ux86_64_flush_cache evlist__parse_event_enable_time annotation__exit kallsyms__get_function_start PyCapsule_GetPointer expr_set_in pthread_rwlock_wrlock dwarf_formstring proc_map_timeout svg_lbox pmu_events_table__num_events sort_mispredict iostat_print_metric rust_demangle_sym evsel__append_addr_filter inat_avx_table_7_2 parse_line_range_desc dwarf_siblingof EVP_DigestInit_ex line_range__clear disable_buildid_cache nsinfo__in_pidns sort_help powerpc_triplets evlist__add_attrs session_done path__join expr__add_ref perf_stat__print_shadow_stats dwarf_filesrc evsel__leader evsel__prepare_open thread_stack__br_sample PyErr_Clear evsel__id_hdr_size machine__resolve_kernel_addr dso__set_build_id perf_env__find_pmu_cap asprintf_expr_inout_ints perf_session__peek_event call_return_processor__new read_cgroup_id log10 arm_spe_process_auxtrace_info parse_events_option funlockfile perf_event__fprintf_event_update inat_group_table_10_3 perf_config__exit dso__name_len machine__process_namespaces_event evsel__bpf_counter_events scripting_context kretprobe_offset_is_supported dso__build_id_equal evsel__clone evsel__group_desc evsel__store_ids maps__remove strfilter__string __perf_reg_name_s390 auxtrace_heap__add dwarf_lineendsequence build_id_cache__list_all map__contains_symbol __map__kmap dsos__read_build_ids copy_to_probe_trace_arg mmap__mmap_len perf_pmu__warn_invalid_config evlist__print_counters machine__is probe_cache__delete annotate_parse_percent_type call_path__findnew PyList_Append evsel__object_config auxtrace_buffer__put_data thread__memcpy perf_env__has_pmu_mapping perf_pmu__scan_buffer map__new2 find_source_path add_perf_probe_events parse_events_terms__delete map__fixup_start strlist__new pthread_cond_init __perf_hook_func_record_end perf_config_scan probe_file__del_strlist probe_cache__filter_purge perf_pmu_get_in intel_pt_decoder_new strtok auxtrace_index__process topdown_sys_has_perf_metrics cpu_topology__smt_on inat_avx_table_6 evlist_cpu_iterator__next evlist__warn_user_requested_cpus perf_session__read_header intel_pt_log_set_name __perf_event__synthesize_id_index evlist__combined_branch_type sample__fprintf_insn_raw evlist__create_streams auxtrace_mmap__read sample__resolve_bstack __realpath_chk intel_pt_log_dump_buf default_top_sort_order bpil_offs_to_addr call_path_root__new __perf_hook_func_record_start fdopen arm_spe_decoder_free get_leaf_frame_caller_aarch64 evlist__append_tp_filter_pids parse_events_set_in svg_process sort_cgroup_id inlines__tree_delete sort_global_ins_lat evlist__set_default_cgroup inat_group_table_8 probe_file__del_events sort_srcfile namespaces__new perf_event__process_exit gelf_xlatetom dwarf_highpc perf_data__open timerfd_create dwarf_attr_integrate dsos__hit_all kvm_exit_event lzma_is_compressed EVP_DigestUpdate perf_reg_name init_rwsem read_tracing_data build_caches_for_cpu svg_waiting parse_events_get_extra evlist__splice_list_tail perf_tool__fill_defaults user_access_is_supported evlist__copy_prev_raw_counts perf_event__process_auxtrace itrace_synth_opts__set_default __perf_reg_name_powerpc machine__process_switch_event expr_get_column dwfl_module_relocations mmap_cpu_mask__duplicate __bpf_event__print_bpf_prog_info expr_get_debug symbols__delete perf_pmu__scan_bytes jit_process tep_list_events sort_sym parse_events_get_column synthesize_perf_probe_arg inat_group_table_25 evswitch__discard build_id_cache__origname die_collect_global_vars kcore_extract__create event_enable_timer__process perf_session__dump_kmaps fetch_current_timestamp __bitmap_intersects dwarf_getfuncs __isoc23_strtoll tep_alloc get_dwarf_regnum tep_find_any_field evlist__find_tracepoint_by_name __perf_reg_sp_mips events_stats__inc PyList_New perf_debug_option intel_bts_recording_init dlsym get_tls_callchain_cursor evlist__stop_sb_thread perf_pmu_get_text perf_data__make_kcore_dir get_term_dimensions memdup evsel_streams__entry print_sdt_events auxtrace_record__options __perf_reg_sp_arm64 __perf_reg_name_csky addr_filters__exit metricgroup__print iostat_print_counters evsel__fprintf inat_group_table_25_1 evlist__strerror_mmap __get_srcline arch_support_sort_key perf_pmu__for_each_event evlist__exclude_kernel lzma_code is_directory regcomp get_srcline_split symlink inat_group_table_27 insn_rip_relative maps__addr_space thread__delete maps__load_first perf_data__close machine__for_each_thread hists__add_entry_block dwfl_module_getelf lsdir perf_env__nr_pmu_mappings evsel__append_tp_filter fnmatch evsel__sys_has_perf_metrics perf_file_header__read intlist__findnew machine__get_kernel_start zstd_init strlazymatch expr_get_leng expr_lex_destroy hists__new_col_len perf_header__process_sections perf_event__fprintf_bpf inat_escape_table_2_3 perf_sample__sprintf_flags perf_pmu__scan_file mkpath parse_events_error__handle tp_event_has_id auxtrace_index__write _Py_Dealloc pr_stat dwarf_lineno dwfl_module_relocation_info perf_env__nr_cpus_avail hist_entry__get_data_type expr__resolve_id tep_event_fields evsel__hw_cache_result callchain_cursor__copy parse_branch_str perf_event__synthesize_kernel_mmap perf_arch_reg_ip symbol__annotation_init riscv64_triplets __bitmap_or dwarf_cfi_end auxtrace_queues__add_event __perf_env__insert_bpf_prog_info build_id_cache__cachedir parse_events_terms__to_strbuf dso__type scnprintf_pad clearerr perf_stat__set_no_csv_summary PyModule_GetDict sort_abort perf_pmu_get_out perf_event__fprintf_auxtrace_error expr__scan_string _Ux86_64_set_caching_policy symbols__fixup_end parse_synth_opt db_export__call_path svg_cstate die_find_realfunc evsel__is_hybrid parse_perf_probe_command expr_get_extra __perf_hook_func_test inat_escape_table_1_3 __dso__load_kallsyms dso__reset_find_symbol_cache parse_events__modifier_group perf_mem_events__loads_ldlat auxtrace_mmap_params__init perf_event__fprintf_cgroup machine__findnew_kernel sort_dso_size dwarf_getelf evlist__ctlfd_process dwarf_aggregate_size perf_env__arch regexec evlist__id2evsel_strict nsinfo__realpath evsel__calc_id_pos _Ux86_64_destroy_addr_space map__srcline trace_seq_do_fprintf perf_config_set__delete strlist__entry cu_walk_functions_at pthread_mutexattr_setpshared thread__fprintf perf_data__close_dir machine__process_exit_event perf_pmu_lex_init_extra parse_event_file __perf_env__insert_btf sample__fprintf_callchain parse_events__modifier_event maps__fixup_end hists__get_rotate_entries_in hists__delete_entries ignore_callees_regex numa_topology__new parse_events_wrap machine__get_kallsyms_filename PyObject_CallObject feat_ops ZSTD_decompressStream __symbol__fprintf_symname_offs PyBool_FromLong parse_events_lex_init __perf_reg_ip_riscv aggr_cpu_id__empty perf_event__process_fork dso__last_symbol auxtrace_record__info_fill perf_arch_reg_sp perf_hpp__is_trace_entry strlist__find is_valid_tracepoint dwarf_addrdie __block_info__cmp callchain_cursor_reset cpu__max_node debug_display_time common_lock_depth getpwuid_r die_find_top_inlinefunc inat_group_table_18_1 map__fprintf_srcline parse_events_add_numeric dso__free_a2l down_read perf_event__fprintf_stat perf_pmu__create_buffer db_export__exec_comm expr_set_column eprintf_time maps__unwind_libunwind_ops svg_interrupt inat_group_table_7 insn_decode arch__find __dso__inject_id syscalltbl__strglobmatch_next annotation_options__init rb_replace_node get_cpuid_0 open_trace_file die_deref_ptr_type __perf_reg_ip_loongarch perf_probe_with_var arch_evsel__open_strerror auxtrace_buffer__next dwarf_getpubnames hist_entry__cmp evlist__id2sid sigqueue inat_get_group_attribute inat_group_table_17_1 perf_event__synthesize_extra_kmaps perf_session__auxtrace_error_inc _find_first_and_bit parse_task_states perf_host setup_list db_export__switch evsel__intval_common dsos__findnew_id die_get_real_type perf_hist_config __symbol__fprintf_symname fgetc maps__copy_from intel_pt_log_enable inat_group_table_21_1 auxtrace_heap__pop parse_events_push_buffer_state machines__process_guests __bitmap_clear print_hwcache_events sort_mem_data_page_size inat_avx_table_6_2 x86__is_amd_cpu die_is_signed_type parse_clockid dso__is_vdso evsel__precise_ip_fallback ins__find __perf_reg_ip_powerpc threads__exit db_export__symbol perf_env__cpuid perf_event__fprintf_namespaces strcspn _Py_FatalErrorFunc common_pc perf_data__switch perf_can_record_cgroup machine__process_ksymbol perf_hpp__is_srcline_entry perf_pmu__flush_buffer rblist__add_node tep_set_long_size rblist__findnew perf_event__synthesize_bpf_events __perf_reg_sp_s390 show_probe_trace_events db_export__sample trace_report ann_data_stat debug_kmaps flockfile evsel__bitfield_swap_branch_flags dsos__findnew_module_dso evsel__zero_per_pkg ordered_events__free die_find_variable_by_addr evlist__get_tracking_event jit_add_debug_info evlist__check_mem_load_aux parse_events_lex_destroy ordered_events__queue regerror symbol__config_symfs expr__switch_to_buffer maps__set_addr_space thread__set_comm_from_proc ZSTD_initDStream nsinfo__mountns_exit callchain_cursor_append dwarf_entrypc sort_cycles perf_data_file__write perf_pmu_realloc perf_pmus__print_pmu_events __openat64_2 srccode_state_free _find_next_zero_bit auxtrace_index__auxtrace_event parse_events_restart python_scripting_unsupported_ops hists__set_col_len dso__kernel_module_get_build_id PyCapsule_New zstd_decompress_stream arch__normalize_symbol_name sort_mem_locked hists__inc_stats perf_pmu__mem_events_parse PyArg_UnpackTuple default_parent_pattern machines__for_each_thread thread__find_symbol dwarf_diecu dso__find_symbol_nocache dwarf_haspc __perf_hook_desc_record_end sort_cgroup getpwnam_r default_tracepoint_sort_order sysfs__sprintf_build_id sort_code_page_size tep_free die_is_optimized_target affinity__set nr_cgroups __cgroup__find intlist__remove thread_stack__sample tep_set_flag sort_mem_daddr_sym dwarf_frame_cfa PyLong_FromUnsignedLong dwarf_offdie annotation_config__init parse_callchain_top_opt perf_event__process_finished_round open_svg threads__nr block_info__new copyfile_mode perf_pmu_set_lineno strfilter__compare aggr_cpu_id__global arch_evsel__must_be_in_group evlist__find_evsel_by_str __perf_reg_sp_riscv hist_entry__annotate_data_tty sort__iaddr_cmp __strncpy_chk annotation_line__next perf_event__process_feature thread__namespaces probe_file__get_namelist inlines__tree_find intel_pt_decoder_free perf_pmu__find_metrics_table list_sort arm_triplets auxtrace__flush_events inat_group_table_13 inat_group_table_15 cpu_map__snprint_mask perf_pmu__pathname_scnprintf perf_usage_string PyModule_Create2 sort_trace cpu__get_die_id symbol__annotate_zero_histograms machine__process_lost_event auxtrace_cache__remove rb_first_postorder default_sort_order probe_conf cpu_aggr_map__empty_new perf_mem_events_intel inat_get_last_prefix_id dso__read_running_kernel_build_id free_config_terms pthread_mutexattr_init evlist__set_id_pos strlist__load localtime_r sort_transaction trace_seq_destroy auxtrace_cache__lookup intlist__add kvm_exit_trace evlist__uniquify_name die_is_func_instance perf_stat_merge_counters gelf_getrel dwarf_tag expr__get_id arm64_triplets parse_events_formats_error_string strftime auxtrace_record__reference branch_new_type_name ui__has_annotation sort__setup_elide PyObject_SetAttrString map__fixup_end pmu_metrics_table__find dwarf_getcfi_elf perf_mem_record tep_print_field die_find_inlinefunc perf_session__register_idle_thread inat_escape_table_3_2 sort_simd __isoc23_vfscanf parse_probe_trace_command addr_location__copy dso_id__cmp is_mem_loads_aux_event auxtrace__free_events __perf_reg_ip_x86 die_get_typename aggr_cpu_id__cluster __perf_session__cache_build_ids evsel__detect_missing_features immediate_value_is_supported die_get_cfa strtailcmp reset_dimensions machine__process_itrace_start_event perf_pmu_wrap inat_avx_table_4 die_compare_name probe_file__open_both symbol__match_symbol_name cu_find_realpath have_tracepoints sort_sym_ipc perf_debuginfod_setup fetch_kernel_version dso__delete qsort_r filename__read_debuglink perf_home_perfconfig print_tracepoint_events hists__inc_nr_events perf_counts__delete hist__account_cycles print_events probe_cache_entry__get_event perf_event__synthesize_extra_attr perf_event__process_auxtrace_info perf_hpp__is_thread_entry perf_event__synthesize_modules inlines__tree_insert arch_fetch_insn argv_free db_export__branch_types pthread_mutex_destroy svg_text record__parse_freq strlist__delete evlist__cpu_begin perf_pmu_lex ins__is_call hist_iter_branch asprintf__tp_filter_pids __hists__init perf_pmu__lookup evsel__remove_from_group dwfl_module_addrsym parse_events__delete_buffer c2c_add_stats evlist__findnew_tracking_event perf_event__process_mmap2 _Ux86_64_init_remote evlist__finalize_ctlfd dso__demangle_sym inat_escape_table_1 db_export__evsel debug_set_display_time thread_map__new_all_cpus comm__str callchain_avg_cycles color_vsnprintf pthread_cond_wait __perf_reg_name_x86 machines__fprintf_dsos strglobmatch_nocase PyErr_Print perf_event__synthesize_features EVP_MD_CTX_new perf_mem__blk_scnprintf rb_next_postorder perf_ns__name PyUnicode_FromStringAndSize map__set_kallsyms_ref_reloc_sym ins__is_nop evsel__rawptr get_dwarf_regstr expr_restart probe_cache__new evlist__amd_sample_raw dsos__fprintf_buildid parse_events__shrink_config_terms inat_avx_table_5_3 machines__findnew dwarf_dieoffset cleanup_perf_probe_events tep_get_header_page_size perf_event__process_aux_output_hw_id db_export__comm_thread perf_event__synthesize_attrs probe_cache__show_all_caches parse_branch_stack cgroup__findnew evsel__output_resort_cb gelf_update_ehdr maps__get addr_filters__init ann_insn_stat rblist__remove_node __read_chk cu_find_lineinfo ZSTD_createCStream __perf_reg_ip_mips perf_counts__reset perf_event__process_stat_event machine__thread_exec_comm perf_can_comm_exec sort_local_weight machine__process_bpf sort_mem_iaddr_sym tep_find_field pthread_mutex_trylock ZSTD_initCStream machine__map_x86_64_entry_trampolines machines__set_id_hdr_size intel_pt_log_fp gelf_update_phdr perf_event__fprintf_time_conv kvm_exit_reason perf_env__pmu_mappings show_line_range arch_evlist__add_default_attrs evlist__set_tp_filter nsinfo__tgid PyLong_AsLong thread__free_stitch_list parse_saved_cmdline comm__override cpu_cache_level__free hists__output_recalc_col_len perf_event__fprintf_mmap ordered_events__reinit parse_events__scan_string branch_type_count svg_io_legenda inat_escape_table_2_1 probe_cache__add_entry __perf_reg_name_mips perf_cpu_map__empty_new evsel__reset_counts intel_pt_decode pthread_cond_destroy exit_rwsem evlist__ctlfd_ack threads__remove_all_threads svg_highlight perf_hpp__is_sym_entry PyDict_GetItemString auxtrace_mmap__mmap dso__load_sym fileno event_format__fprintf gzip_is_compressed __perf_reg_ip_csky intel_pt_fast_forward perf_data__kallsyms_name perf_mem_events_amd dso__load_vmlinux perf_event_paranoid symbol__annotate evlist__scnprintf_evsels perf_config_set expr_get_lval find_sourceline evlist__find_tracepoint_by_id evlist__fprintf_nr_events syscalltbl__strglobmatch_first dwarf_diename perf_config_set__collect auxtrace_queues__free die_find_member gmtime strspn auxtrace_queues__init build_id__sprintf events_stats__auxtrace_error_warn debuginfo__new perf_event__process_aux build_id__init dso__data_file_size thread_map__new_by_tid_str pthread_mutex_init perf_mem_events_intel_aux hists__get_entry is_bts_event dwarf_hasattr cacheline_size perf_event__synthesize_auxtrace_info convert_perf_probe_events __isoc23_vsscanf probe_file__get_rawlist syscalltbl__new evlist__add_newtp perf_time__skip_sample cap_free perf_session__fprintf_dsos_buildid dwarf_linebeginstatement perf_pmu__scan_file_at perf_pmu_free __map__is_extra_kernel_map cpu_aggr_map__new perf_event__fprintf_switch event_attr_init thread__insert_map expr__add_id auxtrace_regroup_aux_output perf_can_record_build_id ordered_events__flush _Ux86_64_step copy_config_terms thread_stack__event addr2line_timeout_ms machine__addr_cpumode regfree sort_srcline_to event_type dso__parse_addr_inlines is_perf_data intel_bts_process_auxtrace_info parse_events__create_buffer symbol__tty_annotate block_range__create evlist__reset_stats thread__init_maps nsinfo__init thread_map__new_by_uid gzip_decompress_to_file inat_group_table_21 default_branch_sort_order PyInit_perf_trace_context sysctl__max_stack perf_event__synthesize_tracing_data perf_event__process_build_id timerfd_settime nsinfo__put expr_alloc inflateEnd sort_mem_tlb insn_init cpu__get_core_id perf_config_global perf_env__purge_cgroups reallocarray ref_reloc_sym_names dwarf_nextcu die_get_typename_from_type evsel__compute_deltas perf_event__attr_swap parse_events__is_hardcoded_term is_event_supported expr_get_text perf_mem_events_find_pmu expr_push_buffer_state strreplace perf_callchain_config insn_get_length PyTuple_New block_range__find perf_pmu_set_extra intel_pt_find_overlap inat_avx_table_7 parse_callchain_record PyRun_SimpleFileExFlags auxtrace_parse_snapshot_options machine__set_current_tid __perf_reg_name_loongarch scripting_context__update up_read parse_intr_regs __symbols__insert parse_events_realloc expr_id_data__value __perf_hook_desc_record_start tep_find_event perf_env__single_address_space parse_events_error perf_env__init copyfile thread__find_cpumode_addr_location iostat_prepare dso__strerror_load perl_scripting_unsupported_ops dwarf_decl_line read_all_cgroups evsel__is_leader inflateInit2_ parse_events__add_event parse_filter_percentage elf_section_by_name hists__reset_col_len symbol__tty_annotate2 name_to_handle_at parse_events_lex_init_extra perf_event__process_comm decay_callchain dwfl_report_begin insn_get_displacement expr_realloc parse_events__filter_pmu perf_stat_process_counter build_id_cache__remove_s dso__find_symbol perf_event__fprintf_stat_round nsinfo__pid inat_group_table_10 nsinfo__copy perf_tool__process_synth_event auxtrace_cache__free exclude_perf event_symbols_sw perf_reg_value inat_group_table_14 get_bpf_prog_info_linear sort_thread machines__fprintf_dsos_buildid thread__find_map_fb evsel__source_count _Ux86_64_dwarf_search_unwind_table event_format__print machines__set_comm_exec evlist__reset_weak_group tep_set_function_resolver svg_partial_wakeline perf_pmu__warn_invalid_formats strtobool auxtrace_record__free perf_data__open_dir PySys_SetArgv strpbrk perf_data__read syscalltbl_native_max_id perf_pmu_set_in pthread_setspecific python_scripting_ops rblist__find auxtrace__dump_auxtrace_sample __build_id_cache__add_s rlimit__increase_nofile annotated_data_type__tree_delete auxtrace_record__snapshot_finish evlist__start_sb_thread machine__exit_vdso map__objdump_2rip thread_stack__process perf_data__guest_kallsyms_name symbols__fixup_duplicate hists__reset_stats affinity__cleanup inat_group_table_5 __perf_reg_sp_arm ftruncate64 pmu_metrics__broadwellx pmu_for_each_core_event pmu_events__tigerlake pmu_events__westmereex pmu_metrics__icelakex pmu_events__broadwell pmu_metrics__broadwellde pmu_metrics__amdzen4 pmu_metrics__haswellx pmu_metrics__skylake pmu_metrics__icelake pmu_metrics__amdzen2 pmu_metrics__snowridgex pmu_events__icelakex pmu_events__broadwellx pmu_events__nehalemex pmu_events__grandridge pmu_events__alderlaken pmu_events__knightslanding describe_metricgroup pmu_events__skylakex pmu_events__amdzen5 pmu_events__test_soc_cpu pmu_metrics__amdzen5 pmu_events__haswellx pmu_events__graniterapids pmu_events__snowridgex pmu_events_map pmu_metrics__ivytown pmu_events__elkhartlake pmu_events__amdzen4 pmu_metrics__alderlaken pmu_events__ivytown pmu_events__emeraldrapids pmu_events__sandybridge pmu_metrics__haswell pmu_events__broadwellde pmu_events__bonnell pmu_metrics__emeraldrapids pmu_metrics__sandybridge pmu_events__test_soc_sys pmu_metrics__amdzen3 pmu_events__westmereep_sp pmu_metrics__amdzen1 pmu_metrics__grandridge pmu_metrics__elkhartlake pmu_metrics__ivybridge pmu_metrics__alderlake pmu_metrics__cascadelakex pmu_events__alderlake pmu_metrics__rocketlake pmu_events__icelake pmu_events__haswell pmu_events__meteorlake pmu_events__cascadelakex pmu_events__amdzen2 pmu_metrics__jaketown pmu_metrics__test_soc_cpu pmu_metrics__skylakex pmu_metrics__sierraforest pmu_events__lunarlake pmu_events__amdzen1 pmu_events__skylake pmu_events__sierraforest pmu_events__goldmontplus pmu_metrics__sapphirerapids pmu_events__amdzen3 pmu_events__nehalemep pmu_events__westmereep_dp pmu_events__ivybridge pmu_events__goldmont pmu_metrics__tigerlake pmu_events__sapphirerapids pmu_events__jaketown pmu_events__rocketlake pmu_metrics__broadwell pmu_events__silvermont PyArg_ParseTupleAndKeywords Py_BuildValue PyErr_NoMemory PyObject_GenericGetAttr PyObject_Str PyUnicode_FromFormat PyExc_OSError PyErr_SetFromErrno PyArg_ParseTuple _PyObject_New PyErr_Format PyFile_FromFd PyInit_perf PyType_GenericNew PyType_Ready PyModule_AddObject PyExc_ImportError PyErr_SetString perf_kwork_add_work match_callstack_filter lock_stat_find lock_stat_findnew __cxa_atexit libm.so.6 libz.so.1 libelf.so.1 libdw.so.1 libunwind-x86_64.so.8 libunwind.so.8 liblzma.so.5 libcrypto.so.3 libslang.so.2 libpython3.12.so.1.0 libstdc++.so.6 libzstd.so.1 libcap.so.2 libnuma.so.1 libtraceevent.so.1 libc.so.6 ZLIB_1.2.3.3 GLIBC_2.2.5 CXXABI_1.3 XZ_5.0 OPENSSL_3.0.0 SLANG2 libnuma_1.1 libnuma_1.3 libnuma_1.2 ELFUTILS_1.6 ELFUTILS_1.3 ELFUTILS_1.5 ELFUTILS_1.0 ELFUTILS_0.126 ELFUTILS_0.161 ELFUTILS_0.160 ELFUTILS_0.138 ELFUTILS_0.130 ELFUTILS_0.142 ELFUTILS_0.127 ELFUTILS_0.157 ELFUTILS_0.143 ELFUTILS_0.122 GLIBC_2.22 GLIBC_2.33 GLIBC_2.3.3 GLIBC_2.26 GLIBC_2.9 GLIBC_2.8 GLIBC_2.17 GLIBC_2.11 GLIBC_2.4 GLIBC_2.6 GLIBC_2.32 GLIBC_2.3.4 GLIBC_2.28 GLIBC_2.3 GLIBC_2.15 GLIBC_2.14 GLIBC_2.38 GLIBC_2.3.2 GLIBC_2.34 GLIBC_2.7 ! " # # $ % & % ' ( ) * + # % , % - x 3 ) O n ui \ ӯk h ( s +p z b % @ AE # CE ! BE P , + 枙 * ! ( ' ؞ & О # 2 瞙 A 7 P Þ _ ➙ n E - } % si $ " ii ii ii ii ti ii * ri 5 A ui \ ii L I H PI & & #& 5& <& P& j& s& & ( ( ( 0 "( 8 :( @ J( H _( P u( X ( ` ( h ( p ( x ( ( ( ( "( 6( A( P( ^( r( ( ( ( ( ( ( ( ( ( ( #( <( ( U( 0 `( 8 y( @ ( H ( P ( X ( ` ( h ( p ( x ( ( ( ( !( ,( ?( S( g( {( ( ( ( ( ( ( ( ( ( ( ( 0 ( 8 ( @ ( H ( P ( X ( ` ( h )( p 0( ( 8( =( C( N( _( k( x( ( ( ( ( ( ( ( 0( ( ( ( ( ( ( ( 0 %( 8 +( @ 1( H <( P ( X H( ` P( h ^( p k( x x( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( u( ( ( ( 0 ( 8 #( @ 6( H 1( P A( X P( ` >( h V( p ( x ( e( i( ( m( ( .) k .) k 0 1( X k h .) k 9 .) k ; .) k ; .) 8 k @ 9 H .) p k x ; .) k ; .) k .) k ( /) P k X ` /) k 3! +/) k 3! </) k 3! L/) 0 k 8 3! @ _/) h k p J x i/) k J v/) k RB |/) k RB /) H k X /) k /) k /) k /) ( k 8 /) ` k p /) k /) k /) k /) @ k H I P /) x k I /) k L 0) k L 0) k ( L 0 0) X k ` L h $0) k Q ,0) k Q 40) k Q >0) 8 k @ Q H E0) p k x Q O0) k Q [0) k Q d0) k Q ( n0) P k X R ` s0) k R z0) k 0) k B_ 0) 0 k 8 B_ @ m( h k x 0) k 0) k 0) k 0) H k X 0) k ( k ( k ( ( k 8 ( ` k p ( k #( k 0) k 0) @ k P 0) x k 1) k ( k ( k 0 6( X k h A( k 1) k +1) k =1) 8 k H H1) p k [1) k o1) k {1) k ( 1) P k ` 1) k 1) k 1) k 1) 0 k @ 1) h k x 1) k 1) k 2) k !2) H k X 12) k A2) k U2) k i2) ( k 8 }2) ` k p 2) k 2) k 2) k 2) @ k P 2) x k 2) k 3) k 3) k 0 3) X k h ( k ( k Y) ( Y) Y) k) k) l) l) l) ( 'l) 0 9l) 8 Kl) @ ]l) H ol) P l) ` K' Q' ң& _ Q' ܒ& _ R' h & p X #& #& X PR' @S' & X $& $& 0_ `S' h @& x $& S' T' H & P X ` $& %& 1_ T' ` %& & 4_ $& @ V' P 0V' h $& p \ x && V' & \ & HW' ( #& 0 X @ W' +A& _ W' @ H ` 8Y' L& X '& ;0& X ''& H '& P X ` XY' D'& X Y' ! && ! X ! Y' h! && p! X ! Y' " Z' H" L& P" Y `" '& " K'& " Y " Z' # D'& # Y # Y' h# && p# Y # Y' # && # Y # Y' $ @\' $ L& $ b $ '& % n'& % b % p\' h% D'& p% b % Y' % && % b % Y' (& && 0& b @& Y' & ]' ' L& ' ,Y ' '& h' '& p' 8Y ' ]' ' D'& ' Y ' Y' (( && 0( !Y @( Y' ( && ( "Y ( Y' ( '& ( %Y ) '& H) !& P) $Y `) ^' * _' (* L& 0* LY @* '& * ;0& * HY * ''& * '& * CY + '& H+ D'& P+ @Y `+ Y' + && + AY + Y' , && , BY , Y' , `' , L& , g - '& H- ;0& P- `Y `- ''& - (& - \Y - a' . (& . pg . (& h. (& p. g . Xa' . (& . g . (& (/ )& 0/ hg @/ a' / )& / g / a' / )& / lg 0 a' H0 )& P0 ig `0 #)& 0 >)& 0 jg 0 (b' `1 c' 1 L& 1 h 1 '& 1 ;0& 1 hY 2 ''& H2 (& P2 dY `2 a' 2 (& 2 h 2 (& 3 )& 3 h 3 a' h3 (& p3 h 3 d' 3 (& 3 h 3 (& 4 @f' 4 '& 4 h 4 )& 5 )& 5 h 5 )& h5 )& p5 xY 5 pf' 5 )& 5 tY 5 f' (6 )& 06 pY @6 f' 6 )& 6 lY 6 g' @7 g' h7 )& p7 |Y 7 g' 8 h' H8 *& P8 Y `8 h' 8 *& 8 Y 8 h' `9 (j' 9 (l' 9 & 9 \ 9 & 9 `l' : +& : Z : l' h: )& p: Z : m' : +& : Y : Pm' (; s& 0; Y 8; s& @; xm' ; n& ; Y ; n& ; m' ; G' ; Y ; G' < m' H< & P< Y X< 8& `< +& < +& < Y < +& `= o' p= o' = Pq' = )& = Z = g' `> U-& > & > Z > $& @? v' P? 4& `? U& h? (& p? 7& x? 7& ? 7& ? & ? <& ? ~' ? p; ? ? (' ? p; ? 8 ? X' ? p; ? ? ' ? < ? G @ =& @ @ =& (@ 0@ >& 8@ p; @@ H@ >& P@ p; X@ `@ ' h@ p; p@ pF x@ 8>& @ p; @ @ @' @ p; @ p @ J>& @ p; @ 0 @ ]>& @ p; @ p @ p>& @ p; @ @ h' @ p; A O A ' A p; A Y A ' (A p; 0A h 8A ' @A p; HA pm PA ' XA p; `A 0r hA 0' pA p; xA v A X' A p; A { A ' A p; A & A >& A p; A A ' A p; A A >& A p; A P A >& B p; B B >& B p; B Х (B >& 0B p; 8B @B >& HB p; PB Ј XB ' `B p; hB pB >& xB p; B B ?& B p; B B ?& B 7 B 4?& B 5 B ??& B < B C?& B C $& C C G?& (C p 0C Ψ& @C HC e?& XC `C y?& pC xC ?& C C ?& C C ?& C C ?& C C ?& C 06 C ?& D @> D ?& D ` D ?& 0D 0 8D ?& HD @ PD ?& `D hD K=& xD Т D A=& D D 6=& D D +=& D D 0' D 0 D ?& D p D @& E E @& E 0 (E W=& 8E @E $@& PE O XE X' hE T pE x' E , E @@& E Y E Ђ' E _ E ]@& E I E a@& E h E {@& E pm F @& F 0r F @& (F v 0F ' @F { HF 8' XF & `F @& pF xF X' F F @& F 0 F @& F 0 F @& F F @& F P F A& G G A& G @+ G 2A& 0G I 8G JA& HG H PG ]A& `G H hG ' xG pF G s<& G ; G G G ' G G G vA& G Х G A& G G A& G Ј G ' H H A& H (H A& 8H @H A& PH XH A& hH pH A& H H B& H H B& H H 7B& H H QB& H 0 H lB& H @ I B& I 0 I B& (I Ъ 0I B& @I 0 HI B& XI 0 `I B& pI xI ' I @: I C& I 7 I H& I lI& I H& I yI& I I& J .' J I& J I& J I& J I& (J I& 0J I& 8J I& @J I& HJ I& PJ J& XJ J& J H& J +J& J BJ& J TJ& J cJ& J tJ& J J& J J& J J& J L& J & J U& J U& J U& J U& K V& K $V& K >V& K XV& K rV& (K V& 0K V& 8K V& @K V& HK V& PK W& XK (W& `K BW& hK OW& pK \W& xK iW& K vW& K W& K W& K W& K W& K W& K W& K W& K W& K W& K W& K X& K X& K &X& K 4X& K BX& L PX& L ^X& L lX& L zX& L X& (L X& 0L X& 8L X& @L X& HL X& PL X& XL X& `L R& hL R& pL S& xL S& L AS& L US& L lS& L tS& L S& L ' L `' L ' L ' L ' M [& M [& M [& M (' M [& 0M [& HM \& PM (' XM [& `M \& hM [& pM 7\& xM C\& M [& M Y\& M 7\& M C\& M k[& M l\& M h[& M \& M \& M [& M \& N \& N \& N T[& N \& 0N \& 8N \& @N [& HN \& PN \& hN \& pN \& xN G[& N p' N \& N ]& N [& N ]& N ]& N \& N ]& N -[& N -]& N J]& N R]& O [& O R]& O b]& (O p]& 0O R]& 8O [& @O z]& PO ]& XO ]& `O [& hO ]& pO ]& O ]& O ]& O [& O ]& O ]& O ]& O [& O ]& O ]& O ]& O ]& O [& P ' P ]& P ' P [& (P ' 0P ]& HP ]& PP ' XP [& `P ]& pP ^& xP ^& P [& P ^& P %^& P 4^& P ^& P Z& P >^& P J^& P U^& P & P ' P NZ& Q J^& Q ' Q k^& 0Q v^& 8Q @' @Q ^& PQ NZ& hQ ^& pQ @' Q ^& Q ' Q ' Q ^& Q NZ& Q ' Q ' Q ^& Q ' Q H' R ^& R NZ& (R p' 0R H' @R ^& PR ^& XR ^& `R x& pR NZ& R ^& R ^& R <Z& R _& R _& R x& R NZ& R _& R _& S .H& S `ڎ S 9_& S ڎ 0S M& 8S `َ HS >_& PS َ pS .H& S M& S >_& S .H& S M& S >_& T 9_& T M& 0T >_& HT .H& XT .H& hT 9_& pT | xT x T T T M& T .H& T >_& T 9_& T +A& T _& T Ey& T s& T |& T Ⱥ' T (' U ' U X' U & U {' U 1& 0U 8& @U G[& PU \& `U ?& U 3& U L& U f& U & U & U & U & U ډ& U r& U 0 U ' U 8 U & V @7 V & V 5 V ' 0V @3 8V ??& HV : PV & `V 0 hV 8' xV . V ˋ& V . V p' V 1 V _& V j& V v& V & V V P V P V `- W `C W _& (W j& 0W v& 8W & @W @ HW `W ͘& pW ݘ& W & W & W & W & W p W u& W & X P' X & (X & 8X & HX ś& XX & hX ۛ& xX & X & X & X ,& X & X 8& X A& X & Y Q& Y ,F' Y 8F' Y DF' Y 6' (Y nF' 0Y lF' 8Y ~F' @Y H& HY F' PY F' XY 4& `Y F' hY F' pY F' xY F' Y W& Y b& Y j& Y t& Y {& Y & [ WH& [ & [ & [ & [ & ([ Ƣ& 0[ Ϣ& 8[ ݢ& @[ & H[ & P[ & X[ & `[ & h[ & p[ $& x[ 1& [ ;& [ C& [ N& [ `v [ |& [ & [ $& [ & [ ]& [ s& \ I& (\ ' 0\ f^& `\ I' h\ ' p\ "& \ & \ !& \ ,& \ =& \ N& \ X& \ S=& \ ]& ] e& (] o& 0] t& 8] x& `] & h] & ] & ] & ] & ] & ] & ] & ^ x& (^ & 0^ & 8^ & @^ Ũ& `^ ' ^ _& ^ _& ^ ɨ& ^ ը& ^ & ^ & ^ & ^ & ^ & ^ +& _ +A& _ $& _ 1& _ =& _ & (_ ;& 0_ B& 8_ M& @_ e& H_ |& h_ Y& p_ & x_ & _ ^& _ 8& _ d9& _ r9& _ 9& _ x;& _ <9& _ z& _ k& _ Y9& _ w& _ & _ & _ & _ & _ s& ` & ` & ` & ` & ` ű& (` б& 0` & 8` ' @` & H` Υ& `` _& h` (' p` _& x` (' ` ɨ& ` Ψ& ` ը& ` 5& ` & ` & ` & ` (' ` & ` (' ` & ` (' ` & ` (' ` +& ` (' a & a (' a & a (' a & (a +A& 0a $& 8a (' @a 1& Ha (' Pa =& Xa (' `a & ha & pa ;& xa (' a B& a (' a M& a 1& a e& a F& a |& a (' a Y& a (' a & a (' a & a (' b C& b R& b t& b Ȳ& b & (b /& 0b G @b ( Hb b& Pb s& Xb & `b & b & b S& b & b ȷ& b & b ( b & b ( b 0( b ( b J& b e& b y& b & b & b Ǹ& c ݸ& c & c c Hc ` Xc X `c & pc X c e c & c c M c Pz c & c c L c y c & c c `L c py d & d d L d y (d & 8d @d K Hd Pd & `d hd @K pd x xd & d P d J d x d & d p d J d l d $& d 0 d T d z d .& e e e e 6& (e 0e G 8e @e A& Pe Xe S `e he N& xe `@ e @G e & e e R e | e \& e ` e P e e i& e @^ e F f ] f ݢ& f a f F 0f & @f Hf E Pf Xf 5& hf pf O xf Po f t& f f N f p f & f P f `E f pm f & f f E f @n f & g й g N g g & 0g 8g PM @g @ Hg & Xg `g D hg pg C& g g Z g g & g p g [ g g & g ` g C g g & g h j h ` h & h & (h & 0h & Hh : Ph , Xh 9 `h 7 hh ? ph ? xh 7 h `8 h , h 9 h p? h ? h , h @7 h @7 h + h p@ h P+ h , @j R Hj ( Pj * hj , pj + xj ) j 6 j p( j P4 j * j ) j > j ( j 3 j (' j R& j h& j & k & k & k & k & k (' (k .( 0k .( 8k & @k & Hk .( Pk & Xk (/( `k !& hk =& pk S& xk j& k H/( k & k & k f^& k "& k ~D& k \!& k ru& k & k & k * & k & k L& k e& k & l & l & l & l & l & (l & 0l & 8l & @l & Hl & Pl ң& Xl & `l & hl & pl & xl & l a& l & l & l & l & l & l #& l u& l )& l 3& l 9& l C& l J& l ' l S& l [& m b& m i& m r& m z& m & (m & 0m & 8m & @m & Hm & Pm & Xm & `m & hm & pm & xm !& m D& m & m & m YO& m & m & m & m & m & m & m & m & m & m & m & m %& n 0& n /& n 9& n B& n J& (n I& 0n P& 8n W& @n ]& Hn c& Pn !' Xn & `n i& hn q& pn {& xn z& n & n & n & n ?& n & n (& n & n & n v& n & n & n & n & n & n & n & o & o & o L& o & o & (o & 0o & 8o & @o & Ho %& Po /& Xo 9& `o C& ho !& po M& xo V& o L& o _& o f& o m& o {& o & o & o & o & o & o & o & o & o & o & o =& p & p & p & p & p & (p +& 0p >& 8p U& @p l& Hp & Pp & Xp && `p & hp & pp & xp & p & p & p & p & p (& p & p *& p & p & p & p & p & p & p & p & p & q && q +& q 2& q & q @& (q N& 0q ^& 8q k& @q t& Hq & Pq & Xq & `q & hq & pq & xq & q & q & q & q & q & q & q & q & q & q & q & q & q & q Y9& q & q & r 1M& r -& r =& r F& r Q& (r ^& 0r h& 8r r& @r & Hr '& Pr & Xr & `r & hr & pr & xr & r & r & r & r & r & r (& r 9& r F& r T& r b& r o& r & r (& r '& r & r & s & s & s & s & s & (s & 0s & 8s & @s & Hs & Ps & Xs & `s & hs #& ps /& xs 6& s A& s L& s Y& s k& s |& s -?& s & s & s & s & s & s & s & s & s & s & t & t & t & t & t & (t & 0t & 8t ?& @t )& Ht -& Pt =& Xt F& `t Q& ht [& pt g& xt p& t (& t & t & t & t & t & t & t & t & t & t & t & t & t & t __& t & u & u #& u 1& u ;& u M& (u _& 0u m& 8u t& @u }& Hu & Pu & Xu & `u & hu & pu & xu & u & u & u & u & u & u & u & u !& u -& u 8& u ?& u O& u W& u `& u n& u y& v & v & v & v & x & x & x & x & y & y & y & y & y & (y & 0y & 8y '& @y .& Hy :& Py B& Xy N& `y Y& hy i& py v& xy & y & y & y & y & y & y & y & y & y & y '& y 8& y v'& y C& y Q& y [& y e& z w& z & z & z & (z & 0z & 8z & @z & Hz & `z ~& hz & pz & xz n& z 8& z F& z f& z V& z s& z & z & z & z & z & z & z Y9& z & z *& z <& { M& { & { & { & { & ({ & 0{ ű& 8{ W& @{ =& `{ & p{ & { & { & { & { & { & { & { & { & | & | & | (| @| P H| 0f P| X| 8 `| | | P8 | | 0 | e | | p | | d | @ } } 7 } } 0 } d (} nk& 0} c& 8} ' @} k& H} & P} & X} Q( `} & h} Q( p} & x} & } & } 0& } M& } Q( } } M& ~ gn& ~ & @~ pn& H~ & h~ p~ x~ ~ ~ ~ @ ~ ~ ~ ~ @ ~ ~ s& (' ' & & ( & 0 ,& 8 & H ' ` & h (' p & x & & & & & & " Yg& & & & & & & & & & & ( & 0 & 8 & @ ' H Ȅ& P ' X & ` & h & p & x ' & x' & {' & & & & & Ȁ & Ѐ & & & 耍 f<' & & %& )& ' ' ' ( ' 0 -& H *& P ' X ' ` ' h ' p q( x ' ' C' 8q( ' ' ' ' (' C' ȁ ^' Ё z' ' ' 聍 ' ' ' ' :' U' ' +' ( 0 8 @ ` H P w ` ' h ' p ' x ' ' ' 3! 5! 9! PS! V! `W! & Ȃ / ' Ђ u& 3 ' 6 ' & ~' & yE' ( + ' 0 : ' 8 B ' @ J ' H Q ' P y! X z! ` z! h ! p ! x ! ' , ' @ ' ] ' w ' ' ' ' ' ȃ ' Ѓ ( ( ' 胍 , ' @ ' ] ' w ' ' ' ' ' ( ' 0 ' @ ' H , ' P @ ' X ( ' ` > ' h Y ' p q ' ' ( ' & >& "9& Є ^& ' ' ' ' k& 0 ' @ ' P ' ` & p ' ' ' & ' ' Ѕ ' ! ! P! ! ! ( ! 0 ! 8 p! @ ! y' ' ' ' ' @ y' H ' P ' X ' ` ' ' & ' ' ' ' -' Ȋ 6' Њ :' ؊ >' H' 芍 _' P' y' y' U' E' ' H' ( & 0 ' 8 Y' @ c' H v' P ' X ' ` :' h -' y' U' E' ' & ' ' ' ' ȋ ' Ћ ' ؋ y' ' 苍 :' +' ' !' & & ' ' 0 ' @ ' P ' ` ' p ' ' ' & )' Ȍ (' Ќ (' ، (' .' 茍 (' 3' 8' (' <' @' (' E' ( (' 0 (' 8 (' @ J' ` ' h & p & x & & & ó& dz& ˳& ϳ& ӳ& س& ݳ& ȍ & Ѝ & ؍ & & 荍 & & & & & & & & ( & 0 #& 8 (& @ -& H 2& P 7& X <& ` ' h A& p D& x G& J& M& P& S& V& Y& \& `& d& Ȏ h& Ў l& ؎ p& t& 莍 x& |& & & & & & & ( & 0 ' 8 ' @ & H ' P & X & ` ' h ' ' ' ' ' ' ' ' ' ' Ȑ ' А ' ؐ ' ' 萍 $ ' ) ' . ' ' ' ' ' ' ( ' 0 ' 8 ' @ ' H ' P ' X ' ` ' h $ ' p ( ' x , ' 0 ' 4 ' 8 ' < ' @ ' D ' H ' L ' P ' ȑ T ' Б X ' ؑ \ ' ` ' 葍 d ' h ' l ' p ' t ' x ' | ' ' ( ' 0 ' 8 ' @ ' H ' P ' X ' ` ' h ' p ' x ' ' ' ' ' ' ' ' ' ' Ȓ ' В ' ؒ ' ' 蒍 ' ' ' ' ' ' ' ' ( ' 0 $ ' 8 ) ' @ . ' H 3 ' P 8 ' X = ' ` B ' h G ' p L ' x Q ' V ' [ ' ` ' e ' j ' o ' t ' y ' ~ ' ȓ ' Г ' ؓ ' ' 蓍 ' ' ' ' & & & & ( & 0 ó& 8 dz& @ ˳& H ϳ& P ӳ& X س& ` ݳ& h & p & x & p ' x ' ' ' t ' | ' ' ' ' Ȕ ' Д ' ؔ ' ' 蔍 ' ' ' ' ' ' ' ' ( ' 0 ' 8 ' @ ' H ' P ' X ' ` ' h ' p ' x ' ' ' ' ' ' ' ' ' ' ȕ ' Е ' ؕ ' ' 蕍 # ' ( ' - ' 2 ' 8 ' > ' ( D ' 0 J ' 8 P ' @ V ' H \ ' P b ' X h ' ` n ' h t ' p z ' x ' ' ' ' ' ' ' ' ' ' Ȗ ' Ж ' ؖ ' ' 薍 ' ' ' ' ' !' !' 0 !' H !' !' $!' Й )!' ؙ 0!' ' 虍 & & & & & ij& ȳ& ̳& ( г& 0 Գ& 8 ٳ& @ & H & P & X & ` !' h z& 5!' 9!' =!' A!' E!' I!' M!' Q!' U!' Ț Y!' К ]!' ؚ b!' g!' 蚍 l!' q!' v!' {!' !' !' !' !' ( !' 0 !' 8 !' @ !' H !' P !' X !' ` !' h !' p !' x ( ' ' & & & & & ó& dz& ˳& ț ϳ& Л ӳ& ؛ h ' !' 蛍 ( ' !' !' !' !' !' !' !' ( !' 0 !' 8 ( ' @ ˳& H ϳ& P ӳ& X س& ` ݳ& h & p & x & !' !' !' !' !' !' !' !' Ȝ .' М Y ' .' 蜍 .' \& }& P .' .' H1' `1' v1' 1' 1' ȝ 1' Н 1' 1' 蝍 1' 2' 2' /2' B2' U2' i2' }2' ( 2' @ 2' H 2' P 2' ` 2' h 2' 3' 3' +3' F3' ]3' p3' Ȟ 3' О 3' 3' 融 3' 3' 4' 4' ,4' C4' @ V4' H `4' P w4' X 4' ` 4' h 4' p 4' x 4' 4' 4' 5' 5' П `( ؟ ! <' 蟍 !' <' !' <' !' <' !' <' ( !' 0 <' 8 !' @ <' H !' P <' X !' ` <' h !' p <' x !' <' !' <' !' <' !' <' !' <' Ƞ !' Р <' ؠ !' ࠍ <' 蠍 !' =' !' =' !' =' !' =' ( !' 0 =' 8 !' @ =' H !' P =' X !' ` %=' h !' p *=' x ( ' /=' ( ' 4=' ( ' 9=' ˳& >=' ˳& C=' ȡ ˳& С H=' ء ϳ& ࡍ M=' 衍 ϳ& R=' ϳ& W=' ӳ& ]=' ӳ& c=' ( ӳ& 0 i=' 8 س& @ o=' H س& P u=' X س& ` {=' h ݳ& p =' x ݳ& =' ݳ& =' & =' & =' & =' Ȣ & Т =' آ & ࢍ =' 袍 & =' & =' & =' & @ & P & ` & p & & & && & Y ' У & ࣍ z' ' B& E& H& 0 L& @ P& P T& ` X& p \& Ƶ& ˵& е& յ& ڵ& Ф ߵ& ऍ & & & & & 0 & @ & P & ` & p & >' >' >' >' <' Х <' ् !' <' <' <' !' 0 <' @ <' P <' ` !' p <' <' <' !' <' =' Ц <' !' =' =' =' !' 0 =' @ !=' P =' ` !' p &=' +=' 0=' ) ' 5=' ̳& Ч D=' ্ ?=' :=' г& S=' N=' 0 I=' @ Գ& P d=' ` ^=' p X=' ٳ& v=' p=' j=' & Ш =' =' |=' & =' =' 0 =' @ & P =' ` =' p =' & =' =' =' >' ੍ !' !' !' !' !' 0 !' @ !' P ( ' ` ˳& p ϳ& ӳ& س& ݳ& & & Ъ & % `% P% % % `% @% ( `% @ P " ` + p 3 7 @7 47 (7 7 ્ ; ; c @W P 0 P @ O P dO ` @N p D < < ; h Ь h h @ 0 @ P y ` o p `o o l Э ୍ Ć 0 Æ @ Æ P Æ ` Æ p ` @ < 8 Ю `dž 0 @ P ` ` p ކ ݆ ۆ ؆ Ն Я І ் `φ φ Ά Ά ̆ 0 @ P ` ` p ` ` ` L H 0 0 ( @ P ` " " * $ # б # ్ # # `# 0 : 0 9 @ @7 P `6 ` 5 p 5 3 3 2 1 @@ `S P M J J 0 H @ E P D ` B p `B Y [ [ [ г ` ್ ࣇ 0 Ĉ @ P @| ` s p h g g e д ` P ʇ @LJ Ç 0 @ P ` ` p ` @Ї ҇ е ҇ ് ҇ ҇ ҇ 0 @ P ` p އ އ ݇ ݇ `ۇ ڇ ж `ڇ ඍ ه ه ؇ @ 0 @ P ` p ` $ @ 0 @ P ` p ` @ и ญ * + 0 0 0 @ / ` j p W Q I @H @A 7 й 7 ํ 6 `4 @ ঈ 0 @ P ` ` p ` к ຍ ` @ @ 0 @ @ @ P ` `ň @ň ň Ĉ ш л @Ո ໍ ۈ ۈ @ֈ ܈ @ 0 @ P `݈ ` ` @ м ། @ @ 0 @ P ` t p @ ཌྷ ` T 0 @ ` p о ྍ & U& @& 0 -& @ & P & ` & p h& D' & D' Ҫ& & п & & (& ?& X& q& 0 & @ & P D' ` D' p D' ( ( & ߫& ū& E' & & l& )E' CE' 0 X& @ ]E' P gE' ` t& p rE' ~E' E' E' E' E' E' E' E' E' F' F' 0 %F' @ 1F' P =F' ` IF' p UF' eF' wF' F' F' F' F' F' F' Í F' Í F' Í G' HÍ V PÍ G XÍ N `Í `R hÍ J pÍ J xÍ `R Í C Í @@ Í < Í < Í & Í ^ Í & Í L' (č & @č M' č S & č U' č && ō U' ō && ō U' Hō )& Pō Y `ō Xj' ō *& ō Y ō j' ƍ *& ƍ Y ƍ j' hƍ (& ƍ k' (Ǎ i,& @Ǎ 0o' Ǎ >& Ǎ Xo' Hȍ ,& `ȍ q,& ȍ ,& ȍ ,& ɍ L& ɍ '& ɍ 4& ɍ 4& (ʍ 4& @ʍ 4& ʍ 4& ʍ && ʍ 4& ʍ 5& ʍ && ˍ 5& Hˍ 5& Xˍ && `ˍ v' ˍ ,5& ˍ && ˍ 65& ̍ #& ̍ w' h̍ K5& ̍ 8w' ̍ S5& ̍ hw' (͍ Z5& @͍ w' ͍ e5& ͍ w' ͍ q5& x' H 5& ` (x' *1& Px' ύ 5& ύ 5& hύ 5& ύ x' ύ 5& ύ x' (Ѝ 5& @Ѝ x' Ѝ 5& Ѝ 5& Ѝ & э 5& Hэ !1& `э y' э 6& э Hy' ҍ "6& ҍ 66& hҍ R6& ҍ y' ҍ X6& ҍ j6& (Ӎ v& 8Ӎ 6& @Ӎ y' XӍ Ӎ 6& Ӎ 6& Ӎ @z' Ӎ P Xԍ 8n& pԍ & 8ݍ 0 @ݍ SY& ݍ tY& ݍ lY& ݍ j& ݍ ( ލ j& ލ FA' 0ލ j& 8ލ ( `ލ j& hލ XA' ލ j& ލ oA' ލ j& ލ A' ލ j& ލ ( ߍ j& (ߍ A' Pߍ j& Xߍ A' ߍ j& ߍ A' ߍ j& ߍ A' ߍ j& ߍ A' j& A' @ j& H B' p j& x "B' j& 4B' j& IB' j& ^B' 0 j& 8 pB' ` j& h B' j& B' j& B' j& B' j& ( B' P j& X B' j& B' j& C' j& C' j& 0C' @ j& H (( p j& x H( j& BC' j& \C' j& nC' 0 j& 8 C' ` j& h C' j& C' j& p( j& C' j& ( ( P j& X C' j& C' ? ? O & (O O & O O & O @P & HP P & P & Q & Q HQ r PQ r XQ t `Q 8& hQ & Q pK' Q pK' Q pK' Q pK' Q pK' Q ,M R ) R 3 ) (R = ) 8R F ) HR T ) XR ` ) hR 3 ) xR k ) R 3 ) R 3 ) R 3 ) R 3 ) R ~ ) R ) R ) R ) S 3 ) S 3 ) (S ) 8S ) HS ) XS 3 ) hS ) xS 3 ) S ) S 8Y) S l) S l) S l) S l) S m) S m) S 0m) S Wm) S gm) S m) S m) T m) T m) T _s) (T is) 0T ws) 8T s) @T s) HT s) PT s) XT s) `T () T c) T g) T ) T ) T k) T o) T s) T v) T y) T }) T ) T ) T ) U ) U ) U ) U ) (U ) 0U ) 8U ) HU ) PU ) XU ) `U ) pU ) xU ) U ) U ) U ) U Ű) U ɰ) U ̰) U а) U ) U ذ) U ۰) U ߰) U ) U ) V ) V ) V ) V ) (V ) 8V ) @V ) HV ) PV ) `V ) hV ) pV ) xV ) V #) V ') V ,) V 1) V 6) V :) V ?) V D) V I) V M) V R) V W) W \) W `) W e) W j) @W ) HW 1 PW ) XW `W %) hW 2 pW 1) xW W ?) W W ]) W ^ W q) W Y W ) W ] W ) W = W ) W ſ W ) W W ) W X ) X X 1) X X K) (X 0X e) 8X * @X ) HX PX ) XX `X ) hX pX ˶) xX X ) X 5 X ) X з Z & Z & Z ` Z & Z & Z Z ' Z & [ @ [ & [ 8M' [ [ & ([ & 0[ 8[ ) & @[ / & H[ P[ J & X[ T & `[ h[ 8& p[ n & x[ [ & [ & [ [ & [ & [ [ [ [ [ [ [ [ \ & \ && \ +& \ 0& (\ ' 0\ 1& 8\ cy& @\ 1& H\ cy& P\ 1& X\ 1& `\ 1& h\ Ey& p\ 1& x\ Ey& \ 1& \ & \ 1& \ 1& \ by& \ %1& ] 91& ] ' ] 1& ] cy& ] 1& ] cy& ] 1& ] 1& ] 1& ] Ey& ^ 1& ^ Ey& ^ 1& ^ & ^ 1& (^ 1& 0^ by& 8^ %1& @^ 1& H^ ' @_ M1& H_ ' P_ 1& X_ cy& `_ 1& h_ cy& p_ 1& x_ 1& _ 1& _ Ey& _ 1& _ cy& _ 1& _ & _ 1& _ 1& _ by& _ %1& ` \1& ` ' ` 1& ` dR& ` 1& ` cy& a 1& a 1& a 1& a m1& a 1& (a :^& 0a 1& 8a & @a 1& Ha 1& Pa by& Xa %1& `b q1& hb ' pb 1& xb dR& b 1& b cy& b 1& b 1& b 1& b m1& b 1& b 1& b 1& b & b 1& b 1& b by& b %1& c 1& c ' d 1& d dR& d 1& d cy& d 1& (d 1& 0d 1& 8d 1& @d 1& Hd 1& Pd 1& Xd & `d 1& hd 1& pd by& xd %1& e 1& e ' e 1& e cy& e 1& e nh& e 1& e %3& e 1& e Tx& e 1& e 1& e by& g 1& g ' g 1& (g cy& 0g 1& 8g zh& @g 1& Hg %3& Pg 1& Xg Tx& `g 1& hg 1& pg by& h 1& h ' h 1& h cy& h 1& h Q& h 1& h 1& h 1& h Tx& h 1& h 1& i by& 0j 1& 8j ' @j 1& Hj dR& Pj 1& Xj nh& `j 1& hj 1& pj 1& xj Tx& j 1& j 1& j by& k 1& k ' k 1& k nh& k 1& k nh& k 1& k 1& l 1& l Tx& l 1& l 1& l by& Pm 2& Xm ' `m 1& hm zh& pm 1& xm zh& m 1& m %3& m 1& m Tx& m 1& m 1& m by& n 2& n ' n 1& n zh& o 1& o zh& o 1& o %3& o 1& (o Tx& 0o 1& 8o 1& @o by& Ho 1& Po ' pp .2& xp ' p 1& p zh& p 1& p Q& p 1& p 1& p 1& p Tx& p 1& p 1& p by& r @2& r ' r 1& r zh& r 1& (r W& 0r 1& 8r %3& @r 1& Hr Tx& Pr 1& Xr 1& `r by& s R2& s ' s 1& s W& s 1& s zh& s 1& s %3& s 1& s Tx& s 1& s 1& s by& u d2& (u ' 0u 1& 8u W& @u 1& Hu zh& Pu 1& Xu %3& `u 1& hu Tx& pu 1& xu 1& u by& u 1& u ' v |2& v ' v 1& v nh& v 1& v cy& v 1& v %3& v 1& v Tx& w 1& w 1& w by& @x 2& Hx ' Px 1& Xx zh& `x 1& hx cy& px 1& xx %3& x 1& x Tx& x 1& x 1& x by& y 2& y ' y 1& y W& y 1& y cy& z 1& z %3& z 1& z Tx& z 1& (z 1& 0z by& `{ 2& h{ ' p{ 1& x{ u& { 1& { cy& { 1& { s& { 1& { Tx& { 1& { 1& { by& | 2& | ' } 1& } ' } 1& } cy& } 1& (} 2& 0} 1& 8} Tx& @} 1& H} 1& P} by& ~ 2& ~ ' ~ 1& ~ dR& ~ 1& ~ cy& ~ 1& ~ 1& ~ 1& ~ & ~ 2& ~ 1& ~ by& 2& ' 1& ( nh& 0 1& 8 cy& @ 1& H 1& P 1& X & ` 2& h 1& p by& 3& ' 1& zh& 1& ȁ cy& Ё 1& 1& 1& 聎 & 2& 1& by& 0 3& 8 ' @ 1& H W& P 1& X cy& ` 1& h $3& p 1& x & 2& 1& by& )3& Ȅ ' Є 1& W& 1& 脎 cy& 1& $3& 1& & 2& 1& by& ( 1& 0 ' P @3& X ' ` 1& h u& p 1& x cy& 1& s& 1& & 2& 1& by& Q3& 臎 ' 1& cy& 1& zh& a3& s& 1& ( & 0 2& 8 1& @ by& p d3& x ' 1& cy& 1& W& a3& s& 1& & 2& ȉ 1& Љ by& t3& ' 1& cy& 1& ( u& 0 a3& 8 2& @ 1& H & P 2& X 1& ` by& 3& ' 1& cy& 1& ' a3& Ȍ Ơ& Ќ 1& ، & 2& 茎 1& by& 3& ( ' 0 1& 8 dR& @ 1& H nh& P 1& X %3& ` 1& h & p 2& x 1& by& 3& ' 1& ȏ zh& Џ 1& ؏ zh& 1& 菎 %3& 1& & 2& 1& by& @ 3& H ' P 1& X zh& ` 1& h Q& p 1& x %3& 1& & 2& 1& by& В 3& ؒ ' 1& 蒎 zh& 1& W& 1& %3& 1& & 2& ( 1& 0 by& ` 3& h ' p 1& x zh& 1& W& 1& %3& 1& & 2& 1& by& Ȕ 1& Д ' 3& ' 1& nh& 1& nh& 1& ( %3& 0 1& 8 & @ 2& H 1& P by& 4& ' 1& N& 1& N& 1& %3& 1& ȗ & З 2& ؗ 1& by& 4& ' 1& ( dR& 0 1& 8 u& @ 1& H %3& P 1& X & ` 2& h 1& p by& "4& ' 1& cy& 1& Ț ' К 1& ؚ 34& 1& 蚎 & 2& 1& by& 0 84& 8 ' @ 1& H cy& P 1& X ' ` a3& h ' p 1& x & 2& 1& by& C4& ȝ ' Н 1& ؝ cy& 1& 蝎 ' a3& ' 1& & 2& 1& by& ( 1& 0 ' P T4& X ' ` 1& h dR& p 1& x u& a3& f4& 1& & 2& 1& by& ࠎ j4& 蠎 ' 1& dR& 1& u& a3& f4& 1& ( & 0 2& 8 1& @ by& H 1& P ' ,& `M' l& M' & M' Ȣ & Т M' ࢎ & 袎 8N' ܒ& ( xN' 8 & @ N' P & X & o& N' & !& #!& 3!& ȣ P!& У N' ࣎ b!& 裎 O' (& ( 8O' 8 (& @ `O' P & X k!& !& O' >& O' !& O' Ȥ I& Ф O' ऎ !& 褎 P' & k!& @ !& H @P' X 5& ` hP' p !& x P' & P' !& ȥ P' إ !& ॎ Q' & !& !& !& & ( !& ` "& h (Q' x ң& PQ' #"& Q' & 2"& ' 覎 O"& & l"& @ S & H PV' X && ` xV' p && x V' .H& .H& w_& خ .H& எ .H& 讎 _& 9_& 9_& w_& ( .H& 0 .H& 8 _& P 9_& X M& ` }_& x 9_& >_& P_& 9_& 9_& |_& ȯ .H& Я >_& د [_& .H& >_& P_& .H& >_& ( G_& @ .H& H M& P ~& h .H& p M& x }_& .H& .H& w_& 9_& >_& Ȱ P_& ఎ 9_& 谎 9_& w_& 9_& 9_& |_& 0 .H& 8 >_& @ P_& X .H& ` >_& h G_& .H& M& ~& .H& M& }_& б .H& ر .H& _& .H& .H& w_& 8 .H& @ .H& H _& ` 9_& h 9_& p w_& .H& .H& _& 9_& M& }_& ز 9_& ಎ >_& 貎 P_& 9_& 9_& |_& ( .H& 0 >_& 8 P_& P .H& X >_& ` G_& x .H& M& ~& .H& M& }_& ȳ .H& г >_& س [_& @ ` mH& 8' л ؇' N& ' 0 (' P P' p _& Aa& a& м Tb& b& ' 0 -c& P c& p Х' Ȧ' ff& н f& ki& ' 0 k& P & p p' m& o& о o& p& {r& 0 s& P ;u& p gu& u& v& п v& z& z& 0 ){& P U{& p {& {& {& z|& ]}& ~& 0 ~& P & p & \& & B& ,& O& 0 & P G& p & & & & & `Î +& hÎ 2& pÎ K& Î V& Î k& Î V& Ď & Ď & (Ď & `Ď & Ď & Ď & Ď NJ& Ď ܊& Ď & Ď ' Ŏ 6& @Ŏ 8~' HŎ `Ŏ `Ŏ =& hŎ c=& pŎ v=& xŎ M Ŏ =& Ŏ X~' Ŏ v=& Ŏ A Ŏ =& Ŏ ~' Ŏ v=& Ŏ M Ŏ =& Ŏ ~' Ŏ =& Ŏ `% Ŏ =& Ŏ =& Ŏ Ǝ =& Ǝ ~' Ǝ @L @Ǝ E& HƎ `Ǝ `Ǝ E& hƎ f^& xƎ Ǝ 'E& Ǝ & Ǝ Ǝ 6E& Ǝ ?E& Ǝ Ǝ r& Ǝ mH& Ǝ ǎ J& (ǎ 8' 8ǎ `ǎ K& hǎ ǎ ǎ $K& ǎ K& ǎ v=& ǎ 0 ǎ `' ǎ ǎ ǎ ' ǎ `' ǎ v=& ǎ Ȏ K& (Ȏ ؇' 8Ȏ `Ȏ L& hȎ Ȏ Ȏ L& Ȏ ' Ȏ v=& Ȏ Ȏ L& Ȏ (' Ȏ v=& Ȏ Ȏ L& Ȏ X' Ȏ v=& Ȏ Ɏ ' Ɏ Ɏ Ɏ M& (Ɏ ' 0Ɏ v=& 8Ɏ @ `Ɏ ' hɎ N& xɎ P Ɏ N& Ɏ ' Ɏ Ɏ :O& Ɏ (' Ɏ p ʎ GO& (ʎ P' 8ʎ `ʎ T& hʎ ʎ ʎ U& ʎ ' ʎ - ʎ =& ʎ U& ʎ `0 ʎ -U& ʎ =U& ʎ @$ ʎ MU& ʎ VU& ʎ " ˎ iU& ˎ rU& ˎ ˎ U& (ˎ U& 8ˎ p `ˎ yZ& hˎ ˎ ˎ Z& ˎ Z& ˎ 6 ˎ Z& ˎ Z& ˎ `= ˎ & ˎ ' ˎ Z& ˎ 3 ˎ Z& ˎ ' ˎ `< ̎ Z& ̎ ' ̎ 7 @̎ Z& ͎ `P X͎ [& Ύ P (Ύ O 0Ύ @O pΎ [& 8ώ N ώ -[& PЎ N Ў G[& hю N ю T[& ю h[& Ҏ M Ҏ k[& Ҏ [& ӎ `M ӎ [& ӎ [& Ԏ M Վ [& Վ [& Վ M ֎ [& (֎ [& ֎ M 0 [& @ [& M `؎ M h؎ `M p؎ M ؎ `P ؎ P ؎ O ؎ @O ؎ N ؎ N ؎ N ؎ R ؎ @R ؎ Q ؎ Q ؎ Q ؎ P َ G_& (َ P_& @َ [_& pَ }_& َ ~& َ o_& َ }_& َ ~& َ o_& ڎ w_& (ڎ |_& @ڎ _& pڎ w_& ڎ _& ڎ _& ڎ _& ڎ _& ڎ 0Y ێ Ua& ێ Aa& ێ P^ @ێ b& Hێ a& Xێ i ێ pb& ێ Tb& ێ ێ b& ێ b& ێ c& ' p @ Jc& H -c& X 0 c& c& p d& td& zd& d& ݎ d& ݎ d& ݎ d& ݎ ݎ d& (ݎ d& 0ݎ d& 8ݎ @ݎ d& Hݎ d& Pݎ d& Xݎ ݎ Ie& ݎ Х' ݎ ݎ ze& ݎ Ȧ' ݎ 0 ގ yf& ގ ff& ގ @ގ f& Hގ f& Xގ @ ގ i& ގ ki& ގ ގ i& ގ ' ގ ߎ k& ߎ k& ߎ @ߎ & Hߎ & Xߎ @ ߎ m& ߎ p' ߎ ߎ m& ߎ m& ߎ @ o& o& 0= @ o& H o& X 9 Go& p& 7 r& {r& 0? ' s& J @ 3t& H ` ` ;t& h Nt& x Q at& ot& @X }t& t& O t& t& N t& t& K Qu& ( ;u& 8 a ` wu& h gu& x a u& u& `` /v& v& c v& ( v& 8 Ph ` z& h z& x x {& z& P :{& ){& ` U{& ( U{& 8 ` {& h {& x @ {& {& |& {& P z|& ( z|& 8 ` ]}& h ]}& x ~& ~& ~& ~& & ( & 8 ` & h & x k& \& z& & ' & p & ( & 0 & 8 ` 5& h & x ` R& B& H& ,& t& ( @ @ & H & P H' X @ ` & h & p p' x ^& O& & & T& ( G& 8 ` & h & x & & & p" & # ÿ) 8% ̿) & տ) ( ( 0 ݿ) 8 x( @ '& H `Î ` & h Ď @T T T 0X Y pZ & ( ph 0 0b @ H P ` X ` ` pi h @` & ph 0b ` ` ` @` @ !& H ph P 0b ` h p p ` x ` @` & ph 0b Д ` ` @` ` & h ph p 0b 0 ` ` @` %& ph 0b P ` ( ` 0 @c 8 @` .& ph 0b ` ` } @` 6& ph 0b 8 @ ` H ` P y X @` =& ph 0b @ ` ` u @` 0 E& 8 ph @ 0b X ` ` h ` p q x @` M& ph 0b ` ` m @` ` & h && p S & ,& 3& S & 9& S & S & @& I& O& & V& S & H' [& S & &$& ( c& 0 V& ` P h p x x& 8 & p (& & & 0 & & & & @ & X & p & & & & 5& <9& & & 0 & H && ` & x & & & & & ' & 0 & H #& ` 0& x ;& 4& & & J& V& `& 8 s& P k& h +A& q& ~& & & & n& n& 0 kD& H & ` S& x s& ' *A' & & & [& & 8 & P & h f& & & Y9& & & && & ( & @ H' X & p & & :& & ;-' 8 & ` & & & & ( 8 0 H p 8& 0' 0' 6' & h H& & ( @ & & j& 0 & H ` & & @ p& h & & ( P H P h 0 p ` & (O& & |& & & ۜ& & Þ& S5' & ( p 0 Ǟ& 8 @ Ξ& H P Ԟ& X ` nU& h p ۞& x & 5& |& P & & `& & & P & 0 & 0 & ( 0 0 & 8 0 @ & H 0 P & X 0 ` & h 0 p & x 0 & 0 & 0 !& 0 $& 0 ' 0 (& 0 ,& 0 1& 0 5& 0 :& 0 >& ( 0 0 B& 8 0 @ F& H 0 P K& X 0 ` O& h 0 p T& x 0 X& 0 \& 0 `& 0 d& 0 g& 0 j& 0 n& 0 r& 0 x& 0 {& 0 ~& ( 0 _& 8 @ & H P & X ` & h p & x & & & & & & & & & ß& ɟ& ( 0 && 8 @ ϟ& H P \& X ` & h p Y& x & ՟& ۟& & & & & & x& 3& 8& ( 0 & 8 @ :& H P & X ` & h p & x & & & %& ,& 2& 9& B& G& 0 & N& ( 0 R& 8 @ X& H X ` @ x ` ' " 0 8 @ @ X P ` x ` 0( ( (' +& m& @ Z& ( @ :& H ?& P `M X K ` M h L M 3& b& L K M L @L y' y' y' & ( 0 P 8 P @ 0 P ` & h p p x ` & z & z )& ( y @ p ` 5& h Py Q& x g& px P y& ( 0x @ P ` & h w Е & pw p & w P & ( u @ Д ` & h Pu P & t Г & `t P & ( @ ` & h v & v /& v ` )& ( v @ ` C& h @v =& @v ` J& r ^& ( s @ ` q& h & p @ & & ( @ 0 H ` & h p P & p & p & ( `r @ @ ` & h q p r & q & @q & ( q @ ` & h P & %& @ %& ( @ ` :& h p p x ~ P I& `p @~ N& 0 } Z& ( ` 8 @ H ` & h 0 x& p P h& o p p& ( o @ P} H ` & p x & & ?& R& D& H& L& Q& V& Z& b& i& q& w& H ' P ' X ' h ' p ' x ' ' ' ' ' ' ' @ @ ph$ H d$ P `d$ X c$ ` Pi$ h _$ p p^$ x f$ d$ P_$ _$ ^$ 3& b& $ $ p$ p$ м$ p$ $ @$ $ $ 5' 5' ! 5' ( 0 !' 8 ` 5' h 5' p 5' x }5' q5' p% r% po% 5' pq% p% o% ! 5' ! r% (! s% 8! 0p% @! 5' H! 5' P! 5' X! 5' `! 6' ! 6' ! 6' ! )6' ! 26' ! ;6' ! D6' ! N6' ! X6' " b6' " l6' (" v6' 8" 6' H" 6' X" 6' h" 6' x" 6' " 6' " 6' " 6' " 6' " 6' " 6' " 6' " 6' # 6' # 7' (# 7' 8# 7' H# 7' X# &7' h# .7' x# 67' # >7' # F7' # N7' # V7' # ^7' # f7' # n7' # v7' $ ~7' $ 7' ($ 7' 8$ & H$ 7' X$ 7' h$ ' x$ 7' $ 7' $ 7' $ 7' $ 7' $ 7' $ 7' $ 7' $ 7' % 7' % 8' (% 8' 8% 8' H% 8' X% w& h% 8' x% 8' % "8' % 8' % #& % (8' % ,8' % 38' % & % !' & ;8' & G8' (& & 8& S8' H& Y8' X& c8' h& j8' x& q8' & v8' & {8' & 8' & 8' & 8' & 8' & ' & 8' ' 8' ' 8' (' 8' 8' 8' H' 8' X' 8' h' 8' x' 9' ' 9' ' $9' ' 69' ' I9' ' ^9' ' r9' ' 9' ' 9' ( 9' ( 9' (( 9' 8( :' h( :' x( #:' ( 6:' ( C:' ( O:' ( [:' ( l:' ( w:' ( & ( 5' ) <' ) :' () :' 8) :' H) :' X) :' h) :' x) :' ) :' ) :' ) :' ) :' ) :' ) :' ) :' ) :' * :' * ;' (* ;' 8* ;' H* %;' X* 3;' h* E;' x* W;' * k;' * };' * ;' * ;' * ;' * ;' * ;' * ;' + ;' + ;' (+ ;' 8+ ;' H+ <' X+ <' h+ <' x+ <' + *<' + 1<' + 9<' + @<' + F<' + M<' + V<' + ]<' , e<' , l<' (, s<' 8, |<' , =' , & , ' , ( , ' , ' , ' , ' (- ' 0- ' 8- ' H- ' P- ' X- ' - *' - (' - . . @' . P% . ( . V& (. % 8. ( @. D& H. % X. ( `. @' h. % x. H( . @' . 0% . A' . A' . % . p( . 2A' . % . ( 1 & 1 x;& 1 & (1 & @1 5& P1 s& X1 m& 1 v& 1 L& 1 & 1 & 1 :& 1 8& 1 & 1 9& 1 9& 1 z& 1 g& 1 & 2 9& 2 :& 2 8& 2 9& 2 9& (2 & 02 L& 82 & @2 n& H2 z& P2 & X2 & `2 #& h2 & p2 +9& x2 & 2 m& 2 QD' 2 9& 2 _D' 2 9& 2 n& 2 G' 2 & 2 gD' (3 .H& 03 (' @3 3 3 U& 3 % 3 nD' 3 G' 3 % (4 `5 p4 / 4 5 4 % `5 % x5 % 5 L& 5 p% 5 ( 5 ~D& 5 % 5 %G' 6 * & 6 % 6 0( 6 @G' (6 % 86 P( @6 (O& H6 @% X6 x( `6 KG' h6 % x6 WG' 6 gG' 6 `% P7 `/ 7 @8 7 % @8 ~D& H8 `% X8 ( 8 rG' 8 p% 8 : 09 / 9 % : % 8: % : G' : % : < 0; / ; % < @% 8< % < G' < % 0= / p= > > G' @> G' H> G' h> G' p> G' > G' > G' > G' > H' > H' > H' ? #H' ? ,H' 0? =H' 8? 9& X? MH' `? ZH' ? eH' ? :& ? oH' ? zH' ? H' ? H' ? H' X@ H' @ `% @ % @ / 0A A A G' B G' B G' (B G' 0B G' PB G' XB G' xB G' B H' B H' B H' B #H' B ,H' B =H' B 9& C MH' C ZH' @C eH' HC :& hC oH' C H' C % PD 0 D @E @E G' `E G' hE G' E G' E G' E G' E G' E G' E H' F H' F H' (F #H' 0F ,H' PF =H' XF 9& xF MH' F ZH' F eH' F n& F G' F G' F G' 8G H' xG % G 00 H H H G' H G' H G' I G' I G' 0I G' 8I G' XI G' `I H' I H' I H' I #H' I ,H' I =H' I 9& I MH' J ZH' J eH' (J & HJ #H' PJ H' pJ H' J H' J @% PK P0 K @L @L G' `L G' hL G' L G' L G' L G' L G' L G' L H' M H' M H' (M #H' 0M ,H' PM =H' XM 9& xM MH' M ZH' M eH' M :& M oH' M Y9& M & M & N #H' N 3H' @N =H' N I' N 0% 0O p0 pO P P G' @P G' HP G' hP G' pP G' P G' P G' P G' P H' P H' P H' Q #H' Q ,H' 0Q =H' 8Q 9& XQ MH' `Q ZH' Q eH' Q :& Q oH' Q n& Q G' Q G' Q G' R n& R n& xR #I' R % S 0 PS T T G' T G' (T G' HT G' PT G' pT G' xT G' T G' T H' T H' T H' T #H' T ,H' U =H' U 9& 8U MH' @U ZH' `U eH' hU :& U oH' U n& U G' U 9I' U 3I' U G' V G' V DI' (V >I' 0V Y9& PV & V II' V p% 0W 0 pW X X G' @X G' HX G' hX G' pX G' X G' X G' X G' X H' X H' X H' Y #H' Y ,H' 0Y =H' 8Y 9& XY MH' `Y ZH' Y eH' Y :& Y oH' Y _I' Y YI' Y n& Y G' Z G' Z G' (Z 0' HZ dI' PZ RU& pZ uI' xZ I' Z I' Z I' Z I' 0č @ @ č ō ō ~ pƍ ( 0Ǎ 1 Ǎ 1 1 Pȍ ȍ ɍ ɍ # 0ʍ # ʍ # ʍ # Pˍ # ˍ # ( ̍ # X p̍ # \ ̍ # ` 0͍ # P ͍ # Q ͍ # R P # S # T ύ # d pύ # e ύ # f 0Ѝ # Ѝ # h Ѝ # l Pэ # p э # ҍ # ҍ # # pҍ `ԍ hԍ w xԍ . ԍ ԍ d ܍ d ԍ ܍ ԍ ܍ ԍ ܍ ԍ h ܍ h ԍ ܍ ԍ ܍ ԍ ܍ Ս j ݍ j Ս ݍ Ս ݍ Ս ݍ Ս (Ս 0Ս 8Ս @Ս HՍ PՍ XՍ `Ս hՍ R pՍ T xՍ Y Ս Ս Ս ٍ ! @ٍ # `ٍ % ٍ + ٍ / ٍ 4 ٍ ٍ ڍ ڍ ( @ڍ `ڍ ڍ ڍ ڍ ڍ ڍ ڍ h ڍ ڍ @ۍ Hۍ Pۍ Xۍ ۍ ۍ Q ۍ S ۍ ۍ ۍ ۍ ܍ ݍ (ݍ 0ݍ Hݍ U ݍ ݍ ݍ . ݍ ) ލ ލ @ލ pލ t ލ ލ ލ ލ n ލ ߍ ߍ ` 0ߍ @ߍ `ߍ pߍ g ߍ ߍ K ߍ P v ` U ` v @ { P ' p @ 0 ` L 5 9 I 0 P # ^ w ; @ 6 p 0 @ ` p j u S ` S r " / H 0 8 @ H K P z z X F ` h p x K e e O 9 V g ? 7 E O h ( t 0 8 @ 5 H B P 6 X ` h % p x H ` x @ ` 8 P h L o o a ( a ( 0 a ( u 8 u T ( ( ( 0 8 < h < @ H ? P X ` h 0 0 p x 7 , 4 i L * k k j ; ( 0 ( 8 S @ r H c P * X ` _ h p Y x : 8 < 3 " ( ( ( 0 ( 0 8 H @ u H ] P G X | | ` h P p x q P q C Y | b b ( 0 w 8 @ H M P X e ` 9 h ( p x c @ { [ & e f J / H ` h 6 9 ( [ 0 4 8 @ H P C X ` ( h p x I ; a S { 6 آ * ` 0 H e } أ 0 3 H F ؤ l P j h ( Х < 襎 w p z x P h H ` h p x : E ȹ D й ع ๎ , 蹎 H ( 0 8 @ @ ( H 2 P X ` x h 3 p x G 8 j Ⱥ к غ / ຎ = 躎 . p X R ( ( + 0 7 8 @ H P 8 X ` h # p x O ػ 4 8 X x G ؼ 8 ` X x ؽ b 8 C X x i ؾ % 8 X x % ؿ F 8 X x @ 8 T X x = < \ Q 8 a X x { 8 = Î (Î L 0Î 8Î @Î o HÎ xÎ Î Î y Ď , 8Ď hĎ S Ď Ď Ď i _ % { Y S P h 7 , % ( c @ v X A p L N 4 @ X p z } v ` 0 x H K h . w @ x ` l < 6 l N B ( 7 0 H 8 l @ H P m X ` q h p m x f * 5 9 ! 4 . q ( 0 8 @ H P X > ` h p x ^ d | ( S 0 8 @ H t P - X o ` h ) p x - % ` ( ( G 0 & 8 @ H P X ` h { p X x s \ O L 5 - A * ( 0 8 @ H P X ~ ` h p x v ! S # $ ( 0 H 8 % @ H & P X ' ` h p ' x ( p E ~ 0 C B q ) * + ( , 0 8 - @ H P X ` h p r x . W / 0 \ I 1 2 6 D ( 0 3 8 4 @ H 5 P 6 X ` h p 7 x % 8 9 | : : ; 3 < = f > V | ? 0 ( @ 0 8 o @ E H P A X B ` h p ] x C D + T ~ E F G T H I ( : 0 8 @ J H P X ` ` j h Z p L x < M 1 ^ d s X . e N O h P ! Q K ( R 0 8 @ H P R X + ` h S p C x k 4 n b T U _ ? f V ( C 0 8 @ H W P X ` h p x X Q 0 o i 6 Y Z ( 0 8 @ [ H \ P X ` ] h ^ p x N ] f _ ` x a O r ( 0 b 8 n @ c H # P d X ` h X p x x e f # u l g h i j = & ( 0 8 @ H k P l X . ` h p m x B n ! i 6 o _ l L ; 2 x t p $ q ( o 0 8 @ r H P d X ` h p r x s t j / u ) 1 K ^ v t w x k ( y 0 8 9 @ z H P q X { ` h p 5 x | } q ~ f = } A ( 0 8 @ g H P X ` h p Q x \ P } ( 0 8 @ H D P X h ` h p x Y - J I ( { 0 8 @ , H P X ` h p x s / ~ 1 _ - - ( T 0 t 8 @ H P X ` h p $ x | R % * A ( 0 8 @ H P p X ` V h p x D ! & ( H 0 8 @ H P X ` l h s p x F W h c ? ( 0 : 8 I @ G H P X ` h h p x y h R @ Y ] ( 0 " 8 @ H P X J ` h p ^ x \ C 7 ( 0 8 @ H ~ P + X ` h V p x G C ) s ` o } E a = \ M ( * ( w 0 W 8 @ H P X ` b h g p x " 6 y F a o 1 , ( R 0 8 @ @ H P X t ` h p x s & i n Z ( t 0 O 8 @ H P X ` h p x ! { ( 0 8 @ d H v P X ` P h p b x } u . ( 0 8 @ / H P X ` h p N x _ a $ F ( j 0 H 8 & @ H W P 3 X y ` h 0 p x ^ D " G 5 t ( 0 8 B @ H P X ` h p x X $ M ( z 0 8 X @ s H P > X k ` h p , x n N | 1 ] ( 0 P 8 @ H a P X ` b h ; p x o c D ( 0 8 U @ H P X ^ ` 2 h # p x > v D c _ : 2 ( 0 8 \ @ 6 H P X ` h p x O ] T ! { < # P p G l ( 0 8 @ H P | X ` h - p w x , ! R B " # $ ( ^ 0 8 @ . H % P & X ` Y h p > x S a i ' E 1 7 } Q Y 8 ( 0 8 u @ H P g X K ` ( h p ) x j 2 g k R $ ^ Y ~ X + a ( , 0 i 8 H @ H a P - X . ` h / p 0 x 1 X 2 3 4 ' z 5 6 X ( 7 0 8 @ > H P X ` h 4 p b x 8 9 3 R : ; < O = = ( > 0 8 @ ? H 4 P @ X % ` h p x 1 A B Z ( > 0 8 @ C H P X ` h D p E x 7 U F G H I J K L M N e E - ( 0 O 8 @ H P P X $ ` h p V x Q s R # S T \ U V W ( l 0 X 8 @ H d P { X ` h O p x Z & [ \ ] ^ _ F ` j G j a ( b 0 e 8 c @ H P d X y ` e h ; p x ` ) 8 f " 2 v l ? K ( g 0 8 @ h H i P + X j ` h p F x p w Q k l m n o p | q r ( s 0 u 8 @ H P y X n ` x h p t x u v w o [ W x y z ! o ! ! Y ! . ! (! 0! { 8! / @! d H! P! & X! `! h! p! - x! ! ! ! y ! | ! } ! ! ! ~ ! ! ! ! ! ! ! ! W " " " y " & " - (" } 0" I 8" + @" u H" P" ! X" `" h" p" x" " " " " " " " u " e " " " " " " " W " # # # # # (# 0# 8# @# _ H# P# 7 X# `# e h# p# c x# # # # # | # # # # R # # # # c # # # @ # = $ $ $ Q $ $ w ($ 0$ 8$ @$ H$ " P$ X$ `$ v h$ p$ x$ $ $ $ $ p $ $ $ $ $ $ $ i $ ^ $ $ [ $ $ _ % % % Z % % (% 0% 8% @% v H% M P% X% `% h% p% b x% c % % % % % Q % % 3 % % W % " % % % q % % q % & ) & \ & V & & { (& 0& S 8& @& H& U P& X& H `& g h& p& x& & & & & & & & & & & > & & & & @ & & ' ' G ' ' b ' M (' Y 0' k 8' p @' H' P' X' A `' h' p' x' ' ' ' ' ' q ' ' ' ' V ' ' M ' ' ' ' N ' p ( 5 ( ( $ ( ( (( 0( 8( # @( 9 H( P( X( + `( h( 0 p( x( ' ( z ( < ( ( ' ( ( W ( ( ( ) ( ( ( ( y ( ( ( ) ) ) d ) ) () 0) 8) @) s H) D P) X) `) h) M p) 8 x) W ) ) ) ) ) ) Z ) ) ) 2 ) ) ) ) ) m ) ) * * * * * (* F 0* D 8* @* H* P* X* + `* h* p* x* * * < * * * * * * * * * * * * * m * + n + + + + (+ 9 0+ 8+ E @+ H+ P+ X+ N `+ 2 h+ # p+ x+ + z + + + + + B + + B + + e + + + + + + , , , , , (, Y 0, l 8, 8 @, H, Q P, f X, `, h, p, ~ x, [ , , , , , , , , , # , , , 5 , , , , - - - - - (- 8 0- 8- @- H- P- X- `- h- | p- x- - O - - ( - - - n - - u - - - X - - - - p - . . , . . . (. 0. 8. v @. H. P. X. `. h. p. x. . . J . . . . . . M . . b . . . . 5 . . / / / g / / (/ 0/ ~ 8/ @/ H/ P/ X/ `/ l h/ p/ x/ / / / / / / / / / / / / / J / / / / ; 0 K 0 y 0 0 0 u (0 00 80 @0 H0 P0 X0 `0 h0 W p0 x0 0 P 0 0 0 0 0 0 0 ; 0 @ 0 0 0 0 0 0 0 1 ) 1 9 1 1 1 (1 01 81 @1 H1 P1 X1 `1 h1 6 p1 " x1 1 1 1 1 R 1 1 1 P 1 1 1 1 1 1 ) 1 / 1 1 2 2 2 2 ; 2 (2 02 82 @2 H2 P2 X2 `2 h2 p2 x2 y 2 2 B 2 U 2 2 2 2 2 C 2 2 2 + 2 L 2 2 D 2 2 3 3 3 3 3 = (3 03 83 @3 H3 P3 [ X3 `3 h3 ? p3 x3 3 3 D 3 3 3 3 3 / 3 3 3 3 3 3 3 3 3 4 4 4 4 7 4 (4 04 84 @4 H4 P4 X4 `4 D h4 2 p4 x4 4 4 4 4 4 4 _ 4 4 N 4 4 r 4 4 4 4 4 N 4 & 5 5 r 5 5 2 5 Q (5 05 * 85 ] @5 H5 l P5 X5 3 `5 z h5 = p5 x5 x 5 5 5 5 5 j 5 5 5 U 5 5 5 5 5 5 5 5 6 ( 6 6 ] 6 6 (6 06 86 @6 H6 A P6 9 X6 `6 r h6 p6 x6 6 ] 6 6 6 S 6 d 6 6 6 6 6 ? 6 6 6 6 6 6 7 ( 7 1 7 7 7 s (7 07 87 @7 H7 ! P7 " X7 U `7 # h7 p7 x7 = 7 7 Z 7 m 7 7 k 7 $ 7 7 % 7 k 7 7 n 7 a 7 7 7 7 8 o 8 8 8 @ 8 (8 N 08 ' 88 % @8 H8 P8 X8 `8 h8 p8 x8 8 8 ( 8 8 8 8 c 8 ) 8 8 5 8 * 8 + 8 8 , 8 8 X 8 9 9 } 9 3 9 - 9 (9 09 . 89 k @9 H9 s P9 X9 0 `9 1 h9 p9 Z x9 9 2 9 d 9 9 9 ' 9 9 n 9 9 3 9 9 9 9 > 9 4 9 4 9 m : 5 : : : y : 7 (: w 0: 8 8: @: H: P: X: < `: ^ h: V p: " x: : W : : : : : ~ : : ; : < : : 0 : = : 4 : : k : : ; ; ; ; z ; > (; ? 0; 8; @; @ H; P; A X; A `; B h; p; Z x; { ; H ; ; ; [ ; ; n ; D ; E ; ; F ; ; ? ; ; ; ; G < H < < < ~ < J (< 0< B 8< z @< K H< P< X< `< h< L p< = x< ' < < L < < M < N < < , < O < O < P < < 2 < e < < T < = Q = R = = = S (= h 0= 8= @= H= | P= X= T `= h= U p= V x= W = ( = = = X = = = = f = r = = Y = = = Z = k = > > > > > (> ] 0> 8> 9 @> H> : P> [ X> c `> h> p> z x> > \ > > > > J > ] > > - > HHIJ HtH 5O %O @ %O h %O h %O h %O h %O h %O h %O h %O h p%O h `%O h P%zO h @%rO h 0%jO h %bO h %ZO h %RO h %JO h %BO h %:O h %2O h %*O h %"O h %O h %O h p% O h `%O h P%N h @%N h 0%N h %N h %N h %N h %N h %N h! %N h" %N h# %N h$ %N h% %N h& %N h' p%N h( `%N h) P%zN h* @%rN h+ 0%jN h, %bN h- %ZN h. %RN h/ %JN h0 %BN h1 %:N h2 %2N h3 %*N h4 %"N h5 %N h6 %N h7 p% N h8 `%N h9 P%M h: @%M h; 0%M h< %M h= %M h> %M h? %M h@ %M hA %M hB %M hC %M hD %M hE %M hF %M hG p%M hH `%M hI P%zM hJ @%rM hK 0%jM hL %bM hM %ZM hN %RM hO %JM hP %BM hQ %:M hR %2M hS %*M hT %"M hU %M hV %M hW p% M hX `%M hY P%L hZ @%L h[ 0%L h\ %L h] %L h^ %L h_ %L h` %L ha %L hb %L hc %L hd %L he %L hf %L hg p%L hh `%L hi P%zL hj @%rL hk 0%jL hl %bL hm %ZL hn %RL ho %JL hp %BL hq %:L hr %2L hs %*L ht %"L hu %L hv %L hw p% L hx `%L hy P%K hz @%K h{ 0%K h| %K h} %K h~ %K h %K h %K h %K h %K h %K h %K h %K h %K h p%K h `%K h P%zK h @%rK h 0%jK h %bK h %ZK h %RK h %JK h %BK h %:K h %2K h %*K h %"K h %K h %K h p% K h `%K h P%J h @%J h 0%J h %J h %J h %J h %J h %J h %J h %J h %J h %J h %J h %J h p%J h `%J h P%zJ h @%rJ h 0%jJ h %bJ h %ZJ h %RJ h %JJ h %BJ h %:J h %2J h %*J h %"J h %J h %J h p% J h `%J h P%I h @%I h 0%I h %I h %I h %I h %I h %I h %I h %I h %I h %I h %I h %I h p%I h `%I h P%zI h @%rI h 0%jI h %bI h %ZI h %RI h %JI h %BI h %:I h %2I h %*I h %"I h %I h %I h p% I h `%I h P%H h @%H h 0%H h %H h %H h %H h %H h %H h %H h %H h %H h %H h %H h %H h p%H h `%H h P%zH h @%rH h 0%jH h %bH h %ZH h %RH h %JH h %BH h %:H h %2H h %*H h %"H h %H h %H h p% H h `%H h P%G h @%G h 0%G h %G h %G h %G h %G h %G h %G h %G h %G h %G h %G h %G h p%G h `%G h P%zG h @%rG h 0%jG h %bG h %ZG h %RG h %JG h %BG h %:G h %2G h %*G h %"G h %G h %G h p% G h `%G h P%F h @%F h 0%F h %F h %F h %F h %F h %F h! %F h" %F h# %F h$ %F h% %F h& %F h' p%F h( `%F h) P%zF h* @%rF h+ 0%jF h, %bF h- %ZF h. %RF h/ %JF h0 %BF h1 %:F h2 %2F h3 %*F h4 %"F h5 %F h6 %F h7 p% F h8 `%F h9 P%E h: @%E h; 0%E h< %E h= %E h> %E h? %E h@ %E hA %E hB %E hC %E hD %E hE %E hF %E hG p%E hH `%E hI P%zE hJ @%rE hK 0%jE hL %bE hM %ZE hN %RE hO %JE hP %BE hQ %:E hR %2E hS %*E hT %"E hU %E hV %E hW p% E hX `%E hY P%D hZ @%D h[ 0%D h\ %D h] %D h^ %D h_ %D h` %D ha %D hb %D hc %D hd %D he %D hf %D hg p%D hh `%D hi P%zD hj @%rD hk 0%jD hl %bD hm %ZD hn %RD ho %JD hp %BD hq %:D hr %2D hs %*D ht %"D hu %D hv %D hw p% D hx `%D hy P%C hz @%C h{ 0%C h| %C h} %C h~ %C h %C h %C h %C h %C h %C h %C h %C h %C h p%C h `%C h P%zC h @%rC h 0%jC h %bC h %ZC h %RC h %JC h %BC h %:C h %2C h %*C h %"C h %C h %C h p% C h `%C h P%B h @%B h 0%B h %B h %B h %B h %B h %B h %B h %B h %B h %B h %B h %B h p%B h `%B h P%zB h @%rB h 0%jB h %bB h %ZB h %RB h %JB h %BB h %:B h %2B h %*B h %"B h %B h %B h p% B h `%B h P%A h @%A h 0%A h %A h %A h %A h %A h %A h %A h %A h %A h %A h %A h %A h p%A h `%A h P%zA h @%rA h 0%jA h %bA h %ZA h %RA h %JA h %BA h %:A h %2A h %*A h %"A h %A h %A h p% A h `%A h P%@ h @%@ h 0%@ h %@ h %@ h %@ h %@ h %@ h %@ h %@ h %@ h %@ h %@ h %@ h p%@ h `%@ h P%z@ h @%r@ h 0%j@ h %b@ h %Z@ h %R@ h %J@ h %B@ h %:@ h %2@ h %*@ h %"@ h %@ h %@ h p% @ h `%@ h P%? h @%? h 0%? h %? h %? h %? h %? h %? h %? h %? h %? h %? h %? h %? h p%? h `%? h P%z? h @%r? h 0%j? h %b? h %Z? h %R? h %J? h %B? h %:? h %2? h %*? h %"? h %? h %? h p% ? h `%? h P%> h @%> h 0%> h %> h %> h %> h %> h %> h! %> h" %> h# %> h$ %> h% %> h& %> h' p%> h( `%> h) P%z> h* @%r> h+ 0%j> h, %b> h- %Z> h. %R> h/ %J> h0 %B> h1 %:> h2 %2> h3 %*> h4 %"> h5 %> h6 %> h7 p% > h8 `%> h9 P%= h: @%= h; 0%= h< %= h= %= h> %= h? %= h@ %= hA %= hB %= hC %= hD %= hE %= hF %= hG p%= hH `%= hI P%z= hJ @%r= hK 0%j= hL %b= hM %Z= hN %R= hO %J= hP %B= hQ %:= hR %2= hS %*= hT %"= hU %= hV %= hW p% = hX `%= hY P%< hZ @%< h[ 0%< h\ %< h] %< h^ %< h_ %< h` %< ha %< hb %< hc %< hd %< he %< hf %< hg p%< hh `%< hi P%z< hj @%r< hk 0%j< hl %b< hm %Z< hn %R< ho %J< hp %B< hq %:< hr %2< hs %*< ht %"< hu %< hv %< hw p% < hx `%< hy P%; hz @%; h{ 0%; h| %; h} %; h~ %; h %; h %; h %; h %; h %; h %; h %; h %; h p%; h `%; h P%z; h @%r; h 0%j; h %b; h %Z; h %R; h %J; h %B; h %:; h %2; h %*; h %"; h %; h %; h p% ; h `%; h P%: h @%: h 0%: h %: h %: h %: h %: h %: h %: h %: h %: h %: h %: h %: h p%: h `%: h P%z: h @%r: h 0%j: h %b: h %Z: h %R: h %J: h %B: h %:: h %2: h %*: h %": h %: h %: h p% : h `%: h P%9 h @%9 h 0%9 h %9 h %9 h %9 h %9 h %9 h %9 h %9 h %9 h %9 h %9 h %9 h p%9 h `%9 h P%z9 h @%r9 h 0%j9 h %b9 h %Z9 h %R9 h %J9 h %B9 h %:9 h %29 h %*9 h %"9 h %9 h %9 h p% 9 h `%9 h P%8 h @%8 h 0%8 h %8 h %8 h %8 h %8 h %8 h %8 h %8 h %8 h %8 h %8 h %8 h p%8 h `%8 h P%z8 h @%r8 h 0%j8 h %b8 h %Z8 h %R8 h %J8 h %B8 h %:8 h %28 h %*8 h %"8 h %8 h %8 h p% 8 h `%8 h P%7 h @%7 h 0%7 h %7 h %7 h %7 h %7 h %7 h %7 h %7 h %7 h %7 h %7 h %7 h p%7 h `%7 h P%z7 h @%r7 h 0%j7 h %b7 h %Z7 h %R7 h %J7 h %B7 h %:7 h %27 h %*7 h %"7 h %7 h %7 h p% 7 h `%7 h P%6 h @%6 h 0%6 h %6 h %6 h %6 h %6 h %6 h! %6 h" %6 h# %6 h$ %6 h% %6 h& %6 h' p%6 h( `%6 h) P%z6 h* @%r6 h+ 0%j6 h, %b6 h- %Z6 h. %R6 h/ %J6 h0 %B6 h1 %:6 h2 %26 h3 %*6 h4 %"6 h5 %6 h6 %6 h7 p% 6 h8 `%6 h9 P%5 h: @%5 h; 0%5 h< %5 h= %5 h> %5 h? %5 h@ %5 hA %5 hB %5 hC %5 hD %5 hE %5 hF %5 hG p%5 hH `%5 hI P%z5 hJ @%r5 hK 0%j5 hL %b5 hM %Z5 hN %R5 hO %J5 hP %B5 hQ %:5 hR %25 hS %*5 hT %"5 hU %5 hV %5 hW p% 5 hX `%5 hY P%4 hZ @%4 h[ 0%4 h\ %4 h] %4 h^ %4 h_ %4 h` %4 ha %4 hb %4 hc %4 hd %4 he %4 hf %4 hg p%4 hh `%4 hi P%z4 hj @%r4 hk 0%j4 hl %b4 hm %Z4 hn %R4 ho %J4 hp %B4 hq %:4 hr %24 hs %*4 ht %"4 hu %4 hv %4 hw p% 4 hx `%4 hy P%3 hz @%3 h{ 0%3 h| %3 h} %3 h~ %3 h %3 h %3 h %3 h %3 h %3 h %3 h %3 h %3 h p%3 h `%3 h P%z3 h @%r3 h 0%j3 h %b3 h %Z3 h %R3 h %J3 h %B3 h %:3 h %23 h %*3 h %"3 h %3 h %3 h p% 3 h `%3 h P%2 h @%2 h 0%2 h %2 h %2 h %2 h %2 h %2 h %2 h %2 h %2 h %2 h %2 h %2 h p%2 h `%2 h P%z2 h @%r2 h 0%j2 h %b2 h %Z2 h %R2 h %J2 h %B2 h %:2 h %22 h %*2 h %"2 h %2 h %2 h p% 2 h `%2 h P%1 h @%1 h 0%1 h %1 h %1 h %1 h %1 h %1 h %1 h %1 h %1 h %1 h %1 h %1 h p%1 h `%1 h P%z1 h @%r1 h 0%j1 h %b1 h %Z1 h %R1 h %J1 h %B1 h %:1 h %21 h %*1 h %"1 h %1 h %1 h p% 1 h `%1 h P%0 h @%0 h 0%0 h %0 h %0 h %0 h %0 h %0 h %0 h %0 h %0 h %0 h %0 h %0 h p%0 h `%0 h P%z0 h @%r0 h 0%j0 h %b0 h %Z0 h %R0 h %J0 h %B0 h %:0 h %20 h %*0 h %"0 h %0 h %0 h p% 0 h `%0 h P%/ h @%/ h 0%/ h %/ h %/ h %/ h %/ h %/ h п%/ h %/ h 鰿%/ h 頿%/ h 鐿%/ h 逿%/ h p%/ h `%/ h P%z/ h @%r/ h 0%j/ h %b/ h %Z/ h %R/ h %J/ h %B/ h о%:/ h %2/ h 鰾%*/ h 頾%"/ h 鐾%/ h 逾%/ h p% / h `%/ h P%. h @%. h 0%. h %. h %. h %. h %. h %. h! н%. h" %. h# 鰽%. h$ 頽%. h% 鐽%. h& 逽%. h' p%. h( `%. h) P%z. h* @%r. h+ 0%j. h, %b. h- %Z. h. %R. h/ %J. h0 %B. h1 м%:. h2 %2. h3 鰼%*. h4 頼%". h5 鐼%. h6 逼%. h7 p% . h8 `%. h9 P%- h: @%- h; 0%- h< %- h= %- h> %- h? %- h@ %- hA л%- hB %- hC 鰻%- hD 頻%- hE 鐻%- hF 逻%- hG p%- hH `%- hI P%z- hJ @%r- hK 0%j- hL %b- hM %Z- hN %R- hO %J- hP %B- hQ к%:- hR %2- hS 鰺%*- hT 頺%"- hU 鐺%- hV 逺%- hW p% - hX `%- hY P%, hZ @%, h[ 0%, h\ %, h] %, h^ %, h_ %, h` %, ha й%, hb %, hc 鰹%, hd 頹%, he 鐹%, hf 逹%, hg p%, hh `%, hi P%z, hj @%r, hk 0%j, hl %b, hm %Z, hn %R, ho %J, hp %B, hq и%:, hr %2, hs 鰸%*, ht 頸%", hu 鐸%, hv 逸%, hw p% , hx `%, hy P%+ hz @%+ h{ 0%+ h| %+ h} %+ h~ %+ h %+ h %+ h з%+ h %+ h 鰷%+ h 頷%+ h 鐷%+ h 逷%+ h p%+ h `%+ h P%z+ h @%r+ h 0%j+ h %b+ h %Z+ h %R+ h %J+ h %B+ h ж%:+ h %2+ h 鰶%*+ h 頶%"+ h 鐶%+ h 逶%+ h p% + h `%+ h P%* h @%* h 0%* h %* h %* h %* h %* h %* h е%* h %* h 鰵%* h 頵%* h 鐵%* h 逵%* h p%* h `%* h P%z* h @%r* h 0%j* h %b* h %Z* h %R* h %J* h %B* h д%:* h %2* h 鰴%** h 頴%"* h 鐴%* h 逴%* h p% * h `%* h P%) h @%) h 0%) h %) h %) h %) h %) h %) h г%) h %) h 鰳%) h 頳%) h 鐳%) h 逳%) h p%) h `%) h P%z) h @%r) h 0%j) h %b) h %Z) h %R) h %J) h %B) h в%:) h %2) h 鰲%*) h 頲%") h 鐲%) h 進%) h p% ) h `%) h P%( h @%( h 0%( h %( h %( h %( h %( h %( h б%( h %( h 鰱%( h 頱%( h 鐱%( h 週%( h p%( h `%( h P%z( h @%r( h 0%j( h %b( h %Z( h %R( h %J( h %B( h а%:( h %2( h 鰰%*( h 頰%"( h 鐰%( h 逰%( h p% ( h `%( h P%' h @%' h 0%' h %' h %' h %' h %' h %' h Я%' h %' h 鰯%' h 頯%' h 鐯%' h 逯%' h p%' h `%' h P%z' h @%r' h 0%j' h %b' h %Z' h %R' h %J' h %B' h Ю%:' h %2' h 鰮%*' h 頮%"' h 鐮%' h 逮%' h p% ' h `%' h P%& h @%& h 0%& h %& h %& h %& h %& h %& h! Э%& h" %& h# 鰭%& h$ 頭%& h% 鐭%& h& 逭%& h' p%& h( `%& h) P%z& h* @%r& h+ 0%j& h, %b& h- %Z& h. %R& h/ %J& h0 %B& h1 Ь%:& h2 %2& h3 鰬%*& h4 頬%"& h5 鐬%& h6 逬%& h7 p% & h8 `%& h9 P%% h: @%% h; 0%% h< %% h= %% h> %% h? %% h@ %% hA Ы%% hB %% hC 鰫%% hD 頫%% hE 鐫%% hF 逫%% hG p%% hH `%% hI P%z% hJ @%r% hK 0%j% hL %b% hM %Z% hN %R% hO %J% hP %B% hQ Ъ%:% hR %2% hS 鰪%*% hT 頪%"% hU 鐪%% hV 逪%% hW p% % hX `%% hY P%$ hZ @%$ h[ 0%$ h\ %$ h] %$ h^ %$ h_ %$ h` %$ ha Щ%$ hb %$ hc 鰩%$ hd 頩%$ he 鐩%$ hf 逩%$ hg p%$ hh `%$ hi P%z$ hj @%r$ hk 0%j$ hl %b$ hm %Z$ hn %R$ ho %J$ hp %B$ hq Ш%:$ hr %2$ hs 鰨%*$ ht 頨%"$ hu 鐨%$ hv 逨%$ hw p% $ hx `%$ hy P%# hz @%# h{ 0%# h| %# h} %# h~ %# h %# h %# h Ч%# h %# h 鰧%# h 頧%# h 鐧%# h 逧%# h p%# h `%# h P%z# h @%r# h 0%j# h %b# h %Z# h %R# h %J# h %B# h Ц%:# h %2# h 鰦%*# h 頦%"# h 鐦%# h 逦%# h p% # h `%# h P%" h @%" h 0%" h %" h %" h %" h %" h %" h Х%" h %" h 鰥%" h 頥%" h 鐥%" h 逥%" h p%" h `%" h P%z" h @%r" h 0%j" h %b" h %Z" h %R" h %J" h %B" h Ф%:" h %2" h 鰤%*" h 頤%"" h 鐤%" h 逤%" h p% " h `%" h P%! h @%! h 0%! h %! h %! h %! h %! h %! h У%! h %! h 鰣%! h 頣%! h 鐣%! h 連%! h p%! h `%! h P%z! h @%r! h 0%j! h %b! h %Z! h %R! h %J! h %B! h Т%:! h %2! h 鰢%*! h 頢%"! h 鐢%! h 逢%! h p% ! h `%! h P% h @% h 0% h % h % h % h % h % h С% h % h 鰡% h 頡% h 鐡% h 逡% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h Р%: h %2 h 鰠%* h 頠%" h 鐠% h 造% h p% h `% h P% h @% h 0% h % h % h % h % h % h П% h % h 鰟% h 頟% h 鐟% h 速% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h О%: h %2 h 鰞%* h 頞%" h 鐞% h 逞% h p% h `% h P% h @% h 0% h % h % h % h % h % h! Н% h" % h# 鰝% h$ 頝% h% 鐝% h& 逝% h' p% h( `% h) P%z h* @%r h+ 0%j h, %b h- %Z h. %R h/ %J h0 %B h1 М%: h2 %2 h3 鰜%* h4 頜%" h5 鐜% h6 逜% h7 p% h8 `% h9 P% h: @% h; 0% h< % h= % h> % h? % h@ % hA Л% hB % hC 鰛% hD 頛% hE 鐛% hF 逛% hG p% hH `% hI P%z hJ @%r hK 0%j hL %b hM %Z hN %R hO %J hP %B hQ К%: hR %2 hS 鰚%* hT 頚%" hU 鐚% hV 通% hW p% hX `% hY P% hZ @% h[ 0% h\ % h] % h^ % h_ % h` % ha Й% hb % hc 鰙% hd 頙% he 鐙% hf 這% hg p% hh `% hi P%z hj @%r hk 0%j hl %b hm %Z hn %R ho %J hp %B hq И%: hr %2 hs 鰘%* ht 領%" hu 鐘% hv 逘% hw p% hx `% hy P% hz @% h{ 0% h| % h} % h~ % h % h % h З% h % h 鰗% h 頗% h 鐗% h 逗% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h Ж%: h %2 h 鰖%* h 頖%" h 鐖% h 逖% h p% h `% h P% h @% h 0% h % h % h % h % h % h Е% h % h 鰕% h 頕% h 鐕% h 逕% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h Д%: h %2 h 鰔%* h 頔%" h 鐔% h 途% h p% h `% h P% h @% h 0% h % h % h % h % h % h Г% h % h 鰓% h 頓% h 鐓% h 逓% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h В%: h %2 h 鰒%* h 頒%" h 鐒% h 递% h p% h `% h P% h @% h 0% h % h % h % h % h % h Б% h % h 鰑% h 頑% h 鐑% h 逑% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h А%: h %2 h 鰐%* h 預%" h 鐐% h 逐% h p% h `% h P% h @% h 0% h % h % h % h % h % h Џ% h % h 鰏% h 頏% h 鐏% h 透% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h Ў%: h %2 h 鰎%* h 頎%" h 鐎% h 逎% h p% h `% h P% h @% h 0% h % h % h % h % h % h! Ѝ% h" % h# 鰍% h$ 頍% h% 鐍% h& 逍% h' p% h( `% h) P%z h* @%r h+ 0%j h, %b h- %Z h. %R h/ %J h0 %B h1 Ќ%: h2 %2 h3 鰌%* h4 頌%" h5 鐌% h6 逌% h7 p% h8 `% h9 P% h: @% h; 0% h< % h= % h> % h? % h@ % hA Ћ% hB % hC 鰋% hD 頋% hE 鐋% hF 逋% hG p% hH `% hI P%z hJ @%r hK 0%j hL %b hM %Z hN %R hO %J hP %B hQ Њ%: hR %2 hS 鰊%* hT 頊%" hU 鐊% hV 逊% hW p% hX `% hY P% hZ @% h[ 0% h\ % h] % h^ % h_ % h` % ha Љ% hb % hc 鰉% hd 頉% he 鐉% hf 选% hg p% hh `% hi P%z hj @%r hk 0%j hl %b hm %Z hn %R ho %J hp %B hq Ј%: hr %2 hs 鰈%* ht 須%" hu 鐈% hv 逈% hw p% hx `% hy P% hz @% h{ 0% h| % h} % h~ % h % h % h Ї% h % h 鰇% h 頇% h 鐇% h 逇% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h І%: h %2 h 鰆%* h 順%" h 鐆% h 逆% h p% h `% h P% h @% h 0% h % h % h % h % h % h Ѕ% h % h 鰅% h 項% h 鐅% h 逅% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h Є%: h %2 h 鰄%* h 頄%" h 鐄% h 逄% h p% h `% h P% h @% h 0% h % h % h % h % h % h Ѓ% h % h 鰃% h 頃% h 鐃% h 逃% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h Ђ%: h %2 h 鰂%* h 頂%" h 鐂% h 适% h p% h `% h P% h @% h 0% h % h % h % h % h % h Ё% h % h 鰁% h 頁% h 鐁% h 送% h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h %J h %B h Ѐ%: h %2 h 鰀%* h 頀%" h 鐀% h 退% h p% h `% h P% h @% h 0% h % h % h % h % h % h % h % h % h % h % h % h p% h `% h P%z h @%r h 0%j h %b h %Z h %R h ~%J h ~%B h ~%: h ~%2 h ~%* h ~%" h ~% h ~% h p~% h `~% h P~% h @~% h 0~% h ~% h ~% h ~% h }% h }% h! }% h" }% h# }% h$ }% h% }% h& }% h' p}% h( `}% h) P}%z h* @}%r h+ 0}%j h, }%b h- }%Z h. }%R h/ |%J h0 |%B h1 |%: h2 |%2 h3 |%* h4 |%" h5 |% h6 |% h7 p|% h8 `|% h9 P|% h: @|% h; 0|% h< |% h= |% h> |% h? {% h@ {% hA {% hB {% hC {% hD {% hE {% hF {% hG p{% hH `{% hI P{%z hJ @{%r hK 0{%j hL {%b hM {%Z hN {%R hO z%J hP z%B hQ z%: hR z%2 hS z%* hT z%" hU z% hV z% hW pz% hX `z% hY Pz% hZ @z% h[ 0z% h\ z% h] z% h^ z% h_ y% h` y% ha y% hb y% hc y% hd y% he y% hf y% hg py% hh `y% hi Py%z hj @y%r hk 0y%j hl y%b hm y%Z hn y%R ho x%J hp x%B hq x%: hr x%2 hs x%* ht x%" hu x% hv x% hw px% hx `x% hy Px% hz @x% h{ 0x% h| x% h} x% h~ x% h w% h w% h w% h w% h w% h w% h w% h w% h pw% h `w% h Pw%z h @w%r h 0w%j h w%b h w%Z h w%R h v%J h v%B h v%: h v%2 h v%* h v%" h v% h v% h pv% h `v% h Pv% h @v% h 0v% h v% h v% h v% h u% h u% h u% h u% h u% h u% h u% h u% h pu% h `u% h Pu%z h @u%r h 0u%j h u%b h u%Z h u%R h t%J h t%B h t%: h t%2 h t%* h t%" h t% h t% h pt% h `t% h Pt% h @t% h 0t% h t% h t% h t% h s% h s% h s% h s% h s% h s% h s% h s% h ps% h `s% h Ps%z h @s%r h 0s%j h s%b h s%Z h s%R h r%J h r%B h r%: h r%2 h r%* h r%" h r% h r% h pr% h `r% h Pr% h @r% h 0r% h r% h r% h r% h q% h q% h q% h q% h q% h q% h q% h q% h pq% h `q% h Pq%z h @q%r h 0q%j h q%b h q%Z h q%R h p%J h p%B h p%: h p%2 h p%* h p%" h p% h p% h pp% h `p% h Pp% h @p% h 0p% h p% h p% h p% h o% h o% h o% h o% h o% h o% h o% h o% h po% h `o% h Po%z h @o%r h 0o%j h o%b h o%Z h o%R h n%J h n%B h n%: h n%2 h n%* h n%" h n% h n% h pn% h `n% h Pn% h @n% h 0n% h n% h n% h n% h m% h m% h! m% h" m% h# m% h$ m% h% m% h& m% h' pm% h( `m% h) Pm%z h* @m%r h+ 0m%j h, m%b h- m%Z h. m%R h/ l%J h0 l%B h1 l%: h2 l%2 h3 l%* h4 l%" h5 l% h6 l% h7 pl% h8 `l% h9 Pl% h: @l% h; 0l% h< l% h= l% h> l% h? k% h@ k% hA k% hB k% hC k% hD k% hE k% hF k% hG pk% hH `k% hI Pk%z hJ @k%r hK 0k%j hL k%b hM k%Z hN k%R hO j%J hP j%B hQ j%: hR j%2 hS j%* hT j%" hU j% hV j% hW pj% hX `j% hY Pj% hZ @j% h[ 0j% h\ j% h] j% h^ j% h_ i% h` i% ha i% hb i% hc i% hd i% he i% hf i% hg pi% hh `i% hi Pi%z hj @i%r hk 0i%j hl i%b hm i%Z hn i%R ho h%J hp h%B hq h%: hr h%2 hs h%* ht h%" hu h% hv h% hw ph% hx `h% hy Ph% hz @h% h{ 0h% h| h% h} h% h~ h% h g% h g% h g% h g% h g% h g% h g% h g% h pg% h `g% h Pg%z h @g%r h 0g%j h g%b h g%Z h g%R h f%J h f%B h f%: h f%2 h f%* h f%" h f% h f% h pf% h `f% h Pf% h @f% h 0f% h f% h f% h f% h e% h e% h e% h e% h e% h e% h e% h e% h pe% h `e% h Pe%z h @e%r h 0e%j h e%b h e%Z h e%R h d%J h d%B h d%: h d%2 h d%* h d%" h d% h d% h pd% h `d% h Pd% h @d% h 0d% h d% h d% h d% h c% h c% h c% h c% h c% h c% h c% h c% h pc% h `c% h Pc%z h @c%r h 0c%j h c%b h c%Z h c%R h b%J h b%B h b%: h b%2 h b%* h b%" h b% h b% h pb% h `b%⪆ f%z f% f% f%b f% f%B f% f% f%J f% f% f% f% f%J f UH5< HHdH%( HE1= uH5 1UH5 HHdH%( HE1nH5 1[H5n 1HH5 10H5C 1 H5+ 1H5 1H5 1DH5 1H5 1H5V 1H5V 1H5 1{H5& 1cH5U 1PH5! 1=(H5 1$H5m 1H5 1~zH5 1H5~ 1XzH5 1H5c 1H5[ 1H= 1 H5: 1yH5[ 1fH5U 1SH5 1@H5/ 1-H5 1H5 1H5 1H5 1H5 1οH5 1;yH5i 1訿H5 1蕿H5w 1肿H # H# 1H5~ aH5 1NHS3H= 1j HS3H=X 1Q9 H5 1 H5 1H5 1H5 1оH5 1轾H5 1誾H5 1藾H5 1脾H5 1qH5D 1^H5@ 1KH5 18H5 1%H5 1H5 1H5 1 AH5 1̽H5 1蹽H5; 1覽H5 1蓽H5 1耽H5 1mH5\ 1ZH5< 1GH= k~ 衩H= U~ 苩H= ?~ uH=M )~ _H= ~ IH= } 3H= } H= } H= } H= } ۨH= }%o H=? ~}C} H=? j}L"H=J T}音 H= C}a H= 2}L% r H=g }܇ ߾ H=* }A Hܣ L * H * HU 01Dž, H= |s H% H%( H=C^ |y_ I?|3_ I?t|&_ H=] c|z_ H=^ R|] H=] A|,_ H=] 0|1_ H=] |_ H% % % 1H% % 1L H % % 1% % H=J {LkMu LL9mtwIUfHnI}flIVL2AE BI}`@ LM~jH}ILI9t2IH= >{1 H= +{I~` xH5jH=L { H= z H]H= MzLMt IQ i 1 H3 H% H1L,% H1L,% H% H% H% 1 H HEdH+%( uHH=! [A\A]]0zKyH=,! z1T H1L,% LL 1LH ^ KLy齃 H5 1 rH% UHHdH%( HE1HEdH+%( uɺ H5T H=A ~x H= H H9tH Ht H= H5 H)HH?HHHtH Htf D = u+UH=⟆ Ht H= Qd} ] w UHH}uHEH@ HEH@ HE@ HEPHEHEUP] UHH@H}ȉuHEȋPEЉE܋EHHHEEHHHEHEH@HUHH]HEH} u HEH@HUHH|]HEH} uHEHf EHH HEȋ@HH HEHȾ HIyEHHHHEȋ@HHHHEHȾ HyHEȋU܉PHEHUHPHEHUHP UHH }u HEH} t5UHEHotHEHfHE HEUPHE UHHH}HEH@HeHEH@HeHE HH UHHH}HEHIeHEH}e UHH0H}uЉMfEHE EHEHE@9u HEPHEHnyjHEHPHE HHHEHEHPHE HHHEfBHEHPHE HHHE܉BHE PHEE UHH0H}uHUHE؋ 9E| HEH@UHcHHHEHEH@UHcHHЋHHE@HE0HEHkE} x8HEH@UHcHHHEH@MHcHHHHRHHQE UHH0H}HUHMfEE HE u E HEH@UHcHH@f HEH@UHcHH@f#EftXH} tHUЋMHELE؉HAHEH@UHcHHf@ HUHRMHcHH@fB&HEH@UHcHHЋ@uEEHE 9E+E UHHH}uHE HcHEH@UHHs UHH H}HuHEHEH HHǸ eEE QHEH@UHcHHЋ} t H H H}HH HƸ dEEHE 9E|HEH HHǸ dUUHH}uHUMHEUHEUPHEHUHPHEHUHPHEHUHPHE@ HE@$ ]UHH0H}dH%( HE1HE@$t HE؋@ HE HE؋ EfE HE؋P HE H8rHHEH} u n H} ~ Euh HEH} HE@$gHE؋@HEHHHE؋ HΉ胩HEH} HE@$,HEHPHEHPHEHPHEHHEHP HUdH+%( tIpUHH H}HEHPHEH@H9uHEHE} tEHEH@HHHUHJ UHSH H8H0H($dH%( HE1Dž@ HDžH HDžP DžD H0H H~_A H8H#DD 3 @ HPH HHHHUHXHX HXHHHHHPHH`HhHHXHpHxHHHXHMH]HH HX(HMH]HH0HX8HMH]HH@HXHHMH]HHPHXXHMH]HH`HXhHMH]HHpHXxHPDž@ @P@DH`D;$@HcHPHHPHHHHzTHXHX HXHH@HcHHHPHH`HHR@HcHPHHHH @HHPH0HHHH(HPHHP(HHH>]H0H HHUdH+%( tmH] UHHH HEHEH UHHH HEHHHj HjkHEH` UHHHEHP HEH} tHE HEHn UHH] UHHHi HEHEH5 UHHHD HEHHH HjHEH UHHxYHEH HEH} tHE HEH UHAYH] UHHH HEHEH UHHH HEHHH HjHEH UHH`HEH HEH} tHE HEH UH`H] UHHH HEHEH UHHH HEHHH] HQiHEHG UHH2HEHW HEH} tHE HEHU UHH] UHHHp HEHEH UHHHK HEHHH HhHEH UHHOHEH HEH} tHE HEH UHH] UHHH HEHEHi UHHH HEHHH HgHEH UHH謲HEH HEH} tHE HEH UHuH] UHH H $ H HhdH%( HE1H HH HsHxHx ui HhHHHHlu?HH)IHHhHPHxHuHhH@HFHHHxH5k HǸ `WoHxHxu HUdH+%( tg UHH HxHpdH%( HE1HUHxHHyHEH9pt HUdH+%( tCg UHH H}HEH@HEXHEHP@HEH HHLu5HEH HGHHEHPHEH@Hu HEHEH Hu UHHH}Hu#HE UHEHEHmH} u UHSHHH}dH%( HE1HHHEH HoqHEHEHHHHUк HHо HHkHH HH)H9tH H$ H H)H Ht% HHH HHEHEHHUHEHHJHUHEHHHUHEH _PATf@H HEH裝HEH} u 0HEH%FHHEHPHEH@Hu HHUdH+%( t eH] UHHH}HEHtt[HEHtHHEHt5HEH@Ht]Hw H H# HH! H6RHEH@Hu(HB H H HH HR UHH}HEH@] UHSH8H}dH%( HE1HHHEH H3oHEHEHHHHUغ HHо HHkHH HH)H9tH H$ H H)H Ht% HHH HHEHEHHuHEHH HǸ yHUHEHHHEHrHu HEH@H HHUdH+%( t cH] UHH H}HEHH`HEHHEH} uwHEHHEHEHHEA Hƿ WuCHEHP@HEHHu(HEHPCHHEHPHEH@HEHEHH[HE UHHpH}HudH%( HE1HE HǸ tEE} yAHME@ HΉ跚H~HEHeHUE EXEHUdH+%( ta UHHĀH}HuUdH%( HE1HE HǸ EE} yWHME@ HΉ H~/UHE HHUHHEH HtE E?XEHUdH+%( t` UHHH}HuHMHE HH UHHH}HuHMHE HH UHH H(H HdH%( HE1H( HǸ @@y虽 @HpH@ H H H HH H@H<< y"H H HOH H Dž< @V<HUdH+%( t]_ UHHpH}udH%( HE1HE HǸ EE} yENUHEH HHǸ HME@ HΉ芾H@uE EVEHUdH+%( t^ UHH H $ H@HHHdH%( HE1KHH uTHHHIHH HǸ tHHHHHMSHUdH+%( t] UHH H $ H@HHdH%( HE1ǶHH uSHHHIHH* HǸ sHHHHHUdH+%( t(] UHHH}HuHMHE HH UHHH}HuHMHE HH UHH H $ H0HHdH%( HE1谵HH uMHHHIHH HǸ rHHHH{eHUdH+%( t\ UHH H $ H@HHHdH%( HE1HH uTHHHIHHW HǸ qHHHHHPHUdH+%( tT[ UHH H $ HpHHdH%( HE1Dž .HH u HHHIHH HǸ /qH HǸ y HH HHHyt-y@nt/n6YtY,NtN"0t1uH H DžGQHUdH+%( tY UHH H $ H0HHdH%( HE11GHH uMHHHIHH* HǸ oHHHHbHUdH+%( t(Y UHH H $ H0HdH%( HE1 HH uYHHHIHHp HǸ o= ~HHHUdH+%( thX UHHH}HuHUHEIHH H¾ HՆ HǸ n UHHoHEH} u HEHHӧ HHՆ UHHoHEH} u HEHH H=H\Ն UHHkHEH} tHE HEHE UHHH}HEHH2 H UHH H}dH%( HE1HHUHEHHH5 HǸ y HEHUdH+%( tV UHHH}HEHF UHH H}dH%( HE1_HHUHEHHH5g HǸ zy HEHUdH+%( tGV UHHH}HEH)F UHHHE H H3HEH} t HEH<vHEHEH܌HE UHH H}H HHEH} uHEH 1HuHEH#~ HѺ H FEHEHlE UHH H $ H lH`HXHPLHdH%( HE1HHHuH HPHIHHͤ H¾ Kkltl : ;Gu > H H HHLuSHPHHXH`HHIIH҆ HH[ HǸ jH HHXH`IHц HH HǸ oj HXH`H HH HǸ >j 蔝HHHXH`IIH_ц HH HǸ iEHpl HΉzUHHXH`HH5 HǸ i HUdH+%( t(S UHH H $ H`HHHdH%( HE1HDž HDž H HtmH HHHH輖uMHa H H]H;s'HE HP HHHO^ H HH H"HH u ƅ H HjHH W HHHH HxjHH HHPH H H HHI HH <2u HHHH-] HHHHHWcHH HH HX HiHt\HH \HH H# HkiHt'HHHH}\7 HHHHHHIHHU@HH]H Hu H H Ht>H HH HH<H HP HHH[t8HHZH;s HHHH~[ HUdH+%( t~O UHH H $ H0HdH%( HE1HHH HEyAHH HǸ reHHHHdHUdH+%( tN UHH HHXH`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1Dž0 Dž40 HEH8HPH@HHx H H0HHH,,HHdH+%( tM UHH}HuHUHly HUHH | HUHHpz HUH] UHH0}HuHUHUHMEHΉ;E} t.}HM؋UHuHEAIȉH HǸ cHE UHH }HuHUH?w H HUHMHH UHH ,H H`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1H܆ HtRDž0 Dž40 HEH8HPH@LY܆ H0H ,HΉAHHdH+%( t+L UHHH} hH HEHۆ UHH@H}dH%( HE1E HEHEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHH?0EHUdH+%( t'KUHH}uHEU]UHHH}uUHEHUHHH}HEHUHH@H}HEHEЋEЃEԃ} u } Ht EԋUHMHMU܉EE܉EEEHEHEHuUEHMEE쐉E؋E;Et E؉Ew}u(H/ H` H HHQ H7 UHHH}HEHu(H̞ Hm H HH Hc7UHH@}HuHEHEЃ}Ht E+ẺEԋE9Es7E9Es(H H H: HH H6 _EԋUHMHMU܉EE܉EEEHEHEHuUEHMEE쐉E؋E;Et E؉EH} UHHH}HEHƿ UHH}HE] UHH}uHEUP] UHH }} u GEHHHHHEHEHEH} tHEUPHE HHE UHH HEH} t HE@HE UHH H}H} HEHHE} Ht_q E} Ht&Hq H H H H聰} Ht } HEH87 UHH H}HEHEH} tHEHYH HE UHHH}H} t$HEH(Ht HEH UHH T hcE} y }S NcEE;Et)MUEAȉщH Hƿ KEHEH} t&E HEUHcҋMLEE;E|HE UHHHE H HH HHEH} t HEH<HEHEHeSHE UHHHEH} tHE UHH}HuHEHEHEHEHEHE )] UHH}uHEUHcҋD] UHSH8}HuEHHHEẺHEH} HEHHHUHEHH)EHHUHzHFHѺ HyE E [} t+UHEHAËE؍PHEH+9t&UHEHE܍PUHUHLEE;E|UHEHE;E~(H H Hi HHh H1HEH] UHH`H}dH%( HE1HE E HE E E EHMHUHEH5 HǸ 3EЃ} } UE+ẼEԁ} E} Ht_-݇ E܃} Ht&HPm H H HHǸ 5} Ht ܇ } E;E|_E EȋEHH HEHHM)HEH} HEHE EčPUHH HEHẺEE9E|ՋE;Eu6E EHH HEHH(HEH} txHEHEEčPUHH HEHE}uE<-uEEE}tE< t6} ~ HUEH։HEHEH1HEHUdH+%( tA UHH`H}dH%( HE1HE HE HE E HE E H} u Hk ,HHE HHH % @ HE , HE HMHE HHSHEH} HE tHE <,tHE <-_ HE <-uoHEHHEHEHEHE HMHE HH݄HEH} HE tHE <, HEH;Es HEHEH} E} Ht_ه Eă} Ht&H j H H D HHǸ 2} Ht ه } E &EHH HEHЋ HU90 EE;E|ҋE;Eu:E EHH HEHH%HEH} HEHEEPUHH HEHHU؉HEHEH9ETHE t HEHHEHEHE)HHE HHH % } ~HUEH։_HEKHE t+HEHH Hƿ d^hHESHE HEHG.HEHUdH+%( t,> UHH}HE@] UHH H}uEH} t$HEH9E}UHEHnE UHHH}H} tHEH~ UHHH}H} tHE Hu UHHH}H} u 6HEH u HE Hu UHH}H} ] UHH H}uH} uwE HEHERUEЉ EUHEH3EUE9uE(UE9~EE EEE;E| UHHH}uUHEHB UHSH H}HuHEH;Eu H} tH} u pHEHEHEH9Et IE 3UHEHLËUHE؉H99t EE;E|Ÿ H] UHHH}H} t HE Hu UHH H}EE UHEHNKE(EtEE)EUHEH$KEHEHE9E|NjE UHHH}EHEH~~ HEHnPHEH#E UHSH H}HuHEH;EtH} u H} t HEHHEH9~ E E wUHEHËUHE؉H9~ bUHEHmËUHE؉HZ9u EHEH9Eu EHEHd9Et H] UHSH8H}HuHUHEHHt HEh HUHEHHt HEH1HEHV4 HEHHEH؉E܋EHHH衆HEH} u E E؉EԋEԉE UHEȉH?ËUHEH,9cUHEȉHËUHEH9uEEЍPUЋU؍JMHcH HUH HUȉH5EԍPUԋU؍JMHcH HUH HUHHEH9E}LHEH9E5EЍPUЋU؍JMHcH HUH HUȉH5HEHa9E|5EԍPUԋU؍JMHcH HUH HUHHEH9E|E;E~(H H H_ HH H$HUEH։HEHEH&HEH/HEH] UHSHHH}HudH%( HE1HE HUHEHHtHEHȠx HUHEHHtHEH蠠P HEH%EHEHEċUċE9MEԋEHHHރHEH} u E EЉE̋ẺE UHEH|ËUHEHi9}EgUHEHNËUHEH;9~E9EEȍPUȋUЍJMHcH HUH HUHHEH&9E}HEH9EE} tHUEH։HEHEH%HEHUdH+%( t4H]UHH@H}dH%( HE1E HEHEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHH:EHUdH+%( t"4UHH}uHEU]UHHH}uUHEHUHHH}HEHUHH@H}HEHEЋEЃEԃ} u } Ht EԋUHMHMU܉EE܉EEEHEHEHuUEHMEE쐉E؋E;Et E؉Ew}u(Hz H` H HH H UHHH}HEHu(H Hm HP HH H^ UHH@}HuHEHEЃ}Ht E+ẺEԋE9Es7E9Es(HԈ H HՇ HHS H _EԋUHMHMU܉EE܉EEEHEHEHuUEHMEE쐉E؋E;Et E؉EH} UHHH}HEHƿ UHH H}uUE+EHHHEEHHHHHEH HEH¾ H3HE@ UHH H}uEHHHHEH} t HE@ EHUHEHH}HEH} tUMHEH2HE UHH}uUHEUHcHHHE] UHH}uHEUHcHHHHH ] UHH }HuEƿ HEH} u iE 9H} tEHH HEHЋ uHMH:EE;E|HEUPHE HHE UH 膢] UHH H}H} HEHE} Ht_Yɇ E} Ht&HtY H H Hj H]} Ht ɇ } E UHEHEH EHE@9E|HEH UHHH}H} t HEHHE UHHH}H} t HEHt HEH UHH}H} t HE@ ] UHH}uHEUHcHHHЋ ]UHH}HEHUHHEHUHP]UHH}uUEHcHEH HHȋEHcHEH@HHHP HEHH]UHHH}HuHUHEH@H9EsHEH@ H9Er HEHEHEHgUHH}HEH@ ]UHH}HEH@] UHSHH}HuUHEHHEHUH HZHHHXHJHZHH HX(HJ HZ(HH0HX8HJ0HZ8HH@HXHHJ@HZHHHPHXXHJPHZXHH`HXhHJ`HZhHHpHXxHJpHZxH H H H HEU䉐 HEHUH H] UHH H} N HEH} tHMHE HHHE UHHH}HEH UHH H}uUME ΉN HUH HEH HtaE PE ;EHcЋEHcHEH HHHEH} t HE EE;E|EE;E|HEH Ht UHHH}uUME` ΉN HUH HEH Ht UHH H}uUMLEMH}uUHEIAHƿ* # UHH(H}uUHMHEH HEHEH;EuHE gHEH HuPEHcЋEHcHEH HHiHEH} t HE uHEHE؉ UHSHXH}HuHUdH%( HE1E H} u9HÇ Hu"譖HÇ HÇ Hu HyÇ HEH} u9HoÇ Hu"(H^Ç HWÇ Hu HAÇ HEHEH Hu3HEXHEH袀HEډHy 3 E UHEH:9E E EHcЋEHcHEH HHHEH} u E HM̋UԋuHEHE} MHEUHcHHHЋ HUHzUA _E܃} yʅ ؉EMHEU܉EHE@9E>EUHEHO8EHEHp9E} t HEHEHUdH+%( t'H] UHH H}uE REHcЋEHcHEH HHHEH} t!HE xHE HE EHEH H9E| UHH H}E UHEHLEHEH H9E|Ӑ UHHH}HEH HJ HEHǀ UHHH}HEH HtHEHUHEH UHHH}uHEH HtUHEH UHH H}HEH H HEH H E E EHcЋEHcHEH HH HEH} tMHE xCHEH Ht$EHcЋEHcHEH HH H2 EHEH H9EeEHEH H9E<HEH HH HEHǀ UHSHHH}udH%( HE1E UH۾ EHEH HtHEH Ht HEH H#HEH H HEډH(y C E E EHcЋEHcHEH HHaHEHEH UĉHP4EH} HEЋ HEH Ht$EHcЋEHcHEH HH HEHEع H/ HEЋMHuHEH0 Ẽ} tHEH$EFEHEH H9EEHEH H9E HUdH+%( t#H] UHH H}uUEHcЋEHcHEH HHHEH} tAHE x7HEH Ht'EHcЋEHcHEH HHHu <HEH Ht$EHcЋEHcHEH HH H UHH}HEH@0HEE E E HEHt EEHEHt EEHEHt EEHEHt EEHEHtHE؋ EEEEEEE] UHHPH}ȉuĉUHMHEH(HHEEHcЋEHcHEH HHuHEHEH@0HEE H} t HE y V HEHƿ gHEH} u 0 HE HUHMHΉE HHEH:~ HEHt%E܍PUHH HEHHHEHPHEHt%E܍PUHH HEHHHEHPE܍PUHH HEHHHEHHEHt%E܍PUHH HEHHHEHPHEHt%E܍PUHH HEHHHEHP HEH UHH}HuHUHEH@0HEE EPUHH HEHHHEHHEHt%EPUHH HEHHHEHPHEHt%EPUHH HEHHHEHPHEHt%EPUHH HEHHHEHPHEHt%EPUHH HEHHHEHP ] UHHpH}uUHMdH%( HE1HEH/HHEEHcЋEHcHEH HH|HEHEH@0HEHE( H H} t HE y HEȃHtHMUuHEHV HEH H EHcЋEHcHEH HHHtbHEȃHuVHEH Ht'EHcЋEHcHEH HHH HEHHc3 u DHE HUHMHΉA H z HUHMHEHHM HUdH+%( t UHH0H}uHU؉MDEԋEHcЋEHcHEH HHHEH} t HE y EHcHE HUHΉǸ - UHH0H}uHU؉ME .}MHU؋uHEAHDE} tE!EHEH H9E| UHHH}uUHEѺ $ Hb UHH H}uE HEH UH+ENMUHEAȉѺ $ HE} tE<EHEH UH+EHEH Hr9E| UHH H}E E "UHEѺ $ HEEHEH Hl9E}} tE UHHH}uUHEѺ $ H) UHH H}E E "UHEѺ $ HEEHEH H9E}} tE UHH H}HuE E MHUHE$@HEEHEH HGq9E}} tËE UHH}HEH ] UHH}HEH ] UHH}HEH] UHHH}uU} t} u ME@ Ή#< HUH HEH Hu^EEHHH; HUH HEH Hu)HEH H< HEHǀ UHHH}HEH HX< HEHǀ HEH H0; HEǀ UHH}HU؈EE } HEH@HuEHEH HEHPHEH@H9 EHEH Hx fH* HHH fH*f(XHEH@Hx fH*HHH fH*Xf(YHEH@Hx fH* HHH fH*f(X^f(f/m sH, m \H,H H1HUHH} t HEU]UHH}HEHUHHEHUHP]UHH}HuHUHEHUHPHEHUHHEHUHPHEHUH]UHHH}HuHEHHHUHEHHUHH@H}HudH%( HE1HEHUHPHEHEHEHEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHHEdH+%( tUHHH}HEHHEH@HHUHHH}HEHHEHBUHH}HuHEH HEHEHUHH} t HUHEHPHEHUHHUHEHP]UHH}HEPHE )]UHH}uHEU]UHHH}uUHEHUHH}HEH HEHE]UHH}uUEHcHEH HHȋEHcHEH@HHHP HEHH]UHHH}HuHUHEH@H9EsHEH@ H9Er HEHEHEHg UHHH}HEHHE@ HEH@@ H^@HEHn UHH H}HuHE t(HEH H d=HUH HE@ HE HEH H HEH HEH@HHtHUH HEH HB0 HUHEHHGHEHUHEHH`pH} *HE PHE HEH HEHEHEHEH;Eu HEH Ht2HE@u&HE tDHEH@H<Mt0HEH H HEH@HU|HUH OHEH HEH H9t4HEH Hz HEH H|HUH HE t%HEH HHUH .HEH HHEH@(HHUH HEH HEH@ HH)nHUHB UHH@H}HE@HEH HEHEHEHEH HEHEHE.HUHEHH,HEHEHEH HEHEHEHEH;EuȐ UHHH}HuHEPHE HUHEHHHE@PHEPHE@tHUHEHH UHHH}HuHEHHE@PHEP UHH 2 HEH} t HEHHE UHH}HuH} uHEH HEHEHEHEH HEHEHEHEH;Eu HE] UHH@H}HEH HEHEHEHEH HEHEHE3HEHHEHHEHEHEH HEHEHEHEH;EuHE@ UHHH}HEH@HHEH@ HwHEH@(HHEH@ HEH@ HEH@( HEH@HS UHHH}H} t>HEH1HEH11HEHHEHBHEH= UHH H}HuHUHEH@H9Et$HEH@HHEH6xHUHBHEH@(H9Et$HEH@(HHEHdHUHB(HEH UHH0H}HEH HEHEHEAHEH HEH HEHHCE} x$HEH HEHEHEHEH;Eu HEH/E UHH0H}HEH@HEHEHE HEHHEH@HEHEHEHEH;Eu UHH0H}HEH HEHEHE HEHohHEH HEHEHEHEH;Euא UHH0H}HEH HEHEHE HEHMHEH HEHEHEHEH;Euא UHHH}HEHbHEHEH@0 UHH@H}HuЉỦMLEEHcЋEHcHEH HHuHEHEHUHPHEHUHPHEH@HEE HEH냵FaHи@ +EHHЉEEHH H HEHHEHH UHH}E HEUHcH H E} ~ݐ] UHH H}HuUMLEEHcЋEHcHEH HH{HtRH}MUHuHEIHHEH HE HHU HHHEH UHH`H}HuUMDEdH%( HE1f)E)EE EHcЋEHcHEH HHHu HUȋE$HΉǸ Eă} Pg t HEHHt HEH@0Ht HMЋE HΉ[BHu[HEH@0HtEHEH@0HtEEHHDHEH}ȋMUHuHEIH HUdH+%( t UHH@H}HEH@ HM`EHEH@(H*EE HEH HEHEHE4HE tEE EEEHEH HEHEHEHEH;EuHEH@HZ9E~ HEHP@E܉Hy UHH0H}uHU؉DEfEEHEHx@MԋEE} x5HEH@XUHcHHHEHE Ǹ E UHH0H}uHUHEH@UHcHHH HEH} t HEHv UHHH}fEEHUHz@ H UHHH}uHEHP@EHV\ UHH0H}؉EHE؋@0HcHHHHHd) HEH} u E h} t EHcHHHHHPHEH HEuԋEHcHHHHHHEH<HE HJ EHE؋@09E|HE UHSH8H}؉uԉUЉM̋EHcЋEHcHEH HHHEHEUԉP HEH H]UЉHC$HEH ỦHHUB(H] UHH H}UE} t HEHh HEH` HEH} uJUHEHRHEH} u C} tHEHUHh HEHUH` EHcHHHHHHEH UHH H}HuUMMUHuHEH\ UHH}HuЈE} tHEHUHx HEHUHp ] UHHpH}HuUHMDEDMHEH@ UHEHEH HEHEHE HE@;EHE t } HEH UĉHEȃ}^ HEL@MËUHEHAHEH} u U } tHE HEHEHE HEHEEHcЋEHcHEH HH" EHE HEỦHEH HlHEH Ht HEL MHUHuHEHAHEEщHY Hƿ HEL@HEMHuHEHAЅy Z HE PHE } uyUHMHEHH`HEŰEAȉщHBY Hƿ YHEE̾$ Ǹ t HEH EÃEHE EԋEȋ}HUuHEAHyHEH xHEH@0HtB}̋MUHuHEAHFyAMUȋuHEH\HEH HEHEHEHEH;E1 UHHPH}HuHUdH%( HE1HEH@(HO#EHEH@ HXEE E UEAЉHX HHW Hƿ γE YEEDEHMUHuHEHH}WH}WH}WEA H H EEE;E|E REEDEHMUHuHEHH}WH}WH}WA HH uOEEE;E|HEȋP0E9t'HEȋP0E؉щH%W Hƿ ̲ HEHT#HUdH+%( t UHHPH}HuHUdH%( HE1HEH@(H!EHEH@ HVEE UEAЉHV HHV Hƿ E aEEE >DMDEHMUHuHEHH}WH}WH}WHFH uTEE;E|EE;E|HEȋP0E9t'HEȋP0E܉щHU Hƿ q HEH!HUdH+%( tS UHH H}HEH@ HUEHEH@ HtHEH@(H* EmE UHH@H}HuHUHEH@ HEH} tHEH@Ht HEH@Hu ( HEH@8H )BHEȉPHEH1HU؉B0HEH HEHEHEqHEH@0HtNHEH Hu>HEH H@ HEH H@HEHy HEH HEHEHEHEH;EuHEH@PHuHEHy@HEH+tHUHMHEHH:HUHMHEHH UHH@H}ȉudH%( HE1f)EfEHHEHEHEEăH) HEHP8HUHMHEHH HUdH+%( t UHH H}HEH` HtBE -HEH` EHcHHHHHH EHE@09E|HEHh HtBE -HEHh EHcHHHHHH EHE@09E|HEH` H HEHh H UHH}HuЈEH} t HEH@X } t HEHx HEHp ] UHH}HuE HEH HEHEHE&HEHUH EHEH HEHEHEHEH9EuHEЋU䉐 ] UHHH}HE@t&HEH HEHEHEHEHUHHS UHH H}E HE HlmHE;HEH H9EuHE ~EHUHEHH/mHEH} uE UHHH}HuHE t*HEƀ HE@tHUHEHHUHH@H}dH%( HE1HE HEH HEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHHEHEHEHUdH+%( t}UHH@H}HudH%( HE1HEHEHEH HEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHHEdH+%( tUHH@H}dH%( HE1E HEHEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHEHUdH+%( tUHH}uHEU]UHHH}uUHEHUHHH}HEHUHH@H}HEHEЋEЃEԃ} u } Ht EԋUHMHMU܉EE܉EEEHEHEHuUEHMEE쐉E؋E;Et E؉Ew}u(HZO H` HkM HHM HY UHHH}HEHu(HN Hm H M HHM HUHH@}HuHEHEЃ}Ht E+ẺEԋE9Es7E9Es(HN H HL HH#M H _EԋUHMHMU܉EE܉EEEHEHEHuUEHMEE쐉E؋E;Et E؉EH} UHHH}HEHƿ UHSH}uUHE MHɻ HHHHHHH HʋMHH@tH1H] UHH H}HuHMEHE@ HEUP0HEHUHP@HEH HH} t HEHUHPX UHH}HE@Hv Ѓ] UHSH(H}HuU܉MHEH@ HEPHEPHEHEHUA Aй Hƿ IHUHHEH HuHEH HEU܉P HEU؉P H] UHHH}H} HEHHHS HEH@P HEH HtLHEHHHEH HHHEH HE@ HEH HHEH@@HtHEHP@HEH UHHH}HEHHS UHHH}HEH Ht<HEHH0u(HcK HM HI HHI HJHEHHt HEHUHHH}HuHEH HUHH UHHH}HEH H UHH H}HEH HEHEHHHEH@H9uHEH8 Hu UHH H}HE@0t HEH@HEHUHEHH HEHHu HEHIt HEHt UHH@H}؉uHUHMHEH HEEԃEHEHHEIHHI HHH Hƿ HEHEHH!HEHHEHEH HUH)EH9rUHoH Hƿ 覢HEH HUH)EH9sHE@H)EHEHUH EHH#EHHEHHEHE@fu+H6H Hƿ -HEHUH 4HE@HEHEHH1H Hƿ UHH@H}HEHHEHEH@HEHEHH HHEHE@0tHEHEHUHB HE@0tHEHEHUHB(HEHP(HEH@ H)HEH@8H9s HEHP(HEH@ H)HUHEȋ@HHH;E HE@0 E } Ht_ E܃} Ht&H H H3 HF HV} Ht } HEHUHPHEH33HEHH(HEHP HEȋpHEHt UHHH}HEHHu HEH UHHH}HEHHLtHEHHUHB UHH`H}HuHUdH%( HE1HEHH HHEHE HEHEH )ЉEЃ}} HEHHE@HH!HEHHEHE@HEH}v HE9E} : HEHHE@HH!HEH HEHHEHHE@HH!H9 HEH EHEEHEH@HHEHEH@PH;EsDHEH@HHUHHHEH} u HEHUHPHHEHUHPPEЉHE@!ЃEẺEċUċE9FEԋUHE@#EȉHEHHEHHEEȋEHEE)Ẽ} uHEH@HHEHEHHEHHEHHEHUdH+%( t UHH H}HEHHu iHE@0tHEH2HUHB(HEHP(HEHH HEHHHEHE@0tHEHP HEHPHE UH}E3EUEUH H ] UH1EUEUH H ] UHHp HHdH%( HE1HH HDž Dž HDž HDž HDž HDžH tH@(u E HHHPHEHXDž tn{tHit tUHPHXdHPHXfNHPHX:HPHHXH$HHXHPHHHhEHE HHH@HEHHDž tn{tHit tUH@HHdH@HHfNH@HH:H@HHHH$HHHH@HHH~HUHHPHE HH H0HEH8Dž tn{tHit tUH0H8dH0H8fNH0H8:H0HH8H$HH8H0HHHHUHHPH@(n HHPHH@H9O ;HE HH4HEHEHEDž t\ct<Qt t=HEHELHEHEf<HEHE.HEHHEH HHMHUHHHEfE HH2HpHEHxDž tn{tHit tUHpHxdHpHxfNHpHx:HpHHxH$HHxHpHHHEHE HH8H`HEHhDž tn{tHit tUH`HhdH`HhfNH`Hh:H`HHhH$HHhH`HHHHEHH@( HE HHPHEHEHEDž t\ct<Qt t=HEHELHEHEf<HEHE.HEHHEH HHMHUHHHHEH HE HHXHEHEHEDž t\ct<Qt t=HEHELHEHEf<HEHE.HEHHEH HHMHUHHHHEHE HH HEHEHEDž t\ct<Qt t=HEHEȈLHEHEf<HEHEȉ.HEHHEH HHMHUHHH?EHE HHHEHEHEDž t\ct<Qt t=HEHELHEHEf<HEHE.HEHHEH HHMHUHHHyHEHH@(Z M H fE HH0HEHEHEDž t\ct<Qt t=HEHE؈LHEHEf<HEЋHE؉.HEHHEH HHMHUHHHyEf@ )Hӥ @ )Hӽ H HE HHHEHEHEDž th q ct<Qt t=HEHENHEHEf>HEHE0HEHHEH HHMHUHHHi E;HHPHH@H9 HH+ H#HH HHHHHHH(HHPH(HHHP t HHPH(HHHPHHH HUdH+%( tn UHHH}HEHƿ +$ UHHH}HEH H*HEH UHH }uHUEHHUHHEEHHEH(HsHEH} tEHEHUHPHEHUHEEHcHEHPEHcHEHPEHcHEHP HE UHH H}HEHPHEH@HHEHEHH(HEH¾ H UHHH}HEH& UHH@uHUHMȈEHEHEHEHEi} tHUHMЋEHΉHUHMЋEHΉs;HEH} y 39 t H} HEZHEH)EHEHEH} uHEH+EHHEH9t(H5 H HS5 HHQ5 HHE UHH }HuHUHMHUEƿ UHH0}HuHUHMHEHEUHMHUHuEOHEH} y H8 t'H} HE&HEH)EHEHEHEHEH} uHE UHH }HuHUHMHUEƿ ;f. f. SI H dL %( L$ IH H IH Q4 H / H81H$ dH+%( u H [fPXH Ht$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$ )$ )$ )$ )$ dH%( HD$1H$ H$ HD$HD$ D$0 HD$ ;ff. AUATUSH H $ H8 dH%( H$( 1HK H= H</Z L$ L]H H=2 IHtLH ] LHIHIDH= C,/ HHL)K|,H] MHH ? L% HLHE1J R HH] L HH l? L40 HHE1 H$( dH+%( H8 H[]A\A]f H$( dH+%( H8 []A\A] L/H > L%Ҧ IL MIE1~ L-/ HLu8H$ Le8H$H9$ nHD$H9$ [ LLF H= _ H=3 1Hھ< H=0 1ff. H H8H=0 HP HpHH D H?/dL %( LL$IH$ tJHC HH = H0 L@1B t>H$HT$dH+%( u%H @ HD$dH+%( u LH餶H=2 1 USHHtA? Ht9HHs f. HH9r ;/uH9s HH[] 1HH[] @ HHH)H;o HtHkHH[] H5 H=o H Hxmff. f H=n Ht黵 SH H{ Ht8 u H{[J H[f. AUATUSHdL,%( Ll$L-% IL H$ Hb HHHDH5Mn H5H=H $H ; L. HHEHtI1H LFt=HH4$L XH<$HD$dH+%( uH[]A\A]H=0 1 AUATUSHH H L(H H1 HHH| uzHcH"! L(Iff. ff. I HH\HuHI LL0LH[]A\A] L(I뷐 Hh H$@ H$H H$p L$X L$0 H$8 L$P dH%( H$( 1LL$H$p D$ H|$ HD$ Hc/ HHTHtgH VA HA)HcHL$HcILL$ ff. f. HL9tHHcHH IDHu t[HD H|$ ;H$( dH+%( u_Hh D AЃOLDMtH tH% D H H HY H H1 Qf. H?H6HH9f AWFAVAUATUSH8dL4%( Lt$(IH=+ D$. HtYH1 Z!H=~+ fD$ Ht41 H5!f|$ fD$"tf ff. @ 1HT$ T :I D$ P O t$9 HcIIF1HDH AăT$ HD$HD$ H5 1E1 0Hc\$ Hl$E~nLEEIK D AL$ D9t A .H9BT$IGH5 AH 1HH/E9t IGH9rLEEIHF H0)H\$HCH9\$tHD$? HD$(dH+%( uLH8[]A\A]A^A_ù A f|$ D$"f SI H dL %( L$ IH H IH ) H# H81SH$ dH+%( u H [rfPXH Ht$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$ )$ )$ )$ )$ dH%( HD$1H$ H$ HD$HD$ D$0 HD$ ff. AVIAUIATLb USHL_HtyHL( LI9H}LICHH"HSH BD- H{HBH9s/HtI0HH9HBH3H轳HHt HSHCHBHCH,[]A\A]A^H=' 1f. AWAVAUATUSHH H|$HdH,%( H$ HHD$( HO IHm HD$ILl$(1Iؾ H 4 HX' LJ HD$0HD$f D LH HHXsHHHuL|$(Iؾ LH 3 H MIEG LHt$H|$(G-uD$H k@cHD)Hv |.exeuHcD$H|$HcH4MLH-LtH|$(jH$ dH+%( u?H []A\A]A^A_ D D$ A H-% H=( 1 ATIUSI|$ Ht,11 D H<I|$H ]HI;\$rȺfID$ A$[]A\Ð AWAVAUATUSHLwM H_I It2f. DmH<N<HIwgtkEHL9r111HHt 9tH˃BHL9r݉ID$9s\H)H<1[H ]A\A]A^A_ LI\$Mt$EHJ L9OMnH[]A\A]A^A_ AWAVAUATUHSH(LoM IE1E11IH L9 M;w HUH H$HHT$HxIGJ4H4 yHCIt$L9 HT$HD$J Ht$J<HUH$LmLd$HH HHH\$L9bff. M9s*HEL @ H<藸HEH HH;]rMLmH([]A\A]A^A_ IH D L9tL9sHUf. J<N, I+HUJ*LmH H HHL9rS AWAVIAUIH= ATIUSH HHH HLLHH I~ IvHH$wL7H H^HD$H( @ HHr tLHLPI_: HIHuHH< tLHLH|$I|$It$ H $L07HHLL[]A\A]A^A_ HtH蛧HD$I LLLL{: L>HHuLLLxH H$N AWAVAUIATIUHSHHvHzH MD$111f IH H9B؍BHH9rH LE11ff. f. IH H9B؍BHH9rH L=v LH5\N 1%H5 1%LAąt!ff. I7- AuI7 H&I7H []A\A]A^A_ #L H5 HIHD$1%H5 1$LLI L= DDpt ff. I7- cAsI7 PLvI7 9H|$H} H[]A\A]A^A_ D 1HX AUATUSHHoHtILgHE11 AEIH9s,I4HH uH []A\A] H1[]A\A] HH H8H H8 H=] H6f D H E1dH%( H$ 1HT$HL$ HH$ H$ HDŽ$ HH 1H L1H5 H= yH$ dH+%( uH f H SH8H H8 H=\ 5T [l ff. H Hx H=\ @ USHdH%( HD$Ha Hx xH \ H >1HT ʬu D$c\ ; tfH5 HtSHQ H=[ 7\ H[ H-H Q [ H[ $ HD$dH+%( H[] D Ht1HT u D$[ H H=F gHH H HǪ H H諪 Nf D =Z u*=Z H=H= f=Z f D Hukff. Z D HH= |Hu Z ҍBN DH 1HH @ AVAUIATIUSHcoHc^ D = v*A wEH Eu3[]A\A]A^f D H ,A wV u={ t)uI|$IuH& []HA\A]HDHA^HDc { D؉)uu{ )wff. AUATUSHH? G0uu t H[]A\A]L% L- 1LI<$菹KI<$Hc L 1nHHHKHt'C I<$H 1>HHŋI<$ 3 w0H C0tH{ Hj 1HHH )I<$LK 1 L% H^ 谸C1I<$LK(H1[LY% ] A\H1 A]u D H 1]HH I4$ R f H- Hu +HK 9 SH} HHN 1[ ]A\A] D C0HKH H_ tH{ H@ t| 1谷HHf D | C0 I<$H 1aHKHHHf. H x @ H 0 @ H H{ H H SI H dL %( L$ IH H IH A H H81蓶H$ dH+%( u H [費fPXH Ht$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$ )$ )$ )$ )$ dH%( HD$1H$ H$ HD$HD$ D$0 HD$ +ff. AWAVAUIATUSH8HL$Ht$(T$$ L=5 H IHt%H;HJ 1pI?訪I IM H;H. 1 MeCMEL- Mu%lH;LIL 1M$MtIA8 uL-Z L=! H- A8 H;HuLL 1IδM$MuHD$( tH3 HD$( LT$(1E1ff. MAtf D A}`I`AuI}XDLLT$ @HcHHT$IHq HcHT$Ht$H<@DHHH9HB)HH@H)LHMUXMtADM[McAoE K@HL AoE@AoE @ AoE0@0AoE@@@AoEP@PA$ MLL51 I` AE uHcL` xMA4$tiHD$H P HD$rH HhLlLu AAv<- @ueA;D$ HL9uAD$`I`uH3 H8L[]A\A]A^A_t$$LI`A $uf D I|$HtLT$T$t'I|$ HzLT$XT$Hat$$LI`kA$[HD$Pf@A;D$t@-!I|$HIvT$PT$fHcL` AE L1҅ObMu%Ld$(fH ` 1LHM@ H IH u>HOtHHw 1`HH{ 1Jf. OH* HǾ 1' AWAVAAUATUHSHH dL$%( L$ AAX H F0 AA p AA@\ HW H9t H< H] H} AA M ff. fLK(Ll$ H L LLE 1-Ƅ$ C0 & Ec HKE H7߅ M H H81ƯE1H$ dH+%( Hĸ D[]A\A]A^A_ F0 \ @tHW H9t H~ H] EA AA 3V - H HcH> D D ; H} Ut HE H@8- HE Uq D Hޅ HKL H8E H 1膮A H} q;h`HE E HKH݅ M H0 H81'\f fo )D$ f)D$0)D$@)D$P)D$`)D$p)$ )$ H/݅ H8E HKME"H 1設 E1< H܅ KMHF H81m fo )D$ f)D$0)D$@)D$P)D$`)D$p)$ )$ HSHHtE Hu| HtHE 1HS8E HS1Euf 1EuC@HS 1EuHC@HSHHSE H 1HSHHttHSHHt 8 A D E H} H HE Ht$HSHD$8 <DH5 H]b E H} H HE HkHt$ gHE HD$8 E H} H HE HkHt$ 臕HE HD$8 AEw H} H HE ?-DH5G9 Hotf. HSHC@ !EDƉHCAAD0HCHH D E H}U H HE ?-hHkHt$ v(HE HD$8 PHSHHtE '11HS8E[Hoم HNL H H81kEtDJA EtsLl$ L7 1 LDT$ 3'DT$ H H8E HKME H 1xAE1LJMM Ll$ L 1 LDT$ &DT$ {Hz H8E HNL 1H" m HCH KMH 1 Ǩ<fHC HM Hr HE HH f FHCUt HE H@8- @ HE UHPHxHU H]Utt HE H@8-c HE UHPHxHU H_Ut/ HE H@8- HE UHPHxHU "HaUt HE H@8- V HE UHPHxHU $HUt HE H@8- HE UHPHxHU nHLMt Hu Hv>- MHM HqHIHu HCHS@HHCHS@HUtK HE H@8-: M HE UHPHpHU CH fHK@HS@HCHMDJ*H% 1wKMH 1 ֥YH"Յ HNLC H H81詥 H{@yH{@H{@ H{@fH{@NL 1HS ZHԅ HNL HG H81-HK@Hs@$QH=r3 1DH5 HafDH5 HJC0Uff. @ PXHHt 11 ff. ATUHSHH HL$8LD$@LL$Ht7)D$P)L$`)T$p)$ )$ )$ )$ )$ dH<%( H|$H=Ӆ H$ H HD$HD$ $ D$0 HD$L'薸t&LHt11HH H= 1=ff. f AWAVAUATIUSHHL$ H H-҅ IH1LwH< H} SMEL-0 Mu!pLIL 1*MMtQA8 H} uL-j L= f. A8 H} H uLL 1I٢MMuHu 3 |$ L- LsMt_LLLHH% LLH9HFHu Il$H²H{HHtoK`H`uH[]A\A]A^A_A$9CtS`H`t9Cu1H f. 1HLNHYf D 1H @ AWAVAUATIUS1H HT$HL$ LD$DL$dH%( H$ 1HDŽ$ Ht I8 T$CfMl$D$PHDŽ$ HDŽ$ DŽ$ AljDŽ$ $ HDŽ$ Ӌt$P\$( HD$ EE1AMu A>- A EH$ Hcl$PHHA HtHD$H ŕMcHLK<HcI H$ dH+%( < H []A\A]A^A_ D AFk<- I^<hu L$( Ht$ 9F H`uHvXHuIcA7 IU AE1If D IcAM4Il$PA~ DD$(I^E H5 HDL$8L\$0 H5 H = H.L\$0DL$8HS 1E1D$l E1Lt$pHl$LD$8t$hHD$`L\$XDL$@Ld$HMD|$TMDu E M H|$8 HmXH Du EtDt$0E1LmMl LLHHI# MDt$0J +A l <= MDL$@Ld$HLYD|$TD$PH$ HL$ L$ $ HD$D$ L$ D$ H$ $ L$ L$ D$ T$PH$ L$ D$ HT$ Ht$H|$1HHD$HPH Ht$11d HHL$0轭Ht$0LHݚ D H`> 1A~ tIFT$PH$ H$ HD$HL$ $ L$ D$ H$ D$ $ L$ L$ D$ T$PL$ H$ HT$L D$ MHDL$8L\$0L\$0DL$8HHZ A~nu{ou {-r HD$IƋ 1 L\$0DL$8Hl$@LIff. H}HtLH|# E`H`uL\$0DL$8Hl$@\$(T$PHL$MM u A>h Ht$D Eb A-ff. ff. f D DV`H`E/ 9Fu1A~ tIF$ H L$ L$ D$ H$ H$ D$ L$ L$ $ D$ H$ H$ D$ I Hȅ LL$ H-P HH LL 1 HD$ E1L5o L M \$PH\$ Ld$(M HL LL$ MIE1 LI7NMz MtHL LLL$ MIE1:t5LNt @ L@H 1 H= 1f\$PLd$(L$ H ! LLL܋ MIE1tLkH$ HD$H8f D Dt$0]f D L\$EϹ Ht$H|$HL\$!jeH=bȅ IE H H HHEˀx-E1 H' H軍Ht$H|$l @ uH|$ t7HD$ HHt*HH-Pm HH 1HdHSHuHDž H0 ] D H5N HDL$8L\$0/L\$0DL$8J H5 o HDL$8L\$0L\$0DL$8 H|$DH-D$PHt$1҉$ H$ L$ $ HD$L$ D$ L$ H$ ~f HL$LHt$H|$ HHD$@}Ht$ 1$ H$ x @ |$0A} n A}o A}- IEHHD$0 Ht$0HHHD$x& HT$xH <= %HcD$@Lt$pMLd$HL\$XID|$TAM4tf HvXHI~DL$8T$PHL$Lt$0|H\$0DL$8IE -@H@L\$0DL$8HHT$`HLH)K 7 H HH= H9HF ;n={o3{-)HD$pLLHHHHL$0ݒHL$0J 1 D1}EL\$1HH|$Ht$EωT$P LI\$(T$PMHL$!H3H|$0HHSH|$8 @ E`D$0 T$hD$h HE`L|$8T$lHl$8HLD$8HD$`M 8 E`D$0? ML$hL\$XID|$@Ld$HH5b L\$I@H L HEօH QÅ LEƾ H9AqHIR1H" ԓY^L\$L\$XDL$@MD|$TLd$HLIc8 D$lL|$8D$hHD$`HHD$XE`D$04 T$hL|$8HE`D$h T$lH|$DHD$PHt$$ H$ 1L$ $ HD$L$ D$ H$ H$ 1ML\$XDL$@Ld$HD|$TDH$ EϨ\$PIHcDHIT$PMHL$MLD$8L$hIL\$XD|$@ Ld$H9E`D$09 D$h HE`LD$8Mt$hL\$XDL$@Ld$HD|$TMEωIf T$hMHE`D$h T$lmLD$8L$hMML\$XD|$@MLd$HL$lML\$X1HD|$@H5 MLd$HL\$L\$nH|$DHD$PHt$H$ L$ $ HD$L$ D$ L$ H$ $ \MML\$XDL$@Ld$HD|$TMm H|$DHuHt$$ 1H$ HL$ L$ D$ L$ $ +E`D$0tt1HE`|$hHD$Hl$H 8 @HUHt H 1H`U uE`H`uH= 1PMML\$XDL$@Ld$HD|$TMEϋL$lIMLD$8t$hML\$XDL$@Ld$HD|$TLwH Hپ Hs H81葏 EϋL$lIMк J EI1ϓff. @ 1HWu Nvt1 1HȍA1f DE HAVAAUAATIU@SHuVH{Ht@t LtAS`H`u[]A\A]A^fH{Ht@t LtC`H`t D;suD k0[]A\A]A^ DE AWAAVIAUEATIUSHHH@Ņue H{Ht@t LjtIS`H`uH[]A\A]A^A_ @ H{Ht@t L2tC`H`t!D;{uELs(A D k0A Dk0H[]A\A]A^A_fS L5 H dL %( L$ IH趈H IH H H81?H$ dH+%( u H [^ff. PXH Ht$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$ )$ )$ )$ )$ dH%( HD$1H$ H$ HD$HD$ D$0 HD$ ˽ff. AVAUATU1SH G,dH %( H$ Hu K E1 E1u C 10C C,l { E E {~ { ff. fH{Ht HC H H(Hu# HC HhHPHS H H= HHuf D SH|$ D$A CC, D z { EF { E 1H$ dH+%( Hİ []A\A]A^f H|$ D$A CE @ H|$^ D$ E1C C,f D |$ 藆`f苆Kf D {'f D |$ "|$Y|$P; 1{ 9C,HC0HtHC8H HЉܺ @ H=/ 1 1ʼn誫C,~ H=/ 1 ʼnv诅C,[ H=i/ 1 ʼnB{ff D H3C, H !{D0 { < E {2 E 1A-' D |$EIf |$ׄf|$1腪|$輄|$ 賄C,If. |$ R|$艄|$ 耄C,' !L @ H> |$?|$ 6|$'|$ f |$|$uX{ u1Eu3{u{~踃u={ t褃ȋ|$虃|$萃9|$考|$ w뛋|$l|$ Ht$ 8HSH=a HHH01 D USH dH %( H$ HG, Hl$ { H0t| 8tHt$ 苍H HH} H81K, S(H$ dH+%( ulHĨ [] D S( C, @ ;CuL$ ȃ<uՀtEuƊf D USH dH %( H$ HHl$ G, u|{1Hys8tHt$ xH HHj H81K, S(H$ dH+%( u[HĨ [] D S( ;CuËL$ ȃ<uՀtEɉf SHt[ D H[ff. @ HXfdH%( HD$HHHD$(HD$8 D$D$H$ D$,ϣHT$HdH+%( uHX D SI H dL %( L$ IH ~H벅 IH ! H H81sH$ dH+%( u H [蒈fPXH Ht$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$ )$ )$ )$ )$ dH%( HD$1H$ H$ HD$HD$ D$0 HD$ ff. AUHW" ATIUSHcHHHHHcCS H;9|3LR0p 9Ls HcH nHHt;HHcCL,LHcKHIE H<HtCH[]A\A]H= 1ff. SHcH! HHÍG w*HcC~HHtmHtk1[ø[É1H= H USHHHcd! b! H=O! 9|=L@0r 9L5<! HcHmHHt~H! Hc! H,H ͍Hc H HE H<Ht H KH >H 1HH [] H= 1`UHEEHİ HtE E]UHEEH Htm E]UHH}uHUMHEUHEUPHEHUHPHEHUHPHEHUHPHE@ HE@$ ]UHH0H}dH%( HE1HE@$t HE؋@ HE HE؋ EfE HE؋P HE HHHEH} u 4 n H} ~ Eu HEH} HE@$gHE؋@HEHHHE؋ HΉ1HEH} HE@$,HEHPHEHPHEHPHEHHEHP HUdH+%( tUHH H}HEHPHEH@H9uHEHE} tEHEH@HHHUHJ UHH H}HuEHEH HEH~E} yE }/~(}9"HEH HHE0HH HEHn}`~(}f"HEH HHEWHH HEH@}@~(}F"HEH HHE7HH HEH} tE E > UHHEEE}tt}wu UHHEEE}Tt}Wu UHH H}HEH/E} x} t UHH H $ H H $ H HHHxdH%( HE1H HǸ y w HH HDž HHHH tHH HH'HH tHH HDž JHH x9 t0HHHЈHH vHHH HHHLxHAЉ ulwHUdH+%( tUHH}HE]UHH}HE]UHH}HEH= H]UHH}H} HuHEH= Ht ]UHH@H}dH%( HE1HE HEH HEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHcHEHEHEHUdH+%( t~UHH@H}HudH%( HE1HEHEHEH HEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHbHEdH+%( t}UHH}HE@ ]UHH}HE@]UHH}HE@ ]UHHH}HEHfUHHH}HEHfUHHH}HEHhfUHHH}HEHGfUHHH}HEH&fUHHH}HEHfUHHH}HEHfUHHH}HEHfUHHH}HEHfEf} tf} tf} tf}u UHHH}HEHYf UHHH}HEH8f UHHH}HEHfUHHH}HEHfUHHH}HEHfUHHH}HEHfUHHH}HEHfUHHH}HEHUuHEHft UHSHH}HuHEH0HEH"f9t HEHtHEHwt H]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEHEHEH H HHEH H ]UHH}HEH ]UHH H}uHEHHUHHHHHHEHEH%E} tHE@% HE@UHH H}uHEHrHUHHHHHHEHEHE} t HE@ UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH H}HuHEHHEHEHHEHEH9Es &HEH+EHHEHHEHH豼UHH0H}HuHUdH%( HE1 HEHeq HEHȃHt HUHEHH^HUdH+%( t#xUHH}HuHUH} t[HmHE HUHEHHMHUH HEHEH;EsHUHEH uHUHEH ]UHHH}HEHUH}uUE E E]UHH}Hu HE t HEHmH} ݸ ]UHH H}HuHUHMH}w.HUHEHHH! Hƿ THEH+EHHUHEHHHZt'HEHH Hƿ UHH}} y UډEUHH}} y EUHH}Uډ UHSHH}HEH4tHEH؉ډHEH uHE H]UHH}H} t HE u ]UHH}HE <]UHH}} yEE Ǹ :cUHH }EE} yEk}bEE EEulU} y1E؉EщHp Hƿ iUEUHH}uUMUEƿ$ $iUHH }uME ΉE} y EEkEUHH}H} tHEHH#EHu ] UHH0}HuHUH+ HE HEH-HEH} HEH HHxu rHEH، HHRu LHEH HH,u &H} H HMHUH5 HǸ e ;Es HE H HUHMHH UHH}HEH~ HEHE] UHH HH`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1H H(H( tl $Dž0 Dž40 HEH8HPH@L H0H HΉA$HHdH+%( tq UHH |dH%( HE1|d roW HEHƿ z|| 6 HEH+ HEH= w)HUHEHH d HǸ 踇 HEH= wbHEHx fH*HHH fH*X ! ^fH~HEfHnH d HǸ G`HEHx fH*HHH fH*X ! ^fH~HEfHnH. d HǸ HEHH Hƿ aHEdH+%( t8pUHH}HE] UH} ] UH ] UH ] UHH ] UHH H}H} ttE HE@xxHE@x gEHE@xHEH H_HEHǀ HEH Hm_HEHǀ UHHH}H} HEHVHEH H#_HEH HEH@H_HEH@ HEH@8H^HEH@8 HEH@HH^HEH@H HE@P HEH@@ HEH@ UHH}HE uYHE % = uCHE u2HE@<u#HE@uHE@fu ] UHH}HE <] UHHH}HEH6tHE@<@u UHH0H}HuHUHMLELMH} tHEHu HEЃHt?HuHMHUHEIIHHHs Hƿ U HE HoHEHUHPpHEHUHPHEHHHEHP HEHHHEHP(HEHP(HEHP@HEǀ HE@xHEǀ HE <?uHE@| HEHE@|HE@}HEp HEPhHEHMMHHEHPHEH@HthHEH)MHHEHHEH HtIHEHHHEHP8HEH@8Ht(HEH@8HUHMHHP ?HUHEHHH) Hƿ HEHZ UHHĀH}HuHUMHEH HEHEH HEHEH@HEHEH@XHEHEH@`EHEH@HHHHHEE EHcHEHH:{ HEHE@9E HE@ HEH@HEHEH@HEHE؋ HEHH~v HEH} u1HUHEHHH- Hƿ _: HUHEHH9Es1HUHEHHH+ Hƿ M_ HE 9Et@HE@u1HUHEHHH$ Hƿ HEHHHEHHHuHUHEuQIIHHH Hƿ HEHcHE HHHEH} u1HUHEHHH$ Hƿ V HEHUHPXEHcHHHH HHHHEHHEHUHEH<EHcLMLEHUHuHEuWHHE} tE HE@tHE@~HE@~t.HE@tHE@uHE@EEHcHEHP`EEHH;E UHH H}uE HEHHE%UHEH9EuHE"EHE HEH,9E|Ǹ UHH0H}HuHUE HEHHE9HEHEH|IHHEHH芫uHE"EHE HEH9E| UHH HHHHLLHEHHEHdH%( HE1HH& HHIĤ HǸ #}HHHHIHѺ H6 y.HHHt Hƿ ^ HHPbHHH H5c Hv y8HHH; HHE Hƿ . HHaHHHxHDž #HP9t+H HH9rHH}9u>HHIHb HHH Hƿ VHHHHHHHHHHH HUdH+%( t~d UHH}HE@0] UHH}HuE FHEHHXEHcHHHH HHHH9EuHE EEHcHEH@`H9r ] UHHPH}E _ E E HEHHXEHcHHHH HHHHEHE E HEHHhEHcHHHHHHEHEH HEH@hP HEH H7_HEHEHSEE JHEH@hH UHcHHH HEHEH;Eu EHE t E EE;E|EEHcHEH@pH9} t} HEP|EEHcHEH@`H9 UHH HdH%( HE1HH HpHpH HxHH@hHEHEP HxH]HEHEHxHCHELXL HPH`HuHpHHWH$WH3H44 t 4 H`Ht H`H HpH( HE$ HEP HH@AAȉHH~ Hƿ H`Ht H`@HBLHXPHP8$HPXHX@Hƿ qHHEHPHEH@Hu HEH@HEHH@8HEHP8HHEHEHHhDž0 HhHxHAHEHh@<<HEHHEHhPHxHLHEH} y7HH@HUHHH| Hƿ HE HPHUHEHHHEH} HUHEHHt8HH@HUHHH| Hƿ " HEH 0HHH Ht6HEH 0HHH @| HEH 0HHH HH@HUHHHy| Hƿ n HPHPHUH)HHH@0HEHuHP@Hut8HH@HUHHH=| Hƿ HEȋ@DDHEHHEHhHH(HxH- HEHEȋHH,HEHj- HEHE؋PHE@1% t\HE@ HE؋@ HH@HUAAHHH{ Hƿ ( HEH HEH HEHEH 0HHH Ht8HEH 0HHH H9EtHEH 0HHH @| HEH 0HHHEHH} _ HUHpHHt8HH@HUHHH{ Hƿ -: HEHH,HEH+ HEHEHt8HH@HUHHHz Hƿ H`HtH`@HE HE u HE HE@ HE 9tl HE HE HELHHEL HH@HUHWVQHHH\z Hƿ H HE 9@tlHE HE HELHHEL HH@HUH@WVQHHHfz Hƿ xH HEH@0HHЋ8DʉHEH0HH@<HUHDQAIHHHwz Hƿ H ,HEHFHEH} x HEH;EtFHH@HuHMHUIIHHHqz Hƿ HEHH@<HUHDQAAHHHtz Hƿ 6HHUHMHEHH>0Hh HEH=90 HUdH+%( tX UHH0H}HE iHEHHhHUHHHHHHEHEHu,HE u HEH E} t E HEHEH@pH9Er UHHpH}HuUHM}u HEH HEHMHEȺ HH]E} y*HEHHVy Hƿ / UHEȉHSHEHEHbHEE HEHEH H~SHEHE؋HEH H/9HEHEHEH HPqE} y2HE HUHщHx Hƿ j UHEH HRHEHE؋HEH H8HEHE u#Hx Hƿ HEHgt*HEHHx Hƿ U HEH} HEHEH?tHEH! HEUP HE@HEHP HEH6HHEHPHEH@Hu J UHEPTHE <?uHEƀ HEHE@0 HE@4 HE؋PHEP8HE@< HEHw HHku HEP@HEƀ ( HHEHPhHEH@hHu HEH@hHEHE؋@H諢HHEHPHEH H褛HHEHHEHHH_HHEHPHEH@HtHEH Ht HEH@Hu HEPHE؋@ЉHEH@H9s1HUHEHHHv Hƿ * HE؋@HEHHE@H HEH@HHH8UHEP HEpHMUHEAIȉHHv Hƿ EHE HEH9E UHH0H}E HEH EHcHHHHHHEHE ubEHcHEHH_ HHEHHa HEH} u_MHEHHUHuHEHE} tE$EEHcHEH H9O UHH0H}HuHUHMHEH]H Hƿ JHEH} u1HEHHiu Hƿ KH3 HEH HEHH]H} tHEHMк HHFHEHhHHE HHHE. HojHEH} tHE HEǀ HEHUH HEHUH HEǀ HEǀ Z HUBPHEƀ HE UHH H}HEH H HEH HHEHǀ HEHǀ HEHǀ HEH H@HEHǀ HEHǀ E HE苀 xHE苀 GEHEǀ HEHǀ HEHǀ UHH HHdH%( HE1DžT HHH Ht#HPs Hƿ ` HHH Ht3HHH HHH HH誣HX HHH HǸ HH HH yn ؉THpT HΉ " H`HHH H`HHr Hƿ T HH HXHX uHʝHHHH HHH=r Hƿ DžT` HHHXH HXH\t8DžT_HHH HHr Hƿ <# HXHet8DžT_HHH HHq Hƿ HXH HhHHHhH HHH HuH藜HHHH HHHq Hƿ tDžT_Q HHH HXHHItH+HHHH HHHfq Hƿ DžT_ HHH HXHHM| HHuE豛HHHH HHH4q Hƿ DžT_nHh@fu!Hh@ftFHh@f= t5HHH HH q Hƿ 'DžT_ HHHTHUdH+%( tK UHHH}HEH @<u +HEH HHp Hƿ ] UHH@H}HuHUdH%( HE1H} u-HEH HHp Hƿ >_pHEHHEHE@ HUHEH9HGHEHHHEHHHEHPHEH HHHAp Hƿ HUdH+%( tJ UHH0H}HuHUdH%( HE1H} tH}t-HEH HHo Hƿ V_EHE EUHEPPHE@PHUH Ho Hƿ HUdH+%( tI UH}} t} u ] UHH0H}HuHUH} uQHUHEHHV HEHUHEHHX HEH} tHEH@HE؉ UHH0H}HuHEH HEHE HUHEHH.Y HEHE@ HE@<tHE@<upHE HEHHT HEH} u.HEHH~n Hƿ HXHUHEHH{u HE;HEHEH@HHHHH9EH& UHHH}uUHEHƿ? h< UHH Hm HgE} y A E UHH H}HEH@pHPHEHpxHEHhHѺ H r E} tEHHd HEHphHEHPpHJHEHHpHHHHHHEHEHUH(HUBHE@yHE@HHHE@,HEƀ HE UHH0}܉uؿ cHEE UEЃM EEHHEHEHEHUHEHHHu HHHEHHEHE UHH H} bHEHE@0t!t)HEP<HE@8։/HE@<HE UHH@H}HuHUdH%( HE1HEH@`Hu HEH;Eu HEA A! Hƿ zHEH}u ^HEHEHEHEHUHEH9HGHEHH`HEHH.*HEH@`HUHHgHEHUHP` HUdH+%( tD UHHPH}HudH%( HE1HE HEHOHEHUHEH9HCEċEăvE HEH. H/]Ht E 3EH H)HUHEHOHEHUHEH9HFEHMuċUHEHuAIȉHBj HǸ xZHHEHEH.HHE HHH u HE <_tHE <.tHE _HEHE tHEHH9ErHEHm$HUdH+%( tyC UHH0H}HuHEЋ@Tu HEЋPTHEH HR?HEHEHIt HEHHEE HEH:EUHEHEH H>HEHEHuHEHo t EHE E;E| UHHPH}؉uHUȉMLELMHEHHEHEH`tHEHB HEUԉP\HEUЉP HEH@ HEH"HHEHPHUHEHHHUHBHEH@Ht HEH@HuBHEH@H1HEH@ HEH@H1HEH@ HEH0HEHE HE@ HEHEPHE@ }t}u HEPHUHEHH1 HUHEHHtHE@HEPHEpHEHH HEP HEH@AIȉHHf Hƿ HEHJHEHEA A! Hƿ uHUHB`HEH@`Hu~؝ ؉EHEH@` HEH@UHHf Hƿ (HEH@H 0HEH@ HEH@H/HEH@ ElH} tHEH@`HUHMHH$HEH@HUHRhHMH)HHHHH?f Hƿ UHH0H}E E HEH EHcHHHHHHEHEH@H HEH@H@Hk HE G 5 EHcHEHHK HHEHHIM HEHEH@HxHEH@H0MHUHEII HE HEƀ EHcHEHH8K HHEHHL HEHEH@HxHEH@H0MHUHEII HE^EHcHEHHJ HHEHHqL HEHEH@HpMHUHEIA H'E} tE$EEHcHEH H9+ UHH H}HuE MHEH UHcHHH@HUHH:uHEH UHcHHEHE苀 9E| UHH0H}HuUE tHEH UHcHHH@HEHEHGHEHH9u7EHcHMHEHH4uHEH UHcHH EHE苀 9Ey UHH H}HuЈEHE@(td }mu4UHEH@HHb Hƿ }yHEm}yu HE [}mu HE IHE =HEU1UHEH@HHb Hƿ a HE@ UHH0H}HuHUHE@(t5HEH@HUHHHjb Hƿ HEH FHEHEHPHEH <"t5HEH@HUHHHOb Hƿ HmHE@,HH9ErOHE@,pHEH@HMHUAIHHH*b Hƿ DHE@,HHEHEHHHUHEHH HUHEH HE@ UHH0H}HudH%( HE1H HMHEغ HHzHUH t6 ؉EUHE؉HHa Hƿ sE7HE t'HEHHa Hƿ C HUdH+%( t9 UHH}HuHE@,EHE@,u KHE@8t*E HHEHEHHHEHUHHH] UHH H}HuHUHE@(tMHE@(tAHE@(t5HEH@HUHHH` Hƿ = HE@(u<H}v5HEH@HUHHH` Hƿ HUHEHHt<HEH,HEH@HUAHHH` Hƿ sHE@,tFNt.Dtt8HEHE1HEHEf"HEHEHEHUH HE@ UHH`H}HuHUdH%( HE1E HE H X` HH+/t t HE= H\OHEH} u*HEHH#` Hƿ . HEHAE̋EHHPHEH < uEHHPHEH HE HEH u1HE =HEHH_ Hƿ HUHEHHrHEH} t HE@ t z HE@4HcHEHHEHEHHEHE ytyV"t2"|LmwDHE HMHEHHE HUHMHEHHE HUHEHH5Eȃ} t3HEH@HUHHH^ Hƿ E HE@(t>HE@(t2HEH@HUHHH^ Hƿ VHUHMHEHHEȐ} tE0HEH@HUHHH^ Hƿ Z HUdH+%( t54 UHH H $ H HHH@dH%( HE1DžP H`HH`H HHHR^ HǸ !JTT y " T ~ HH^ HH9jHXHX u H] HH] HjHXHX uH] Hƿ ! H@HHHHHPP t-PHHH] Hƿ 轿$HHX HH9HuHXH,~PHUdH+%( tb2 UHH H $ H@HHHdH%( HE1Dž HH;=HHH] HH迭HH U ؉H\ Hƿ 趾 HHHHHk t-HHH\ Hƿ Q HH HXHuHH>HUdH+%( t0 UHH0H}HE E 3HEH UHcHHHEHE uHEHEEHE؋ 9E|H} u qHEP4HE@,HHEHE؋ HMHEIA H[ HE} tE HEH@pHE؉ UHH0H}uHU؋UHEH ,HEH} t8HE؋U-H} t HEPHE؉HEPHEH+HEHEHuHEHuHE UHH0H}uHU؋MHE HBHEHEHt 8HEHHUHEH HEHEHtHE UHfEE H HZ HHZ H>HAZ H:Z H2Z HrE H Z HZ HZ |HZ sH Z jH Z aH Z XHZ OHZ FHZ =HZ 4HY +HY "HY HY HY HY ] UHHH}HEH UHH@H}HuHUHMHEȋHHEк HHEHEȋHEЉHkHEHEH tCHEHgHHUHEIHHHY Hƿ 7 HEPHEЉH,)HEH} u8HEHHUHEAHHHzY Hƿ ܹ uHEH蓯t@HEHHHUHEIHHH_Y Hƿ 艹 "HEHHEHEPHE UHHPH}HuHUHMdH%( HE1HEHHE HHEHEHEH HEHEH蚮t6HMHUHuHEH EӀ} t EԉHEHE HEH跮tVHEHŮtCHEHHHUHEIHHHfX Hƿ X HEH肭ft.HUHEHHHcX Hƿ [HEHt#HEHsHEHE@HcHEH#HEHbHEHEHdHUH HUdH+%( t* UHH0H}HuHUHMHMHUHuHEIHHW HǸ @E} yEHH;Er UHH H $ H0HHdH%( HE1H uHXW HHHfHHH H tHHHH6HUdH+%( td) UHH HHHLLdH%( HE1H )HHE0HHƮH@Dž, U H@HH HHHH u5,HHHV Hƿ 聵D HHH V HHbluUHHHH@HHH]t H Ht HHHU HHkuUHHHH@HHHt | H H HHH8U HH~kuUHHH H@HHHyt H @H HHHT HH kuTHHH H@HHHt H H HHHiT HHj H8H@HHHt ' H@ tVHP 89tB8HP HAȉHHS Hƿ 8HP H H9 HHHS HHi H@PHH!HXHX u9H@PHHHlS Hƿ N HXHާtBHXH"HHHHHDS Hƿ HXPHHHhHh yEHXPHhHIȉHHS Hƿ 臱HhH H@ tXH@ H9htCHP HhHIȉHHR Hƿ HhHP HXPHPH HA HHHR HHg H8H@HHHt I H@tVHP89tB8HPHAȉHH R Hƿ " 8HPH H[ HHHQ HHf H@PHH HXHX u9H@PHHHQ Hƿ p3 HXH tBHXHDHHHHHQ Hƿ HXPHHH`H` yEHXPH`HIȉHHGQ Hƿ 詮H`j H@tXH@H9`tCHPH`HIȉHH'Q Hƿ A H`HPHXPHPH Hc HHHP HHdS H@*H@+* t HP HP HP) t-HHHP Hƿ Z 09,t7HHHHHHP Hƿ *t;+t-HHHP Hƿ ɬ H@tHH@t9HPHHHaP Hƿ s6 H@ H@PHHTHXHX uDH@HHPHAHHHP Hƿ HXH覡uHXH5@t7HPHHHHO Hƿ 蒫U HXHH HAHXHXHtLHXH8HHPHIHHHO Hƿ HXHH HHX+ t\HXH蒡 HXHHHHHH<O Hƿ v9 HXHHtBHXHJHHHHH,O Hƿ HHpHH:O HǸ N3HHXHHpA IHH44 t 4i H H HHHN HHk` ) t-HHHN Hƿ 3 H8H@HHH0t 8t@8t58HHHJN Hƿ 质w 8HP$H H HHH!N HHi_u`H8H@HHHt H8HHP(H Hp t7HHHHHHM Hƿ ˧ HHHHHHM Hƿ 蔧,H@ ,;0H@u*HHHeM Hƿ ? HUdH+%( t UHH H} 6EH} u wuHE HHHHu!MHE HHPtHE<E EEH9Es EEe u;EsHE UHH}HE@0t HE@0 u ] UHHH}HuHEPHEP0HEP HEP4HEPHEP8HEPHEP<HEP HEP@HEHP(HEH HEP HEPDHEPHEPPHEPHEPTHEH(tHE@<HoHEP<HE t-HEPHEH@HHK Hƿ IHE t9HEH HEPHEH@AȉHHK Hƿ :HE t-HEP HEH@HHwK Hƿ ɤHE t9HEHHEPHEH@AȉHH[K Hƿ 腤:HE t-HEPHEH@HHOK Hƿ IHE t-HEPHEH@HHEK Hƿ HE @t-HEP HEH@HH;K Hƿ գHE % t/HEHP(HEH@HHH-K Hƿ 藣HE % t-HEP$HEH@HH!K Hƿ [HE % t-HEP HEH@HH K Hƿ HE % t$HEH@HH K Hƿ UH}}t&}w)} t}t HJ HJ HJ HA ] UHSH H8H0,(L DȈ HEHdH%( HE1f)E)E)Ef)E)E)EH0HH,HcHHHHHHPHPH8H HHXHXH~H`HXH8H HHhHh tHh u+,HI Hƿ [ HP@HP@HH H@H9s-HhHHI Hƿ HXHtBHXHHHhHHHaI Hƿ 諠f H` tCH` HHhHHH@I Hƿ Z HXHH8H H HpHpHtBHXH HHhHHHH Hƿ ԟ Hp@HPR9s-HhHHH Hƿ 菟J H8HHxHxHptHxHO HhH HHxHPHxH@Hu-HhHHfH Hƿ Hx@\ Hx@0 Hx(P HP@HxHP ,HxPHHxHH HxP HhIȉHHG Hƿ ^ H8H HxH@LEH}HpMIHLL t L HUHxHHEuZHHxHHLL t2HxH@HHhG Hƿ 蚝LT E% DWHHxHPpHxH@pHu HxHXp6CHxH@p@yHxH@p@ HxH@p(P HhHHHxHZpH]HCHxH@pH@Hu|HxH@pH@HhH A HHǸ oHxH@pHUHH,HxH8HHfO LL tL HUdH+%( tH] UHHPH}HuHUȉMLELM +HEHEH H}HEHEHEHUHEHHHu HHHEHH9Es5HMHUHEIHHHuE Hƿ wvHEH\HHEH HEH HuEHEH HUHMHHHEHUH HEH HEHP` UHH`H}HUEHE HE y A HE HcHEHH~ HEHUHEHH HEH} tH} u:HEH HHD HHD Hƿ J HEH H1EE UHEH H HEHEHuPHEHEH HHEHEH!D HHPuHEHEЋUHE EE;EpH} u-HC HHD Hƿ d HEH莎EE LDEHE H}UHuHEHuEIHlHẼ} tEy EE;E|E HEHHhEHcHHHHHHEHE@0! HEH Ht@HEH HPHEH@HHH<C Hƿ f HEHUH HEH HtUHEH HxHEH HHE HuHEIIȉHC HẼ} tEkEEHcHEH@pH9HEH Ht:HEH Hu*HB HHB Hƿ 芗 UHH H}HuE H} t(HEH HvHE@ EH} tHEH H v HEH@ HEMHUHEHEEu HEHZEEu HEHEEu HEH&EE UHH H}uEHcHEHHV HHEHH^ HEH} u HEH@H UHH}H} tHE <?u ] UHH H}HE HU EHE HU EHE HU EHE HsU EHE H_U EHE HKU EHE H7U EHE H#U EEuMEuBEu7Eu,Eu!EuEu Et UHSHhH}HuHE HT EHE H}T EHE HiT EHE HUT EHE HAT EHE H-T EHE HT EHE HT EE E 8 UHEH7HEEtHEHuEt9HEHJt)HE@ HE@ HEH E HEH HEH^HEHEHZHEHEHEHMHE"HE <.t HE <?uHE _HEHE uHEHjEE HEPE THE@ HEȉPHEHEȉPHEHEHHEHEHEȉEHE HE E;E| EtcHEH誉tSHEHEH[H+t3HEHEH;HEHE <?C HE _7 EtFHEHt6HEHQEE HEPHE@ Et HEH興tHE@ Et HEH]tHE@ Et*HEH趈tHE HE@ \ Et*HEHÈtHE HE@ ' EtHHEH t8HEH@HEH މEHUB E HEH } uCHE H5.< H`E} yE UHEHHEHEH5HEHEH茅EE HEPE UHE؉PHE@ EHE E;E|EHEH'U9 H] UHH}HE y HE uHE ~ ] UHH}HE ] UHHpH}HuHUdH%( HE1EH} HEH@HEH H*HUH HEH H!E} t<HEHǀ EH: HH: Hƿ ǎg HEH HfH} C HEH Hu2H3: HH]: HH`: Hƿ b HEH@HEH HVuHUH HEH H E} t<EH9 HHI: Hƿ HEHǀ HEH HHEHEH H(HEHEH HHHEE 0 EHHDHEHEȋ@ HEȋ@H H;GHHEHPHEH@Hu E E HEH HE EHEHEH HHEHEHuLHUHEHHE HEH} t1HEHHHEH@UHcHHHЉʉHEȋPHE@HHEHEHHEȋ@ HH9EEEE} t.HEHot H8 Hƿ ,E HUdH+%( t UHH}HuHEHEHEHEHEPHE@)] UHSHxH}HuHUdH%( HE1E HEH݀EHEHEHgHEE H} u#H18 Hƿ [ HEH) HH?B? HEH'8 HH!B! HE@ujHUHMHEHH$E} uEu5UMHEAȉHH7 Hƿ 踊 UHEPEE HEHZHE HEHEHHEH} tHEHSt*HEHH7 Hƿ 2c HEH׃HEHEЋ HEЋ HEȋHEHHEH} u/UHEHHU7 Hƿ 跉 HUHEHHDHEHEH|t1HUHEHHH=7 Hƿ _ } tHEH@HEPHE@tHE@u HE EHE E;Er]HEH豂HHH H0 HUdH+%( tH] UHH0H}E HEH Hu HEH H+ EE \UHEH H6 HEHEHNt,HEH HUHEHH9E} tEEE;E| UHH}HE tHE u )HE uHE u ] UHHH}HEH UHH0H}HEH Ht,HEH @TtHEH0 Hu E @HEH UHcHHHEHE uHE@8t EHE؋ 9E|HEؾ HHE>HE@|uHEHt pHUHEHHHEH} uHEؾ H9HE.HEHt #HUHEHHy9HEH} u˸ UHH H}EHEH( HuHEH Ht EtHEHWt cHUH( HEH( H`E} t2EH3 Hƿ uHEHǀ( E UHH`H}dH%( HE1HEH HEE HEH Hu HE HD t?HEHUt E H3 Hƿ 辄 [ E 2 HEHHXEHcHHHH HHHHEHE@ HUHEHH' HEH HEE UHEH H2 HEHEHzugHEH4uVHEHEH H@HEHEHHEHH:u ~HUBEE;EVEEHcHEH@`H9HEH>E} HEH HUHHdHEЋUHEЉH HEHEHE} tE HEH H2[HUHEHHE} tEa HEH Ht_E HUHEHHcHEH} u " UHEH HMHHQ' HEȾ H4DHE HEp HEHh HEH` HEAHK E} tH} u4HEH#HEH H3HEȾH{3HEH} tVHEHE} t H 0 H"0 UHH40 Hƿ nEtE EHUdH+%( t9 UHH H}HuHEH HEH HUHH^7HEH} uEBHHEH HEIHHH/ Hƿ HE UHH H}HuHEH HEH HUHH6HEH} uEZBHHEH HEIHHH(/ Hƿ 2 HE UHH H}HuHEH HUHHk"HEH} uEAHHEH HEIHHH. Hƿ HE UHH0H}HuHE HEH HEDHUHEHH HEH} u BHUHEHH@6tHE#HUHEHHHEH} u UHATSH H}HuH} u hHEH>*HEH} uM@IHEH HEH MHHH. Hƿ ~ HEH [A\] UHATSH H}HuH} u HUHEHH/HEH} u sHE HEHH]HEH} uM?IHEH HEH MHHH~- Hƿ } HEH [A\] UHAUATSH(H}HuH} u HE HUXHEH} urP?IHEL HUHEHHHHuH - HEH$ MMHHH, Hƿ | HEH([A\A]] UHH}HuHEH H@HHHHH9Er "HEH HHUHHHHH] UHH}HuHEH@HH9Er HEH HUHH] UHHH}HE H M, HHm UHHH}HuHE@u HE@=Lou HE@u1HEH@ Hu$HEH+ HH2u HEHCt {HE H + HHuWHEHEHt @HEH& HH/2tHEH& HH2u UHH}HuHEHEHEHEHEHPHEH@H9t#HEHPHEH@H9s( !HEHP HEH@ H9s ] UHH`H}HEH HEHE HE E E HEH HEH HHt@ <HHEH HHH:* Hƿ y_e HEH H3HHEH HEH Hu % HE HUHEHHwHEH} u _ HE@ HEH Ht0HEH HH) Hƿ 'y_ HUHEHH^HEH} u _x HEHEHEHUH HEU HE@(HEH HUHEHHHEH} HEH Hu0HEH HH ) Hƿ ^x HE HEH?EHEH EHcHHHHHHEHUHEHHHEH} u _n HE HEHH HEH} u _B HUHEHHc HUHEHHHEH} u _ HE@HEHHHE@(AHEHpHUEWQEIHщH2( Hƿ ,wHHEHU( HH.u3HEHPHEHHEHH^E} E^ HEH( HH-u3HEHPHEHHEHHE} Y E HEH' HH|-u#H' Hƿ [v HEH HH?-uHEU HEH! HH-u#HE@t _x HEHE HEH! HH,u#HE@t _; HEHEn HE@^ HE@5 HEH@H$ HEH@HtSHEH% HHX,u HEU MHUHuHEHt|E} E HEH& HH,t HE H & HH6u'HE HEHUHPHEHUHP\ HEHf& HH+t HE H O& HHu'HE HEHUHPHEHUHP HEH& HHE+tNHEH HH++t4HEH% HH+tHEH% HH*u/HE HEHUHPHEHUHPHEƀ eHEH HH*u!HEHUH HEU G HUEHщHn% Hƿ `s HE@ j HE@,EHEH@8HuEHcHEH H9r _ UHEHZ HEH% HH) HEH % HH) HEH% HH) HEH$ HH)t{HEH$ HHl)taEHcHEHH*HHEHHHuH" uHMUIAH$ Hƿ r HE HEHUHPHEHUHP HE@u]HEH$ HH(t HE H u$ HHu$HE HEHUHPHEHUHP6HEHH HUEIHщH1$ Hƿ CqHUHEHHHEH} HEH HtHEH UHcH9s-HEH HH# Hƿ p_KHEH@`Ht'HEHp`HEH@XHHѺ HhHUHMHEHH UHH}HE@EHE@fu%}t}uHE@u ] UHH}uHE@EHE@EHE@9Et 4} u }u !}t}u }u ] UHH0H}HuH} u HEH7EE UHE؉HgHEHEH=ftHEHe HEHE؉HHEHUHEHH%uZHEHetHEHh tFHEHxetHEHit EEE;E' UHH0H}؉uH} u HEHEE wUHE؉HKHEHEHBeuJHEHgHEE HEE9uE1EHE HEH c9E|EE;E| UHH@H}؉uHUȋMHEغ HuHEHEHE؉HaHEH} tHE HEHb s t ` HEHZeEEt HE@u 3 ) H} t EHUȈHE@u HE@t#HE@wHEPHE@!Ѕt HE@t HEH HHV#t }HEH HH+#t \ UHEHxd@u ;HEH^d HEغ Ht UHH H}HuHEHEHEHEHEHE 9t$HEHE 9s HE udHEP0HE@09t HEP0HE@09~T MHEP,HE@,9t HEP,HE@,9}" HEHPHEH@HH! UHH H}HEHEE >UHEHHEHEH`tHEHb< uEEE;E| UHH@H}H} u HEȺ H 3 HH#E܃} y UHEȉHHEHEHcHEE 1HEHEȉHHEHEH|`u EHE HEH^9E|HEH^9Eu QHEHEUHEȉѺ H5 H E} yH Hƿ 7iE UHH HHHDžx HE HHH Hu B HH HcHHHHHEHUHHHHHEH} tHEH@8Ht _ HHH Hhh y h HEH@ HUHJ8 HllH Hƿ hDž\ \ \HcHHHHHEH} u _5 HEHX HE HHHHkHEH} HE HHH HEHH HcHE@ HHaHEH} u HHHUH HH HHHEHE@ HHH PHH HHH HUHH%HUBHE@5HEPHEHHt Hƿ fHE@ HE@HHH HuHEHEHHH H#HUHBHE\PHE@<HEP!HEH@H>@ HEHEH@ HEH@HH9Et9HEH@HUHHHHEHPHEH@Hu HEPHHH HHUB HE@ ?HEH HEPHEAȉHHV Hƿ @eHE@ HE@ HHH H'HEHEHHH HչHEHEHU HH HEH{[t8HEH@H# HHH Hƿ d HEHxHE HEPHHH HWHEP,HE@,5HEP,HEHH Hƿ dHE@,` HEPHHH HHUB0HE@03HEP0HEHH Hƿ c HEHP8HE@HHH HHUB(HE@( HEHHe Hƿ Gc HEH1 HH+u;HEHEHE HEHP8HEHHHH Hʥ.HEHH Hƿ b \\;lHH H Hƿ ybHH u HH HcHHH H{HѺ@ H H} ; HHH H.phHHH HHEDž\ lHHH \HcHHHEHE u7HEHHHEP\IȉщH Hƿ ra\HH 9\{HEHEHEH{VlDž\ Dž` HEHZH\HcHHHHHHEHEHHH HHEHEHHH H葵HEHUHHHHHEH} u9HEHHHEHH7 Hƿ Y` HEHV HEPHHH H0HEHEHYHEDžd adHH HEHЋ@t<dHH HEHЋ u dHH HEHHE dHEHT9d|hHEHE@f HEPHE@HEP HEHX pHEP`HEPHE@ \``\;l`HEPHx & HxHEDž` Dž\ HHH \HcHHHEHE HE@0ttP`ЙttHEP4HEP4HE@,Љ`HEHpHEH4HEP\IAȉщH Hƿ ]\HH 9\"`HEPHEHRlDž\ HEHcWH\HcHHHHHHEHE؋HHH HlHEHEHHH HHEHUHHHH螒HEH} u'HEHHG Hƿ \@HEHV HE@4HE؉P\\;l UHH}HuHEHPHE HH9] UHH H}HuHE HHEOHUHEHHu HEH HUHH(uHE/HUHEHH:HEH} uj, UHH}uHEH EHcHHHHHȋ w ] UHH}uHE 9E] UHH}uHE 9Eu SHEH EHcHHHHHȋ t w!tt ] UHHĀH}HuUHMLELMHEH@8UHHHEHEH@pH@pHEHEH@pHEHE@EHEHp_tZHEHWtGHE HEH MHUAAHHH Hƿ @Z[J HEH& HEH@H EHE苀 EE ,HEH UHcHHHEHEЋ@9EtEE;E|E;E|:HEH MHUAHHHl Hƿ Y[ HEЋxHEHpHEH UHMQAIHHe Hƿ ?YHHE <u HE HE UHEPHEUP HEH]2 HE@<t-HEH HH Hƿ X[ } tHE苀 9EtcUHEHH`HHEHHHEHEH HMHUIHHH Hƿ >X[H HEH@Ht?HEHHHEH HUIHHH Hƿ W[ HE UHEPHEH@HEP } t } v:HEH MHUAHHH Hƿ wW[ HE苐 HEH3 HEH@HuHE؋@HHtIHE؋pHEHHHEH HUAIHHHs Hƿ V[ HE UHEPHEH@HEP UHEH#EUHEHHiHHEHHHEHE苀 9Eu`HE UHEPHEH HEH@hH)HHHHEPHEH@HEP } UHEHMt;HEH HMHUIHHH Hƿ U[ HE HEHHhHUHHHHHHEHE@\9Eu~HEP HE@9uhHEHP HEH@H9uSHEHH HED@ HEHxHEH HUȋuVQEIHHH Hƿ THHEHEH;EAHEH;Er?HEHHHEH HUIHHH Hƿ T[ HE UHEPHEȉHEPHE@ u UHEHgt4HEH HUHHH Hƿ T[) HE HEHHhHUHHHHHHEHE@\9EuiHEP HE@9uSHEHH HED@ HEHxHEH HUȋuVQEIHHHV Hƿ xSHHEHEH;EVHEH;Er1HEH HUHHHX Hƿ *S[7HE UHEPHEȉHEPHEH@HEP UHH}HuHEH@ H9Er HEHP HEH@(HH9Es ] UHH8H}HuHUE HEH@`EHEH@`H E+E EЉEHEHHXEHcHHHH HHHHEHEH@H;Er HEH@H9EuHEH@ H9ErEE EEE;EoHEHHXEHcHHHH HHHHEHEH@H9Eu HUHEHHtHE UHH H}HuHxHE@,HEHEH H9Er 0 HUHEHHHEHUHEHHMHEH} u _ HE HEHHHEHUHEHHAHEH} tH} u HMHUHEIHHH Hƿ lPHEH@ HUHz8 HEE A EHcHxHHHEH} u/UHEȉHH Hƿ O_ HEH@H HEHUHEHHHEH} u7MHUHEAHHH~ Hƿ O_ HE@HEH H9rEHE@ȋuHUHEAIHHHV Hƿ 8O_; HEH HuHEHHEH@H9r:HEHMHEAHHHQ Hƿ N_ HEH HEHE@u<HE u2HE@HEHHgHHEHHHEHE HEHHHEHEHuH HEHuMUHEIAȉHH Hƿ NUHMHEHH[HEH} u7uHMЋUHEAIȉHH Hƿ M HE@PHcHEH@H HHGHEH} u HEHUHPHHEH@ )EHE@PHcHHHHHHEH4LEH}HMUHEMIH!E} tE&HE@PPHEPPEE;E UHH H}HuHEH Hu HEP HE苀 9tHEH[t `HEHtFHEHPHEH HH3E} yEHE@P UHEPT UHH H $ H H $ H0HdH%( HE1.HAȉH) HǸ 'HX H>HH/ HHe!HH t ؉HHH Hƿ BKg HHH HHǸ uH HHH HHǸ xuHP HHH ^ HHǸ 9uHP vHHH 1 HHǸ uHP:HHH HHǸ uHPHH HHHHi HUdH+%( t谼 UHH}HE ] UHHH}EHEH t EHEU UHHH}EHEHWt EHEU UHH}HE ] UHH HxtdH%( HE1EX EHE HCHUHMtHΉ+%E} t# uHUtH։9E} tED HEHHjE}u>UHxH@HMHHHpuHxH@HٛHEHEHHÛHEH} uS ؉6D t Ǹ wE} y ؉E Hx@U։EE} HxH@HWHxHUHPUHxP0UHxP4UHxP8UHxP<UHxP@UHxPPUHxPTHxƀ HUHxH HEH蹩E CHUdH+%( t蛹 UHH}HE@<] UHHH}HE@0~ot HEH@p UHHH}uHEH t B9HEUP<HEH菟tHE@<H֞HEP< UHH0H}EHEH Ht<HEH u*HEHH Hƿ E HEH HE} t EHEH HuH HEHE HǸ 3E} yb ؉E} t H! H HUHuM}IIH HƸ D} tE# E *EEޮ} Et7}u1HEHUHHH Hƿ XD } t Hc H[ HUHuM}IIH HƸ D} tEh a\ HHEH HEH HuE #HE؋U HEH UPX UHH HhdH%( HE1ƅ`aaaafDžb Džd ƅhiiiifDžj Džl Džt Hp HsHh t Hh AH HHHDžp D\HHHHH HHHHHHHH H(HHH0H8HHH@HHHHHPHXHHHhH Ht G pp t!pH Hƿ mAtHcHH`IIHH H¾ pp y?tHcHH`IIHH H¾ `pp ypL pHpp HΉ肆 HxpHxAHHK HH Hƿ w@pp褪 HUdH+%( t; UHHH}uHEH Ht 7HE tHEH UH Eƿ UHH HdH%( HE1DžX H H%HHHΉ t) u HH։ tN Hp HΉ HHщHL Hƿ > H@09uqH@49u] H@89uI H@<9u5$H@@9u!H`HH H9u HUdH+%( t7 UHH HXdH%( HE1HXH H`` b ؉ddu4HXH HHG Hƿ = : d؉Hp HƉU HhHXH HhHHH Hƿ L=d `HXHHt>HXH HH Hƿ <`0x`HXHd`d td=HXƀ HXH HH Hƿ r< HUdH+%( tM UHH H8H0dH%( HE1H0@\PDžH H8H H H0H8H0HP`H8H@hH0H)HHHƉH8H H Pt PuAH8H@hH0H)HHHH8H H H0HP`H0@HH ՜TT tr ؉THpT HΉ赀 HXH0He HHXHH Hƿ :T Pt P H0@ TT tr ؉THpT HΉ HXH0H HHXHH Hƿ :T> H0HfH`H0@@% H0@@% t DžL DžL H0HH0H@`LH`A Aȹ HHhHhuJ ؉TH0H HTH Hƿ 9TUH0HhHP`<H0H@`Ht,H0H@`H`HHRH0H@` HUdH+%( t蚫 UHH}HEH uHE t ] UHHP HHЈdH%( HE1H8 H譭f)0)@)Pfօ`HDž08 H0H8HHH@HHH HHPHXHHH`H HH0HHDž Dž H H tHH@HH@( H@ H@DHH HH $H t HH)Et=H@XH@Lx H@L ̀ HH HtVHH H{x<HH HaH@PH@T H _ HH@pH HH@pH t HHHpH HH& t:HH@HHT Hƿ N5 HH@pPHP,H@,xH@,H !u} HHH H!Hu% Hu>HDž Dž Dž H@P H@T Dž HH H t)HH@hHH)HHHHDH HD@HHH0HH HWHWH HH@HHx HHHPH LHMAI u ؉Hp HΉx HHH@HAHHH, Hƿ 2Dž Dž Dž H@P H@T Hx HHHPH LHMA6H h[tjHH@pHtZHH HtHH@p@HH@pHՙ HH@pHHH@p y2H@9u H@։/HUdH+%( t苤 UHH0H}HudH%( HE1E E { HEH@xUHHH HQ HEH@xUHHH HEHE@EHEH HtbHEH@hHUH)HHHEHEH@hHUH)HHHHEH HV HEЋ@HUHu AE} tZ ؉E}HEHpUHEH@HMQAIHH Hƿ 60HE uHEHHUHEH@AIȉHH Hƿ /EEHEЋ E9nHEH@xH豒HEH@x HEǀ HUdH+%( t~ UHH0H}HudH%( HE1HEH Ht ^ E HEH@xUHHH H HEH@xUHHH HEHEH<EHEЋ@HUHu 莐E} tY@ ؉E}HEH0UHEH@HMQAIHH Hƿ .HE uHEHUHEH@AIȉHH Hƿ ?.EEHEЋ E9HEH@xH HEH@x HEǀ HUdH+%( t͠ UHH H}E cHEHHhEHcHHHHHHEHE t-HE@0u!HUHEHHE} yE EEHcHEH@pH9r UHH H}HE@0uzHE@<uo)E} y.HEH@UHHy Hƿ ,E8HEH@UHH Hƿ ,UHEP< UHATSH H(dH%( HE1Dž@ H(HHh@HHHHHHPHPHYt)H( HtHPƀ HP t,HPH@HH Hƿ +& HPHwHH / ƅ? HPH H HPH7HH t,HPH@HHx Hƿ B+ ? tDHP@y6HPH@HHe Hƿ *DžH HP t8HPPHPH@HHA Hƿ *L HPH( HH"HH HPPHPH@HH Hƿ B*HPHWt1HPH(HHHH ] HP@0!E HPXHPH HtA A HPHQVHHPH A AD HHPHB`HPH@`HuX ؉HHPH@` HPH@HHH Hƿ )H H(H HtZH(H H(H HPH@`HHH(H H謋H(Hǀ HP t;HP@0t,HPH(HHHH HPH H HP HP HJHH tf?tHu ƅ?FHPH HPH@HAHHH Hƿ '2@@H(H@pH9 - H`H HΉ!m HXHPH@HHXAHHHx Hƿ 'H(DžD DžL H(HHhDHHHHHȋ@x2H(HHhDHHHHHȋ@ېLH(HHhDHHHHH@DD;@YHHUdH+%( t)H [A\] UHH}HE <_tCHEH <_u4HEH <_u%HEH <_uHEH <_t ] UHH H}HEHͣHEHEE'EHcHEHH[t EHm} yHE UHHH}H} t HEH H4HEH( UHSHxH}HuHUHMDELMHEPHEH HHEHEHEH HKHEHEH苼EEE UHEH輓HEHUHEHHm L HEȋHEHVyHEHEH|!# HEHHEHEH;E HUHMHEHHy HEHiHHEHiHHE@uHMHuuSAIHщHX Hƿ #H HE@HcHEH HH HEH} umHE@HHHHEHHEHEHUHUHEPHEHUHHE@PHEP EE;Eg H] UHH HhdH%( HE1Džp HhH t HhH Ht HhƀH Hh HFt k pHpH։7xx t u / x t/ u#H Hƿ " x t;l ؉xxH Hƿ !x p)|| yS { ؉xpxщH Hƿ ^!xD Džt HE HǖHEH#HEE@ HtHM|HΉExx t=a ؉xpxщH@ Hƿ EtHEHF HHu|ˊn HhH( |H։ HEHEHxx t6pxHEAȉHH Hƿ HhHP HPHhHX HhH@ HѺ Hh xx HhH@ HhHP HHHhHP HHHEHEHUHpHEPHE|PHEH)sHHEHPHEH@Hu(Džx|gx HUdH+%( t UHHpH}HuUdH%( HE1HE HE HEHEEEUHEH踍HEH} uH HEHEHXsHEHEH~tHH HEH~HEȾ HEH} uH T HEH8 Hu HEH( HEHMHUHuHEIA H x HE} HEЋ@t HE HEH8 Ht HE HEHrE} E qHEH( H"AHEH@ UHcHHHHHEH@ UHcHHHH}HuHEIHE} u*EEHcHEHP H9uHE HEHgEHHHUdH+%( t蠏 UHH H}uHUMMHUuHEA HF UHH H}uHUMMHUuHEA A H). UHH}HuHE] UHH}HuHUHEH;E] UHH0H}HuUHE@PHcHEH@H HHHEH} ugHE@PHcHHHHHHEHHEHE HEU܉PHEHUHPHEHUHPHHE@PPHEPP UHH}uE HHEHHHEHcHHHHHHEHE uHE@9Eu HEH@EHE@P9E| ] UHSH HHH@<H0L(L dH%( HE1H HHHDž` HHH HhH@@XXH0HEHpHp u HpH0HnHxHx u H@@ 7 XH`H(HH HHH@pXH0HHH`H`H{ tzH`HZ HHpHI^HX<HhSxIAHH Hƿ HH`H H`HXH(A A H \\ tH`H9\EH`LH0<H@HhH MIH HHUdH+%( t2H] UHH HhH`dH%( HE1HE E HhH @Tu H` tgH` H4HhH8 HhH8 H`E} t&EH Hƿ uEV HCHH#H舢 HEHEHO tHEH1 EY HhH HHHEE HEH HE HEH@UHcHHЋ EEHEHhH HkHEHEHt E HEPHEHH Hƿ uDž| HEHHE> HE t , HE EEHcЋEHcHhHHwHEH} u3M|HEAȉHH Hƿ HE@| UHEH@ )ȉEEHcHEH@@H9r HEH@8UHcHHHEȋUHMHEHHkE} t6HEH M|AȉHHD Hƿ .[ HEH@pH H HhH LEH}|HuHEMIH E} t6HEH M|AȉHH Hƿ HEH LEЋ|HMUHuMAH E} t=HEH uM|AAȉHH Hƿ 6f|HE@HEHE@|9HEPHE@HHEHEHHE@ HH9EHhH8 HoHhHǀ8 HEHtyDž| KHEH@|HcHHH HE HEH@HHEH@HEH} u݃||HcHEH@ H9rHEHp EHUdH+%( t UHH@H}uUHMDELMHEHHHEH }ԋuUHQAAHHl Hƿ HE FHE HEPPHEPPHEf@ Eԍ@DwHE؉PHEE}~ UHH0H}uUHMDELMHEHpHEH MUIAȉHH Hƿ HE HEPPHEPPHEf@ E䍐TwHEP UHH@H}HuE H HEHHHEHcHHHHHHEHEHP8HE@HHHHEHE H H HH H>HEHHhHE@HcHHHHHHEHEH Ht$HEPPPHEPHEPy HE t$HEPPHEPHEPF HExHEPLEHMuHEMAH\ HEHHhHE@HcHHHHHHEHEHHEP HEHʉPHEH Ht$HEP`PHEPHEP HE t$HEP PHEPHEPm HExHEPLEHMuHEMAH= HEH HE@HHHHEHE HEH Ht$HEP`PHEȋ HEPAHEP PHEHHhHEȋ HcHHHHHȋPHEPHEHPHE@4B HE@8tBHE@ t6HEP0PHEP4HEPHEHPHE@0B6 HEH@(HEPHEH@(H HHEHP HEH HE@HHHHEHEP PHE@ t#HEP4HEPHEP<HEfP HExHEPLEHMuHEMAH}zHE@<@tjHEH U܉HH Hƿ UHEHEH UAȉHH Hƿ M EHE@P9E UHH H}HuHUHMLxLpHE HE E HEH HE- HEH@UHcHHЋ EEHEHPEHH9 E HEHHEnHEȋ EUHEH@ H9r@UHEHH HEH@(HH9sGH} uHEHEHE@HEHHEEHE@HEHEЋ@U9rH} u v Hx HE@HHEHEH+EHHEHHEHEH HUHH&eHEH} u HEHUHHE@HE HHxHEH+EHHUHEH HEHHH=cHEH@0HEH@ )ЉEHUHEHHEHUHEHHE+HEHEHE EHEHE@HEHEH;ErHEPHp >HEPHEЋ@HHEHEHHE@ HH9E UHH0H}HuHUHEH HtHE Ht HEH;EtHEH H HEL HEH HEH HEH HPHuHEMIHE} }t0HEH UHHw Hƿ En HEH Ht+HEH HH| Hƿ ^ E3 HEH HH Hƿ 3 HEH;EtHEH Hu HEL HEH HEH HEH HP(HuHEMIHE} }t-HEH UHHN Hƿ E`HEH Ht(HEH HHV Hƿ PE(HEH HH^ Hƿ ( UHH}HuHEH HEHEHEHE@HH9Eu HE@HH9Es ] UHHH}HuHE@Pu *HE@PHcHEHpHHELg H? UHH H}HuHEPPHE@PЉEHEH;Eu EHcHEH@H HHzHEH} u} t HE@PtQHE@PHcHHHHHHEHHHHE@PHcHHHHHHEHHHH^HE@PESEHcHHHHHHEHЋ@HEH@0 EHcHHHHHHEHЉʉPEE;E|HEHUHPHHEUPP UHH@H}HuHUHEHP@HEHP0HEHP@HEH@@HHEHEH@8HM HH$ HEH} u-HEH HHB Hƿ HEHUHP8HEHUHP@HEH@@H HEH@8HMHq8HMHI0HHHH4]HEHHEHP@HEH IHHH Hƿ HUHEHH|E} tE UHHPH}HuHUHUHMHEHH/Eԃ} tE HE HEHP8HEHH0HEHHHHEHEHtHEHE HUHEHHiHEH} tHE k H} tSHE tHHE t=HEHEH HUAHHH Hƿ [. H} tPHE u)HE@ HHHHE@HHHHE HEP HE@HHHEgHEHPt4HEH HUHHH} Hƿ /[ HEHP HEHHE@HHHHEHEȋ HcHUHEHH@HEH} u-HEH HHB Hƿ [ HEH@0HuPHUHMHEHHaEԃ} tE HUHMHEHH~Eԃ} tE HEHP8HEHH0HEHHHHEHEH@0HEH@0HE)BHEPHEHH0HEH8HEpHEH HUHQIAHHH Hƿ HHEHEH@(H9E UHH H}HuE [HEHHXEHcHHHH HHHHEHUHEHH芤uHEH@0 EEHcHEH@`H9rHUHMHEHHE} tE UHH H}E YHEHHXEHcHHHH HHHHEHEH@HHvcHEH@H HE@P EEHcHEH@`H9r UHH}HuHEHEHEHEHEPHE@9t HEPHE@9}: 3HEHE 9t HEHE 9s ] UHH H}E iHEHHXEHcHHHH HHHHEHE@Pt+HE@PHcHEH@HHHѺ H"EEHcHEH@`H9r UHHPH}HuH4 HEHEH)}HEHEH HtHE H蛾t R HEH H耖EE UHEH H# HEHEH HEHM HEHEH HwHEHUHMHEHHi HEPHEH H藬 HEHEHuHEH.t-HEH HH Hƿ 7 HEHEH H wHHEH HH舴 HE xHEǀ HEHEHEHat-HEH HH Hƿ E HEHHXEHcHHHH HHHHEHUHEHH! HEHHEHH謳 HE@~u HE@t7HEHHEH HHHF Hƿ X HE x7HEHHEH HHHQ Hƿ HEUЉ EEHcHEH@`H9HE y:HEH HUHHH1 Hƿ EE;E UHH@H}HuHU؉MDELMȋMHE H">HEHEH HEPHEH$jHEHEHouHEH>tfHE tHE uHHEHEH.tHuH3 HEHEH HH蘱u HEHHE HL=HEHEHt _ HEHEHsHuH HEHEH t!HUHEHH u HE t} t t9 HEHt~HEH1 HH螰ud HEHktMHEH HHju3 lHEHt HE@u I HEH HuȋMHUIAHHH Hƿ UHHpH}uHUUHEHS HEHEPHEH: HEHE EHEHEHE@EHE@EHEHE̋UHEHݮEЃ} y E UHEH跦 HEHEHUHcHHHEHE EHE@HEH HHgE܃} tE UHEHL HEHEHWUHcHHHEUHEEE;EJUHEH0MHEH?Eԃ} y!UHEHإ HEUHEE UHH HxHpHE H HEHxH HEE HxH HtHpH Hu Hx Hft E IEHHHH Hp 9u EHHHH HHE EEvH} u - Hp HHEH} u E MHpH Hp EHHEHEHEHH HEHЉʉEHp U9rE HEHHEI UHEȉHdHEHEH HE؋HEȉHnHHEHH. HE؋@EUHEȉH蕣 HEHEH HEH( HEPHEȉHP HEH} r HEH[ HE E QEHH HEHЋHE؋@9u,HpH Hp EHHEEHp U9rH} HEHOEHEH E} E;E HEHUHcHHHEHEHEȉH%mHuH* HEHE@AH}MHUHpHEIH3 HEPE9u6HpMHEȉHXE} y EE UHEP} uGHMHEȺ HHgEUHEȉHE} x} y E HE@NjUHuHEȉщHE} y E HEPHEȉH HEHEPHEȉH HEHEHUHcHHHEUHEP EE;EHEHU HEHTE UHHPH}HuHEH HtNHUHEHHẼ} t&ẺH Hƿ E HEHHE HEHHXHUHHHH HHHHEHE ]HEHHHHUHHHHHHEHEHP8HE@HHHHEHE uHEP@PHEHE@PHH9ErHEHEH@`H9EGHE w HEHHXHUHHHH HHHHEHUHEHHד' HE@| HUHEHHẼ} t0HEH ỦHHV Hƿ E HUHEHHẼ} tE HE HEHHXHE HcHHHH HHHHEHEH@0HuTHUHMHEHHdẼ} tE\ HUHMHEHHẼ} t E4 HEHEH@`H9EwHE HEHHXHUHHHH HHHHEHUHEHHA HE@| HUHEHHẼ} t-HEH ỦHH Hƿ EiHUHEHH:Ẽ} t1HEH ỦHH Hƿ AE HEHEH@`H9E UHSH HXHPHHDžl Džp HE HE HE HE HX tHXH Hu HX HXH H\HEH} u HPH@ HPHZ8 HtDžd w dHcHHHHpHEH} u+dHͼ Hƿ _= HEH@H HHXHHoHEH} u=HEH@H HdHщH Hƿ v_ HE HXHHkHuH, HEHEHEH0HEHHHEH@H HNjduRIIHH> Hƿ HDžh HXHHhhHcHHHHHHEHEP HX 9ulHEH]HHE@HHHHHHHEHE@HEH H9r,HEHlHHHEHHE@ȉH9s)hhHcHXH@pH9.hHcHXH@pH9u<HEHHUdIHщH[ Hƿ HE@0bHE@0cb t HK HF HEb HE@HX 9t2HUdHщH Hƿ [| HE@0 uHHE@4t<HEHPdA HщH Hƿ ( HUHXHH.nHEH} HUdHщH Hƿ s c HUHXHH*HEH} u2HUdHщH Hƿ q HEHPHE@H9u7HEH@ H HEH@H9uHUHXHHt<HUdHщH Hƿ [ HEHXH HtWHEHEȋHHXH H+HEHEHhfu HEHHHEH>HHHHH HHEHE؋HXH H<HEHEH HH诞t HEHHEЉHfxHEHHE@H)xH9s HEH HE@)+xxlx щȅt m lx xHE 9x x|pHcЋ|HcHEH@xHHHEH} u HEHUHPxHE |)pHHUHJxHU HcHHH¾ H[HE| b tHEHEHUHRxxHHHHEHPHuxdHuIAHщH Hƿ Hdd;tw H] UHH@H}E ? HEH EHcHHHHHHEHE HEH@HEHEH@HEHE@,EHE@ u } xEHcHEH H9r( HF Hƿ \ HEH EHcHHHHHȋ u HUHMHEHH c EEHEȋ 9Eu HUHMHEHHLEHUHMHEHHE} tE0EEHcHEH H9HEHH UHH}HuHE u[HE % = uEHE u4HE@u%HE@uHE@HE ] UHH0H}HudH%( HE1HEH@8HEHEH Ht E HUHEHHucEqwps WrwO%HEؾ H訢t8HE@ +HEؾ H胢tHE@- EHEEHcHEH@@H9Y HUdH+%( teU UHH@H}HuHUdH%( HE1HEȉEEt'HEH@p Hݡt HE@ EtHEЋ@HEЉPHE؋ u EtHEЋ@ HEЉPE t2HEH@p HctHEǀ 0 HE@ 0 E HE؋ E E HEH@/ HlHEH} u*HEH HH Hƿ fHEHMHUHuHEH j E} tE;EHE؉ EHE؉ EHEЉP(EHEЉP HUdH+%( tS UHH H(H HLDHEH dH%( HE1Hp HUH HHHDž p H HHHHHHHH H(HHH0H8HHH@HHHHHPHXHHH`HhHHHDž` HDžh HDžp ƅ?H @h@H t tC H HPH H HHH Hƿ % H u0H H HH Hƿ ~ H t u H( HtH H H`H H H H H H(H H H(H HK H( H4 H(H HKH H HH H H H HH H @H H(Hx HH( H( t H H@H H H@H@(H H H@L@(H H@HPHH HHAЉLL y9H H LHH~ Hƿ L= H H@8HH H@@H(H Hu H(H@XH H)HH)\(\HNjLcH HH H(H LHWHWH; HH p @ H H@XHt0H H@XHpH H@`Hhƅ? H(H` Ht6H(H` HpH(Hh Hhƅ? HDžP HhHHXHXHPH9HCHhHhHpHH3HxHx uDžDJ HxHpHp ƅ?HpHHh@HcH LHHH`MIDD @ t9? t0H H HpHHH Hƿ H( H( H诘 DžH H H@pHHhHHcHHHHHHH@\ HHD Ή`tte Hp HΉ) HHHPH H HIHHHD Hƿ HHHcH(H@pH9H DDžD # @ uDž@ ? t u H9h ؉DHhHpH HHM ҧ Hp HΉ HH H HHHHm Hƿ D? tJHp t@Hp t2H H HpHHH Hƿ ? tHpH9DHUdH+%( tpI UHH}HuHEH;Eu 4HEHHEHmHEHH;ErHEH < uHE] UHH@H}HuHUHMLELMHUHEH HUHEHHH)HEHEHSHEHEH;E HEH9E HUHEH HUHEHH9r6HUHEH HUHEHH)HHEH)HHEHE /HEH+EHUH+UH9sHEH+EHHEH+EHHEHUHEH4HUHEH HEHH>5HUHMHEHH, UHH HHHHLLHEHxdH%( HE1HHH HHǸ K% HHHH HH@pH HH HHH HH H^ = v Hg H HHIIȉHA H¾ \HxH+IHHHHHIH)HEdH+%( t#F UHH HHH@H8H0L(L HEHdH%( HE1HHH@pH`H\HXH(H5 HǸ CI \-@Dw\\ \HcH`H@pH9 H`HHh\HcHHHHHHhHhHHXHpIȉH HǸ \[HH+(IHpH(H0H8H@IHHEdH+%( tD UHH HHH@H8H0L(L HEHdH%( HE1HHH@pH`H\HXH(H5 HǸ G \-Tw\\ H` \9 H`H \HcHHHhHhHHXHpIȉHߥ HǸ YHH+(IHpH(H0H8H@IHHEdH+%( t C UHHPH}HuHUHE H} HEHNHHEHEHPHEHHEE HUHEHH+HEH} HE H * HH:uXHUHEHHHEH} LEH}HMHUHuHEHuMIH8H HE H Ӥ HHX:uXHUHEHHsHEH} LEH}HMHUHuHEHuMIHH HE H x HH9uXHUHEHHHEH} t9LEH}HMHUHuHEHuMIHH(EHEHE؋EHH;E^ UHHPH}dH%( HE1HEH@pHEE HEHHHEHcHHHHHHEHEH HEЋ@HHHHEHEЋ N t ; HE؋ / HE؋@HEH HR<H0t EHEЋxHE؋@8HE@!HEHpHEH DEHWEA Ht{ H HEЋHHE@!HEHpHEH HQA A H({ HWHEЋ@EHEH@@EHEH@@EHEH@@ EHEH HUHHI EHE@P9EA HUdH+%( t> UHH0H}؉uHE UHEHHXHUHHHH HHHHEHUHEHHE} tEu HEHEH@`H9ErHE 2 HEHHXHUHHHH HHHHEHUHEHHn HE@|t(HEH HH Hƿ HEPhE HEPhHEH Ht HEHHEHHxHE؋xPHEL@HEH@@AHEHP8HuHEHQADHHE} t.HEH UHH Hƿ IE)HEHEH@`H9EHEHG UHH H}HuHE H(<HE HEH@HC HUHBHEH@Hu3HEHPHEH HHH Hƿ HEH@PHE HEH@P HE HEH@H@ HtZHEH@HH HEH@HPHEHHщE} y-HEH UHH Hƿ E'HUHEHH ;HEH} UHHpH}HuHUHMLEH} tH} uH菻 u=HEHuH) HH* Hƿ \H`DH H} t7HEHHEH X HtH H} tHEH Hv HEH@ HuHEHEH} t*HEHEHEHH Hƿ HEHHʞ Hƿ H} tHEH H?v HEH@8 HEH} tHEH HGv HEH@@ HEH} tHEH HKv HE@H E̸H;EsH H} tH} uH H} tHEH HWv HEH@P HEH} uH HqHEH} t%HEHDH= vHjn HMHUHuHEHHEHEHYt HE9 HEHUH` HEHUHh HEỦp H} t6HEHHHEH HEH Hu E H} tHEH H7v HEH@0 HEH} tVHEHCH= v Ej HEHNHHEH0 HEH0 Hu E4 H} tHEH H/v HEH@( HEH} t6HEHHHEH HEH Hu E HEH{EȋEȅu HEHEȋEȅu HEH0JEȋEȅu HEHl[EȋEȅu HEH;EȋEȅuHUHEHH,EȋEȅuHUHEHH5EȋEȅu HEHEȃ} uHEHHEHEH|EHH UHHH}HuH} u *HUHEIй HHs UHHH}HE H1 UHHpH}HuHUdH%( HE1H} tH} u SHUHMHEIHH @ HǸ LHuHMHUHEIHƿ *H躿HUdH+%( t5 UHH H}H} u"k HE E HEHHhHUHHHHHȋ@x*HEHHhHUHHHHHȋ@,EHEHHhHUHHHHH@HEHHhHUHHHHHH@hHtVHEHHhHUHHHHHH@hH@H$HEHHhHUHHHHHH@hH@ HEHEH@pH9EHE 5HEHHXHUHHHH HHHHHEHEH@`H9Er UHH H}HE HqtHEXHEH?Ku-HE H辀tHE@@HEP@HUHEHHtHEH} u UHH0 HHdH%( HE1Dž H^ HH HFHH u;А ؉H Hƿ 1 H HHHIH5 HǸ g|uHHuvt-Hu Hƿ 觿DžDHHH LHAЉ u5HH?HUdH+%( t"2 UHH@H}؉HUHMEHEHEHEH HHDHE}du*H} t#HEH+EȉHMHEHHHEHUHEHH,HEH} t HE t HE@HEH H-HEHEHVt HE@ tGHEH@(H9Et9HEHP(HMHEIHHH Hƿ OHE@ t;HE@ HEHUHP(HUHEHHH Hƿ 讽 UHHH}HEHH]H UHHPH}HuЉHMLEfEHEH( HEHE UHMHEHHvE} HEHE} tE E KHEH@ UHcHHHEHEH HEUHMHEHHu E}u EEHcHEHP H9r} HEHUHHEHUHE UHATSHpH}HudH%( HE1HE HE HEHpHMHUHEIHѺ HE} yH}uHE@!t HEH@HHH Hƿ ʻE HE@8EUHEH*HEHEHEHsHEHEHHEHUHRHEȋMHUHEH uH觞E} HEH UH@*HEHEЋHEH HHEHEȋHEHHEHEHHDeHEHHHEH@Hu؋UHuSATIIȉHHP Hƿ 蒺H wHE@ HEHt HE@ HUB0HEUP4HEHNHHEH@HuUIIȉHH; Hƿ HUdH+%( t,He[A\] UHH@H}HudH%( HE1HE HE HE@8EHEH@HuHEH@HMHUH}IHѺ HEԃ} yH}uHE@!t HEH@HH Hƿ 9EX UHEH4(HEHE@E؋MHUuHEH HKE܃} gHE@!t HEHt HEH@H_~ HUHRu؋MAIH5 Hƿ 菸 HEH HE@ HEH H= u7HEPHEH@HH Hƿ )F HEH HuHEHǀ HEH HPHEH HEHx HѺ HbU E܃} tE HEH HEPHUHEHx HEH HpHMH HH BHE@ HEUԉP4HEHt HE@ HEfP<HEHt HE@ HUB0HEHt HEH@H| HUHRMAHH4 Hƿ HUdH+%( t) UHH0H}E HEH UHcHHHEHE HE@8 HEH Ht HE@ HE@0 HE@4 lHE@HEH H3%HEHEH tHUHEHHEHUHEHHE} tE EHE؋ 9E UHH@H}HuE E E HE HEȋ u HEȋ x.HEHHhHEȋ HcHHHHHH@`HEE X HEH UHcHHHEHE u HE@8t E E HE HE@4HcHEHHEHE HEH@ H Q HH u E HEH@H HHykuD0 HEH} HEH@HHݎ Hƿ 7> HEH@H HHku HEȾ HsHE HEH@HƎ HHjuHEȾ H~sHE`HEH@ H HH uHE@!t.HEH@HHz Hƿ dk HUHMHEHHE܃} tEC HUHEH@HHH] Hƿ .HEH@HHg Hƿ EHEȋ 9E} H} HUHMHEHH(E܃} t E E @HEH UHcHHHEHE uHE@ tEEHEȋ 9E|} t&HUHEHHE܃} t } t HEH@E܃} t } t HEHE܃} t E HEH UHcHHHEHE@ t:HE@!t+HEH@HH Hƿ EOHE@ t$HEH@HH Hƿ EHEȋ 9EQ UHH@H}HEH@hHEHEP HEH H H HEE gHEH UHHH HEH} tCHEHEHEHPHEH@MHHȋ HHEEHcHEHEHEHr9Er UHH H}E ^HEHHhEHcHHHHHHEHEHVu HE uHEHEEHcHEH@pH9r UHH0H}uHUH} uϫ HE t/HEHH_ Hƿ 9葫 HEH Ht*HEH@pHEH@`HEH uH9 HEHiEEu HEH3kEEuHE H(EEuHEH HEHHEEu HEH+EEu HEHEEu HEHYEEu#HEH0 HuHEHUHH EEu HEH(EEu HEHPEEuUHEHEEu HEHEEu HEHEHEH HtZHEH HtHEH H&_} u,HEH@pHEH@`HEH HO EHEHx H!HEHǀx E mHEH@ UHcHHЋ@7HEH@ UHcHHH HHEH@ UHcHHH@HEEHcHEHP H9yHEH@ HoHEH( H|HEHǀ( HEƀ } u E HEHHhEHcHHHHH tYHEHHhEHcHHHHH t,HEHHhEHcHHHHHȾ H肂EEHcHEH@pH9bHEHHEH HH Hƿ aE蹧 UHHH}HE H UHH HHdH%( HE1DžT HHHHXHX u HXHH`H` Ht{ t { ؉THXHp T tTT؉Hp HƉ! HhHhHHHHH Hƿ THUdH+%( t UHH@ HdH%( HE1Dž H u HHHH u HH~HHHHH諂t`y Hp HΉ HHHHHH Hƿ y ؉HH u>HJH9t-HHH Hƿ 跨DžHUdH+%( t UHH HXHPdH%( HE1HX@xy5HXH HH/ Hƿ 1艤/ HPHdd tdY HPHdd td) HX@xHPH։{t{x ؉dHpd HΉF HhHXH HhHPIHHHu Hƿ 7d茣5HXH HPHHHf Hƿ HUdH+%( t UHH H}HuHE@xy/HEH HH1 Hƿ 蛦wHEHE} t EҢVHEHE} tv ؉諢/HEH HUHHH Hƿ UHSH HHH@dH%( HE1HH u(Hà Hƿ ƥ L HH@y6HHH@HH Hƿ 肥ڡ HHH H H@ tyHHH H@HH6\tUHHH HHH襈H@IHHHN Hƿ @n HH HHH HHH:HHH- Hƿ 臤 H@ u:HHHHH. Hƿ H蠠 HH t:HHH謇HH Hƿ T H@HHHHH HHH Hu)t ؉T HHH HcTT tT֟ HHH HVTT tT蟟 HHH HH@H։ts ؉T?HHƀ HHH HH Hƿ ɢ WT؉H` HƉp HXHXHH Hƿ xT͞HUdH+%( tKH] UHSH(H}HuH} u(H Hƿ t[ HEH H H} tjHEH HEHHXtLHEH HEHQHUIHHH Hƿ 藡 HEH HE>H} u7HEHHH Hƿ H蠝 HEH*E} t E|fHEH E} trq ؉U?HEƀ HEHnHHEHHU Hƿ 跠 H] UHH H}HuHE H} t)HEHQHEH} up ؉Ĝ'HEH HAHEHUH UHH}HEH ] UHH}HE ] UHH}HE <.uHE _HEHE uސ] UHH H $ H@HHdH%( HE1H u H t(H Hƿ U譛 H HvRH HDž H H t[HH}HHH H. u\HHHHHH Ht0HHHH7 t cHHHHQHH aHH HtH HtHHHHEHH u%HUdH+%( t UHH H $ H@HHdH%( HE1H uƙ H HPH HDž H tmHH诀HHH H` tC HHHHHH Ht7HHHHes tט4HHHHOHH HUdH+%( t UHH H $ H0HHdH%( HE1H uBp H t(Hs{ Hƿ 譛3 H H H|HHHH H u`HHHH u;HHHH@ HH v HEHHHH H%uHHHHPHHHHMHH u͖HUdH+%( tK UHH H $ H0HHdH%( HE1H un H H' H HHHH H% tjHHHHO tѕ3HHHH HH X HUdH+%( t UHH H}HuHUHEHHA'E} t EL@HUHEHH.E} t HUHEHH=pE UHH H}HuHUHEHHE} t EΔ-HUHEHHoE} t E覔 UHH H}HEH@pHt,HEH@pHHEH@pHHEH@p HEH@xHHEH@x HEǀ HEH@`Ht=HEHP`HEH H H9t"HEH4HHEH@`HH-HEH@` HEH@hH HEH@hH@HAHEH@hH@ HEH@hH H HEH@hH HEH@hH@HHEH@hH@ HEH@hHHEH@h HEH@HHEH@ HEH@HHEH@ HEH HHEHǀ HE@x.E HE@xHE@ EHE@ UHH H}HEHY HEH H讯 HEHǀ HEH H: HEH茷HEHHEH HHEH( HHEH HODHE *HEHHhHUHHHHHH1HEHEH@pH9ErHEH0 H:HEHǀ0 HEH HHEHǀ HE EHEH HUHHH@HHEH HUHHH@ HEHE苀 HH9ErHEH HHEHǀ HEǀ HEH@hHhHEH@h HEH@p HEH@XHtZHEH@`HtMHE 5HEHHXHUHHHH HHHH裗HEHEH@`H9ErHEH@XHHEH@X HEH HHEHǀ HEH HHEHǀ HE苀 ~HE苀 HEH HWHEHǀ HEH< UHHH}H} tHE UHH}H} t HE@P ] UHH}H} t HEH ] UHHH}HEH HtHEH H UHHH}uHE t ʎHEUPP UHH H}HuH} utH} t-HEHHEH q H̍t@ KHEH} u HEHUHHEHUH UHH0H}HuЈEHEH@`HEH} u H} uF} t HEH@X HEHHXHUHHHH HHH- H HEH@pH9Et.Hq Hƿ a HEH@XHUH)HH)\(\HH} t HHHEHEH@`HUH9sH} y (HEHHXHUHHHH HHH UHH H}HuHEHEHMHE HHHEH} tHUHEHH|3uHE UHH H}HuHEHEHMHE HH)HEH} tHUHEHH 3uHE UHH}uUHE ] UHH}HEH ] UHH}HEH@] UHH}HE@|] UHHH}EHEH@p t 莋HEUP| UHH}HE@}] UHH}EHEUP}] UHH}HEH@8] UHH}HEH@@] UHH0H}HuHUHEH@p t HEH@8HMغ HHHEH} u1H} t*HEH HHX Hƿ 1<HEH HMHEHHHEHUHP8HEHUHP@ UHHH}H} u - HE@xy HE@x UHH}HE ] UHHH}uHEH@p t ÉHHE 9Eu 2HEU HEHPH H9t HEH@ UHH}HE ] UHHH}uHEH@p t /HEU UHH}HE ] UHHH}uHEH@p t шHEU UHH}HE@h] UHHH}uHEH@p t vHEUPh UHH}HuHEHP`HEHHEH@X] UHH}HuHUH} tH} uPHEH@`H9s7HEH@p t HEHUHPXHEHUHP` ] UHH0H}uUHMH} t5HEHHEH o ( H܆tn њ =uR H} tlHQ HHHN 8 HH HEH} u HEH H H HHH)HHHE%= tņV H뙅 HEH} tHEHH HEHH} tHEH Hut HEUPHEUP H} tHEH Hv HEH@ HUHBH} tHEH Hv HEH@ HUHB H} tHEH H v HEH@ HUHB(H} tHEH H'v HEH@ HUHB0 HEPH} tH HH ۘ HE@ UHSH(}܃} H t5| 9Eu*8 HN HFw E *H EHcHHH)HHȋ@9EtEEHcH H9rEHcH H9u蟄 H EHcHHH)HHH HE{H ~ EHcHHH)HHH5_ EHcHHH)HH8HH HZHHXHJHZHHHXHJ HZ(HH HX(HR0HP0EEHcH H9oH喅 HHږ H Ӗ HԖ 8 HH袁HEH} u H Hu HEH H] UHH H}HuHEH H HEHEH HUHH </u@HEH HHHEHHEHHu HEH HUHH <+u\HmHEHHUHEHHt MHUHEH tHUHEH </u " HEHHEHH= UHH H}Hf EE FH [ EHcHHH)HHHEHUHEHHt HE EE;E|Ee E CEHcHHH)HH7 HHEHUHEHH8tHE%EE;E| t H UHSH8EEܠ EHHEHEH} u + HE E EHcHHH)HH 7 HHE} t,HEHP(H.H9 HEH@H HEHHËEHcHHH)HHH6 HHkHHUHcH9sHEH fHEH:HHEHf EHcHHH)HHH=6 HHEHH%EEdHEH] UHH0H}HuHUH} u HEHsHEH} t!HEPHEHEP HE؉ kHEHH h Hƿ 0 HEH} t,HEHH)h Hƿ HEHG UH}}8v EH Hm0 H] UH}}v EH H 2 H] UH}}!v EH Hm2 H] UH}} v EH H]3 H] UHH(H}uHUHE wHEHHhHUHHHHHHEHEHMu=HE@ 9Eu2HEH@ H9Er$HEH@ HUH)HE@8H9sHE HEHEH@pH9Ew UHHĀH}HuHUHEH HEHEH@ HUHJ8 HEE + EHcHEHHHEH} u(EHDf Hƿ _ HEH@H HHEHHHEH} u2HEH@H HH!f Hƿ 苀_ HEȋ HEHH'HuHD0 HEHEHHE@,HEHHEH} u-HEH HHe Hƿ HEH HEH@ )ЉEHE@EHEH@hHEHEȋ0HEHH HEHHEH@IHEH@H IHEH@}uVQRALHHte Hƿ nH } v>HEHHEH@MAHHHe Hƿ -[; HEH@Ht9HEHPHEH@HHHe Hƿ ~_ HEH@HEHEP HEHHEE HEHQHEH} u3HEH@UHHe Hƿ f~t HEH)wHUH)HHHEHEHEHHEHEHHE HsHu5HEH@HUHHH8e Hƿ } UMHEHH+HEH} u:HEH@HMЋUIȉHH e Hƿ x} HE t5HEHHEH@HHH/e Hƿ 1}BHEH UHHHEHHEHPEHHEHEE;E UH}HuHU}+t:}+wh} tH} w\}t}t NHEHd HHE MHEHd HHE 3HEHd HHE HEHv9 HHE ] UHH HXHPHHDdH%( HE1HHHPHpIHH6d HǸ :ll x lv DHpHXHH 5HUdH+%( tvUHH@H}HuЉUdH%( HE1HUHMEHΉcEHuHUHEHHUdH+%( t UHH H}u&HEHEH E} t%H6c Hƿ zE(wUUHMHEHH.E} HEHHc Hƿ zHEHEv UHH HdH%( HE1Dž H HH HHΉ" t4щH|b Hƿ y DžEu Hb Hƿ y EhHHH0 t(EщHUb Hƿ 7ybHH HH2HH %HHH,b Hƿ xHUdH+%( t UHH`H}HuUHMLEHE HE: H#HEH} tHEHEHEH+EEHEH} t EHcHEH = HHu^H} tHEHEHUH( UHHE} ~ HE HEU }tE HEHTE} tE E HEH@ UHcHHHEH} t!EHcHEH@HMHHuWH} tHEHEHUH UHHE} ~ HEPHEHEU 2}tE'EEHcHEHP H9C UHH0H}HuHUHMHE苀 EHE苀 EE HE苀 t } } u-HEH HH_ Hƿ kv$ UHEHE} y=HEH uHMUAIȉHH_ Hƿ vE HE HEЋU HEH@pH Ht7HEH@pH UHMHH5! HE HE %HEH@pH}HM؋UHuIHE} t5HEH MHUAHHHM_ Hƿ GuE UHH H}HuH} uxq HEHHEH} umHEHH(_ Hƿ t HEH} t,HEHH;_ Hƿ tHEHpNHEHP(HH9t p.HEH@Hu pHEP HE UHHH}H} u ~p!HEHj;tHE@ UHHH}HE@\u%HEH@Hy% HH*t 6HE@\u%HEH@HU% HH*t UHHH}H} u "HEH]t HEH@HEH@ UHH}HE@0] UHHH}uHEHd:t \oHEUP0 UHH}HE@@] UHHH}uHEH:t oHEUP@ UHH}HEH ] UHHH}HuHEH9t nHEHUH UHH}HE@D] UHHH}uHEH[9t SnHEUPD UHH}HE@4] UHHH}uHEH9t mHEUP4 UHH}HE@8] UHHPH}uHEH H&HEH} u HEHuEHEЉH HEHEH,ht2HEHTHH[ Hƿ pZ HEH fE} u2HEHHTHH[ Hƿ p HEHOjHEHcHHHHH HHEHEHEЉH HEHEHHEк HHEHEHet2HEHSHHF[ Hƿ oh HEHIhHEHEHEЉHEă} ~"HE@U)uĉȺ щȅt=HEH SHMEAȉHZ Hƿ do HE@U)uĉȺ EHE HE@ƋUHEЉщHẼ} yE HEPTHEЉH HEHEHhHEHcHHHHH HHEHEHEЉH< HEHE؋UPHE@U)HEPUHEP UHH0H}؉uHEH uHE tj HEH@`H HE؋@0t HEH覚HEHE؋P<Eԉ։HEHUHMHEHH՚E} t2HEHSQHEHY Hƿ mErUHE؉HE} tI}tCHEHQHEHY Hƿ LmHE@T HE@P HE؋UԉP8 UHH}H} t HE@P ] UHH}H} t HE@T ] UHH0H}HuHUHEH uHE th HEH@`Ht HE@\u hcHE@0!uHEH H HE HE@8HEHEH;Et h HEH@`HUHMHH UHHH}HuHEHezt%H} tHE@8HEHHEH@hH@OHEH@`Hu ;HE@0!uHEH H HEHHE@8HEHHEH@` UHH}HE@\] UHH}HE@(] UHHH}uHEH2t ygUHEP( UHHH}uHE@0t%HQW Hƿ jgyHE@,t%HHW Hƿ jfHHEH@pHt,HEH@pH.HEH@pHMHEH@p HEUP, UHH@H}HuЉUH} t HEH@hHu: HEH@hHEHEHHhHEHPpHHHHHHEHEH;Er HEH;Er5HDt HHzV Hƿ i: lHEH@hHUH)HHHHEHHHEHEH@pHUH9sH} y HEHHhHUHHHHH UHHH}HuH} uH} t HEH@hHMHE HH UHHH}HuH} uDH} t=HEH@pHu AHEHHhHEHPpHHHHH- HHMHEHH UHH H}HuHE HtHE HE <.u1HEH@HtvHEH@HUHH u[HE HEHt!HEH@HUHH u*HEWHEH@HUHH u HE6HUHEHHHEH} L7 UHHH}HuHUHEHHH UHH0H}HuHU؉ȈEHEHc.t HE@4H9Et?HEH4HEH@HUAHHHS Hƿ ft HE@y.HEH@HHS Hƿ yf; Eԃt & HE@0 ` HHЃH 6KEE HEP8EЃu EHEEHHEH9E EHHEHHEH@H}uHUHQIAHHHIS Hƿ eHTHE@8H9Et?HEH8HEH@HUAHHHZS Hƿ De UHH@H}HuHUHMLELMHUHuHE HE} t EDaHE@HMHUHu UHH@H}HuHUHMLELMHUHuHE HWE} t E`HE@HMHUHu UHH0H}HuHUHMHuHE HE} t Eo`HE@HUHMHΉE UHH@H}HuHUHMLELMHUHuHE HE} t E`HE@HMHUHu8 UHH0H}HuHUHMHuHE H E} t E_HE@HUHMHΉ UHSHH}HEH/Vt 4HEHUtHEHU؉@3ډ73 HH] UHH H}HuHEHE} y/HEH HHP Hƿ kb^,HEHGNE ƉEE^ UHH}HE@ ] UHH H}E HEH'Ut HE@ t HEH HtHEHHEH҉EHEH@HtHEH@HHEH@HtHEHPHEH HEHfE] UHH}HE@] UHH}HEH@] UHHH}HE@a] UHH H}HEH|(E} y@^1 ؉EUHEHHdO Hƿ `EY] tHEH} uE&]XHEH9HHEUPHEH/HHEHPHEH@HuHEHK\HE UHHH}HE@t r0 UHH H}HuHEH@Ht(\ HEH舴E} tE\ HEH莵E} tE[ HEHAHHEHPHEH@Hu[ HEHPHE@H։<t4/ ؉EHEH@HHEH@ EY[2HEHPHE@HщHM Hƿ ^ UHH H}HEH@Hu ZrHEH@H E} t . NHEHPHE@HщH=M Hƿ G^HEH@H+HEH@ UHH0H}HEHEHEHEE HE@ $ Ǹ 蔻y K. ؉EHEP HE؋@9tHE@ HE؋@HEH@(HtNHE@0t"HE@1HEH@(H E HE@1HEH@(Hq3 EE UHH H}HEHEHEHEHEH@(HHEH UHHp HHdH%( HE1DžH t;HHHH K HWXt,Y y=HH HHK Hƿ K\X HHq y5HH HH^K Hƿ [Xs 8 HH udXD HHHHHYHPHP H t HH Hv H@ HH@p H HP HH t HH Hv HH@ f) )0)@)P)`HDž P H@H H(HHH0H8HHH@HHHHHPHXH HH`HhHHHHѺ) 苲 ymW* ؉Hp HΉ苟 HHH IAHH6I Hƿ Y HP3 H tUHH HvEHH@Ht5HH HH I Hƿ YDž_ $@Ǹ 螶 Q) ؉Hp HΉ腞 HHH IȉHHH Hƿ X HH HHH Hƿ HX HP $ Ǹ ˵ya( ؉Hp HΉ趝 HHH IȉHHH Hƿ W H3 x HHwTHUdH+%( tV UHHH}uMHE H[8 UHH HXHPdH%( HE1HXH HH,HhHh u_N' ؉dHpd HΉ肜 HHXHHHG Hƿ Vd H`HPHhHHǸ ddt{dt & dHpd HΉߛ HHXHHH>G Hƿ UHhHmdHhHV`HUdH+%( t UHHHF HEHEHG HHD UHHH G HEHEHF HH UHHHG HEHEH'G HH UHHHG HEHEHF HH UHHp HHDLdH%( HE1HDž H;s HH H t ybHp HΉ H t HPF H@ HHHEF Hƿ Sz tr ybHp HΉ] H t HE H HHHE Hƿ TS H HH HHHHH H HHHUHHH u IHA AHƿ* y " HUdH+%( tB UHH HH H`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1Dž Dž( Dž,0 HEH0HPH8H(H H@ H x = vH HǸ ?$$ y ! G HcH@$HΉ#Hys! ؉ $, HHdH+%( t UHT y, HSC Hƿ-S S ] UHt HC H#C ] UHt H C H=C ] UHat HKC HjC ] UH>t HxC HC ] UHt HC HC ] UHSH8H}HuHUHM |_ q2H}HMHuHEHSIIȉHC HǸ HE C H UHcHUHHHH uEHcHEH _EEHcHEH uH] UHATSH H}HUHMЈE} t H @C H BC } tAr Ap UHHUHEHuIIHDH C HƸ 1HHe[A\] UHSHH}E} t H B H B HHEHHHB HƸ H] UHSH( HdH%( HE1 t H IB H KB OHHHIIHHGB HǸ HH!? HHKHUdH+%( t`H] UHH` HHHDdH%( HE1HDž HHHH yZHp HΉ蘒 HHHIHHH]A Hƿ L HH\ y`Hp HΉ HHHIHHHA Hƿ L HH H~HHHDž u IHA AHƿ* yI ؉Hp HΉ HHr@ Hƿ $K HHHUdH+%( tܽ UHHG@ ] UHH dH%( HE1H(H( u H(H0HH? @ HǸ xZ--H0A Aй H¾ F$$ x $X$ dH0Hp HH0Hp Hy Hp H5 HUdH+%( t耼 UHH HhH`HXdH%( HE1H HҾf)fօHDž HHHHHHHDž HX t;HXHHXH J> H{DtPEa HX t HXH H v HX@ HX t HXH Hv HX@ {HX t HXH Hv HXH@ HHX t HXH Hv HXH@ H2 ztf t/w~ uhƅzƅkz tD$ ƅJz u HhH@p Ht!C C zt8{HH`A Aƿ | HH`H HHHsHH u)C: {HH`HAH|| ؉H HΉ H{ t H; H5 HhHHH`HQIIHHj; Hƿ EHR H|HhH&HHHC |裯H HΉ H{ t H: Ha HhHHH`HQIIHH: Hƿ DHz tx\z tJHHHHHHHP(H@0H{P1H7{HHHHF@HUdH+%( t% UHHpH}HUEdH%( HE1HE H腹f)E)EHE EEHEHUHEHUHEHUHEHUHUHMHEHHHUdH+%( t UHH H(H HdH%( HE1H0 HѸf)P)`HDžP HPHXH0H8H`HhH@HHH t;HHHH 8 Hx>tM? H(H@p HFt@HuH H HpIHH8 H¾ *H HpHHk8 HǸ H t HH Hv H@ HH t HH Hv HH@ H8H0HpH(HHHUdH+%( tx UHHH}Hu=HE <?u HEHE&HEHE 8t HEHEHE tHE t HE <*uHE <*uUHEHE <*tHE u- VHEHPHUHUHHBt 0HE uHE uHE u UHHH}HuHEHHEH HH^ UHH@H}؉HUHMEHEHEHEH@HEHEHPHEH0HEL H/Hu jHEH@HPHEHpHEHHѺ H^ E} tE0HEHpHEH@HHHUHJHHHEH UHHp HdH%( HE1JHDž HDž HDž HDž HH HHHH uEq ؉HHH&5 Hƿ >] H HH 5 HHǸ uHHn t0H4 Hƿ H>Džo HHH HH HHPHHHѺ H H H蛑HH u% ؉ HHHPHHHHHH uDž HHHHѺ HHHHHHHHHHH)|HH@HuDžDž )HHcHHH H萟HH;rHHiHHHUdH+%( t@ UHL H] UHH0 HdH%( HE1 HDž HHr HHHH uE2 ؉HHH1 Hƿ ;k H HHH5 2 HǸ uHH+ t0H1 Hƿ ;Dž HHH HHX HH@HPHHpHHHѺ H0 u_HHpHH@HHHHJHHHHHH@HuDžHH譺HUdH+%( t UHH HhH`HXdH%( HE1HP HEf) )0)@)P)`HDž P H H(HHH0H8HHH@HHHHHPHXH HH`HhHHf))H`HHDž HX t;HXHHXH / * HX4t-5: HhH踙|| y5HhH HH' Hƿ ?84 HX t HXH Hv HXH@ HHX t HXH Hv HXH@ HHX t HXH H'v HXH@ HHX t HXH H v HXH@ HH` u#H uH u3 H` t7H u H uH u H t3 H` uH u}3 H tH tZ3g H` t^WtHHfxHHxx HHHHHX t HXH H(v HX@( vHX t HXH H)v HX@) wv tw tm2z w t8 * HHHH HHHv )HH uDžx HHHH| 虍 yYe ؉xHpx HΉz HHhH HHH+ Hƿ 4)HPHHrH,HHYHHJx0HUdH+%( t) UHH H}HuHxdH%( HE1HE H脩f)E)EHE HEHUHEHUHEHUHEHUHE HxH HEH@HѾ HHt HEH@H ) HHru ( HEH@ H * HH蕞EEȄtHEH@H HEHEH@HHEHMHUHEH5\* HǸ 蓩E} *HEHHL* Hƿ 2 EȄt5HEHt,HEH蓕H4* Hƿ 2GHEHEHMHUHEHHHxHHEH>HxH HHUdH+%( t UHHpH}HuHUdH%( HE1HE Hyf)EfEHE HEHUHEHUHEHEHEH HEH@Hr) HHt HEH@H]) HHyu HEH@ H <) HH蜜EEЄtHEH@H HEHEH@H HEHUHMHEHHHUHHEH Hu [ HUdH+%( t輣 UHH HhH`HXdH%( HE1HE0 Hf)E)E)EHE0 HEHUHEHUHEHUHEHUHEHUHEHUHXH HhH@H ( HHt!HhH@H' HHu HhH@ H ' HH EEtHhH@HHEHhH@H HEHUHEH ' HHǸ || 'HEHH' Hƿ 3/BHMHUHhHHHXHHEHHXH HHUdH+%( tʡ UHH HhH`HXdH%( HE1HE0 H f)E)E)EHE0 EHEHUHEHUHEHUHEHUHEHUHEHUHXH HhH@H& HHu HhH@HHEHUHEH & HHǸ x|| 'HEHH3& Hƿ -OHMHUHhHHHXHHEHbHXH Hu HUdH+%( t/ UHH HXHPHHdH%( HE1HDžh HDžp HDžx HE8 Hcf)E)E)EfEHE8 HEHUHEHUHEHUHEHUHEHUHEHUHEHEDž`HHH HXH@HxHpHhIH5$ HǸ Ϣddt dt}Dž` HhH$ HHEHxHpHuHXIH\HHHHHH H``5HXHPHXH HHHF$ Hƿ `+HhHDHpH5HxH&`HUdH+%( t UHH0H}HuHUHM H}HMHuHEIIȉH# HǸ +E C}H UHcHUHHHH uEHcHEH _EEHcHEH uUHATSH H}HUHMЈE} t H _# H a# } tAr Ap HHUHEHuIIHDH+# HƸ HHe[A\]UHSHH}E} t H " H " uHHEHHH, HƸ ?H] UHSH( HdH%( HE1 t H l" H n" HHHIIHH HǸ jHH HHHUdH+%( t͛H] UHH HHH8H0D@DdH%( HE1HDžh DH0H8HHH\\ yA\H0H8AHHH{! Hƿ (\` DHHHu`` yG`\\H0H8AHHHG! Hƿ ' HhHp H Hht`HHxDžp @u @IHpA AHƿ* }dd y2y ؉\\H Hƿ &d DHHH\HUdH+%( t蒙 UHHpH}HuHUdH%( HE1HEHl HEHEHit@HEHKHEHUHEHHH< Hƿ &HE HUHMHEHHo HHEH} t3HMHUHEIHHH Hƿ %O EHUHEIHHH Hƿ %Eft4HUHEHHH Hƿ _%HE_ EHEHH"HEH} uD HHUHEIHHH Hƿ $HE` HUHMHEHHby HEH} ~REHEH }HuHUHEQuAIHHH Hƿ $HEHEHEHcHEHl HEHUdH+%( t? UHH ] UHH`H}HuHUdH%( HE1f)EfEHEH HH uHEHi HHHt0HW HHEHT HEcHEE %HK HHEH= HEE E EHHDH EHHDHE HE <:uHEHEо: HˮHEH} t HEH+E HEH*Ẽ} tzH}HMЋUHuHEIIȉH HǸ 2UHE HƿIx1HUHEHHHp Hƿ " <HEо: HHEH} EEăHUdH+%( t' UHH H $ H HxtHhH`LXdH%( HE1HDž HDž HP HJf) )0)@)P)`HDž P H H(HHH0H8HHH@HHHHHPHXH HH`HhHHHDž Dž HDž HX t;HXHHXH 1 Hh t= 8 HxHȁ y5HxH HH Hƿ O HX t HXH Hv HXH@ HHX t HXH Hv HXH@ HHX t HXH H v HXH@ HHX t HXH H'v HXH@ HHX t HXH H/v HXH@( HHh u H` uHHu H` tCH u*H u H uH u HHt:`[ H H 1Єt50 H` Hh/ H H HHh HH tKHxH HhAHHH Hƿ HHhHHH`HhH^{ y?: HHeH t[HHHHhA Hv y HHHhHHH HHHHHHX t&HXH H0vHX@0t t u ftt ~ t <HH uDž HHHHHѺ0 t yYv ؉Hp HΉa HHxH HHH Hƿ (HPHH~H+HHk~HH\~ HUdH+%( t; UHH H $ H H $ H0 HHHLdH%( HE1HDž( HDž@ HDž0 Hp HGf)fօHDž HHHpHxHHH t;HHHH , Ht H t HH H+v H@( H t HH Hv H@ H t HH Hv HH@ HHH t HH Hv HH@ HxH u HH HHOH@H@ t~ƅ HDž H@H+HH H HH9HGHHHHHH(H@HH H/ H,H HH HH) tKHH HAHHH7 Hƿ HHH t HH H'v HH@ HPHP H( t7HPHH(HHH8H(H HPHHHo H8H8 yH8 H8H tf t/w~ uhƅ ƅk tbG ƅJ u HH@p HIt!" t? HHHHIAƿ 9 HH t HHH@ HHHiH0H0 uX= HHH0AH ؉H HΉ[ H t H Hh HHHHHQIIHH Hƿ HR Hp HHHXHXHo ~H HΉ=Z H t H H HHHHHQIIHH Hƿ H tx\ tJHXH`H`HhHhH0HP(Hh@0 Hh P1HX7 H0HH0HrvHUdH+%( tQ UHH HHH@H8dH%( HE1HE0 H覈f)E)E)EHE0 HEHUHEHUHEHUHEHUHEHUHEHUHDžh HDžp HDžx Dž`HE H8H HHH@HxHpHhIH5 HǸ ddtld dtdt Dž` HHHPHHH HHH Hƿ Hx+ HgHEH} tZH\HUHEH5 HǸ 9ddu \HcHEH u HE HE HhH HHIt HhH HH,u EEt4HEHt+HHH HHy Hƿ HxHEHEHHpHMHHIHHSH8HH8H HG`5HHHPHHH HHH- Hƿ GHhH+sHpH sHxH s`HUdH+%( t UHH H}UHxLpEdH%( HE1HE0 HCf)E)E)EHE0 EEHEHUHEHUHEHUHEHUHEHUHEHUH}HpHxuHEIHHUdH+%( t UHH` HHHLLdH%( HE1HH@pHH t;HHHH - , H] t2 X HHoy5HH HH Hƿ O H u H/ H跙H HH HH tKHH HAHHH Hƿ < b HHHH H~ tHH H HH HuRHH% HH HH H tHH H H t HH Hv HH@ HHH LHHHHMIH? HHHH tHHUdH+%( t UHHPH}HuHUdH%( HE1HE HE HE HEHcHEHEH HHuHEH HuHMHUHEIH5V HǸ Eԃ}t)HEHHR Hƿ L E?HuHMHUHEA IHHUHHEH H˝EHEHmHEHmHEHmEHUdH+%( t} UHH H $ H0HHdH%( HE1HHHHIIHH HǸ 跓 y Z= v4HHHHHU Hƿ HH HH課HUdH+%( t| UHHP HHdH%( HE1HDž HHHH yZHp HΉ O HHHIHHH Hƿ HH H~Dž HHHHA A Hƿ* p yf ؉Hp HΉ4N HHHIHHH Hƿ 3HUdH+%( t{ UHH HHHH dH%( HE1H0 HP}f)Pfօ`HDžP HPHXH0H8H`H@H t;H HH H G Ht H t H H Hv H H@ H8HHHH ynHp HΉL HHH HHIIHHH Hƿ x H0 HHlH(H(H$$ tx ZpHp$ HΉK HHH HHIIHHH Hƿ $RH(HUdH+%( tx UHH H}HuHUHUHuHE Hq UHH@H}HuHUHEH HEH@H HH"t HEH@H` HHu HEH@HXHEH} u HEH@ H O HHpuHEHHE HEH HEHE/ H#HEH} uHEH\gEHE HEHUHMHEHHHUHHEH gHEH H UHH HHHdH%( HE1H0 Hbyf)Pfօ`HDžP HPHXH0H8H`H@H t;HHHH Ht HHvd y5HH HH Hƿ = 購H(H( ui H(HvHHH8H t HH Hv HH@ H@H0 H։q$$ y ؉$H(H eHp$ HΉG HHH HIHHH Hƿ $oH($PH(HUdH+%( tt UHHH}HuHMHE HH} UHH@H}HuHUHE HEH HE HEH Hɂ HH:HHEH Htɂ H HEH@HH=lurHEH HFɂ HH~HEHEHPHEH u HEHPHEH </u HEH@HUHHHEHEH}*H} u5HEHPHEH HHH` Hƿ * )HUHEHH$HUHHEH H辒 UHHP HHdH%( HE1HP HGuf) )0)@)P)`HDž P H H(HHH0H8HHH@HHHHHPHXH HH`HhHHH t;HHHH % HtZ HH_ y5HH HH2 Hƿ l= "HH u HHHH t HH Hv HH@ HHH_HHщ OV yu ؉HH`Hp HΉ@C HHH HHH Hƿ FHPHHUdH+%( t p UHHH}HE H UHHH}HuHUHEHH UHHH}HE H UHH H}HuHUHEHHUHHEH H% UHH H}HuHUHEH诅HUHHEH H UHH HHDH8H0dH%( HE1HHH ]\\ y5HHH HHl Hƿ A \HhHh u HhH HHHH`H0`D\Sdd y ؉dHhH]Hpd HΉ@ HHHH H8IHHH Hƿ d;HhdPHhHUdH+%( t]m UHHH}uuHE H H UHHH}uuHE H H UHHH}uuHE H H UHHH}uuHE HӁ H UHH H84H(dH%( HE1HPP Hnf)E)E)E)E)EHEP HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUH( t;H(HH(H K Hjt? H( t H(H Hv H(@ HH( t H(H Hv H(@ L4 u5H8H HH Hƿ L t>H t5H8H HH Hƿ X H( t H(H H v H(H@ HxLpHtH( t H(H H v H(@ XHP4H8HH HHUdH+%( ti UHH H84H(dH%( HE1HPP H?lf)E)E)E)E)EHEP HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUH( t;H(HH(H : Ht H( t H(H Hv H(@ HH( t H(H Hv H(@ L4 u5H8H HH Hƿ S L t>H t5H8H HH Hƿ H( t H(H H v H(H@ HxLpHtH( t H(H H v H(@ XHP4H8HH ~ H8HUdH+%( t;g UHH H84H(dH%( HE14 H( 1Єt5H8H HH( Hƿ mg H8 t5H8H HH1 Hƿ & 4 HPP Hhf)E)E)E)E)EHEP HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHU4H(HPxLL yLFCLlHP4H8HHJ HJH8H HUdH+%( t<e UHH` HHdH%( HE1HP Hgf) )0)@)P)`HDž P H H(HHH0H8HHH@HHHHHPHXH HH`HhHHDž H t;HHHH Ht H t HH Hv HH@ HH t HH Hv H@ HHQ y5HH HH Hƿ L HH u HHŎHHHѺ oH yu; ؉HHRHp HΉ`5 HHH HHHl Hƿ fHPHHUdH+%( t b UHH H}HuHUHE HxHUHHEH H证 UHHP HHdH%( HE1HP H8df) )0)@)P)`HDž P H H(HHH0H8HHH@HHHHHPHXH HH`HhHHH t;HHHH HvtK HHN y5HH HH# Hƿ ] HH u HHHH t HH H v H@ H t HH Hv H@ H t HH Hv H@ H t HH Hv H@ HHѺ- D yu艼 ؉HHNHp HΉ1 HHH HHH Hƿ LHPHHUdH+%( tn^ UHH0H}dH%( HE1HE HEH@HtHEH@H@0Hu HEH\Ly/HEH HHW Hƿ WHEH@L@0HEH@HHHUHEHHAЉE} t ENHEHu 9HEHUdH+%( tn] UHH0H}dH%( HE1E HEHEHEHEHE@ yHE؋@HUH։6HE؋@VTHUdH+%( t\ UHH0H}dH%( HE1E HEHBt3HEH@HH% Hƿ :[ HE؋@y3HEH@HH Hƿ a ( HEH} u HEH@hHPHE؋@Hu JE} t1HE؋@@% t}tHEHKEv HEHIHHE؋@@% u HE؋PHEPHE@ HEZHE؋@ , AE} yHEHQKE HEUPHE؋PHEP HEHUdH+%( t[ UHH0H}HudH%( HE1E HEHat HEЋ@y.HEH@HH Hƿ HEHEHEHEHE@ ytHEH@hHPHEЋ@Hu IE} t }tE=HEЋHHE؋@ ΉwE} yEHEЋPHEP HUdH+%( tY UHHĀH}HuHUHMLELMHEHEHEH)HEHEH HEHUHEHHEE; HEHH#EHHEHHEHE@HEHUHEHHMHUHH9 HEHEHUHEHH+EHEHEH+EHEHEH H;EsSHEH HHHEH誦HHEHHEH HuHEH E HEHUHHEH HUHMHH=HEHHEH HUHEHHv=HEH HEHUHEHMHHщEHEHE}uHEH;EHUHEHH}E UHHH}HuH} HEH@HtLHEHP(HEH@ HHEH@HHTzt"HE@$H Hƿ HE@ x+HE@ $ Ǹ 6BHE@ NHEH@HXGHEHLG UHH H}HEHg HEH@0Ht{E VHEH@0UHcHHH HEH} t.HEHP(HE@HH։}HUHEHHEHE@@9E|HEH@0HFHE@DxHE@DMHEH@8HrFHEHfF UHH HXHPLHdH%( HE10 HhHh uHD HhHXHHhLP$HhHP(LHPA AѺHƿ* JHhP Hh@ yW ؉dHpd HΉ*( HLHщHc Hƿ 5F HhH HXHP(HXH@ HA Aȹ Hƿ 1HhHBHhH@HufHhH@ 1 ؉dHpd HΉe' HLHщH Hƿ p Hh@ $ Ǹ >yT趱 ؉dHpd HΉ& HLHщH Hƿ Hh*HhHXHHdHHHUdH+%( tS UHH HHH LLdH%( HE1HDž( f)0)@)P)`H t;HHHH Ht H t HH H v H@ $$ u Dž$ H(Hp H(UH(tHDžx Džp HE $HE$EHpH0HH@H HHHHPH0H HΉt HHUdH+%( tQ UHHĀ}HuHUHMLELMdH%( HE1f)E)E)E)EH} u1 H} t5HEHHEH N H t HEHEHEHEHEHEH} tHEH H v HE@ EH} tHEH Hv HEH@ HEH} tHEH H v HEH@ HEHUHMEHΉ HfHUdH+%( tP UHHP HHdH%( HE1HP HHDž H tHHH#Ht4HHH, Hƿ Hr HX HhRDžX HHHΉ@ ؉tXHp HΉ3" HHщH Hƿ >HH" Hn Hƿ Ct8HHHH Hƿ HH P 舕H H uH HHPH HHHPH HPHHPH HPHHP H HPJHcH HP H H@ HHH HP(H PH cH BDH @DyLD ؉Hp HΉx HH Hƿ H@(~HP(H P@btH B@H @@yH @@ t& H @@9s H P@H @@H H输HH HP8H H@8Hu(DžH Hƿ H @@H H_HH HP0H H@0Hu(DžH Hƿ J HHHHH4 t&H Hƿ = Dž Dž H@(~ HH@0HcHHЋ H@(~ HH@8HcHHЋ H@(29L HHH , HH0H HHHHtHH H H@0HcHHHHHHP H @HH 39 tlߧ ؉Hp HΉ HHp IAщH Hƿ Q H HH8HcHHHHH H HH8HcHHHHHHHBH HH8HcHHHHHHP H @D ,y`Ѧ ؉Hp HΉ HHP IȉщH Hƿ OH @@9H P@HH8H 8HH8H tH HHHoHUdH+%( t[H UHH@H}HuHEHEHEH HEHEHEHEH Ht'HEL HE؋H$HEH@HUȉHA HEȋ tU HEHEHEH@H HEL@HEPHEHx HE؋p$HEH@HHAfHEHEHEH@HtTHEL@HEHPHE؋H$HEH@HA+HEȋ H Hƿ D UHH H}HuHEHxHEHHHEHP HEHp(HEH@HuL IHHE}tE UHH}HE@D] UHH0H}؉uHE؋P@HEHp8HE؋@DMԉhE} y E pHEHH8EHcHHHHHH@HEHUHEHHE} t*EHb Hƿ ETEE;E|E UHH}HE@@H] UHH H}HuHE@@HH9Er 4HEH@0HUHHH HEH} u HE@ UHH0H}uHUHMHE@@9E| RHEH@0UHcHHH HEH} u e#HEHPHEHHEHP(HEH UHH H}HuHE@@HH9Er @HEH@0HUHHH HEH} u HUHEHH; UHH H}E sHEH@0UHcHHH HEH} tKHUHEHHE} t0UEщH Hƿ EHEHE@@9E| UHH@H}؉uHUdH%( HE1E E H} t} y( HEH@p t } t H} uUHE؉ } t.UHEȉHUEE Ei H} uS HEH@p HIE} t E&nHE؋ HEH@pH}HMHuIHVE} t E0EHE؉ EHE؉ UHE؉ HUdH+%( t4B UHHPH}HuHUdH%( HE1E EHEH HE HE <,t HE < u HEk H}HuHMHUHEIIH5t HǸ EEE} ~}~1UHEȉHHS Hƿ mE= }uEEEx UE9~6UEHMIȉщH( Hƿ E EHcHEH HHg'HEH} u E HEHUHUHE )HcHUHcHUHH¾ H7CUE)BHUHcHUHH¾ H CEPHEEHHEHE fHE u Hi Hƿ 2$ HEH H 0HEH EHUdH+%( t? UHH HXHPHHdH%( HE1Džd HX HǸ hh yE ؉ddHXHH Hƿ Rd Hph HΉwlh\6l Rl t u ddHXHHK Hƿ delv*HXHHE Hƿ 0lHƄp HHHPHpHHHUdH+%( t8> UHHPdH%( HE1E Hڄ HEHEHEE }tM}W}t3}K}t}t=HEHE؈IHEHEf9HEЋHE؉+HEHHEHEHHMHUHHH|"EE} ~E Hσ HUHMHHhE} tE E E HUȋEHH tEEE9E|HEH,EEHل HEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHX!EHUdH+%( t@< UHHPH}HuHUHME EHHEHHEHHEHEH@HEHEH HEHEH@HEHUHEHHXMHUHHEH Hu'HEHH Hƿ @H} t!HEH @\tHEH HP`HEHEEHH;E= UHH@H}HuHUHME EHHEHHEHHEHEH@HEHEH HEHUHEHHҌHUHHEH Hu'HEHH Hƿ EEHH;Eq UHH H}HuHEHHHEHPHEH@HuIHƿ HEHEHZtGHEH<EHEH@UHHL Hƿ Ef HEH@ HUHHE@,HcHE@(HcHEHp0HEH~E} t5HEH@UHH Hƿ EkHE@<HcHE@8HcHEHp@HEH E} t5HEH@UHH Hƿ 0E UHSHhH}HEH@HuW HEH@HhHEH} uAHEH@HYHH Hƿ ؉E HE@HcHE@HcHEHpHEH@H E} t-EHo Hƿ AE HE@$HcHE@ HcHEHp(HEH@HE} t-EH Hƿ E7 E ` HEHP8HE@4EHHHEHEH@H HEHEHјEUHEH3HEHEH脻tSHEHBHHEHѧHHH Hƿ v HEHCEHEH辽HEE tHEHEH2HEHEHEHHEHEHHEHHzu!HEHP`HE@HEH@HHEHE E;E|EHE@09E H] UHHH}H} t>HEH@H&HEH@(H&HEH@8H%HEH% UHH0H}HEH@ H H E} t5HEH@UHH: Hƿ ElE RHEHP0HE؋@,EHHHEHEH@H HEHEH@HtHEH@HUHR`HEHE؋@(9E| UHHPH}E HEHP@HE@<EHHHEHEH@H HEHEH@HEHE@| HE@} HEH@H HEH@H@0Ht}HEH HutHEH@L@0HEH@HHHUHEHHAЉẼ} tCHEHBHẺH Hƿ Ẻtj EHE@89EE . HEHP0HE@,EHHHEHEH@H HEHE HE HEH HE@, w-HEHHHB Hƿ D HEH@HEHEH HujHEHoHUHHEH HuLw ؉EHEH脣HẺH Hƿ ϿẺ' EHE@(9E UHH@H}E FHEHP@HEȋ@<EHHHEHEH@HEHEH HeVHEH EHEȋ@89E|HEȋ@, vdE MHEHP0HEȋ@,EHHHEHEH@HEH} tHEH HUHEH EHEȋ@(9E| UHHH}H} tZHEH4qHEH@ HtHEH@ H HvHEH@0Hd!HEH@@HT!HEHH!UHH}HuHUH} t[HmHE HUHEHHMHUH HEHEH;EsHUHEH uHUHEH ]UHH}Hu HE t HEHmH} ݸ ]UHH H}HuHUHMH}w.HUHEHHHr Hƿ \ THEH+EHHUHEHHHZt'HEHHK Hƿ UHH}} y ]UډEUHH}} y ; EUHH}} yEE Ǹ Q UHH }EE} yEk}bEEˌ EE&跌U} y1E؉EщHw Hƿ 而UEUHH}HE]UHH}HuUMHUEƿA +#UHH }HuUUHMEHΉEE UHH H}uUUHEHƿ E} y̋ u m} ͋E UHH ,dH%( HE1HDž@ ƅPQQQQfDžR DžT ƅXYYYYfDžZ Dž\ HDžH H@H` H 0Dž` HPH^HhHHdH H;Hp,E, t E EH@H`Hƿ 7<< x<$$ HUdH+%( t, UHHH}Ʉ t HEHؼ UHH dH%( HE1CɄ u !< t R Ʉ H Hu 8Hp HEHEHEHEHƿ St r HUdH+%( t+ UHH LH@H<D8L0dH%( HE1HDžXP HXH` H.H0 t;H0HH0H 8 Ht. L`H@ t5 : t"H@H`HJ HHHd<h8lH0 t H0H H v H0@ EH0 t H0H Hv H0@ EH0 t H0H Hv H0@ EH0 t H0H Hv H0@ EH0 t H0H H3v H0@0 EH0 t H0H Hv H0@ tH0 t H0H H v H0@ pH0 t H0H H'v H0H@ HEH0 t H0H H+v H0@( xH0 t H0H H/v H0@, EH0 t H0H H7v H0@4 EHXH`Hƿ TTHUdH+%( td( UHH@H}؉uԉUЉM̋UЋEHHEHEHuHEH} u gHEHEE JUHMHEHH E+ẺUHEHHʾ Ht*EHE؋EHEEE;ErHE UHH H HHLLdH%( HE1HDž@ HDž0 HDž8 H t;HHHH ȿ p Ht H t HH H v H@ y u Dž H@H` H+) `H t HH Hv H@ EH t HH Hv H@ EH t HH Hv H@ EH t HH Hv H@ EH t HH H v H@ EH t HH Hov H@l EH t5 /5 t"H H`HJ0 HHHH'HpH;s HHHhHdH t HH H'v H@$ H t HH H+v H@( t tep H t HH H#v H@ Ẽ t E EH t HH Hgv HH@` HHH t HH H_v H@\ H t HH H[v H@X $HH 1Єt[f H t HH HGv H@D (H t HH H?v HH@8 HP(EHPHHEH t HH HCv H@@ EH t HH HWv H@T ,H t HH HOv HH@H HX,EHXH)HEH t HH HSv H@P EH t HH H7v HH@0 HHE$ t+HHHHE |$xH@H`HH t HH Hkv UHPh ^ 9 H0 uoEthE;(s]Mu(HPHH0H0 uO~ H0HHE(E H8 Eȅ E;, Muȋ,HXHH8H8 u} 1 H8H:HE,EH@H`HH t HH Hkv UHPh D} u H0 H8 $ HH t{HHHHE |Džx H@H`HH t"HH HkvUHPhH0HH8HHUdH+%( t UHH LH@H8H0dH%( HE1HDžX HXH` H!L`H@H]HhH8HGHpH0HxHXH`Hƿ #TT'HUdH+%( t UHH LH@H8dH%( HE1HDžX HXH` H* L`H@HyHhH8HcHpHXH`Hƿ MTTQHUdH+%( t UHH LH@H8H0dH%( HE1HDžX HXH` HM L`H@HHhH8HHpH0HxHXH`Hƿ bTTfHUdH+%( t# UHH LH@H8dH%( HE1HDžX HXH` Hi L`H@HHhH8HHpHXH`Hƿ TTHUdH+%( tM UHH LH@H8H0dH%( HE1HDžX HXH` H L`H@HHhH8HHpH0HxHXH`Hƿ TTHUdH+%( tb UHH LH@dH%( HE1HDžX HXH` H L`H@HHhHXH`Hƿ TTHUdH+%( t UHH LH@H8dH%( HE1HDžX HXH` HL`H@H>HhH8HxHXH`Hƿ TT HUdH+%( t UHH LH@H8dH%( HE1HDžX HXH` H!L`H@HpHhH8HZHpHXH`Hƿ DTTHHUdH+%( t UHH LdH%( HE1HDžX HXH` HYL`HXH`Hƿ TTHUdH+%( ti UHH LHH@H8L0L(HEH HEHdH%( HE1HDžX8 H t;HHHH H;t' HXH` H@HEH@HH`H8H|HhH0HfHpH(HPHxH EH t HH Hv HH@ HEH t HH Hv HH@ HEHXLH`HΉTUH THUdH+%( t UHH }HuHUHMHUEuuA Iй ƿ H UHH0}HuHUHMLELMH}HuHMHUEuuIIƿ |H UHH0}HuHUHMLELMH}HuHMHUEuuIIƿ (H UHH0}HuHUHMLEHMHUEuuIIй ƿ H UHH LH@H8dH%( HE1HDžX H8 t;H8HH8H H5t HXH` H:H8 t H8H Hv H8@ pH@HdH`H8 t H8H H v H8@ lLhHXH`Hƿ TTHUdH+%( t UHH}HuHME HΉGC UHHH}HE Ht UHH HHH@dH%( HE1HDžX H@ t;H@HH@H Ht HXH` HH@ t H@H Hv H@@ pHHHH`H@ t H@H H v H@@ lHXH`Hƿ TTrHUdH+%( t/ UHH`}uUMdH%( HE1HE Hf)E)EHE EEHEHUHEHUHEHUHEHUHMUuEbHUdH+%( t UHH <84H(dH%( HE1HDžX H( t;H(HH(H Ht H( t H(H Hv H(@ HH( t H(H Hv H(@ LH( t H(H H v H(@ PL tH tc HXH` H8`<d4hH( t H(H Hv H(@ pH( t H(H H v H(H@ HxH t P lHtPlLtHXH`Hƿ kTToHUdH+%( t, UHH <84H(dH%( HE1HDžX H( t;H(HH(H Ʀ H#t H( t H(H Hv H(@ HH( t H(H Hv H(@ LH( t H(H H v H(@ PL tH t HXH` Ht8`<d4hH( t H(H H v H(H@ HxH t P lHtPlLtHXH`Hƿ :TT>HUdH+%( t UHH}uUE ƿ O UHH}uUUuE O UHH0 HdH%( HE1HDž@ H t;HHHH S L Ht-1 H t HH Hv H@ H t HH H v H@ u t t HDž H t7HHHH)HHHHHHlt u)- HH` H `dhH t HH H v H@ l tp ! H H HH H>H t HH Hv HH@ H.Hpx H t HH H'v HH@ HpHDž@( H t7HHH@H)HH@HHHHt X | H t HH H#v H@ pH t HH H'v H@$ tH t HH H/v HH@( HHxH t HH H7v HH@0 HHEH t HH H?v HH@8 HkHEHDž8@ H t7HHH8H)HH8HHHHGt H t HH H#v H@ EH t HH H'v H@$ EH t HH H/v HH@( HhHpH t HH H7v HH@0 H-HxH t HH H?v HH@8 HHEH t HH HGv HH@@ HHEH t HH HKv H@H EHDž P H t7HHH H)HH HHHHht !% H t HH H'v HH@ HxHDžH( H t7HHHHH)HHHHHHHt d H t HH H#v H@ pH t HH H'v H@$ tH t HH H+v H@( xH t HH H/v H@, |HDž00 H t7HHH0H)HH0HHHHt 4 LP H t HH H#v H@ H t HH H'v H@$ t t t pl l pH t HH H/v HH@( HxHDž(0 H t7HHH(H)HH(HHHH<t H t HH H#v H@ H t HH H'v H@$ t trv t pl l pH t HH H/v HH@( HxHDž0 H t7HHHH)HHHHHHt HDžP H t7HHHPH)HHPHHHHvt u$37 HH`Hƿ 5 x O] ؉t du pt HDžX H t7HHHXH)HHXHHHHnt u(/wƿ Q HUdH+%( t UHH LdH%( HE1HDžX HXH` H*L`HXH`Hƿ" yTT}HUdH+%( t: UHH LHH@dH%( HE1HDžX H@ t;H@HH@H H7t H@ tUH@H HvEH@@ t7H@ t-H@H Hv H@@tjH HXH` HL`HdH@ t H@H H v H@@ hH@ tQH@H HvAH@@ t3H@ t H@H Hv H@@ lYH@ tOH@H Hv?H@@t1H@ t H@H Hv H@@ lHXH`Hƿ ;TT?HUdH+%( t UHH LdH%( HE1HDžX HXH` HPL`HXH`Hƿ! TTHUdH+%( t` UHH LHH@dH%( HE1HDžX@ H@ t;H@HH@H ɔ @ H]t% HXH` HbL`HdH@ t H@H H v H@@ hH@ t H@H Hv H@@ xH@ t H@H Hv H@H@ H HpH@ t H@H H/v H@H@( HHEH@ t H@H H'v H@H@ HHEH@ t H@H H7v H@H@0 HsHEHXH`Hƿ `TH@ t H@H HvlH@P H@ t H@H H?vHUH@HP8H@ t H@H HvxH@PTHUdH+%( t UHH \XTHHL@L8dH%( HE1Hp@ Hf)E)E)E)EHE@ HEHUHpHxHEHUHEHUHEHUHEHUHEHUHEHUTxH@HEH8 EHpX\Ή7lHH t|HHUH8lHUdH+%( tW UHH LH@dH%( HE1HDžXP H@ t;H@HH@H ڐ P HZt HXH` H_L`H@ t H@H HOv H@@L EH@ t H@H HKv H@@H EH@ t H@H HGv H@@D EH@ t H@H H?v H@@< EH@ t H@H HCv H@@@ EH@ t H@H H3v H@@0 EH@ t H@H H7v H@@4 EH@ t H@H Hv H@@ hH@ t H@H H v H@@ lH@ t H@H H'v H@H@ HHEH@ t H@H H/v H@H@( HHEH@ t H@H Hv H@H@ HuHpH@ t H@H Hv H@H@ H:HxHXH`Hƿ $TH@ t H@H H vlH@P H@ t H@H H7v UH@P4H@ t H@H HCv UH@P@H@ t H@H H;vdH@P8THUdH+%( tC UHH LH@HdH%( HE1HDžX HXH` HL`HXHH`HΉTT udH@THUdH+%( t UHH}HuHME HΉ UHH}HuHME HΉ UHH}HuHME HΉ UHH}HuHME HΉ UHH LH@dH%( HE1HDžX H@ t;H@HH@H h Hth HXH` HL`H@ t H@H H v H@@ hHXH`Hƿ (TTHUdH+%( t UHH}E * UHH LH@dH%( HE1HDžX H@ t;H@HH@H / H蝿t/ HXH` HL`H@ t H@H H v H@@ hHXH`Hƿ TTĿHUdH+%( t UHH}E UHH LH@dH%( HE1HDžX H@ t;H@HH@H Hdt HXH` HiL`H@ t H@H H v H@@ hHXH`Hƿ 趿TT苾HUdH+%( tH UHH}E N UHH LH@dH%( HE1HDžX H@ t;H@HH@H H+t载 HXH` H0L`H@ t H@H H v H@@ hHXH`Hƿ }TTRHUdH+%( t UHH}E oH UHH LH@H8dH%( HE1HDžX HXH` H5L`H8 dH@HuHhHXH`Hƿ _TT udH8TKHUdH+%( t UHH }HuHUHUHMEHΉ: UHH }HuHUHUHMEHΉ UHH }HuHUHUHMEHΉ UHH }HuHUHUHMEHΉ UHH LH@dH%( HE1HDžX H@ t;H@HH@H HSt HXH` HXLhH@ t H@H Hv H@H@ H肻H`H@ t H@H Hv H@H@ HpHXH`Hƿ hTT=HUdH+%( t UHHPH}udH%( HE1HE H`f)EfEHE HEHEHEHUHEHUHEHEHUEH։HUdH+%( tf UHH H8H0H(dH%( HE1HDžH( 証HHH` HH( t;H(HH(H $ HAtӸU H( t H(H Hv H(H@ HPH( t H(H HvH(@ HXH( t H(H Hv H(@ DH;Xs HX tHP u} H8HH`H0pH( t H(H H v H(@ EH( t H(H H#v H(@ ED t/HPH\HhHXtDxHHH`Hƿ \@@ ycHP tYD uPHPHHhHXtDžx HHH`Hƿ @H( t H(H Hv|H(P@蛶HUdH+%( tX UHH LHDH8L0L(HEH HEHHE HdH%( HE1HDžX0 HXH` HjL`HdDhH8H衶HpH0 lHXH`Hƿ |TlH0xH(|H HUHHHUHHT7HUdH+%( t UHH LdH%( HE1HDžX HXH` HHL`HXH`Hƿ ƵTT蛴HUdH+%( tX UHH LHH@dH%( HE1HDžX H@ t;H@HH@H ~ HUt HXH` HZL`HdH@ t H@H H v H@@ hHXH`Hƿ# lTTpHUdH+%( t- UHH LH@dH%( HE1HDžX H@ t;H@HH@H } H0t² HXH` H5LdH@ t H@H H v H@@ `HXH`Hƿ$ 肳TTWHUdH+%( tUHH}HEH]UHH}HE ] UHH}HuHE EHE +EHEEHcHEH] UHH}u}~#HE fvHE 9E| ] UHH}HE@?] UHH8H}؉uHUE HEHE} xE;E~ EHcHHHHHHEHHEHE fv HE@ftHE@E-HE ft!HE HH Hp EHEHy;EszHE@ft$HEHTHE@9~IHE fu7HEHHEHEHHHPHEH t UHH}HE ] UHH@H}؉uHUȉMLEdH%( HE1EԃHH HEؾ H0HEHEEЉE HEH EE;E H} t"HUMHEHE} EHH HEHH Ht EHay Hƿ lEHH HEHHEHHUHEHHHEUHEH4E EHUdH+%( t UHSH(H}uHUHMHEHfHEHFHHMЋuHEIȉH_H] UHHĀH}dH%( HE1f)EfEfE fE HE HE@% u HEHHEE HE@% uHEHHEEHcHEHHEHE HEHH+EEHuMHUHEI H{t Hx Hƿ Hj >HEHtHEHHEHEHHw Hƿ j HUdH+%( tUHfEEf]UH}E]UHH}HE]UHH}HE]UHH}HEH= H]UHH}H} HuHEH= Ht ]UHH}HE@ ]UHH}HE@]UHH}HE@ ]UHHH}HEHfUHHH}HEHfUHHH}HEHgfUHHH}HEHFfEf}tf}u UHHH}HEH fUHHH}HEHfUHHH}HEHfUHHH}HEHfUHHH}HEHfEf} tf} tf} tf}u UHHH}HEH>f UHHH}HEH fUHHH}HEHfUHHH}HEHuHEHt UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH H}uHEHHUHHHHHHEHEHUE} t HE@ UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH0H}HuHUdH%( HE1 HEHeq HEHȃHt HUHEHH+HUdH+%( tUH}uUE E E]UHH}Hu HE t HEHmH} ݸ ]UHH H}HuHUHMH}w.HUHEHHH s Hƿ e THEH+EHHUHEHHHZt'HEHHr Hƿ d UHH}} y 5UډEUHH}4Uډ UHSHH}HEHtHEH~؉4ډHEHsuHE H]UHH}u} u "HEH|Jy7Hи@ +EHH]UHH}HE] UHH@H}HuHUHMLELMHUHEHHEH H9rHEHHEHEH HUHEHH9Es HEH HEHEHHEH}wHE HEH9EsHEHEHUHEHH9EsHUHEHHEHEH HUHMHHHEH} u eHEH HUH)HHEHUHHHMHUHH¾ H)HEHUHHEHUHHEHEHHEH UHH0H}HuHUHMHEH H;Er MHEH HUHH)HEHHUHuHEIIHAHEH} u UHHH}HuHE@@HEHp8HEH0HUIA H UHH H}uHE HHEH} uHEU UHHH}HE NHUfHE@MHUBHE@8HUBHE@ #HUB HE@HUBHE@HUB UHSH(H}HEH@HEHE؋@w#Hn Hƿ ` HE ~f9u\HE@HE@wt3HE@dHn Hƿ "` HEH<HE f=t/HE Hn Hƿ _? HE؋PHE@9s5HE؋PHE@щHn Hƿ _ HE؋PHE@)UUHE@HE@HH9},HE؋@Hsn Hƿ 5_ HE@HE@ HHE@H9~FHEpHEHHEP HE@AAȉщH/n Hƿ ^3HE@t Han Hƿ ^ H] UHH0H}HEH@HEHEH@XHEHEH@@HEHHEHEH@HHtHE@u HE@t HE@xHEH t Hm Hƿ ]=HEH@HHu+HE t Hm Hƿ ] UHH H}E HEHCfEHEH H Hm HH|m H>E E E E UE E }UEgE EUEMUE7E/HEHJHl Hƿ }\ UHHH}HE HUHE@lHUBHE@WHUB UHATSHPH}HEHfEHEH H Hbl HHVl H> HEH HUHZ E HEHHE3HE HUHE@HEPEHEE9E|ĸ E HEHDHEFHEȋ ;HUȉHEȋ@'HUȉBHEȋ@HUȉBEHE E9E| $ HEHHEHE HUHE@HUBHE@HUB E HEHHEFHEЋ rHUЉHEЋ@^HUЉBHEЋ@IHUЉBEHE E9E| [ E HEHHE1HE؋ HU؉HE؋@HU؉BEHEE9E|Ƹ HEHFD HEH7HD E HEH HEFHE qHUHE@]HUBHE@HHUBEHE E9E| ]HEH HEHډ /HEHvHh Hƿ XHP[A\] UHH0H}HEH@HEHEH@ HEHE@ HEHHE HE@t HEHHEHE} yE EHcHEHH9Es7HE؋@PHE؋@@ЉHh Hƿ W HE@tHEHt HEH@ HUH)HE؉HE} tE[EHHEHE؋@@PHE؉P@HEH H9EHEH;Et HQh Hƿ ;W UHH0H}uHU؉MUHEHvHEH} u2MHU؋EAHщH h Hƿ V UHH H}uUUHEHHEH} u*UEщHg Hƿ iV UHHpH}HuUHEHEHE0UHEHg HE} tE } EH H#h HHh H>HEHUHEHE} E HEHHEHEUHEHEEuHEHUHEHE} ( E) HEHmHEHEHEE ZHEȋ0UHEHf HEEuHEȋHUHEH!E} tE EHE E;E| HEHHEHEHbEE 8HEЋ0UHEH'f HBE} tE= EHEE;E|" HEHYHEHEHEE 8HE؋0UHEHe HE} tE EHE E;E| HEHUHEHE} tE HEPHEHHEHEH9f Y HEPEщH'e Hƿ YS. HEHHEHEHEE ZHE0UHEH e HEEuHEHUHEH&E} tE EHEE;E| HEHsHEHEHgEE .HEUHEHE} tELEHE E;E|4UEщHUd Hƿ 7R UHH0H}HEHEHE؋@PE=UHE؉Hq HEUHMHEHHnE} tEEE;Er UHH}HE@PHE@@] UHH}HEH@H] UHHH}u} u H6a QHE@P9EsHEH@HUH.HEHP HEHH0HE@PƋE)HHȋ H UHHH}uHE@PHE@@9ErB! UHEH> UHH0H}HEH@HHt HEH@H@p~HEH@H@p HEH*EE UHE؉HZHEHEH$ HE@t HE@umHEHE؉HHEH} tQE 8EHH Hk HHEHHu HE@*EE vEE;E; UHHH}HE@puHEHHUBpHE@px HE@pH UHHH}HE@puHEHkHUBpHE@py HE@pH UHHH}HuH}tH}t %HEHEPp UH ] UHHH}tHE@ HE@ UHHH}u} t}t NЃ}9HEPHE@t HEH@HHEH@ UHHH}H] H9EtHEHt UHHH}H} tHEHt UHH0H}؉uE HEUHE؉H^HEE % HEH }tOt\ HHH O HuLHp HuHu8 HE@HE HEH HE HE@EhHEHHE} t)HEH u9sH HE@UEHE EH}UHE؉H1HEE} HEHNH} yBH1} t# uH9E~HEHE UHHPH}udH%( HE1UHEH萺HEHEHfEEȃ }! tSt HHH HukH@ Hu0H j HEHUHEHE@HEHUHEH9HFs HEH$b HEPHEHH HEH}HEH' HEHHEHEHfEE E HEPHEHxEԃ} Eԉp EЉE؋EԉEUE9MEЋUHEH%u#HE@UѺ Ѕt uEHE E9EkHE@Mк щȅt ?E:HEH%H[ Hƿ XI HUdH+%( t( UHH H}uE UHEHHE#HE@EUHEHHEE} CHEHt0HEHuHEHuHEHu} tHEHt E UHH0H}HuHEHEHEHZ HH9u oE TUHE؉H$HEHEHE؉HܜHEH} t HUHEHHuEEE;Er UHH@H}؉uHUȉMHEHWE} tHEH,Z HHxu EԉEiUHE؉HaHEHEH9Eu;HEHE؉HHEH} t HUHEHHuEEE;Er? UHH H}HuUHEpPMHUHEH UHH H}HuUMHUHE H UHH}HEHPHEH H9] UHHH}HEH HE@lxHE@laHEHt0HEH@HHEH@ HHEH@`HT HEH H¨HEH@H貨HEH@0H袨HE@itHEH@HH8HEHz UHH H}x 6HEH} uH| HE@@ HE@P HE@T HE@lHE@p HE@ H} tDHEHUHPHHEHHEPPHEH@@HEPTHEPHEPH} u HEPHE@Hƿ `HHEHHEH Hu HEH^H HEHHEHPHEH@@ HEH@f HEH@@HEHHEH@@HHEHP HEHHEH@@HHEHPXH} HEH@҉PHE UH 5HJ] UHHH}HEHH$ UHH0H}uHUؾx 4HEH} uH~ HE@@ HE@P HE@T HE@lH} t5HEHUHPHHEHHEPPHEH@@HEPTEHHHEHHEH Hu E UHEH HMHH芚HEUPHEHHEHPHEHE} HEHHEH@@HEH@@HHHEHPXHEHHEH@@HEH@@HHHEHP HEHqEEu HEHIEEu HEHE} } tHEHƝEHHHE UHHH}uMHE HH UHH H}uHUHUMHEHH UHH H8H0H(dH%( HE1HDžP DžD HUH8HHHu(H0HHtS Hƿ @ HHH8HHt(H0HHWS Hƿ i@N HHH8HH HRH H0HH@S Hƿ @ DHpHPHH豳HHpH9t0H0DHщHS Hƿ ? pHHH8HHH`H` u0H0DHщHR Hƿ Q?6 H`HR HH7uH(HXdH`HR HH uH(HHX3H`HR HH H(HHXHP HHhHh u7H0H`DIHщH?R Hƿ a>IHXHhHHPH8HH薷HPHP _HUdH+%( t UHH`H}HuHUdH%( HE1f)EfEHE HE E EHE &u1HEHHQ Hƿ s=H`Q HE HǸ +Eă} yR ؉E HHEHHHAQ Hƿ =EHH+ Eĺ #HEH} u,E_HEHH Q Hƿ <1 HUHMHEHH[E} HEHu6HEHH P HHP Hƿ O<E HEHtPHEH@HEH HHEHEH[t HEH=EHE u HEHuHEHUHRHUH HH;HEHEHtHEHE$ H} t;H} t4HUHEHH<(E} HEHsHE H} tHE@iHEHtt&HEо Hs4HEо H`!HEHHO Hƿ :H} tRHEHtIHEH@HEH H!HUHHEH Ht/HEH HEH} tHEH H} t HEHV Eĉ蜤} uHE;H} tHEH HHEH>HEH2EHHFHUdH+%( t UHHH}HuHUHE HHf UHHH}HuHMHE HHH0 UHH@H}HudH%( HE1HE HE HE E HEHN HHHEH} u ؉E= HUHEHѺ HHw E Ef=t Uf9t EԹ HE H t ؉E HEHHEH} y ؉E HE Ha t ؉EjHEHHEH} u EJHUHMHE H&HHEH9s E HEHUHEH_HEHEHɚH} t HEHV} tEHHHEHUdH+%( t艪 UHHH}HE HH UHHH}HuHUHEHHH UHH0H}HuHUH} t HEH HUHEHHhHEHEHE} uHE,}tEHHHUHMHEHH UHHH}HuHUHE HMH UHHH}HuHMHE HHH UHH HhH`HXTDPdH%( HE1HE( H肫f)E)EfEHE( HEHUHEHUHEHUHEHUHEHEE HE E Hh@lx3 HX tH` u HtHh HH HEH} u E tHhPHhHUHT H` uaDžx E||x9CEUHEHH#HEH} u E; HEHEHE H` t H`HEHEH` t HXEETEPEP t E EtHUHEHH(HhBlHh@l T uDžT H` uE u E. ؉EEHH Hƿ 3H` u-HE t"HEHHnH Hƿ `3HEHEEHUdH+%( t' UHHH}HEA H UHH}HE@l] UHH}uHEUPl] UHHH}HEH@XHt HEH@XHEH@`HA UHSHXH}HuЈEHEH@HEЀ} t HEH@HEH HEH} tHEPHEHEj HEЋPHEЋ@ HEЋ@ЉE̋EHƿ HEH} u ) HEHEHEЋ@HMHEHHʼn} t HEHcHEЋ@HEHEЋ@ HEHH HEHH膉} t[E DHEH@0UHcHHЋ HEHHEHEH-uqHEHEHE@@U9rHEЋ@ HEHEЋ@HEHBHHEHHHHEЋ@HEHEỦHEHEHœ H] UHH0H}HudH%( HE1HEHEHE@HMHEHHHEH} u <UHEPHE@tHEHUHP HEHUHUHEЉHEHUdH+%( t UHHH}uHE@T9EsHEH@HUHPHE@TE)ȉHEH@@9s!HEHHURTыU)ʉH UHHH}uUHEH֨ UHHp}HudH%( HE1E E EHHEH} uHCI HEк H臤HEHHEЋEEHUHMЋEHΉ E} E9E E؉EUHEHH HEH} uHHE HEHEE HEк HHEHuHEЋEEHUHMЋEHΉkE} uE9Es-} t HH2 H$HEMHUHEHNHEHEH踐HEHUdH+%( t蠠 UHH }HuEE} y ؉+HUEH։HEE藗HEH UHH}E { UHHH}HEH HtHEH HHEH HEH@Ht HEH@HƏHEH@ UHH0H}HE EHEHtHEHc HEH@@H HEHEH@@ HHEH} 1 H} & HEH@@HEHHHEHHHEH@@ HEHH HEHHHEH@@HEH@XHƿ&9 HEHEH tHEHE HEHUHPHEHUHP HEH@@ HEHP(HEH@X HEHUHP`HEH@@uHE@hHEH@HHuHEH@@uHE@hHEH (HEH9 HEHHEHߍE UHH H}HuHEH@HHt%HEH@HHUHHE}tETHEHt 8HEH@`HUHH*: E} y E HEPTE UHH H}HuHEH@HHt%HEH@HHUHHvE}tErHEH5t FVHEH@`HUHHM: E} y E*HEH@`H8 HHEH@PHEPTE UHHH}HuHEH@@ HEHp(HEH HUIA H UHATSHH}HEHHEHۿD`HEH豿DRHUBH[A\] UHH H}uHEH@P HEHE} t E\HEH@H UHEH@ʉP HEH@HUHEH@ʉPHE@@PHEP@HE@PHE@@Ѓ UHH0H}HudH%( HE1HEЋ u HEH@Ht9HEЋ HEH@HUHH? tHEHEЉ HEЋHEH H#HHEH@HHME} yEXHEH@Ht=EHcHEЋ HEH@A A H蔶 E} tEUHEЉ HUdH+%( t UHHpH}HudH%( HE1HEHNE} yE7 HEH@Ht EHcHEH@HH HEH} u EHcHMHEHH[~HMHE HH褭 E} t4ETHUHEHHE} t Ep,HEH趰 HEH} uHEH@UHHUdH+%( tƘ UHH@H}HuHUdH%( HE1f)EfEHEHEHEHEHUHEHH\HUdH+%( tY UHH HXHPdH%( HE1f)EfEHPHEHXHEHPH@HHtV HXH#t4 HXH@@pHPH@@ tHPH`xtHcHXHHHEH} u迿: xHcHXHHXHEH} u芿 H(' HH& HD HEHEHLtI tHcHPHH HEHH{Džh HEH || y|l HXH@ HUH)HEHMHE HH诪 ll &HUHEHHll HEHí HEH} uHMHE HHE ll ur6HE t+HEHX@PHX@@ЍPHEHEHM HEH} u|HHEHEh tHHXHJ HXHRR HH¾ H̗HXH@Pp)HXHPXpHHHʾ H莗HXH@pPHEH0 l) h;x HXH@H tHXH@ʉP HXH@HtHXH@ʉPHXP@xHXP@HEH蜭 HX@PHX@@x)HUdH+%( t UHH0H}HuHU؉MH} t HE u3 H} tHEHH#EHuH}v Eԃv HEHtϻ E EHcHEHHHEH} u虻 HUHEHHَE} yEaUHE YHUBHE؉HEPEHE؍ HEH ʉUHEH UHH0H}HuHUH} t HE uܺ H}t+H}t$H}t H} tH}t誺 HEHzt苺 E EHcHEHH~HEH} u UcHUHEHH蘍E} yEBUHE HUBHE؉HEPUHEH UH}} x} y ] UHH0H}uHU؉ME Et萹 HEH`tq E EHcHEHHdHEH} u ;rH} t,HE t!HUHEHHlE} yE?UHEE HUBUHEPUHEH UHHH}uUHEѺ H UHH@H}؉uԉUЉM̋EԉuEЉvtV HEH&t7 E EHcHEHH*HEH} u nHE HUBHE@ HEH`HEUHEUHEPHEỦPUHE؉HS UHH0H}uHU؉ME HEHCtT E EHcHEHHGHEH} u rH} t,HE t!HUHEHHOE} yE?UHEE ϵHUBHEUPUHEHl UHH H}HuUMHUHE H UHH H}HuUMHUHE H UHHH}HEH蒲PHEHK UHATSH@H}HuUMDEE HEȋ@@uڵ HEHHEHEH讱t訵 Et苵 } u Et E׀e} t'} t} w } v;x HEHt} tS HEHt4 E EHcHEHHHEH} u H} t/HE t$HUHEHHE} yE UHEUHEPE EHEPHEHHE} uHEH躯tA A HEH苯XHEHbDމHUBHEH@H UHEH@ʉP HEH@HUHEH@ʉP H@[A\] UHH0H}HuU܉DE؉ЈEE } tE܃#E܅u}vg HEH7tH E EHcHEHH;HEH} u rH} t,HE t!HUHEHHCE} yE?UHEUEԾ ñHUBHEU܉PUHEH` UHH H}HuUUHuHEA H UHSHHH}HuHUHEȋ@@u7 HEHHEHEHFtk H} t HE uJ HH9E~ H9E~躱 HEHt蛱 E EHcHEHHHEH} ue HUHEHH襄E܃} yE UHEHEHEPHEHHEHEHkH} y3HEHaHEH; މگHUBHEH@H UHEH@ʉP HEH@HUHEH@ʉP H] UHH H}HuUȈEMUHuHEA H UHH@H}HuHUHE؋@@u'G HEHHEHEHWt H} t HE uԯ HEHt赯 E EHcHEHHHEH} u HUHEHH迂E} yE~UHEHEȉHEPHEH HEPHEHHEHEHwHEH@H UHEH@ʉP HEH@HUHEH@ʉP UHH0H}HuUH} t HE u覮 }v}tf~HUHE HE} E`UHEHHE}¾ >HUBE$HMHE HH UHH H}HuUH} t HE u ֭MHUHE H UHHH}uUHEѺ H UHHH}uUHEѺ H UHHH}uUHEѺ Hc UHH H}HuUH} t HE u MHUHE H UHH0H}HuU܉MH} t HE u 襬y} t}t}t 臬[MHUHE HE} ~0UHEH腿HEEܺ ƿ >HUBE* UHH H}uE t HEHt ޫsE EHcHEHHHEH} u 諫@HE 莪HUBUHEPUHEH+ UHH@H}HuЉUE ẺQt1> HE؋@@u$ HEHHEHEHt HEHtƪ E EHcHEHHHEH} u萪 H} t,HE t!HUHEHH}E} yEjUHEUHEPHEHHEHEHHEH@H UHEH@ʉP HEH@HUHEH@ʉP UHH@H}HuЉỦMH} t HE u趩 } t}t}t蕩 Eȉtx HEHHtY E EHcHEHHLHEH} u #yHUHEHHf|E} yEXUHE HUBUHEPHEHHEUHEUHE؉Hj UHH0H}HuUH} t HE us HEHCtT E EHcHEHHGHEH} u `HUHEHHa{E} yE?UHE HUBHEU܉PUHEH~ UHH@H}؉uԉUЉMHE؋@@u茧 HEH5HEHEH誤tZ Eԉ]t= HEH t E EHcHEHHHEH} u tUHEHEUЉPHEỦPHEHwHEHEHHEH@H UHEH@ʉP HEH@HUHEH@ʉP UHH0H}HuU܉MH} tHE t}}4 E܉7t HEHt E EHcHEHHHEH} u ¥qHUHEHHyE} yEPUHE 腤HUBUHEPHEHݣU؉UHEH UHHPH}HuHE HE@u HE t.HEH@HH Hƿ HEHHEH @HE HHHEHE@EHEHHE@hHHE@HEHH9s@HEHHEHEH@AȉHH~ Hƿ }w.HEH@HH Hƿ HE EHE@9Er Ẽt3HEH@ỦHH Hƿ rq HEHHEm} HEH@HHx Hƿ *) E E;Es.HEH@HHk Hƿ HE؋@Eԃ} u.HEH@HHe Hƿ MЋUԋEHHHEEH;Es+HEH@HH Hƿ dfHE)EHEHEHE} HEH@HEHE@PHEP HEỦPHEHPHEHHEHEP UHH@H}dH%( HE1HEH @EHEH @ EE HEHHEH HEHUHEHHHUdH+%( tky UHH@H}dH%( HE1HEH @EHEH @EE HEH(HEH HEHUHEHHHUdH+%( tx UHH@H}dH%( HE1HEH @EHEH @ EE HEHHHEH HEHUHEHHHUdH+%( tkx UHSH(H}؉uHEHE}v HE@9Es#H< Hƿ . HE &f9u#H+ Hƿ HE f=t/HE H/ Hƿ HE@<t-HE@H Hƿ }jHE@t-HE@H Hƿ D1HE@9Eu H Hƿ H] UHHH}HEH[uMHEH@HfHEH@8HfHEH@XHfHEH HfHEHf UHH H}up HHEH} uݞ HEUPhEHHHEHHEH Hu E UHEH HMHHZHEH UHE} ufHEH @w EXHEHE} u<HEH?E} u*HEH @ v HEHE} } tHEH EߝHE UHH}HuHEPhHEHEH ] UHH H}HuH} t5HEHHEH H貜tDH HUHEHH HEHEHt7HEHHH Hƿ HEHt E HEH* E} t#EH| Hƿ 6 HEH E} y#EHl Hƿ H HEH E} y#EH\ Hƿ HEH$ E} y#EHL Hƿ HEH. E} y#EHD Hƿ V HEH+ E} y EH< Hƿ kHEH!/ E} y EH/ Hƿ 6HEH!2 E} y EH* Hƿ HEH E UHH}HuHUHHH)HHEH] UHH H}HuUUHEH@HuA A Hu UHH0H}؉uԉUdH%( HE1HEHP0HEH@8H9uwHE HEH@8HHEHUHEH9HBHEH@8HHEHP8HEHH8HEH@( HH聘HEH} uQHEHUHP(HEHp(HEH@0HHHUHJ0HHEԉHEH@ UHHEЉ HUdH+%( tq UHH}E 2HEHP HEH@(MHcHHȋ HH EEHcHEH@0H9rHEH@0 HE@@ ] UHHH}HEH@H HEH@ HEH@Hi`HEH@ HEH@ HM`HEH@ HEH@(H1`HEH@( HEH` UHH}HuHE] UHH}Hu ] UHH}HuHUHEH;E] UHH@H}Huh 腶HEHHEE H} uH轒 H} t$HEH HvHE@t HPHEHEHUHH} tHEH Hv HEH@ HUHBHE H HH@ HUHBHEH@H@t$HEH@H EHEH@ 9 HEHEEHHH[HHEHPHEH@Hu E HEH@ E sUHEH HHEHEHuHEHӓt HEH@UHcHHE܉HEH@UHcHH EE;E|EHHH蔻HHEHP HEH@ Hu E1E HEH@ UHcHH EE;E|ِ} tHEHEHH褐HE UHHĀH}HuHUdH%( HE1E HEH PPEЉHEH H蠨HEHMHE HHK E} t*E HUHEHMHHщE} tErHEHg HEH} uǃEHEH @@U9_HEH@Hu .HEH@HUHMHH1 E} tE HUdH+%( t1l UHH0H}HuHEHEHE؋ E} tHEH @T9Es HEH UHWrHEHEH H@HHt>HEH H@HHUHHE} xUHE؉ L}tEAHEH@`HUHH E} yE HEH PTEЉHE؉ UHH H}HEH @ht * k HUHB`HEH@`HJtHEH@`H(E HEH H@HHu'HEH@`HK HH/ E} HUHEH \HH%E} uhHEH H@`Hf HEH@`H HHEH H@PHEH HUHR`HP`HEH@` HEH @h #HEH@`H HEH@` E UHHH}HE Hƿ ;HEHE@HEHH HEHE@HEHHHEHE UHH}HuHEHE 9u+HEPHE@9uHEPHE@9u ] UHHH}HE@ EHEH HEUHEHHhHEHE UHH H}HuHUHEHH>t HE@ EHE@ EE;E UHHH}HE Hƿ HEHE UHH0H}HuHEHfEHEHOHEHEH?HEE 7HEHE 9uHEPHE@9t HEHEEE9E| UHH0H}HuHEH膋fEHEH͍HEHEH轍HEE IHEHE 9u$HEPHE@9uHEPHE@9t HE HE EE9E| UHHH}HuHUHEHHt :HEH訊fuHUHEHHlHUHEHHUHHH}HEHmtHEHgfu UHHH}HuHEHt(HEHtHUHEHH?HEHE 9u'HEH܋tHEH̋t UHH(H}HEHHEHEH蕉EHEHHEE @HE HEHH HEHE@HEHHHEHE EE;ErHE UHH0H}HuHUHEHHt ~HEHfEHEH@HEHEH0HEE 7HEHE 9uHEPHE@9t HE HE EE9E| UHHH}HEH芊HEHEHHEHE HEHHHEHE@HEHHHEHE@HEHHHEHE UHH H}HuHUHEHHkt cHEH܉HEHEH̉HEHEHE 9u+HEPHE@9uHEPHE@9u UHSHH}HuHUHEHHt #HEHAXHEH2@9H] UHH(H}HEH證HEHEHņfEHEHHEE @HE HEHH2HEHE@HEHHHEHEEE9E|HE UHH0H}HuHUHEHHt ~HEHfEHEHHEHEHЈHEE 7HEHE 9uHEPHE@9t HEHEEE9E| UHH0H}HuHE؋HEЋ 9uHE؋PHEЋ@9t lHEH[fEHEH#HEHEHHEE %HEHE 9t HEHEEE9E|Ҹ UHH0H}HEH H@HHu \ E 8 UHEH HwHEHEH@UHcHHEHEHn H H^ HHR H>HEHHE HEH2HE~HEHHElHEHPHEZHEHHEHHEHHE6HEHăUщH Hƿ >UHMHEHHft EHEH @P9E UHATSH@H}uHEH UHHEEEHEHts HHH< Hu/H H %@ H% HEHHEHEH@H@HtUHEH@HXHEH@H@(AHEH@HHEH@HPHEHHDHyHHH HE HEH@L@HEH@HPHEH HMHHAЄtFHEH@EHEH ỦH諙HEHUHEHHt ẺEȐ HEH@HEH} su HEH+HEHEH@H@HtUHEH@HXHEH@H@(AHEH@HHEH@HPHEHHDHcHHH HE HEH@L@HEH@HPHEH HMHHAЄ HEH@EHEH ỦH葘HEHUHEHHtẺEbHUHEHHBt/HEHtẺE3HEH@UHHEHEH@HEH} - HEHtHEHEH@H@HtUHEH@HXHEH@H@(AHEH@HHEH@HPHEHHDHHHH HEHEH@L@HEH@HPHEH HMHHAЄtCHEH@EHEH ỦH7HEHUHEHH t ẺEȐ HEH@HEH} vEHEH@UHHEȉE;Eu!UHMHEHHt H@[A\] UHH H}E 1HEH PPEЉHEH4E} tEEHEH @@U9r UHH}uHEH@UHHЋ ]UHHH}uHEH@UHHЋ EUHEHtHEH@UHHЋ 9EuE UHH H}uEEHEH UHVH~t EpHEH@UHHЋ EUHEHtHEH@UHHЋ 9EuHEH UHUH`~tEEUHHH}HEH@}t UHH H}uUHEH UH軔HEHEH UH裔HEHEH}uHEH}t HUHEHH UHSHHH}uUHEH UH2HEHEH UHHEHEH|u HEH|HEH |f9t HUHEHHt HEHK~HEHEH;~HEE HEH{EmHEЋPHE؋@9tMHE؋PHEЋHHEHht*HE؋PHEЋHHEHt EHE HE E;E| H] UHSHxH}uUUHEHËUHEH9u UHEHEHEH@ UHHЋ EEx`E;Eu C UMHEHut ! UMHEHt UMHEHPt HEH UHHEHEH UHґHEHEHyfEHEHyfEHEЋHE؋ 9t i f}tf}uwEf;Etmf}uEfEHEHRfE9EfEHEH8fEEf;EuHEH @P9EsHE@@Ef;E Ef;Et E H H[ HHO H>HUHEHH3 HUHEHHj HUHEHHbO HEЋPHE؋@9t 3 HE؋PHEЋHHEHG HUHEHHt HEHxzHEHEHhzHEHEPHEHHEHE} E HEHEHEH HUHEHHt ^ HEHwfEHEHzHEHEHyHEE ;HEPHEHHEH9E} E HE HE EE9E| HUHEHHt HE؋PHEЋHHEHE} E HEHvfEHEHyHEHEHyHEE 8HEȋPHEHHEHaE} E#HEHEEE9E| H] UHH0H}E S HEH@(UHcHHЋ EHEH@ UHHЋ EUHE؉HEUHE؉HEHEH UH"NHufEHEH UHNHufEf}t f}uHEH@UHHEHE@@ f}u f}tHEH@UHHEf}tf}uNf}tGUHE؉Ht2UHE؉HtHEH@UHHEEEHcHEH@0H9 UHATSH@H}uEEHEH@UHHЋ x HEH UHIHEHEHZtfEf}tf}t HEHHEHEH@H@HtUHEH@HXHEH@H@(AHEH@HHEH@HPHEHHDHyHHH HE HEH@L@HEH@HPHEH HMHHAЄ HEH@EHEH UȉHFHEHUHEHH?uWHEHlUȋMHEH Ẽ} yE } t#HEHHE@@uEȉE HEH@HEH} HEH@UHHEĉE;Eu!UHMHEHHt H@[A\] UHH H}E 1HEH PPEЉHEHE} tEEHEH @@U9r UHATSH`H}uEEHEH@UHHЋ u HEH@UHHЋ xUHEH~m HEH UH肉HEHEH@UHH HEH{q H H HH H>HE؋PHEHE} yE UHE؉PHEHhHEHEH@H@HtUHEH@HXHEH@H@(AHEH@HHEH@HPHEHHDHuHHH HE HEH@L@HEH@HPHEH HMHHAЄtFHEH@EHEH UH(HEHUHEHHt EE HEH@HEH} sy HE؋PHEHE} yE UHE؉PHEHHEHEH@H@HtUHEH@HXHEH@H@(AHEH@HHEH@HPHEHHDHtHHH HE HEH@L@HEH@HPHEH HMHHAЄtFHEH@EHEH UHHEHUHEHHFt EEO HEH@HEH} s3 HEHpHEHEHEHxE} yEA UHEHEPHEHIE} yE UHEPHEHHEHEH@H@HtUHEH@HXHEH@H@(AHEH@HHEH@HPHEHHDH,sHHH HE HEH@L@HEH@HPHEH HMHHAЄtFHEH@EHEH UH^HEHUHEHHt EE HEH@HEH} s HE؋PHEHE} yE UHE؉PHEHmfEHEHoHEE 9HEЋPHEHE} yEs UHEЉPHEEE9E|HEHHEHEH@H@HtUHEH@HXHEH@H@(AHEH@HHEH@HPHEHHDH{qHHH HEHEH@L@HEH@HPHEH HMHHAЄtCHEH@EHEH UH调HEHUHEHHxt EE HEH@HEH} vCHEH@UHHEE;Eu!UHMHEHH:tEH`[A\] UHH H}E 1HEH PPEЉHEHE} yE6EHEH @@U9rHEH@H}` HEH@ UHH0H}HuHEH HkEE HEH UH\HEHEHmjfEf}t f} HEH@UHHЋ 9EulUHE HEA A Hb E}u-HE HEA A Hyb E} t EEE;E0 UHHPH}HuUdH%( HE1HEH UH_HEHEHiEHEH^ifEf}t HEH@UHHЋ 9Et HE HUHEHHc t {HEHu kHEHEH H赀HEHEHhfEf}u} u f}u }t HMHEH@UHHЉʉ HUdH+%( tD UHH H} HHHuH\ HEHEHgtHEHg|HUHEHHFE} xME 1HEH PPEЉHMHEHHE} xEHEH @@U9rHEHJ] E UHH@H}HEH @PEHEH@ E HEH@ UHcHHEEHEH @P9E|E HEH @PE#HEH@ UHcHH EEHEH @@U9rHEH H@ HEE HEH @PE HEH@UHcHHЋE9 UHEH H>HEHEH6rE} yE EHcHMHEHH/HEH@ UHcHHE؉HEH H@ HUHH)HEH HP0HEH @PƋE)HHЉʉEHHEEEEHEH @@U9 HEH @PHEH U)ʉP@HEH P@HEH HP8HEH H@ HUH)HEH H@P HEH HH8HEH H@0 HHhHEHEH H@8HtH} uiHEH HUHP0HEH HPHEH H@R PHEH H@PHEH H@@ HEH H@PHEH ʉP UHH H}HuHEHEHEHEHcEHEH@ UHHЋ EEyHEU UHHpH}dH%( HE1E HEH PPEЉHEH H{HEHMHE HHT E} tME HEHEHEHEH@ UHHЋ EEy~HEUHEHW HEH} uEHEH @@U9<HEH@Hu 1HEH@HUH HHO E} tE HUdH+%( tf? UHH H $ H dH%( HE1H HH H H H(H H0H H8H5 H@HO HHHi HPH HƿLEyAHHHW Hƿ H`HV!Dž q H H:HH uL轛 ؉ HHH* Hƿ f2 HHH- Hƿ H HH H`H H HǸ TH HƿDumH H9HHH] HHH Hƿ u H= Hx Hƿ NeHUdH+%( t< UHHpH}HudH%( HE1HUHEHH: P HǸ RHUHEHHHUdH+%( t@< UHHPH}HuHUHEHHEHEH HExE HEHHE:HEHHHEHUHH҉E܃} yE EHE@HEHE@U9rHEPHE@HHEHEHHE@ HH9EkHEHHHEHEH HEuE HEHHE7HEHHHEHUHH҉E܃} yE\EHE@HEHE@U9rHEPHE@HHEHEHHE@ HH9En UHHPH}HuHUHEHHEHEH HE@HEHUHMHHщE܃} tE HEPHE@HHEHEHHE@ HH9ErHEH(HEHEH HE HEHUHMHHщE܃} tE E HEHHEcHEHHHEHUHH҉E܃} tEX HEHHHEHUHH҉E܃} tE/ EHE@HEHE@U9rHEPHE@HHEHEHHE@ HH9E HEHHHEHEH HE HEHUHMHHщE܃} tE E HEHHE7HEHHHEHUHH҉E܃} tE\EHE@HEHE@U9rHEPHE@HHEHEHHE@ HH9EI UHHpH}udH%( HE1HEH UHsHEHMHE HHrL E} = EU HE HEHE@ 9 HEHPHE HHЋ HEHEH H;sHEHEHL[uN/ HHЃHt4HEHEHPHE HHЉʉHEH[tE9HEHZHE щH Hƿ VHE u+HEHEH|E} tE*HEHwN HEH} HUdH+%( t6 UHH@H}HEH@@PEHEH@H-[EE E z HEH@UHcHHЋ D UHEH HqHEHEHYEHEHEH HHE} }}8} } }to} q Eb ; E HHH / H H@ H % H E߃Z HEHUHHE } t4HE . HEHHEH@HUuHǥE HE HEHUHH贚E } t1HE HEPHEH@HMHH<EzHE HEHUHHTET} HEHUHH2E2MUHEAȉHH] Hƿ W} xMEPUHUHRMHcHHʉ EHEȋ@ U9tE UHHpH}udH%( HE1HEH@UHoHEHMHE HHG E} tnE HEHPHE HHЋ t#HEHPHE HHЋ HE&HEHE@ 9rHEHE@()HEHEHJ HEH} u HUdH+%( t2 UHSH HxHpHhdH%( HE1HE HE HxH4WEf)E)E)EE HxHSHEHp tHh tH} uzZ XHEH} u[Zd HxHO3HEHOE HxHEHEHu E HxHEHEHE HHHgHI HEHEHTt Eh HEHVEHEH@@EHx@PE"UHEHE} EE;ErHEHbE} HEH*'HEH} uJ ؉E HEHEHx@PE8UHxH-lHEHUHEHHkE} xEE;ErHEHE} xa]HEHU)ÉډЉEHEHTEE UHEH^E} xEE;Er HEH HEH7I } t$HEHHEHEX!HpHUHHhHUH HUdH+%( tv/H] UHH}HEH@] UHHH}HuHEHUHPHHEHSHEPPHEH@@HEPT UHH H}HuHMHE HH V E} uHE@i E/WUHH}} y /UډEUHH}} y E UHH0}HuHUH} tH} u& EIE} 9HUHMEHΉc EHEHPHEH Ea } wE- HH H HHEHUHuHEHHa HǸ "DEHEHPHEH EHH;Er ^ WUHuHEH HǸ CEHEHPHEH EHH;Er o c UHH }HuUEHcЋEIHMHΉ2E}u d E} t_}u0EI؉EHcHEHo HǸ C)EHcMUHEAȉHW HǸ BHEUHH}Hu HE t HEHmH} ݸ ]UHH H}HuHUHMH}w.HUHEHHH Hƿ THEH+EHHUHEHHHZt'HEHH Hƿ 賸 UHH}} y UډEUHH}HEH]UHHH}HEH UHHH}HEH UHHH}HEH UHHH}HEHH UHH}HEH]UHH}HE HHEH]UHSH8H}؉uHUȉMHE؋ EЃ= v H} } 1Єt HEHrHEEԉHEfPEЍPHEfH} t'EHcHEH)HHEHHHHE؋ HE HE؉ H]UHH H}uHEHHEÈHE Ht HEUHHH}HuHEHH+EHEf UHH@H}ȉudH%( HE1E HE H+fE Eĉ¾ ":E} yt HUEA HѺ yH Hƿ 蹵HME HΉW|y ؉EME HUHMEHΉ y ؉E E܃ t E\UHEȉE E~ EHUdH+%( t( UHH}EL UHH }HuUUHMEHΉ?E} yA t5 t˃} y # E UHH H}uEHcHEH HH HEH} u HEHUHEHcHEHP UHH }uUHxLpLhdH%( HE1HE HE f)E)E)EfEHEHEHE EHE H E} E HME" HΉE} y EE EHHUH9s UHEHE} HME HΉ:E} y EE~ } c HEHE( HE@ 9Et EUO HEPE9t ET5 HE@tEHE@ttAHx <HEHHEHE tvHE EHEH8G E HhHpHELxHHAЉE}t } } t}vuE mMHE )ЉEHE HE}~ HE vHE U9} tE HEHEHUdH+%( t~$ UHHPH}؉uHUHMLEdH%( HE1E UHEHE} yE HE@ 0ZHE؉PHE؋ Hu؋E *Hyb ؉E2HE؋@AuH}HMHUȋEIIHD҉oEEEHUdH+%( t# UHH`H}HuHUdH%( HE1HEHHEHEHHEHEHEHE HUHEA H9CHEHu HEHHUf HUdH+%( t" UHH H8H(f4dH%( HE1HP HHHHDžP fDžT fDžV ƅ`ƅa4H8HP HzLL yL*H(HPIй H H{HUdH+%( t! UHH <840dH%( HE1HP H2$DžP fDžV fDžT ƅ` <dHP+ HzHHHH u H8HP HVDD y D 0t:H0HP HDD y D 0t7H4HP HDD yD=HHHPHHHPA HHUdH+%( t! UHH0}uUHMH} t2HEHHEH \ Ht 6XH} tHEH H v HE؋@ E} tMEMUuEEE UHH}uHUHMUEDŽ UHH` HHHdH%( HE1HHHH HHHHHA A H>tS%HHHLHHAHUdH+%( tq UHH H}HuHxdH%( HE1HEHEHEHEHE tHEHE@9t HxHX H Hu HxHX HHE H:?E} tE HEHu HEH3HUBHE@u uHEHtHEH>HUBHEHtHEH"HUBHEHtHEHHUB HEHtHEHHUB HUdH+%( t UHH HhH`HXdH%( HE1HhHHxHxHHEHXHEHh HUHEA H<HEHt HEHu \HEHtHE 9tt 5HEHHUHBHEHtHEHHUB HUdH+%( t UHH HdH%( HE1HP HHHHDžP fDžT fDžVƅ`f) )0fօ@HDž HDž H t;HHHH , HtW- v= #t $H HPIH HH) H t H t HH H v(HPH t HH Hv,HP H t HH Hv0HPH t HH Hv4HPH t!HH Hv8HPH tHH H'w H H¾ H HR y/ uHH@ < Y/ HP HtDžP fDžV fTƅ`ƅaHHP H y HHPIй HT H t ^H t"HH H'vHHHP H t"HH H+vHP( HUdH+%( t UHH |xHpdH%( HE1HE0 Hf)E)E)EHE0 HEHUHEHUHEHUHEHUHEHUHEHUHUx|ΉCE} tET xE<tx uUHp^xtUHpCxtUHp(xtUHp Hp HUdH+%( tK UHHH}HE@ HE@ HE H HH UHH}HuH} tHEH Hv HE@ wu It=BH} t HEH HvHE@t!HEHFH ] UH}Hu}w} u D}t-<HE t8}uHEHE u ] UHH H840dH%( HE1HHH8HHDD y D HP H*DžP$ 0fV4fTƅ` H8 t H8H H v H8@ dHHHPH҉DD yD$HPA HaHUdH+%( t UHHH}HE $ H UHHH}HE % Hr UHH H}H} tLH} t&HEHHEH Hu H} tHEH H v HE@ qHEH5EEV UHHH}H} tLH} t&HEHHEH a Htu H} tHEH H v HE@ H} tHEH Hv HE@ tKwRwu Gt!@HE H +HEHsrf Z UHSH HhH`HXȈTdH%( HE1HhHxHx tHxH Hu F T tHx@t $ HXHH Hu HXHHHE H2HEHu HxH Ht,HxH H HvHEHxHHCHxH Ht*HxH H HvHxH H`RPHxH Ht-HxH H HvH`PHxH PHx@T t HUdH+%( t*H] UHH HXHPHHdH%( HE1HXHHhHX $HhHPHpA H/HxHu 6HX@HpHhHHHrHUdH+%( tO UHH HdH%( HE1Dž H HHH HΉ y HH H y H HP@HAHH HǸ $ y k 8= v$HHH HCHUdH+%( t UHSH HHdH%( HE1HDž0 HDž8 H tvH tlH t,HHHH H)u6H t;HHHH Ht[ H t HH H v H@ H t HH Hv H@ H t HH Hv H@ H t HH Hv H@ H t HH Hv H@ H t HH H v H@ H t HH Hv H@ H t HH Hv H@ ~ t t v vv t Dž H@ H Dž@$ f fFfDžD, ƅP T XË : ؉`H H։$$ y$ \H@ H Hg$$ y$pF H@ HH(H( u< H@Hl$$ y$ Dž HH@ H$$ y$ H(H@HHHH0H0H@Iй H H$$ y$G 8t -$HUdH+%( tH] UHSH HH ЈdH%( HE1Dž H tlH t,HHHH ݵ Hu6H t6H HH H Ht I H t HH H v H@ H t HH Hv H@ H t HH Hv H@ $H t H H Hv H @ (H t H H Hv H @ ,H t H H H v H @ 0H t H H Hv H @ 4H t H H Hv H @ 8 ~8 u0 u 4 t , v } t(( t , u S Dž ( u , t + H@ HNDž@$ fDžF fDžD- ƅP Tt2(X,Ë j5 ؉`$HH։<< y<u\t7H@ H H<< y<$H@A H HUdH+%( tH] UHH H}HuH} u %HMHE HHEE UHSH HHdH%( HE1HDž0 HDž8 H tvH tlH t,HHHH _ Hru6H t;HHHH = H<td H t HH H v H@ H t HH Hv H@ H t HH Hv H@ H t HH Hv H@ H t HH Hv H@ H t HH H v H@ H t HH Hv H@ H t HH Hv H@ $ ~-$ u$ u u t u v| Dž( H@ HDž@$ fDžF fDžD. ƅP TXË(!1 ؉`HH։h,, y,* \H@ Hc H,, y,vHH0H0H@Iй H% H,, y, 8t m,HUdH+%( tH] UHH}HuHUHEH@HEHEHEHEHHEH H9_ HEH@ HEȋ@$EHEȋ@ EE E E HEȋ@,HEHEH HEHEHEEH HEHHHEH H9 HEH@UHHEԉE܃H HEHH HUH)HBU܃H HUHʋH9 HEH@U܃HHE+E؉EԉEE HEH H9EsLEE;Es E;E E;Eu/HEH@UHHE+E؉ ] UHHH}H} tMHEH HHEH@HHEH@HHEH@HHEH UHH0H}HE؋ E} u&[ [ HE؋ w[ 7 0 CDHEH} uZ HEUP HE؋ HEP(EHUR(HHEHEHJHHEHHEH H HEH HHEH HUHHHE؋@hE} tTHEH HtDHE؋ 9Eu5HE؋ v&HE؋@l9EuHEH@pHt HEH@xHu HE" HEUP$HE؋ HEP,EHUR,HHEHEHIHHEHPHEH@H HEH HHEH@HUHHEHHIHHEHPHEH@Ht\EHHkIHHEHPHEH@Ht8HEH@xHHEH@pHHEHHuHE) HEHKX UHHPH}HuUMHEȋ@$9ErX HEH@UHHЋ E؋E;ErZX HEH@UHHЋEЉEHEȋ@,EHEHPEEHHEHEHEHEH H9EsW rE)EHEȋ@(EHEHEEHHEE 'HEH H9Er$EHEEHEHEHEEE;ErEHHHEH UHH0H}؉uԉUHE؋@ EE;ErDW HE؋@(EHEHEEHHEHEHEHE 9EsV HE)EE HE 9Er EHEHEHEEE;ErEHHHEHUHH}} y VUډE UHH0dH%( HE1H HEHE Hƿat HEH HH}[HEH} u cHuHMHUHEIH5T HǸ EHEH}t EE E 9GHUdH+%( t UHH0H}dH%( HE1HEH Hץ HH HEH} u SHuHMHUHEIH5 HǸ t EE E 9GHUdH+%( t^ UHH dH%( HE17ll t l HpHHpHll tluHhHdH`HpH IHHHĤ HƸ t )`d h 9GHUdH+%( ta UHH H $ H@ HHHLdH%( HE1Hp HH HAH HHHDžp DHHHHHHHHH H(HHH0H8HHH@HHHHHPHXHHH`HhHHHpHxDž HDž B H H HH H>Dž Dž Dž $ , Dž HHpDžl Džh u Dž Dž Dž0 DžH HuHHpDžl Džh Dž0 DžH H/Dž$ #DžDž - HHHIIHH B P ؉ x ` tT y;t DH t%HHHHHu HUdH+%( t UHH@}HudH%( HE1EEEEEfE E EEEEEfE E HE H} t *HUHuEA EԋEԉHUdH+%( t UHH HhH`HXHPDLdH%( HE1f)EfEfEEE H`EH`EHPEHE( HL t Lf)E)EfEHE( UEHEHUHEHUHEHUHEHUHEHEUEEЉppHHp>HxHx u HMHx HHzEEHxHHhHHTEƋEEHHxH HXHHH"pHcHUHxHH#tHxHtHUdH+%( t UHHĀdH%( HE1H bpf_spiHn_lock vHEHUH_lock vaHl cnt l HEHUE E E E E E E E E E E E E E E E E E E HUHEA L HHUdH+%( t UHH LdH%( HE1HE8 H*f)E)E)EfEHE8 HEHUHEHUHEHUHEHUHEHUHEHUHEHEDžd Džh DžlDžpDžtDžx Dž| DžX Dž\ Dž` L!_ LH H HH H>Dž\ 7 DžX Dž\ E DžX Dž\ Dž` DžX Džd Džh Dž\ Dž` E 6pp p DžX Dž\ `mE EDžxSDžX Dž` =DžX Dž\ Dž` HE E ; L t L u=A A tt xrtEp xpEdEhE`\XH}LIA l+I ؉|l x lt x tp x px t%l y|;xu l HUdH+%( t UHH }HuH} t EEE UHH H $ H@HdH%( HE1ƅfDž ƅfDž Dž HDž H t w ƅ HHHA P yoo uaHH HHHu<HHژ HHHu HHΘ HHcHt HUdH+%( tUHH}HE]UHH}H} HuHEH= Ht ]UHH}u} u "HEH|Jy7Hи@ +EHH] UHH}HuHEHHEHPHEHUH] UHH}HuHEHPHEHHEH@ ] UHH}HuHUHMHEHUHHEHUHPHEHUHPHEH@ HEH@ HEH@( HEH@0 ] UHH0H}HuHUؿ8 Y5HEH} uHv HMHUHuHEH?HE UHH0H}HE QHEH@HUHHH HEHEH HEHEH} tHEH@HE uHEHEH@ H9ErHEH@HHEH@ HEH@0 HEHP0HEHP(HEHP(HEHP UHHH}HEHuHEHHEHf UHH}HEH@0] UHH}HEH@ ] UHH}HEH@ Ht-HEH@0HHHHHHEH@ H9s ] UHSHXH}HEH@(HHEH}wHE HE HHHEHEо Hh,HEH} u HE HEH@HUHHH HE\HEHEHHEHPHEH HHщH\HEHEH HEHHEHHrHEHEH} tHEH@HE uHEHEH@ H9EUHEHUHP HEHUHP(HEH@HHEHUHP H] UHH@H}HuHUHMLEHEH@Hu HEH@HUHHHEHEH HEdHEL@HEHPHEH HMHHAЄt$H} t HEHUHHEHUH $HEHHEHEH@HEH} u UHSHXH}HuHUMLELMdH%( HE1H} t HEH H} t HEH HEH@(HEHHEHPHEHHщHiHE} HMHUHuHEIȹ HthH} tHEHHEHH} tHEHPHEH}t}u!HEHUHHEHUHP } u }u HEH>tPHEHEԃ} tE HEH@(HEHHEHPHEHHщHcHE /HEHEHuRHEHUHHEHUHPHEHUHRHMHHHHDHEH@0HPHEHP0 HUdH+%( tH] UHSHHH}HuHUdH%( HE1HEH@(HEHHEHPHEHHщH~HEHMHUHuHEIȹ Ht H} tHEHPHEH HUdH+%( tH] UHSHHH}HuHUHMdH%( HE1HEH@(HEHHEHPHEHHщHHEH}HMHUHuHEIHt cH} tHEHHEHH} tHEHPHEHHUHEHHHEHHEH@0HPHEHP0 HUdH+%( tH]UHH}HE]UHH}HEH= H]UHH}H} HuHEH= Ht ]UHH}HE@ ]UHH}HE@]UHH}HE@ ]UHHH}HEHfUHHH}HEHfUHHH}HEHgfUHHH}HEHFfEf}tf}u UHHH}HEH fUHHH}HEHfUHHH}HEHfEf} tf} tf} tf}u UHHH}HEHfUHHH}HEH_fUHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEHEHEH H HHEH H ]UHH}HEH ]UHH H}uHEHHUHHHHHHEHEHE} tHE@% HE@UHH H}uHEHrHUHHHHHHEHEHFE} t HE@ UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HE (HUHHH)HHE HHHEHEHE uHE]UHH0H}HuHUdH%( HE1 HEHeq HEHȃHt HUHEHH HUdH+%( tlUHH}HuHUH} t[HmHE HUHEHHMHUH HEHEH;EsHUHEH uHUHEH ]UHH}Hu HE t HEHmH} ݸ ]UHH H}HuHUHMH}w.HUHEHHHA Hƿ g THEH+EHHUHEHHHZt'HEHH Hƿ 4g UHH}} y 7UډEUHH}h7Uډ UH}EH H9s EHH)H HH ] UHHH}HuHEHP UHH H}HuHUHUHEHHa UHHH}uHEH UH UHH H(H H`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1Dž0 Dž40 HEH8HPH@H(L@H(H@H0H HHAАHHdH+%( t@ UHH0H}HuHUHMH} t5HEHHEH ) H?tk H} uU HEH} u, HEHUHHEHUHPHEHUHPHEHHt HEP HHHHHUHBhHEH@hHmt!HEH@hHKEHEH@h w HHHTH/HUHBpHEH@pHt!HEH@pHEHEH@p HEH( E} uHEHEHE UHH H}HEH H*EHE@ 9E EHHUHr0HUHz(H t EHHUHr@HUHz8H tZHE@ u&HEH@(HEH@(HEHh E} tEHEUP UHH H}HE CHEH@HUHHH HEHEH H:HEH@HEH} uHEHEH@ H9ErHEHj UHH H}HEHI HEH@(HHEH@8HtVE AHEH@8UHcHHH Ht HEH@8UHcHHH H~EHE@ 9E~HEH@8H^HEH@HHNHEH@XH>HEH@hHHEH@pHHEH UHH H}uHEH H9Er HEHRE} t E~HE@T MHE Hf E} y EhHE .HEH@HUHcHHЋHE H EHE@T9E|Ƹ UHHPH}HEH HEHE@ E UHEH HHEHEHfEHEHl H H HHՂ H>HEHP(HE@HH@E HEHHEHEHP(HE@HH@HEHP(HE HH@ HEHHEE )HEHP(HE؋@HH@EHE E9E| HEHfHEE )HEHP(HE@HH@EHEE9E|THEH=HEE (HEHP(HE HH@EHE E9E|EE;E# UHH0H}؉udH%( HE1HE؋PTHE؋@P9|xE HE؋PPЉ EUE9MHHEHEH@HHM HHHEH} uFHEHUHPHHEHE؉PPHEHpHHE؋@THHU؉JTHHHEԉ HUdH+%( t1 UHH@H}ȉuĉЈEHEH@(UHHHEHE <u HEH UĉHHEHE <uRHEHt} tHE t s EĉH Hƿ \K HEH. H H HH H>HE HEHHEȺ HEHEE HEH?HEȺ H HEHHE} tHE t s HEHEH3fEE 4HEHHEȺ H(E} yE EHE E9E|HE t"UHEȉHE} yE HE HE uHE @u"UHEȉHE} tE HE v UHEHHEȉHTE܃} yEL } t} u 6 UHEȉH-E} tE HEH@(UHH UHEHHEȉH HEHHEUHEHHEȉHE} yE } EHEHZfEE :UHEHHEȉHPE} yEK} ~EEHEE9E|E)HEH@(UHH UHH H}uHEH UH HEHE u .HEHEHHH| HH UHHPH}uUHEH@(UHHHE} EHE < HEH UH|HEHEHfEHE < HE V E } t| E;E0 HE u#EH{ Hƿ W HUMHEHZ HEH{ HHǸ }HEXUHEH[t3HUuHE H, HEH{ HHǸ $HEl E^ H HY{ HHM{ H>HUMHEH HE } t3HUuHE H1 HEHz HHǸ HE HEHUHEH HEHUHEH HUMHEH HEHjz HHǸ HEA HEHEHUHEH)HE uKUHEHt3HUuHE Ho HEHy HHǸ gHE HE} u HE ujHEHHEHEHfEHE uEEEE !UHEHHEHGEHE E9E|RHE uDE;Et<HUMHEHa HEHx HHǸ HE} tGHUuHE H HEHx HHǸ ?HE HEwHEHHEHEHfEHEHUHEHNE !HEHUHEH-EHEE9E| UHHPH}ȉuHUdH%( HE1E HEHXHEHEH1fEE ~HEPHEȉHzEUHEHE} t)} u#HE@UѺ Ѕt UEE؋EE܋U܋E9MEEHE E9EuHE@u щȅt HUdH+%( t UHSH Hhd`\DDTXdH%( HE1Hv HEHh@EHv HEE Hv HEE Hv HEE d;` E bEHHH@HHH EEHHH@HHPH HEEEEPdЙ}EEE;`~EEvE;d E;` X uUE;`u'\EEPdЙ}E;Eu#E;`tk`+EE+d9SX t E+d T HHUHhAHHH5nu HǸ Ed `+dxE||x9NEE;EuITHƋMHUHhAHHH5t HǸ Ed E EHHH@HHPH HEEHHH@HHH EE;E|FTHƋMHUHhAHHH5]t HǸ Edm} od;`HEdH+%( teH] UHATSH H}uHU؋UHEHU IHE؋ t H s H s HEH*t Hs Hs H}MHHHs HƸ H [A\] UHHpH}uHUMdH%( HE1HEHcHEHEHEE E HEH"fEHEH UHuEȀ} t&HEH HUMHot EUHEH. HHE t Hr Hr } t Hr Hr H}IHHHr HƸ E HEHEHOHEUHEHE̋UHEHNEЀ} uHEPHEH Ho EԀ} t } t EeED@}MԋUЋuHEEAHWEHHEH q HHǸ EHHEpHUHEH/ } t/UHEH {q HHǸ sUЋEЉEELHE HEPHEH HsHEHUHEH9HME̋E̍ EЉEE HEHq HHǸ EHE E9EY} t1EHHE@NjUȋuHEAA щH&f} u HE@tEHEHp HHǸ EHHEH jp HHǸ YHEHQp HHǸ <} tHEH2p HHǸ HEdH+%( t' UHH0H}uHU؋UHEH HEE cEHHHHP HHEHHu5EHHHH{P HHMHEH5 p HǸ r EEv UHH H}uHUUHEHz HHEH o HHǸ UHSHXH}HuUfEHEHHEHEHEE HEЋHEHHEHEHHpHUHEHH HEH}v\} t H*o H3o HEHEЋXEHHMHUHuHEAIHHHǸ 6S} t Hn Hn HEHEЋXEMHHUHuHEAHHHǸ EHEE9EH] UHHPH}HuUfEHEHAHEHEHqEE HE؋HEȉH>HEHEHHpHUHEHHj HEHEHHEH}vY} t Hn Hn HEEMHLEHMHUHuHEMIHHHǸ P} t Hm Hm HEEHHMHUHuHEIHHHǸ EHE E9E UHH0H}uHU؉MHEHfEUHEHq HHE؋ t Hk Hk H}HHH2m HƸ f} T HEHm HHǸ HEH^tMUHuHEHMUHuHEHEHHEH l HHǸ fHE؋@u HEHl HHǸ ? HE؋@ HE@ HEHtELEE 6HEHHEHcHHHHHȋ@tE EE9E|} t HEHl HHǸ UHH0H}uHU؋UHEH HEHEHAt!HUHEH k HHǸ 7 HUHEH k HHǸ UHH0H}uHU؉MUHEHX HEHE؋@u7HEH]k HHu HEHUk HHǸ 5HEHak HHǸ HE؋pMHUHEH UHH0H}؉udH%( HE1HE؋PdHE؋@`9|xE HE؋P`Љ EUE9MHHEHEH@XHM HH(HEH} uFHEHUHPXHEHE؉P`HEHpXHE؋@dHHU؉JdHHHEԉ HUdH+%( t蟶 UHH0H}uHUH} t5HEHHEH j Ht5 HEHE} tE H} tHEH Hv HEH@Hg HEH} tHEH Hv HE؋@ EH} tHEH Hv HE@ HUB MHUuHEH HE@ UHHPH}ȉuHUMdH%( HE1HEȋ@dEHEH UĉHbHEHE@ tHEHuGUHEȉHEԃ} y0EԉHh Hƿ AHEȋUЉPd } HEH_ua HHH HuzH. HuHu HE؋@EDHEH E1HEHUĉщH6h Hƿ 0A HEH@XUHcHHHEHEȋ@d+EЉEMHUHuHEH HEȋUЉPdHEdH+%( t辳 UHH H}Hu HEHHE@HHHHЋ EHEH UH華HEHEH tO t t xHEHpg HHǸ 9HEH]g HHǸ HEHGg HHǸ HE@PHEPHE@) UHH H}Hu\HEHHE@HHHHЋ EHEH UH蝮HEHEH*u HE@PHEPHE@u UHH0H}HuЈEHE tE܃t Ee} t Hc Hc HUH}HHH,f HƸ UHH`H}HuHUME HEHHE@HHEHHE@HHHЋ EЃ} u7HUHEHHHEHe HHǸ "E " HEH UЉHFHEHEHfEEȃ H He HHe H>HUHEHHHEHEHqHEHUHEH e HHǸ wp HUHEHHHE u*HE@ tMHUuHEH) HUMHEH HUHEHHcHE u*HE@ tMHUuHEHe HUMHEHU HUHEHHHUMHEH HUHEHHUHEH HHEH c HHǸ A: } t Hc Hc HMHHc HHϸ HEHc HHǸ HEHic HHǸ HEHPc HHǸ HUHEHHHEHEHSHEHUHEH c HHǸ YR HEHHEHUHEHHHE@u>UHMHEHHHEPHEH b HHǸ HEHHE@HHHHЋ EHEH UԉHHEHEHEHE t&EƃtHEHT_ HHǸ pEǃtHEH-b HHǸ JMHUHuHEHEǃtHEHa HHǸ HEPHEH a HHǸ HEHHEHEHfEHUHEHH HE@tOHEHta HHǸ MHUHuHEHHEH@a HHǸ [UHMHEHH HEH a HHǸ 'f} tf}u+HE؋@u HEH` HHǸ E } ~HEH` HHǸ Eʃ9Eu(HE؋@u HEH` HHǸ HHE؋HEHPHEHE؋pMHUHEHEHEE9EcHEH` HHǸ *WEȋUЉщH7_ Hƿ 181f}EHE@eUHMHEHH UHH H}uЈEHEH@x@0 HEH UHЦHEHEH HEH } tHEH%_ HHǸ BHE@ HE@ uHE H[ HHE@ HE@ } t!HEH^ HHǸ UHHPH}HuHUdH%( HE1HE HEH褊HEH} u tHMHUHEHHHEHHEHEHHuHUHEA Iй HHE܃} t HEHNHEHBHEHUdH+%( t* UHSHxH}uHUdH%( HE1HEH@(UHHHEHEH UHHEHEHEHuHEHEH@8UHHHEHE u HIZ HE t!HEH Ht HEH p HEg HEHu!HEHt&HEHfuHE HE! HUHMHEHHHEH} HHHE HEHHEظ HPHEHо HHkHH HH)H9tH H$ H H)H Ht% HHH HHEHMHUHuHEIHH\\ HǸ 觽HEH HHEHHHE HEH Ht HEH HEHUdH+%( tH] UHHH}uHEHPhMHEH UHHH}uHEHPpMHEH] UHH}HEH@x@uHEH@x@,u HX H&X ] UHH}HEH@x@,u HW H<[ ] UHH H}HEH@x@ HEH@x@,ЉEHEH@x@u>E +HEH@xHP HEH Z HHǸ EE;E| UHH H}HuUHEHHEH Z HHǸ 7 UHHPH}HuHUȉDLMEĉЈEHEHEHE HEЋ@v,HEЋ@H<Z Hƿ 1 HEЋ@E)HEHHEHcHEH HHEm} yUEЈEU@ )fEU@ )fEEHUHEHHEH UHH@H}HuHUȉDEĉЈEdH%( HE1}MLEHUHuHEMAHE} tEHEHu HUdH+%( t£ UHSHHH}HuHUDEЈEdH%( HE1}MLEHUHuHEMAHE܃} tEBHEHHHEHHHUHEIH5X HǸ HUdH+%( tH] UHH0H}HuUHMHEHrfu HE@E HE@E} ~}~*U܋EщH X Hƿ /,EHcHEH q? HHf u UHH0H}uHU؋UHEHLE} u HE؋UHcʺ HHHH UHSHhH}HuUHMDEdH%( HE1HEHEEEHE@E} tEv-UEщHV Hƿ . HEH HUMHt!EHcHMHEHH5HEHE} EH HW HH W H>HEHEHEH HEHEHH HEH} uBHEHGHHEHuHHUHEIH5 V HǸ x HEHHHEH3HHMHUHEIIH5U HǸ /\ } tEHEHHHEHHHEHHEIH5U HǸ HEHqHHEHHHEHHEIH5U HǸ } tDHEH&HHEHTHHEHEIH5?U HǸ U HEHHHEHHHEHEIH5U HǸ > } tHHEHHHEHHHE HEIH5T HǸ HEHPHHEH~HHE HEIH5lT HǸ { HEH@x@2 HEH@x@1 HE uJHEHHHEHHHEHH5T HǸ HEH@x@1+ HHE HHH % @ tHHEHcHHEHHHE HEIH5S HǸ } tEHEHHHEHCHHE HEIH5*S HǸ @pHEHHHEHHHE HEIH5R HǸ +UEщHR Hƿ * HUdH+%( t֜H] UHSHXH}HuUHMdH%( HE1HEHEHE@EHEH HUMH't!EHcHMHEHH[HEHEȃ}t } } }tU HEHHHEHHHE(HEHd$<$HH5@R HǸ H HEHOHHEH}HHEH0HEHfHnH5Q HǸ xHEHHHEH6HHE fZfH~HEHfHnH5Q HǸ #*UEĉщHP Hƿ +( HUdH+%( tH] UHH@H}HuЉUHMHEH耾 E} t}tHQ HEHQ HE HSL HEHUHEH N HHǸ YHEЋ@EHEH UH|HEMHEغ HRHEЋHE؉HHHEH P HHǸ HuMHUHEHj A I H H UHSHXH}HuUHMHEHHEHE؋ EHEH MԺ H}iHEHEH UԉH艆HEH} /UHEHHO Hƿ U&p HEHtH}u HEH@x@2HEH@xP,P,HEH|HHEH O HHǸ HEH@x@0EHEH@x@0HEH@x@1EHEH@x@1 E KHEH@x@1uIHuMHUHEHj A I H+ HEHEHEHE؋@9ErHEH@xUΈP0HEH@xUψP1HEH@xP,P,HEHHEH~HHEHHHEHH5N HǸ 賾 H] UHSHXH}HuUHMHEHmHEHEHFfEE HEH@xP,P,HEHHHEH N HHǸ *E HE؋PHEH HGHEHE؋HEHŽHEUHEHعEԋUHEH%E}ɋEAEHELHE؋HHUHuHEHWHg HEЃ} yEoEHE E9E<HEH@xP,P,HEHEHEHHHEHHHEHH5L HǸ EH] UHSH8H}HuЉUHMdH%( HE1HEH HUM̉HtQHE؋@uEHEH:HHEHhHHEHHEIH5`L HǸ h HE؋@HcHMHEHHgzHE؋@u>HEHHHEHHUHEIH5K HǸ =HEHHHEHHHUHEIH5RJ HǸ 迻 HUdH+%( tǔH] UHHPH}HuHUȉMLEdH%( HE1HEHMEHEH HUȋMĉHtOHMHUHuHEIA HE} tE HEHHEH HEЋ@t& t0 tvtF HEHHEH } t HEȋ HHEȋ HUH } t HE H HE HUH W} t HE H HE HUH ,HEЋ@UĉщHJ Hƿ 2 HUdH+%( t UHATSHPH}HuUHMdH%( HE1H}ЋMHUHuHEIHẼ} tE# HEHiEHEH E HEHHEzHE؋@HcHEH9u]HEHIHEHHHE؋HEHHHEMHH5C HǸ w EHEHEH袲9EnHEHRHHEHHHUЀ} t HH HlG H}IHƸ t E HEHHEyHEHHUH9uZHEHIHEHHHEHEHHHEMHH5B HǸ |EHE HEH觱9EoHEHWHHEHHHEHƀ} t HG HG H}IHHHƸ p HUdH+%( txHP[A\] UHATSH@H}HuUHMHEHIHEHHHEHEȉHնHHEMHH5/G HǸ ݶE HEH諳HE HEHEH HHEHE@HEH4HEHUHEHj A I HP HE܃} yEAHEHKA HHǸ >EHE HEH9E\ He[A\] UHH@H}HuUHMDDʈE؉ЈÈ} tIUEЃPHEUHEHHEH@xH H9r E HEH U܉H{HEH} x H}~/HEU܉HHE Hƿ v HEH Mܺ H3^HEH} u%E܉HE Hƿ *jHEH詮uIF HHЃHt/EHEHHEHHEH@xH H9s HE UHHĀH}HuUHMDDʈEЈEdH%( HE1HEH@x@ u2HEH@x@,t#HEH@x@0t HEH@x@2t HEH M H\HEHEH蜭 H HD HH}D H>} t$}MHUHuHEAHWS HMUHuHEH7 HMUHuHEHw HEHîHEHE EHEH UȉHPyEHEH MȺ H\HEHEHt }u EeE g} u} tHE u { }EẺHEH UHuHEA AHE}tE9 EHE@U9r HEH/HEHEHfEE HE؋PHEH HKHEUHEHEċUHEHAE}EAEHEH HE؋PHuHEAHE}=tEeEHE E9E^HH}ЋMHUHuHEIHE} tE HEHu HUdH+%( t> UHHPH}HuHUȉMLEDʋEUEdH%( HE1E DE}HMUHuHEEAHE} yE DE}HMUHuHEEAHE} t}uE E HEHZHEH@x@ tGH} t*HE t HUHEH 7A HHǸ MHEغ H)HEH Mĺ HXHEHEH莩 H H@ HH@ H>UHMHEHHE } t'}MHUHuHEAHE }HMUHuHEAH\Ee HMUHuHEHiEF HMUHuHEHE' HMUHuHEH E HMUHuHEHE } tZ}MLEHUHuHEMAHWE} HEHEHMUHuHEHqE HMUHuHEHREmHMUHuHEHHEQHMUHuHEHE5HEȋ@ EĉH? Hƿ } yEEHUdH+%( tɆ UHHĀH}uHUHMLEdH%( HE1f)E)E)EfEH} t5HEHHEH > H衫t3 HEH UHTHEH} uv HEHUHPxHEH@xHMHUHHH} tHEH Hv HE@ HEH@xP H} tHEH Hv HEH@HuHEH@x@ $HEH@HUHRxHJ HH H} tHEH Hv HE@ HUHRxBH} tHEH Hv HE@ HUHRxB H} tHEH Hv HE@ HUHRxB HuMHUHEHj A I HHEHEH@x E芪HUdH+%( t萄UHH0H}HuHUdH%( HE1 HEHeq HEHȃHt HUHEHHjHUdH+%( tUHH}Hu HE t HEHmH} ݸ ]UHH H}HuHUHMH}w.HUHEHHHA< Hƿ THEH+EHHUHEHHHZt'HEHH< Hƿ T UHH}} y UډE UHHH}HuHEH@Ht'HEHPHEH@HHlHEH@ HEH@ Ht9HEHPHEH@(HHHHEH@ HH&HEH@ HEH~r UHH HhdHXHPdH%( HE1DžxX HEX HHxHMdHΉ|| tJs ؉||dщH: Hƿ |y Et0dH: Hƿ Ak Hh@ HcHhH@ HHHEH} u& HhHUHPHh@ HcHhH HHjHEH} u HhHUH8 HEH} ur HhHPHh@ HHHHEHHEdP0HEHXHHEHPHPEHEHP(HhH@dA Aй Hƿ gHEH}u= ؉||dщH>9 Hƿ HEHUHPHhH@UHHHEHhH@HdHEIAй Hƿ ĴHEH}u= ؉||dщH8 Hƿ = HEHUHP HhHPHEHHEHPHhHHh@ HcHHHHHHEHE HeHE HhP HEPHh@HMd by: ؉||dщH@8 Hƿ Z Hh@ PHhP #HUHhHH |HUdH+%( t} UHH H}H} E +HEH@UHcHHHHEHHEHE@ 9E|HE@xHE@tHEH HrmHEH@HbmHEHVm UHH0}HuHUHMH} t;HEHHEH 17 H3t HEH} uU HcHEHP ۑHUBHE@y, ؉EEH6 Hƿ { 'HMHUuHEHE} uHE HEH*Uډ UH}emEE] UHH H8H0dH%( HE1HDžh HE H8H@HEHEHEDžT Tt\TcTt<TQTt Tt=HEHELHEHEf<HEHE.HEHHEH THHMHUHHH`HEHxHxHpƅG HE H8H@ HEHEHEDžX Xt\XcXt<XQXt Xt=HEHELHEHEf<HEHE.HEHHEH XHHMHUHHH9_HEHEHEHE H8HPH8H@(H#pHHEE HEHEHEHEDž\ \t\\c\t<\Q\t \t=HEHEȈLHEHEf<HEHEȉ.HEHHEH \HHMHUHHHK^EHHLL A ƅGLHHpL% @ HEHHEH8L LHcH8H@HMHHAЉPP HpHEH8H@HEHEHEDž` `t\`c`t<`Q`t `t=HEHEЈLHEHEf<HE؋HEЉ.HEHHEH `HHMHUHHH\PH HhHpHEH8H@HEHEHEDžd dt\dcdt<dQdt dt=HEHENHEHEf>HEHE0HEHHEH dHHMHUHHH\ HhH;0s#HpH;EG HhHUdH+%( tv UHH0H}HuHE E bHEH@UHcHHH HEHUHEHHiHEH} y HE":HEHEHEH)EH} tEHE؋@ 9E|HEH9HO UHH0H}HE E fHEH@UHcHHH HEHEHHEH} y HE1HEHE H9E| HEEHE؋@ 9E|HE UHH@H}ȉuHE HEȋP HEH0HEȋ@Mĉ蛗E} y ؉ E qHEHEHcHHHHHȋ@EHEH@UHHH HEHEHHEH} y HE+HEHEEE;E| H9E|HEHE UHH}HE@] UHHH}uHE@ 9Er " HEH@UHHH UHH@H}dH%( HE1HE HEH@HEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHuXHEHEHEHUdH+%( tTs UHH@H}dH%( HE1HE HEH@ HEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHWHEHEHEHUdH+%( tqr UHH H}HEHôHEHEHCHEHEH+E UHH}HEH@(H] UHH}HE@0] UHH H}HuHUHEHHHEH} y HEHEH9HO UHHH}HEH UHHH}HEH@Ht'HEHP0HEH@HHHEH@ HEH@Ht9HEHP0HEH@(HHHHEH@HH褓HEH@ UHHH}H} t3HEHPHE@<xHE@<hHEH` UHH HxtdH%( HE1EX HEX HsHUHMtHΉE} t: ؉EUtщH* Hƿ )E E t+tH* Hƿ HxtP8EHxHP(HxH@0tA Aй Hƿ ޤHEH}u: ؉EUtщHK* Hƿ ]ED HxHUHPHxH@0UHHHEHxH@0HtHEIAй Hƿ ;HEH}u:[ ؉EUtщH) Hƿ E HxHUHPHxHP0HEHHxHP HxHEHE Hx@<HMt Qy7 ؉EUtщH) Hƿ E HUdH+%( tm UHH }HuH} t;HEHHEH t) Ht* @ kHEH} u HcHEHP0 聂HUB<HE@<y, ؉EEH( Hƿ !!UHEHJE} uHE HEHaUډ UHH}HuЉЈEHEHP(HEH@ HMH)HHHHEHEHP HEH@(H#EHHEHE %E} tM @HEU] UHHH}HuHMHE HHX UHHH}HuHMHE HH) UHH HxtdH%( HE1t?v= HE HxH@HEHEHEE }tM}W}t3}K}t}t=HEHE؈IHEHEf9HEЋHE؉+HEHHEHEHHMHUHHH PHEHEHEHEHE HxH@HEHEHEE }tM}W}t3}K}t}t=HEHEȈIHEHEf9HEHEȉ+HEHHEHEHHMHUHHHTOHEHEHEHEHxH@(EHEHE)EЉEtEE9Es + E;Ese HxHP HxH@(H#EHHEt HEHE@ UHEHHEHxH@HEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHMHxHP HEHHHxH@(H!HHUdH+%( th UHH}HuHE ʚ;HEH HEHHEH@HHEHEH HEHHEH@HHEHEH+E] UHH`H}uUdH%( HE1EE} y}t }t$HEHƿ mE} t HE@B UHEH[HEH} t HE + t HuHE@<UѺ ΉE} y m}tKHEHƿ lE} t FHUHEHH HuEE+EE} 5UHEH![HUdH+%( tfUHH}HE]UHH}HEH= H]UHH}H} HuHEH= Ht ]UHH}HE (HUHHH)HHE HHHEHEHE uHE] UHH H}HuHEHEHEHHEHHEHEH{ UHH@H}HuHUHEHEHEHHEHHEHEHHEHHEHUHEHH豩 UHH@H}HuHUȾ( SHEEH} uHjP HEHHJHHHu}HEHEHC HEHUHPHEHUHP H} HEH該HHEHHEH H HEH HUHMHHIHEHUHPHEHUHPHE \HUHuHEA A H迀E}t} uEHEHHEHHvoHUHHHEHEH@HUH9rHE HEH EHH UHHH}HEH%u-HEH@ H0}HEH HSHEHS UHH}HEH@] UHH}HEH ] UHHH}HuHEHHHEHPHEHpHEH}IIHѺ H肌 UHH@H}HudH%( HE1HEH8nHHEHUHEHHjHEH} uMHEH@HEHUHMHEHHGHEH@ HUHMHHtHEHUdH+%( tzb UHH@H}HudH%( HE1HEHymHHEHUHEHHHEH} u HEH@HEHUHMHEHHFHEH@ HMHUHuA Iȹ H ~Eԃ}uHE&} tEHEHPHEHHEHPHEHUdH+%( taUHH}HE@ ]UHH}HE@]UHH}HE@ ]UHHH}HEHfUHHH}HEHfUHHH}HEHgfUHHH}HEHFf UHHH}HEH%fUHHH}HEHfUHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH0H}HuHUdH%( HE1 HEHeq HEHȃHt HUHEHH?FHUdH+%( t_UHHH}HEH'UH}uUE E E]UHH}Hu HE t HEHmH} ݸ ]UHH H}HuHUHMH}w.HUHEHHH Hƿ THEH+EHHUHEHHHZt'HEHH Hƿ UHH}} y UډEUHH}H} tHEHH#EHu ] UHH H}H} K HEH HNHEH@HtHEH@HHE@xHE@,UHEH@0HHEH@HHFHEH@PHlE HEHH EHcHHHHHHEHEH HnMHEH@8H^MHEH@PHNMHEH@hH>MHEH H+MHEH HMEHE@(9EdHEH@ HLHEH@`HLHEHL UHH H}HuH} t;HEHHEH Hgt u8eHH Hƿ UĹ wh HEH} u蘹 KHE@HUHEHH E} uHE HEHawLUډ UHH0H}HuHEH@ HEHE؋@(tHE؋@(H HEHMHE躠 HHBHEH} u HE؋@(HHUH)HHHHHHE؋@(HcHHHHHHEHHʾ H]HEHUHP HEHE؉P(HEHH HUHHHHH- HHEHEHEPHEH;HHEHHEH Hu HE UHH0H}HuHEHH HEHP@HHHHHHEHE@0HHHHHHEHEHHHEH@8 HHHEH} u HUHHHHHHEHHEHE HY\HEHUHP8HE@0HEP0HEH@ HP HEH@ HHP HEH@(HPHEH@(HHPH} t HEHUHHE UHH0H}HuHEH :HHEHHEH Hu HEк A HǸ _HU؉BHE؋@y9X ؉EUHEЉHHV Hƿ E HE؋@ |HUHBHEH@Hu0mHH# Hƿ ]; HEH@H:HUHBHEH@Hu0HH Hƿ HEH@f@ HEH@f@ HEH@@ H HƿHUHB0HEH@0HiwHtHEH@0HTws HEH HHHEH} u H HEH@HDHUHBHEH@Hu0%HHC Hƿ HEH@H_HUHB HEH@ Hu HEH@HзHUHB(HEH@(Hu0补HH Hƿ o HEHHEH@0HHE} yED HEH@HPrHUHBHEHPHEH@fP>HEHPHEHP8HEH@ UHEH@ @ HEH@ H@ HEH@ H@ HEH@ @( HEH@ @, HEH@ H@0 HE@0 HEH@ H@ HEH@ H@8 HEH HHHEH} u H HEH@HDHUHBHEH@Hu0%HH Hƿ HEH@H_HUHB HEH@ Hu HEH@HеHUHB(HEH@(Hu0衣HHW Hƿ o HEH@(@ HEHHEH@0HHE} yE5 HEH@HApHUHBHEHPHEHP@HEH@ UHEH@ @ HEH@ H@ HEH@ H@ HEHP8HEH@ P(HEH@ @, HEH@ H@0 HEH@ H@8 8HUHBHHEH@HHNsE} tEdHEؾ HHEH} uAHE HE@ HE@ HEf@ HEH@ HEH@ UHH H}HuHxdH%( HE1HU HHE Hx t;HxHHxH Hat> HEH@Hu" EuHMHxHuHEHp EEuHUHEHH EEuHUHEHH EEuHUHEHHA EEuHUHEHHH EEuHUHEHHQ EHEHAHEH:HEHGHEH{AHEHoAHEHt HEHZEx EHEHUdH+%( t+Q UHHH}HE H HH^I UHH H}HEH@(HEHEH HEHE@u HE@=Lou HE@u4HEH@ Hu'HEH H HH耔u HEH H*t {HE H E HHHuWHEHEHt @HEH HHtHEH HHu UHH0H}HuHEH@8HEHE؋@@tHE؋@@H HEHMHE@ HHOHEH} u HE؋@@HHUH)HHE؋@@HHHHEHȾ HQHEHUHP8HEHE؉P@HEH@8HUHH@HHEHEHEPHEHUHHE UHH`H}HuHUHME E HEHH Hƿ HEHUHHE HǸ HUBHE@y9ͫ ؉EUHEHH Hƿ -E HE@ HUHBHEH@Hu:HHEHHHF Hƿ HEH@HҵHEH} u:荜HHEHHH! Hƿ s0 HE@9Et?E<HHEHHH Hƿ "E HE@fuHE@f= u HE@<t?E՛HHEHHH Hƿ Ez HEHPHEH@HH蜂t:~HHEHHH Hƿ d! HE HEHEhHEHEH蕄HEH} uAHHUHEIHHHu Hƿ HE HEHHHEH@HHHEH} uA衚HHUHEIHHH> Hƿ = HEȾ HIHEH} uHDHHuHUHEIIHHH Hƿ HUHEHH(HEH} u HEHUHP HEHUHP(HEHUHP0HEHfHUHBHEHt HE@ HE@ H H` HHT H>HEH@ Ht(EHk Hƿ 5E HEHUHP b HEH HH uvHEH@ HEH HrHUHB(HEH@(HiE} t-UHEHH Hƿ E` HE@ HEH HHz HEH@ HEH HgHUHB0HEH@0HhE} t-UHEHH Hƿ E HE@AHMHUHEIHHH Hƿ EE HEH@HUHHOHEH} GEu HEHJ EEu HEH EEu HEH EEu HEH< EE UHH H}HEH@ Hu-HEH HH Hƿ HEH@Hu-HEH HH Hƿ g E F HEH@8UHcHHHEHEH u8HEHHEH@HHH Hƿ R HEH H HEH@(H@0HtbHEH@(H@0HtGHEHHEH@(HP0HEH@IHHH Hƿ r HEH@(HP0HEH@0H@ H9tVHEH0HEH@0HH HEH@(HP0HEH@IIHHHk Hƿ U HEH@(HP HEH@0H@H9tVHEH0HEH@0HHHEH@(HP HEH@IIHHHH Hƿ HEH@(@ w4 H H HH H>=Lo HUHEHH' E} E HEH@(H@H HEH@(H@ H HEHHEH@(HP HEH@IHHH Hƿ HUHEHH_ E} tcExHEHHEH@(@HEHHEH@IIHHHz Hƿ |) EHE@@9E UHH@H}HuHEH@(H@8Ht HEH@(H@ HUHR(Hz8 HHHHt p HEH@(@(tHEH@(P(HEȋ@@9rEHEHHEH@(@(HEH@IHH Hƿ HEHP8HEH@(@(HHHEHEH@(@tEHEHHEH@(@(HEH@IHH Hƿ HEH@(H@ HUHR(Hr8 HEHEH@0H HEE B HE@EHE@EHE@E} uzHE uCHE@u7HE@u+HE@fu HEH@HuHEH@H HEH HH% Hƿ } tE}t?}t9HEHPMEAHщH Hƿ U } t?}t9HEHPMEAHщH Hƿ HE@fu\} u$} t HEH@HuHEH@H HEHEHщH Hƿ & HE@f=w^HE@HEȋ@@9|HHEH0HE@HEHPEIIHщH Hƿ ;}uHEH@Ht !EHEE;E UHH@H}HuHEH@(H@8Ht HEH@(H@ HUHR(Hz8 HHHHt HEH@(@(HEH@ H9tEHEHHEH@(@(HEH@IHH Hƿ C HEH@(@,tHEH@(P,HEȋ@@9rEHEHHEH@(@,HEH@IHH Hƿ O HEHP8HEH@(@,HHHEHEH H HH[7u!HEH HUHHHHt8HEHHEH@HHH Hƿ > HE@t ( HEH@(@tUHEH@(@tEHEHHEH@(@,HEH@IHH_ Hƿ 9 HEH@(H@ HUHR(Hz8 HEHEH@0H HEHEHP8HEH@ HHHEE Y HEH@H HEHEH@HEH}tYH} tRH}tKH}tDHEH0HEHPHMEIIHщH Hƿ a H} t%HUHHHHHHEH@(H@ H9rAHEH0HEHPHMEIIHщH Hƿ ~HEH@(H@HtPHEH HtAHEH0HEHPHMEIIHщH Hƿ EHEE;E UHSH(H}HuHEHEHE؋HEH`9r H] UHH H}HuHEHEHEHEHiBHEH} u UHHĀH}dH%( HE1HEH@(Hu HEH@(HZ`EE UHEH@(H wHEHMHE HHO E} t E HEE9r HEHR HEH} uHMHE HHTO E} t)EPHEHEH@(HMAHu,HEHqR HEH} uŃEE;E HUdH+%( t: UHH H}E HEH@0Hu |HEH@(HuhEu"HEHP(HEH@0H HHEEu"HEHP(HEH@0H HH%E} tE UHH@H}HuHUHE@0 HEH@ HEPHEЈP HE@t HEH@Hr{HEH} u l HEHaHEH} u K HEHqHEH} u * HEHUHPHEHUHP HEHUHP(HEHTHUHBHEHHEH@0HHQE} yE UHEHEH@(PHEPHEH@(HPHEHPHEH@ HE@( HE@, HEH@(HP0HEHP0HEH@(HP8HEHP8HEH@0PHEPHEH@ HEH HEH@0HP HEHP HEH@ UHH H}HuE GHEHH EHcHHHHHHEHEH HUHH{uHEEHE@(9E| UHHH}HuHE@ u HE@t HEH@ PHEH@(@9t-HEH HHg Hƿ HEH@ HPHEH@(H@H9t*HEH HH= Hƿ LHEH@ HP8HEH@(H@8H9t*HEH HH Hƿ UHHH}HuHE@0HcHEH@(H@ H9t 8HE@0HcHEH@0HHEH@8HHt UHHPH}HuHUHE@t HE@ t(HUHMHEHHEԃ} tE HEH@ H@0HEHEH@(H@0HEH} uHE HEH;EsHEHEHE@0HcHEHH HuHHEHHEHEH@(HP HEHHEHEH@(@ HEH@8HUHHdHEH} uH} t HEHUHP8HE@0HHUH)HEHH8HE@0HHȾ H+7HEH@(HP HEH@0H HMHq8HMHHHZHEHEP0HEH@ HUHP HEH@(HUHPHEH@ HUHP0HEH@(HUHP HEHEP UHH}H} t HE@t BHE@t /HEH@(@tHEH@(@u ] UHH}H} tHE@u HE@t HEH@(@ ] UHH0H}HuE HEH@8UHcHHHEHEH HEHHEHHHEH} uzHEHHEHHHEH} u y HUHMHEHHE} HEH HH1 Hƿ sE* HUHEHHt-HEH HH Hƿ . HEH H HHvt HEH H HHuu\HUHEHHet*HEH HH Hƿ 譾eHE@HEPHEP 4HEPHEP HUHMHEHHgE} tEEHEЋ@@9E UHH@H}HuHEHP8HEH@ HHHEHEH@0H HEHEH@(H@ HUHR(HJ8 HEHEH@(@(EE܃H HwHHEHPHHEH@HHu E } HE EHcHEH@HHsHEH} u/HEHEHщH Hƿ /G}HMHUHuHEAH E} tEEHEE;EY UHH}HuHEHH HEHP@HHHHHHEHEH@8HEHUHHHHHHEH] UHH0H}HuE eHEHH`EHcHHH)HHHEHEH@0HHURHcHHEHUHEHHsuHEEHE؋@X9E| UHH H}HE@XHcHEH@` HHHEH} u hHE@XHcHHH)HHHEHHEHE H0HE@HEHUHP`HE@XPHEPXHE UHATSHĀH}HUMLED|EHE HEHEMHUHEHHE|H|HEHHEE HEHHEH8 HEHEH3HEHEHEH3HEHUHEHHYqt8HMHUHEIHHH Hƿ # HEH HEHtHEHt HEHjtHEHnt HEHHHEH.t Hg Hd HUIHHZ Hƿ \ HEHtHEHt / HEHtHEHt HEHHHEHt H H HUIHH Hƿ 许 HEH HEHf9tNHEH|HHEHmHHEIHHH Hƿ A 9 HEH P HHЃH HEHEH\1HEHEHEHD1HEHUHEHHntMHEHHHuHMHEIIHHH Hƿ u m HEH H H HH H> $ HEPHE@9t^HEXHED`HEHHHMHEHSEIHHH Hƿ H E HE@EHE@|wHEH EHEH |MHEHEHEHEE:Et1HUHEHHH Hƿ HE@EHE@|HEH EHEHl EE:Et1HUHEHHH Hƿ 脵 | HE@EHE@|MEt K HEHHEHf9taHEHDHEHHEHHHEEAHHHI Hƿ Ӵ HEHGEHEH5HEHEH%HEE HEHEH-HEHEHEH-HEHUHEHHLkt=HuHMUHEIIȉHH Hƿ HEPHE@9t6HMUHEIȉHH Hƿ ɳ HED@HEHuH}HUHEEIHWt EHE HE E;E _ HEHHEHf9taHEHDHEHHEHHHEEAHHH- Hƿ HEH[EHEH[HEHEHKHEE IHED@HEȋHuH}HUHEEIH:t iEHEHEE;E|HE@EHE@|$HEH,HHEHHH Hƿ He[A\] UHH HXHPHHH@L8L0HEH(dH%( HE1HHPH0@9tH Hh HHP H0@ 9tHY Hh HH@H0@1ЄtH+ Hh HH tVH0xHHHH8HPHXAI HtH Hh) HHPH0@9tH Hh HH@H0@1ЄtHw Hh HH tVH0xHHHH8HPHXAI HtH Hha HHPH0@9tH Hh6 HHP H0@ 9tH Hh HHP H0@ 9tH Hh HHP$H0@$9tH Hh HHH0 1% tHh Hh HH % tlHXHpHH< HǸ 38H(H8H@HPHpHj IIȹ HH9 2HhHXHHH Hƿ Y HUdH+%( t4! UHH HHHH LDdH%( HE1f)0)@)Pf)`)p)Ef)E)E)Ef)E)E)EH H@(H H(H(H謿t5HHH Hƿ D H(HH H@( HH(H Hp(H}HMH(HIIȹ Hm$$ t-HHH Hƿ 詬 H@ HH@HHH(H(HHH@H H3H(HHpHH`H0H(HIIȹ H$$ t*HHH Hƿ DH L@(HHpHLMH`H0HHH}WHHHUdH+%( tu UHH@H}HuHUHMLELMHE؋@ t} u*HEHHh Hƿ * / UHEH@(H HEHEH1tLHEHt9HEHHHEHH( Hƿ 貪 HE؋@tdHEHH HE؋@HcHHHHHH H& HHiau(DEH}HMHUHuHEEIHHuHEHH(HE؋@ HEHPHHEAIȉ Ht UHHH}HEH tHEHq u HEHƻtHEHt UHH`H}HuHUHMLEE HEH@(Hu-HEH HH Hƿ 5H HEH@(H@EE UHEH@(H HEHEHtBHEHEH@(H?"HEHUHEHH_p EԉEi HEHQ HEH>HEE HEHE HEHEH@(HXHEHEHEH@(H!HEHUHEHH_ HEH3tHEH蛺 HEHtHEHto} tEHEE9t8HEUHEAȉHH Hƿ 肧 HEUԉHE HE wEHE E;EEE;E } tHE HEU܉ %HEHH> Hƿ UHH H}HuE =HEH@8UHcHHHEHEH HUHH]uHEEHE@@9E| UHH`H}uHUMUHEHTHEUHEHTHEHEHZt HEH¸ XHUBHEPHEHbTHEHEPHEHITHEHEHGHEHEH7HEE HEHE]HE؋ tDHE؋HEH HEHUHEHHEԃ} yE'UHEEHEHEE;E| UHH}uEHE@HEP] UHH}uHE@EHEP] UHH}uHE@HEPHE@E ЉHEP] UHH H}HuHUHMD|dH%( HE1HE HE HE E E HE@EHE@EHE@EHE@fE} t4HEH@(H H: Hƿ 褣 HE@f= HEHP8HE@HHHEHE@t ] HEHH HEȋ@ HcHHHHHHEЃ}u6HEЋ@@t+HEH@H|HcHHHEЋ@@ } U H}HMHUHuHEIH<E} tE } E HE EHEH@(HHEHEHEH@(HHEHEH HHQYtoHUHEHHUHEH} u*HEHH Hƿ HEHH HEȋ@ HcHHHHHHEHUHEHHFHEH} ) HEH@H|HcHHHE؋ Et`HE@tQHE@tB}t<HEHHU|IHщH= Hƿ 76 }|LcLEHMHUHuHEHWHHt HE؋ HcHEHHHE}uHE HHE@ HE@9E~UHEH} t HE@t}u f UHEHjHEH@HEfPHEȋ@HcHEH@HHEHPHEHPHEHPHEЋPHE؉PHE@ MHEHP(HE؋p HEH@HHat HE@ HEH@H|HcHHHE؋ HEH@0HUHHE} yEo HUHEHHʷHEH} u G UHEHEPHEPHEPHEPH} t HEH@HE@HUfBH} t HEȋ@H HUHRHHEHPHEHPHEHPHMHEH@H|HcHHЉʉ}u H} tHEHEЉP@HEH@ } ttHEHxHEH} u[HEHE؉H} t HEЋ@ HU؉BHE؋UPHE@ HEUP}HE؈P HUdH+%( t UHH HxHpHpHP8HpH@ HHHEE HpH@8UHcHHHEHEHu HpHP8HEH@(@,HHHEHE@E HEHHxHH HEH} u|HEHHxHH*HEH} u HUHMHxHHE} trHEH HHW Hƿ 虜E HUHEHHt-HEH HH Hƿ T{ HxHP@HEH@ P(HxHH HE@ HcHHHHHHEHEHPHEH@ P,HEPHEP HUHMHxHHE} tE HEH@0H HEHEHP8HE@HHHEHEH@(H@ HUHR(HJ8 HEE k HEH@H HEHEH@0HHUHHHHHHEHpH@HHUHHЋ HHEHEHHE@HHHEHHEH@HEHEH HHEHHEHPHE@ HpHP8HE@HHHEHEH@(H@Ht]HEHP8HEH HHEHE <u#HE@HE@HHЉHEP9HEPHE@HEP H Hƿ <EHEHEE;EEHp@@9E= UHHPH}HuUHMHEHP8HEH@ HHHEHEH@0H HEHEH@(H@ HUHR(HJ8 HEHEH@(@(EE HE@H9EucHE@9EuSHE EHcHEH@HHZOHEH} u >HUHEHHOu HE!EHEE;Ep UHH`H}HEH@(Hu D HEH@(HA0EE UHEH@(HFHEHEH輩f HE؋HEH@(HHEHUHEHH/HEH} t$HEH@(HtqHEH@(H@ HE؉PZHEH HHNd HUHEHHٺHEH} u R HE@HEH@ HEȋUP8HEH1HEE HEHE HEЋHEH@(HKHEHEH] HEHEH@(HxHEHEH袩 Eă}uoHEHpHUHEHѺ HHEH} u.HUHEHHH] Hƿ 藖GHEH@HEЉPEHE E;EEE;E UHH H(H dH%( HE1H H@(Hu ] H(H@HH-8H H@(H-<<H HOHH HPPH H@PHu Dž0 HDžX 0H H@(HnHEHEH车f HEHE HEH H@(HHPHPH(HHpHXHX ! HX@uHE@؉HXPHX@ t,H H@P0HcHHHX@ H HH(H(H@HHUHH[LL y9H H0HщH+ Hƿ Ln H H@P0HcHHLHX t+HXLP HE@؉HXP00;<!H(H@HHR+<80 0H(H@HHAHEHMHE HH DD D~ H HPPHE HHЋ HH u5HE t+HE H Hƿ ̒ H HPPHE HHЋ HEHEHB HEH} a00;<Dž0 H(HH`0HcHHH)HHHEHE@yZH HPPHE@HHHЋHEPHE@ H(H@HHq@HEHE@HEP0H(@X90TDž0 H H@80HcHHHpHp@8 Hp@ H(HH Hp@ HcHHHHHHxHx@DHp@8H H@(H HEHEH譣H`HEHd<Dž4 HxH@PHEH HPPH` HHЋ @HDžh @H(H@HH>HEHEHi HEH(H@HH HPHPH(HHHhHhPHx@9tFHxHHhPHPAȉHHH Hƿ 躏 Hh Hh@ HxHHPHh@HcHHHHHHEHh@H(H@HHGHEH} y5HEHPHH Hƿ _ HEHEP Hx@HHcHE HH蟡HEH} u HxHUHPPHx@HPHxPHHxHHPHx@HHcHHHHH HHEH HPPH` HHЋ HEH`PHEPHp@H`@HEPHh tHx@HPHhP4H` 4;<0H @@90 HUdH+%( t UHH H}HuHE@HEH HHHEH@HH%HEH} u VHEHUHPHEH HURHHEHE@HMHEHHHEH HPHEHHE UHHĀH}HuHEH@0Hu HEH@0@EHEH@0H@HE HEHEH@(HgHEHUHEHHHEH} u*HEHHG Hƿ A HEHH HEЋ@ HcHHHHHHEHE؋@`u UHE؉P`HE؋P`E9t*HEHH Hƿ ͋ E HEHHEyHEHPXHEHH HEH} u H HEHEЋ@HEHEHPPHE@HHЋ HEPEHEH@0@HEHE@U9uHEH@0PHE@HHEHEH@0HPHEH@0@HH9ECHEH@0@0EHEH@0H@(HE HEHEH@(HHEHUHEHHHEH} u*HEHHg Hƿ a HEHH HEЋ@ HcHHHHHHEHE؋@xu UHE؉PxHE؋PxE9t*HEHH3 Hƿ E HEHHE HEHPpHEHH&HEH} u e HEHEЋ@HEHEPHEH@(HHEHEH@HHUHH E} y UHEPHEPHEH@(HHEHEH@HHUHHE} y UHEPEHEH@0@0HEHE@U9HEH@0P0HE@HHEHEH@0HP(HEH@0@4HH9EHEH@0@PEHEH@0H@HHE HEHEH@(H%HEHUHEHHIHEH} u*HEHH Hƿ HEHH HEЋ@ HcHHHHHHEHE؋ u UHE؉ HE؋ E9t*HEHH Hƿ 肇> E HEHHE HEH HEHHHEH} u HEHEЋ@HEHEHPPHE@HHЋ HEPHEPHEH@(HT HEHEH@HHUHHyE} y{UHEPEHEH@0@PHEHE@U9$HEH@0PPHE@HHEHEH@0HPHHEH@0@THH9E UHH0H}HEH@Huv) HEHi E} tER HEH@0H HEHEH@0H HEHEHH HEHP8HHHHHHEHEH@(H@ HEH@(H@ HEH@(HUHHEH@(@ HEH@(HUHPHEH@ HUHP E bHEHH EHcHHHHHHEHEHPHEH@8H9t"HEH@HtHEH@(HUHR8HEHE؋@(9E|HEH@ HSHy<EFHH Hƿ Eژ HEH@ H?SHy9E9FHH Hƿ )E脘:HEH@HhHE؋@CHEH@ HE@ UHHPH}HuHUHMLEHEH@0HUHH&E} yE HEH@H}8HEH} u HEHlWHEH} u HEH.HEH} u UHEHE@ HEH@ HEHUHP HE@( HE@, HEHUHP0HEH@8 HE@ HEHUHPHEHUHHEHUHP HEH@ UHH HxdH%( HE1HE Hf)EfEHE HEHUHEHUHEHEHxH@HHEHxH@HHu E HxHH EHcHHHHHHEHE@D HE@0HEHHEHH`E} y0HEH UHHO Hƿ iE> E VHEHHPEHcHHHHHHEHEHHEPHE HEHHt EHE@H9E|EHx@(9EHxH E} t&EH Hƿ 覀E{ HxH@PHEHxH@HHUHH)E} t&EH Hƿ NE# HxH@HHUHHaHEH} u EHUHxIHѺ H5 H E} t&EH< Hƿ E HxH@PH HxH@PHUHHdPHEH} u[EHUHxIHѺ H5g HsE} t#EH Hƿ -E HUdH+%( t UHH@H}HuHUHMHEHEHEH Hu HEH@HHUHHpE} yiHEHEUHEHEH HEPHEHEH HURHHEHEHHHUHEHHGHEHEHEH+E UHH HxHE HE HE HE HE HE HE E HxHH EHcHHHHHHEHEH@XHtuH} u HE@`HEHE@`H9Et3HEP`HEHHN Hƿ h} HEH@XHEHHEHHHEHEH@pHtuH} u HE@xHEHE@xH9Et3HEPxHEHH Hƿ |0 HEH@pHEHHEHHHEHEH H H} uHE HEHE H9Et6HE HEHH Hƿ T| HEH HEHHEHHHEEHx@(9E*H} uH} uH} u F HE H} t HEHEHEH} t HEHEHEH} t HEHEHEHEHƿ t5HEHEHEH} u HEHEHEf HE@HE@ HE@ HE HE@ HEHE؉P HEHE؉PHEHE؉PHEHEHE؉PHEHE؉P H} HEHEȉHEE iHxHH EHcHHHHHHEHEHHXHEHHuHxHE} y EE EHHEȃEHx@(9E|H} HEHEȉHEE iHxHH EHcHHHHHHEHEHHpHEHHuHxHE} y EE' EHHEȃEHx@(9E|H} HEHEȉHEE lHxHH EHcHHHHHHEHEH HEHHuHxHIE} y EE EHHEȃEHx@(9E|HEHEЉH&`HxHBPHxH@PH E} t/HxH@P EHT Hƿ xHEHEUHH0H}HuHUdH%( HE1 HEHeq HEHȃHt HUHEHHHUdH+%( t'UHH}HuHUH} t[HmHE HUHEHHMHUH HEHEH;EsHUHEH uHUHEH ] UHH}uHE E] UHH H}uHEHP HEH@H)HUHE@<t HE@< ExUHEH¸ H9rHE@<zUHEHHEH@HHHEH} u.HE@<HEH@HHEH@ $HEHUHPHUHEHHEHP UHH H}uHEHPHEH@H)HUHE@<t HE@< ExUHEH¸ H9rHE@<zUHEHHEH@HHHEH} u.HE@<HEH@HHEH@ $HEHUHPHUHEHHEHP UHHH}HuHE Hu%HEH@ HUHHEH@ HPHEHP UHH H}HuHUHUHEHHHUHEHHq UHAWAVAUATSHxH}uUMHE HE H HU HEUP8HxHH H!ȉHHEHHp̠HH H!ȉHHEHHhHH H!HHE؉H H HHEHiH`HH H!HHEH H HHEH&ALILIH L!IDIHELHALILIH L!IDH q H IHELHEHHHHEALILIHEH HE@8t UȃHH L!H IDIHELHHEHP HEH@H)HEHP(E HEa̠HNjEHE)ʉHH H!H ЉHHuHEHHEՀHH H!H HHuHEHiHEHH H!H H HHuHEH+EEHH;E%E %UHEHHEH_ EE;E|ALILpIH L!IDIHELHHHHHH H!HÉHHEHHmHx[A\A]A^A_] UHH@H}HuЉUdH%( HE1ẼEHE UHE؉H(t HEH@HEH} tEUHEH@HMHHE+ẺHEHPEH HEHHHeUHEH@ HHEHPEHHEHPHEH@HUH)HUdH+%( t UHHH}HE@4@u0@ H Hƿ oHE@< HE@4HHUJ4 UHH H}HE苀 = u1HE HdEHE苀 U)HcHHE苀 HHU艊 @ UH}}t }w6}t}w*}t }t ] UHAUATSHH}؉uԉUб HHрHHH H!HыUH H HѰ`H H!ЉH}HHA LILIH L!IŋEH DH IALIL`IH L!IDIHELLH{HHHHH H!HÉHHEHH H[A\A]] UHAVAUATSH H}؉uԉUЉMA LILIH L!IЋUH DH Iа`H H!ЉHMLHHEЉaALIL IH L!IDIHELH/A LILIH L!IŋEH DH IALIL`IH L!IDIHELLHEЉ#cHHHHH H!HÉHHEHHlH [A\A]A^] UHATSH H}uUMA LILIH L!IЋUH DH Iа`H H!ЉHMLHH/EJaALILIH L!IDIHELHEcHHHHËEHH H!H HÉHHEHH9H [A\] UHAWAVAUATSH(H}ȉuĉUMDEEsaALIL`INjEHH L!H IDIHELH} t@ALILIH L!H IDIHELHgA LILIH L!IŋEH DH IALIL`IH L!IDIHELLH@E[cHHHHH H!HÉHHEHHH([A\A]A^A_] UHAVAUATSH H}؉uԉUЉM̋EЉaALIL̠IƋEHH L!H IDIHELHA LILIH L!IŋEH DH IALIL`IH L!IDIHELLHEЉcHHHHH H!HÉHHEHHWH [A\A]A^] UHATSH H}uUM܋EaALIL̠IċEHH L!H IDIHELHE?cHHHHËEHH H!H HÉHHEHH{H [A\] UHAWAVAUATSH(H}ȉuĉUMH H!ЋUH H HUHH A LILIH L!INjEH DH IALIL`IH L!IDIHELLHALILIH L!IŋEH DH IHELH]ALILIH L!IDH H IHELHHHHHH H!HÉHHEHHH([A\A]A^A_] UHH}HEHH9E] UHATSH H}HEHH(HEHP HEH@H)HH)HPHHHHHHEHEHtMALILIHEHH L!H IDIHELH>HE@<HHHHø H HÉHHEHHH [A\] UHAWAVAUATSHX HHLdH%( HE1H@8 HHH Hi : x1 y(HHHHH r=%f@d HHHHHHbH HH H!HH H HAILIIL`IH L!IDIHLHALILIH L!IƋH DH IHLH xVALIŋH LH IH L!IDIHLH xVALIċH LH IH L!IDIHLH/HHHHH H!HÉH H HHHHHEdH+%( tHX [A\A]A^A_] UHH H($ HLpLxt )E)M)U)])e)m)u)}dH%( HH1Dž0 Dž40 HEH8HPH@H0H $H(IH:HHdH+%( t UHH H(H H`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1Dž0 Dž40 HEH8HPH@H0H H(IHѺ HWHHdH+%( t UHATSHH}ՀHUR8t HH H!H ЉHUHHAL ILIH L!IDIHELH^HHHHH H!HÉH H HHEHHHEH HѺ HǸ 6H[A\] UHHH}ua̠UHH H!H ЉHUHHHEH UHSHH}u H H!ʋMH H ʰ`H H!ȉHMHHaHHHHH H!HÉHHEHHHEHH] UHATSH H}؉uԉUHE؋@0U9rHE؋P4E9tNHE؋p4HE؋P0MЋEAAȉщH8 Hƿ :]HE@<HE؋@< HEؾxHeE LEHHf?HE؋@4H EHHHHE؉Ѻ HEHE؋@0U9rE 5UHE؉HEHE؉Ѻ HTEHE؋@4U9rALILIH L!IDIHELHfHHHHH H!HÉHHEHH.HE؋@<H Hƿ [HE؋@<u_HEH HEHEHPHEHPHEHP HEH@H)HEP HEHPHEHPHEHPHEH@H)HEPHE؋@<H [A\] UHHH}H} t.HEH@H"HEH@HHEH UHSH H8H0,dH%( HE1DžD DHcHP HG,Hء Hƿ Z,H0H8HHSH,`DHPH8HH"LLH8A H LH8A HLH8A HHLH8HDLH8 HM,H8H HHǸ H8HcH HHpHH H!Hڸ xH HÉHH8HH?HEdH+%( tH] UHAVAUATSH H($H DDHEHdH%( HE1Dž4H ƅ3 4HcH@ H$@ DHH@ PHH@ HEH t"HH@HJ HHH@(XH@,lLH@ tH@xx$EH@H AAȉH Hƿ kW4H@H(HH,8xt$80H(x H@ w-8H(| Hƅ3} x2E 8 H(A Ѻ H48H( HPxD$UH@Hp H(HQEAHH5 HǸ HH(H} ySAcL ILpIH LH!¸ |H IDIH(LH H(P4E9tH(@< H(H<A LILIH L!Iŋ<H(HH DH IALIL`IH L!IDIH(LLHcHHHpHH H!HÉHH(HH3 tH(|HHEdH+%( tHe[A\A]A^] UHH@H}HuЉUdH%( HE1HUHMEHΉbUHE؉ HEHUHz\HUIHH H¾ pEEv HE@<HEdH+%( t UHAWAVAUATSH8H}HEH\HEHE HUH\H Hƿ SUHEHH\HEHHIEHE HH H!HNjEH H HHMHȀ`HH H!ȉHHEHALILIH L!INjEH DH IHELHALILIH L!IHE H DH IHELHALILIH L!IDIHELHkALILIH L!IDH H IHELH$HHHHH H!HÉHHEHHHE HEHp\HEHH5 HǸ HEH H8[A\A]A^A_] UHH0H}HuDDMЈU܈E؉ȈEHE@HHcHEH@@ HHjHEH} u HE@<xHEHUHP@HE@HHcHHHHHEHEHUHHEU܈PHEU؈PHEUԈPHEUЉPHEUP HE@HPHEPH UHH H}HuE }HEH UHcHHHEHEP HE@9uKHEPHE@8u7HEHHEH HHuHE@PHEPHE EHE苀 U9nHE苀 HEH HHHEH} uHE@< HEHUH HEH HE苀 HHU艊 HHHEHEHHEHHEPHEP HE@ HE@ HE@ HEPHEPHE UHAWAVAUATSH8H}HuHEH HEȋUHEHHEHHEHE HH H!HNjEH H HHMHȀ`HH H!HHEHALILIH L!INjEH DH IHELH=ALILIH L!IHE@H DH IHELHALILIH L!IDIHELHALILIH L!IDH H IHELHlHHHHH H!HÉHHEHH1HEHHEHHEH5 HǸ -H8[A\A]A^A_] UHAWAVAUATSHXH}HuHEH HEċUHEHHEHHSEHE H:EHE HH H!HEH H HHMHȀ`HH H!HHEHHEHH H!HNjEH H HHEHHEHH H!ȉHHEHHE HH H!HEH H HAILIIL`IH L!IDIHELHALIL@IH L!IDIHELH ALILIH L!IDH H IHELHAyL ILpIH L!IDIHELHHHHHH H!HÉHHEHHKHEHHEHHEH5 HǸ GHX[A\A]A^A_] UHAWAVAUATSH H}HuUHUHEHH HEH} HEȋ@~SHEȋ@EHEѺ HHEȋ@EHEѺ Hv HUȋEBHUHEHH HE@t HEHHEH5Eā} ~8HEHEHщH Hƿ HHE@< HUȋEĉBuHHHHH H!H HÉHHEHHAbLILIH L!H IDIHELH[AjLILIH L!H IDIHELHALILIH L!H IDIHELHAcLILpIH L!H IDIHELHHE pHH H!ȉHHEH_HEw HH H!؉H H HHEH"HE HH H!HËUHEHH H HHMHȀ`HH H!ȉHHEHHEc̐HH H!؉HHEHHxU HH H!H HHEHHHpjHH H!H HHEHHhHH H!H HHEHH`jHH H!H HEH H HHEHHE@8 HXàHH H!H HHEHHHPi ̀HH H!H HHEH HEȋHHEHHEAIHT HѺ HǸ H@ HH H!HHEȋPHEHH H HHHH`HH H!ȉHHEHH8a HH H!؉HHEH%HEȋHHEHHEAIH HѺ HǸ .HĨ [A\A]A^A_] UHATSH H}HuUHUR8` àH H!H HUHHyAiL IL̀IH L!H IDIHELH3HEHHE@HE@HEMQRAAH HѺ HǸ (HqH HH̀HH H!H HÉHHEHHHEHHE@HE@HEMQRAAHR HѺ HǸ HHe[A\] UHAVAUATSH0H}HuUHUHEHHQHEH} HE؋@~SHE؋@EHEȉѺ HHE؋@ E HEȉѺ HU HE؋UPHE@HUHEHHALILIH L!H IDH H IHELH-HEHsAcLIL̐IH L!H IDIHELHAwL ILIH L!IDH H IHELHcHHH̐HH H!H HÉHHEHHMHE؋PHMHEHH_H0[A\A]A^] UH ] UHAWAVAUATSHhH}HuUHUHEHH"HEH} HEȋ@ HEȋ@ E HEѺ HHEȋ@EHEѺ HtHpUHH H!H HHEH> HEȋUPHUHEHHHE@t HEHSHEuHH H!H HHEHHEbHH H!H HHEHHEbHH H!H HHEH_HEHH H!H HHEH,HEcpHH H!H HHEHHxwHH H!ȉH H HHEHAcLILpIH L!H IDIHELHmALILIH L!H IDIHELH-EAqL IL̀IH L!H IDIHELHATL ILIH L!IċEĉH DH IHELHsHHH̐HH H!H HÉHHEHHRHEȋPHMHEHHdHh[A\A]A^A_] UHH H}HuHE@XHcHEH@P HHHEH} u HE@<DHEHUHPPHE@XHHHEHEHPH HMHHQHE@XPHEPX UHATSH0H}HuЉUHE@t Hp Hl HUЋr HUH HUЋRIAHV Hƿ :HEЋ@ EЉEA LILIH L!IċEH DH IijHHH`HH H!HÉHHELHHHE@t<HE@tUHMHEHH*.UHMHEHH?UHMHEHH&H0[A\] UHH H}uE 4HEHH@EHcHHHHHUHEHHVEHE@H9E| UHHH}HE@Xt)HEH@PH]HE@X HEH@P UHH H}uE HEH UHcHHHEHE@t5HE@t&HE@EE EUHEHYHE@tJHEPHEHHEHKHE@=? HE苀 PHE艐 EHE苀 U91HE苀 t0HEH H2HEǀ HEHǀ HE@Ht'HEH@@HHE@H HEH@@ HEHO UHAWAVAUATSH HHHLLHEHdH%( HE1Dž HcH0 HMHAHщHˀ Hƿ -7HHBPHHHHH HHHH 0H@ tH@ EH@pDžX H4H@\H@D|H@@EU|HHH8HHH H@TEH@PEUEHHHHHHH$E H@XEUEHHHPHHH(HH0HJ0 HHJH0HHH<,,HH;, HH,P HH,`$HH,耉(HHH ,xHH,HA Hg, HA H=, HA H,HHx HH d HHH HH H!HNj,H H HAILIIL`IH L!IDIHLHϽAcLILpIH L!H l IDIHLH8AwLILIH L!IDH H IHLHAcLILpIH L!H p IDIHLH襼 HH],H H4H0Hp0HHH5{ HǸ _ HHH t-,pHHjHǀ HH+cH HHpHH@0Hf?HH H!H HÉHHHHwH@0PHP0HEdH+%( tH [A\A]A^A_] UHAWAVAUATSH HH dH%( HE1Dž Dž HcH0 H H_z Hƿ i0 HHHH*$H H HH(Hy`HHHHH H!H ЉHHH HHH H!H HHHϹH HH H!HNj$H H HHHȀ`HH H!ȉHHH谹HHH H!HNj H H HHHAaLIL`IH L!H IDIHLHѸAELILIH L!H IDH H IHLH聸ALILIH L!IDH H IHLH7ALILIH L!H IDIHLHHHHHH H!HÉH q H HHHH謷 H0HHH0,HHw,HѺ HR,(HH,$HHؽ ,H H} HH5v HǸ HH HEdH+%( tZH [A\A]A^A_] UHH HHD@<dH%( HE1DžT THcH` H芡@<DAȉщH v Hƿ +H@HH HH膺XTH`HHHHa\DHHH訳\HHѺ H能\XHHH+<HHHQ\HHHT\HH H@<DHHAH5 u HǸ HHH HEdH+%( to UHH HHDdH%( HE1DžX XHcH` H軟DHt Hƿ *XH`HHHHǸ\DHHH\HHѺ HX\HH HXHHHCt HHǸ HHHHEdH+%( t>UHH}HE@ ]UHH}HE@]UHH}HE@ ]UHHH}HEHfUHHH}HEHfUHHH}HEHgfUHHH}HEHFfEf}tf}u UHHH}HEH fUHHH}HEHfUHHH}HEHuHEHt UHSHH}HuHEHHEHyf9t HEHtHEHwt H]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEH ]UHH}HEHEHEH H HHEH H ]UHH}HEH ]UHH H}uHEHHUHHHHHHEHEHyE} tHE@% HE@UHH H}uHEHrHUHHHHHHEHEHE} t HE@ UHH}HEH ]UHH}H} t HE u ]UHH}HE <] UHSH8H}HuHUHEH@Ht HEȋ@t 6HEЋHE؉H HEHEЋXHEH59H] UH}} EH Hp HHp H>Ho sHo jHo aHo XHo OHo FHo =Ho 4Ho +Ho "H p Hp Hp H p ] UH}}w ] UH}} w}s } u ] UH}E w ] UHATSHPH}uHUMDEE UHEHHEUHEHnHEHUHEHHu m} y MHUHEHlfHEMHUHEHSfHEH} tH} u : HUHEHHXt HEH H Hn HHn H> HEHuuHEHeu HE@EHE@EHEH? EHEH. EHEHRHEHEHBHEHEH fEHEH fEEf;Et E } HEЋHHUHEHdHE؋HHUHEHdExMuHUHEAHẼ} E EHEHEE9EsHEHHUHEHTdHEHHUHEH;dDe]HEHFfEHHl Hƿ "! HP[A\] UHHĀH}HuHUHMdH%( HE1HEPHEHuHEHEHu HE <:u HE H)HEHUHHEPHE HEP HE HE@ HEHl HH@t HE <:uHEHMHUHEH5?l HǸ xt A HE @u ( EHHEHE HHU MHUHH LHE fHE u HEHHUHEH9bHEH} u HE EHEHHEЋUHEЉEHEЉPHE PHE HE@ HEHu%HE HEHЋE9 HEH0t HEHGUHcHHЋ 'HEH<HEHcHHHHHȋ EUHEH#sHUHB HE@ t j UHEH~HEH} y HEE HE؉E HE E MHUHEH`HEH} u HEUHcH DEHE HHHHEHHHEHEH HEH ЋE9 EHEȉH;EHE EHE HEHHEHcHHHHHHEHE tjHEHEHqHEHEHt UHEЉEHEЉPHEHUHPHE PHE HE@E HEHz# HEHHEHEHUHEH^HEH} u X HEHHHUHEHHEEtHE@U9r HE EHUHcHHHMHE HEHcHHH HE PHE UHEHU{HEH} y HE HE HU؉ыUHE VHEH `HuHEPDEH}HEQVEIHH!g Hƿ H EHE 9E HUdH+%( t脍 UHHPH}ȉuHUMMHUHEȉH?]HEЋMHUHEH&]HEH} tH} u ~ HEHxtHEHht T HUHEHHt 0 HEH H HSf HHGf H> HEЋHEȉHgnHEHE؋HEHOnHEHEHHEHEHHEH} t,H} t%HEH;Eu"HUHMHEHHlu a ZHEHuHEH}u 3 ,HEHv EHEHe E= UHHĀH}HuHUMLELMMHUHEHR[HEH} u HEHt j HE EUHEHHEHEH*HHE@HHHHHHEHEHEHlHEHEHEHEHHEE UHEЉHEHE @u HE EHE HE HHU HUHH EDHEȋHEHlHEHEHt>HEȋHLEH}HUHuHEMIHDEă} E HUHEHH HE HHU HHHHEHHHEUHEUHEPHEHUHPHEȋPHEHEȋHHEpHUHEHEă} uHE PHE EJHE +EHE HE PHE EHE E;E+ UHHpH}HuUHMHE H7HEHUHUHE HE HE HE tYHE u%MHE HEH HUH@ MHE HEH HUHd HEHHEHEHHEHE MHEH HUHWHEHEHt HEH@HHEE . HEHt HEH UHcHHЋ E*HEHHEHcHHHHHȋ EHEH UHhHEHEH<HEHEH;E HEH@HUHMHH(u{UHEЉUHEЉPHEHUHPHE PHE HEЋHHE HEHcH LHE PHE h EHEH9E A HE t E MHEH HUHUHEH} u HEH@Ht=MHEH LEH}HUHuMIHEă} ~ E } HEHt u HEHHEHEHHHUHEHHoEEt HEȋPHE@9r HEHUHEHTHu HE @u UHEЉHEȋPHEЉPHEH@ HE PHE HEЋHHE HEHcH LHE PHE UHEHMqE} yEMHE HEȋPEHE EHEHEHE 9E UHH H}HuHUHMLELMHEHxdH%( HE1HE HE@ u H} HEH O H} u > HE HHHHEHHHEHEЋHEH H躾HEHEH@H HE@ u_HE HEHHEЋHEH HoHEH} y HEHEHEЋHE HE@ u9HEЋHEH HoHEH} y K HUHEHAHE HEP HEAȉHH7\ Hƿ 1 Hx t Hx HEHHHEЋ@HHHHHHEHEHHEH HUHQHEHE EHEЋPHE؉H"Eȃ} E} HE@EċE uĉEEc}vAHE HEP HEAȉHHx[ Hƿ " eċE uĉEEŰEȍ E )ЋU9xIUHEH HmHEH} y HEEHE EEEHx tEHxHE@ H HZ HHZ H>UHEHE HEUĉUHE UHEH HEHt HE@x&HEHt HEH7t HcHEHHx taHx UE ŰE)ʍB@HEH5@ +EȉHEHHx tHx HUdH+%( t UHH0H}HuHUHMH} tHE H} uHEH HE@ tB tA wvtt%jHE HEHH} tWHE NHEH BHE HEH H\kHEH} yHUHEH UHH0H}HuHUHE@ t t H} HEH H} u HEPHEH HJHEHEHAt+HEHXHUR HHЋ@HcHEH@HEH?HHE@ HHHHHH-HUH UHATSHPH}HuUHMLELMEܡHEH HEH@ HE@ HE@HE@ HE@ HEP HEPHE@ HEP HEPHE@ W HEHxHELHHEL@HMHUHuHEHWHqHE܋E܅u<HEL@ HEHx HEHHHUHuHEHj MIH+HE܃} x HE@ HEPHE@ 9d HEPHEH H^HEHEP HEH HBHEHEHtHEH HEHwt4HEHgt$HEH<tHEH< HE@ HE@ tHHEHHHUHuHEHE܋E܅u HEHPHuHE HE]HE@ tJHUHMHEHHE܋E܅uHEHPHMHEHHiE }܋uHE@E ^}ܡuXHE HED` HE@ HUHEHSEIȉHHT Hƿ HEHe[A\] UHH H}uUHMMUHEAȉHHT Hƿ HE HEPPHEPPHEf@ HE@# UHH}HE t1t%'tt ] UH}}t }w6}t}w*}t }t ] UHH`H}HuUHMDELMHE EHE@tNHEHt HEHHEPuHEHgHMUuHEHQ HEH HEHEH@HEE߃t8 t* HE t P HE@tXHE@HH9EtIHEpMUHEuuAAȉHHR Hƿ H HE@HHEHEHEPHuMUHEHuIAȉHHR Hƿ H HE@t_HE@HH9EtMHE@MUHEuuAAȉHHR Hƿ H% H} v<HuMUHEIAȉHHR Hƿ p HE@t0MUHEAȉHHR Hƿ /HE@HHEHEHEfPHuMUHEHuIAȉHH)S Hƿ HHEP HE@9, HEH*EHEPE9tKHEH}uUHEHQAAHHS Hƿ _H HE@ E} y?HEp MUHEAAȉHHS Hƿ t HE E HE ЉHEHEH HExuUHEHQAAHHR Hƿ H HEHubHE@uSHE@fuFHEH u7HEH@u$HEH@uHEH@ft5MUHEAȉHHR Hƿ [ HE@HEH@HH H HEHE@tPHEH;EtFHuMUHEuuIAȉHHYR Hƿ s H HEHEPHEH HHEHPHuMUHEHuIAȉHHOR Hƿ HwHED@HE@HE@HE@HE DDUUHEAPWVQEЉHH.R Hƿ H UHATSHĀH}HuHxE Hx EHxH UHǭHEHEHxH HSHEHEHuH]H Q HEHCIHx HMHuHEHSMAHHQ HǸ HEEEEHH;ErHEEEHHEEHH)EHx tE Hx HxH M H@HEHEH HEHHx HcHHHEHEHxH HRHEHE@y HP HP HEHExHMHUHuHEAHǸ ߆EEEEHH;ErHEEEHHEEHH)E HEH HHx HcHHHHHHEHEЋHxH HQHEHE@y HP HP HEHEHHHMHUHuHEIHǸ EEEEHH;ErHEEEHHEEHH)EE3 Hx E HxUHcHHHH HtlHxUHcHHHHHuHEHHAO HǸ WEEEEHH;ErHEEEHHEEHH)E } HxUHcHHH teHxUHcHHH HuHEHN HǸ ɄEEEEHH;ErHEEEHHEEHH)EEHx 9EHMHEHYN HHǸ cEEEEHH;ErHEEEHHEEHH)EE HxUHcH T} u HM HM HuH}AHHM H¸ ڃEEEEHH;ErHEEEHHEEHH)EEHx 9EiHx ttHx Hx HuHEAȉH8M HǸ :EEEEHH;ErHEEEHHEEHH)E]Hx HuHEHL HǸ ۂEEEEHH;ErHEEEHHEEHH)EEEHe[A\] UHATSH HhH`\HPLHL@HEH8dH%( HE1H@HH@H HH@H@ HH`@xxHPHHHHPHJMHH u HH`HPHhH|| H`PHPHLHHHuH SK HHu LL%J HH<HƋx\HhH|QSATIAHHJ Hƿ eH HH HH\HhIȉHHJ Hƿ H`@ ulH8( HslH8@ H8@ H H8HH H8HP HHstYH`X H`@ H\HhAIȉHH(J Hƿ *_ Džp Džt HHH pHcHHЋPHHH pHcHHH0HHH|| ysHH HHp\HhH|QIAHHI Hƿ DH|t HH H| u HI HI p\HhHHVAIHyI Hƿ H| 7 LHH\H`HhMIHE|| t | t uaH8HHHHXHHHHHXHHP HHHƸ HHH/ H H 9tUH H \HhAAȉHH|H Hƿ H8@8uHH8H@H9 H8HxH8@t HMH HLH Lt H+H H*H \HhWPMIHHH Hƿ H HHH pHcHH4HHHtPtHHHHHVHHQpHH@9pVt ~HHtPt uu\HhHHG Hƿ H8H\H`HhIA H|| t| HUdH+%( tdHe[A\] UHH@H}HuHUHMHEЉHE؉HXFHEHEHEȉH@FHEHEHBtHEH2THEHiHEHEHYHEHEH;Eu"HUHMHEHHM\u UHH@H}HuHUHMHEHfEHEH{fEHEЋPHE@9t 4 Ef9Es E E HEHt HEHUHcHHЋ 'HEHHEHcHHHHHȋ EE {HEHt HEHUHcHHЋ 'HEHHEHcHHHHHȋ EMuHUHEHtEEE9ExEt EE9E UHH`H}HuHUHMDDMEHEH8HEHEHfEHEHfEEf9Es E HEHHEE E zHE HE HUHEHuIED@}HEHHEpHUHEEAH` E} yEP} ~EEHE E9EyE߃t EHE E9E4 UHATSHpH}uHUMDDMEE } ~ w m} y c MHUHEH0HEЋMHUHEHj0HEH} tH} u HE؋ HEЋ HUHEHt HEHfEHEHfEE H HB HHB H>Ef;E HEЋ@ Ee} tXEf;EuUHE؋@ 9I f}u Eu f}u} t Ef;Et UHE؋@ 9 HEHt HMHUHuHEH# } tRHE؋@ EeEf;Eu f}t q f}E9U Ef;Et A }DEHMHUHuHEEAH Ef;Et HEHEHEHEHEЋPHE؋@9uE:Eu Ef;Et EHEЋ@EHE؋@EHEHqHEHEHaHEEf;Et J HEPHE@9t . HE EHE EHEHDHEHEH4HEHEHfEHEHfEEf;Et Ef;Et E KED@}HEȋHHEpHUHEEAHE} EiEHEHEE9E|HEЋ@EHE؋@EDe]HEH~.EHH5 Hƿ Z Hp[A\]UHH}HE]UHH}HE]UHH}HEH= H]UHH}H} HuHEH= Ht ]UHH0H}HuHUdH%( HE1 HEHeq HEHȃHt HUHEHHAHUdH+%( tO[UHH}HuHUH} t[HmHE HUHEHHMHUH HEHEH;EsHUHEH uHUHEH ]UHH}HUډ UHH}HE (HUHHH)HHE HHHEHEHE uHE] UHH0H}HEHd= HHkHEHEH[= HHkHEH} tH} u*HV= Hƿ H 0 ĠHEH} uHuHEHUHHEHUHPHEؾ HjHUB(H Hƿ `HEP)HEؾ H(HUB*HE UHHH}HEH4u HEH@H$IHEHI UHHpH}HudH%( HE1HEH4gt8HEH#gHEHHc< Hƿ HEH[ptu,THEHHY< Hƿ { HEHHw< Hƿ Q HUHEHH(Hu Eft:Eft0EHEHH>< Hƿ ?E E9Et'HEHHd< Hƿ HUdH+%( tW UHH@H}HuHUHMdH%( HE1HE HUHEHHJt HUHEHH虆 H,Hux HUHEHHWHuvHEȋ HMHEHH#HEH} t)HUHEHH赚uHEHUH 'HUHEHH\HEH} pHUdH+%( tTV UHH}HuHEHEHEHEHEHHEH H9} ] UHHĀH}HuHUHMdH%( HE1HEH HUHEHH8t? ؉EE E = HUMHEHHu ؉EE EĉNjEHEHHEIHEIHUEHWVQHщH : Hƿ 7H E HEH HHHEH HH3HEH} u HEHUHHEHHEH HHHEHEH HPHEHHEHHEHHUHEHHHEHPHEHHEHPEăHUBEEHcHEH9HEH Hu'HEHH9 Hƿ 4*HEH0HEH HHѺ H܈ HUdH+%( tS UHH H $ H H $ HĀHHHdH%( HE1HH HHHH58 HǸ l9u9tnHHHHtHuS覰 ؉HHH8 Hƿ HH HHHH 8 HHǸ òHH8 HHzHH ؉HHAHHHR8 Hƿ L Dž <HHHHH uʋHHHHHHߕ> HHHHHHQIIHHH7 Hƿ H<x HH HHHH HHyHH uDžv HHHHHHH HHHHH HPHHHHHHHHHHPHHHHPH@LHHHHHHVMIH56 HǸ ?HHH HuBHHAHHH6 Hƿ Dž5HH0HH HqHѺ H蓄Dž HH:]HUdH+%( tO UHH}HuHUE HEHE*HEH H9E|HEH@H9E}HEEHE EHH;Er˸ ] UHH}HuHUE HEHEAHEH@H9E|*HEHPHEHHHEH H)H H9E}HEEHE EHH;Er ] UHSH H8H0H($LLHEHHE H dH%( HE1HDžX HDž` HDž HDžh HDžp HDž HDž HH H H HxH`H0H54 H:DD t8H(HH4 HH4 Hƿ D] duHUH0HHRHu7H(HH@4 HH4 Hƿ , HXHhH(H0HDD t0DH(HHR4 Hƿ a HH H0H5b4 HuH0HHx HYHHDž HDž HDž LPLHHHHH(H0HHWHz HDD HHHHۏ HHHH躏 HHH t$HHtHHH)HHXHhHHHHH uPDžDHH(HHIIHHH2 Hƿ H@tgDžDHHHHHHH(IIHHH2 Hƿ H HH HH)HH@HHEfg H8@(Q $ y(H2 Hƿ DžD H`HujH`HpH($DD t9DH($AHщH2 Hƿ & H`HpHHH;HH uPDžDHH(HHIIHHHn2 Hƿ HHHH@H)HHHH t HL@A H t HHx H t HH0 L LLEfu H2 H2 H(HHAPWVASARAQIIH1 Hƿ H@HH H8@)tFH(HHIHHH&2 Hƿ DžDC HHXHhHHHH uPDžDHH(HHIIHHH1 Hƿ % H@tiDžDHHHpHHHH(QIIHHH1 Hƿ HJ HHH H)HH@HHHLPHLHHL HHEfu H/ H/ L(HHARAQAPWVMIH1 Hƿ H0HHHH HHHH uDžDQ HHHHHH)HHHHHH HGHHHHHHPHHHPH HH HHHHUHHHy DD HHPHHHHHIH|HH 5HHHH HHHDHhHC4HpH44D yHH 4DHUdH+%( tDH] UHSHHH}HEHEHEHEHEH@ HEHEH@HHgE fHEH@@UHcHHH@HgHE@(t2HEH@@UHcHHHHEH@HvHމtjEEHcHEH@8H9rHEH@Hu1HEHP0HEHPHEHP(HEHPHEH@0 HEHPHEH@(HHEHEH@HM HHHEH} uH} uRHEH@(H HEH@0HMHIH4 HMHHH'HEHUHPHEHUHP H] UHH H}HEHEHEHEHEH@0H-2HEH@@H 2HEH2 UHHH}HuHEH4 UHH H}HuHUHUHEHHх UHSHXH}HuHUHMLELMdH%( HE1HEH HHUHEHH_t HE؉HEHE HEH@(HHHEH@0 HHZHEH} u k HEHUHP0HEH@H HEHPHEH@HHHЋHEHE HcHEH HHEA A H\Eԃ} tE HEH@HPHEHP HEHX HEH HYH9r HEH@ HEHE HcHEH HHEA A HR\Eԃ} tESHEH@ HPHEHP HEHP0HEH@(HHHE HEH@(HPHEHP(HE HUdH+%( t?H] UHH HHHLLdH%( HE1HDž HDž H 0 HAf)P)`)pHDžP0 HPHXH H(H`HhH0H8HpHxH@HHHDž HDž HDž HDž HH HqHH@HqHHHH/ t.j HHHH y Dž u 蒭HLLHHHHWHWuHH ! t H8HH HWUHHHtHH P 诃HH uDž HHHP HHHHH!HPH@*t~H H7HH H HH HHH tH t H uPDž H H蹂HHHP@HH@@HuDž Dž HHcHHH)HHH LEH}H HHHMIH E H HPHu )t_z ؉EHHHHQIIHщH& Hƿ H H@( H HU -) ؉uAEHHHIIHщH& Hƿ UH H HHQIIHHz& Hƿ H H@*t~H HHHH HHHHH HHHH HHHHEHcH HHHHK H H@H(H@(tEH H0H H@HH HHIHHHHHyX tSHHHHQIIHщHZ% Hƿ \H0 HH@@HcHHHHBHH@@HcHHH H HHH@8HPHHP8HcHH9"H@*X HE8 H6:Hf)E)E)EfEHE8 HHUHHUHHUHEHEHUHEHUHEHUHEHUHEHUHEHUHEHEHMHHIȹ H蝏HHBHHH@HHuQM ؉HHHAIHHH# Hƿ jHHr&HHc&HHT&HHE&HHOHH H HH&HH%HH%H tHHYHH%HHOHHJ HUdH+%( t5 UHHĀH}HuHUHMLELMHEHEdH%( HE1HE HUHEHHH " HH~-t HE@t u HE@HEHEHEH}w O HMHE HHHEHHEHUHEHH+EHHEȾ H}BHEH} u HEHUHEHH9Es HE u HUHEHH+EHHEо HBHEH} u HEHUHEHH9ErsHEHUHHEHUHPHE t HE <:uHEHM! HP HEHUHPHUHEHPHUHEHP HUHEHP( HUdH+%( tq3 UHH@H}HuHUdH%( HE1HEHUH HEfǀ HEH@HEj HE f ~HHEHHHEHPHEH IIH Hn Hƿ ؿ% HE HHHHEHHEHE HMHUHEH E} yE E HEPEyE؉EEu4 HHЃHtE )HEP;MHE HUAHщH Hƿ 8EHHEHE HEf HE HUdH+%( t1 UHH H}E |E gEHcȋEHcHHHHH H]Ā HHEHH:uu$EHcHHHHHHHĀ HAEEvEExHEHH Hƿ ҽ UHHPH}ȉuHUHMdH%( HE1H}HuHMHUHEIIH5 HǸ wuHHE@ HEHHEHHEHEԃ} yEq EԉHEfP \ HuHMHUHEIH5] HǸ uEHE@ HEH HEHEEԃ} yE EԉHEfP HuHMHUHEIH5 HǸ uBHE@ HEH HEHEԃ} yE EԉHEfP }HuHMHUHEIH5 HǸ $u%HE@ HEHHEHHEf@ ,HUȋEHщHo Hƿ ѻEHUdH+%( t.UHH}HE] UHH}uUUEHE@9r UE;Es HEHEH] UHH0H}؉uԋMHEغ HHEH} t HE =PKt HE@fEUEHHPHE؋@H9t HE@fEHE@fuHE@fuHE@ f9EtNHE@EHE@ EUMHE؉HHuHE؋UP UHE؉P UHH(H}EHE؋@w`HE؋@HHEHEH- HE"HEHE؉HE}t HmH} xHEH;E~ } uE UHH0H}HEؾ HǸ E} y HH4 E HEH}t H9E~E#H HEUA Aй Hƿ XaHE ؉EE>#H}uEHH5 yHEH} u!HUHEHH=NH_HEHUHHEHEPHEH4E} t.HUHEHHMHEHSEHHHE UHHH}HE@HEH HHMHEH UHH H}uMHE HDHEH} t HE =PKt HE UHH8H}؉uHUȋUHE؉HHEH} u * E HE@uHE@t HE@ЋMHE؉HHEH} u HE@EHE@ ЋMHE؉HUHu HE@ EHE@EUMHE؉HHEH} uPHEPHEfHEPHEfPHEHUHPHEHUHPHEȋUP HEȋUԉP$ UHHPH}HuHUHEHY4HEHEȋ@ EE MHEȺ. HbHEH} t HE =PKt E.HE@ fEU܋MHEȉHHEH} u HE@fEEރuUEރuJEH9Eu@HEHEH HUHEHHPuHEH*HUHEȉH}<EEHE@ EHE@ EEHEȋ@9E UHH HXHPdH%( HE1 u-HXHH Hƿ 袴` HX HǸ `` y_߄ ؉dHpd HΉHHXHHHb Hƿ d ` ޚHhHh uGuHHXHHH$ Hƿ 足` _&HP`PHPHhH HUdH+%( t\& UHHH}H} t HEH H4HE@v UHHpH}uHUdH%( HE1)HUHEHH&HtUE9uHE$HUHEHH-,HEH} u HUdH+%( t% UHH HXHPHHDD@dH%( HE1HDžh HX H'HUHPHH ^Hu=tHHHHHH Hƿ q DHP HHhHh u-HHHHe Hƿ 藱 HpHhHH8%Hu EHXHP(Hh H%HXHBHXH@Hu=sHHHHHH Hƿ s HXH@H@HM HHHXHP HXHPHHX@ D t HP oHCHhHh u Hh H%HXHBHP oHHhHh u Hh HҊHXHBHXH@Ht HpHhHH~#Hu*HHHH Hƿ 蒯EHXHP0 HUdH+%( tV" UHHPH}dH%( HE1HEH@HEHEHHEHE HEH@8HEh HEЉHEH@HUH訁H. HE@HE 9 HE HEHH(HEH HHdHEH} HE@HEH HHPHEH} HEHP HEHH"H HEHPHEHP8HEHUHHE@` HE@d HEH@HtNHEЉHEH@HUΉHYHtBE% HE؉P`E% HE؈PdHE, HEHEH@ H9E HUdH+%( tq UHH@H}ȉudH%( HE1HEH@Hu E fE9EtEtwUEЉEFUEЉHEH@HU؉HHtHE؉HEHH0HEH HH)c-HEH@HUMԉH~9Hx HUdH+%( t UHH@H}uHUHMLELMHEH HUHMHHt HEHHEH t HEHHEH <@t pH} u b} uAHE؋P`HEHpHEH} u 5HUHEHHbHEH HUHHb UHH}HEHPHEH@0H)HEH@8H] UHHp HHHdH%( HE1E E HDžHUHHHWHuClHHHHHz Hƿ ܪHDž_E EfH@ HK6HH tCHH+HHH <@uHHHH!HHh(HHDž Dž DžHLHHHA HGHHHb H = HtLHHHHMIH H@ H HHHHH9 tStJHH HHIHHHs Hƿ HDž_N t*HHHHH2HH H 7H ~<HHHIHHH Hƿ H uP t H H HHIH Hƿ ħHDž0HHHHH Hƿ 芧HHUdH+%( t` UHH@H}HudH%( HE1HEHUHEHH-HHEH} tHE+HEHUHMHHHEHEHHEHUdH+%( t UHH H}HuHEHEHEHEHEHHEH HH] UHH@ HHHDdH%( HE1E E Dž Dž H HHH t H H_HH H_HH t H uDž Dž cHH HHЋHcHHHHH HHHHHHB ;|HcHH=HѺ HLDž HLH HH@AH! H HHH @ HDž0 HDž8 H H H0HcHH0LU HHH H@ HH HHHHH H HH H9 H@t_tVHH0H H HHIIHHH Hƿ ]Dž u .HHHHPH@HH H R;t DžHHHHH tHHwH HHUdH+%( tN UHSH( HHHHdH%( HE1E E HDž HDž HDž Dž H HHH t Dž ! HLH HH0A H HH HHH_uqHHPHH HѺ H> H HHPHHH HH HH0HJHH GH uH t$H HHHHHDž tH H H HHUdH+%( tH]UHH}HuHUH} t[HmHE HUHEHHMHUH HEHEH;EsHUHEH uHUHEH ]UHH}HE] UHH}} x E E UHH <dH%( HE1HDžH ƅPQQQQfDžR DžT ƅXYYYYfDžZ Dž\ HHH` HDž` Hp HHpHPHHhDžd <E< t E EH`H0 H HHHHH` HODDeHUdH+%( t UHHP dH%( HE1ƅ@AAA AfDžB DžD ƅH IIIIfDžJ DžL ƅPzQQQQfDžR DžT* ƅXYYYYfDžZ Dž\ ƅ`aaaafDžb Džd H8 H t f) )0)@fօPHDž 8 <TH H(HHH0H8HHH@HHH HHPHH`p H tA A H HHHDžp D<HHH`HhHHHpHxHHHHH HHHHHHHH H(HHH0H8HHDž HIA H] Hƿ ytj ؉Hp HΉH؉HAHH HH Hƿ 轙eDHcH`H@IIHH H¾ [HUdH+%( t0 UHH0}dH%( HE1E E E E UHEAй H H oHUdH+%( t UHHP}dH%( HE1E E E E E E E E E E E E UHEAй H\ 0 HWHUdH+%( t UHHP}dH%( HE1E E E E E E E E E E E E UHEAй H 0 H HUdH+%( tR UHHP}dH%( HE1E E E E E E E E E E E E E E UHEAй H 8 HKHUdH+%( t UHHP}dH%( HE1E E E E E E E E E E E E E E UHEAй HZ 8 H%HUdH+%( t UHH0}dH%( HE1E E E UHEAй H HHUdH+%( t_ UHHP}dH%( HE1E E E E E E E E E E E EUHEAй HF 0 H fHUdH+%( t UHH@}dH%( HE1E E E E E E E E E E UHEAй H ( H\HUdH+%( t UHH ldH%( HE1HE8 Hm l t lf)E)E)EfEHE8 U܉EHEHUHEHUHEHUHEHUHEHUHEHUHEHEHEIA H Hƿ ||HUdH+%( t UHH dH%( HE1H p Hf tA A Hp HHHDžpp Dž| DEuHpHxH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHUHPHXHEHUH`HhEEEEEfE E EEEEEfE E Dž HcH HEIIHHn H¾ SHUdH+%( t% UHH@ dH%( HE1Hp H tA A HP HHHDžPp DduHPHXHHH`HhHHHpHxH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHEEEEȠEfE E EEɃEEɃEfE EEзEуEEуEfE E EطEكEEكEfE E EEEEEfE Eq EEEEEfE E Dž HcHHEIIHH H¾ DQVHUdH+%( t UHH0 dH%( HE1ƅ`aaaafDžb Džd ƅhiiiifDžj Džl H 8 H t f)@)P)`fօpHDž@8 \tH@HHH HHPHXHHH`HhH H(HpH0Hp H tA A H HHHDžp D\HHHHH HHHHHHHH H(HHH0H8HHH@HHHHHPHXHHDž H IA Hf Hƿ yw@\ ؉Hp HΉtH؉HAHH HH Hƿ e HcHH`IIHH7 H¾ M yI H Ή& HUdH+%( t UHHp}dH%( HE1E E E E E UHEAй H Hh E} y YHE HHEHHEE HUHMEHΉ.#EE!} HUdH+%( t UHH dH%( HE1EEEEEfE E EEEEEfE E H p H tA A Hp HHHDžpp DEuHpHxH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHUHPHXHEHUH`HhH HEIA HH6 H¾ J y X r ) ~SX ؉ x yu HUdH+%( tt UHH <dH%( HE1H p H< tA A <Hp HHHDžpp Dž|0 DEuHpHxH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHUHPHXHEHUH`HhH`P Hf)))))HDžP HHH`HhHHHpHxHHHHHHHHHHHHEEEEEfE E EEEEEfE E HDžX H HEIA HH H¾ iGLL yUU B HZ HHXHDž H`LHѺ0 %PT ؉TP y Tt-P x PL DžH HHXHDž H`LHѺ0 PUT ؉TP x PLP yTu HUdH+%( tv UHH dH%( HE1EEEEEfE E EEEEEfE E H p H tA A Hp HHHDžpp DEuHpHxH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHUHPHXHEHUH`HhDž HcH HEIIHH H¾ GDYHUdH+%( t UHH0}dH%( HE1E E E UHEAй H HHUdH+%( t- UHH \dH%( HE1E E E E E E E E E E E E E E E E E E E E E E E E E E E ƅ`aaaafDžb Džd ƅhiiiifDžj Džl ƅpqqqqfDžr Džt ƅxyyyyfDžz Dž| DžP DžT DžX Dž\ Hpp H\ tA A \H HHHDžp DLHHHpHxHHHHH HHHHHHHH H(HHH0H8HHH@HHHHDžd \HEAй H l Hhh y hHPHDž Dž dHcHpH`IIHH HH Hƿ ?lhlHUdH+%( t% UHH HxtdH%( HE1tHHHą HHEHx uH쌁 HxE tH HxHHEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHEr HEHPHx@X҉E} E tH HxHHEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHH6 } E tH HxHHEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEȋHE+HEHHEHEHHMHUHHHv HEH UHH* Hƿ TzE tH HxHHEHEHEE }tM}W}t3}K}t}t=HEHEЈIHEHEf9HE؋HEЉ+HEHHEHEHHMHUHHHE tH HxHHEHEHEE }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHEHUdH+%( tUHH}HE@ ]UHH}HE@] UHH@H}HuЉUdH%( HE1HEH@ HE@ HE@$ HE@( } t}f HEHd: H H HH H>HEf f@ HEf f@HE HE@ HEf f@HE HE@ HE@ HEf f@HE@ HE@ HE@ zHEf f@HE HE@ HE@ HE@ HE@ 2HEf f@HE@ HE@ J HEH" H H HH H>HEf f@ HEf f@HE HEf f@HE HE@ HE@ HEf f@HE HE@ HE@ kHEf f@HE HE@ HE@ 9HEf f@HE HE@ HE@ ;2HE؋@ tHEHHE؉P(HEHUHP HUdH+%( tF UHH}HEH@Hu / HE@ yhHEP$HE 9}-HEHpHE@$HHUJ$HUHDHH HE@ HEH@HP HEHPHE@$ HE@ uHEH@ HEP$HE@9|8HE@ PHEP HEHPHE@ HHHEHPHE@$ HEP HE@(9}.HEHpHE@$HHUJ$HUHHDHHHEH@ ]UHH}HE@ ]UHH}HE@ ]UHHH}HEHfEf}tf}u UHH}HEH ]UHH}HEH ] UHHpH}udH%( HE1HEH UH!HEHMHE HHjE} t$E;HEHP0HE HHЋHEHEHHEH} uʸ HUdH+%( t UHH0H}HuHEHEHEHEHEHHEH HH})E} u:HE@t+HE@t HE@HE@)E UHH@H}HuЉUHE ẼEE iUEЉ EEHHHHEHHEHUHEHH E} uHEHE} EE EEE;E~HE UHHpH}udH%( HE1HEH UH HEHEHut HMHE HHoE} E HE E HEH UHq HEHEHt#r m}t|^wV'HE@EPHEHHEHE E5HE@ 9EsHEH@0UHH E E } KHEHHEH} " HUdH+%( t UHSH HxdH%( HE1HE E Hx@ H)HEH} u EW Hx@ HHHEHHEE HxH@UH HEHEHxH@MHHHMH HHEHHHEHEB HEPEHHHEHȁ P ʉPEHHHEHPPEHx@ 9E?Hx@ HEHHѺ HiHx@ E%UHxHE} EHxP Hx@ 9ErHx@(H H(HEH} u E E mHxH@UH HEHEHu9HEȋ t/HEȋ HEH <tHEȋ HEHEHx@9ErE [ HE HE HxH@UHHEHEȋ HEHCEEEHEȋHxH@HHEЋE HHHB Hu$H0Hu:% Huo EEHEȋ@% E ЉEEHEȋ HEH <E ЈEHEȋ@% E ЉEHx@ HMHEHHHE HE@ tHEP Hx@ 9r3HEP EщHC Hƿ kE HEP HxH@HKHEHEHE}+ EH H HH H>}t} }t.}t= HEHgHEHY8t3 HEHDt$ HEH/ E;E HEHPHEHB8t_c E;EtUZ E;EtK}tEG HxHP0HE@ HHЋ u!HEȋPHE@9 HxHP0HE@ HHЋ HxHP0HE@ HHЋ tkHxHP0HE@ HHЋHEȋpHEP HEЋ}HQAAHHl Hƿ iHEf HxHP0HE@ HHEHxHP8HE HHHEȋ HEH} t+HEH;Es!HUHEHHEHx@9EE HxH@0UHHЋ t HxH@0UHHЋ uiHxH@UHJHEHEHxH@H聽HEUHEHH Hƿ thEEHx@ 9EHHEH8HEH,EHUdH+%( tH] UHH H}E HEH@UHxHEHEHEEuN HHЃHt4HE uTUEщH. Hƿ gDUEщH\ Hƿ VgEHE@ 9E; UHSHxH}udH%( HE1HEH UHHEHMHE HH5E} E HE HEHE@$9r"HEHEH(HE@$)HEmHEHP8HE HHЋ E} u?HEUHEH HHH~ Hƿ 0f,UHEHEHHEH} 7 HUdH+%( tH] UHH H}HuHxdH%( HE1HEHnEf)E)E)E)EE HEH4HEH} t HEH9Eu HEHEHEH EȋEЋU)UHEHEHEHEE H HEHEH茨@ H HEHEHjHEHEHZHEHE@EHE@EHEHt HEHu E HEHyE} EЉE$UȋE4EHUMHHʉ) EE;ErHEH;E} E EЉE"UHEHE} uEEE9ErE #UЋEHEHE} uJEE9ErHUHEHHTHx t$HUHxHHE HEHsHEHgEHUdH+%( tPf. f. f. f. f D UHATSHdH<%( H}H=3 5H%` H5 1 5 CH=I` 4H%o Ht/H o L%}3 fHKL 1H5HHuHEdH+%( uH [A\]Ckff. UHAWAVAUATISHHLodH%( HE1HEHE HEM I} I$ 1IH52 4I $MMMuHLMHMLuLHtLcLLHMMLH! HH1JH 1!HuLM H]AHo BIM H@HEdH+%( uHH[A\A]A^A_]5 D U1ɺ HAWAVAUATASH8H dH %( H]H1H8H5r; A A H ) HDH L57q AM H51 LAątcH51 LtJH L H5^ 1W31HUdH+%( H8[A\A]A^A_] A H D H g EF L;H5 LL5Ml H>l HEM LL Ad HCH5c HHE5 HELHMt9MMt1HuLLMLE|LELM MAIMuHE8-Z xhP x F LH54] 12HEHXHt:HHt2L%/ ff. HKL 1H1HHu ?kf_f D E MILLELMH}IE|McL LELLIHݵ H1 L 1 LMHsA}LcALE,E @ H yj MHHH; uf E1 HEHEL0MLH5. 10 V H=y[ /@ LLH5~. 1 LMs0LMHEML0H}fLH5V[ 1:0HEHXHXHL%- HEf D HKL 1H/HHu @ H}H5- HULH5[ 1 /f. f UHATSHdH%( HE&m t/H m L$ff. @ ; HI9uHEdH+%( u H[A\].ff. UHAWAVAUATSH =l dL<%( L}I AG A H5 Dž\ Xr.H LHX KAGtQE1L`Ad 1ff. DHcA)LHc9KÃc~AE;wrHEdH+%( u"HĈ 1[A\A]A^A_]Ad$ f. U H5 HAWAVAUATSH dL4%( LuIDž\ AFX`-H9KHX KSSSSESSSSfnd fp )`)p)E)E)E)E DžH AFL`} DžL d f DLE1f D IcHC| H)L,OJAAc~كLAFL9rHH; d {HEdH+%( uHĘ 1[A\A]A^A_] UH " H" HAWAVAUATSH dL%( LEE1c < HHi HVJ=i H^ H-J=i H =|i $c fi 0 Džl L-%f Hfnp DHpf~9HH|IH e HpLb fnHfAnHfoLXHPfbHH HxHHJHH`f֕( IHHIE =h Mu LpIMn H b fnfnfb=>h AFAFu(%FHumLD1} D LLɸGK gLHLGLHLH?7THL=g A$ HxHIH9LpH`HL=I@ LIH=Eg AD$ ID$ $KGB AD$A|$ H5l LDž (HGH ;FSSSSk` ESSSSfnHfp )`)p)E)E)E)E E1AL`DI } Dž d f DE1f D IcHC| H)L(^FAAc~كAG9r; _ {1D @ H1Ҿ AG0F = 1Ҿ HPAE=me L% LL ^ 6e 1Lt( LF HEE; d r1H# L&HB d 1Lu$JLȧ H; d s(=d tHd LH<H?; qd rL1LHL+H+y IH@B H j HS㥛 H5( HH?1HHLH)I&H=c L-` 6H=` H L9t HGIHCHHHM9uH=` L-{` H L9t HGIHCHHHM9uHEdH+%( HĈ 1[A\A]A^A_]1Ҿ H?Cf L L'CK LHtBLLLHk2CLHHH9p=b u HXM|$l;HGL9ub ll(; 6\ xb DH cb =cb L-SO H 7 H5T IE1$[ =,b L7 MEH5X& 1 \$L HS㥛 HH?H5L& 1HH)IH.& $$ 5H! H5& H81賾 BBBf. UHAWAVAUATSH H $ HHdL<%( L}L=_a HcI<H> L%8a M,M =Da N I3AL 1LF- L;Lg= a A}( I H5% 1Dž D ADtIIH5T 1"DA s H=f% !b A}(H1 H5% *H: LL"H誹A9 1HUdH+%( HH [A\A]A^A_]f. 1脶A @ H5x$ 1 薪IIH[Q D IH5R 1D!DALH7$ Lԫu7I L H5R h! f D IU H5# 1I!Di2f UHAUATSHdH %( H]H?E 1 ZX E1Lmԅ~: uJ{ LA{ Lf D;%X |HEdH+%( uDH1[A\A]]Ð{ LA, { LLD9%W 봐C U D UHAUATSHdH<%( H}H H , HIHHtY LޠH{H] IˠH] HtVMtQ1LЯHEdH+%( ~ H[A\A]]H L H"Q H81PH H=<" H(Hx H=" Hd(o:f. UfE1H = HV HAUATSH dH%( HE1)E)E)EGH}H}1HpE=\ E E EEEEEEE4 H ]HM1HH}+HHMH}1H]+H}1H}1H1%LeH]L+pH+x H=[ mH=[ H=[ UH=[ } uQ} uKHf HS㥛 H5 HH?1HHLH) HEdH+%( HĘ 1[A\A]] IH@B ? E AAŅ^ }nU 5T H]~? M Hޅ }A} H D9%RT 1=Z HzG H 0 -T HEH5jN 1Mi@B L HS㥛 HHH5n H?HH)1IHv l IS fI*ff( *S H58 X^( f 1*}S X^ H5 ^,J @ } 9S E1H]~:f D E Hޅuq}A} HED9%R Hl1D 'f D }A} H4D;%R 'Zf}A} HD;%R W D LAfHL H*XEH]W EH H H81z 諺f. UH T Hm HAWAVLpAULPATSH dL%( LEE11H@)11E1 & 1L H Hx H = HEH HE fP1HDžp LX=8A (8n =sW 1H=Q fA !P f1A)LLA)FDA)F A)F0A)F@(8U 8HpL!DHDžXHP1HDž` ˣ7HH; hP fn( L1H<\ 977<Ѓ<M7Ѓ ?71LvLPHXL+@H+Hy IH@B H HS㥛 H5j HH?1HHLH)"HEdH+%( Hĸ 1[A\A]A^A_] 11 !@D袢>6 D H9O H5O 1Mi@B L HS㥛 HHH5v H?HH)1IH~ tI HN fI*H fH*f(ѿ H58 ^(f( HN (H fH*^ ~ ^H5 1,f D LAfHL H*H#N XHTHfHH H*X? HfHH H*XdHs H H81 [E1111 {41 H=t UE1H H HAUATSHHdH%( HE1S H}1sS ~1f ;2; VS |H}1ULeH]L+eH+]y IH@B H t[P HS㥛 H5Y HH?1HHLH)HEdH+%( 3 HH1[A\A]]ÐR H H5 1 Mi@B L HS㥛 HHH5 H?HH)1IH HLxvfH*ff( *7R H5[ M^NfM1*R ^ H5 ^, D HfHH H*XuH H H81蕮 Ƴf D UE1H H HAUATSHHdH%( HE1YQ H}1UCQ ~ 1f 1/; $Q |H}1#LeH]L+eH+]y IH@B H taV HS㥛 H5' HH?1HHLH)HEdH+%( 9 HH1[A\A]] P H H5c 1 Mi@B L HS㥛 HHH5X H?HH)1IH` VHLxvfH*ff( *O H5# M^fM1*O ^ H5 ^, D HfHH H*XuH H H81] 莱ff. UE1H q H HAUATSHHdH%( HE1O ' H}1O ~91 u 13 11 ; N |H}1LeH]L+eH+]y IH@B HC t] HS㥛 H5 HH?1HHLH)HEdH+%( HH1[A\A]] .N H H5 1 Mi@B 9L HS㥛 HHH5 H?HH)1IH HLxvfH*ff( *M H5 M^fM1*M ^ + H5o ^, D HfHH H*XuHs H=< Hb XHI H= H8 .H H3 H81豩 f UE1H H HAUATSHXdH%( HE1yL ' H}1ucL ~O1f H HE HE Dž" 11 ; L |H}1LeH]L+eH+]y IH@B H tG HS㥛 H5 HH?1HHLH) K H H5k 1 Mi@B L HS㥛 HHH5` H?HH)1IHh ^ HL fH*ff( *K H5' M^ fM1*J ^ H5 ^, HEdH+%( HX1[A\A]]f D HfHH H*XYH H= H Hu1H=z Hm H=g Hf \HM H= H< 2H# H7 H81赦 f D UHHAVAUATISH0LwHdL,%( LmIAH}1}C ~1ېLLA9 B H}1OHUHEH+UH+Ey HH@B f*B MxRfI*YffH*H*^ X^HEdH+%( u0H0[A\A]A^] LAfHL H*XϪff. @ UHAWAVAUIHATI1SH8LLdL4%( LuI$LLLAH}1MA ~1ېLLLA9 A H}1 HUHEH+UH+Ey HH@B f*A MxQfI*YffH*H*^ r X^HEdH+%( u/H8[A\A]A^A_] @ LAfHL H*X蟩ff. @ UHAWAVAUATIHSH1H(LwLdL,%( LmIHLLAHE=G HHE HEHE@ ~$E1 HLLAAD9=q@ Hu=UG HEHMH)HUdH+%( uH([A\A]A^A_]赨 D UHHAWAVLuAUATSHH(LoHdL$%( LeIAՋ=F L?HEHE? ~&E1f. DHLAAD9=? =F LHEHMH)HUdH+%( uH([A\A]A^A_]f D UHcHAWAVAUIHvATISH(EdH%( HE1HLL<3IOIH5 Hÿ 1H- E1A|$ H 9 =E HLLL AT$H J 1uC=E H fH* ^EH5 f LؖHEdH+%( H(H[A\A]A^A_]鯖 AT$H ff=D H5 kf LIHH@ H59 1E1/Jf. H@ H5 1H5 D 1=CD uj ] f/B [ K f(Yf/ A Yf/vof( H57 uHxsfH* ^EH5 GbfHfHH H*X fYʿ H5 f( D HfHH H*Xxf. f( H5h 謤ff. UE1HAWAVAUATSH(HJdH %( H]HHq =B tAI6MAH5 B * 1裘B Aą H=> f* ; IH fH*YMM L5|> E&Aa. L;I?EF IE1H ff. @ H5u Lt-A>huA~ t LH5g 1jf. H=` A L-h gHHHt1ff. HHL 1 HLIHHuA 9 I?IAHLLuELDHE1HEdH+%( H(D[A\A]A^A_] D EfAlEfL;AlI?EA Htff. EDLHAiHJ0IHug @ 8& H3 H= 6 H" 3 D LHfH H*XYMMH H b< H A H81c虡HZ HS5 A01R @ UHH0~<~ dH%( HEHX HUEHEHufHnH~ flHEExHUdH+%( uf UHH0~~ dH%( HE1HV HUHE HEHfHnH~ flHEEHUdH+%( u茠f. f U1HSHH j dH%( HE1 @ H,H ooffH~Hyf HU HEdH+%( uH] UHAVAUATSH j? HLodL$%( LeIH躒-+? HH=s> 莎H趸07 E1H 7 @ IHID$E1E1j ? J41ɓ; ZYu[ 8 M 6 IF9r=> Ol5tMl$HEdH+%( u5He1[A\A]A^] D => u D H== Ҟf UE1HAWAVAUATL%~ SH ~ LHH dL,%( LmE1 oIH H0L HHH8B1H HH0e=5 5 ߾ HHH =x5 D=x5 L5? c D-l5 HMAWEH54 1E1fH=&= H< )< fo, < H=y< dH=-< X4 < HHHƋH= 1HcHH?D 4 H_LIHAXE ff. @ Eu =v4 IEH H1LbL*1LDHHHH9sH HI HLH HI}LHX [ AI D;53 FL~HH=; 5x; t)ff. H5y; H=: ͊ O; uH=: 7H=P; ۴=M3 H 1\; H舰H ooffH~Hyf L- H1ۋ2 AE Lpt.ff. fI>1趝uI ; 2 rH=(: E1H ^: yH=9 mH=: aHLp|2 L? M 1LH5 2 LAI `D;=.2 s`IM E1H~ IF1HILHM H1 8 u1 IAvuMH51 1 G D LH ٓ f/ L,HBI] M fI*AL =e1 H H` HDH5d1 H趉L讉HEdH+%( He1[A\A]A^A_]f. 9 L5 f. \L,I?3 D LLfHH H*X+ L0 L8H5k 1L H54 1jLHo誘f. UHHdH%( HE19 HEdH+%( uh UHATSHdH %( H]H 9 H%-7 tZHH=8 HH +9 D%7 H1DE1j E1H 1PZYt1rH=k8 @ UE1HAWAVAUL-~ ATLSH [~ HH dL$%( LeE1z _HHH0L HHH8.1H HH0Q=. . ߾ H8 HZ=. D5. L%+ F HMAVL 7 H5R/ 1ffo7 H=p7 ) i6 z6 ) 6 6 HY6 H6 H=6 =H=6 1H AYAZDž DE =!7 L5 7 1L讨- LcL5 I?D- IIIE L8L1LKH1HɥHHHL9sH HI T LLL= 1HLLn LI; , [LcH=5 =4 t*ff. fH55 H=5 轃54 uH=,5 1%H=5 ɭ H1聩D%F, EtM O4 E1f HE1E1j , 1 H5v5 ɈZYAD9%+ uD1HL54 HHLH+H 84 IH@B LHHL=+ % + E1t'H4 1J<>IID;%g+ rH B ;}MH=34 H=3 H=[4 փHxHfI~葱LfI~xfInfH~fIn fHnӋ * H56, H,f(ȿ fIn^ƌ H=4 H葋HEdH+%( He1[A\A]A^A_] D fD D[* H5+ I*ōP ^K ?2 L% H 2 L-E2 H) A =!LxH5 1L]H5t 1LH诙f. UHHdH%( HE1f4 HEdH+%( u訑 UHATSHdH %( H]H 3 He-2 tZHH=b3 =HH 4 ^D%2 H1DE1j E1H 1萅ZYt1貧H=K3 @ UHATSH0dH %( H]HH=2 %H}1誥HE1E1j D%s( 11 H5[3 DCZYA9tDH=:* 1;H}1PfoEfEfH~Hyf C1f D UE1HAWAVAUL-h~ ATLSH ;~ HHh dL$%( LeE1\ H0L HHH8ô1H HH0=0 蔹HH* 0 D%0 AD$9 0 AA ߾ D5' 0H1 H=Z0 L= 5 AVL 1 ATMH5( 1ffo- H=o1 )H0 -Y0 )z0 -0 H80 Hm0 XH=0 蜵H=0 萵H) AZA[Dž| A =!1 3 =/ CHH L-0 E1Hc/ LcLk/ I?D G/ IIIE Hx|L1L苐HO1HDHHHL9sH HI LLH( 1HHL HAID;5. YL衁H=/ 5D~. Et&f H5/ H=b/ {5W. uH= / E1L%]H=v/ @ 7H_{1H. H=. 1P>=- Lt7ff. fLLHLC AI D;5- rH=O. E1 - Lt)f D I>1趎 AI D;%c- rH=. H1觼=- t3ff. fH. 1H<^ H; - rڋ- p HE1L%[- H - LhMff. fIvLAI \AvHP , A9rՃ|=, HU{H |;H=y- L%, 草H=&- 聉H=- u{LpLfH~0H=Y, fI~pfHnfI~fInkfIn + H5% H,f(ȿ fHn^a H=M- zH,HEdH+%( H He1[A\A]A^A_] fo fHDž HDž )) ME1HLf D It$HAI At$LD;= + rH]oHfI~LfH~CofInfI~fHn/ fInD* |H,f(ȿ H5$ fIn^ a|=n* fo= fHDž H)LHDž )")* L=C ׳&f. H(D%) ) AD$9*1AoA"L|H5 1L|H5 1LHHL\,f. f UHHdH%( HE1, HEdH+%( u UHATSHdH %( H]H + Hz-r* HH=* L%+ rvH蚠f. == 3* uaHE1 E1j 1ɉL1{_AXt8 t= @ HEdH+%( He1[A\]fH1Lj L + E1 1Z{Y^tD_8 V= uH= 1 D H=Q* HE1E1j 1H5* zXZEH= 1'2]ff. f UE1HAWAVAUL-~ ATLSH ~ HH dL$%( LeE1l HH>H0L HHH8辪1H HH0=l j ߾ jH) H4 u %( D=6 D9s + A߀= = Hl L5 LEL% Hp LEHٿ H) AWMPL ) H5! 1AVfH fop H=( ) ' ' ) ' ' H' H' 2H=+( vH=' jH Dž ff. @ =Q( L5L( 1Lޖ LcL& I?IIŋ I f. LhrL1L{H?1HHHHL9sH HI T LLL 1HLL LI; [LwH= ' 'vD%% Et(ff. H5& H=& q % uH=\& 1E1RH=& ,H1讗D= E D-w% 1E1EA If HDL & 1j H5& 1 vAZA[AD;=. sH= D* tHL ]& D1j H5F& vAXAY E1HL5%% HLH+IH@B L%$ LHLLL= uGf=q I*Dm ^Q{ P D H5d w=4 2 50 1ۅt4ff. HY% 1H<讃QH; rH ;MMH=$ \H=U$ PH=$ DqLlfLfH~LfI~RffHnfI~fIn>fInԋ o H5, H,f(ȿ fHn^4z wH=$ kpHxHEdH+%( % He1[A\A]A^A_] H" DE1j H57$ 1E1}t Y_9H= 1證~A)Eٿ EH5 K AqH" L-" IHX {cf D LsH5 1LsH5 1LH"f U1HSHH dH%( HE1 $ H̓HE ooffH~HyfT H HEdH+%( uH]~ UHAUL-o# ATSHLgdH %( H]HL\q--# LH=u" 0mLX f D = =8# H$# Hs1j E1 E1Ƀ1or_AXu <HHs1ɋ" j E1E1 15rZ^t = I=" yLcHEdH+%( u%He1[A\A]] H=! |b}f UE1HAWAVAUL-~ ATLSH ~ HH dL$%( LeE1| HHH0L HHH8Ρ1H HH0= \ . ߾ zH! H =d D%^ LJٿ H5 E1PfH=%! H ) foˇ H=x H=, H=` 1 ͐L5 葎 HcH߉ H?観= HIIFL, E1H f D H HBL1L~H1HD蕋HHHL9sH HI LLLW H ( HHjLH/ LI{H D;5 sbLDLHiH HHڀ= D2 HtHHBH LnH=I Tm5& t'f. H5) H= i uH=L 臆H= += H 1 H؎HQ ooffH~Hyf` L5 1At6f H1HH Hx|6H; q rH= 1E1wH= L- wH=8 i9 taf IE1H~H> 1HDHILLH 8 = AH D;% rLp^ r f/ H,LM&H fH*7EHٿ =u H; H HDH5 rH={ fhHpHEdH+%( = H 1[A\A]A^A_] H=9 AHH H̚D;% H M H5z HHH1 D D\LH,ߕM&H?HHHfHH H*X D HR NLkH5 1նLmkH5 1躶wLH~f. U HHdH %( HM9HUdH+%( uvff. U1HSHH dH%( HE1 HLHŢ ooffH~Hyfԁ Hu HEdH+%( uH] vUHAWAVAUATSH(= dL,%( LmD- tDo ߾ 購H IH E1t1ME1 fA{ AIA9r؍CLuL}E HM4+ D CAL A<HIXuA$L DXHEdH+%( uDH([A\A]A^A_] @ ǻH IHt D UHAWAVAUATSH8H}D= D- A= dH %( HMHOHMtDoH K HSg-$ HH=l Lu#cHLeG D LDmy8tf. ] k8 L賬= tҀ= HE= L` = ff. HEL`HEdH+%( H81[A\A]A^A_] @ =c u=Y u0HE @ Lھ DE V=) tLھ DM @V Lھ DE wV= t?Lھ DM @UVLeI= HExiLeIH= 薳+|rff. UHAWAVAUATSHXH}fo} dH%( HE1=_ HE )E =E Hw H HEH5 1H H8܆= _ HE = à 芸IHA H1HcL)H1HpHHMHLHHoLIHHoo@oRAM PAE BL9uL!aG HM E1Laf= Ãv{ M4$蹷HEHA f D H1HcL)H1HxHC HLICIL9uH}w`m t[E1Lmf D J f D Hy'8 u I$ L<=N uԋ IHI9r8 II I91H}HE= = t&HU H5 1Hw H8蟄HEdH+%( u*HX1[A\A]A^A_]À= HE qo UE1HAWAVAUL-~ ATLSH ~ HHX dL$%( LeE1茢: H0L HHH81H HRH0јHH= = G Ǿ }HH>H wj = D 2fnfofl) H V=, D5 H L- LED% ) H AVEMH5L 1fH= Ho )X foPy a DH= 舔H= | H=ߙ 1? R=t @AYD5f AZDA A ƀ=j DU =@ HcHH?HD7 HDž IH 1LHHHHHE Lf = t$ ]~AE/= S A] =u ILIEH E E1I Mu== O tA] 1N< %IUMALc HgOZID;% r= LL1LL4nLL1L{HHHL9sH HI HHHiY HHHI}LHN9H I ; >LL/_= P H= ]5 t)ff. H5 H= }Y _ uH= vH=` 苃H1HH =Q H E 1c HH ooffH~Hyfu L-= =$ AE H1 Dl H=% hH= hH= Z= * L1L%% tfIM E1H~ IG1HILL-S IOA$ MH5Z L 1I #; I rLN b f/ H,L$Ee H fH*iHD H5 1= `HDaH L`t'ff. @ I<$I pX; rH\XHEdH+%( Z He1[A\A]A^A_] L1MH5 I ; , z\H,H?= H H V HEH = H8 H5p HE1HV H8~|= WHUFH H5[ 1VH H;7|=f @ H5< 1!H; |? bHo" HHHfHH H*X x VD E = = HB H5 H H h3H= bH H8#{;HfH~H5[ 1 Hȏ H8z1GeLHm H ZH53 1iHYH50 1J D U1HSHH z dH%( HE1 H<zH ooffH~Hyfp He HEdH+%( uH]e UHAWAVAUATSH 8 HHfop dL<%( L}IH)EW- HH= SH}HEHE #H5 1ҋ= HHHIG(4E HHHcHEHHHHH)HHE H# Lu LGu HcIDH}1 =w # =h N tD%M 1Luff. @ IG(L DL, HcE HHE"GuIGIG(L DJc(E HHEFuIGIG(1ɾ DB(Fu IG H; 4 j D H; P 1ɾ F D Lu E LfFHEdH+%( u"HH1[A\A]A^A_]H=) 责bf. UE1HAWAVAUL-~ ATLSH k~ HHh dL$%( LeE1謕 H0L HHH81H HH06HH4 sY ; E Ǿ0 葨HxHH j = D 2fnfofl)P H ֈ[D-? D%4 EE H5 1ffol H=5 ) ) ) H H H EH= 艇H= } H= 1 Su= K sE1HcHH?/HD HDž IH HxHEL LD#= IڦHC(H7 EtHE1 D 1N4AHC(FE IA9r̀=" ` = LL1LLbLLٶ1LDoHHHL9sH HI T LHHLH LHH{HH g AH0D;%X LLS=( H= QD Et-ff. H5 H= ]MD EuH= jH= iw=[ H G 1 HsH ooffH~Hyfi H? =} Hx=j 1L`t"I<$1E`#I0; @ rH=7 H \H= [H= M5 LxE1HL%- ff. fE1Kt7K<LJ43IIu< H LLIO(AC VH5 AQML1 AI0D;-d ZYrL% E1LI LMBf/eV H,KD= LI(zB;IIuHH fH*Hڿ H5D JHH fH*Hڿ H55 HHy fH* uHڿ 1H5$ ʻ=< SHSTHxL`(" t&ff. I<$I0K; rHxlKHEdH+%( He1[A\A]A^A_] D5 E1L D AD;= oHC(DL DHDž p>y HVH5 \gT H,KD= O1t= HHfHH H*XHHfHH H*XoHHfHH H*XH=z T8HH谊eHHHHfH~H54 1 HGQ =9 芠H IHZ MME1 AI1k AEA9rߍCLLDž HM$'CA$L A<HI<uA= L <*=f B H5ܿ 1=# H莟H IHE1)LH@`HLH5 1HLH5 1=X{ UHHdH%( HE1 HEdH+%( u1Wf D UfHAWAVAUATSH HHfoic ,5 dH%( HE1HE HE )pE)ME HPD,I1H@H H8H`H0>f. HLpLmLHc5 L; " H@1} kjHH1AWH8LA LZY H01kH`H+PHi@B HhH+XJHELpLm L;LfH~t, H9 HϽ HEf(ȿ H5 fHn#L;LH;t H5 f(HfHnӿ ^HH5 f(¸ µ1HUdH+%( uHe[A\A]A^A_]Uff. f UHAWAVAUATL%~ SH ~ LHH dL%( LEE1诈8 = u= fHo HE HEEEE1ɺ11BHH= aIHq H= Lm۳1LLHtCLEHff. HUdH+%( i He[A\A]A^A_]ù LLH[L牅]EH襴u= tffH =" )E)EHE)E)E H= D= H D9= H f D A 1H5 D1E1 蘳5 ffo%&_ HDž0 HDž` ) 8)PhuI HL LPALHc5 LH脳D;% 1ɺ11GHH= hH1Y gAWHU1j H A 1LZY 1HsgHH+ Hi@B HH+"H L LP @ LA7LfH~gp H5v f(fHnL7L0p H5w f(ޱfHnӿ ^H5} f(¸ 跱D9= e1 f D Sf D H߉T %ns fHy HX 101aH話Hx H 1016LHXPf. D UHHdH%( HE1HEdH+%( u1Pff. f UHAWAVAUATL%~ SH q~ LHHhdL%( LEE1҃ f| HE Le)Efo[ E HE1L}HxL54L-T HLeL־; sN1Ld1LLauyHx1dHuH+uHi@B HEH+EyH L85L^UI fH~m H5 f(fHn^ )I l1HUdH+%( uHh[A\A]A^A_]LHW<Of. f. UHHdH%( HE1= HEdH+%( uNf D UHAWAVAUATL%~ SH ~ LHH dL%( LEE1 A A A_? pIHcLfo Z fHE HE I)p])U]EN D MDž8 % H HpH0HEH(H 1LPD118ff. ff. ff. ff. f Hʾ HH I t D9rHP E1DH@H`HH ff. @ H@1E1bI thD<Eff. HLAD9s,ff. fDAVHLY[AD9rAD;% rD<HH1aH`HhH+PH+Xy HH@B Hi@B H0E1H4<H@1>ax tZDIDff. E1 IM9t$Mu sDI<<M9u܃; " rLAHH1`H`H+PHhH+XHi@B AH(H4腺D;% h8E 1 H5# 膫L0L1LfH~i H5 f(fHnKL(L0LfH~_i H5 f(fHn 9 tWѥ88A9D MLE:ACHEdH+%( u+H 1[A\A]A^A_]ÿ LHTRJf. D UHAUATSH8dH%( HE1 HuL- Lc% Hqxp1HIkMHID$HtO Hٿ PAD$Hq H 01 ;k 1HUdH+%( u H8[A\A]]Iff. @ UHATSH H $ H H $ H dH%( HE1H L7{ 16ff. @ { Lt"腦 t ud ? D { 0@HEdH+%( uH 1[A\]Hff. UHAWAVAUATSH H $ HxHhIHvILHdH%( HE1HpHxSD LH HXHpHLLsHI9IF1Ht Ht 1HfOt McfAn $ H LxLI fpI fDž fDDž fօ LA|$HDž Dž IH vvLxLLL)lH D= 1LH LL諦fLLHhA|$HcH݀slHxRL& D HhHLLCHŀClHUdH+%( u!Hx [A\A]A^A_]f D HFf. UHAUATSH H $ H dH%( HE1HcHH H fn L LDž H fpHH H5 LH0 1fօ(fA81LLH5 fv{L8kHUdH+%( uH [A\A]]EfUHAVAUATSH H $ HP " H IH HA dL,%( LmAA1Hʤ Dž fHfDDž Dž DDDpjHUdH+%( uHP [A\A]A^]D UHH H $ HP dH%( HE1AHHDž HDž@ HH DDž@ fH Dž HDž HiHUdH+%( uD UH fHAWI AVAUATSHX fo{O dH%( HE1@H HDž HDHT HDž )IHXk L) 01菝HE HIGH L1Hk H ً01AH% H I Ј CA A:A :}:A1_A9A _A9H= 1Dž v_D AD`Hc'HH~ H= #H= H #HCE }[9DH1nf 1HWIL }#9A9A9H0} HHzH }8H1dVA苧 AH AwA?H r = Dž Y= LcIL- ?ME HcЋIHi҃CD H2)Hh i@B 01A)H McLLLHxG l E11 D A ; J DAuLLHyH=[ LpLL L%L^9 fH~U^L H5 f(ȸ fHn^ 9 L% Lf(f H*^fH~] fH5 f(ȿ fHnà H*и ^艟L%LfH~] H5 f(fHnUHEdH+%( HX [A\A]A^A_]i= ;9 AL A6LA?1HLeHf AH D LP01ɘ1LLxSH0H+LHi@B H8H+H49LL.I1@; } L H=" HC AH HD H0ncH @ H= LLL = i UHAUL-A ATLSH ~ HH8dL%( LEE1pD 1AsͲ1ff| H < f H H H5H=i kgx"Hd HQ 01o twH]1HH߾ 1H ~' @ HHHH=& H<_9 H= q,HEdH+%( uCH8D[A\A]]H= AbH= T JhLHC<f. UHAUATSH(dL$%( LeI H LmHL趒HL1j A E1LH觡ZYuQLL% -LHxs1LH薠HEdH+%( HeH[A\A]] D LL5$L,Hc HG 101TH1; Hb HJ 101' D Hb H 11ۋ01Z:ff. UHAWAVAUATSH H $ H H $ H H ~ L%Ҳ~ HLdL%( LEE1m H HI\ HJ\ = Z H LD%G HI4EDLHDHcM>\ HcEt$1HhE2 @ A9, LE b# A9 HhLLJtH ~;H 1HH#a 01rLzDž\;f D L HL该H` L1Hs 01#HEdH+%( ' \HĈ [A\A]A^A_] H= 1L.HhH\HIH fHx1HDž )foD ҏH5* 1MID$( H5! P12M4$M9t0f I I DxyM6DM9uAT$H5S 1 ߗ H5С 1 ƗLN8 L5q_ E1Y @ Mi@B ILLL`TH 8A6D1L`H AxD;% s A6DHX 1 RHhHH Hp1KHTxx5 HrX H誳H蒳H3H0H1KLHL+pH+xMi@B I `H 8z8A6H 1H1tD`HD`6D`D\Hh$& `荓H 8 8A6H 1H1D` L`LfH~S H5B f(fHn褕o Dž\Yf H }7H# 1HH"] 01q @ LH߹ L迡H\ L1H˖ 013 f D HǺ 7H 1HH\ 01LH<4 @ UHHdH%( HE1 D tHEdH+%( u14f UHSHdH %( H]H"H1E1E1j 1H 1(XZtHEdH+%( uH]1 4ff. f U HAWAVAUATSH(H}dL$%( LeL%N^ A|$zHJI HU At$E H]ątBME1H]ff. f1HHL蜠͵AIE;|$rE H E1E1H 1AL$j 'AL$XZZ1 I| 1Hp5A;\$r4 @ L"HEdH+%( uHe1[A\A]A^A_]2 UE1HAWAVAUATL%9 SH ~ LHH dH%( HEH ] ,e L%\ A<$H0yA|$ I yIMǴH MnHH1LH@LIMI @ AGIA; $ 1 LE1HH+ 1LA* ƅhbH@1LxDžt HE %y AWzH= qHEdH+%( H 1[A\A]A^A_]f. LLH01EAD$tqH,L1MI D 1LHLAD$I9rLt 1 I<1H3A;\$rH@1\EL@L+0LHHH+8 A $t!E1 C<I'A $A9rL L HW tI HS㥛 H5 HH?1HH)HHÏmf D HAZ ED$ H5p 1藏L HS㥛 HHH5Z H?Ei@B LHH)1IHX NL%Y AD fH*fH Y H5& A$ H*ЋCf(^fH*и ^A$fH5} H*C^fH*C^fH* Y蠎J A $HH@B 2Ns.HX H H81) jZLH5ff. @ UE1HAWAVAUL-3 ATL%~ LSLH dH %( H]1Dž, Ca HHHE11ҹ AHHw' * ƅhbH@H+HxH@HH1Džt HE !Å- L=Y AAEgDHH tHH8EtjIH,E1LI f AA9H#LHHVHC1ƯAHE9uƋ' E1H01uAL- W AM t@f D 11$ 0U11 $ 'AE;u rH1AH@H+0HHHH+8H Dž, H E1H,E1 1Aj G XH HZIHEt I I>1I.M9uH"HS tUs HH5 HS㥛 HHH?HHHH)11 @ AEGH5r 1AU HHS㥛 HLH5ʍ HHH?LHH)1IHČ 躊Ai@B ffH5 ؉H*H U H*ȸ ^zHEdH+%( He1[A\A]A^A_]f D HH@B 0 談~ KH=- 0f D HT H H81$ ULL1)f. UHAWAVAUL-~ ATL%¥~ LSLH dL%( LEE1\Z L-8Q f1E1 )Efo4 Au H 1HE EL= NL辥IH f. Ѐ H=Ѐ HL4@ILnH I<$Nt0HЀ LIAD$ AFAD$tAFkIL$8It$81AFAF H9t D H H9uAV ENM Au RLP &Ѐ 1Ѐ LY^IH2M,HE\HxHEn 1HpHEHhf f D Hp1<1E zHh1<HEHUH+EH+Uy HH@B Hi@B HxE1H4mWπ ff. @ H1π KL4At'A~ u ID9=π KL4A~ tI>Hi DHtEFE9 HH`siEFH`ID9S HF8HV8E1H9tff. H AH9uEF E9` ID9=| 6*; fHxH! HpDEAu pf(" f(H 1 H \dHc̀ L5̀ ~ H@MM,I<$IM9uL H̀ ̀ HEdH+%( He؉[A\A]A^A_]xIAu H 11) HAu H 11)HAu Hj 11|)HAu H 11p[)f(H 1 H A BLL, % D Au H 11f. UH ء~ H~ HAWAVAUATSH8dL%( LEE1 XHu1A* ~ 1 D Ӌ; ͽ |Hu1*HiU ʚ;HUHiE ʚ;HEH)HS㥛 HHHK HHӅt@ H5h 1HEdH+%( H8[A\A]A^A_]fHM 3 IIL= H L+5ˀ L 1L+=ˀ Lo 1Iؾ L H LH H H=Pˀ tlML- MLH H IO1 Hˀ H9 ˀ t.HL MH MIOH H81 ffɾ L* J L-g H*LH ^ H=ʀ u$H ʀ L iH yʀ @ ffL * HJ L I*^3 H<ʀ H9-ʀ tffL I*H" L * ^ dH:L HN H81 "N!ff. f UHHdH%( HE1HEdH+%( u1! UHHdH%( HE1HEdH+%( u1x! UHHdH%( HE1pHEdH+%( u18! UHHdH%( HE10HEdH+%( u1 UHHdH%( HE1HEdH+%( u1 f. f. @ UHAWAVAUIATSHHH8dL$%( LeMH L5ɀ LcE[ E\ EW E A` HHHIcHHHHIHcHHH9J f. AHEH HE HKE1<H)I| 1HMHDEHb"DEHMIL9}[ E[ DA%b A1DHHH HH9HOHEuH9}AX AY - tIt ID HIT$H)ǃtHHH9m HHHPH9RHHHPH9u= A` HHHIcHHHHIHcHHH9H)H9~EHHAZ IT IDL-f. AX tL AY tIL$HHH9ICH9uHEdH+%( $ H8L[A\A]A^A_] @ ulH)HtSHID fHHH D oHfH9ufofsffH~I@HH<2Md f D ID It ff. L HIT$HPH9uf D AAIDIL5* AX tL AY tIt$H0HL9HBH9uHL1 D UHHdH%( HE1Ht]HHHE H Hpŀ Ht p 1HUdH+%( u$f D H5 1|Ҹ UHHdH%( HE1Ht]H8HHE H HĀ Ht p 1HUdH+%( u$f D H57 1|Ҹ UHAWAVAUATSHHDEDMdH%( HE1H HAAA̅K HE H DE11 A HPIAtUE E E I H% HUdH+%( \ HH[A\A]A^A_]f um t HH9tHÀ uǀ H= yZ 1HL[ EZM0HU1HcH?HHJ+ H}HÀ 11 HcfB 1)E/LcL&R1HIG?HHMH< HH}H HUHu1 LQIH HU1H }+ Ht Hc ~QLE1 ff. ff. HHL9sHIHIM HH9uHu1LzIL H} @ stHHsHIHHHH; H fHnLHfHnfo $ flHflLff. @ foHffBH9uHHVHIJ HHh7H) ǀ H= wH} fH} }HE D kHI#uLE!IIw HP @H Ht*p ~ IWA 1H5 H UwL D 1fjH }HHECLMutEE~lDm1LmH]LDeIff. DH%t"LHL9sLD HHI <ID9#IDmH]DeLHu1LGLA H}8 1% UHAWAVAUATSHx LgD(HdH%( HEȋG G$H# p HG0H,1LHcH?HH^F` HD`AtVpIH!DLJ IE Iu HP>IH Htp LHLeDL LPE 1L 1'bH0 1Ҿ HH Dm Dx HHHIHn [H 佀 HZ YDž D9u 9 ȃ~6H1LLH5 tH U A]A^ H 1v)fo D` fH~)fօhIE IcE1LHDž H@LHDž HH L L EH HMF EH IċHM E 1IH HMDh LHE H Hc L L IL H H1L 1_DLEy%D Eu uDd E HH1Dh,'d Ht&HHH+ H9}H9 I9: h)9x HhH H1ۉ ;1 'HHHJ1IHLH?HHHHH1L HIH H1HjI xZHS ; }KHcHHHH9sH HI HL1L{ALtLLE1~H5z 1.q&1LHcH?HH A LP HHL)L)y HH@B Hi ffHi ʚ;H*HH*XH6 fH*^ LH5 ipH": H8J%AEH 鸀 HHH+ H+y HH@B Hi ffHi ʚ;H*AEH*f(XxHt^p xTffH5| *` ^=l H*ȸ ^f(^ Z YZ }oH u Hc IH ]HE DH1H E1A E1AHE1LH EDfO$vIIA<$x=Hq HAD AD$, A9DG9BID9~H ID9AHEEE! L DE1E1EL H; DH8tC9OA9DLHö I D9ĉDEHӅ Dž E1DLADDt D H; H8oH5X E1E1E~tff. f ~VE1 AD9m ADHH@HH 8 H5絀 9uË AAA9|Dp H9 ;Dp DHDDtE 1AE1퉍 @ Hc nZIƅ~ 1H7 E1 D HAA D9~zADHH@HH 8H 䴀 yL8ff.z HH HDž D A^ ffLfHLff. ofofoHfdfof`fhfefofafiffofeffofafiffH9ufoȉfsfȉfofsff~f9 )DFAv~A~ >f҉fdfof`f`ffofofpNfefefafaffpNffofafafpNfffofs ff~tpHcA46r9}_HcA46r9}NHcA46r9~=HcA46r9~,HcA46r9~HcA469~ HcALtRA9DG9CA A9$A 9 ff. p x wH & Hzp xH)3 H8Q H DD;` L HH5u D 1iH5 LI|$XH EHH H I*I|$XHH!H O H 2HH{XH, h oH{X!H AEDD;` L1L HHH+ H+y HH@B Hi ʚ;HfHi HHA8H=ɚ;v>HSZ/D H HHH1H HHP fH*^v L H AGP tHHi8 Hi0 ʚ;HHi( IG@Hi ʚ;HIGHHt H )H "H˯ HH H ! HEdH+%( He1[A\A]A^A_]Lff.(p H5ls x^h fHDž H ) H f111FHHfɃH H*XE)1D H5r DD fH DDHuV1D 1AEDp E ff.8HDž (Dp EE1DDE)H5 r e H iDDffI*I*^ \H.Dp E?Y H5q eH ff.\VDp Ex-H5fq x^w dH C tA fD xZ&HfHH H*X .p Dž Cf D E1Dž p "Dž A)L;L.H{Hi H`QP`; Hx HD HxhH4 ƀ HphH VH tHxhm H DH5o 1;cH ԫ IED H54 H1c&H Hc 1mHHHH9sHIHIM HH9u9Hx0CHL ƃ LMHDž L6E1AE1gg U! AHAWAVAUATSH H1dL %( LME1i71 HH H* H o H o@ o@ ( o@08 o@@H o@PX o@`h o@px o o o o s)H ܩ H- 8 tDp E H H 1{H 8 H H( Ht1u{H H0 H7 1V{P 6 1Ҿ 8 Yn Dm YDx YYH,@ YH YH,H YH YH,H H,H HH HxhH H cH| HxHl Hx0CH\ H H ? Hc n Dm Dx H<@HL= H A E E1A Odm IcIM H_?AD$HH6H1ID$HIc 1I~>ff. f D HHH9sIT$HƉMHIL HH9uIE9 bEp E I H ]Ep H`HE H`HMHH9 Dž0 HHHYIH - HHMtEp E 1LH [NH{1 Iʼn$BNDD9艅Mؾ# LVDž HtHx 1N_ L$Dž( HtHx 1M(x LDž HtHx 1MMtAp m A 9C $-Z DDZ (HcL5\ LcD$D9K LHIc H?HH Hc0L<@HǍ$I 1EAN1L8Ɖ )ȃ9M(tȍ HƉHHA; 0M (HDž8 Ap x&($H5h 1 [L5@ Ic t3H1IGH#(~Z$ L @ E9 ILHH9sIGLD HHH 4IE90 0H8`H89i A; I IAp /, h(L5W MHc<% {2H1IGH*$ff. LDMLD IfI~LHH9sIFLD HHH <IE9LDMI9H Hj 1yt@ M# Ap $H5 1YL51 H$$HA9H!$H5T 1H1YL=ʡ MtEp E A 09 HAp I H Ep H`HE H`H0E1MHH3 HHH.THH - HIMtEp E 1HM HI1 H8AHL8(D9DMEǾ# HDž$ HtHx 1XH$x HuA HtHx 1*HAMtEp E A D9 (A9Ej LIcD H @C!8Hff. D; JDHIAŅ EE AE;/ DLtLH u L IEZ p x DH5d 1VH ; 8AEuH`A9@$D AD9(I LH09DH5 13VL=̞ MtAp A D9 H Ap Ic HuL=z IA @ LP1L A z L8E1! D L=1 C IE9 F PEAH Ht"p ~DH5b 1 AUuHpDLeEHH8d LALb 1:mL 1{AH HL$@IL Et$AtUIH DLIE Iu HP H' HtDp E LZMd$ 1HcLH?HHW$q H Hc H1Ҿ IH n H Dm Dx H Iƃp L0MEAADHcH IHH Dk$ALsD{ C(NL1HHHIHC0H8HCX`H D9L0~"1ېI| 1HHɛ 9 MtH LL1 H= RL= Ap L-;` 1LQHd D ~9L% E1f I<$DD H* AD; |ڋ H T EAH#) H5q HD1FRHߚ H5{ H ` HH HI1H RH H5z H ` HH HI1HQHm H5y H ` HH HI1HQH=^ PLPH@ H8hL= { @ Dp EDH5 1BQH ۙ L8A % 1LH`= H8E 1LLE~& @ A<1LH^CL=g A9 Ic I H<RE1HHH8Hff. @ HIH9HGH`H9uHSZ/D H HHH H1$H`HhH+PH+XIy HI@B Ap Ii ffHi ʚ;fH*H*I H*(X^80H fH*fH~Me fI*fA A* ^^8fI~! HH#\ HHEH 9 H 0HL] H ] H5\ OHv 8 z (HL\ H ] H5\ NH3 8 l HfInL\ H c] H5D\ N0H f(\(8 YL ^Y0 HL\ H \ H5[ 'NH ffHn* Hx 8 ^^8w HLA\ H F\ H5}[ MH1 fHn^88 HL'\ H [ H55[ MH ffHn* H 8 ^0Y8^ HL[ H [ H5Z MH ffHn* Hf 8 ^^8^0 HL[ H [ H5cZ LH fHn^0^88 HL[ H d[ H5Z ^LH p L8 E1ff. E1LeISZ/D fLZ LH -[ H5Y KHS@fH HIH0 H 8 H* LZ LH ` H5<Y KHSHfH HIH H 8 H* LZ LH _ H5X 5KHΓ I D9 AHfEA)D$L*Z % LA)$% ID$ HLH @1HH AU cXH* CPZ8 HY H5uX JAp H3 H8[L= H=:W sIL=쒀 MEp EH5'W 1 JL= H=BW (IL= M>Ep E.H5% 1IL=n A H5V 1IL=H I H(H5V D$ PD1dIYL5 ^MHL 1H5AV =I 1LL5̑ HC9$ÉXǃp IH H`9 t HpHx0Hl 9H`uHx HI HxhH=9 D HhA9 H`1HHBH`H+PHHhH+X| H H = Dp 8E fo`Hyh)PH ƀ Hxh Hw H +L=d (D 1D$H5T D8GL-. D8HH5wT L1 iG 1HL- M7(AA5 OUL=ȏ 9UL= A D9D)DH5ݙ 1 FL= D HQV H5T Ff D HV H5zT Ff D AD; WL8LH8aH8H:HtH H8Lc H 1IE~/ H[HHI HxTA9 LH HtK4dH8HhH8 HT1HW HUdH+%( # He[A\A]A^A_]ÿ LP H= DL= I Ap H^A H5R 1-EL=ƍ I H0H=mR H0DL= H0MAp RL=d H00 H H5zR DH 8 ( H H5ER ^DH 8 fInſ H_R H5R ,D)H5d 1DL= HS H5Q CHR H5Q CHR H5Q CH,R H5hQ CHQ H5FQ _CH H5$Q =CLAfHL H*f(XHfHH H*XfH~LH=WP BH H\p NH5 1B6I HIUA 1H5 H D{BH0 81:HHO HHEH 8 ut0LO H P H5O AH Iڿ H5 1AHs LHH@B u0 H]O H5tO A Hi ʚ;ff Hi H5 H*H* X^JAH ㉀ HDp E H=N >@H H K E1$AD9(wT D H5Q 1@`H= ?OH5P 1@7H0MdHMW|ff. UH-M HAWAVAUIH51 ATA SH(dH%( HE1.@E~4IcMH b Mt IH 1I?M9uH=G ?1 LH H1~ HH$ DH ]~ CRfCPH HCH CTHCH CeHCX1AE1Cl Clu31 HEdH+%( H(1[A\A]A^A_]H=) L-y Xff. fIEI} HE% LE1ff. ff. HMcAH8 uHU 1OtH5 M>I$ 1IH5 >M9uE1AAH=)F =1 HH E1LH H\~ H~ DfCPHC HCH% CRHCH CTCeHCXDclqu H}IŐ H L9 Lf D HH5 1E1 E1=2H5~ H=[~ df. f. f. f. f. f. UHSHdH %( H]HH5R G!u H HHEdH+%( uH]1 ff. f UHZR HATSH HL% dH%( HE1A4$6LA4$ H#R 16H{@sLHW~VHcHHDA4$H R 161VHUdH+%( uH[A\]f. HB5 D UHAVAUATISHcHdL,%( LmAHOH H9 HA 1ff. H Hx u A@ADOU I$L5r HN1EH:Q DCA6P15XZAtoE HEdH+%( ] A6HeHQ 1[1A\A]A^]e5 D M $L5 N11HP A675AuID$H xHHHHH HEdH+%( H HP H5P H8He1[A\A]A^]M* D HEdH+%( H HbP H5eP H8He1[A\A]A^] *f. HcHHD HEdH+%( u2HJ HO H5O H8 HcHLLfUfHAWAVAUIATSHh |GH_dH %( HMHO@GL)H HHAHHt5H8 t/H 1 H Hx ut L= A7D HHHHtlH9 tfHA 1 H Hx utEHc HLHN 1HD@12* HN 1HHL 12 HLHHHf. d L牝Dž9 nf t5H IH~.A?Ƅ H HH0 @ A> vLNJA?Au | H:D|DዕHnHEdH+%( : Hh [A\A]A^A_]fLLHLHf. 1A7HHHH@ LhIA?Au H :D|DዕH L=k~ HL 1D|HHA7L10 HLLnHH @ HHHHtfH9 t`HA 1 @ H Hx utCHc HLHK 1HD@1/(HK 1HHL 1/H~ HH0\H8D|H< HLLFE D UHAWAVEAUAATISH(dH%( HE1=} H P IIHH L`@H ~ DhHXL @@,W,~ZHGG,HHG87u= t I?D1HUdH+%( H([A\A]A^A_]ÃW, L=~ HI A7U.IT$~LHcHHDLA7H J E1 .MEDLd HB뺸Nff. UH V fHnH ، HAWIAVAUATL`SLH( H H5I fHndH%( HE1H@l HDžH HDž( HDž0 HH I H s H`H(fHnH'I flfHnH v h~ P~ HHi flHH F x~ P~ H Hp{ h~ fHnHH ~ P~ H@H p flHH*{ fHn(HH ~ _P~ HH S flHH fHnHы ~ )P~ H H w flH@H0fHnfHnHKH flfHnHWH Dž HfHn~ O~ HF Dž HDžX flXfoflfHnHV ~ ~ fHnH : ~^O~ HPfl 1H=1 H~ 11 H8$E1LLHPL@H ~I?H5g9 : L0MS =Py =By tѶ H2~ A 1fDH@d H(HHtHHGH E1E1HDII7A L6Mm HLE D I>I~9LHt1H? t+HO 1Hff. H Hx u IHDAGL4M AHi1 HUdH+%( ! H( [A\A]A^A_]H ~ LH;9 H ~ LH; H ~ LH;f H ~~ LH;L H ~ LH;2 H ~ LH; H`~ LHIE 101(f ɴ L 1҃H% HH HcL8L( )ЉMM D DM؉CE L E1HMK| L賲H8: ugH9~ ID9̐HHL<MsHHH5e H9f KtLHtff. L MH~ HC 101''IOHZH9 PHq 1H H Hx u)1 H H~ uE1HL HM식I:H5Q~ LED$1HH"C ILL61&M9t5IOHuH~ M1ED$HB I01K&M9uL Hs 1ff. H LcHy uLLoLAHLMLt(ff. @ H;A9DLH L9uDLOd, @ LIHv I9j L牝BHH HcH E1Dž DLL8L$I DL8IcHX D)M LDLff. DE ~CHL L8I> LjH8: H9q IM9uHHPH H: HJ 1 @ H Hy u LcH@ILE1ff. HW N|2 H H; L譮H8: uIHH9tUHL9uI L9t~HHPHuff. @ L8 H3L Ht I L9 Hƅ HPH=I L9!H@ f. HHqHX HHHHt/H9 t)Hq 1Hf H Hx u HcHDHH Dp% DHHHHHH^DIIH I9 HHcEHL, LHԷI9V=$ L#uDLfI6LUH; HL8HA~ D1H= 0HL1p!Ha~ H> H5 = H81 @ H,H1H H~ uE1LcHHcMLDH6 LHL|1 LMI~>H H; LpH8: uTHH9tXHL9uIL9 HDHHH HcMX H3LHtHcMHDHH ƋmIL9t-HDHHHcHHL>H1H SH`L0D' UHATSH H $ H H=; dH%( HE1Y@yV1 H=; B@y?L H; HHL1VH螴 L1?HUdH+%( u H [A\]off. @ UL+ HÓ HSHH~ dH %( HMHOH}HE H0; LE1F x&H}=H}t t HEdH+%( uH]û @ UHAWAVAUATSH H $ H H8IILdL$%( LeME3H Lx: SAH@ 1H0r;H0 LLI|Ƅ/ ZYH LHģH HH8謣H HCHX HC>IHtrH8I]LIE kH IEI$I>H4 H I$IL,HI$HEdH+%( ukHe[A\A]A^A_]H~ 1HP| 017 HEdH+%( u4HeH[A\A]A^A_]H~ HL| 101H~ H{ 101cHr~ H{ 101H萱L舱5 U1HAWAVAUAATSHh HL~ H5 HdH%( HUH蒨 HLc1IHׅ L4M A~. M~. LHHtH58 AF<t*uMH1LDX:% = @ u' LD1$HHHHI9M1f H<HHHI9u/HEdH+%( N Hh [A\A]A^A_]f. 1ɺ LD 11LDqAQH@ ljHH @#uvHH HHA:!uPLHIfHQ x- t<HH9u躀 LDH~ LL D`HLHcL HH9 HW?x#tL ~ LcC uӅA 8 A LLIHxLDtML"f D HW?H A| AH S HH9uǺ LDL ~ H LL DHHHHcHH DHHHHH,IcLLHxDtH#ff. f D HQA t HHu HcDƄ 聴HHHLHLDPHLL HxDtTɼf UHSH(dH%( HE1HE HE oy;HEH}H4 HtnHUH HUdH+%( uNH]ÉHuHUHEH}H4 誢Ht"HUHE؉H ^HEH~ H%v 101 % D UHHHGdH%( HUHH9Ju H@H9BuJ1HUdH+%( uQH\~ L 2 A 0H 2 H2 1H%~ L 2 A 0G UHHdH%( HE1G HH9u`x u_H H9tOxtH~ L !2 A 0H 2 H+2 1HUdH+%( u= 1 @ Hi~ L 2 A 0HQ~ L 1 A 0s UHHdH%( HEHH9u-} D @ f@9 H H9tRP8uH~ L 1 A 01H ;1 HD1 HEdH+%( uuɸ HEdH+%( u\{ Hy~ L I1 A 0Ha~ L F1 A 0 HA~ L 71 A 0b` UHHdH%( HEHu xuQHxub1HUdH+%( uiH~ L 0 A 0H B0 HP0 1H~ L 0 A 0H~ L (0 A 0貸f UHHdH%( HEH x Hx Hx HP( uY uPN H x& Hx Hx F HP( uk ubK 1: D H~ L / A 0H ,/ H:/ 1HUdH+%( f D Hy~ L / A 0Ha~ L / A 0HI~ L . A 0{H.~ L . A 0`H~ L / A 0EH~ L . A 0*H~ L D. A 0H~ L . A 0H~ L . A 0ƶH~ L . A H - H- 01 UHHdH%( HEHu[x Hx HxH HxP H Hx 1HUdH+%( H~ L y- Ai 0ff. fH *- H8- 1H~ L , Aj 0Hx~ L - Ak 0H`~ L - Al 0HH~ L - Am 0|H-~ L 4- As 0aH~ L ]- An 0F1 UHHdH%( HEHu5xufHx xDumHxPu~1HUdH+%( H~ L ?, Ay 0H + H , 1Hc~ L + Az 0HK~ L , A| 0H3~ L , A~ 0H~ L + A{ 0|:f. UHHdH%( HEHu5xufHx xDumHxPu~1HUdH+%( H~ L ?+ Aj 0H * H + 1 Hc~ L * Ak 0HK~ L + Am 0H3~ L + Ao 0H~ L * Al 0|:f. UHHdH%( HEHu5xufHx xDumHxPu~1HUdH+%( H~ L ?* A/ 0H ) H * 1 Hc~ L ) A0 0HK~ L * A3 0H3~ L * A5 0H~ L ) A2 0|:f. UHHdH%( HEH] Pujk D HuoHxH _ HxP t H P8 @ f@9 H Pt`HHtuHtHD~ L ( A 0ff. fH ( H( 1f @ Hx( Hx P8 ` @H f@9 H x Hx P85 @ f@9= 1ff. @ HUdH+%( HI~ L x( A 0 D H)~ L f( A 0 D H ~ L T( A 0 D H~ L ' A 0 D H~ L ' A 0 D H~ L ' A 0m D H~ L ' A 0MHn~ L ' A} 02HS~ L & A 0H8~ L ' A 0H ~ L & A 0H~ L ' A 0H~ L N& A 0L & A H~ H 1& H:& 01L & A L _& A L e& A L A& A L & A L & A {tL 2& A df UHHdH%( HEHu5xufHx xDumHxPu~1HUdH+%( H~ L o% A 0H -% H;% 1H~ L $ A! 0H{~ L % A$ 0Hc~ L % A& 0HK~ L $ A# 0|jf. UHHdH%( HEHu5xufHx xDumHxPu~1HUdH+%( H~ L o$ A 0H -$ H;$ 1H~ L # A 0H{~ L $ A 0Hc~ L $ A 0HK~ L # A 0|jf. UHHdH%( HEHu5xufHx xDumHxPu~1HUdH+%( H~ L o# A 0H -# H;# 1H~ L " A 0H{~ L # A 0Hc~ L # A 0HK~ L " A 0|jf. UHHdH%( HEHu5xufHx xDumHxPu~1HUdH+%( H~ L o" A 0H -" H;" 1H~ L ! A 0H{~ L " A 0Hc~ L " A 0HK~ L ! A 0|jf. UHHdH%( HEHu xuQHxub1HUdH+%( uiH~ L ! A 0H B! HP! 1H~ L ! A 0H~ L (! A 0販f UHHdH%( HEHu xuQHxub1HUdH+%( uiH/~ L A 0H H 1^H~ L _ A 0H~ L x A 0f UHHdH%( HEHH9u-} D @ f@9 H H9tRP8uHj~ L ' Ak 01H H HEdH+%( uuɸ HEdH+%( u\ H ~ L Al 0H~ L Am 0 D H~ L An 0b UHATSHdH %( H]H {$ DC E6 H{ H{H5 . H{$ { 1 H{ H{H5m t) H{$ s , H{ H{H5@ 9$ H{$ K ' H{ H{H5 U HS$, C H{ H{H5 4 H{$ { H{H5C L% H{Lx H{$ { H{H5 I H{L5 HUdH+%( H[A\]H~ L \ A 0ff. H H( 1H~ L 9 A 0Hh~ L A 0HP~ L A" 0H8~ L A' 0|H ~ L A+ 0aH~ L A0 0FH~ L A4 0+H~ L A= 0H~ L K AH 0H~ L @ AJ 0H{~ L AV 0H`~ L AX 0HE~ L A 0H*~ L A 0nH~ L A 0SH~ L A# 08H~ L A) 0 H~ L V A, 0H~ L M A2 0H~ L 2 A; 0Hm~ L A9 0HR~ L A5 0H7~ L A> 0{H ~ L AL 0`H~ L AM 0EH~ L AZ 0*H~ L c A[ 0f. UHSHdH %( H]H up{tH H5T C8 @ fC9ub 1HUdH+%( H]H~ L A 0H q H 1=H~ L A 0H~ L A 0H~ L w A 0H~ L L A 0|Ht~ L > A 0aHY~ L 0 A 0FH>~ L A 0+]ff. f UHAWAVE1AULmATSH8dL$%( LeL% M|$<HH LH1LjLH~ LHA AXZEuEL-HUI M9uHEdH+%( HeD[A\A]A^A_] L Q~ L1DEH[ A1LMLL=L赑HݠDELMA11LH DEHDEAEERL ~ A UHAWAVAUATSH H $ H H0H8dH%( HE1H I ILLi 1LLпHHD H̿H[ x.LpuA~ tހx.u A~.uA~ tff. H MLAVLY 1 GL_AXZEtH5y LH(HH_H@ HH xH L LЩH(Ƅ? ,LdL0LIRL8HIE _I>HtI} u#KH8H8<ff. E1HEdH+%( u7HeD[A\A]A^A_] @ H f D H(茫sfUHAUATSH(HGdH %( H]HHt Є IH LmLsHH3Lj1A E1LdZYu>LSL辎LHEdH+%( He[A\A]]f D H~ H A 12HW .H3LH5 L脯 D H~ H 1ۋ01oH~ H 101L蝜ff. fUI L HSHHHP dH%( HE1V HDž HZHHH@HUdH+%( uH]f D UHAUATH}SH(dH4%( HuHutALeLmLL.L贋L謋HEdH+%( uH([A\A]]û脛 @ UHSHdH%( HEGu#9wu^1HUdH+%( H] HFHHthHuH~ L e A 0 f. H~ L Y A 0H $ H2 1jH~ L A 0詚f UHAWAVAUATSHDgdH %( H]H¸ A9 e HE1L- L5 L Hk C8% @ C: fC9 H HH$ p 6 L#L L# AD$8- E @] AD$:o fAD$9 I$ HL A$p 2uv1HUdH+%( H[A\A]A^A_]f. H~ L n A 0f. H H 1 A迟A9xI $T D 裟 @ 蓟 Hf D H!~ L A 0u D H~ L A 0U D H~ L u A 05 D H~ L i A 0 D H~ L A 0 D H~ L < A 0 D Ha~ L - A 0 D HA~ L A 0 D H!~ L A 0u D H~ L A 0U D H~ L A 05 D H~ L U A 0 D H~ L I A 0 D H~ L w A 0 D Ha~ L A 0 D HA~ L A 0 D H!~ L A 0uH~ L A 0Z% D UHATSHDgdH %( H]H ¸ u-A9u2{ucH{ut1HUdH+%( u{H[A\]ÐۜHw~ L A 0H H 1H@~ L A 0H(~ L A 0Jf. UHAWAVAUATSHDgdH %( H]H2D@A9 H L;L9y E1E1L5 ff. AG [ A AG8 O @ AG: fAG9@ I L9K A Ap M f D I( + I ; AG8I \ @o AG:} fAG9 M M9 I L A A$ A9 Ep E` MM?L91g I AG8 @ AG: ? fAG9h LLt I A + Ap WH~ L l A( 0 Hm L AG8@ n @ AG: fAG9 M; Ap H~ L A7 0 H Z Hh 1&HUdH+%( H[A\A]A^A_] @1 AG: AG8Щ LLwt'I I A + uZAp H ~ L A 0"f A9 H~ L A 0HӸ~ L A 0H~ L , A 0H~ L # A 0H~ L ? A 0Hg~ L 7 A 0kHL~ L 1 A 0PH1~ L A 05H~ L A 0H~ L A 0H~ L A 0Hŷ~ L A 0H~ L A 0H~ L A 0Ht~ L A 0xHY~ L A 0]H>~ L A! 0BH#~ L A" 0'H~ L A0 0 H~ L A# 0HҶ~ L A1 0H~ L A2 0H~ L D A$ 0H~ L A3 0Hf~ L \ A% 0jHK~ L A4 0OH0~ L & A5 04H~ L A6 0H~ L A 0Hߵ~ L A 0Hĵ~ L A' 0H~ L A 0H~ L " A 0Hs~ L C A 0wHX~ L = A 0\H=~ L " A 0AH"~ L A 0&H~ L A 0 H~ L A 0HѴ~ L A 0H~ L ^ A 0H~ L A 0H~ L ( A 0He~ L A 0iHJ~ L # A 0Nif UHSHdH%( HE1 H" HH9uTHz( ufHz uHH9t;ztH³~ L ) Aj 0H % H3 1HUdH+%( u{H] Hq~ L Al 0 HQ~ L An 0H9~ L Af 0rH ~ L Ag 0W=ff. f UHHdH%( HE1 HH9u1 f D @ f@9 H H9tZP8tH~ L G AO 01H H HEdH+%( ɸ HEdH+%( u H!~ L AP 0 H~ L AQ 0r D H~ L AR 0RHƱ~ L k AL 07 D UHSHdH %( H]H uM { H{( ucH{ HUdH+%( H] H1~ L AY 0H H 1`H~ L n A\ 0H~ L I A[ 0Hʰ~ L P A^ 0H~ L AZ 0|ш UHATSHdL$%( LeL' A|$ I|$usHH5 L!k {I<$ HuzH5p j 1HUdH+%( H[A\] H~ L y A 0H D HR 1f H~ L 9 A 0H~ L . A 0Hq~ L A 0HY~ L A 0sH>~ L A 0XH#~ L f A 0=H~ L K A 0"' UHSHdH %( H]H {uSH5 Hi H;usH5 gi 1HUdH+%( H] @ Ha~ L AY 0H H 1f H!~ L A^ 0H ~ L AW 0H~ L 4 AZ 0H٭~ L A_ 0s UHHdH<%( H}H=8 {vHHUdH+%( u诅ff. @ UHHdH<%( H}H= +vHHUdH+%( u_ff. @ UHHdH<%( H}H=z7 uHt&HHEdH+%( u'H5gv ' HEdH+%( u1 UHAVAUATSHdH%( HE1GL 1IHH E1{ {tZHK~ L A 0H H 1zHUdH+%( H[A\A]A^] D E11ff. HHt)G;CuEuNA A HHuE HLFHH0EtC1if D Hy~ L A 0)H^~ L A 0HC~ L A 0H(~ L Az 0H ~ L A 0,ff. UHHdH%( HEHH9u-} D @ f@9 H H9tRP8uH~ L G A^ 01H H HEdH+%( uuɸ HEdH+%( u\ H)~ L A_ 0H~ L A` 0 D H~ L Aa 0b UHSHdH4%( Huw H1HB8 @ fB9 5 9uHHx C8 @| fC9a $ 1 HUdH+%( H] H~ L A 0f. H J HX 1 H~ L y A 0H~ L v A 0 Hq~ L g A 0 HQ~ L A 0e D H1~ L A 0EH~ L A 0*5L A H~ H [ Hd 01% L A L A L z A L X A L A D UHAWAVAUATSH H $ H H $ H E1dH%( HE1Dž LIH HDž I HDž RH L: IH HHSH19H HJAYAZ H"IH f D LH HXf. HDž H) 8HuHLLLM SL _AX= H5LY LIH HHH nHu H? H蝖HH mLHDž eH~ L Hg9 01LH D L舚LIH$HEdH+%( g He[A\A]A^A_] @ CmLLHDž ɊHMLS L 1L :HLL HY^ I>- HfHSIٺ Lf A6 LHqLHXZH'~ L H@8 01gD؉pH~ H]7 1012M D Hɣ~ IH7 L01y D H~ LH7 01DDDD HQ~ HH7 01L DžH~ Hٿ H6 01[H~ H H 016Džz D UH5 HSHdH %( H]HH?d]t HEdH+%( u[HH]d @ Ha~ L w A H H 01HEdH+%( u H]Qz UH5T6 HHH?dH%( HE1\t1HUdH+%( u9HС~ L A H 5 HC 01y UH5 HHH?dH%( HE1F\t1HUdH+%( u9HP~ L f A H H 01Sy UH5c HHH?dH%( HE1[t1HUdH+%( u9HР~ L A H 5 HC 01x UH5 HHH?dH%( HE1F[t1HUdH+%( u9HP~ L f A H H 01Sx UH5 HHH?dH%( HE1Zt1HUdH+%( u9HП~ L A H 5 HC 01w UHAWAVAUATSH(H}dH%( HE1CuH! HE1L- ff. fHؗH/ x.L`uA|$ t݀x.uA|$.uA|$ t LLEtH5m L2tH5g L tL蓬HEH H>IH fL8Htex.LpuA~ tx.u A~.uA~ tff. LL襺tLH5w 蒺LAӖHuLfH}]H赖Hff. H8HED9xubHEdH+%( H}H([A\A]A^A_]Hŝ~ L R A4 0H ( H6 1AH~ L @ AM H H 01HEdH+%( udH([A\A]A^A_]H:~ L A% 0pH ~ L A7 H H 01NU$u @ U1H LN1 HAVAUL-@1 ATLeSH L5~ dH%( HE1A6LGn1LLXu6LL褡HEdH+%( u5H [A\A]A^]f D A6ALH0 1[tff. UHAWE1AVL5 AUE1ATSH(L%~ dH %( H]H S} AHA t_A4$L 1DL HtLA4$ED1Hw0 DMAEEAHA uHEdH+%( uH(D[A\A]A^A_]}sff. f UHAWE1AVL5 AUE1ATSH(L%~ dH %( H]H s} AHAKt_A4$L 1DL)H!tLA4$ED1H/ DMAEEAHAKuHEdH+%( uH(D[A\A]A^A_]rff. fUHHdH%( HEGu$Gu]1HUdH+%( f D YHHtkH5 uH~ L t A 0 f Hљ~ L i A 0H 4 HB 1 kH~ L A 0qf UHAVAUATSHDgdH %( H]H蔣¸ A9G HTAl¸ D9: O HE1L-a L Hl C8& @ C: fC9 H; ) < p N L#L AD$8M e @} AD$: AD$8% = HL' I$ A$ + A$p uo1HUdH+%( H[A\A]A^] D H~ L ^ Aq 0f. H H 1 AvA9I $S D v @ vf D sv?f D H~ L Ar 0e D H~ L As 0E D H~ L U At 0% D H~ L I Au 0 D H~ L w Av 0 D Ha~ L - Aw 0 D HA~ L X Ax 0 D H!~ L Az 0 D H~ L A 0e D H~ L A 0E D H~ L A 0% D H~ L 5 A 0 D H~ L ) A 0 D Ha~ L W A 0 D HA~ L A 0 D H!~ L N A 0 D H~ L A 0eH~ L Ac 0JH˔~ L Ae 0/lf. UHAUATSH_dL$%( LeIǞ¸ 8 9- L I $I9" E1 f. u {b H, C8 @ C:" 5 fC9D H; R p _ HI9 CsH{W C8f y @ C: fC9 H H9 9 p X I\H~ L A 0H z H 1FHUdH+%( H[A\A]] C8 @ C: fC9 LH虤tH + uDp HP~ L ) A 04 @ qD f18H~ L G A 0H~ L A 0H~ L A 0Hɑ~ L ] A 0H~ L V A 0H~ L A 0wHx~ L D A 0\H]~ L 6 A 0AHB~ L A 0&H'~ L A 0 H ~ L A 0H~ L A 0H~ L j A 0H~ L c A 0H~ L A 0H~ L Q A 0iHj~ L A 0NHO~ L | A 03H4~ L A 0H~ L A 0H~ L A 0H~ L A 0Hȏ~ L A 0H~ L A A 0H~ L A 0vHw~ L A 0[H\~ L U A 0@{gff. UHAVAUATSHDgdH %( H]HT¸ A9 7A HD9 HE1L-W HV C8Z @ C: & C8% = 3 H E H H9U h 9 v p L#L L AD$8 @ AD$: AD$8% = HL I$ A$ + A$p 赗ui1HUdH+%( 5 H[A\A]A^] H9~ L AO 0fH H 1f AOlA9}I $3;l @ +lA lMf D H~ L y AP 0m D H~ L n AQ 0M D Hi~ L AS 0- D HI~ L AT 0 D H)~ L AU 0 D H ~ L AV 0 D H~ L AW 0 D Hɋ~ L AX 0 D H~ L AY 0m D H~ L b AZ 0M D Hi~ L & Ab 0- D HI~ L Ac 0 D H)~ L Ad 0 D H ~ L Af 0 D H~ L Ag 0 D HɊ~ L Ah 0 D H~ L u Ai 0m D H~ L Aj 0M D Hi~ L B Ak 0-HN~ L AA 0H3~ L , AC 0Rbf UHAVAUATSHDgdH %( H]H4¸ A9 HA ¸ A9z HE1L-R H2D C8 @ C: fC9 H 0 H H9@ S 9 a p s L#L L AD$8j @ AD$: fAD$9 HL諚 I$ A$ + A$p 蟒7 蒒E1 I $H C8 @ C:X 5 fC9 H H H9 j 9 = p L#HP LEG AD$8 @ AD$: fAD$9 HLP I$ A$ + TA G1ۄt Lf9~pM$$L AD$8 @- AD$: fAD$9 M;$ { ϐu1C @ Hq~ L . A 0f. H H 1薸HUdH+%( H[A\A]A^]ÐAgeA9I $k D Ke ;e' @ +eE1)tAeD9r @ H~ L q A 05 D H~ L f A 0 D Ha~ L A 0 D HA~ L A 0 D H!~ L A 0 D H~ L A 0 D H~ L A 0u D H~ L A 0U D H~ L A 05 D H~ L Z A 0 D Ha~ L A 0 D HA~ L A 0 D H!~ L A 0 D H~ L A 0 D H~ L A 0u D H~ L A 0U D H~ L m A 05 D H~ L A 0 D Ha~ L : A 0HF~ L Au 0H+~ L $ Aw 0H~ L A 0H~ L A 0Hڂ~ L A 0nH~ L g A 0SH~ L 8 A 08H~ L n A 0 Hn~ L A 0HS~ L j A 0H8~ L A 0H ~ L A 0H~ L A 0H~ L A 0{H́~ L A 0`H~ L A 0EH~ L A 0*H{~ L # A 0H`~ L A 0HE~ L A 0H*~ L W A 0IYL A H~ H o Hx 019L A L A L A L W A L 4 A L v A { UHAVAUATSHDgdH %( H]H蔊¸ A9? HTAl¸ D92 O HE1L- Ht C8. @ C: fC9 H ( H H98 K 9 Y L#L L AD$8P h @ AD$: fAD$9 HL I$ A$ + uq1HUdH+%( H[A\A]A^] H~~ L ^ A 0f. H H 1ư A]A9}I $W] @ ]f D {] Ef D H ~~ L A 0m D H}~ L A 0M D H}~ L ] A 0- D H}~ L Q A 0 D H}~ L A 0 D Hi}~ L $ A 0 D HI}~ L A 0 D H)}~ L @ A 0 D H }~ L 6 A 0m D H|~ L A 0M D H|~ L A 0- D H|~ L A 0 D H|~ L A 0 D Hi|~ L A 0 D HI|~ L ? A 0 D H)|~ L A 0 D H |~ L 6 A 0mH{~ L A 0RH{~ L A 07Sf UHAVAUATSHDgdH %( H]Hԅ¸ A9? H蔽A謅¸ D92 菅 HE1L- Ht C8. @ C: fC9 H ( H H98 K 9 Y L#L LN AD$8P h @ AD$: fAD$9 HLY I$ A$ + ]uq1HUdH+%( H[A\A]A^] Hy~ L A 0f. H : HH 1 AXA9}I $WX @ Xf D X Ef D HIy~ L A 0m D H)y~ L A 0M D H y~ L A 0- D Hx~ L A 0 D Hx~ L A 0 D Hx~ L d A 0 D Hx~ L U A 0 D Hix~ L A 0 D HIx~ L v A 0m D H)x~ L A# 0M D H x~ L A$ 0- D Hw~ L A% 0 D Hw~ L ] A& 0 D Hw~ L Q A' 0 D Hw~ L A( 0 D Hiw~ L 5 A) 0 D HIw~ L v A* 0mH.w~ L A 0RHw~ L A 072Of UHAVAUATSHDgdH %( H]H¸ A9? HԸA¸ D92 π HE1L-U Ht C8. @ C: fC9 H ( H H98 K 9 Y L#L L莲 AD$8P h @ AD$: fAD$9 HL虇 I$ A$ + uq1HUdH+%( H[A\A]A^] H!u~ L AA 0f. H z H 1F A/TA9}I $WT @ Tf D S Ef D Ht~ L Y AB 0m D Hit~ L N AC 0M D HIt~ L AD 0- D H)t~ L AE 0 D H t~ L AF 0 D Hs~ L AG 0 D Hs~ L AH 0 D Hs~ L AI 0 D Hs~ L AJ 0m D His~ L & AR 0M D HIs~ L AS 0- D H)s~ L AT 0 D H s~ L AU 0 D Hr~ L AV 0 D Hr~ L AW 0 D Hr~ L u AX 0 D Hr~ L AY 0mHnr~ L A3 0RHSr~ L L A5 07rJf UHAVAUATSHDgdH %( H]HT|¸ A9? HA,|¸ D92 | HE1L- HRt C8. @ C: fC9 H ( H H98 K 9 Y L#L Lέ AD$8P h @ AD$: fAD$9 HLق I$ A$ + zuq1HUdH+%( H[A\A]A^] Hap~ L Ap 0f. H Hȿ 1膢 AoOA9}I $W[O @ KOf D ;O Ef D Ho~ L Aq 0m D Ho~ L Ar 0M D Ho~ L As 0- D Hio~ L At 0 D HIo~ L ? Au 0 D H)o~ L Av 0 D H o~ L Aw 0 D Hn~ L Ax 0 D Hn~ L Ay 0m D Hn~ L f A 0M D Hn~ L Y A 0- D Hin~ L N A 0 D HIn~ L ݿ A 0 D H)n~ L ѿ A 0 D H n~ L A 0 D Hm~ L A 0 D Hm~ L A 0mHm~ L S Ab 0RHm~ L Ad 07Ef UHAWAVAUATSHDgdH %( H]Hw¸ K A9 uwE HE1L- L5 H C8 % @= C:Q i fC9} H HH~ p L#L L;] AD$8 @ AD$: fAD$9 HLF~ A$p . M$$L L躨 AD$8$ < @T AD$:f ~ fAD$9 I$ HL} A$p uum1HUdH+%( H[A\A]A^A_]ÐHQk~ L A 0f. H H 1v A_JA9I $ D CJ@ 3JVf D Hj~ L A 0u D Hj~ L A 0U D Hj~ L A 05 D Haj~ L A 0 D HAj~ L 7 A 0 D H!j~ L ܻ A 0 D Hj~ L ͻ A 0 D Hi~ L A 0 D Hi~ L ~ A 0u D Hi~ L q A 0U D Hi~ L f A 05 D Hai~ L A 0 D HAi~ L A 0 D H!i~ L A 0 D Hi~ L ͺ A 0 D Hh~ L A 0 D Hh~ L ~ A 0u D Hh~ L q A 0U D Hh~ L f A 05 D Hah~ L A 0 D HAh~ L A 0 D H!h~ L A 0 D Hh~ L A 0 D Hg~ L A 0 D Hg~ L A 0uHg~ L K A 0Z? D UHAVAUATSHDgdH %( H]Hq¸ A9 q HE1L% L- H H HHy EFu C8a HL H胣| C8 HL H^u[C8 pu'1HUdH+%( 3 H[A\A]A^] D AEA9}HH4 E@ {E느Hf~ L ̷ A 0H t H 1@Qf D He~ L A 0 He~ L { A$ 0 He~ L [ A, 0{Hve~ L @ A 0`H[e~ L A 0Ez=f. UHAVAUATSHDgdH %( H]HTo¸ A9 7o HE1L% L-Ŷ Hs H HHv Cu C8a HL H3| C8 HL Hu[C8 nu'1HUdH+%( 3 H[A\A]A^] D AgCA9}HH4 ;C@ +C느Hc~ L | AN 0H $ H2 1Qf D Hc~ L M AO 0 Hac~ L 8 AZ 0 HAc~ L Ab 0{H&c~ L AR 0`H c~ L AB 0E*;f. UHHdH%( HEHP8 @ f@9u5uhxuzHx 1HUdH+%( Hib~ L _ A 0fH ʱ Hر 1薔H0b~ L ձ A 0Hb~ L A 0H b~ L A 0Ha~ L A 0|Ha~ L A 0aHa~ L A 0F9 UHAUATSHdH%( HE1G 1I HHtkL-P* #f. {urHL߬HHt?{tk|HH~ LvuHa~ L A 09 1HUdH+%( uvH[A\A]] @ H`~ L a A 0H , H: 1H`~ L A 0Hz`~ L A 08ff. UHHdH%( HUHB8 tz@ fB9 t HEdH+%( c H_~ L Ȱ A9 01H R H[ HEdH+%( ujɸH_~ L { A6 0H_~ L P A5 0H{_~ L q A8 0Hc_~ L H A7 0m7f UHHdH%( HUHB8 J: @ fB9u"HEdH+%( 9f H^~ L A 01H " H+ HEdH+%( ɸHw^~ L ` A 0H_^~ L A 0HG^~ L A 0H/^~ L A 0iH^~ L ѭ A 0NH]~ L ޭ A 036 UHHdH%( HUHB8 J: @ fB9u"HEdH+%( f HQ]~ L G A 01H H 耏HEdH+%( ɸH]~ L A 0H\~ L A 0H\~ L A 0H\~ L A 0iH\~ L a A 0NH\~ L n A 034 UHAUATSH_dL$%( LeIf¸ 9 kf I $E1C8uu @ @ fC9 , 'fu+HEdH+%( F HL[A\A]] f D A:A9}HC8tH[~ L M A 01H H 迍HEdH+%( H[A\A]]f D :f D :Cf D H[~ L A 0| D HZ~ L ֪ A 0\ D HZ~ L Ǫ A 0< D HZ~ L { A 0 HZ~ L ; A 02 D UHHdH%( HEHH9ue D usH H9tSP:uH3Z~ L ǫ A 01H H bHEdH+%( u;ɸ @ HEdH+%( u!C HY~ L y A 01 UHHdH%( HEHH9ue D tsH H9tSP:tHsY~ L A 01H Ԩ Hݨ 袋HEdH+%( u;ɸ @ HEdH+%( u! HY~ L A 031 UHATSHDgdH %( H]Hc¸ A9# HH9u. @ f@9 H H9tZP8uHrX~ L / A{ 01H ӧ Hܧ 衊HEdH+%( H[A\]HEdH+%( HH[A\]m D S75f D HW~ L A| 0r D HW~ L A} 0R D HW~ L A~ 02HW~ L 3 Aw 0/ff. f UHSHdH %( H]H C8% @0 fC9 uM@, { H{( H{ HUdH+%( H] @ HV~ L n AY 0H , H: 1묐HV~ L AB 0HyV~ L A[ 0HaV~ L զ A\ 0HIV~ L Ϧ A^ 0{H.V~ L A@ 0`HV~ L Х A? 0EHU~ L ݥ AA 0*HU~ L ֧ AZ 0-ff. UHAUATSHWdH%( HE1{ 1I+HH L-s Ef D C H{ H{H H{P HL٠HHtA{tepHH LjuHT~ L A 0; D 1HUdH+%( H[A\A]]HT~ L Ȥ A 0H $ H2 1f HT~ L A 0 HaT~ L A 0 HAT~ L ٣ A 0{H&T~ L A 0`H T~ L A 0E*,f. UHSHdH %( H]HH?G8e B @p fG9tlH5 p {H x Hx M xD HxP 1HUdH+%( > H]f D H1S~ L ' A@ 0f. H H 1V HR~ L , AA 0HR~ L v A 0HR~ L A! 0HR~ L A$ 0uHR~ L A& 0ZHkR~ L ; A> 0?HPR~ L A= 0$H5R~ L A? 0 HR~ L A# 09*f UHSHdH %( H]HH?G8e B @p fG9tlH5 {H x Hx M xD HxP 1HUdH+%( > H]f D HAQ~ L 7 A3 0f. H H 1f HP~ L < A4 0HP~ L A 0HP~ L 0 A 0HP~ L A 0uHP~ L A 0ZH{P~ L K A1 0?H`P~ L A0 0$HEP~ L * A2 0 H*P~ L A 0I(f UHSHdH %( H]HH?G8e B @p fG9ulH5 {H x Hx M xD HxP 1HUdH+%( > H]f D HQO~ L G A& 0f. H H 1v H O~ L L A' 0HN~ L A 0HN~ L @ A 0HN~ L A 0uHN~ L A 0ZHN~ L [ A$ 0?HpN~ L - A# 0$HUN~ L : A% 0 H:N~ L ҝ A 0Y&f UHSHdH %( H]HH?G8e B @p fG9ulH5 {H x Hx M xD HxP 1HUdH+%( > H]f D HaM~ L W A 0f. H HȜ 1 HM~ L \ A 0HM~ L A 0HL~ L P A 0HL~ L * A 0uHL~ L A 0ZHL~ L k A 0?HL~ L = A 0$HeL~ L J A 0 HJL~ L A 0i$f UHSHdH %( H]HH?G8e B @p fG9tlH5 {H x Hx M xD HxP 1HUdH+%( > H]f D HqK~ L g A 0f. H ʚ Hؚ 1} H)K~ L l A 0HK~ L A 0HJ~ L ` A! 0HJ~ L : A$ 0uHJ~ L - A& 0ZHJ~ L { A 0?HJ~ L M A 0$HuJ~ L Z A 0 HZJ~ L A# 0y"f UHSHdH %( H]HH?G8e B @p fG9tlH5 {H x Hx M xD HxP 1HUdH+%( > H]f D HI~ L w A 0f. H ژ H 1{ H9I~ L | A 0H!I~ L Ƙ A 0H I~ L p A 0HH~ L J A 0uHH~ L = A 0ZHH~ L A 0?HH~ L ] A 0$HH~ L j A 0 HjH~ L A 0 f UHSHdH %( H]HH?G8e B @p fG9ulH5 {H x Hx M xD HxP 1HUdH+%( > H]f D HG~ L A 0f. H H 1y HIG~ L A 0H1G~ L ֖ A 0HG~ L A 0HG~ L Z A 0uHF~ L M A 0ZHF~ L A 0?HF~ L m A 0$HF~ L z A 0 HzF~ L A 0 f UHSHdH %( H]HH?G8e B @p fG9ulH50 {H x Hx M xD HxP 1HUdH+%( > H]f D HE~ L A 0f. H H 1w HYE~ L A 0HAE~ L A 0H)E~ L A 0HE~ L j A 0uHD~ L ] A 0ZHD~ L A 0?HD~ L } A 0$HD~ L A 0 HD~ L " A 0 f UHSHdH %( H]H {u4C C8 1HUdH+%( H] @ S_HH H5 XuHC~ L j A 0H J HX 1v HC~ L A A 0HC~ L N A 0HyC~ L A 0ff. UHSHdH %( H]H {u4C C8 1HUdH+%( H] @ C^HH H5 WuHB~ L Z A 0H : HH 1u HB~ L 1 A 0HB~ L Q A 0HiB~ L ד A 0ff. UHSHdH %( H]H {uDC H H56 N^ HUdH+%( H] D #]HH H5˙ VuHA~ L : A 0H H( 1s HyA~ L A 0HaA~ L w A 0HIA~ L A 0kff. UHSHdH %( H]H {uDC H H5; .] HUdH+%( H] D \HH H5 UuH@~ L A 0H H 1r HY@~ L A 0HA@~ L W A 0H)@~ L A 0Kff. UHHdH%( HEHP8& @/ f@9uM x Hx # xD HxP 1HUdH+%( fHq?~ L g A 0f. H ʎ H؎ 1qH0?~ L Վ A/ 0H?~ L A0 0H ?~ L Y A3 0H>~ L O A5 0|H>~ L A 0aH>~ L o A 0FH>~ L | A 0+H|>~ L A2 0ff. UHSHdH %( H]HH?G8e B @p fG9tlH5 {H x Hx M xD HxP 1HUdH+%( > H]f D H=~ L AM 0f. H H 1o HY=~ L AN 0HA=~ L A/ 0H)=~ L A0 0H=~ L j A3 0uH<~ L ] A5 0ZH<~ L AK 0?H<~ L } AJ 0$H<~ L AL 0 H<~ L " A2 0f UHSHdH %( H]HH?G8e B @p fG9tlH5L {H x Hx M xD HxP 1HUdH+%( > H]f D H;~ L A 0f. H H 1m Hi;~ L A 0HQ;~ L A/ 0H9;~ L A0 0H!;~ L z A3 0uH;~ L m A5 0ZH:~ L A 0?H:~ L A 0$H:~ L A 0 H:~ L 2 A2 0f. f. D UHATSH H $ HdH%( HE1HH& HH1: 1HL% :~ H A4$TlH|2HtpHE1Hy2Ht5x.HPuz tx.uz.uz tfHID2HuH.ID$HUdH+%( u=H [A\]A4$L 1A H H kHUH=H HAUATSH(foT dH%( HE1H-XXXXXX ) H u @ A^HH fDo H @ fDn fDn fngffffDn fp )uffnfofp fDnfEp fffEp fEp fEp ff. fAofDofDoHfDffDfoffDofAofAfAofAofDfAfAfDUfEfDofAs fAfDofAs fEffEfDfDfEfDofAs fEfDoAfpfDfrfDofArfAfDofDffrffoffDfEfDofAs fAfDofAs fEffEfDfDfEfAs fEfDoAfpfrfDofArfAfDofrfDffofafifofafifofffafoffAffAfDofs ffofs fDffDffDfEfDofAs fAfDofpfDfrfofrffofffrffofffAfDofs ffofs fDffDffDfEfAs fAfpfrfofrffrffofafifofafifafAfg@H9P @ HDmL- HH= @ LEDHEdH+%( uH(L[A\A]]DE1{ ff. UHAWAVAUATSH( dH %( H]1H LLIŹ HLLHL 1L%%LHHWS LHpy`H4~ L A 0H H 1fAHEdH+%( H( D[A\A]A^A_]fHHL=:~ I MwHL}IV1A LLHfAGI EIcV H9X II9t H3~ L g A 0; D AFfA9GuHIE1I9u @ DYDHI A L1 @ DA LHA @ HHLDH=? H1Jff. ff. ff. ff. ff. fHH? HA4 HHHHHH)H9tH2~ L 5 A 0 H2~ L A 0Hv2~ L A 0f. AuRLD{HqHvLDH2~ L e A 0nA vH1~ L 2 A| 0H H1~ L _ A H HA 01c( UHAWAVAUATLSH8 dH %( H]1HIH LHHH H)1~ 2 B H H ATcHcL H0AƅR LALA -C 18 !IH HL4O LoA9 3HHuHl0~ L 6 A 0L% H 1LHbLHڿ H+0~ L 0 A 01mbAHEdH+%( H8 D[A\A]A^A_] H/~ L A 0h D H/~ L A 0H D E}E1HHJ Hky:Hs/~ L A 0H H~ 1a0 D H߉:tAuIEA9~MIyf H1HMHA 5H tH.~ L A 0hEMHH X McHJ HjAŅy H.~ L A& 0E1HtEtHH E1u8f HDH HA64H D; rLirL H\ HH-~ IL01(`I9L N A1 H-~ H ׇ H.} 01_}f. H-~ L 2 A 0 L A) L A" fU1HAVAUL- ATSLHdH%( HE1迀Aąu0HcDHEdH+%( usHH[A\A]A^]f D 1L1|AƃuHcDI L11TAŃuHcD! {@Hf D UHAWAVL5 AUATSH( dH%( HE1H1LH11LA11LA11LA1Hc؉|DtDlDL]H LHHH H+~ 2 H AH ]L H.+ LA L'HH IHn HLIÅy LajAuH(HH8HfHAy`H*~ L A` 0H HBz 1 ]HEdH+%( H( [A\A]A^A_] @ {EtH(HHxHXfHA H7*~ L S Ad 0a H*~ L A 0L%. H y 1LHB\LHڿ H)~ L ݄ A[ 01\ D H)~ L A 0 H)~ L A 0s D {E,1L1}Aą H(HHxH=eHAyH )~ L < Ao 0JEtH(H8 E HHdHAyH(~ L ߃ Ay 0EtH(H@ DE1 0t-H(N$ILy.I$ ,D;0rLlL H IH!(~ ML01jZM9fL A H'~ H Hpw 011Z, @ H'~ L z AX 0L A H'~ L S Au 0H'~ L Ak 0 UHAWAVAUATSH H $ H( LdH%( HE1=? u%1HUdH+%( He[A\A]A^A_]ÐH IAQH wL HEPL 1.wH H5݂ HaIH%AM MEHE1H n 1EH L HvL HHcgHɁ H1 ELR |vL HHcIgH H1D L 8vL HHcgHE H1D L߁ uL HHcfH H1L L uL HHc}fHEM 1 HLq ouL HHc<fH|EM 1 HL, .uL HHceH;MM 1 HL tL HHceHMM 1 HL tL HHcyeHMM 1 HL ktL HHc8eHxMM 1 HLR *tL HHcdH7EM( H1 L" AsL H߾ dH~EM( H1 L AAsL H߾ ddH~EM( H1 L AAMsL H߾ dHX~EM( H1 Lg AAsL H߾ cH ~EM( H1 L) AArL H߾ cH}EM( H1 L~ AAirL H߾ 4cHt}EM( H1 L~ AA rL H߾ bH(}EM( H1 Lx~ AAqL H߾ bH|EM) H1 L=~ AqL H߾ TbH|EM) H1 L} AA>qL H߾ bHI|EM) H1 L} AApL H߾ aH{EM) H1 Ly} AApL H߾ qaH{EM) H1 L>} AAZpL H߾ %aHe{EM) H1 L} AApL H߾ `H{EM) H1 L| AAoL H߾ `HzEM( 1 HL| AAwoL H߾ B`HzEM* H1 LH| AA,oL H߾ _H7zEM* H1 L | AAnL H߾ _HyEM* H1 L{ AAnL H߾ __HyEM* H1 L{ AAHnL H߾ _HSyEM* H1 L\{ AAmL H߾ ^HyEM* H1 L-{ AAmL H߾ {^HxEM* H1 Lz AAdmL H߾ /^HoxEM+ H1 Lz A mL H߾ ]H'xEM+ H1 Lz AAlL H߾ ]HwEM+ H1 LGz AAlL H߾ O]HwEM+ H1 Lz AA8lL H߾ ]HCwEM+ H1 Ly AAkL H߾ \HvEM0 1 HLy kL HHcw\HvEM4 1 HLhy ikL HHc6\HvvMM8 1 HL3y (kL HHc[H5vMM@ 1 HL y jL HHc[HuMMH 1 HLx jL HHcs[HuMMP 1 HLx ejL HHc2[HruEMX 1 HL{x $jL HHcZH1uL_e D UHAVAUATSL$ H H $ L9uH dH%( HE1 L0H x LH + >)HH LпI 1Lw LHiLЯ1 L w Lw L iHLL' ? LL , Hm~ LMMDžɯ-vvvH 0 Dž̯vvv H߸ 9N HɯRH P1HjZYHUdH+%( He[A\A]A^]f D H~ 0 IHLL v Džп-vvvDžӿvvv L 9N HпRH P1dLli^_cHa~ H:v 01I @ 8.g UHHdH<%( H}H=-v {'HH! H~ HEdH+%( u UHAWAVEAUAATASH8H}dL<%( L}MWLDIu$EHEdH+%( u`H8[A\A]A^A_] H}MEDDD]HELUD]tH>~ 1Hiu 01H zU D UHHdH%( HEH~ 8 uHEdH+%( u f. = u f UHAWAVIAUATSH(H L'dL<%( L}ILox4 uHH@ILH)I)II` LHHtx6 t1HHEdH+%( He1[A\A]A^A_] D L9 uA Mf L ~ t~HIċ A21LUIHȰ 1MFMNAT'GLCXLUZM9t A2H Ht 1LK1FLUA2LH 11FC6: A2H 11LUFAƇ LUZff. UHAWAVAULATSH S HH( dL$%( LeLL6 HL& LHP,L H5 L H8LH, HXLHE HEH |~ Dž H@ Lx8M HHLLff. fMwMo M9 HEx4 u HH+PIIH01L8IHt!HH@y4 uHH+AL9 H8L9pt7I_-L%t} H5.r D It$IH H.uLB@IHFHHLL~FLH5 HE n%LHE H5}X%H0LE H5 >%LLHEdH+%( He[A\A]A^A_]f D L%r} L-zW Ml$IMt"LHLH4u HL-q L%7r} LM A @ LD)xLH-Mt$IMuLL%q} H5p It$IH> H^HtZ @ LI_-It$-HxT HID$ y4 uHH+ALH)HHHHH5Ȃ 6H9HMIؿ HH 1PL1BZLY>IHH01HIH3 HH@y4 HH+AL9)HML$-0ILH 1 7BL=IHHf D CEg*H AEB<AtSHILH 01ALDž(=IH,L9yKH5o H+tH5o Hw+tH5o Hd+pH5o HM+YfLHML$-0H~ H 101 ADžH~ HHn 01@DžuH~ H 01@Hf~ H 101@ D UHATSHdH%( HE16 u! HIt-H^~ HH0;HEdH+%( u0H1[A\]ÐH ~ Hm 101'@AƄ$ UHATISHHG dH %( H]HH tH H` Ht*@6H HEdH+%( uQH1[A\] @ tH~ LH0] H ~ H9m 101_?ƃ 1 UHAVAUATSH H $ H H $ H dH%( HE1T H L%b H En 1LHI5IH= E LHǻo 6L%n 111Lu111L1 I H@Hx tPHx tIL@(IouI1LLKL3HEdH+%( HĐ [A\A]A^]H% H ~ o H 01=7A HP8H HHQ ~ 01=XH< ~ Hm 01=@HM 8LLQH ~ LH5 018=H ~ Hil 01= UHAWAVAUATSH H $ H H $ H8 dH %( H]1|RHH f IHe HH1ҹ L%` H k HHL H!3HH= g HHL 1Lo 5LL-ok A @ HD9C9 A McI w D LHHHH H1 E1 1L11AA9uI w D IHHHJ!HsZA2fH~ D Hj 01; LE11LKL1LI$ DMAd @ Hx HHLL(HCoI9t,HI~ KoEH, 01:DžAt$LHALA79~?A 11DL,; I H@H;X\H% DH'H蠸HLgHHEdH+%( c H8! D[A\A]A^A_]=H@ L8A~D H IH ~ 01l9`< H@A89H HH~ 01*9*H~ Hh A019H~ Hdh A0182<LMHً8 LAPMHQ~ LH 018H-~ Hg A01j8@ U HAWAVLAULATSH dH%( HE1HH HH HH H8ҿHc 1IH5{[ H=0g .IH= HLb LLHÅ 1LLKMI|$(1ULUÅ LÅ$ LY H5f 1 Dž Dž E1Dž AD$0b M$ ML I A9D$0ʋ9 uHD~ H 5 Hf 016LHEdH+%( H [A\A]A^A_]ÐLXHt!8 t.L/"L7HuL6 D LHLL-Å H LLo%= THu~ A1A H [ 2Hݡ 5# HA~ H 2 He 01}5 8H@ 8HHje HH~ 0195 @ 8H@ 8H!E HH~ 014t @ H~ ٿ H e 014M D Hi~ H P Hd 014 LH'~ H HDd 01^44f. f. UHcf HAWAVAUATSHHH dH%( HE1HE )E)EHHH H11IQHIHHz 1LHo 1H-AŅ" 11HH @(s P H 1D h @0f HE11HHH9H} L5 ~ D A6 Hc 12H11HLU @ D AG EuH11HLAHMA61LHc L)2AW f AH.c 1HH} 01E2H KHuL-HEdH+%( + H D[A\A]A^A_] D H H} H 1A011HRAHtb 1HHV} 011cH>} HW 1011A @ H} H 101_1H} H? 101D1H} L a A 0H a HTN 11AH} L pa A 0f. UHHdH%( HE1HEdH+%( u1nf UHHdH%( HE1HEdH+%( u ɿ +Ff D UHda fHnH}6 HAWAVAUATSHH ~}_} dH %( H]1HHx ~ fl)~~ H '~ )EHHG IH LHع 1LHLHH= 1L⾀ c1L⾀ T 7HH[ HHLE1L HHHL+` @ L @ N `1M 1LH=D^ %IH= ) @@ 1HPLHeHLLS BDŽ% /HHHcHi H )ȉ))ʃB%II HHDž $ HHD4Et6LE1AtAA At AAAE9uHHHuL LLyRh> ) LHADž< HHHE Hc L烄PLXHHuLL#L9u= ff. ff. ff. f. M$$L9 Ic$ DD;tLQE H" IIc$ HQ} 01,AHdH HI / H@8P1LHsIؿ H H} 012,ALHHEdH+%( HH D[A\A]A^A_]H} H[ 01+fHq} H{[ A01+ @ HI} L H\ A01+IE1H\ HH} 01H+H} DHb[ 101'+H} H H8 01*ZU.H@ 8IA $ Hߗ IHm} 01*.H@ 8Hp HH1} 01*H } HY A01Y*</f. D UH fHnHAWAVAUATSHHHX ~]Y} dL$%( LeE1fl)LHƅH HDž< $fo HHDž ILH)M HL:Aą? HE11HLAąM M' A LL L E1H1L3HPE $ D S,8JRA =RA HLHH DtDž1E HH?HH2Hs!; HHHH!H HH= u^ A Hھ *J LZFÅ <Lr L MJL5ƅ L-} Dž ƅ ƅ ƅ ƅ HDž At$0[ E1MLHL)HI HH LDH^HH D#DHAw DHHL=Au o ~2D(H11HX &H} 1HHeHHHH9 D(DE9t"Au 1AHHϔ r&DE E9t)Au 1AHHʔ =&E DE9t"Au 1AHHŔ &A . Ls.A 9Ct"Au 1AHHW % Ls*C 9Ct"Au 1AHHW %A H? DHcH>f[IHH } Hu 01C%? D H} H:u 0 1%L|A HUdH+%( HX [A\A]A^A_] Au DH 1 A$HHH9 HH/ H IH# uHxH5 J uI|$H5V ' u I|$ H5iV O GAD$l * @ H{H5^ Au 1AHHU #f H( D F 0 = &H@ 8(HA3 HH} 01#Lf. K&H@ 8Hѐ HHj} 01"L! @ IAu I HH 1A"HHHDLú IE9w0M 4Au H~T 1M "f H} HS 0 C%H@ 8HS HHb} 01!L1f$H@ 8x HQ HH} 01i!LVO H5S H$ tf D u%Au H HA 1 u. u%Au H b H2 1 Lu1 aAD$dfAu HU 19 ?Au H2 1 SAu H F H` 1 CAu H *R H6 1 Au H R H 1 ~Hy} 1HHAu HCQ 1] LF? f. @ UHAWAVL5 AUE1ATSH dL$%( LeL%z} ID$PH8ff. 軦HH I4$H3 L;L9t I4$L$ M?L9uHIL98uD0L%I} E1L5т ID$PH8ff. +HHO I4$H L;L9t I4$L蔦 M?L9uHlIL98uE Dž4 L@Dž8 E1틽8DZ* AAu88uˋ4c HEdH+%( 0HĨ [A\A]A^A_] D LM,$̰L HH} MA01( M?L9 LM,$脰L HH} MA01 M?L9$; 裤E1HHtw8DLDA LH; L3L9t LLtaM6L9uHAGA )HHuH} HN 01% Dž0f D L舯M Hc HH} 01M6Dž4L9Pb Hi} I $A 1A2H$| HfH1} I $A 1A2H{ gH^f. H} L H 011H @ H} HM 01Dž0} D H} HkM 01Dž0UHAWAVAAUIATISHdL<%( L}A豯H H@8uEu21DK,E9u_HUdH+%( He[A\A]A^A_] D HE1M H} I HL 0j1Y^H} HMI HL 0AV1XZiHy} MI HvL 01苿ff. U1H5g HAVL5 AULATSHdH %( HMع 3IH= 1ɺ HǻH5-L y LH5$F A]m L AH5K 6L H5K AEL H5K AE1L H5K AE LH5K AELAE 1LH5K )IH= 1ɺ H5k Ht LH5k AEU LH5%K AE6L H5K AELAEٯHEdH+%( uHH[A\A]A^] Af D H9} L HSJ 01tMf. U HAWAVAUATSHdH4%( HuȾ H PHÉ HpB ѿ fnHfn fo Hfnfp fp Hfp f. fofofoH@fffo@ ffpUf~Hff~`fofjfpf~@f~HfpUf~Hfofjfpf~`f~Hf~@@ @ @ @ @ @ @ H9OЃ HcȉH)LA8= AxD@D9 ALLE)D@AyED9~vALLE)D@AyED9~[ALLE)D@AyED9~@ALL E)D@AyED9~%ALL(E)AyE9~ HL0)y11Ҿ H5DCA97 @Hs ʿ fnHfn fo Hfnfp fp Hfp fofofoH@fffo@ ffpUf~Hff~`fofjfpf~@f~HfpUf~Hfofjfpf~`f~Hf~@@ @ @ @ @ @ @ H9Oȃ HcЉH)LA8= AxD@D9 ALLE)D@AyED9~vALLE)D@AyED9~[ALLE)D@AyED9~@ALL E)D@AyED9~%ALL(E)AyE9~ HT0) z 11H3L-} DCAAu DHKE A@ D¿ fAnHfn fo Hfnfp fp Hfp fofofoH@fffo@ ffpUf~Hff~`fofjfpf~@f~HfpUf~Hfofjfpf~`f~Hf~@@ @ @ @ @ @ @ H9ODA HcDH)L A9= AyDHE9 ELTE)DHAzEE9~yELTE)DHAzEE9~^ELTE)DHAzEE9~CELT E)DHAzEE9~(ELT(E)AzEA9~HT0A)Dz He 1fy 5EE E~2H } H D HD L01L襱LHz 11H0Au Aƅ~6H} H RD H@D L81LWLH,Au A SH{ B= A fnHfAnA fo HfAnfp fp Hfp fofofoH@fffo@ ffpUf~Hff~`fofjfpf~@f~HfpUf~Hfofjfpf~`f~Hf~@@ @ @ @ @ @ @ H9OЃ HcAHA)L ED" EADHD9 ALTE)DHEBED9~wALTE)DHEBED9~\ALTE)DHEBEA9}AALT E)DHEBED9~&ALT(E)EBE9~ HL0)DA fG1fW H0 AM ~2H} H A HA L01LLH 11H#.Au Aƅ~6H9} H A HA L81LLHAu AtlDH 1 @ H} H~ 01 AHFHEdH+%( HD[A\A]A^A_]ÐH& 1 DH~ 1r 뜉HG~ 1[ 1Q1:151H} H@ A01 P U HAUATSHdH4%( Huؾ sHR 1ɺ HHs HC8 fx` 1ɺ H4L%%} A4$A HCDHA fx ~2H6} H ? H? L(1L辬LH# 1ɺ H诨A4$& HCx# fx+ ~2H} H V? H-? L(1LDLHX 1ɺ H5A4$K HCxX fx P ~:HB} H > H> L(1LʫLHHCA4$8% fx1 DHA: fx H x#X fxg xX fx l AX QA j HA} A A 2jPH| 1p XZAHHEdH+%( HeD[A\A]] H} HA E1 0jH| 1 XZ @ DHHE1 H} 0j H)| 1 ^_] A A H]} H{ 01 (f D jA A P HA A j9 @ HA jUf. A A 1 H{ jA A# PdHDHA j#A A# 1 Hz 6HA# A jmH)} H; A01fjA AX PHDHA jXIA AX 1 Hz HAX A jHDHE1 jA AUE1 jA AT j肭A ASA jmA ARA j#A AQ A# j9H 1E1>A AP A jX:f. D UHAWAVAUATL%: SH LHH dH%( HE1L HDž L-: HL L-v HLj* L=: H: HLH B2 L-: HL(D H5s: HY LHv L-: HL L5: HL H: LHH H5: H H5S: H{ LHh LHU LHB" H{: H5~: HH ) H5u: HB H5?: H[ LHx LH LH HM: H59 HH H5D: Hz H5: Hc LHP LH= LH*2 H1: LHH i L=.: HL# H59 Hd LH LH LH L%1: H : HLH w L%: HL] L% : HLC L%: HL) L%: HL L%9 HL 1HUdH+%( ( He[A\A]A^A_]f LHHv} L 6 A 2jPf H6 H 6 1XZ D LH]H } L 6 A 2j P LH-H} L k6 A 2j P| @ LHH} L ^6 A 2j PLLHH} L I6 A 2jP H56 HHb} L %6 A 2jPLHuH6} L 6 A 2jPLHIH } L 5 A 2jPLH H} L 5 A 2j PlLHH} L 5 A 2j P@H55 HH} L 5 A 2jPH5i5 HHR} L 5 A 2jPLHeH&} L q5 A 2jPLH9H} L T5 A 2jPLH H} L 85 A 2j P\H575 HH} L *5 A 2j P,H5 5 HHn} L 5 A 2jPH54 H}H>} L 4 A 2jPLHQH} L 4 A 2jPLH%H} L 4 A 2j PtLHH} L 4 A 2j PHH5#4 HH} L m4 A 2j PH5c4 HHZ} L W4 A 2jPH54 HiH*} L 64 A 2jPLH=H} L 4 A 2jPLHH} L 3 A 2j P`LHH} L 3 A 2j P4LHHz} L 3 A 2jPLHHN} L 3 A 2j PH5{3 H]H } L 3 A 2jPLH1H} L 3 A 2j PLHH} L k3 A 2j PTLHH} L Q3 A 2j P(LHHn} L E3 A 2jPLHHB} L )3 A 2j PLHUH} L 3 A 2jPLH)H} L 2 A 2j PxLHH} L 2 A 2jPLLHH} L 2 A 2j P 諡ff. UHAWAVAUATSHdH %( H]H S HHB L%c2 LL L-N2 LLșADž LH貙~ HL蟙 H52 L舙 H52 Lq H *} L )f LLE HL9 LcL+LL xHK} L m A 0H x. H 1zAHEdH+%( HeD[A\A]A^A_] H} L Zm A 0H )} Lsx LL腘~:HL9tLcL+LLfxH} L $m A 0CHx} L 1m A 0(H]} MA 0LL H;} MA 2j PHu- H b- 1kXZLLɗH} MA 2j PHH觗H} IA 2j PH} MA 0uH} MA 0^H} MA 0G趞f D UHATSHdH %( H]H P HuH H z/ H\H H f/ HCH H B(} L f HL9tgH;H tH} L ./ A 0H , HK 1 HUdH+%( H[A\] H 9'} L fH;蘎H uHL9u1 D HQ} L . A 0rH6} IA 0[H } IA 0DH} IA 0-+ff. UHAWAVAUATSH H $ HXdH%( HE1 HH HI 1L HHIH Dž LH? x.LhuA} tހx.uA}.uA} tf. HLH1AU Li M `HxY^xHM HAULi 1 H'IXZM LfLHI x.LpuA~ tހx.uA~.uA~ tf. LM襦ƅ Lƅ HHLI9tE4$H Ipt0 ugHII9uE D t u2 uAF<vA_tff. fLH1LxHi} 2 11MLHi LDžϺHLLWL诺Hf D L8HEdH+%( uTHe[A\A]A^A_] @ LH.h 1 :H} HC+ 101DžЙH} Hٿ Hg 01 Hm} HH+ 101ff. UHAWAVAUATSH H $ H H $ H H* H+ ~9$} fHnH* fHnH* flfHnH* fHnH* fHnH* dH %( H]H) fHn~#} H~g flfHnH* )0fHn~#} H* fHn1fl)@~#} fl)P~#} fl)`~#} fl)p~#} fl)~u#} fl)~j#} fl)ʿHrH H1jAą H5a* $ A D1H5J* YAŅ^ Ǻ H5?* KDH^ َ H5"* DL L ff. @ M.1H) L L A LD1AŅ IvHH'HDHH DI M9w H5) D3 A D1H5f 0AŅ5 Ǻa H5f "DH` 谍H5( D1IH D荍O L5} 1H1He LA6,1Hپ Ho( L製 LuH% D A6LH( 11 L5q} Hd 11A6L1Hپ H' L&yA6HH-f 11E1y @ L5} Hrd 11A6V @ {L5} 11Hqd A61v @ Hɼ} H^' 101 E1HEdH+%( : H L[A\A]A^A_]ÐL5} H*d 11A6 L5\} 11H)e A6 @ L59} HZd 11A6~f L5} L11Hc A6Sf D L5} L11Hc A6+pf D L5} 1L1H& A6D+@A6HHd 11L5|} H& 11A6藓 UHAVAUATSH H $ H H $ H dL,%( LmE1LLH L HL訌1H5d L'w H0LE1LH HH蜇AŅq H8H# H9 HhHE @ H9] HpH H9 LL聿1L H$ L9 L u|H H Hfo; HBH xHEdH+%( H D[A\A]A^]fH} H"% 1A01L @ H} LH$ 101c Hq} H% 101fHQ} Hb 101fH1} H$ 101wfH} Hb 101WAH} LHa 101+ UHAWAVAUATSH H $ H H $ H8dL<%( L}LL7H4 HrIHz LLkH1E1j A LLH5# XAXZEj H# I$HHH9uKHE @ HHHH9 HHPH H9t:Hڷ} Ha 101 f D H} HM# 101L7LLX1L H+" L_8 L_ u[H H Hfo HBH 迟HEdH+%( HeD[A\A]A^A_]f. H} LHN" 101DfH} H 1AL01 D H} EH `" HxI 01H5D" LwH5 L<DE @ HY} H_ 101A H0} LH&_ 101sIf UHATSLeH Z LHHdH%( HE1E 蕇LH蚸EHUdH+%( u H[A\]֍f D UfHAWE1AVAUATSHhdH%( HE1H )E)E)E HO} IIIHOH % 01AE [oHH H=-E HEH H1H9HELHIT$HHENADž IL$Mu6y1 Mu'y2E Muy3uy H} H$ 01H}{HH}*HHEdH+%( HhD[A\A]A^A_] D 1H1|ADžtEIL${ y BH} Am H] 01-E1a D HL3L9ttA D I H5}# LH@0L8cnuM6IL9uHHxH9t-HxH}1HuuHxH HxH9uIL$ H.} H# A 01pIL$f D H=} LIM6L9Ai @ Lx(Lp(M9zID$HpIHptM?M9uMf. 1LH} H" 0 Am D y `HAq UHATSHdH<%( H}H=@" H5M" H=N" Hb~E H Ht}Le1H HL%kt!HUdH+%( uYH[A\]f 1LH HjuNjMtH} A H[ 101蔉 @ UHSH HHdH4%( Hu1tHUdH+%( u(H] @ HEdH+%( uHH]1ʳ% D UIHH/! HAWAVAUATSHhHx HudH%( HEH} 01H @H}1HHB+ H A E1Hq H} HAN$Mt8 I<$EAPifHA*HMd$MuH Hq II9rH% HEH]E1LuHEHQN,MT L}" L;}tCLZyMmM LM} \HuL IgA $tiIH LhIH @ H=Ht /Hx@ HuHL} 1Lj A LL7L=wLŇLxXZ)H]H} Hn 1A01 HxHEdH+%( a HeD[A\A]A^A_] HEL}HHq II9H]HUHL} HA E1HP HtULuHHN,Mt7 I} EA@gfHA*HMmMuHHP II9rLuHUHLu"E1Lu[LH]_wH} Lx1HY 0L1H5a LtH5b LEHl} H 01AH@} H 101 @ UHHdH4%( HuHw Ht HEdH+%( u"H D HEdH+%( u1 UHAUATL%v SHdH %( H]H 4} Lk(H3LuiHL9uH q 1H7~t#HUdH+%( uCH[A\A]]f HEdH+%( u HH1[A\A]] D Lff. UHHdH%( HE1HEdH+%( uHwH UHAWAVHAUfHnATS1H dH%( HUH fHnfl)HHH Dž L#HC8H9C8 H5 H= wIH IH H@8LfHnIGHfHnflIGxAO8flfHnI AGHfHnflflAOxA cAG LLIMoX襭E11L6 H LfAGpr4 H ~ L-~ L`H f D o LLIfoH s ) o@H )o@ ) o@0)0o@@L0)@o@P)`)PfIE H HoLG H} H 0; HhT 1HHHHH`fHnfHnL5~ flHM)IƐIBMMbMjIBH5b H=c IBIB@fHnMRflLAB@Dž OuHH LLIB LR~ LfAB8eL=LII I H@ HE1f D HAH9 uE9$ LL;f H`H r LL_ HSHH~ ofoL)`oB))poB )EoB0)EoB@)EoBP)EL}LmH} MMLHR 01 Hw @ Hi} L HP 01 @ L%A} HQ 1A4$H A4$HQ 1 h HUdH+%( H [A\A]A^A_]f D LX H} LL`HHR 01 LLDE9 I Hĕ~ L9+1YHP 1<tE1H6} L H'Q 01vL%} D L舎L%} H} L HQ 01-~ UHAWAVAUIATSH(L'HdH %( H]HLvM $L8LL t`Mu:Mt:Hv} MLHQ 01 f D MuMuLLLMwLMuLC ML$LL tWMu)Mt)H} L HVQ 01E MuMuLLLMLELELMuLC(ML$PLL t_Mu1Mt1H} L H&Q 01( MuMuLLLMLELELMuML$ LC8LL t_Mu1Mt1H-} L HP 01m MuMuLLLMLE3LELMuML$HLCHLL t_Mu1Mt1H} L HP 01H MuMuLLLMLEÿLELMuH[@Md$0HL teMu9HuHMt4HH} MILHxP 01 D HtLHXtH5+ HEuIEMHٿ H[P H٢} 01(1HUdH+%( uH([A\A]A^A_]z UHAWAVAUATISHL7L.dH %( H]HLL tgMuIMtIHe} MMLHO 01ff. @ f D MuMuLL[uM|$LkLL tOMu1Mt1H} MMLHO 01' D MuMuLLuM|$LkLL tOMu1Mt1H} MMLHO 012fMuMuLL蛽uM|$LkLL tOMu1Mt1H-} MMLHuO 01gfMuMuLL;uM|$ Lk LL tOMu1Mt1H͠} MMLHEO 01rfMuMuLLۼuM|$(Lk(LL tOMu1Mt1Hm} MMLH O 01fMuMuLL{uLk0M|$0LL tOMu1Mt1H } MMLHN 01GfMuMuLLuLk8M|$8LL tOMu1Mt1H} MMLHN 01RfMuMuLL軻uED$@DK@E8u0ED$ADKAE8uD1HUdH+%( uWH[A\A]A^A_]H(} L HyN 01hH} L HN 01Dwf. UHAWAVAUATSHL=~ dL$%( LeIM IE1H ~ ff. I7I<$ĺu:AE LLu|H]} I $ H N A 01L{HMuEt 1HUdH+%( u:H[A\A]A^A_]H} I $ HM 01D @ v @ UH5 HAWAVAUATISH N~ HH0dL,%( LmIH~ HEL;M E1 D I7I<$费u:AE LLu|HM} I $ Hp A 01L{HMuEt 1HUdH+%( u:H[A\A]A^A_]H} I $HM 1017 u @ UHAWAVAUATSH H $ H L-} Mu0dH4%( HuȾIH" Au LHH Iu11HI@HM9uHL=e} E1HLHff. fLL fAnHH߹ IwHIGIHfp HƅLfօHHDž ALHLH} I9sHL} HH0LH'H HtzLkƀ M H1LxH Lp0 D LHI8L9 IwI? MGEwHHuH 1HҚ} H6O 01L}E1f. HEdH+%( ufH L[A\A]A^A_] @ H HHH} H9tHM} HN 01~frf D UHAWAVAUATSH_8HdH%( HEHH H$uH_ H} H :p H 101(H[Ht,E1ff. t7HA[HHuHEdH+%( He[A\A]A^A_]ÐH H Lk@Lx-H H@ L oDHM 1IH5} MA0AU1AWyHHXZHSk9qf UH 4o H HAWAVAUATSH(HΘ} dH %( H]H101 H[0H E1ff. uyH 1HH HCpHtHH H HUL Ls(DO Lx-DMnHUDMDIH3} 10R1HL AVAWAUrH HAHHfHEdH+%( uHe[A\A]A^A_]p UHSHdH%( HEHH @$ H8H1H D HG0H9G0 H H;X~ H H ttH;X~ H;X~ H;X~ H;Y~ H1} H 01tHUdH+%( / H]f D H;!X~ uH; X~ vHHH5H 1 H; X~ LH; X~ tH;X~ Cff. fH;X~ )H; W~ tH; X~ ff. fH;W~ H; W~ \H;W~ f H;W~ H; W~ 'H SH} A HHJ 012n UHAVAUATSHdH%( HEHH @$ H8HH IHT~ IA Ią E1E11 HHH\ HG0H9G0tH H;SV~ H H H;`V~ H;{V~ H;V~ H;V~ I;D$0 I9D$8F I9D$`\ I9$ r I9$ IIAH;U~ tH; U~ tH;U~ kff. fH;U~ QH; U~ tH;U~ Hff. fH;U~ .H; U~ |H;U~ !f H;U~ H; U~ LH;U~ f H;U~ H; U~ I;D$ff. I9T$I;L$ I9D$8I9T$@I;L$HI9D$`I9T$hI;L$pI9$ I9$ I;$ I9$ rI9$ dI;$ VU H QIu6MEI9 1HUdH+%( H[A\A]A^]ÅuE1H} A LHG 01, @ 1HG0H9G0u&Hm} HG 01|H H;hS~ H H 4 H;uS~ H;S~ H;S~ H;S~ I;D$] I;D$8 I;D$` I;$ Y I;$ HjHH(HH} Hٿ HOG 01!H; AS~ sH;<S~ f @ H; R~ FH;R~ 9H; R~ H;R~ bH; iR~ H;dR~ BH; !R~ H; R~ "I;L$@I;T$H D I;$ I;$ I;L$I;T$ D I;$ I;$ I;L$hfI;T$p[v`hH!} Hٿ HE 01aff. UHAWAVAUATSH dH%( HE1JH H5S HIyH O~ L-Q~ AHpH(E LL%P~ Bh̓H(QI|$I(ËM9uL%N~ MI}I(觋I9uI$ I(葋I9uHEdH+%( 1 HeD[A\A]A^A_] H5 L豑AƅU1Sr L(LL H HHH H} 8~H} H0XL`1 LL0H N~ H LL-9P~ fHnfl)輛I$HI9 LL H L HH L-O~ fAnM IELLLƅfpH`fօh4~. jLHE1AWE111S^_H I}?H0I}IEH@Ht"Q( D q(9t BrvfHnH I(HAEI9,HL8fAnU IELLLfpH`fօhY}S j11E1AWE1LHxZYH/ I}dH0I}IE H@Ht'Q(f. q(9t BrvfHnHI(HAEI9.HH H H9LH L LVM4$M9t8ff. M 1LhH} 8 M6M9uM4$ID$Iƀ LL LeLtrA LLH L VHr} H^A 01赽Af. LM6M9<`LOuLL[1LFe LE1.AbAc UHAWAVAUATSH( dH%( HE1DH& H53 HIYLpLÅtuLL%L~ 6cM$ ~H=ff. fI<$I0裆M9uHEdH+%( H( [A\A]A^A_] H5 LÅr1N LL8HHH H} 8~H} H0SL`1 LLHLHDžd M<$M9j HLMHL=>K~ ff. 1 HLHfH͋} LA$ fAnHIDŽ$ HPIGfpLL ƅH`fօh(yX AG(1LH߉H} 0 I/HIIGքHHt"Q( D q(9t BrvfHnI0HL~ AGI9M$$L9LLRM<$M9kL50 M 1Ld1LH} 0 A@ I u I0 I AD I I8 H K~ LI <H=} 0$ A@ z I Q I0 % AD I I8 ILJ L轗HH~ LH@ I MH} 0 A@ ` I : I0 < AD I I8 , ILJ LMM LH} 07 A@ + I S I0 ' AD B I I8 , Y ILJ L膂LALJ AH} 0 A@ I ~ I0 R AD ) I ) I8 ALJ LtAHEG~ L~2G~ @ A LKHڄ} 05 A@ I I0 AD I I8 M?M9 @ HY} HE: L01蕶LN1H 1sL諆Z1H 1VL莆1H 19Lq;1H 1 LT1H 1L7!1H 1LHv} L D A| 0H ? H 1襵 H<} L N A 0H$} L # A 0H } L U9 A 0H} L 9 A 0yHق} L A 0^H} L A 0CH} L A 0(H} L A 0 Hm} L A 0HR} L A 0H7} L a A 0H } L . A 0H} L A 0H} L _8 A 0kHˁ} L A 0PH} L A 05H} L A 0Hz} L {8 A 0H_} L 08 A 0HD} L 7 A 0H)} L S A 0H} L 8 A" 0H} L A 0xH} L A 0]H} L A 0BH} L 7 A 0'H} L 7 A 0 Hl} L 8 AE 0HQ} L 7 A 0H6} L 5 A9 0H} L $8 A& 0H } L 7 A$ 0H} L F8 AC 0jH} L 8 AA 0OH} L A= 04H} L A; 0W UHAWAVAUATSHH dH%( HE19~| IH fHnH flfHnHF )~_| Hfl)M H5 LL要ÅthLL%B~ WLM$ tI<$I({ID$ M9uHEdH+%( HH [A\A]A^A_]f D L蠇LȊIHtjHQ~} 8~H} LH0HI$LHHHHLAÅ+HII9u H}} L A_ H HP 01 Uff. fU HAWL=^A~ AVLAULATL`SLH H( HdH%( HE1HLHDžd 襊 D 1 HA~HH} LLHfpLH@ALIGƅH`fօh(m Hс} 1LHߋ HIIGxHHt"Q( D q(9t BrvfHnI(HA~ AGI9 LF1HUdH+%( u=H( [A\A]A^A_]H|} H1 01DL|FT UH HAWAVAUL ATSH1H(L5~} L=} dL$%( LeIIH Ix@LLE 1LX1H}HN{} 0k L A I d QL- HLM I L% LH@ H $l I H5 Hx-M I~(dB LZ IJ H 6 PLH趖 I LH@ H 蔖 I H5^ Hx-u I~(d Lʧ IR H , > QPL5 HL I LH@ H I H5 Hx-ޕ I(d L3 IDžB H , . OLH莕 I LH@ H l I H5b Hx-M I(d L袦 I H , )OLH I LH@ H ܔ I L5 LHx-躔x I(dm L Ip H d_ NLHnG I L% LH@ H E I H5< Hx-& I(d L{ I H d NLHړ I LH@ H 踓 I H5h Hx-虓 I(d L I H dt xMLHM\ I LH@ H +: I H5; Hx- I(d La I H d LLH I LH@ H 螒 I LHx-胒 I(d Lأ I H _LLH4 I LH@ H I LHx- I(d H L @$uL H HtlL " LL5LMH HtAL LMl$LLH M;nuL͢IF [iHEdH+%( EH([A\A]A^A_]f D IM1H5 1LRwr D Ht} L ( A 0fH H 1֦Eof. Hat} L A 0 HAt} L A 0 H!t} L A 0uHt} L AD 0ZHs} L j A! 0?Hs} L O A( 0$Hs} L 4 A/ 0 Hs} L A6 0Hs} L A= 0Kff. UH HAWAVAUL ATSH1H(L= v} L5x} dL$%( LeIIH I7LL]E 1LO1HHr} 03 H B H x d1 H(, # C L H z d; Hx(d0 H L @$ H HtlL " LLLH HtAL LMl$赟LLH ôM;nuL蕟IF #fHEdH+%( EH([A\A]A^A_]f D L L @ IM1H 1ңL tHfq} L A 0H H 1蕣EfH*q} L A 0LIff. UH HAWAVAUL ATSH1H(L=s} L5u} dL$%( LeIII 5LLE 1LJM1H谣Hp} 0 L L5y I FLH虌 I LH@ H wz I}( l LɝH IjFLH?~ I L5 LH@ H U I}(dJ LL- dH IFLHڋ1 I LH@ H 踋 I(, L H IELH耋 I LH@ H ^ I( L谜H IQELH& I H5u H@ H I~( y H L @$ H HtmL # @ LL=LUH HtAL LMl$LLH M;nuL՛IF cbHEdH+%( EH([A\A]A^A_]f D L K @ IM1H- 1LJp7Hm} L % AO 0H H 1՟EfHjm} L AU 0HRm} L A[ 0H:m} L Aa 0H"m} L Ag 0wAE UHAWAVAUL ATSH1H(L5o} L=q} dL$%( LeII I 1LLEg 1LMI1H賟Hl} 0 L L-q I BLH蜈b I LH@ H z@ I H5k Hx-[! I~( LL5 覙H IGBLH I L% LH@ H I H5 Hx-ԇ I(d L)H IALH蟇 I LH@ H }s I H5n Hx-^T I(dI L賘H ITALH) I LH@ H r I H5 Hx-S I(dH L=H I@LH賆 I LH@ H 葆 I H5[ Hx-r I~(dx LǗH Ih@LH=i I LH@ H G I H5 Hx-( I~(d LQH I?LHDž I L5 LH@ H 螅 I H5Z Hx- I(d LԖH Iu?LHJ I LH@ H ( I H5 Hx- k I(d` L^H I>LHԄ I LH@ H 貄` I H5 Hx-蓄A I~(d6 H L @$ H HtkL !fLLժLH HtAL LMl$荕LLH 蛪M;nuLmIF [HEdH+%( ] EH([A\A]A^A_]f D L M @ IM1H 1誙LiH>g} L A 0 H [ H 1fE_Hf} L z A 0Hf} L b A 0Hf} L J A 0Hf} L 2 A 0wHf} L A 0\H}f} L A 0AHbf} L A 0&HGf} L A 0 f>f D UH HAWAVAUL ATSH1H(L5h} L=j} dL$%( LeIIH8 I*LL-Eg 1LgB1H͘He} 0 L L- LI H@ H 賁i I H5 Hx-蔁J I ;LHu+ I~(d LL% ÒLIH H@ H 6 I H5.V Hx- I #;LH I~(d LL5 FLIH H@ H 蹀 I H5 Hx-蚀 I :LH{a I(dV LБLIH H@ H C I H54 Hx-$ I 0:LH I( LWLIH H@ H I H5 Hx- I 9LH I(d LL%= ڐLIH H@ H Mi I H5 Hx-.J I :9LH+ I(d LdLIH H@ H ~ I H5 Hx-~ I 8LH~ I(d LLIH H@ H a~ I H5" Hx-B~ I N8LH#~u I(dj LxLIH H@ H }> I H5 Hx-} I 7LH} I}(d H L @$ H HtmL # @ LLLH HtAL LMl$襎LLH 賣M;nuL腎IF UHEdH+%( e EH([A\A]A^A_]f D L K @ IM1H 1LbHV`} L A 0ff. @ H k H 1vEWH `} L A 0H_} L r A 0H_} L Z A 0H_} L B A 0wH_} L ' A 0\H_} L A 0AHr_} L A 0&HW_} L A 0 v7f D UHAWAVAUATSH8 dH%( HE1D~\| HH fHnH flfHn)~6| fl)H H5R HLtaAŅ HH ,~ Z7LL kTff. H{H(ZHC H{lHC L9uHEdH+%( H8 D[A\A]A^A_] D LPgLxjIHtUH^} 8~HE`} LH0B(HLHHLAAŅ IM9uAH]} L o A H v H A01ʏ 5U HAWL=.+~ AVLAUL`ATL%'~ SHLH( HdH%( HE1HH HLHDž gj 1 HHHLHHa} x HNb} fAnH@LLIGHƅfpLH`fօhL H{a} 1LHߋp IiHGIIGXHHt&Q(f q(9t BrvfHnI(HH+~ IPAGI9LW&1HUdH+%( uQH( [A\A]A^A_] @ HA^} @ H[} Hr 01čL%3UHAWAVAUIATI1SHHxdL4%( LuI71IAH[} 0 I}('IH] LMHE LhLMLuH}1 H LZI ID$I9G( I Ml$0LHv I It$H@ H v| I It$ Hx-vE\ H5_} x tIGpI$H9q H_} x LHè I(貇HEIHH} MLh? H^} x < I 2 HY} L A H H% 01 @ I I H |%LhHHI9FLxE1MHMLpWIG MIH@ Jt+H `u IG(Jt+Hx-Fu M?HEII9 HMH}M H 1XL#M9rHX} L A 0H H& 1HEdH+%( Hx[A\A]A^A_] HYX} LMA 0 HA]} 1H HD@1耊LZ LLxLpL9HW} L ( A 0= HW} LMA 0"HW} L A 0HW} LMA 0HW} L w A 0HsW} L l A 0/fUHAWAVAUIATI1SHHxdL4%( LuI31IAHW} 0 I}(#IH] LMHE LhLMLuH}1 H LVI ID$I9G( I Ml$,LHr I It$H@ H r| I It$ Hx-rE\ H5[} x tIGpI$H9q H[} x LHè I(貃HEIHH} MLh? HZ} x < I 2 HU} L A H H% 01 @ I I H |!LhHHI9FLxE1MHMLpWIG MIH@ Jt+H `q IG(Jt+Hx-Fq M?HEII9 HMH}M H 1TL#M9rHT} L A 0H H& 1HEdH+%( Hx[A\A]A^A_] HYT} LMA 0 HAY} 1H HD@1耆LV LLxLpL9HS} L ( A 0= HS} LMA 0"HS} L A 0HS} LMA 0HS} L w A 0HsS} L l A 0+f UH H fHnH fLn< fHnH HAWfHnH: AVL AUIH5u~ ATISH LH ~-N| ~ >| ~>| ~6| dH%( HE1flflfHnH flfAl~= | HfHnH flfHnH~5| HH fl~%ƽ| H)HT Lfl~ | HDž HDž fAl))))@)H) )X)0)(fHnHB 8fHnHDž0 HDž HDž HDž( HDž HDžx HDž HDž 8)P(~ \| HU} )flfP)~ '| flx) )0)@))PHDžp HDž )Q1RHS} H= P} o o@Go@ G o@0G0M}LHt H LHI$ M$ @$uM$ I$ HtnM$ $ @ LH腒HwI$ Ht@M$ LI_<}LLI$ II;]uH}IE D CHEdH+%( uH [A\A]A^A_]_'ff. @ U1ҹ- HAWAVL`AUL ATILSH HS} dH %( H]HH5 ~ H LfP1H=eN} {LH-\t11LL#\I$ M$ @$uM$ I$ HtqM$ ' LHH vI$ Ht@M$ LI_{LLI$ ɐI;]uH{IE D +BHEdH+%( u\HĈ [A\A]A^A_]%ff. @ U < HAWAVLAUL ATILSH H[R} dH %( H]HH5 ~ H LfPx1!H=L} EzLHt11LLI$ M$ @$uM$ I$ HtnM$ $ @ LH腏HtI$ Ht@M$ LI_<zLLI$ II;]uHzIE D @HEdH+%( uH [A\A]A^A_]_$ff. @ UHz H T fHnH[ HAWAVLpAUL ATILSHH5'~ Hx ~%0| ~ | dH%( HE1~| ~ | flfHnH fHnH flflfHnH ~5ٶ| fHnfHnH- flfl~-| H`HH Hfl L~ | H2 )flfHn)H HDž HDž )8)0~ &| flfHnH; )fHn~ | )fl) )0~ õ| )fl) )@)P))))HDž0 HDž HDž HDž( HDž HDžx HDž (HN} 8fPHKJ1tH=5I} vHLlt H` LLlI$ M$ @$uM$ I$ HtqM$ ' LH͋HpI$ Ht@M$ LI_vLLI$ 葋I;]uHcvIE D <HEdH+%( ulHx [A\A]A^A_] UL L H H HSH}HdH %( H]H "H} H؇ LO1gxP3HMHr 1 GzH}ޙH}HEdH+%( uH]f. @ Hff. UHHdH%( HE~ ~ HEdH+%( uPf=~ 1Ҿ$ 1< =~ 11$ ( HEdH+%( u=[~ 1Ҿ$ 1 ? ff. @ UA HATASHhHH dH%( HE1AHH HuHE H`EaE E fHnfl)ph1AH`I1* xhÉǺ( 1A D 10 ; ߉1 1Ҿ$ 1HEdH+%( u8HĐ [A\]HE} HhHz 01x ff. @ UHSHdH %( H]H K} H;HHHHEdH+%( u H]1S UHHdH%( HEq~ h~ HEdH+%( uPf=Z~ 1Ҿ$ 1=B~ 11$ HEdH+%( u=~ 1Ҿ$ 1 ff. @ U HAVAUHHATH1SH@HH dH%( HE1HH E H@Z H1H H@Z| H5BE} L8 H5c=~ H59J} 1 ~ =~ 1Ҿ $ É~ 1=~ 11 $ 1Ҿ $ 1 ~ 11$ t=~ 11$ `=~ 11$ L L]TD L8H ,C} =j~ L1T L8=A~ L T L8=$~ _=~ T=~ I~ 3MH ML P~ P1tXZIt"3I LH 1t ~ t3H 1t }~ t3H 1tI IuKIum=J~ ud==~ 1I!ЃHUdH+%( U He[A\A]A^] @ 31LH tItf. f H 1s 31LHj sIt3LH~ 1 sD3H 1Its53Hܺ 1ISsH @} H 1I3+sH@} Hh 01 sH@} Ho 01rf. D UHHdH%( HE1~ HEdH+%( ux UHHdH<%( H}1pNHUdH+%( u:f. U HAUATHHH@SH1HH dH %( H]1HHH8 E H@ V HHع fo# HLHH] )HDž HH HHw ƅaHaLA1I* 1 Aą Ǻ( 1 D1 ' D11Ҿ$ D11Ҿ $ D1ff. KFu1Ҿ$ D1`H DlOuvDH L-7>} 1Dz~ HH Au npH' O~ d 1HUdH+%( HH [A\A]]L-=} H 1HAu pD2 Au 1D~ HHv oAu HA' 1H o ~ du XAu Ad H 1 oH*=} H Hʶ 01foH=} H 01Ho! UHHdH%( HE1HEdH+%( u1ff. fUHAWAVLAUL-~ ATSHX L5w dH%( HE1@H~LEH@H E1fHnAflA)f D Hfo1 LHDLHDž ƅ`)D^1ALI1* exU0HHduH;} Hr E101mHEdH+%( uvHX D[A\A]A^A_]H];} H AH 01mHcDŽ0tH0L$f ;H I9u{6f D UHAWAVAUATSH HdH%( HUHcH HHHH% H)HH9tH H$ H9u H)HL H\$HE1L=^ HL5~ HHHH HH(H fHnfl) @ foH 1 L H)0DžT LXHDž` ƅH`1\H1IA* 1NH9} 2 BD 1H IkL9Rfo H $@H)fo0H0HJ)fo@)foP)fo`HH)fop< 1Dž ) fo)fo) AH8} 0Ep H 1jtYLI ;HL9uHEdH+%( z HeD[A\A]A^A_] HL D foHH1 H@HL@HH)PDžt LxHE ƅh`+ZH1AI* 1HH 7} 1x|H; 1iH(H 1iHZ7} L AX 0H Hˆ 1iAL Aa HHH 1UiAg H6} L H ; Hi 01%iff. U HAWAVHHAUL@ATSH L5~ dH%( HE1H8HH~ L@Hx fHnHE flƅh`Džt )PX1ALI1* ` H5} H0Dž Dž ff. 1 A Du[H0HE11H 0j 1DgXZHEdH+%( Heظ[A\A]A^A_] @ HcH4[IH E IǸ L1fHnfl) @ H81 fo HH.~ L@Džt HxHE ƅh`)PW1ALI1* 49 ACIA9qLAD9q IcDM< L fHnMEfl) f. AH81 fo HH L@Džt HxHE ƅh`)P*V1ALI1* K A$AGI9oDL EE19AŅt?IcEMHII\ M4 L)ff. A>II9uMLTH0H DH 0AU1 DA?eE^__QHEdH+%( j HeDD[A\A]A^A_]AL $@1|DÉH_2} H0E1L0L1H HH AA6L8kdA11A6HB QdL8DSAAEvH0L Hw HHD8M01L DcD8AL DAHo1} HH H 0H01c]z A UHHdH%( HE1HEdH+%( uɸ: f. U HSHhH`HH dH%( HE1HH uHE H`H3} E`HE fHnfl)pRHA1I* 1 ÅxHEdH+%( u6H] @ eM H H#0} 01pbIf UHAWAVAUATSHdH%( HE1Gc LcÅ L-92} L} LMu @ H} M LMe @ H}uL1HUdH+%( H[A\A]A^A_]f t˸ H/} L Ap 0H H~ 1HaH.} L ܩ Am 0H.} H 01aH.} Hu 01`! UHAWAVAUATSHdH%( HE1a LcZÅ L-0} L} LMu B? H}uxM LMe ? H} m1HUdH+%( H[A\A]A^A_]f t˸ H-} L A 0H H } 1_f D Ha-} L o A 0HI-} H 01_H(-} H 01k_A UHAWAVIAULcATSH dH%( HE1>` AÅ H0/} IcL@LH =k H@ HH1 $@HLHHX Džt HE H@H1} ƅhaHx fHn1fl)P , Hw1} L8 LD`< H8^ 1Ҿ $ 1 LH#1} D`< H83 H0} LD`< H8 1HEdH+%( Hĸ [A\A]A^A_]f D `,8tPH +} HR ,01F]o, tw @ IH MnIEf D H*} L A 0H H z 1\Hg*} L A 0HO*} L k A 0H7*} L S A 0H *} H 01b\tH)} Hţ 01A\ H)} H 01 \,H)} H 01[> D UHHdH%( HE1ߪ~ HEdH+%( u D UHHdH%( HE1~ ~ HEdH+%( uKff. Uf H5[HAWAVAUATSH dH%( HE1)H HHd )) ) H0HDž8 .UH ImIdHM+ H" HLL=H0H1LL5 Aƅy I$LB8HB B@ f%ݟf fB8oxAƅd L! LA h6 ~ t ~ LCA I$ H&xH%Ht) 8u~ HEH%HuHzfH!'} H A01^YLHJLHEdH+%( ! H D[A\A]A^A_]ÃtH&} H 01XAH&} Hx 01XrH@ HE HHM&} 01X9[H@ 8Hl H~ IH &} 01[X]H%} Hp 01:X<H%} H A01Xf U HAWAVHHAUATSH dH%( HE1HDžD Dž< HDž HDž@ HHfh!HDžX HDžP UH H@1I(HH8 HL)jHl`aIH H HHL9L5u,A LJ AŅ Ly ff. <<uL<yM$ L#H HHDž H LhBLp"H 8 uHHLpAŅ H ,H f D H#} H" A01UHnLLNHEdH+%( h H D[A\A]A^A_]YH@ LP8AM AHH'#} L H! 01hUmLHc,H H9NH"} , HC A01 U!H"} Hܞ E1A01THXH@ 8IA H IHa"} 01THL"} H| 01TH+"} H] A01hT>ff. UHHdH<%( H}10tHUdH+%( u HEdH+%( u ɿ f UE1A! HAVAUATSHL-~ dH %( H]H1E Au .H}HCIĿ 1L5%!} MCH} 1A6_S{ HuԺ XHuP~ ud d`~ tAu H{HEdH+%( u+H1[A\A]A^] A6H 11Rff. UE11A! HAWAVAUATSHhdH%( HE1Hh~ &~ 0-H{H~ Hÿ 1L% } Iؿ r~ HU 1A4$6RH=~ =u2H _~ H(1H e=`~ tL/=U~ $A4$L ` A L- H o 1LHQ f D L} Lg0=~ H=~ HuH=~ <=uH Ѡ~ Hz1Hpd=Ҡ~ t=Ǡ~ vM L/=~ HU=~ JH H=~ <H u~ H1Hc=v~ t=k~ D Ls/=E~ H=;~ H[rA<$ H $} H53#} A HHxE11A bH=y~ H b~ pHu$} I H ~ 0~ I~ 1AI T Au߅ p\ L-~ L*EueHxD=IMA4$H1 Iƿ 1OIELL HPL*HMA4$H LH 1I NOLHߞ~ I9]HxE1A1H~ ! ~ 0-*IH H~ 1-A4$M ~ H֘ 1NH= ~ o:u2H ~ H1Ha=~ tI=ڝ~ A4$L ~ A L- H k 1LHHNx L,=~ IU={~ JIuH=~ 9uH ]~ H1H`=^~ t =S~ T D L{,=-~ I=#~ I H=)~ L9 H ~ H1H|`=~ t=~ D L+=͜~ I]=Ü~ RInA<$IHpH=!} bLE11H } IA HA SLL-ޛ~ xH } H=՛~ Hs~ 0*~ I} 1AI Au߅ x LpLd'DkaLDN:HKA4$H Iſ 1LHCLL HPL@'HMA4$H LH 1H KLHV~ H9aHpAHEdH+%( < xHh[A\A]A^A_]f H 1]KLL- H h HxA4$L A LHڿ 1KDžxhf H 1JLL- H h HpkA4$L 0 A A4$L A 2A4$L A A4$L A f D A4$L A o-s UHAWAVAUATSH( dH %( H]HH 11H 8 1HHI8 1HI7 1HI7 HI7HM M MHM H HL L! I7Lm I6LZ Iu LF H\HH$ HH LHLHLHHHHHHH HH5 j HHH0y L#L a L#L n L~#L { H_#HS#H | H0#Hh 1HUdH+%( He[A\A]A^A_] @ HQ} L x A* 0H Hd 1Gf L H } L A. 2jPff. fH0{ H > 1&GXZfH H} L , AJ 2jP L H} L AP 2jP L` Ha} L ؑ AS 2jP`L8 H9} L AV 2jP8 H H} L | A\ 2jPH} L i A1 0H} L N A2 0tH} L 3 A3 0YH} L AL 0>Hy} L A; 0#f. f. f. f. f. f D UHHdH%( HEHG+FHUdH+%( u*f. U1HATSH@dH<%( H}H}ÅurLe ff. u1LÅuFHUHEH+UH+Ey HH@B Hu?H=P ~fo 1H})EOEHEdH+%( uH@[A\]r^ff. U fHAWAVAUL ATLSH( dH%( HE1) )0)@HDžP HH ƅMDžHHDžYHH& HH IH HHHw&H5M L ID$H = LHH L59 LI\$L L7IH= 1 ƀ I; $y HLMI; $ HF H9H5 L* Mt$LL"Af9 LIF 1LLkMI$H9. AV9҃? I9t f I9t @9 H I9uLa`) L| LdH E1111H5 A4O HaX E1111H5 4 RL E1111H5^ 3 Hp E1111H58 3 LcfInfHnHflH) fHnAD$0fl)2 E1E1H`E1H DLHI$ H H A;D$0|E L(-HH HH1HH9t( @ oHH oBH@H9uH LHES DH`DL5 } HHHL HI H L9 LcA$ @ uEl$SUA9* A<$B A6H 1L DHT?A6DH 1 ;?HHHH9 DžHff. @ HHGHBHHH9uH0lDE D<E\ D@EL D> H0 Lt P T A6H- 1M>4 A1IH; LpHLLH LLhIE HIE HpH IEH)H IHwH f. HA } H 01=L`LHH\HEdH+%( { H( [A\A]A^A_]ÐH } H 01=Dž H } Hp 01<[ Hy } L H 01<DH1HK A6 L D<HaHHH9 HbHH L|{ HH AIH; L;(TA6Hc 1;<u DžL D@EtDDEu DžP DHEDžT L5J } 1ɿ 1H= A6;HbHHH9H0L5} HW 1A6=;H5'HHDžH9H0L5} H A6H} Hm 01:Hk} Hl 01:E1E1)H?} Hٿ Hj 01:fH} H/ 01^:EA6H 1C:*H} Hӆ 01": LH'm HL)LHf LH{)DA6H DHA D19AEEX L0MU ED;8 Kt99 @H} Hk 01E9,H} H 01$9 H} Hr 019H} H 018Dž_Ht} Hb 018DžHDž )H>} H 018H } H 01c8JH} H݄ 01B8)Dž Dž El$MA9tJA<$u-El$MA9 A<$uEl$MA99 U @ El$ MA9uMl$H5 L!u@ A6 A L 1H Dž@ s7HfEl$ MA9Ml$H5 L)!< A6uME11L H Dž< 7A<$7Dž Dž f D H8 L DH6YEl$ cLA9Ml$H5~ Lv H A6uA L 1H DžH L6ZEl$ KA9-Ml$H5 L D A6)A L 1Hg DžD 5HcLH IHa H0Hc89~)DI< L)H LE鉅8A6H 1G5.Hc !H0H E HJ LLI8dL5} Hف 1A6A6Hʁ 1L DH4EL5:} H 1A6|4HHDžHH9T;L DHA6Hg 1L DH 4 D UHAWAVAUATSH(HudH%( HE1G0 E IE1E1 AI E9f0 I LH xHIHuUff. fHf D AGEI9Et/ff. @ H8 H@IHtA?uAG EH9EuHuI U E fHEdH+%( uEH([A\A]A^A_]f. U HAVAULATLSH dH%( HE1Hƅ DžLDžTHDžx HmIH IH HH LHLH5c~ Hr H5} H[# 1HL<HHB8f%f fB8O H HL5K~ 7TE1111L # HTLH^ H| HϾ 0191# H| H½ 011AHSHnLvLHEdH+%( H D[A\A]A^] Ha| Hz 010fH@SH{/ L5X} E1111L " H| H 01F0-H| Hd~ A01 0f H| H A01/f H| H 01/ HHRLHE1H:| Hc 01}/d H| H 01T/;H| HT} 013/AE1'H| H;} 01 /f UHHdH%( HE+HUdH+%( uff. fUHSL$ H H $ L9uH foL fnfnfp fp dH %( H]HHUHff. ff. f fofofHf)HH9uH H1f D HH= t!9tH| H1| 01-HEdH+%( uH]f UHAWAVAUATSL$ H H $ L9uHh 1 TLLdH%( HE1HHF ƅ DždHXHHHHHDžHx ~6f| HDž fHnHx flfHn)~f| fl) BNHHhH| HH P HhT Lh LE IE DhA}6IH HhE11HH| A 3 Hhډ(H0H H`H ASSA!DDQHȃLM H Az LLoIH2 H`HLa LHH| 01V+LL 1LL&6IU I9t%ff. fB8f%f fB8HI9uL0I LLXD' HX L-T L% eMff. fLLe3HHt Luۻ f D uL LЫ @ $} rt(LyH| Hx 01*HXE1E1HLHs0HDž HHH LpELXI$ LHH@ D̫L@LM LxLHH: PvуwHh1HyH| MH 01)H@ AH0HHX\H``LؿHhlHEdH+%( HeD[A\A]A^A_] HA| H j LHH8V IE A PwDhE12IH H| H 01/(8 H@MD̫L}AI E;t$0:LpQ A TtS A H5K LHEAHЫHLd (,HhIH| 0M H HZ H R1HH HHٿ 'HHH8 RHLH8H | 1H# HH@ HH H Hu 1 &HH 8| 1u a HجHsu 1 X&HH H@HH)H9ȸ HجHBHH t-H9 s$H| Hٿ H 01%Y I?LHHHH豭H9 Hx H HHH7 HHH1 HH9 H9uH| Ht 0 1,%H| Hyt 01%~H| H8 01$HDžX AE1HDž` Ho| H s 01$뾀R H 1$H8ļLH| H A01U$HDžX HDž` BHHL0M H`34L苺L11Lg^H| H 01#HDžX AHDž` HV| Hnr 01#HH= . HHHH͐HH HHثj˫t1HHث HH讳 HثHجHHCH HHxH H| L̲ LHثHP1Q @H = H:| Hٿ Hr 01z" H5 r HH5N H HH\ HHDž H HxLHDž HHHHH LLLLIǐH HL LH芪& H H: H HH@: H50| f D B HHI uLL A HDžp LLL(I @ 1MHxIHMq D AE L%| HAD AEIADtA@IIH AE A^A uMuHHxMLMHvrLD0L9s4ff. ff. fA8HI@xAPL9rHpIHH 1 if HpHt4If D MMHLHxIP Hp L(L L H1HH5: ! HHH9 HxII)M9 LLHH)LHHpH9HGHHJ< LHIHHL9HHHLH)LLLzH H˫ HHH>.H | 1 H 1: HH| Hl 01 6H| LX8~=S!H L0HH{| HH 01 H`-L'HX11H HHDžX rLLLLHHHH)#H H讧˫ k LMHl H| 01 H8!H%H@ @ Ha| Hdk LX01 H9| H@l LLL01L` DžHXH| Hj A01( H| Hٿ Hu 01 ttHLMd˫ HثKHDžX Hث*HF| Hٿ H 01H˫ 8R<t<HcHH)u`H $ LMH8GHOH@LHi M 1Ht| Hj 01"Hث&:HثH1| H LLL01LXH| H% 017H H| MH g 0 1H@H| Hi 0軿H|| LHh M0MHf H= 11LL%#& ML-i H(| Hi 01kHCH9 HHL H| 012HHШuH| L 01H肣˫ uFH| 0H| Hh LM01˫ Hث'묀˫ LMH*| LHg M0H| L E101SH| Hbh 017 IFL9tKIHL B 0H| 01LHШuH| L 01Lf UHHdH<%( H}1 t\NAH HcH>H1| Hg 01t @ 1HUdH+%( | f @ H| H{g 01$fH| Hfg 01fH| H1g 01o躼f. f. f D UHAVAUIATISH dH %( H]H tHF H9G tIE I9$ t AEA9D$^ AE A9D$ tIEI9D$ @tIE I9D$ & tIE(I9D$( ÀtAEXA9D$X m 4 HI$8 I8 i H9@ tI0 I9$0 f H M@ M$@ 1f. HIHM LIIsH3H3pH r H| H 01.\ @ IEI9D$H| He 01+ H| Hne 01ff. E1HEdH+%( H D[A\A]A^]f. HA| H.e 01fIE0I9D$0H| He 01U H| He 014_ H| He 01 7 H| Hd 01 H@I9CHH9Mff. f tkI$ I HH;X 1HuG HH9t7H|H9|tH | Hݥ 01Ozf. tSAT$\A;U\ I I$ DE"DE̅t$H| Hkd 01 ' t1I$ I; I I$ "# @tIE8I9D$8 ǀtIE`I9D$` tIE@I9D$@ tIEhI9D$h tI I9$ @ tIEpI9D$p tIExH I9D$xuJA I$P I;P IX I$X !H HG| 01 @ H)| H 01l H9 tI$0 I90 I@ I9$@ fIH I9$H QH| H# 01H| Ha 01 I$ I L L; E HBH9A ME HH1 HHqH3H3rH tMH| HO 01Al @ H| H 01 G HBH9AuHHHI9uI( I9$( b 5I0 I9$0 H{ I( I9$( uUf H!| H 01d H| H 01<g H| Hq` 01? I$ I I9$ I$ I; HI$ Ht!I HtH H;| H 01~H| H 01]H| H 01<gH| Hٟ 01FH| H 01 %H| H 01 H H9B AH^| HO 01 I$ I I9$ ? I$ I; HI$ Ht!I HtH H |H| HD 01 1H| H~^ 01 H| Hy^ 01 H`| H 01 H?| Hx 01 H | H7 01a H| HΠ 01@ kH| H= 01 JH| H] 01 )H| H 01 H &H 蛱ff. UHAWAVAUATSH H $ H fo P dH%( HE1IH@IHHDž HH@ HpH)foG H@ LhHH)Hfo( H!C̻HDž )fo H H)fo H HDže )fo H)fo ) fo )fo )fo HS HH )fo HH)foѼ HDžp )foǼ HDž r )fHnHfHnHHDžP flH@H)0fo HXfo{ H`) fou HDžp )0fok HxHHDž HDž H)@foA )PfoB )`foC )pA tHA tHA t HDž foa fHnfLnfLn fl fLnfLn fLnfLnֹ )0fHnfElflfnfElfp fElfEl) fElfnfEl)fp f fofofoHfDofofofo0fDofEfAfEAfAfDofafAfDifofAfAifAψfAaވfafofafifoffifafԕ faffgfۅ)@H9=A5 H HDž HLLHLL ILL0L0HI Lھ HL0Y1fE~HA LLLfAFeL0t) D C| ICuIMuM9 H $| ML1H՛ 3aL9Mt3LH[X 1 <AHEdH+%( H D[A\A]A^A_]foV HDž Lg"LHLLL0HL0AueLLLHD*tvI LaFH | A1MH GW H 3SH | AM3H 7W Hi 1%H | L H 3 ƅ*L`f!HLLHAuIL LHD*H E| H1 1 3 H | A 3+EH| HSQ 01I @ UHAVAUA ATA SHĀfoy dH%( HE1HE )`foc )pfod )Efoh )Efol )Efop )Efot )E@f D ? I tI HE1Lu;MAtVIuH`Lu HI9tH1 tHUdH+%( uAH[A\A]A^] H`Le HI9tH? =t¨f UHAUATSH H $ H dH%( HE1HHDž H L8L@HDžh HH HDž HDž Dž@ fHDžp H HDž@ f HH (HDž HHHDž fHnHfHnHflH0@ ) 4 D H?w`Ht[L迼 HL9tNH H3@u1H能tH | H 0 1CH D H1蒧HEdH+%( u"H [A\A]]H| H N 0̦f. fUfHAWIAVH}AAUAATSH8dL$%( LeMDL)EDDEDEH2| ۋ0 EuH LDM P1^ XZD8m D9u LmMtOM LL LHEdH+%( He؉[A\A]A^A_] MtH| L A 0 D H R H 1 L Q A H:| L Q A 0H"| L Q A 0H | L M A 0,ff. U1ɺ HAVAUL-Q ATLSHdL%( LELxQ n E111 Lj 1ɺ LL9Q g E111 Lk 1LH 2| 3k L%ɔ E1L1L ^ L ] LP3 L 3 LL1A ' L3 LA L1 L P L-P LP L E11 L} LBP L k E11 L` 1LV3` L 9 E1LL 10 L#3l L LL1A L3u LA L1 L gO L-}O 1ҹ LLrO m E111 Le 1ҹ LL.O V E111 LgN 1L53N L N E1LL 1 L3\ L N LL1A L3{ LA L1 L FN LbN 1ҹ LM" E111 L[ 1M LjP E111 LNH 1L 3H L M E1LL 1 L3V L vM LL1A L3a LA L1 L -M L-;M L M L V E11 LfK LL L @9 E11 L!. 1L3m L E1LL 1 L3 L LL1A L3C LA L1 L L ]L!L 1ɺ LM_? E111 LCK 1M L$ E111 L$ 1L3$ L E1LL 1 L3q L LL1A z Lm3 LA L1 L J DLK 1ɺ LMF5 E111 L*- 1M L " E111 L 1L3Y L E1LL 1 L3 L m LL1A a LT3/ LA L1 L I +L~) 11Ҿ LM0. E1111L) 11L>) L E1111LY 1L3 L 9I E1LL 1 Ly3g L I LL1A P LC3 LA L1 L H LH 11Ҿ LM 0 E1111L+ 11M L# E1111L 1L3 L ,H E1LL 1y Ll3, L G LL1A C L63K LA L1 L G LG 11Ҿ LM E1111LE 11M L E1111L 1L3 L G E1LL 1l L_3 L F LL1A 6 L)3) LA L1 L F LF 11Ҿ LM( E1111L# 11M L E1111L 1L3 L F E1LL 1_ LR3$ L E LL1A ) L 3/ LA L1 L E LE 11Ҿ LM. E1111L) 11M L! E1111LAƅ 1Lu3 L E E1LL 1O LB3' L D LL1A L 32 L D LL1A HEdH+%( A HD[A\A]A^]Ë3L ] A H C H 1Af D H)| L \ A5 0H| L \ A6 0 H| L \ A7 0 HѾ| L |\ A8 0eL-[C L%= A% L C LL3L ;\ A9 ff. LL 1#L-B L% A% L &C LL3L [ A: L-B L% 1L B A% LLP3L [ A; l3L [ A? x3L y[ A@ d3L e[ AA P3L Q[ AB <L-2B L% A% L YB LL3L [ AC L-A L% A% L B LL3L Z AD L-A L% 1L A A% LLA3L Z AE ]3L ~Z AH i3L jZ AI U3L VZ AJ A3L BZ AK -L-#A L% 1L NA A% LL3L Z AL L-@ L% 1L A A% LLo3L Y AM 3L Y AQ L-@ L%o 1L @ A% LL3L kY AN 63L WY AR B3L CY AS .3L /Y AT L-@ L% 1L ;@ A% LL3L X AU L-? L% 1L ? A% LL\3L X AV xL-? L%p 1L ? A% LL3L lX AW 73L XX AZ C3L DX A[ /3L 0X A\ 3L X A] L-> L% A% L $? LL3L W A_ L-> L% A% L > LLM3L W A^ iL-> L%a 1L > A% LL 3L ]W A` (3L IW Ad 43L 5W Af 3L !W Ae 3L W Ag L-= L% A% L > LL}3L V Ah L-= L% 1L = A% LL<3L V Aj XL-n= L%P A% L = LL3L NV Ai 3L :V Am %3L &V An 3L V Ao 3L U Ap L-< L% A% L = LLn3L U Ar L-< L% A% L < LL/3L U Aq KL-a< L%C 1L < A% LL3L ?U As 3L +U Av 3L U Aw 3L U Ax L-; L% 1L < A% LLq3L T Az 3L T Ay L-; L%q 1L ; A% LL 3L mT A| 8L-N; L%0 1L y; A% LL3L ,T A{ 3L T A~ 3L T A 3L S A 3L S A L-: L% 1L : A% LLJ3L S A fL-|: L%^ 1L : A% LL 3L ZS A %3L FS A 1L-': L% 1L R: A% LL3L S A 3L R A 3L R A L-9 L% 1L 9 A% LLK3L R A gL-}9 L%_ 1L 9 A% LL 3L [R A &L-<9 L% 1L g9 A% LL3L R A 3L R A 3L Q A 3L Q A 3L Q A L-8 L% 1L 8 A% LL83L Q A TL-j8 L%L 1L 8 A% LL3L HQ A L-)8 L% 1L T8 A% LL3L Q A 3L P A 3L P A 3L P A 3L P A L-7 L%z 1L 7 A% LL%3L vP A AL-W7 L%9 1L 7 A% LL3L 5P A L-7 L% 1L A7 A% LL3L O A jf. UE111ҿ HAUL- ATLSHdH%( HE1M іHHP H{ 1HpAA90 1H~H 1HkLH Hz蠈HH H|{ 1H8p 1HH\ 1HH5 HCAą8 H5zHEdH+%( HD[A\A]] @ H| L [6 A$ 0f. H 6 H 1Af D Hi| L 6 A% 0HQ| L - A* 0 H1| L 5 A4 0 H| L 5 A5 0e D H| L h- A9 0E D Hѯ| L 5 A' 0% D H| L n5 A6 0 D H| L 4 A 0Hv| L 5 A 0H[| L 4 A0 0zf. UE111H5+ HATSHdH%( HE1ufHH H1H 1HӘAąulHxHEdH+%( HD[A\] D H| L 3 A^ 0H 4 H 1A HQ| L 4 Ag 0H9| L 3 Ac 0[ff. UHAUATSHdH%( HE1H~ LfHHI9 L- H{L c HHH x 1HlAA9 1H`H 1HMLHAą HvHEdH+%( " HD[A\A]] H| L 2 AG 0f. H {2 Hx 16Af D Hɬ| L s2 AN 0H| L d2 AO 0 H| L * AT 0 Hq| L .2 AQ 0e D HQ| L 2 AI 0EH6| L 1 AH 0*H| L 1 AL 0:f. UHAUATSHdH%( HE1 H}AH1 1(J H}111qH}HsL-| Au H` ~H| HH0k1H葙Au { ~H| HH051H[Au DcE ~HO| HH01H"t.H6tHEdH+%( HD[A\A]] D Au L 1 A H *0 H' AL 0 A H / H 1HW| L >0 As 0L i0 A L Z0 A L y0 A L 0 Ay =f. UHAWAVAUATSH H $ H fo H-XXXXXX dH<%( H}H)HH8 s yL=~| 1H8Ht0 A7HHp11HpfɺHxIH= ( SI$ H L5 L( LID$ LI$ ʟ,! I$ _L7貪IH H8f11HHpDž xIH= F I I]X H5N1 Hx AEdE1~KDL|- LA7DHD/ HI IDD@ 1E9ud1LE1HcH@H0 fH01҉@DHL\;` HI 9C ;* 9KQ ` o ALDpHcLA9l1L1PAH@H0 f. H01DIcƋ@DHHLI DP D9\ ; ;H ' 3 L踎AL9u1L1虎AH@H0 H01D_IcD@DHI L\`DD9HK 9P- A LAL 9d1L1؍AH@H0 H01DIcƋ@DDHI L\`DHD9 A L9AL^9d1L1AH@H H1Dm@DD0H(L$\ ` ]9 (~ $_ @ ! 0 LGALl90L\ IE9ud D H5* Htt H5* Hs H5, Hsu(1L貋 I )L k Ar A7H ) H 1 J D A7L ) A* H ) HX 1Dž,H8rHEdH+%( ,H [A\A]A^A_] D A7H) 1 A7L Fk A H ;) H 1Dž,Lrc A7L k A f D A7L &k A f D A7L ( AJ f D A7L k A k A7L A) A S A7L B) A ;A7L ( A5 A7L j A A7L j A A7L k A A7L ( A A7L ( A A7L (( A- H ' Hu 5A7L ) A {A7L ( A fA7L ( A QA7L ( A <A7L j A 'A7L Uj A Dž,'L j A *L ( A L ( A L Fj A L ( A L Q( A xL ) A L ( A L ( A L ( A L Z( A qL i A _f D UHAUIATSH dL$%( LeIH L L HHþd Lnd HHH)I| HHphmd H1LH]( 连LLu HUdH+%( uYH [A\A]]H| IA 0H ( H 1Hq| L A 0v UH5' HSHdH<%( H}H@ H}M H}H5' H5' H H#} H H H}yM H}H5' cH5' E!ZEH}D HUdH+%( uH]u UHAWAVAUATSHHdH%( HE1H=- HXjH= IIjLHIHEgH= ' I(jLuHEL}HELeE1H]H]N,LLjo E1M9tJ4LNo IIuIIuL*HuHH}HIo L_mH}LLHIn LLe1mH;H%mL9u1HUdH+%( HH[A\A]A^A_] @ H| L & A 0H % H 1HH| L % A 0Hʛ| L K A 0H| L G A 0s @ UHAWAVAAUATSHHxdL<%( L}IthHIihLHIHHD9ukL`d HL4LLiAƅ LkLkHkHEdH+%( HeD[A\A]A^A_]ÐHxA HÚ| L de H $ 2AVH P1XZA H| L Je A H o$ H 01r U H5Z$ HATL%T$ SLHdH %( HMH q H *$ H5"$ H= $ [ H $ H5 $ H= $ 4u`H ) LHHuBHٺ LHu+HEdH+%( u9HHHHߺ [A\]HEdH+%( uH[A\]~qff. UHATSHĀdH<%( H}H=.# fH= # H fHHIHH Hud HH1-2,4-5,H9EtVH| L c A 0H " H( 1HUdH+%( u]H[A\]f f}7u1L牅|)iH!i|f H1| L m" A 0uPp UHATSHdH<%( H}H=^" d11H HHR HhH=3" d11H HH HphH=" d1H 1HIÅ L<hHEdH+%( H[A\]f D H9| L An 0H ! H 1h륐H| L Av 0 H| L A~ 0o UHSHdH%( HE1f~ f~ & f~ 6 f~ u{H~rRHH 1H~ H~= H g1HUdH+%( H] D H| L v AA 0f. H Hh 1& H| L c AD 0H| L AE 0 H| L AG 0Hi| L A? 0mHN| L A@ 0RH3| L AF 07H| L A= 0 7m UHSHdH%( HE1f~1 ~ x f~ 7 f~ u|H~PHHH= 1H} H= H4e1HUdH+%( H]f H1| L A[ 0f. H H 1V H| L A^ 0Hѓ| L F A_ 0 H| L ( Aa 0H| L AW 0mH~| L AZ 0RHc| L A` 07HH| L AY 0 gk UHAUATSHdH%( HE1f~e F f f~ . Lf1LN L ֹ thL讹uH| L A% 0H o H 1AHEdH+%( S HD[A\A]] L(NHI 1LzAŅ t0sL]z9tHڑ| L O A, 0Jf D LbWH| L V A 0 H| L A 0Hv| L A" 0H[| L A( 0H@| L A 0H%| L A# 0H | L A* 0z)if UHATSHpdH<%( H}H= ! ]HtCHHud HHwaf}1t H| L L A 0 D H=I t]HHt<Hud H[H#a}1,5 tH;| L A 0rfH=1[ $]HH d HuHH`H1,3,5,7,H3EH9,11,13,H3UH t^HϏ| L A 0 H H8 1HUdH+%( Hp[A\] D H,15,17,1H3EH9,21-40 H3UH }H=( O\HHtGHud H6H_}2-5 t%H| L A 0Jf. L% L[HHtbd HuHH_H1,3-6,8-H3EH10,24,35H3UH t H| L [ A 0 @ }-37 uL[HHt`d HuHfH._H1,3-6,8-H3EH10,24,35H3UH t H.| L A 0bf}-37 uH= [HHtkd HuHH^H1-10,12-H3EH20,22-30H3UH t!H| L u A 0f D H0,32-40 H9Eu1ef. f UHHdH%( HE1~uS~ H~ H~d H~ H~(, 1HUdH+%( H| L r AH 0f D H Hh 1&H| L w AI 0H| L l AJ 0H| L I AK 0Hx| L E AL 0|H]| L 4 AM 0a|dff. UHHdH%( HEﾭH9FuH~ uJ1HUdH+%( uQH| L Ag 0H Hd 1"H| L # Ah 0cff. U. HH dH%( HE1HH~HH HFH H~ taH~0 H~@ H,| L A$ 0H H 1[HUdH+%( ÐH~(uHu H~ H~ j H~0 H~@D H| L A% 0tf H~tH~ -H~(tH~0 &ff. H~8HkH~ vH~(kHt$ D H~8^HuH~t7H~ t)H~0tbH~@tiH| L A& 0H~(uHQ 1 H~8tH~@uH~Huf H~H:H~HCH~(GHA| L A# 0H&| L A, 0H | L A. 0H| L A- 0aff. @ U. H HH dH%( HE1HHH1ƅDž Dž SuHUdH+%( u9HO| L xS A; H H 01~R`f U L 1HH8fon dH%( HE1j LEHE, )EnZYuHUdH+%( u9H| L R AY H E H 01_ff. U11H ﾭHHdL%( LEE1 \uHUdH+%( u9H| L DR An H H 01J _f. @ UHHdH%( HE1H~{u+H~u[Y f.Fzdub1HUdH+%( uiH| L H A# 0H H 1賸HM| L A$ 0H5| L & A% 0W^ UHAUATSHX dH%( HE18|H H IHD 11HA{ LRHP MH=m >1H HHP O HW 1HHHH c HL KH HLHE H= "RHH( LH iiÅ L]HEdH+%( HX [A\A]] @ H| L q AZ 0f. H . H( 1 Hy| L O Ab 0Ha| L O Ag 0 HA| L O Al 0H)| L O Aq 0mH| L AV 0R-\ff. f UH~HATSHdL$%( LeI?I|${7 I|$u|HHI 1Hl Hk Hk H)T1HUdH+%( H[A\] H)| L AG 0fH H 1V H| L AH 0Hт| L AI 0 H| L AJ 0 H| L d AK 0eHv| L : AF 0JZ D UHHdH%( HU1H~{u/H~u_HH~H@ du`HUdH+%( uiH | L A6 0H w Hq 1/HɁ| L A7 0H| L A8 0Y UHHdH%( HE1H~{u,H~ utH~H52 觝uHHUdH+%( uiHC| L A 0H H 1rH | L A 0H| L A 0Yf D UHAWAVAUATSH dH%( HE1:Hs H5 HHYL%| A4$ LkfH HL IM0H1)))) DžHDž wHHHHA/ LE11HLaAƅm AM9HPAƅe H 11e11LLLA4$H L H H MM9MHD1覱H1 XM9o9IH H5I HA4$H M}HUK 1IO0LVIH HLLH I} @ 1H1LߗLL A4$M9| H H 1誰LWf{8IHx H5P HA4$ MuHJ 1IN0S]IHC AN8HL1 LGL?E I}?i 1H1LݖLL A4$M9 H H 1訯LVDh7IH H5B HA4$a MuHI 1IN0EH= IIH# AN8HL踝 A4$ HfI 1 A4$L A H H 1谮 MH Z H 1 苮LT^6IHA4$H* 1[1TO MH HY 1 +LT5IHA4$H 11dTO A4$ 1H@H ˭ A4$L A H H 1葭 @ L LL< I}n<Y 1H1LCLL A4$M9 H H7 1LvSf D D4IH H5 H=}A4$ M}HNG 1IO0襬H=c IGIH HL P LJ I}_; 1H1L4LL A4$M9tm H H, 1LkRff. HUdH+%( " H [A\A]A^A_]f. MH b H 1 蓫LQ MH 2 H 1 cLQ63IHnA4$H 131Q7 A4$H- 1 A A4$L 1A H H Ԫ @ 2IH7f. A4$Hh 1虪1Q D L%)x| H= 1A4$j1P두HC 1MLPHC 1-HPPHC 1 LuP`HC 1LUPHyC 1ͩL5PA4$HJ H@ 8QA4$ H H1~AuA4$ 1H= X A4$H% 194 ?A4$H 1A4$L , A A4$L A H H 1輨A4$L A H H 1茨A4$L A A4$H C 1Zf. A4$L B A A4$HRB 1&f D A4$L A 4A4$HB 1A4$H1 1קA4$H 1赧M D UHAVAUATSHdH%( HE1mIH H\IHH< HkHHf 0IIH] L5 L-HHj1 L- L-HHH1 LH5kHIYf HHH Lx-HH0 LHjHIf qHHH L--HH0 L- L -HH0Aą HLzjHHeH߃ `HEdH+%( l HeD[A\A]A^] L_eHs| L ~ A$ 2jP H H 1覥XZA @ LeH1s| L . A, 2jP D dH s| L A5 2jPHdHr| L A 2j Pjf. L+HH]/Hr| L | A 2j P/ L+HH%/Hvr| L D A! 2j PLo+HH.HEr| L A) 2j PL>+HH.Hr| L A1 2j PL +HH.Hq| L A2 2j PdHq| L y A 0H s H6 1KHq| L D A 0Hxq| L , A 0H`q| L A( 0HHq| L A0 0jIf. UHAWAVAUATSHh dH%( HE1jH[Hm H5 HIA[Hx- ذHHQ L- LL)B HHH= )B HHH HLADž B f. Ho HL蹛 B f.9 3 HA HL胛 A f. H HLMM %B f. H HL A f.s m H HL; %QA f. H HL諚 ff. Hs HLy5 -AA f. HJ HLC A f. H! HL 5@ f. H; HLיY ?@ f. Hl; HL衙 @ f. y HV; HLkG ? f. H@; HL5 @ f.m g H% HL2 ? f. H HLɘ ? f.E ? H HL蓘 ? f. H HL] ff.7 1 H HL+u => f.$ HU HL e> f. H) HL迗x ff.+ % H HL荗 ff. H HL[n ff.! H HL) ff. H HLU g= f. Hd HL %1= f. E LH- HL{ f. H HLO H螗HLH= \ H;[\H LH;H5 Las H;LH5 `t H;LH5 `u HC 1HH=7 ͉h H;[H H;LH5m |`W H;LH5c b`X H觖1HH=R fR H;e[HL H;LH5B `A H;LH54 _B j11w_H߈v&1HH= " H;ZHa w H5 H;LH HD_ HǕ1HH=6 膈 H;ZH v H5 H;LH HD#_ Hh1HH=l6 ' H;&ZH H61HH=3 H;YH/ H1HH= Ç H;YH HҔ1HH= 葇 H;YH H;LH5 @^ H腔1HH= D H;CYHj H;LH5> ] H81HH=q H;XH H1HH=N ņ H;XH Hԓ1HH=+ 蓆 H;XH H;LH5 B] H臓1HH= F H;EXH H;LH5@ \ H:HH Hđ HH H覑 f/ HH Hr f/ HHu H> f/ HHX H s ff.ztf/ H- HLΐ Hx ff/` H1HH= 蹄5 H;VH H;LH5 h[$ H HLCAŅ ff. LH - OLI,L, H OLI,L= H OLLI\, LLH{ 1cL;,LHL荏g -5 f. H=ͻ -6 HH:H) HL8e 55 f. H,EHEdH+%( HeD[A\A]A^A_] f(fT tI f. 5 w f.zf/ 5 sff.zH c| L A 0"fHb| L / A 0f. H HX 1A?Hb| L ^ A 0 Hb| L A 0 Hqb| L A 0 HQb| L A 0e D H1b| L A 0E D Hb| L A 0% D Ha| L l A 0 D Ha| L L A 0 D Ha| L , A 0 D KAV Ha| L H < 2j H P1踓XZHRa| L k AA 0H Hð 1聓HB^Ha| L K A 0)H`| L u A 0H`| L Z A 0H`| L ? A 0H`| L $ A 0H`| L A 0Hs`| L A 0HX`| L A 0lH=`| L A 0QH"`| L A 06H`| L A 0H_| L g A 0 H_| L L A 0H_| L 1 A 0H_| L A 0H_| L A 0He_| L A 0yHJ_| L A 0^H/_| L A 0CH_| L A 0(H^| L t A 0 H^| L Y A 0H^| L > A 0H^| L # A 0H^| L A 0Hr^| L A 0HW^| L A 0kH<^| L A 0PH!^| L A 05H^| L A 0H]| L f A 0H]| L K A 0H]| L 0 A 0H]| L A 0H]| L A 0Hd]| L A 0xHI]| L A 0]H.]| L A 0BH]| L > AB 0H H 1BAH\| L AB 0H HI 1AH\| L AA 0H\| L AA 0H 3 H 1贎AHJ\| L u AB 0H H 1yAH\| L ( AA 0H[| L AA 0H Hh 1&A<H[| L AA 0H j H- 1AH[| L AB 0H / H 1谍AHF[| L _ AA 0H.[| L Y AB 0H H 1]A%HZ| L AA 0HZ| L AB 0H HL 1 AHZ| L AA 0HZ| L AB 0HmZ| L AB 0H Hީ 1蜌AH2Z| L K AA 0HZ| L E AB 0H H 1IAHY| L AA 0HY| L AB 0H u H8 1AHY| L AA 0HtY| L AB 0H " H 1裋AH9Y| L R AA 0H H 1hAHX| L AA 0H Ho 1-AHX| L AB 0H q H4 1AHX| L AA 0HpX| L AB 02HUX| L n AA 0=H:X| L e AB 0H H 1iAHW| L AA 0HW| L AB 0H HX 1AXHW| L AA 0HW| L AB 0H B H 1ÉAHYW| L r AA 0HAW| L l AB 0>H&W| L ? AA 0H W| L 6 AB 0H H| 1:A^HV| L AA 0HV| L AB 0H f H) 1AH}V| L AA 0HeV| L AB 0H H֥ 1蔈ALH*V| L C AA 0HV| L = AB 0H H 1AAHU| L AA 0HU| L AB 0H m H0 1A:HU| L AA 0HlU| L AB 0pHQU| L | AB 0H H¤ 1耇AHU| L A AB 0HT| L AA 0HT| L AB 0"HT| L A 0HT| L A 0HT| L A 0HwT| L ` AS 0H\T| L _ AY 0pHAT| L A 0UH&T| L A 0:H T| L A 0 HS| L A 0HS| L A 0HS| L AB 0H h H+ 1AHS| L AA 0H - H 1讅AzHDS| L o AB 0H,S| L E AA 0H H 1[A|HR| L AB 0HR| L AA 0HR| L A 0HR| L A 0*fUHAWAVAUIATSHH dL4%( LuIL* HE1L@? EL L1 A艢L 1vAouHC0~kDž< E1L MLFQL.PHt tB uCAE LPHuLI \ <<;C0|E1* D AHkQ| H 1A01諃H&HEdH+%( uTHĨ D[A\A]A^A_]چ H@A8Q+Hj HHP| 01B)ff. U HAVAUATL@SH@LfHnflH dH%( HE1)Dž( Dž, HH Dž HhHDž cL HA 1 蠠foƅO )@E H LHH~ L0L~H1E1j A LHH5 LAIXZE 1HLH L,L(HLLu5(D,ou Ao H@O| H 101膁A(f D HO| Hb 01\AH'HEdH+%( HeD[A\A]A^] HN| H2 01 f. [HP 8(H HHzN| 01ɀh @ H Hx$LL HE9 HP 8`(H HHN| 01QHM| H A01* & UHt HHdH%( HEHM| 01HEdH+%( uɸ% H U HATE1SH`H dH%( HE1a fUH fEHd H`HpȞ HEHEHEHEHEEkrvEkravHhHDžx HUHE HE HE HE HEHE ff. @ sH;5#9C u0AHAu1HUdH+%( u4HĐ [A\] D HQL| DHc 101~h$ UHAWAVAUATSH HXdH%( HE1 IjIMt H H`L Hڹd Ld *HK| HH 01}HXHgL1HUdH+%( uqHĈ [A\A]A^A_]f. 1L1A 3A-f IcDLHHLI 3ALz9| &#f D UHSHdH<%( H}H= H= H= r H=g ^ H W HG H7 H=D # 1HUdH+%( H]H!J| L A. 0f. H M H 1F| HI| L A/ 0HI| L | A0 0 HI| L \ A1 0HI| L D A2 0mHnI| L ) A3 0RHSI| L A4 07r!f UHHdH%( HE1 HEdH+%( u ɿ k0! UH HHdH%( HEHH| 01{薙1 Z( jLf D UH5 HATSLeH N HdH%( HE1E 'LH5HMBH=I| ?M u&HdHHUdH+%( u0H[A\]ÐHH| M Hg 01Az D UHAWAVL L5b AUATSH`H L-G| dH%( HE1H5 HDž HH H(H H0H H8H HDž ( HDž @HDž@ HHHDžP HDžX MwIMtGM'd HL%Au 1IMH L yHLctHUdH+%( uH [A\A]A^A_] f D U; HAWAVHLAUATSHx dH%( HE1HhDž| HH˱{ DžX LHDž HpHpIF HcHyI HdIH H 1HE16.A*IcD AHHDHI T .AH/uA9|HIN||MnHpDHHhHl P H$Aą H$: P H$T H$& P H$^ P H$- P Hk$ H}?Hq?He?H&HEdH+%( _ Hx D[A\A]A^A_]f D HtcH |L $ A> H@HDŽŰ H D| 0H H 1EvAtf. L HC| L AD 0HC| L AF 0HC| L AE 0|H|C| L AH 0aHaC| L AG 0FHFC| L c AB 0+H+C| L _ AC 0HC| L D AI 0/f. D UHHHG HdH%( HUW(H5B| LG L 16RH tHEdH+%( u1ff. f UHAUATSHHdH%( HE؋FH@IHHи H9Ju HOIH9Jt HUdH+%( uFH[A\A]] @ HG HH2H B^uAU(u ADc ff. UHAWAVAUAATSHHH(dL$%( LeInD9uLHUH5LH]E T HUdH+%( H([A\A]A^A_] @ LmL59A| DH A 1A6usA6H 1_sKDm L-[ L<ff. @ HKL L LCA61H sL9uA6H= 1s1H5LS#f L5@| _ff. @ UH5 H 1H HAWAVAUATSH fo& foq& dH %( HMH fo e& fo5-& H0fo-n& 8HHPHH Hh) X)pfo%)& fo 1& ))Efo.& HHxH$ HHHH HH0HHH`HuHE)) 8)Ph])E;H IL LHI<$Q1HHu AoD$HL t HI:M9uH=4 1HH# H=w 0IHA H= 0IH fo$ HLfo$ A$fo$ e! LPL L2M LLe L L= LLde H L ADž& L5H9L9L9HEdH+%( z H D[A\A]A^A_] D HA=| L Ao 0H H 1poA H=| L As 0H<| L A 0H<| L A 0H<| L A 0sH<| L A 0XH<| L A 0=Hh<| L A 0"HM<| L # Ax 0H2<| L A~ 0H<| L A{ 0H;| L Ai 0f. UHH HAUATISH HL-;| dH%( HE1Au mHuHcAu u[HML9u2HX 1m HUdH+%( uDH[A\A]]MH 1m1f D HT 1km1BfUHAVAUATSH H $ H@ L-:| U H Au dH%( HE1HLH0HDž oCH L)EHH0H H1lL3% LL+Ht"HKAu 1LCH lL3HHLLLG D DA9 E9 H1E fH9Du HA9 LDHD L9tAu I 1H k1HHEdH+%( D H@ [A\A]A^] @ Au 1HT k D Au Hj 1k 1DE1 St" fJ HucII@ J McHtՋ HRuMcAu H" J j f. H~RtJ Au 1H jf D Au H 1je D UH=9 HAWL=x AVL5 AULATISb SHX dH4%( Hu1 ʚ;H= H=I ʚ;H=> H=8 H Jb^Hp LH= HH= oLL H 57| 13~iLLO3 L9u L9 H 1ISb L3iE13L%_ L1L iLL*O3 HSb H9 HH9 3H L1 hH w LHN3 HSb H9m H _ 3H H L1 ghH 2 LHuN3 H HSb H9 3H 1LhH LH N H uHSb H9t$31Hm ISb 1gE1E1H fo, LLfo * HLL))Dž Lfo D!fo fo ALfo H)Lfo Hl )fo ))))HDž V Lfo A!Lfo fo HHk L))HDž Lfo1 A!Lfo c HH Lfo7 )H)Dž foD L A!Lfo fo HH Lfo HHOh' )fo )fo Dž )fo H) Lfo A!Lfo c fok H)H Lfo fo fo )fo ))))HDž 23 Hq A!1zdEAD$HUdH+%( x HX [A\A]A^A_] @ 1H 1ISb )dE1E1H 1HSb dE1y H 1ISb HSb cE1DD"D"D"D"D"D"Yf H 1kc3f D 3H 1Ic @ H 1+cf D H 1 cf D H 1b UHAUATSH H $ Hfo H-XXXXXX dL,%( LmL)HL}H 0| 1LH 01abj E11j A H [| j H7 j H A[LAHUdH+%( u He[A\A]]f. D UHAWIAVAUATIHSH(dH %( H]HHufo LIH-XXXXXX A$ID$Hu LA gI9xD1L1贂 LTfHnHCflH D{1C C$ CHUdH+%( H([A\A]A^A_] D H.| H> 01`D LTHn.| H 01`HP.| L H 01`LaH".| H 01e`;L @ UHAWAVAUATSH H $ HXdH%( HUHIHHHHHU A1L=s L5{ HLHHHH9 H9 HBHA D D9t0H9-| HAe L A2PL1l_AYAZ {HAf LLH,| A A0j 1(__AX@ ; H=H HHH f D H9o HBHD At7HK,| HH Ai H! A0j1u^Y^ H&HHEdH+%( HeD[A\A]A^A_]f D HDž HHuzEa n ƅA oA' HY+| HE1Aj H3 H A0j1]XZf ~\` r u3H;H~ZHHHG HDž HHt(~u(` ƅPf D ` n AUs UHAWAVAUATSH H $ HxElELHHL| HDxLphdH %( HMH$( HE1HA 3HHHL E AD$Ѓ wnKD E1MlDHH9uɀ N HF:HHg HHHt @ Eh L9 D9|M HHE1A 4 @ HHHL(E AEЃ woKE1MdEHH9uˀ z ( Hx9HHA HHHvf D E L9r D9x HE1A 3 HPHL(E AMЃ wwK HE1MdMH9uǀ d H8HH} HHHrf. E HpL9t9HL'| HA MH H0 0W1 uY_AXlD9t8H'| HEA H Ӽ Hۼ 0W1 1YY^DhA8t9H&| HH A H 0@ǿ P1XXZHn!LDHEdH+%( He؉[A\A]A^A_]Ë HDž yHHF [ n ƅA HDž )HH y[ n ƅAL99 f H%| HEA H \ 0|HR P1WA\A]n HDž HH Z n ƅAL9uM D H$| HEA H 0xH P1WAYAZ H$| HMA H t H 01VA[[K D Ha$| HMA H , 0H3 1VA_X3 D Y D 7Y D pY ACAhA D UHAWAVAUATSH H $ HxEEIH|L HpLDxLldH %( HMHh A E1HHDMf IHI H1H9t]HPHD E AD$Ѓ vAD$wAWIMcM 뺐AD$B A7IMcM f N uAHA3HH8 HHHR HDž 1HHv L`tWM n ƅA @ MM9t7H!| HA H Y Hr 0AV1SA^X|D9t:HI!| HEA H# 0Q1H rSA\A]HHE1A D IHI HE1H9t\HPHD(E AEЃ vAEwAWIMcM fAEwoA7IMcM Hm1HH HHHO E ff. @ HpL9t9H | HMA H 0Q1H 3RA[[xD9t:H | HEA H 0Q1H v QAYAZHE1A @ IHI HE1H9t`HPHD E AD$Ѓ vAD$wAWIMcM @ AD$wnA7IMcM f D M H/HHf HHHK EV L9S D9 DlA8t9Hd | HHG A H + 0@ǿ P1PXZHLHEdH+%( ) He؉[A\A]A^A_] HDž HH6 iS n ƅA HDž HH S n ƅAAL9tMfH1 | H MA H 0H 1UO_AXD9oH | HEA H 0H P1 OY^,fGHR * D R D ~qL`QM vMAE|AqAMCM$ f. UHAWAVAUATSH H $ H @ HaaaaaaaadH4%( HuHƅ HHH> HbbbbbbbbHHHHHƅ HH H(E1E1E1 f D IcA@A HH9 x HZH(D2DE A uM LDL[H fo@IB8foPBD8fo`BD8 fopBD80foBD8@foBD8PfoBD8`foBD8p1MA @A ff. fMcLK\= HsHH IJ<8H@LE1A H= t>H| HAA: H [ 1A2h HO K[A\HL-* L%2 IH fEAat1HA< LLH| A0ja1YKAZA[IL9uHD A t9H| HA= H H A0j 1KAXAYHE1E1E1H(IcAD@ HH9 P HZH(AЅ A uM L牕LH fo@DIċB(foPBD(fo`BD( fopBD(0foBD(@foBD(PfoBD(`foBD(p1MA D@ McLK .Hs HHG IJ<(H@LwA H HL- L% IH EAbt/HLA@ LH| A0jb1)IXZIL9uHH+HoHEdH+%( HeD[A\A]A^A_]f. 4 c0 HM'H HHH 6f D 4 0 H&H HHH ^ H8Dž< 8HH ?K n ƅ4} D H8Dž< 8HHuJ n ƅ4 ~>$J @ ~>J hH(HE1E1E1fIcA@A HH; h HZH(D2DE A uM LDLH fo@IB8foPBD8fo`BD8 fopBD80foBD8@foBD8PfoBD8`foBD8p1MA @A McLK\= HsiHIH J<8H@LA IH|| HA9 H J HR A0h 1EA]A^f. 4 f0/ H $HK HHH FH(HE1E1E1IcA@A HH9 ` HZH(D2DE A uM LDLH fo@IB8foPBD8fo`BD8 fopBD80foBD8@foBD8PfoBD8`foBD8p1MA @A McLK /HsjHIH J<8H@LA IH}| HH Q A> HS A0h 1CY^ D 4 n0 H%"H HHH N H8Dž< 8 HH oF n ƅ4 D H8Dž< 8HHu%F n ƅ4 ~>$E @ ~> E hAwH(L7HDž "H(LHDž L1IH*LE1LI UHAWE1AVL5 AUAATSHdL$%( LeE1ff. D LHcH8HH=K EE#HH=? EEEEAA ujE1A1jLHͫxV4Sj A A j Až H=פ %H uAjA A; j; HͫxV4H= A]A_j jxL- Eع x 1A Ax LZY jL=l E11jAx L}AZA[ j A A1jig ͫ H= IAXAY Aj LE1Aj1ɺa Na AQj A A j Aľ H= #H uAEjA A; j; Na H= ZYj jxLDEA 1Ax x ^_ jLE1Ax j 1A]A_ j 1Ac Ajca [H= ZA[A\D HEdH+%( He؉[A\A]A^A_] @ jL= 1jE1Ax LXZj 1ɾͫ A jiAg H=# Y^Bf. jAx LE1j 1_AXj Ac A1jca [H= dAYAZ UHAWAVLuAUATLpSHx~w{ dH%( HEH Džl fHnHN flfHnH )pfHn~v{ Hs fHnH flfHn)E~v{ fl)E~v{ fl)E~v{ fl)EM,$1L/M|$HHL&u5HIM9uHEdH+%( u[lHx[A\A]A^A_]HQ | MILH I01<H_DžlM9bE D UHAWAVE1AULmATSH]HhdH%( HEH# HE HEH HEH HEHs HEH HEH HEH HEL#LLKIH M LHLx%t/LxMH; | L H A01u;LHIL9uHEdH+%( u1HhD[A\A]A^A_] Lɟ MufIL f. D UHHdH%( HE1HEdH+%( uɸf. UHHdH%( HE1HEdH+%( uɸzf. UfHAWAVAUIATISH HhHxLELpdH%( HE1)E)E)EH H= HIH 1HH H5w H=w LHHHEHHE;AątMH}H.L<H$HEdH+%( y HĈ D[A\A]A^A_] @ 1H1DAąu HhL;L9 L`D\Mff. Iu M$ H Mf D IwIH L"uMI$ H5{v LAƄ$ H@0L8X M$$L9uL`D\Hx H} Hp H H9t1DxIH}1L@H Mm L9uDxf E1I H=| LLM$$L9XH H9t-D`IH}1L?@HuJMm L9uD`f L`(Lx(M9gI|$Hu!t;M$$M9uGL`(Lx(M9tI|$Hh!t/M$$M9uM1DxL/ Hp M1D`L Hx HAt UfE1E1HAWL=~ AVLL5I LAUL-N ATLHSHPLHH dH%( HE1LPHDžX, L`HDžh )p F f.H H E1E1LHPH=/ Hg HHpfH HHDžX, L`HDžh HDžx HEHEX )Ub J f.H Hƛ E1E1LHPH˛ H=$ HH`fH HHpH HEHЛ HEH֛ HDžXd HDžh HDžx, HE HE HEHEX )]E f.H H= E1E1LHHXZ P f.H' ! H= E1E1LfHHLPHDžX, L`HDžh )p H= E1E1LHH H E1E1LH= HPfHHq HHDžX = H`HDžh )pe e f.H H= E1E1LL ǚ Lњ HHfLPL`HDžX, HDžh LpHDžx )uL L i S = f.H fMLHH@LL LPH=R LuHDžX L`HDžh, LpHDžx HE )E;^ f.@ =' f.Hc ] HUdH+%( g HĘ [A\A]A^A_]f D L- | L A Au L%ח H pO 1LH(2Au L A/ LHڿ 12p L-{ L Z A Au L%o H O 1LH1Au L ` A. L-N{ L [ A Au HL-1{ L A Au L% H N 1LHX1Au L A A, +L-{ L A Au L-{ L A Au L% H 8N 1LH0Au L o A- L-{{ L I A Au L-^{ L A Au L-D{ L - A Au L-'{ L A Au L- { L ؕ A Au L% H yM 1LH10Au L g A0 L-{ L A Au L-{ L p A Au L%x H M 1LH/Au L A1 L-T{ L A" Au L%* H L 1LH{/Au L A2 NL-{ L A Au L-{ L A Au EL-{ L ( A% Au vf. f UHHdH%( HE1HEdH+%( uɸf. UC HAWAVAUATSHXL'~7h{ dH%( HE1H EA,B,fHnHD fUflHE)EI9? HcGHI HljEHEHEIHL ML9t+ I ԴIH M?IL9uH | A$ @MEtM9$ }!UHu1LHAą[ E@9C L3E1L9u5Z D 8E A U9 M6AL9* DHML}EHcAL<L躵 HcEL|ŠIX Hx L! EuH{ P1lM9 _A O Hq{ Hʔ 01,AHEHuHL,E~ H;HdI9uH}VHEdH+%( HXD[A\A]A^A_]H{ H{ 015,E1H { HC 3,3M MDH^ 1+9H { H 13+IX 3ML@ H55 } LK~ LEH@~ tM9 u A HOH*{ H 12H j+AH{ 12H D+H{ H3 01#+jH{ L A H H2H 01*AmH{ H3 01* UHAWAVAUATSHxdH%( HE1HU H]IH_4LHLAE foX L={ Hctions} )EAGHEIH LpLuL&HE1Lj LA 1L5Y^A H3HLLl L1DlE5 AG臱IH H; Hj3LHLAE ECPI ?IHY H+3H50g H=1g HHLLHG+Aą HLQHALnE HEdH+%( y HeD[A\A]A^A_]L=q{ L H: l1H A7(LLXLпLDlA7L ѐ j APA Hٿ 1AHM\ Q(XZUf. L={ L 1H A7 (HH LyA7L j A AT L={ HY 1A7'L;[L=g{ H A7L j A AU2L=@{ H A7L g j A AU L={ H \ 1A} L Hٿ A7HD D'AL={ H 1L l Aj Hٿ AA7H:D &iL={ H ގ 1L - A Hٿ AA7HC &L=\{ H 1L A Hٿ AA7HC &L= { H ` DL={ H H Hf. UHHdH%( HE1HEdH+%( u1ff. f U HAWAVAUL`ATLSH dH%( HE1HƅƅDžDžHDžU;HHo CIH BIHk LHH8H5q L 1LL0II9t4ff. ff. f D B8f%f fB8HI9uLCAŅ L( I H0H H8sBAŅtO ALLHuHEdH+%( H D[A\A]A^A_]LFE1111H5p >E111HH5p 1 m LFAG0NH`HE1HDž HDž H I LH D(L f D HxHIH A>uEn9A9uEn 9A9uMnH5o L H5o L uLLDHH HL HpHS HD(L *AI E9o0LHMH H H]H LLIT;H HH(:;L5{ L(Hu HH 1A6"A6L LHg 1!A61 LL Hi L!L9!M9HH H9(AH9A EA D LL-CHHtxHLVx=HpHH{ H 01!H{ H H01 ZH{ H H01 2Hf{ H A01 H?{ HX 01 XH{ H 01\ H{ Hmn 01; AE1E1H{ H 01 vH{ Hn 01 H{ Hn A01 7He{ H֬ 01 UHSHVH dH %( H]HSH9HUdH+%( uH]+ff. UHAUATSH H $ H H8H@HHLPLXt&)`)p)U)])e)m)u)}dH%( H(1HHEIH L HH0 Dž Dž0 H`= L-{ Ee E~rHH D1 9 H=Åu+H(dH+%( u`H [A\A]]f Au 1HV D H5 Hlu @ UHAWAVAUATSL$ H H $ L9uH pR 1dL,%( LmAHPLHHL@Dž2H { HF A13D H HH(-E鹀 LLq 1L:E鹀 LL` 1:HEL Hǹ H0 1L:HEL! Hǹ H 1f:HEL HH8 L1.: LHDž@c ,L#H LAVILɅ 1 9L X_AXt]IH HIL Lw 1 9LK LY^ LLPE# HHHIHHLLHHHDžH HDžP LP HHH H5/ M LL L~HHr3H 1 }H= 1/3 HH 1KH Aƅ 3H 1H AHx ;' s HEdH+%( 5 HeD[A\A]A^A_]f D Ǻ9 H5J DH9t 觶Cf蛶;~H H=̓ 1H H81H= ; H8HIHl H5~t HHt H@HH5ot LHt H@HLH3H @ HHH @ HH H H 1u@:H{ H0HH Dž %$p 1 L HfoS HH@HPLWDžT HDžh XV L=W fo LLH HL)H \ H8tfol H8 L`f HIDž I(LfDHDž )LLDI9 L1 HLHH@LHHH 1H HDžIHDže HDž9` Dž8 Dž f艮L1Ҿ LfAƅ6 LtD HH9 A~ H0H(H= 1D ELLL% HH0M1AUH(LL]H AAtD fAn H8H= 4 H0IJ| H 謲 OH8蓲 C @ LتHH̪3H s 1H 3H ~ 1H A @ 3H 1Hx oH Dο 1HV bMH ~ H> 1C뒋3H л 1H %3H O 1H2 3H 1H 3H 1Hn2 3H $ 1H 3H ۺ 1Ht kVf D UHHdH<%( H}1tHUdH+%( u HEdH+%( u ɿ nf. f. D UHATI SHdH%( HE1%LH b} b} ~/1ff. f Yb} [b} 9HEdH+%( u H1[A\]Jf. UHHdH%( HE a} u_o)a} oF)a} oF )b} oF0)b} oF@) b} oFP)b} oF`)b} oFp)b} 1)a} HEdH+%( u获ff. U 1 HAWL=Ka} AVH(AULATL SHX dH %( H]1HHH HDž0 ƅHcH H fo LƅL8H)fo0H)fo@DžT LXHDž` )foPH)fo`HHH)Lfop)fo)fo) 軶HHDž @H 'HL HH) HA1I* 19s HLI1LHL" IM9uc_} Y_} 11 $ LH;1请Aąt HI9u⋽11$ ן ^} ^} 9 ^} L9=^} "H1ҿ L'HEdH+%( HeD[A\A]A^A_]f H@ 8舶Hy HH*{ 01yAqf D HH0 HH HDž( ƅL0H A* A1IH 1^DžyxH{ HR A01 H;1A A Hk{ L y H x 2j HA P1 XZKf D 軪AH@ 8]H HH{ 01N W H@A8H x HH{ 01 (H{ L }x A H x H* 01 YHs{ L w A 2j PH w H@ 1 Y^ 1Ҿ $ 1$H%{ L w A 2j PH { L w A 1RP떋1Ҿ$ 1ۜH{ L w A 2j PdH{ L A 2j PFڱf. UHAWL=K AVL5w AUL-~w ATSH dH %( H]1H$.HHtnL LL LLsg LL`_ LH=L IS LH=w 2uA ADžff. HEdH+%( He[A\A]A^A_]AH{ LH D8L@L=| 01L-ߧ| sE1Lc8HAD{ HPH8I5ɧ| JT 1AH@* LH| HHDžD ƅh蒤Džc=l| LE1LL EIDž DL(L0D1 1Ɖ E1ɺL担H8A H LHD01LH* LHD@DžD ƅh蜣H0H(LIHD H81EL LHD@* E1HHDžD 'LA< H81A4E1ɹ IT EH@* LHHDžD ˢǃ 蛥D蓥舥H LHD0 H(Hs D H{ MD 2PH AAt HPH001H H H0H(DH HAArfD踤譤H LHD0t H(Hr DžD H(Hr DDžHr A A A άf. @ UHHHO dH%( HE1H9u H~ HUdH+%( u}ff. fUHAWAVAUATSHL% { dH %( H]HA<$~HR{ HH0诐L{8E1M 1L5r ! @ LI9G ttLIH AG*<uIGHtH;C sA4$L 1L-{ HLIu Iu LAIGI9G uA4$Hq 1AH{ LH0L IH]HEdH+%( uHD[A\A]A^A_]*f. UHAUATSHdL$%( LeE1H9t(L HLH LH6t"HEdH+%( u"HD[A\A]] D H8E蜪ff. UHAWAVAUATSH H $ H8dH%( HE1K&H4 d d HI}IH: H{ LH0H LL5{ L 1H;p A6 LLoHHt HAUA E1AW1ɺ j Lj -H HH L{ HL螬 tdLAƅ A H{LLHEdH+%( HeD[A\A]A^A_]f D A6Ho 1AfLHH5 HDž HHHHH S(K(9BJv A6Hn 1A LH5&Ln# A L#H{ H<n 01"AH{ H) 01A6H$n 1AmA6LH 1 蘧 U H5 HAVAUATSHdH %( H]H n H蕺D HIE L5SN H5 LiHHI+LAE HL3 7H5m HHHAږE L-m Hm a LH5m HHHA虖E Hm La 輹H5um HIzL` HEdH+%( H[A\A]A^]f D H{ L l A 0H l Hb 1 f H{ L l A 0 H{ L l A 0 Hq{ L l A 0{HV{ L l A 0`u D UHATSHH{ H_dH%( HUHH(HH H-toHwtH HHcH 19{ LBL$H{ HH l 0M1 LHHUdH+%( uoH[A\]f )HvHt{ H3 01&HwHK{ HJ H3 01^ff. UHHdH<%( H}H/HUdH+%( uf UHATSH H $ HPdL$%( LeE1HHHIى¹ HLrLHj1HUdH+%( u He[A\]蔣 @ U HATSLHLHH dH%( HE1HDžx HLD HHxE1LA H=ZÅuDHxHuWH}H`HEdH+%( } HĀ [A\]ÐH{ H#j 01fHq{ A H 01 HA{ Hi 01]ff. f UHAVAUATSHH=| dL$%( LeIt&D)HUdH+%( uNH[A\A]A^] D L7L-v{ LAE( <| uLAE( "| 跡 UfHnǹ flHH@L{ H}HuH}dH%( HE1H{ )EHEHEЋ| HUdH+%( u>ff. UHHdH%( HE1pHUdH+%( uf. UHHdH%( HE1`HUdH+%( u躠f. UHAUATSHdH%( HE1{ H& HHG H{ H@ H/{ ?L-{ Au gA DH߉荳IHtuH LArH躭HEdH+%( HD[A\A]]f H{ HH0ޑ @ HVg 11AAu HRg 11f. HA{ Hf 101AbH { Hf 101c<f. f UHHdH%( HE1{I} HEdH+%( u D UHATS HdH%( HE1~H> 1:L% L LH} tHEdH+%( u H1[A\]g UHHdH%( HE1H} HEdH+%( u% D UHHdH%( HE1 D nH} tHEdH+%( u UHHdH%( HE1HEdH+%( u1諝ff. UHATS HdH%( HE1~H> 1L% LĤL 跤H { 1H}HLW H}1臟HEdH+%( u H1[A\] UHH }dH%( HE1LG} HEdH+%( t軜 UHH }dH%( HE1UG} Љ G} F} tHEdH+%( ti UHH }dH%( HE1E/HEdH+%( t* UHH }HudH%( HE1E } ~HEH HEHHƿ CHHƿ /E5E HUdH+%( t蒛 UHH }dH%( HE1E} HEdH+%( tS UHH }dH%( HE1HHƿ 菢E蕚 >f*fH~fHnwqE} tڸ HUdH+%( tԚ UHH }HudH%( HE1E } ~HEH HĞEtuE( &{ HUdH+%( tM UHHdH%( HE1HEdH+%( t UHHdH%( HE1HEdH+%( t UHHdH%( HE1HHE:D} B1D} HcHiVUUUH H ))хti2HEАHEdH+%( tb UHH }HudH%( HE1E?B } ~HEH HREC} PC} 9E|$吸 HUdH+%( t UH}HudH%( HE1c| Z| S| <{uH| ?| p| /| Ј_| D HH_HOHWHw H(Ho0HD$HG8H$HG@HGH HGP HGX HG` HGh HGp HGx L L L L L L L L UHAWAVAUATI SHdL4%( LuInH3 HHfo I$ A$ 7IH L{8I>LLHH HXw L)H9HFÃsKugt AAU uoM$ I$ 1HUdH+%( H[A\A]A^A_] LLILILHH AAU ALAL ALfALHa{ H;_ 01L|eH3{ H| 01vOf. D UP 1Ҿ HAWAVLpLAULATSHh dH%( HE1HH HDž HLHDž(e Džf g H IHtH Hھ HI81fEl$1A$ L LfAD$@t A| HCuHHuI9tWH{ MHH 01ELHEdH+%( Z Hh [A\A]A^A_]Ð H`LLxÅ f9 f9tH a{ H 133 H6 1 @ D H!{ A1A H H@ 2H T H { H] 13,f. H{ AA H @ H: 01H{ H: 01覓f D UHHdH%( HE1HEdH+%( u0kf. UHHdH%( HEHu xuPxub1HUdH+%( uiH{ L A 0H \ HQ 1H{ L A 0H{ L ) A 0賒 UHHdH%( HEHu[x Hx HxH HxP H Hx 1HUdH+%( H{ L A 0ff. fH [ HX 1H{ L A 0H{ L 0 A 0H{ L A 0Hh{ L A 0|HM{ L T A 0aH2{ L } A 0FQ UHHdH%( HEHu xuPxub1HUdH+%( uiHи{ L u A 0H Z HA 1H{ L A 0H{ L A 0裐 UHHdH%( HEHu3Pu{H@HH HuRu~1HUdH+%( H { L A 0H Y H} 1;Hշ{ L Y A 0H{ L $ A 0H{ L = A 0Ǐ UHSHdH %( H]H C HCHH H HHF H; H<u2H" 1HUdH+%( H] Hٶ{ L q A 0H X HJ 1멐H{ L 9 A 0H{ L . A 0Hq{ L X A 0HY{ L A 0{H>{ L A 0`H#{ L A 0EH{ L A 0*' UHATSHdH %( H]H ' Sg HCHH H HH C8a > L#AD$ ID$HH H uMHLRl AD$8y 1HUdH+%( H[A\]f D H{ L Ai 0f. H V HX 1 H{ L A Aa 0H{ L 6 A^ 0Hy{ L V A` 0Ha{ L rV Ah 0uHF{ L A_ 0ZH+{ L Ad 0?H{ L Ac 0$H{ L Ab 0 Hڳ{ L A Ag 0H{ L Aj 0H{ L a Ak 0H{ L Y Al 0訋 UHSHdH %( H]H C HCHH H HH& H;u5H 1HUdH+%( H]f. H{ L ( AT 0H T H2 1f H{ L AP 0Hi{ L AM 0HQ{ L bT AO 0H9{ L AN 0sH { L AQ 0XH{ L AU 0="f UHSHdH %( H]H {usHH H;G HGHH H H 1HUdH+%( H]f. HA{ L A= 0H +S H 1pH { L A< 0H{ L AC 0Hڰ{ L R AB 0H°{ L ) AA 0|H{ L s A> 0aH{ L X AD 0F諈ff. UHSHdH %( H]H S! HCHH H HH&' H;G HGHH H u.H 1HUdH+%( H] H{ L A A2 0H Q H 1뭐Hq{ L A, 0HY{ L A) 0HA{ L RQ A+ 0H){ L :Q A1 0{H{ L u A* 0`H{ L Z A0 0EHخ{ L A- 0*H{ L A3 0܆ff. U1HAUATSHdL$%( LeIH HL-P 8 H8 L~ { HLHHtc{cHuH{ L 2P Aw 0H O H 1>HUdH+%( uRH[A\A]] 1 @ H{ L O Ax 0 H{ L ) Ay 0賅 UHAWAVAUATSH8dH%( HE1觌 E1E L=5{ H { E7LSLEvLׅE AHA A7LDH 1.HCHt Є fIH# LmLHH3Lj 1A E1LZYUH A7AHE? 1H3LnmLH5 L uLELA7DH A 1 dEUDAHUA HUdH+%( unEHe[A\A]A^A_]fA7H ;uLcEgA7H 11HE衃UHAWAVAUATSH( HdH%( HE1 LcL-,{ AHIL=M @ Au L 1HVI9uA H Au Hڿ 1A)AuAu Hڿ 1H HH Au xYHHҼ 11HUdH+%( uLH( [A\A]A^A_] @ L-Q{ E1ZH f qHL 1U D UA HAWAVH@AUATSHH ,HdH%( HE1HA Ic¾ DHHH 41 5 (fIE1L-{ C1v D8AAAAu ,H 1 L0D<Au 18HK rAu D1HK XAu D1HK >Au D1HK $D<L0A@AA IEqEaEy(HEdH+%( u=Hĸ [A\A]A^A_]Hh{ , Hƅ 01yf UHAWAVHEAUATSH]HHL-{ dL<%( L}L=~ HEHEHE{f. DUAu E;7 IGH9Eq IG H9Ec E;W(Y HJ 1AIL' AG0I0 AGfvHMMg)HLEIc7 Aƃr AW,SHuHE нEu6HuHE 趽}u HuHE 蝽}Au HI 1,Au 1HI AILFAu 1HI ff. @ HUdH+%( HH[A\A]A^A_]f HaI 1DUAu 1HQI AILADUA9 DEAOA9 DEAO A9uuLEIO I9u8AO(A9KAu EHe 1 , Au 1DUH DUAO(A9fAu 1DUH LEIO DUI9hf D Au 1DUHB }DEAO DUA9#f D Au EH 1DDEAODUA9Au HG 1Au 1HG AIL0Au D1HH |ff. UHAWIAVAUATLcSH dH%( HE1 1AƉL-&{ A} AЉƀ H 1H˂ >1HuDž foE)`foE)pAM T LeL` @ DXAu 1D\A A QRH D\DXXZE9g DžTfoE)`foE)pA9 L I$IL$I3I3OH A UMց ҁ t/AE QA VE1H 1AYAZUMփ҃t.AE QE1 VA H 1_AXDUD]DDDf1f1tIAE DXE1D\A RHg V1eDXYD\^UMAAօNE9 Au ٿ H%E yf IT$IL$I3WI3OH Au H 1 A9TTHEdH+%( He؉[A\A]A^A_]f D Au HD 1 w1AH _D 1 H IMMgHB ID$yAu EEЉHH 1uKx UH ) H HHdH%( HEHu{ 01HEdH+%( u1xff. UH č H HHdH%( HEH{ 01dHEdH+%( u1,xff. U HPC HHdH%( HEH{ 01 D UHAWAVAUATSH(dH%( HE1o Lu1҉ljL-E. 1H P YiH` L-1P L 3iH 1 iH 111 hH 1LE 11 hH HHEL%{ 1L=B M A4$L111 |hLMH M9 Å7 1LE 1LP +hH 1 hH 1HP gH 111 gH 1LgE 1ɺ 1gIH A4$HL 1L111 \gHx M9 1HUdH+%( s H([A\A]A^A_]f D 11111gB :13 8tL%Ŝ{ Hy| H1A4$111 fHt&G80A4$ H@ H1A4$L @ A H @ H 1 8ԮL%%{ H? H1A4$c[f D 8蜮A4$ H>@ H12111 eHt&v8_A4$ H? H1A4$L @ A * 38 L%m{ HI{ H1A4$f D 8A4$ H> H1zC D A4$H={ [$f D 8蔭L%{ H> H1A4$#f D s8\A4$ Hg> H1 D C8,L%}{ Hz H1A4$f D 8A4$ HLz H1SL%&{ H= 1A4$gA4$H= 1KQL%{ H= 1A4$(]A4$H= 1 qf. UHAWAVAUATSH dH<%( H}H== ObH H@L-P{ Dž8 L%׆ H(H`H0H01E<$E1ɹ Mt$fo AHH(* )PD@DžD LHDžh heAu MD<AHHy 1 A|$ Au tc 1H= d IHm L9*HUdH+%( 8Hĸ [A\A]A^A_]Ð~,H< 1iDž8<gfH< 1=x Hf< 1 Dž8NDž8Sof. f. f. f. f. UH=; HHdH%( HU&Hם{ HEdH+%( u1Uo D UHATSHdL$%( LeAH={ H { ~Wub Hx; H5Ow 1 3ku/HEdH+%( upH[A\] ֽu2f EtHEdH+%( u6H[A\]f Hٜ{ 8 uċxNx[nff. UHHdH%( HEH{ 8t#HEdH+%( u H={ o^ @?m UHSH dH %( H]H`Hԫ H跾11H{\HEdH+%( uH]m UHSH dH %( H]H`Ht HW1H \HEdH+%( uH].mf. @ UHHdH%( HE1HEdH+%( ulff. @ UHHdH%( HE1HEdH+%( ulff. @ UHHdH%( HE1HEdH+%( u1mlff. f UHHdH%( HE1HEdH+%( uH{ H H !l UHHdH%( HE1HEdH+%( uHǙ{ H H@k UHHATSHH}HHdL$%( LeI {x.H}lH}[HEdH+%( u)H[A\] @ H{ LHھ H8螽Wk UHH HXH`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEH0Dž0 H8HPH@Dž40 HHdH+%( ujf D UHSHdH %( H]HޣHEdH+%( u HH]kMjff. f UHHdH%( HE1HEdH+%( uH{ H H@ j UHSHH HHHPHXL`Lht#)p)M)U)])e)m)u)}dH%( H81HEH HH(H@H0Dž Dž$0 H8dH+%( uH]3i UHHdH%( HE1HEdH+%( uhff. @ UHHLGdH%( HEHHGHGL9rCLO1IL1HIH)LHOHEdH+%( u*H { H H@ HEdH+%( ujhf. UA HHdH%( HE1HHG HHHw LGH{ HO(H fInflH GHtHUdH+%( u D HEdH+%( ugf UHHdH%( HEH({ H H@HtHUdH+%( ufHEdH+%( uzgf. U HAUATSHH=3 HL-a{ dL$%( LeI IM KI} Hھ LWHEdH+%( u H1[A\A]]ff D UHAUATSHdH%( HEH;{ 8 u;L-א{ HI H=13 IM I} LHھ ˸HEdH+%( u H1[A\A]]jff. UHH HXH`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEH0Dž0 H8HPH@Hg| Dž40 HHdH+%( uef UHH HXH`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1H{ : u>HEH0Dž0 H8HPH@H| Dž40 PHHdH+%( ud D UHHdH%( HEH`| H9I| u H=@| 1HUdH+%( u D |dff. UHHdH%( HE1H9=| u$H| Hލ| 1HUdH+%( u df. f. f. f. f. f. UHHdH%( HEHG@HUdH+%( ucff. f UHHdH%( HEHGHHUdH+%( umcff. f UHHdH%( HEHGPHUdH+%( u-cff. f UHHdH%( HEHGXHUdH+%( ubff. f UHHdH%( HEHG`HUdH+%( ubff. f UHHdH%( HEH H HUdH+%( ugb UHHdH%( HE HUdH+%( u+bff. UHHdH%( HEHGhHUdH+%( uaff. f UHHdH%( HEHGpHUdH+%( uaff. f UHHdH%( HEHGxHUdH+%( umaff. f UHHdH%( HE1HEdH+%( u1-aff. f U1HHdH%( HEH H9GtHEdH+%( u ɉ D H9Fu⋆ 9 ` @ UHSH HPt)pdH %( H8H_HEH?HH(PH@@0H0 Dž Dž$0 H菏SHcH9MH8dH+%( uH]`f D UHSH HPHXL`Lht#)p)M)U)])e)m)u)}dH %( H8H_HEH?IH(HH@ L H0Dž Dž$0 HkUSHcH9MH8dH+%( uH]2_f UHSHdH %( H]苟 u_|Hʋ{ x tEHx) Hp HuPH9tH9 uH Hu W|9LH?i9MHUdH+%( u-H] D H9tH9 u@ H Hui^f UHHdH%( HEHG@HUdH+%( u-^ff. f UHHH Պ{ dH%( HE1y tHH H8H L L9r*HI9r H 1H9 t$ff. HUdH+%( u< f tހy tH@ H{ H+@ R(uHH`]UIHAWIAVAUATSHhHUHHML%{ DEL LMA|$ dL,%( LmDmHEHGHE I I9X Lx谣H IL0LHuHEHEHMA|$ HcHuLxHAA At I9XG HI1L4AH AHMM ff. @ A|$) t I t$UIOL1HuL]AHcIU I)UIM9uHMMHLUKHELUIHEIBHEdH+%( Hh[A\A]A^A_] @ fUHuL HMHcIU I)UIM9tA|$) t I tAGtIWH fH*f*^딿 PA`IHt;MpHQ)f H9 u H H HHzHtI9uIG0HcLpM9PLUHL}H HpDxIf D I MI9tYIL9u IV0LrL9uuLLUDxHp A`OHc[ @ HELIGA AGf D HMMՐA|$) t I t}IwI?HukNfHtBHuH fH*YS H fH*^ff. UHuL HMHcIU I)UIM9aHMMnHփfHH H*XHfHH H*X]HfHH H*XY1,Xff. @ UHHAUATSH dL$%( LeIu_|H{ x tKHx) Hp Huvf D H9tH; uH Hu Q|9LL)LcHUdH+%( uO9It$I<$MMHHZ [A\A]1]fH9tH; u@ H HuWf UHAWIAVAUATSH(Hv@dH %( H]HH{ D( HK@Etz u_ H9r-HH9r!1z tI HH9XtbfHUdH+%( / H([A\A]A^A_]f D I H9rH9HH9X^ Hcf D`A~Mc LӝL IÝIM H IG0H0I9tSff. ff. ff. H HXh+ HH@H@0HcI H0I9uHC0H0H9t3H HXh+ HH@H@0HcI H0H9uE II H9r9H9rDHL9u1f LHEELEHEs f H D`AEE9Ic UH}iH} IXMUH@ H7 IG0H0I9tfff. ff. ff. ff. H HXh+ Hp@H@0HcIt H0I9uHC0H0H9t2H HXh+ Hp@H@0HcH4H0H9uIcHIt H9r8HH9r,E A9tHIt H9r3H9r5HL9u1LHEHMPDH}GDHE H)TLHME1UDH}DHcE1LE1CLE1C1f UHAWIAVAUATSH(HvxdH %( H]HHu{ D( HKxEtz u_ H9r-HH9r!1z tI HH9XtbfHUdH+%( H([A\A]A^A_]f D I H9rH9HH9XN Hcf D`A~Mc LÙL I賙IM H IG0H0I9tCff. f D H HXh+ HHxH@0HcI H0I9uHC0H0H9t3H HXh+ HHxH@0HcI H0H9uE II H9r9H9rDHL9u1f LHEALAHE f H D`AEE9Ic UH}iH} IXMUH@ H7 IG0H0I9tfff. ff. ff. ff. H HXh+ HpxH@0HcIt H0I9uHC0H0H9t2H HXh+ HpxH@0HcH4H0H9uIcHIt H9r8HH9r,E A9tHIt H9r3H9r5HL9u1LHEHMP@H}G@HE H)PLHME1U@H}@HcE1LE1?LE1?1f UHAWIAVAUATSH(HvpdH %( H]HHu|{ D( HKpEtz u_ H9r-HH9r!1z tI HH9XtbfHUdH+%( H([A\A]A^A_]f D I H9rH9HH9XN Hcf D`A~Mc LÕL I賕IM H IG0H0I9tCff. f D H HXh+ HHpH@0HcI H0I9uHC0H0H9t3H HXh+ HHpH@0HcI H0H9uE II H9r9H9rDHL9u1f LHE=L=HE f H D`AEE9Ic UH}iH} IXMUH@ H7 IG0H0I9tfff. ff. ff. ff. H HXh+ HppH@0HcIt H0I9uHC0H0H9t2H HXh+ HppH@0HcH4H0H9uIcHIt H9r8HH9r,E A9tHIt H9r3H9r5HL9u1LHEHMP<H}G<HE H)LLHME1U<H}<HcE1LE1;LE1;1f UHAWIAVAUATSH(HvhdH %( H]HHux{ D( HKhEtz u_ H9r-HH9r!1z tI HH9XtbfHUdH+%( H([A\A]A^A_]f D I H9rH9HH9XN Hcf D`A~Mc LÑL I賑IM H IG0H0I9tCff. f D H HXh+ HHhH@0HcI H0I9uHC0H0H9t3H HXh+ HHhH@0HcI H0H9uE II H9r9H9rDHL9u1f LHE9L9HE f H D`AEE9Ic UH}iH} IXMUH@ H7 IG0H0I9tfff. ff. ff. ff. H HXh+ HphH@0HcIt H0I9uHC0H0H9t2H HXh+ HphH@0HcH4H0H9uIcHIt H9r8HH9r,E A9tHIt H9r3H9r5HL9u1LHEHMP8H}G8HE H)HLHME1U8H}8HcE1LE17LE171f UHAWIAVAUATSH(Hv@dH %( H]HHut{ D( HK@Etz u_ H9r-HH9r!1z tI HH9XtbfHUdH+%( H([A\A]A^A_]f D I H9rH9HH9XN Hcf D`A~Mc LÍL I賍IM H IG0H0I9tCff. f D H HXh+ HH@H@0HcI H0I9uHC0H0H9t3H HXh+ HH@H@0HcI H0H9uE II H9r9H9rDHL9u1f LHE5L5HE f H D`AEE9Ic UH}iH} IXMUH@ H7 IG0H0I9tfff. ff. ff. ff. H HXh+ Hp@H@0HcIt H0I9uHC0H0H9t2H HXh+ Hp@H@0HcH4H0H9uIcHIt H9r8HH9r,E A9tHIt H9r3H9r5HL9u1LHEHMP4H}G4HE H)DLHME1U4H}4HcE1LE13LE131f UHAWIAVAUATSH( dH %( H]HHsp{ D( Etz u[ 9r*H9r 1z tI HH9XtXHUdH+%( H([A\A]A^A_]f D I 9r9HH9X Hc D`A~Mc LˉL I軉IMY HP IG0H0I9tMff. ff. H H@0HXhH0+ HcI<I9uHC0H0H9tsff. ff. ff. ff. ff. H H@0HXhH0+ HcI<H9uE II H9r7H9rBHL9u1 LHE1L1HEC f H D`A_EVE9MIc UH})H} IMUH H IG0H0I9thff. ff. ff. ff. H H@0HXhH0+ HcI| I9uHC0H0H9trff. ff. ff. ff. ff. H H@0HXhH0+ HcH<H9uIcHIt H9rFHH9r:E A9tHIt H9rAH9rCHL9u1ff. @ LHEHM/H}/HEN H?LHME1U/H}~/HcE1LE1k/LE1`/1f UHAWIAVAUATSH(Hv`dH %( H]HHk{ D( HK`Etz u_ H9r-HH9r!1z tI HH9XtbfHUdH+%( H([A\A]A^A_]f D I H9rH9HH9X> Hcf D`A~Mc L3L I#IM H IG0H0I9t3H HXh+ HH`H@0HcI H0I9uHC0H0H9t3H HXh+ HH`H@0HcI H0H9uE II H9r9H9rDHL9u1f LHEt-Ll-HE f H D`AEE9Ic UH}H} IMUH@ H7 IG0H0I9tfff. ff. ff. ff. H HXh+ Hp`H@0HcIt H0I9uHC0H0H9t2H HXh+ Hp`H@0HcH4H0H9uIcHIt H9r8HH9r,E A9tHIt H9r3H9r5HL9u1LHEHM+H}+HE H;LHME1U+H}+HcE1LE1{+LE1p+1f UHAWIAVAUATSH(HvXdH %( H]HHg{ D( HKXEtz u_ H9r-HH9r!1z tI HH9XtbfHUdH+%( H([A\A]A^A_]f D I H9rH9HH9XN Hcf D`A~Mc LCL I3IM H IG0H0I9tCff. f D H HXh+ HHXH@0HcI H0I9uHC0H0H9t3H HXh+ HHXH@0HcI H0H9uE II H9r9H9rDHL9u1f LHEt)Ll)HE f H D`AEE9Ic UH}H} IMUH@ H7 IG0H0I9tfff. ff. ff. ff. H HXh+ HpXH@0HcIt H0I9uHC0H0H9t2H HXh+ HpXH@0HcH4H0H9uIcHIt H9r8HH9r,E A9tHIt H9r3H9r5HL9u1LHEHM'H}'HE H7LHME1U'H}'HcE1LE1{'LE1p'1f UHAWIAVAUATSH(HvPdH %( H]HHc{ D( HKPEtz u_ H9r-HH9r!1z tI HH9XtbfHUdH+%( H([A\A]A^A_]f D I H9rH9HH9XN Hcf D`A~Mc LC}L I3}IM H IG0H0I9tCff. f D H HXh+ HHPH@0HcI H0I9uHC0H0H9t3H HXh+ HHPH@0HcI H0H9uE II H9r9H9rDHL9u1f LHEt%Ll%HE f H D`AEE9Ic UH}{H} I{MUH@ H7 IG0H0I9tfff. ff. ff. ff. H HXh+ HpPH@0HcIt H0I9uHC0H0H9t2H HXh+ HpPH@0HcH4H0H9uIcHIt H9r8HH9r,E A9tHIt H9r3H9r5HL9u1LHEHM#H}#HE H3LHME1U#H}#HcE1LE1{#LE1p#1f UHAWIAVAUATSH(HvHdH %( H]HH_{ D( HKHEtz u_ H9r-HH9r!1z tI HH9XtbfHUdH+%( H([A\A]A^A_]f D I H9rH9HH9XN Hcf D`A~Mc LCyL I3yIM H IG0H0I9tCff. f D H HXh+ HHHH@0HcI H0I9uHC0H0H9t3H HXh+ HHHH@0HcI H0H9uE II H9r9H9rDHL9u1f LHEt!Ll!HE f H D`AEE9Ic UH}wH} IwMUH@ H7 IG0H0I9tfff. ff. ff. ff. H HXh+ HpHH@0HcIt H0I9uHC0H0H9t2H HXh+ HpHH@0HcH4H0H9uIcHIt H9r8HH9r,E A9tHIt H9r3H9r5HL9u1LHEHM H} HE H/LHME1U H} HcE1LE1{ LE1p 1f UHHHHMHH dL%( LUDUuH|H[{ HxH u1E1AAEDHEdH+%( u4DUL D HEdH+%( uDUA Lf. UL L@ H HHdH%( HE1j)KHUdH+%( us. UL TL H vHHdH%( HE1jJHUdH+%( u#. UL L H HHdH%( HE1jJHUdH+%( u- UL L/ H VHHdH%( HE1j 9JHUdH+%( u- UL dL>/ H HHdH%( HE1j IHUdH+%( u3- UL L H 6HHdH%( HE1jIHUdH+%( u, ULn H HHL ?U{ dH%( HE1jIIHUdH+%( u, UL tL H VHHdH%( HE1jHHUdH+%( uC, UL H HHL T{ dH%( HE1jHHUdH+%( u+ UL Lw H vHHdH%( HE1jYHHUdH+%( u+ UL. H -HHL S{ dH%( HE1j HHUdH+%( uS+ UL 4L H HHdH%( HE1jGHUdH+%( u+ UL H MHHL _S{ dH%( HE1jiGHUdH+%( u* UL L7 H HHdH%( HE1jGHUdH+%( uc* UL H mHHL R{ dH%( HE1jFHUdH+%( u* UHHHV{ dL%( LUDUx u^ LHvtEHUdH+%( uWH v DH LHML+ 1H١f G| HEdH+%( u DUFj)f. UL DL H HHdH%( HE1jHUdH+%( u) UL H ]HHL oQ{ dH%( HE1jIHUdH+%( u( UHATSHdH %( H]H Q{ H H{h fHnHh fHnH flfHnHH flfHnH flfHnH( flfHnH flfHnH flfHnHx flfLnH flfLnHCXfElfLnfElfElDSX- H D H Dx H H W H8 ( " H HX H H Hx h N H HQ{ H8Zu2L%S{ A|$ 1 .A|$ utA|$ uTA|$ u$HEdH+%( H[A\] HEdH+%( H [A\]- -A|$ t @ - -HuO{ 8 h r- h-O V-H 1HE-A|$ % H fHnfl @ Hx fHnflx @ H fHnfl a @ HX fHnflX , @ H fHnfl @ H8 fHnfl8 @ H fHnfl @ H fHnfl X @ H fLnfElD !fH fLnfElD fHChfLnfElDSh$ UfHnHHHGdH%( HUHVXfHnflHWFXHHEdH+%( u@$ UHOfHnHHHGdH%( HUHVhfHnflHWFhHHEdH+%( u#ff. UHOfHnHHHGdH%( HUHVhfHnflHPFhHWHEdH+%( u#ff. UHAWAVAUATSHdH%( HEHM{ H8诏 L5K{ IHHZIL`L9 L-GL{ 6 D HLAUHt H HID$XM|$XLHXM9tJIHI A tHC`HKXfInflHAHHCPCXHtHf D HEdH+%( uH[A\A]A^A_]}"ff. f UHAVAULoATSHdH%( HEHGI9 IHXf D HChHXI9tcH{( uH{ tI$LpI9t"HCHHt_LHЄuIFXLpI9uH=I{ HyHChHXI9uf. HEdH+%( u<H[A\A]A^] @ IFXHPI9tHBXHPI9uH=OI{ Hxp! UHAVAUATSHdH%( HEHH9teIHXLwID$LhI9t"HCHHtfLHЄu*IEhLhI9uH=H{ H.}ff. HCXHXI9uHEdH+%( u0H[A\A]A^] IEhHPI9tHBhHPI9u ff. @ UHATSHHdL$%( LeIHHxHZL9u ^ @ HHHO`fHnHGhflHJHHWhGXfHnHGpflHBHHGPGhHtHSXHCXHJL9uID$IH0HxH^L9u a HHHOXHW`HwXfHnHQflH HOhHWpGXfHnflHQH HGPGhHtHChHPHChL9uHEdH+%( u H[A\]e D UHAWAVAUATSH8dH%( HUHH HH9 IHXA E1Lu7 D EAD$LLDDHE1SIH AHCXHXH9t>{x uH#tLHAuHCXIH HXH9uf HaF{ ~B,u$HEdH+%( u"H8D[A\A]A^A_] AfE1V f D UHAWAVAUATSH8dH%( HUHH HH9 IHXA E1Lu@ D H"u;EAD$HLDDLSAHCXHXI9H tE1HwtDHUdH+%( uH8[A\A]A^A_]1 ff. @ UHATSHHdL$%( LeIiwuUH="u0 w' H33 HcH>f C| HEdH+%( uKH[A\]ÐHEdH+%( u2HLH[A\]f D C| C| f. UHAWAVAUATSHHH dL$%( LeIHH9t)HX HL&HCXHXI9$H uM$P M$P M9tNff. IFMnHXI9t'ff. @ HLe&HCXHXI9uM6M9uHEdH+%( uH[A\A]A^A_]ff. f UHAUATSHdL$%( LeL%kC{ I$L9t?HXLm HCXHHXL9t LkH}Љ ?,tHEdH+%( u H[A\A]]4 @ UHAWAVAUATSH8H}HudH%( HEHG{ x ) L.L9 HGHEI HEHEH@L`H9E I f L tHuL= Et$xEuLm AƄ2 M L9 A$ M?L9 A9GPuL6 H EuAGT IOHpXIIwIW HH`HxXH1IO(HphIw(HPhHHpH1ID$hL`H9E*Mm L9m1HUdH+%( H8[A\A]A^A_] X VgIHteDpTA$ IAGPjI fHnA M fHnflAL8 D HuLT<AUIE H9EEH H9Eu7f. @ UHAWAHA AVAAUATISH(u dH%( HE1sE~-E1f H? L1A FE9uߋEHcۅ~CE1L-PA ff. EHJ rL L1AHHD9uuH~ L1HHHUdH+%( uH([A\A]A^A_] @ UHAWAVAUATISH HXDm HhH@ dD`LPdH%( HE1HDžx HE~.E1L5> L L1 AE9uHcH> dtH" L1HHË` L5 L1LHPHXLLcL LHI1IHcL D Hh1ɺ H"IHdC{ x LLG LJ]HxnHEdH+%( HĈ H[A\A]A^A_]f D H ? Hw L1 HHYf HhL@ 1Lc.LM HxHU 1]L- 2Lx& UHAWAVAUEATISH HEHX H`DuHX> lDhHPdH%( HE1HDžx AE~*1 Hw< L1 AA9uߋlIc߅ DpL=v E f. hH DrH< L1wHHE9 H = LL1 ALHHD9luH`1ɺ H IH"A{ x LL L[Hx,HEdH+%( S HĈ H[A\A]A^A_] @ L5 L1LHPHXLLcL LHI1wIHcL+f H`L@ 1L+LM HxH 1ZL-] Lx E1L= < L-t ff. @ hHa: DsH L1A LL HLH1 HHD9luHUHAWAVIAUE1ATASDH H0HD H D,dH%( HE1MAL$Dž I Dž LЉ(1ۉMz HI+@@LMhI+@8L8HA@,A@0 mgL8HH , DL8H0L8HMxIHI9tlLE1D8MEI ,ELL8D(APH0 M$$YH^M9uLD8H8{ x Ip D(AL$D,H H0E H=_8{ HË9G ff. H18{ Lx HEdH+%( W HeH[A\A]A^A_] IP@AL$D,H0Ip D(EwH57{ HË9FgL H7{ x uH !(M;H I9+H@1 H=-| HHLMH 7{ x8u"Mt IE Ht@p)E,AD$E1DD(HO| WH0 AHXZ)f UHAWAVAUATSHH dH %( H]1H L6IIML IHH H HH@ H HH L8M! MM I1LbLHMAIM9tyLLMILM̐H{ HH1ɺ |H9 LH1HHIL9uLLMLMGIM9tiLILM D I " LH1ɺ H LH1SM?HII9uLLHL@LxM9tlLILM I LH1ɺ |H9 LH1M?HII9uLLHL@LxM9tlLILM I LH1ɺ H LH1SM?HII9uLLHLxLHM9tlLILff. I Z LH1ɺ |H9 LH1M?HII9uLLM~IM9tYff. @ I LH1ɺ H LH1cM?HHM9uMt$IM9tJL= I~ wfLH1ɺ L LH1 M6HHM9uHEdH+%( HH H[A\A]A^A_]f D M6M9uf D M?M9Y M?I9 M?I99 M?I9\ M?I9 HL9,qr fUHAWAVAUATSHX HdH%( HEH 7{ LhHHw MLDE1H HHA Hh LM MM MM MM6 M:MQ HI7LLLLH0I_HHLLIAILLL9H HHLLLLHHLIDMI @ I|$ wGH1ɺ L?H op HIDI 1HE 1HIM$$M9uMHLMLLALHIZMzL9 HHLLLHHLIDMII|$ wGH1ɺ L_H o HIDI 1He 1HIM$$M9uMHLMLLAHM{I[I9 HHHDLILHHLMIff. I|$ wGH1ɺ LH n HIDI 1H 1HIM$$M9uMHLMLHAMyIYL9 HHLHHLEMIff. @ I~ wIH1ɺ LEH m HIDI 1H E1 HIM6L9uMHMLHAMxIXL9 HHHHLMIDIf. I|$ wGH1ɺ LH m HIDI 1H 13 HIM$$M9uMHHMALzHZI9 HHHLIDIff. I wGH1ɺ L@H pl HIDI 1HF 1HIM?M9uMHMAHYLyL9twHHLMIfH{ wIH1ɺ HEH k HIDI 1H E1HIHL9uMHEdH+%( uHX L[A\A]A^A_]f UHAWIAVAUATSHH HH8dH<%( H}HHtHI#YH H+{ E1Dž HHx LHLD8E1L8:E1Dž HDDž DžP LLHb HAHHHHH+A@H+A8HA0A,\XHHH H+ LHHH1^HËtELE1A݉L%) L L1#AAD9uDHLH4 L1H LLcHh HHX1HHcHcLHYLLiL4LL9t[E1HLEIċHHE苍PL8LAPHHZIYL9uLHH8H@HHx u HA@H@PHy E1T H@E1LIL0LHDž( Dž, H M IELH0H I+E@I+E8H AE0AE,(BVHH H L1\AċtIH ' E1LMID D L L1 A9uMLPIcH+ uH) L1H LHH1HX LA1HHcIcHHIMHHHIEHH9 HL f,{ Dž LHMH L1HDž "Aŋt>1LA܉ H& L1A AD9uLMc14H ' H` L1 HIōC TH rH& L1eHIŅt tH b L1H:H@H0LHcaH 0 LHHH1LHL,HH1ɺ p A|$ H; LHL DHHHLH HH9;LH@A~ Hu IE@HTI} E1\HlDžh HDž HDž HH HAHHHHH+A@H+A8HA0A,hRHHHpw H1 LHHËt6E1 H# L1A VD9uHHHcE1 HX DrH;% L1AHHAuHXL1L HHLaHHQHL9v H({ HE1LxIHHHff. H L1HDž _Ët21ɐ L1H" 4Ã9uEHcAE1 H* L1DD`HHHAu E 1H # LH\ D`DD`DHcHAHA lD`DDMH! L1?D`DHHHH H ' L1HHHLHc&H LHHHHH1HHH1ɺ L3IHx LLAL @HM$$HM9HLxHA~ Hu HA@HDlHy 1E1AD%Dž HDž IHHM{ IBLLxHHI+B@I+B8HAB0AB,XNLxHH`Y LLxLxIIRMZL9 Džx LLMAIHf. xHELLH AxPH eHAZIA[H L9LLuDMIA~ } DELHIr A IA;^tL`MA~ n LMA;FtHpH&A~ LH HH,HH,A;FtLMHHL0H Lx HHHIŋ;FtHHHHDLLx H 1E HUdH+%( He[A\A]A^A_] IR@EIr DALzIA9^A~ HHH9uH1 H=o| HHHhLA~8u0H t&HH Ht@p)ȉ\EE1LA H| PAXAYIf D A~ uH Af. L@ 1LLLL L1HHHv 1<L LLH@ 1LL" Hپ 1LHH H ;nHbA~ uH tlhHH9H1 H=| HHHhA~8u0H t&HH Ht@ph)\HL 1DlH HDž iE1AAŅt9DEAHھ L16AAD9uEDIcE1&H 3 L1AHT HHEH rHh L1HHAuL- L1LHHLAL L1v1ɺ H=| HL W { H=| IAy LL/L 29HVHcIcHHcHHHA~ uH iT]HHx H Ѓ!P!HH9@H1 H=:| HHHhHHx8u$Mt IHt@p()\TH LHDž L% 11ɉA΅t!L L1AD9uߋHcH L1H LHHyR H1L L1L%| aL LA1LH@HLpL L11ɺ H=J| HH=1| IH { x | LLL 6HHcIcHcHHHcHHHcHIL@ 1LLL 1LHH L- 6LH V LAIcML98H1 H=| HHLhyHHx8u$Mt IHt@p)\HHE11L8H| LPIXZAoE8fofsffH~H98MeIEHL9b H { H8 H{ 1E1Dž Dž HHH L HH1 HJ E1ɉHDDMAHL1 Aċ9uڋD 1HǺ LMDKH L1ۉ1+DMAHL1 Aċ9uDMD L1H HHHN HH{ HHS HH1ɺ LH LH1]Hx H L14HHË;BL M$$AL97 EuH{ H8 H L1t`HO E1ɉHDDMAHL1 Aċ9uDዝMDL@ 1LLL 1LHH L%_ 24L(H{ H H8suHxyuBxmu<M$$A L9u,AHHI] w11LLWVE1H HHHHaL HHl{ HHCQ H` D H L1 (H L؉1 H{ 1Dž Dž H Ht>H5{ 1HHH{ E1Dž HHLHa{ E1HHf. UIHAWAVAUATSHHHm{ dL<%( L}I׀x # H { HO@@ ) L H LM311LMHHH5O ! HUALMHu H>HH H L1A LkHULLEHU LE1LLLcHU LI1bHcuHcEHLIHcIH { LeD;pTHUV H HH{ @ H LMH LM1H5N E1HUILMHu Lx=IHt}I]HULAHH LE1HLLcBHU LHE1[Hc]HMHLHHH { H]D;psHUX D HEdH+%( ueHHH LL[A\A]A^A_]If H{ HM 1017A1HEdH+%( uHHH[A\A]A^A_]ff. @ UHAWAVAUIATSHH8H{ dL%( LEIЀx tH Z I LxI9J HK{ L3LEA HPHH LuHHEEHE8f D AW(LHLE;HHH)CIGXLxH9E Ax uLM udEAD ut%HsH;HG 1HME HHH)CH{ LHLHxH gIG HZЉWLLuIGXLxH9Eaff. @ LuHD)HUdH+%( uH8[A\A]A^A_] 17 UHf HAWIH=T AVAUATSH Hx dH%( HE1H)HDž HHDž MHx{ H q{ @ HIH_H@ IH B Hhc HE1HpfH!{ Dž LpHHLhH9 MH LD f D IH 1IEXLhH9 A}x uLucuuHxLLpDLLHAUuHxH^yf LLuIEXIH LhH9cf Hx AH*Hh@ A9}) Hپ H=i @LIH @ H@ HUdH+%( HĨ [A\A]A^A_]A` H@ HHX؈8 IP HBLjLpI9txHpH H LHE@f. LE11LLAVHI1HxH IFXLpI9uHpH IP 1H`H9R LpLxff. HALyLhI9 D_HHPHhDMAT HpE11LHhE1AVHH C LH1 IFXLpI9t_A~x uL0u,EuHc L1zf. HpL!uIFXLpI9uHPH H`H9Hht$H L1}HhLpHx H=ӭ I8 H{ H8MP MjIBHpI}L9 H H; LHE@LLPL5: LHhAUHxL H8L 1IE H9pLPLht}LHXHxLPL8 D HhHaLHPLAUM$L H18IEXLhH9puLHXI:H`1HH9 Hp D HGH_AL`H9 HhD_PH1 AHpLLA E1AT$AID$XL`H9t:A|$x uLtLLuID$XL`H9uf HhPHH?H`D9ABH90H@AH HxH HHHEH8L H1Hٺ H= #G Hx H=% L%Y FIH HLpH9 LpLxff. A~x uoL ; HpHLE1AVÅ ff. @ L. A$D9uHp1HH IFXLpH9yHx H#Hٺ H= FHh@ LIHx1L AH rXHx Hr L@H{ ALH815 HpLHpHH L LQE' UHAWAVAUAATSHcH H6 <L`D;\dL<%( L}L={ MgH})H6| H ] @-[...fP1H| HI HtYDžX E& <tLHDž 9X|9H=| HEdH+%( % H H [A\A]A^A_]ÐHIH Dhf L(HPH LLMV0Mn HDž HCL9ICM:HhJ @ HLH%LH\/ HPM fHE E_ )EHpHhM HxEy A A LHIH LpHL#HP1H`H LHAfA t ; McL <tXX9 A I L ~IH A uA IZI Mb(LHLHH A tIRpL"Mx/fI*Y Hx@fH*^ZQ LAfHL H*XYv HyHfHH H*Xf D \HLHHLHHA ` ~8: u/L@H`1L j AH LHfH`Lr? H1 LHZ\<LHFXX91f. HP6 H9z 8 I H`LHH8HHSH{ HH H1LH @ HPLeHHE L)EHEHhHE'} LH@HPH`H 1 uLHHH A MwHtI A HhHO L= HPLH @1L@D0LHHpHxHL@IP HH)HpHQHHxHHH9Lb MHi LLpIELL H@(D0AD (^ H@H?7 19HLLHHpH)xIH @ AT$(LLH0*HpIT$XHxHHLbH)HpHxH9H EVHLH0H H(W AT$(LLH)HpIT$XHxHHLbH)HpHxH9Hq H@H26 1,HLLHHpH)xIH xID$ HjЉhIH HLLƅ0 ID$ HЉf D LLL M HH)1HPHpH`Hu5 Hx L@LHgL@LHAI HH9L` MH LpH@IEL(HPL5Ǣ LHAH0LKfAT$(HH0LH`I 1HHAID$XL`H9 t?HhIH HpLH@H(HxuID$ Ht @ H@LIH` EL@LH%L@LHAA tfA t A IcH D I E1LeE1D@MLHLP f D AEII;syM HhfLeHHE IH HEHH)EEn} uH`L 1H E@AEII;rMD@McL f D f H`HXfL0L(M A` L8 H L@LHL@1HpHxL@LHH H`LHLHAI4 LLHH`HHLHDHH HDž HDž H;z , H= H*9o UHAWAVAUIATSH V H(HudH4%( Huȋw0uEE1E1MYf DffH}H*EL Ya H H*ȸ ^/HIIIStiDHHIZtHz GD0x) tEtMt } pH}LH 1 IHIISuHUdH+%( uH(L[A\A]A^A_] UHHW.dH%( HEHz G fG$Hz fG&)fG(HEdH+%( up U HAVAUATISHdL,%( LmIH5 H=*{ IL5={ HtL t$I>I HuE1LR LIIHtؾ, HxHt HxHcHHH{ HHSLc1HUdH+%( u H[A\A]A^]x UHSHdH %( H]_0w0蘹HEdH+%( uH],ff. UHHdH%( HE1@t 5 t) u f/) 2 s1f. @ƃ3HEdH+%( utff. @ UHHdH%( HE1HEdH+%( uG" b&]ff. f UHHdH%( HE1HEdH+%( uG"G G.ɍ< &f D UHAWAVAUATSH(G$dH %( H]HEW`4 EH t Dk&E1Ds$vAEJ1HHHIĿ xEEt-E1DDH!E9 a A E9u1?EES(A { s")MC. u6HsPHt-HEdH+%( uoH(11[A\A]A^A_] HEdH+%( uBH([A\A]A^A_]f. ` AR E9)N @ EHf UHHdH%( HE1HEdH+%( u HkFf D UHHdH%( HE1HEdH+%( u HH2 D UHH H`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEH0Dž0 H8HPH@Dž40 HHdH+%( uMff. f UHAVAUATSHdH%( HE1 IItCHG u{H! HLЄt HI;\$ ID$xHuH_MuM~k D H HLЄtHI;\$~ ID$xHuIsI\$HEdH+%( H[A\A]A^]f 1ItH[fHLЄtH[I;\$tID$xHuIf 1HX ID$xH4HLЄ$H[I;\$u1ff. UHAUATSHHdL$%( LeItwHt^u,eHMl$M~8 HIsH{HEdH+%( u5H[A\A]] @ t)IHHf D H D UHAUATSHH_dL,%( LmIHt^E1HX HHt(D1Ls DHLAUhAE(AD9uDHUdH+%( u'H[A\A]] I}_HIE1Hujf. UHHHwdH%( HE1H;7HUdH+%( u# UfHHdH%( HE1HEdH+%( u HGp11ff. @ UHATSH1HdL$%( LeI1 8 HX HEdH+%( uS$HLH[A\]ojf. UHAUATSHHL-z dL$%( LeIL HLHEdH+%( uHL[A\A]]ff. UHAVIAUATISHH HHLPLXt&)`)p)U)])e)m)u)}dH%( H(HCXH HL-z LQLHH{@MLLcH!LHC@HELLH H0HDž Dž0 H aAą:LAH(dH+%( uBH [A\A]A^]f. H{HL1 Hz HCX UHATSHL%z dH %( H]HLBH{HH{@HEdH+%( uHL[A\], UHATSHL%z dH %( H]HLҵHLHEdH+%( u H1[A\] UHSHdH %( H]H1 H* Hz Hs@HHHD1HEdH+%( u HH] (H UHAWAVAUATISH HH8L@LHt))P)`)p)])e)m)u)}dH%( H1HEHL HHLH HL5= L-G Dž Dž0 ye D L8HLLdtH-HdH+%( uUH [A\A]A^A_] HELHDž HH HDž0 ;1ff. UHATISHdH %( H]H @ L`HtHUdH+%( u H[A\]Vf D UHATISHdH %( H]H @ L Ht tH5z ȍPE<YHEdH+%( u H[A\]ѿ UHHdH%( HE1 HG HEdH+%( u HwHGp1膿f D UHAVIAUL- ATSHH z dL$%( LeAff. H(L01H3D#B A thA u^v#fA~* t vv uAƆ f D HUdH+%( W H[A\A]A^]à t+wЍ IcT L>f D INAv(A H1H9MJ<H9s HHL)H1I>LIV AVp IFHAv(H9 H)HHIVH LI)AVpf AV*fAN,9pfAF,c fA~* AF,fFfAF,9f A IH9INAV(HIHH9H LINAVpLȜ Av(A LHHcH9I HNH)HIFAVp 1I LAVXIv@LfI~H"h IHTIVHIH9@HHLIV AVp H1bQ UHAVAUATSHLwH_dL$%( LeIL9| HtwE1 @ ID$xHt HLЄu*D1LDHLAT$hAD$(AD9tHI9uDHUdH+%( uhH[A\A]A^]f I HLЄtHI;\$t"ID$xHuI\$I9S1f D 1I\$I99If UHHdH%( HE1t@t#uHGHGHEdH+%( u*f D HWHHDHGHHwѺ UHAWAVAUATSHHGLodH %( H]HAM E1; sdL=z P HCxHt Iu HЄu&D1H DLHShC(AD9t AID; s AA9rHEdH+%( u&HD[A\A]A^A_] LkLk\ff. UHAVAAUI ATASEHdH %( H]؉3LDDID){#HEdH+%( uH1[A\A]A^]g3bf U HSHdH %( H]:3HEdH+%( u H]13 UHAWIAVAUATASH H(dL,%( LmIH9 2K(HSIHI9 E1L9s EA)D)ADDHFD"DDH0L;k l AT$DH q HAT$D + nf D +2HS 1I9 C(IHI9rhAEDH߉M MA<W"DDH C(HCI9 HEdH+%( H(1[A\A]A^A_]1EA)E D EUHA)DD) l DHAT$ uAtMHSDD)& D EHA)DD m HAT$D E/HS6f D m AT$DH~ q tHAT$Dd + Z蠶 UHAWAVAUATSH(dH%( HE1~1IEƿ AAԉ`0IGEt7B#HH9 HEdH+%( H([A\A]A^A_] D DH9rA)AULD t LDD HEdH+%( H(1[A\A]A^A_]/ @ )EuLDU t Ky"d @ LD3 rDDA+w9|DLu l uLD YP @ DA+w=f. UH=HHdH4%( Hu1H5{ HA H { H{ ={ 0H5{ H H { H{ ={ H5{ H H { H{ ={ H5{ H H { H{ ={ H5{ H H { H{ ={ H5{ HtxH { H{ ={ gH5{ HtSH { H{ ={ BH5{ Ht.HEdH+%( u0H { H{ ={ D HEdH+%( u肳f UHHdH%( HEHz tH~(HUdH+%( u;ff. UHAVAUIATSHH@Hz dL$%( LeAHW8@LrI)D'H5 z E E1Ҁ> Eu UHc LfHnC$H]H ~Hz fHnH=u HU H}LflE)E~Gz fl)E7} tL HEdH+%( u#H@[A\A]A^]f D ʃ" [ UHHdH%( HE1HEdH+%( u ۱ff. UHH H`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEH0Dž0 H8HPH@Dž40 fHHdH+%( u ff. f UHHdH%( HE1t 5 t7 u.HG8Hz H@RH)H2 ;r0t 13HUdH+%( uɉU萰 UHHdH%( HE1HEdH+%( u [ff. UHHdH%( HE1HEdH+%( u @, UHAWAVAUATSH8HW8L-z dL4%( LuILbAEI)_,A} u I$D`$Hz Dx uS4 LVAF(1DLH^HEdH+%( q H8[A\A]A^A_]f. M H5V UMIGLEIF8HHHy-HMOHMUHlAEIHLUI)IE @$EܯAIw8I} UH H5z > A @`uEI} E tHz E x j 6 LU5EULMIE @@UutE觳IGpHx(HP HUz 8 ff. ff. f HBpHx(HPtHMHUHUM HrHMH IHI MEuE1L9uA)ȉIE @@tE f HBpHx(HPt Y H2l A @\uEpE Iw8H= W D UHAVAUATSHHHG8dL,%( LmILpHz HLJ @MI)LLLL I $HH9 Lpf I A ~^Hxz f@@w=HcIHH)Iff. D H8_f(H9u f/v I H) f. z H H/ Hz Hcp@HcH H4H)H \f/wVHBHt=HHA LXf.zuH8H9uHBHuff. fHBf. HBHuHBI~xfIVxLA H8 I $fIFhLpH9LSLH HEdH+%( uDH[A\A]A^] IFxIFxf D HBHSHL1^茪ff. UHAVAUATSH H $ HPHV Lo8MedH%( HE1Ho HXz Mu@@ Hy?z HPIF ML$-@ L @ L x L1 "11H貗8 HS$LH߃賺X1ZHUdH+%( uWHe[A\A]A^] Hz A H H~w H81&Hx Ef. D @ UHAWAVAUATSHH H z dL$%( LeL'HXHG8IH@H)L(L9t@Hz IL 8 t@H{(tH{0IHt LHuWH[L9uH=v 1 H{0IHt L軺Hu H[I9uH=v 1s D L$Av&DfHnfflAt0Ht+H_z : twfH[H{(tHIFtHuI^ AƆ AƆ HUdH+%( uFH[A\A]A^A_]ff. ff. f D HtHH[4D9uIF蠧UHAWAVAUATSHH H Iz dL$%( LeL'HHG8IH@H)L(L9t@Hxz IL 8 tAH{(tH{0IHt LTHuWHL9uH=Iu K 1 @ H{0IHt LHu HI9uH=u 1tf D L #Av&DfHnfflAt0Ht+Hz : twfH[H{(tHIFtHuI^ AƆ AƆ HUdH+%( uFH[A\A]A^A_]ff. ff. f D HtHH[4D9uIF UHAWAVAUATSH H $ H H $ H & ~S;z LoHHLH=sz HhLWLdH%( HE1H)HPHHCƅfHnHHflfHnƅ)~z fl) HH HHH@M HCLp A H9 AE+ H=Es ,HPL5z HBFJ(HA> f+ HH HpHHXHXH>z H8@H)HhH1HtXH HpIHH` LLAǃ HLL M A> M}j AuPL牵x0 xfHnffl)tQHtLA> HB)ff. ff. MH@H@H@uHLL ƅ D L膖ADž t" |ݍ@uwH n HcH> @ A ff. fA A uH(H H(8 H Hh L H@H9H HEdH+%( HeD[A\A]A^A_]fHH0HJA LHL Iu-L1H=Lp AzE1AF@u Abg AF@ @ A z ` A x L M` A> M} AuLL牵x xfHnffl)tAHt<A> uPHB)f. HM@H@H@uHLƅL MI(tHtHuE1퀽8 9 u;H9DH @o H5Po H=Ro U <9 /L H=P E1H z x fP E1HHz LHH+Lz@ HI)LxI LA> IcP` I9~Ex\HxL LL0HH A @( L0A@\HL) E111腥H`L!E1HAv E1HH5L| LH=z H VLL| @,P1Y^E1H9DH m H5m H=m ~9 qLiB\E1AvHHCE1HAv/*E1HHXT E1AF <CAF E1H5o L }E1HXH贾E1H(H "Hx(! L@@M LH Ul @ 1L LeE1AvXE1AvK HLMt<M;m t6AtdAAGu H=~ HcH> @ AtvA AGu H HcH>f D = = MKLSIHGH蛐I* AuP9 MI(tH'u AuL x @ D HxL9L0LLNHALR,Hމ L0IcP`HHL)H= HH! @ L\ H= oML莽IHH6If D HLHXH+z Dh {L)H@,A 3 E1A ^ E1 Ab AF@ D L` HpLPLLE@ #L(MIGLEL AA HKz Iw8PHH@H)H8HHBH9t.1A> tgH H9tdHHHHhHAH9uH=h 1ff. ff. HHhHHAH9tH; uLHxLxh3HxffHnfl)HtCft>A> 9 ff. ff. HtHM49uHLƅI HH9u/ ff. ff. H H9k DH`ExHcP`IAbAF@ A Hh HhHxsHH8 :H= D @ HPH8AbAF@ eHfz A H )g HCf H816H9DH f H5f H=f 9 H=Uf H=n HhHL iI@H9u ff. H@H9 x`xlH=P &f D MI(tHHuE1E1dE1Hh UeHh BRA gL LH ܖff. UHHdH%( HE1HEdH+%( u`蛖ff. UHAUIATISHdH %( H]H111詮 HEdH+%( u HI HL[A\A]] ff. @ UHAWAVAUATSH H $ H HXdL<%( L}L MIGH Hz ILg8HRH)HI|I IpIH Ao$L)`IGHpHXLH` Mt$Ml$Haz @@ H*z HPIF LMM- L*c @ L @ 1, LH聙XZHEdH+%( He[A\A]A^A_] D HEdH+%( HeH= [A\A]A^A_] LHEdH+%( u_IwHeH= 1[A\H-A]A^A_]靃 D HYz A H T H6b H81ގH0 f. UHHdH%( HE1HEdH+%( u`˓ff. UIHAWIAVAUATSHHHG8M`dH4%( HuȉL L M ILeHMILEu2 @ 1H5b L1%fLGM$$MR M9pE HEI9$ 3 Ic$ HMHE A+hHHHAL@IEXHH@Ht5M fI*Y H fH*^EuLLE+EL؉艩H:z LEx u(x EH5a L %LH5ya L1 HfHH H*X_fLLfHH H*X" LELeAH ID$(IT$ It$H9H5y H` HEHH5 HDHA|$4At$0D RL PLAt$ H5` 19H HEdH+%( AW$H5 HeL[A\A]A^A_] Ht#It$H9HM` H5 HEj @ ID$L -` LAL$4H9H AT$0MD$ LEH5 ` 1螩df LEH . @fL衧A HLPyLEIHHH5_ LA@ D 1/HEdH+%( u AW$H.ff. UHAWAVSHdL %( LMIIAX4~zDX0L IHD @ IcHHf D I9tDH9 u;Hc MzXHM4ω+ HIHIAE~D8INHHHuAD9uHEdH+%( u H[A^A_]_ff. @ UHAWIAVAUATISH( H8HudL,%( LmE謱H\ Hc IIFH3 MfH}LLEn H MT$H fHnL fHnHMflAL0IT$L9 AEA LeI։EMDmILEDEHuHLL M6AM9uMLeLDmEIT$L9tA( DM贰HthH ~EDh DMH fHnflA HHEdH+%( u3H8D[A\A]A^A_] @ A AL}A覍f D UI HAWAVH LAUfInATflSHH H~"z dH%( HE1H)HHpH=[ ƅNfHnHƵz LXDž flH)>Hz fox t H9 HX( L8L L II\$H IH Hc OIGH I_HLLAG $HML$(LM7IGL8It$(Dž I9t LIL( 舮HH Hc HCH L{HHC HHMGHL3 HCHIwI9 LILL ( IHa Hc ID$H; Ml$HLAD$ HHH LIUI $ID$L MuA L9 HL( FIH Hc uIGH MwLI^HAG HBHH LIIGL8MnA I9 HHA LH Mm AL9uI;^t=( }H HH @ AHHHPHE M6EL9LHI;Ut=( H HH @ AHH0HPHE` Mm HDI9LL M9otA( 葫H H@ HL0HPH M?L9LLIt$(I9 ( H H@ HL0HPH D L H1HtXHXHL L̖ LH LJ8P 1. LL1HӐ LY^ 11Lu8 LpHqz x x HPercent HLML% L LH5V LPHV PHs P1DLL'H XZb HYz> FusHHxL HSamples H?o= , hW HH5p eoi=`HHLAHLI $LM9t>IT$fHnI|$IflHSHA$ШLIvHLM9uHEdH+%( % HeD[A\A]A^A_]= 5DžPeriDžiod 1L% HxAŃht@~ = t7߃qtJ= uA < RuHLId뙃q'Aq XM>bA> LL tL LHtL DƄLtf AQUL DFf. D UHHdH%( HE1f9w(HUdH+%( uH UHHdH%( HE1HEdH+%( u1 ff. f UHHdH%( HEHG@HUdH+%( u̓ff. f UHHdH%( HEHGHHUdH+%( u荃ff. f UHHdH%( HEHGPHUdH+%( uMff. f UHHdH%( HEHGXHUdH+%( u ff. f UHHdH%( HEHG`HUdH+%( u͂ff. f UHHdH%( HEH H HUdH+%( u臂 UHHdH%( HE1HEdH+%( u1Mff. f UHHdH%( HEHz @t H9 HUdH+%( u UHSH~y dH %( H]LA t ~x A+ uCHH{ 1RL H:Q X|CXZHEdH+%( uH]f D A- kff. UHSHdH %( H]H_`H uHuHt[HLCHKLKI9t/I H9t`ApyH9tH:1H9t=IHApyH9uLH^HHuHEdH+%( u$H]ÐHC H@ HC H@螀ff. UHAVAUIATSHH H@t)`dL$%( L(LcHEDž H`H0DpH Dž0 At$ I<$HsH;LD 菧HI<$H5 A1觘H(dH+%( uH D[A\A]A^]ff. f UL L H }HHL Ǫz dH%( HE1jHUdH+%( uC ULK H HHL wz dH%( HE1j詛HUdH+%( u~ UL~K H ]HHL 'z dH%( HE1jYHUdH+%( u~ UL.K H HHL שz dH%( HE1j HUdH+%( uS~ ULJ H =HHL z dH%( HE1j蹚HUdH+%( u~ UHSHdH %( H]HH 觫fC$HEdH+%( u HH]}ff. @ UIHAWAVAUAATSHH8HU~y LMdL4%( LuA t~x A+ E1 t"IB(HtHz E1RH)H8 AS$AEEHDLU)U4 t LUHE5 IL @H1DHyDH5 H跍1HDH5 胕AH+HEdH+%( u+UHuH8H[A\A]A^A_]c A- P| U1HAWAVAUATIHL H dL,%( LmIMAMtlMvHc1LH)HK LIx M 芣I LM AHuK 1IcH)L_AA u2LHEdH+%( u;HDA\A]A^A_]f. IcLH(K H)I<1AK{ff. UHATSHHHOz dL$%( LeIHx Hͧz PID$0H)H8 tzH H H I|$ dAăqtu5H H t?HUdH+%( H[A\] H HߋpHEu1 D H HߋpHނH61fH HZ D H Hp ػ1jz @ UHAWAVAUATSHhH~dL$%( LeIH> xHDhdMcLHHo I|$ H% wHcI HLH19AI<$Hu=It$HHhi1HUdH+%( He[A\A]A^A_] @ Hz H HH9uH@B H@B L} HpE)L葈LE HpLLxrHIcIcLxHM1 HAPLH XZ+ I|$0Ht>H-轃DhdMcIL$0E1HH-H6H Ad Ad }:xf. UHSHH HvdH %( H]HH <HԪHEdH+%( uH]1w UHHdH<%( H}H~( HEdH+%( u1wf D UHHN<HVdH%( HEH H ǜHEdH+%( u1?wff. @ UHAVAUATSHHL dL$%( LeILdA@ HF HI1L荞Mt HLHF LH)H<1kHEdH+%( uH1[A\A]A^]v UHAWAVAUATISHH8 dH4%( HuȉHD@ AcAL4IHz x t H9 8 HLLHH@DLL< L p H A HE MEH1AVsLH5h LLc1茎H L L XYHt`AƄ$ E HH譬DLL HH A HQE LE1LHIAT$$LD) EtI$ HEdH+%( He[A\A]A^A_]f D HIHHH % H9 @ H IHvH9ul @ 2 LH4Hct UHAWAVAUATSH dL$%( LeIuFI$0 HA$& AƄ$$ HEdH+%( H[A\A]A^A_] I$ I$ HHA$& E1gHtH<HAHgHHtL5&z @ HHHbHCHSL{DhyH9tHS HCH@yLAF tuL;sff. UHAUATSHHz dH %( H]Hx uj LktTHsH;Ht 1L 舚HI} H5y A1蠋HEdH+%( uCHeD[A\A]] O| HL z HL ? jH AXZirf UHAWAVEAUAATISHӺ H EHXHLP H߉lHE L}H`dH%( HE1HDžp HDžx *~IHz x ujE L`LHL狍lEAHpaHxaHEdH+%( HĘ [A\A]A^A_]fL@ 1HLL@LH詉LH1H@HxH@ QL > 8LxE1fHPHXL@ LLH7tL 1LHHpHjC L= Lpp UHAWAVAUATSH H $ HH H= dL$%( LeE1脨HH H|IH LL E1LHH HHf D LHH xuHHHHLIĺ HǾ HLG H1Q LH5J bIXZMtHL HvH s L|A CH=~ 1u^L 1LD萕D9 AMcMIO<7 D LI蛑M9uIff. HH{L9u f. HOIcHHHDH]OHHHt AI<H=} 1]L{L8EAHEdH+%( ujHeD[A\A]A^A_]HHNIHt.=~| L-Öz uMe E1g| I} ]H=} 1]mff. UHHdH%( HE1 t$H=m} 1\1HUdH+%( u Lmff. UHHATIԺ SHH dH %( H]HVyIHt^Hz HHH#E L@HH< MLD1xMHHUdH+%( u\H [A\]fHMt$IL1 HB? 軳y1 HH 1 蚳y1Mlff. fUHAWAVAUATDSLH HEH}HLXLuHEHE xHEfMdH%( HE1Hkz x MDLE_DeH HHE9EH}H xDdD}@|D}Hp HGH}HEH}HpLoHwI9$ HhE1A Hu> D HIH}HED}DЄ + Mm HEE1I9tEu } DEA}y tA}x + t- IHu|HDLLEHuAVDuH}PEA!8fEH D}T D Hh-uEALO@Hw H}xLXDHuAVu fED}H D}H}HEDЄuHpfDdED)HUdH+%( u7He[A\A]A^A_] D oG8fofsffH~H9Ei UHAWIAVAAUATSH HEL@LXH`fhdH<%( H}H HP]LPH0Hz x I L Hz E@ LhHM`L0DLXI @LhH HXy tM HUdH+%( He[A\A]A^A_] Mb@T I LPE\LPH1HtHLHHP辽ƅHPHLHu!oB8fofsffH~I9hDHPLH @ K H8H0H]@ HHxk1Hپ HxH? ˮ+ H7 E11E1HxHDž( H@HLLLXDH DhH(A%WL WAfhHHH`LЄ HP HPHH8NHDžx HPHXH HHXHHf I LH]ZDPLHHH HLPA λLPHu oC8fofsffH~I9AhDHIL DLXˉPM5 ID$LH YMt$I|$Dž8 HA I9 H(LLAJ HIE DPH`DLЄ A+X HE1H9(m Eu H 8p{y A t{x A+ tA- IE HwHHDHAUL0L@A!VH ufhH Dh4 @ DL PD) @ Dž8 R @ HDž( H8LPLpM9 H(A L1L L 1HMM2f Mm M9t7HxA HLHHHuMH 0 I~ME1H8LpLhM9 L8HMLE D M6H8E1I9tVHxHLIA 9EIEHuIMH a0 HxH( D IMHI DHLD)G @ DH`LЄ7L LDIT$I|$H9tAH(HK HIE DPH`DLЄA+xHE1H9(eEu H u8p{y A t{x A+ tA- IE H{HHDHAUL0L@A!VH fhH Dh8Dž8 vE1A 1IRaff. @ UHAWAAVIAUIATDSDH \_$dH%( HE1fA A Hz z Є9 A$ u#LHpxHpxA& A% H HB1fE9}(tzHf LLALHHLHDž PXZ# tI M I ftB1HEdH+%( He؉[A\A]A^A_] @ HuDžT ƅ[ DžT ƅ[ [1DLxL肵I xHH HH9L` E1HHLphMDIHxP @ A 4 L h TR IF HpHH H`LH`HpLhͳHchH5 1LLwƅh +DI DIFXLpH9H HxfA~x HDž )LHDž HuHpL`L :c` AE,Dz9I Dd @ HDžT ƅ[+f I M I f D PLpH5D LA x ڻ nD\A[-2x1 @ LL腀`I H5E L1v HhLAV(HhHpLLL1H5 uf [L1H5. u5 Lsaf D HE1HLpHxHMDƅhIH`Z 4 Lh F T IF HL HpH`LH`HpLhڰHchH5 1LLtƅh +DI DIFXLpH9H HxfA~x HDž )LHDž HuHpLPL G`Pu%AE,Dz9I Dh D LLP7~PuI <1H5{C LsIF HHpH`LAV(H`HpL蒯LL1H5R ~sf ZLp D [L1H5k, =s DžT ƅ[-;5Z D UHAWAVAUATSHx dL,%( LmL IH P Hh, HHDž| Hp @ HpfA@ HDž HDž HLDž )tHKz z y HH HLpH9 E1 f. C,EgD9rHL|LLAVHHHHH)HH u 1HlA 蓀HHH)tqH EHH IFXLpH9tSA~x uL]LLL{9H HH IFXLpH9uff. D|1HDA(F8 HS$HpH߃%iHhD|D9x ~NL 5 D HpHv@ 1 HcHH)oH JHEdH+%( uHx [A\A]A^A_]Wff. fUf H@ HAWAVAUATSHx L dL4%( LuIH)A$` HxHDž p1HHDž ~HcHH)m M$P HE1 HICMkHXI9 LhLEAAF,D9bHE11HHSHHHHH)HHt41H> ~HHH)tE1HCXAHXI9uLLhE MI$P I9~ LHLp HA HAHYLxH9 f HE11LLAWHH HoHI`HII9tHPLBHIcHH)HtnE1IGXLxH9t^Ax uL Z E^HH1H| |HHH),ff. HHH HH9t2HH1H! W|HHH)Lp11L^B8 L1AV$HxLZeHEdH+%( Hx [A\A]A^A_] D LLEwpHHU L HLL@1{LHcHH)7Sff. UHATSHH EdH%( HE1H D H Lc(GH H(z z tHSpL"M fI*YM HxdfH*^Z u /E H舨HtsH{HHo1HUdH+%( H [A\]ÐHfHH H*X D LAfHL H*XPH1趍HH fD HkSR UHAVAUATSH D dH%( HE1E H_IIH A$ I|$EEEH HID$1f H M fID$Itu t1 t( )L9\ 1I)f A$ H1ErEHHHuff. fHEdH+%( V H [A\A]A^]H HX0H_ )f D t ff. MA$ ]ff. H8lHH\H Lp(DH H$}z z tHSpL2M fI*Y J HxxfH*^Z u/ErMI\$I A I1 HL9 1M,f @ HfHH H*Xsf. LAfHL H*X4fH I|$jH^yA$ HmHuYh ffI*YH H fH*^Z u /E HjHH H Lk(NCHtiH{z z tHSpL*MyLAfHL H*XYfH HoHfHH H*XZ fR 1 1I\$f MI݄= HL9=Df I\$ f ID$1f MfUHAWAAVDAUIDATISH `_$<dH%( HE1A HDž fLjI H@` L8@tI M$ I$ A$ uLA& ƅg et A% <e-ggH@ A" 1DL?f tA$ p 4 L"`LD4@H׳ DHHHD)9]I HP HFHLpH9 f E1HHXLxDIIƅpHhHP gH5 L1dXIF HxHH HXLHXHxLp:HcpH5 1LL d+ƅp B+DXIFXLpH9P HxL HhfA~x HDž )LHDž HuLO AD$,D{9C A$ 4 LGp XH52 L1@c E1HHXLxDIIƅpHhHP g1H5 LbXIF H1 HHxLHXHXHxLp芞HcpH5K 1LLob+ƅp DD艅XIFXLpH9P HxL HhfA~x HDž )LHDž HuLMT AD$,D{9 4 L襌p 1H5S1 L狝XaIF HHHxLHpAV(HpHxL]LL1H5 Ia @ D3 p ALxXu 8HHLDt@DD)YAD$,D9 Hff HDž HxHH)HDž HtA$ 4 L_I HLpH9t|p LtMgH5w L1L=`IF LLLH )IFXLpI9 t HH LXf A$ HHL ڻ WD<A Ae t HEdH+%( 0 He؉[A\A]A^A_] D LLic HpLAV(HpHxL:LL1H5 &_D AV(Hx)vH5Ƨ LH1^H pz Hff. H u 5 L{/f D LLh$ H@15 LE10`LD4@H DHHHD)GVI HP HFHLpH9 5 Lˈgf D fE9|$(+HfALH@`HDž LLLHH'PXZƅpE1oD UHAWAVAUATSHh dH %( H]H. LcMQ H fHx E @ LP /wSD}A} A A$ LH,AC(D}D9 E$ EF f D L1~IH A$ uL-Ppz Mt$A} `I$ M|$(7H A} tIT$pL:M fI*Y = HxwfH*^Z f AƄ$ RfLHUEC(M93HEdH+%( ' EHh[A\A]A^A_]f D HfHH H*Xtf. LAfHL H*X5uHD{$E$ uH Au` JMa 1Hח4 HڅGlm H5 HDE) SH D}LP IGIOE1HMLhH9uU 1DUH LAUAH5: H߃ARD}D)uE1IEXLhH9EtHH A}x HuuL^FHuu~C,EWD9~IEXELhH9Eu EH5 HD4@D'RDmC,E)D9 H5 HA DQE D L dr= Hxf1H h 5 H^f fw L}L Lf Z 荸LH5q AH1YAE)f. Hlz H߀x t]{LcMff. H fL`0H HxLcME ~[? @ UHAWIAVIAUIATMSHH L0dH%( HE1H H=Lئ HO H1 Lv H0I_Mg0IGHIGDž8 Dž< Hkz H8H H5۶ QH M IEHD| H(L@I ƅD Dž@ in "N- PpHHkz HcHcfAL H H)I LMH Hu<MH{N HH(1 ex*H0I_HMgpIGPHIGX8<I IG@HEdH+%( <Hĸ [A\A]A^A_]ÐMtIH-H N L2 _ @ 1H LH ÄMff. Dž8 Dž< [ MtIL$-MHM H(1LH\ S=UHAUATSHHiz H dH %( H]H z tD Hx0E15 t t A1w HHHuIcH C,HUdH+%( ufH[A\A]] D Hxh tD u D Hxp uH uދD yf.zuɀz uÀ uDhH2;ff. fUfHATE1SHH dH %( H]HHLJ Hx0 .z9u7HZhz z u*H@PH : 1Iv HHHufInfl H=H hH߃fC$|HEdH+%( uHH[A\]: UHAUATSHdL$%( LeLfH HH Hz8 t^MtYH~h HtrH Hh}1 ~#L I|$hoID$h sH #sH{HEdH+%( H1[A\A]] A|$! H5 uqB8uRH=J 1aL L1 IEh"H H Hphnjf AT$ H=dJ 1a L7HH HH q9 D UHSHdH%( HEH HH DB4EtXV8xQD Hx[H HD |H 1 ǀD "H ? H'HEdH+%( u9H]1ÉD !H H HD Q8f. UHATSHHdH<%( H}HH HH @0tuHtpH~p } H Hp{1 A!H H@p qH &HEdH+%( HH[A\].f D HEdH+%( uiH[A\]Lg 7H5= uI$ 1H=H _ H L`p H H Hpp%S7ff. UH`HAWAVAUATS1Hx@udH%( HE11+HtWAHHCHKH9t1} usff. @x PyAH H9uu`H而HHuDHEdH+%( Hx[A\A]A^A_]ff. f D PyAPxH H9u H{ *HtDlE1DuIDIIEIMH9t,EuPff. D @x PyH H9uuALIHuDlALE @ PyPxH H9u @ I} )HtLpE1䉝xDIID$IL$H9t,EuPff. D @x PyH H9uuAL!IHuA܋xLpD8PyPxH H9u @ I|$ >)HtL}E1Le|HHCHKH9t0EuSff. @x PyAH H9uu@H耊HHu|L}LeD9fPyAPxH H9u H{ (IHtH]E1DmIGIOH9t7EuZff. ff. @ @x PyAH H9uu@LIHuDmH]E@ PyAPxH H9u I 'HtDe1MHHBHrH9t8Eu\ff. ff. f D @x HyH H9uuAHAHHuMDeABf. HyHxH H9u @ Hz HU['HUHtLeE1HU]HHCHsH9t,EuOff. @ @x PyAH H9uu@H蠈HHu]LeHUD< D PyAPxH H9u H{ &HtH]E1HHCHSH9 E ff. ff. @x HyAH H9u H{ [&IH E1I@IPH9t;ff. ff. f @x HyAH H9u L蜇IHuEH艇HH-H]Eff. f D HyAHxH H9uu)HAHHH]Ef H{ E1t%IHtI@IHH9t6ff. ff. f PyAPxH H9uuALIHuE Ix1L`L`A Ix L`sL`A0fUHAWAVAUATSH8H}UdH%( HE1 H A1{$IH ff. @ IEIMH9 E1E @x pyAH H9u@ I} E1$IH IAIIH9tMff. ff. @x pyAH H9u@tIy1LMXLMALIIHuE5ff. ff. f D pyA@pxH H9u@uWDLIH1} DHEf" HEdH+%( H8[A\A]A^A_]f. I} E1#IHtIAIqH9t?ff. @ HyAHxH H9utIy LMWLMALHIHuE1 L8 M I1]f fI*YW( H fH*^ZA u A/ LȃIHI Mn("HtoH Zz y tIVpL*MzLLfHH H*XY' HgHfHH H*XR fJ18- UfHAWAVAUATSHH dL,%( LmI HX0H) @ IHLs lhA$ HuLƸA$ A$ - LL I$ M|$(k!H HYz z tIT$pL:MT fI*Y& H fH*^ZA$ uNA /w@A$ I / (L|T AƄ$ ff. HL/A HEdH+%( 9 HL[A\A]A^A_] 1fA$ I$ Mt$([ H HXz z tIT$pL2M fI*Y{% H fH*^ZA$ u>A /w0A$ A$ uI AƄ$ H IHLs SfA$ HuL譶A$ AƄ$ 1LL 1fA$ HfHH H*X!fLAfHL H*XHfHH H*XfLAfHL H*XA$ I A$ I f~ f~ I AƄ$ fA$ ) UHATSHdH %( H]HH~(H HH @0tPHtKH~p tdH Hpl1 `H H@p bH HhHEdH+%( uqH1[A\]f D Lg oH5u uI$ 1H=#: P H L`pH H Hpp]l( UH`HAWE1AVAUATSHXdH%( HE1t Ho IIFIVH9G Axy q xx / - H H9uۀ- I~ H E1HHCHSH9 Axy * xx - H H9uۀ- H{ H LuE1DmH]HHCHSH9= Axy xx % - H H9uۀ- H{ fIH D}E1IEIUH9 Axy xx - H H9uۀ- I} H DuE1LmDeEIIGIOH9, Axy 6 xx - H H9u@- I IH H]E1IFIVH9 Axy xx - H H9uۀ- I~ IHtt1DeAHHCHKH9t;Axy xx t'- H H9u@-uH{[A H{HHuDDeAf D Lh{IH+H]E D LH{IHDuELmDeEf. L{IHD}E D HzHHDmLuH]Eff. fHzHH Ef LzIHHEdH+%( uHXD[A\A]A^A_] f D f D .f D yf D f D f D \$f UHAWAVAUATSHHdH%( HE1;H IE1ff. HKz @ txIGIWH9t&1f HH H9uyx ALmyIHuHEdH+%( HHD[A\A]A^A_]Àxx f D Af. IGIOH9C xy txx tH H9 H H9t H H9uIGIOH9t fH H9uAH D I H.L}E1]HHCHSH98 Axy R xx - H H9uۀ- H{ IH DuE1IEIUH9 Axy xx - H H9uۀ- I} VH} D}E1LmDeEIIFINH9' Axy xx - H H9u@- I~ IH H]E1IGIWH9 Axy e xx - H H9uۀ-} I Hto1DeAHHCHKH9t6Axy xx t"- H H9u@-uH{A HvHHuDDeAf D LvIH0H]E D LvIHD}ELmDeEf. LhvIH DuE D HHvHH]L}D D f D f D Tf D f D E1gIGIO1H9xy oH H9 @ UHAVAUATSHdH%( HE1 5 ' A H8 E1H I H Ls($H+ H\Lz z tHSpL2M fI*YE Ht fH*^Z u A/$ AHtHHuHEdH+%( HD[A\A]A^]f D Hs LAff. HXtHHtH Ls(@H7 HxKz z tHSpL2M fI*Ya HxTfH*^Z uA/$ {A JHsHHfHfHH H*X D LAfHL H*X`HfHH H*XwfLAfHL H*X<HEdH+%( u:HH [A\A]A^] f f fb fUHAVAUATSHH dL$%( LeL M H I$ HH90 Pa p`A$$ uL荨A$" H)A$ L5Iz H) A~ E1A$% I$ fA$" A~ t A)D A$ & H HEdH+%( O H[A\A]A^] @ 1 @ L5Hz H) A~ uCA$% E1tz1LHWA$& tA$% D LHA$% A A~ tA$" A)D)A$ A$' t AƄ$' 1fA$" 1҉ H f D ft D AƄ$' fA$" A$ Mff. @ UHAWAVAUATSHhdL<%( L}LzM IG H LrIIHMtiH:Gz PLH)H8 1IN-H L a oAD$ HCID$0HID$ hf D HLuA 1QLL] Hx@ @ Hx11M IXZMu(HC 1HUdH+%( u@He[A\A]A^A_]þ LC%HtI LLsLZf. UHAVAUATSHH dL$%( LeL M H I$ HH9, xa p`A$$ uL{A$" H)A$ L5qEz H) A~ E1A$% I$ fA$" A~ t A)D A$ $ H HEdH+%( R H1[A\A]A^] L5Dz H) A~ uKA$% E1~ 1LH] D A$& tA$% LHA$% A A~ tA$" A)D)A$ A$' t AƄ$' 1fA$" 1҉ H f D ft D AƄ$' fA$" A$ Off. @ UHAWAAVAUE1ATISH HdH%( HEH HtDhI$ LL H(ID$SA$ I$ Ht LLH1LLHw FR" u:L=2 DLE Ãe>B @"w-IcL> eB C"F f D L(YHEdH+%( He؉[A\A]A^A_] @ I$ Ho% bLU D A$ AT$(A$ . I$ HH @ AD$.)I $fAD$(fA+T$f9)BHH)I $ @ L+f D I\$&N5<{ I$ DFHJHA$ D{ EL$(WH=m& P1At$A4$ED$.><H U D 1LAt#+L" D I$ I$ HH HxI$ A$ Hxh fHx0.z7 1 f D 1HNA$ HHHufHnflA$ LyL t8HHp 9< t < L1H$ 'I$ Ht LLLL @ AD$.AD$. fAD$( Hxp H D f. H g?z y Q Hx0H@PI$ @ H. HcH>I$ HD% 7L* @ +nL+ T @ Hȋ { H <z A H U H Z{ H81{ I$ A$ AD$(A$ I$ I $HH R AT$.)ЉfA+T$fAD$(f9K)BHH)I $2 L I\$J5{ I$ DFHJHA$ Dy{ EL$(WH=" P1At$A4$ED$.8H 1LA$ Hx0I$ I$ HH HxI$ A$ Hxh fHx0.z 1 f D 1HUKA$ HcHHufHnflA$ LLgEt8HHp 9< t < L1H! Z$I$ Ht LLLL%vAT$.AD$. fAD$(]Hxp H D f.zCuAH ;z y Q t Hx0H@PI$ A$ uHx0:5l{ HȅoH8z A H 7 H <{ H81] I$ .HL;z R H<;z R Jff. UHH H5VH=HHdH%( HEHL7z HP HH H ۚH@ H H` H HEdH+%( uJ) D UHDHfHnHeHH~Fy dL%( LEIHGpHS:z flH PƇ GX HH 1tw x @q.thIP DI*HGHHpH9t&AAff. @ HVXAHrH9uAfDI*HEdH+%( u;L : @ HHpH9tQ* HFXHpH9ufQ* D UHATSHdL$%( LeI /HHt LH4HEdH+%( u HH[A\]T @ UHHdH%( HE1HEdH+%( u ff. UHAWAVAUATSH H $ H H $ H8 DeHLMωHLLdH%( HEH HHGCIƸMm H HI M I Dž,Dž t Cs>111h# ufI .Hx0 A .zuH7z z ? 1 1HEA HHHufHnflA I H HH 1 HH H HHH6z H Ht%H t H IFPAH HDž f1A1E1Dž, HLI ,HtI L D HZz Pw H5& HcH>f. = XHI JLL f D LI+I9u,HUdH+%( He[A\A]A^A_] A f= _= D = f H H D H I5z { ' H H "5z 0;( [( 9 Dž,H H H51' HJ+ LHD f HH D`,Ee I H H5z 8 H@ H H HAH IcI HHHHC H H3 HxX ( HH8HH 1 jNI xEIcHAHHH ̎HH IcHH HHH Hz8 M Hxh H F tH 6 A! L%n R DZ8E EO HH 1 MI HH x>IcH _AHHH LIcHHHDR0E H HMdLS u HC L I H n Hxp tH Y H1 HF Lx>IcH AHHH H(IcHHHI I H H H H9H xa HHx A hII I Hz Hq H H9A @`H r Ht HDH1 H Kx6IcH UAHHH IcHHHI I HH H DI0L@Et}MLtqHH 1hKI HH xEIcH5<ALHHH L(IcHHHy4t|ExwD H M xH ; H1EHB Jx>IcH AHHH D8IcHHHH p H1 H fJxIcH AHHH,LLHHDL 1f D9 HLHI4,uHLD)uŋ,9HA/z pI f ,RH5{ L 6H@H HH5 H= D U 1@ HHEHH x&LHHH@ HLLH H=V 1bH THLHDž HDž0 *I HH8B%LHh CHH W5LH HMI_H@ H@ AGH HHLH(lHH @, I HCHXH6HS H) H@H H ,z HIH)H: fHnfHnfl(HL耄H |'z H= 4)օ1A 1i'I D8HH I4tEkD U I HD BI 1 ǀD I AL)A H L- " D A HA @ H1Li&1HotH5z H|aHH A I~A JH說LH LIHf H*z I\$x HfI$ Le A$ H HDžp ` HPHDžX LRH )` @1f A$ tA$ <-H9DI$ HP LxHHIL9 LPHLAWHPHXHHH)IHPHXLxH9tnHXHPHh 1$LLHHHPH)XAW(HPHXHHH)IGXHPHXLxH9uH\ L d 1LP$HPHXI$ HHH)HHPHXLxH9tbH 1#LLHHHPH)XAW(HPHXHHH)IGXHPHXLxI9$ uLL01L HH5 cA$ t 7 A L16H谧IH$HHHH= 1#;H@H HH5U H=" D, EN HPHuff/wf/ R H DL cf D HH H Yf D H@PI H HDž Hffo H@)@fo )Pfo )`H HffA$ HDžp HDžX HP)`tEH&z x t8A$ A$ ƅ-- f I ƅ HH HLxH9 A Y LPHLLAW(LLH߉E1NHHPH)XI HH IGXLxH9 Ax uI$ LHu8EuHXHPHR 1w HHPH)XRfHLuI HH IGXLxH9tff. HH1Hh2 -HfH1H)@LL0H@Hs Lv)0PF^_d H= 1 D I t)HH P8t M @, HE11LHLHHHͷH AI McJ<HH H 1H ^ H_ LV>LxGHIAH H^BDŽ< JJMcJHI H H H1H Z H L=LxGIH~AJHBDŽ< JH McJHI H H tzH1H H3 L*=LxGIHD~AJHBDŽ< JMcH JHI JH1H L<!LHH AIJIcHHf I < @ LHD,HHe 1<fH@ H, Hƅ HH 1JI HH HLxH9HXHPHf1HA$ H)@L0H@HoL$rL)0PQAXAYmDD I I HD XH L4 1YI H(aI HJpH9: HJhH9 HD H9pHH Da4E\8ND = I HH H HH; HH HHH HH HcHHIH HHHH9HP HHH`HP@HHHHAH lH I E1HDž HlLHeHII HH I L@MgHH1LLHHH7H AIcHHHƅ++ HIE1LHHLHHձHH AH IcHH HH(L脸?HDJ 1AQH@ L H>iXZ& xH1ɺ 2LH E1HDž H>HHH* 1 IH I H_0f(^$ H fH*Yf/ E H,HL=z AGZA 1LLA H"IHA Met1Aƅ fA A t?fA t4HR z x t'A C HI( I LAW L*Aƅ LHzA Aƅ 71fA 5H H z 8 H HHLhHMHX`H1LLA @ SL @ LfL11H߾ A\A_HHa H)HC I} HiHH0H@HH(gx IE(H fH*Yf/ H,HvI w\ H,H?HH E1HDž HA% HfHH H*X@\" H,H?HIEpH (HH-H L4 1=L H1LLA @ AULe @ L,eL11L AZA[IH HwHtkH{ L6hI L0H@MHfHH H*X[HLrmDž,HL`I HDž0 H@H(-H`HHDž0 H@HH(D ^IL@ 8LHH= H1ff. @ UIHAWIAVAUIATSH HDdH %( H]ȋ_x G Hz x tGII9 1ff. H I9tH9 uH I9u L 1 ~ z LHHFtL8fHnHhLXflfHn؉U)M~ Tz fl H= LM)MEM7M9t<f LHDHH9 M6fDM9uHXHM AEH L牅 H H H1*& L4K L uI}AU } u} t tH L1;E D M6M92 HE H LH H1v%W 1L uЀ} uʀ} tĀ tHJ L1E D q = LuMHLKPI}AU HM LPHLMEVH LAXZA Aq A 9MvHI9mMvdf D HGxHx ff. @ HEI?1APHM_AXAHUdH+%( HeD[A\A]A^A_] D H5ɸ L1A L*f q = LuMDHLNH AULME1LEHH LAY^A Aqt&A MvHI9uMvyAq 211 @ A|]A A D H5 L @ M6HI9M6A4A}*AM6HI9M6AlA" UHAVfA~AUIATSHPdL$%( LeI` H L HHVnL- H L L%` D 111 Of)E)E)E)E1ɺ LHSatN tG?uLH D quH1HUdH+%( uQHP[A\A]A^] D H HtHPHt~@fHnHuHflE]icf. f UHATISHHdH4%( HuXfHXAT$*g уt wHIL$H PML$ 1H5 A S$D )XY HEdH+%( u4He[A\] HEdH+%( uHeIt$-H[A\]ff. @ UH HAUATSH HH ~ z dH%( HE1HHB HHx0HfHnHz H8flH)H L% z HE1f. HG A $I9LB苅~GF8HHuι 1MH L ZA$H H߈HJ H# HOHH@ H 1 ; 1HAŃ/tL:tuH%HEdH+%( H D[A\A]] @ qt= ufA$~LE1H LH5 H= 5 j0u!H z H<xt[HLHt1fn@H0fl) f D L% z E1LH=w 1 1L YHHA UHAWIAVAUATSH(HuH5# dL4%( LuIֺ #uAIcF?sM.H IIIE HtSI^HM1MF HH= 'x-AFHEdH+%( u!H(D[A\A]A^A_] A3 UHATSHHdL$%( LeI F uEID$uY HEdH+%( H[A\]H -F +metGric HID$tHfo2 Hn --xed H HPID$ ~HH -F +ireHH@egs ID$ZHiH -F +ureHH@egs ID$ 6H:HH -F +phyHHys_addr HC f UHH HATSH HL%z dH%( HE1A4$8HSXxWH5 1|>H5z H8]111 IHEdH+%( u*H[A\] Q @ A4$HH 11A8f. U HAWAVHI AUfHnIHATL`SHfHnflH dL$%( LeE1HHH@)0LHHHfo0L$ HH(LH ` Hxƅ )`+H IM3 IvLLP6HcpH`HHHhH L D HH z x! HH 1AVHxLID #Y^px pH`HH L D H< H HB z x! HHh1 AVHxH L #AZA[px pH`HH A L C H< H Hz x! HHh1 AVHxL Hv #AXAYxpLH=HcpH`H L C H IH< H?z x! HHh1 AVHxLB H "^Dp_x ADpHHIcA@ HE)H<0HA? ? D) DfAn1fn鹀 ffInfHnfp fo flHflfp f fofDofffofrffrfDffofAbfAjff fDf DH H9uDDA HcD)@HLH̀HH̀J?tVHcD)@HLH̀HH̀J>t'HcD)@HLH̀HH̀D¹ A1HHH1Dlj0AÅ A9 90J E9LHE1EE E1f J<IE9E Hz H H H MH z@ LD逽H PL@M RHXHʫ 1 ZY\ HXJHX1HUdH+%( E He[A\A]A^A_] @ L ݪ @ L ͪ _ @ L @ L RH z H H M H H $ @ HHHLf. LE1H X? DHLH5> H= +DH LE= ƅH AC H> Hnf D¹ ?1HHH1Dlj0AÅ E9?D90~yf D IcH@ DHHŀ]DHDM 1L(H@H DHMDHCLE1ƅHJH> HMcL-= LLQLYL-= &9f UHHAVAUATSHHL( dH4%( Hu؉fEJLLs8AMAHHHEI9LC4S$HLHEdH+%( u H[A\A]A^] UHTfHnHAVAUHHATSH ~oz dH %( H]HH@fl)0h IHH{1rLL@L f D HxӾ SHuHc IH L Lpf D L` IMf L\HuHP fo0H HH:y ]HPH5 HLhHE1)UxHL% ff. f1H= Y?to tuHLH@HEdH+%( u|Hİ 1[A\A]A^] = u HE f= uLH課e D HEHPH HGHEG htƃq^-h UHATSHHdL$%( LeIH5~ Bt HEdH+%( u8H1[A\] @ HEdH+%( uHLHH=z [A\]f UHHdH%( HE1HEdH+%( u1H=L f UHAWAVAUIATSHh HHdH<%( H}HK= HHcHHx H H E1HpHLEHMAAIHE9 I>@ L۹EN EF1LH HyHAGEt:HcЉIHHLdH I)f. HHI9uLHTff. @ HUdH+%( He[A\A]A^A_]f D H1LpHzHHcHxIL$fLIM9uLHh9ZHHL@ LL LHL-D H8H+=z HzH=z H;HcЍpƄ@,Hc H)LOH;@ L?HLHL)Hy DC @!E H x7 HtL- LEL 1LH G3 LFS LL[ 0 H HC H 6 HtL-( LEL6 LMDCH6 IE Hy L HHw HH { AWHARQHAUATAQIH P1ASAVH`dH@H蠾1Yf H H"L-< H5 LEf H H^L-5 H LDDf H HH {1 1LxLH%ECHLLLxHL v H5 IzH1HHHcH4 HKf. UHHdH%( HE1z{ HEdH+%( u D UHATL%z{ SHdH %( H]H y uY C*8u;L tHEdH+%( H [A\]e D )8u;LtL% f D )8u; L+HtHEdH+%( uH [A\] UHSHdH%( HE1@u y{ tEH fy y{ H輾 HEdH+%( u(HH]f D HEdH+%( uH]f D UHAVAUATSHcH dH%( HE1tT=)y{ L@ LX HDžP L@LHH@HDžH 8 E1=x{ LX E1HDžP LHLP11ML 蕯 (1ۃ8ÃHEdH+%( HĠ [A\A]A^] =x{ LX< H5 1LHHDžP T 蓶Ãt1 L1Hfo L L@HDžP )@諮/ 4ff. UHATSHdH<%( H}A@"Å 11Å 3:Å L% H= L kL L%l WL JL =L L%)L L H=y c ) HEdH+%( u+H[A\] D H!y H 101g"@ UHHdH%( HE1@t Hy 8 ud J6H=y 'u*EHEdH+%( uWH=y 9f :6H=Gy H5y 1HR H=J 贪{f. UHSHdH %( H]1H5$N 1h UHSH dH %( H]1ZH5M HeH= & H/Hߺ 1f D UHATISHHdH4%( HuG;H4Y HEdH+%( uS$I4$HH[A\]rmff. f UA HATSH`L`HHm H ~6y dH%( HE1HH=LDEfHnHy HxH5: flHE1)E Ht|1Lq t t}tx]= ti= uꋝ`L HEdH+%( uSHĐ [A\] = t)= tf1L薸qt߃ ttu띻 ff. f UHAWAVAUE1ATIS< HXH}HuHUHMdL4%( LuE!f D HL)9Lڀ8 AUt&L`Aվ LPHuL9LL%y LoAu K1Hy uM AA Alj AA)H7y )UyEUDHƉMMEH} putD H}AuAD H}UDDA AC</}DoDuDA H= E9uދ}uK Doy}uk H}+6LcEDE'Aǃ ; 2 L&q{ Dm1LEXf. E}4 5L1 Do'Aǃtg tbAt\L褵AtHEHcӋ}DkD<E4D D6 @ LD'Aǃu SLEHcH}HcLA "HEdH+%( uHHXD[A\A]A^A_]ÐLEH=u A LEVLE2 륺 1Lo{ f D UHAWAVAUIATE1S1H8H}HudL4%( LuI%f HL)9Lڀ8 AT$t+LhAԾ L'HuLAT$9LAD$KAEM Hyy 1M D D)H y U AA Aʼn AA)JM}DDE}H} t}AuH}DmDADM DeH}ADA DDEA}DH= A}DeHEdH+%( ufH8L[A\A]A^A_]^f D UA D HEdH+%( u)H}H8AD[DA\DA A]A^A_]0ff. UHAUATSHHL-My dL$%( LeIL蝲1HLk2HEdH+%( uHL[A\A]]u D UHAWAVAUIATISHHL5y dL<%( L}AL#HLL%1L(HEdH+%( uHD[A\A]A^A_]#ff. UHHAUATSHH}HHdL$%( LeI ~DHuH=r 1HB 諡H}Љ耮HEdH+%( uQH[A\A]] @ L-qy H + HZ 1 I} I} HL bff. UHHAUATSHH}HHdL$%( LeI H~DHuH= 1Hr ۠H}Љ谭HEdH+%( uQH[A\A]] @ L-y H d H 1 I} +I} HL Kff. UHHdH%( HE1HEdH+%( uHH 1H= UHHdH%( HE1HEdH+%( uH11H ҟ譼f. UHHdH%( HE1HEdH+%( uoff. @ UHAVAUIATSHL%y dL4%( LuILHc=n{ LH ey H)HLGan{ AHy On{ Hc < t0LHEdH+%( u2HD[A\A]A^]f H!s.m{ 蒻f U1HSHHy dH %( H]H8`1詧HBy Hߋ0h.HEdH+%( uH=Uy HH] +f D UHHH5y dH%( HEHy HHEdH+%( u H= !ź D U HHHy dH%( HEHG HcH9r1HHfHnflGHEdH+%( u_ff. @ UHATSHdH%( HEHy ~w1L%y LHBy 1 JHy 1A Ȯ,HEdH+%( u,HL[A\] @ HEdH+%( u H[A\]蓹 UHAWAVAUATSH dH%( HEHy H H ( L?1H=y H]y 1 AA AbA 1L-y Et$ADAM DLAE A D H設5 AE 1DA HHCHs pK+H=y HEdH+%( usHĸ [A\A]A^A_]f D HWL L@LL`HS L H MMH d L1 UHz HHdH%( HEH1y HHEdH+%( u蠷 UHHdH%( HEHFHPHVHWHHEdH+%( u1[ff. UfIID HAUATL SHLHHX L-y dH%( HE1)HA}HDž t'HUdH+%( HX [A\A]]f D I tI H% @tH r"I I HcHDI uIǂ I HLLA H=A {D LHHu!HuAE(uH$ HH f. D UfHHdH%( HE11HG HG( G0 fG1HG4 GHEdH+%( u肵f UHSHdH %( H]HHHC H;H H{誔HC HEdH+%( uH] UHATSHHH?dL$%( LeIVH{MH{Ao$AoD$I<$CAoD$ C AoD$0C0/I|$HIL$HCHt Q(q(9t BrvHKHEdH+%( u H[A\]Gf. f. f. f UHHdH%( HEHHHHUdH+%( u @ UHHdH%( HE1H9HUdH+%( u詳f UHHdH%( HE1HEdH+%( uoff. @ UHHdH%( HE1HEdH+%( u1-ff. f UHHdH%( HE1HEdH+%( u1ff. f UHHdH%( HE10HcHe{ HEdH+%( u蛲ff. UHAUATSHHdL$%( LeIHH=B* qHH=TN A_Eu(LH=K Iue1f. t$HUdH+%( uxH[A\A]] D LH= 1tL-^% " L-M% LLtuLLfy英ff. UHHdH%( HUHH=t -t&FH=n +t,HA H T HEHHEdH+%( u-Hڵf. .H H HEH UHH H`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEHH0H8 HPDž0 Dž40 H@HHdH+%( u5 D UHAWAVHEAUATSH8HH}HdL,%( LmIHE HEH9 If HcSdo L=y fAG@w6HH4H)Hff. @ HhH8_f(H9uj f/ IFI~Hp)LK(IV1A I4IFLJ1Hx HCHIAG@L}EMu @ IGHS II8L yIGHuMGLHc{d~Z}! H4 HH)H t!H H HC8H9t"f. H5a HpHpHpPH9uH{fHSHu[I8 HEHHH9yH}0HH @ HIHuLHIU H IcL$TH HH)H x D HBH H¸x Af/zt\vHBHuHBfI$LLAD$L Q HXHEdH+%( r H8[A\A]A^A_]f D H8H9uHBHwf. HBf. HBHtH1 HMHcCdH } H4 ۦ LH)Iff. f D BxH8\B@H9u_ @ MGuH H4H)HHH4ff. ff. @ @hH8DPH9uL1H4 H)ƋEHH<1 D ADxXDhADxH8H9uLE1)ff. UHAVAUATIHSHHID$dL,%( LmIH H9uT @ H H9tHHHHqH; |HIH; 1HUdH+%( H[A\A]A^] I$I9u3 D H I9t&HHHqH; |HIH; ~H I9uڿ IHtQfHn fl fInfl@Ht!IT$LpHXID$L HPH=LϚ/ªfUHH5~ HAWAVAUATSH H(dH%( HE1 H= HH HIIH L%y L5rw L-~ AGT1fɅ~\fH MH)HATxf(UI<$ELHƸ M]_f(A9_TI_8f(蹬I<$LHH1UL-IHaHEdH+%( uJH([A\A]A^A_]HEdH+%( u,T H( H5} [ A\A]A^A_]H C UHAUATIH5} SHHdL,%( LmIպ hP H5h} HY H5g} H H5g} Hk H5e} H H5c} H H5c} H H5e} Hwo H5i} H` H5f} HI H5 H2 H5T} H H5P} H@ H5K} H LH=:} FHy @f 1HUdH+%( H[A\A]]I} LH5{ ݏAE <wuAE f AE f LH={ AE LH={ 衆AE e D LH={ 聆AEE D LH={ aHy @ LH={ 9AE D LH={ HXy @ LH={ AEL=IE(HH H y 101W L IE HcH f. L؆Hy H H1H Hy Hٿ H 01LH=z H\y @膥f D UHAWIAVIAUATSHHE H(HUMH]EdH%( HUȋU(= Iwdf~Ew@LcLcJJ< L)LI<ff. HhH8_f(H9ufɸA*f/ ɸ @D9@ @} L%uy HtqAD$LH)H9t`I9t[uLmI݉LeIEESLE1HUHuE1LPj jMm H M9,$tM9uEuLe UMOHcH UH)Iǃ| L}L5y I) @ HH<x tI8M9tH 讦A|$ I>H A|$ tI HI81Hy (M9uL}H5ȟ 1lLeMg(L\HIafH5x f/r/f/ H5 w H5 Hx f/HFI>MMHx 1IO0LHMfHMH5`x f/r H5O HDx f/HFI>1HZ FMt)EE0Et M;e EAM4t M;e( MgHMt:H=pU{ Ht Lkt"I>LH x H1IGHH=U{ K1HUdH+%( K He[A\A]A^A_] t D9~L%y A|$ t HuA|$ t M9 7 IG08 H H5fw 11c @ LcHEL5:y L}M&I H1Hv HEI8I9tMCDhE*A|$ I>EHu7A|$ uHHsu I8HEI9uL}v D I H1Hnv x{ I H1HNv XHEO8DEH PH5fv 1 X1ZZA IEHHI fH*% IE8YH fH*^f/ } z IEPHO fH*Y љ H5u ^bA}4e Lff. ;p4HDžtIE@H fH*HG8Yg H fH*^f/I H5u 1ESE H5t 8HfHH H*XHfHH H*XHfHH H*X\HfHH H*X HfHH H*X1 EH5*t IEHEHxUfH*RIE@HxwfH*IE8Y# HxBfH*^f/ EHfHH H*XHfHH H*XHfHH H*XtƝf D UHAWMAVAAUATISHH(LMdH%( HU1Ҁ4 uLL+GHDy HRs H 01HSHs I9skHy HLK-A H VAWRH 1<H HUdH+%( e He[A\A]A^A_]f D I9r H9uI9uIcLIH)IMl$ HI|$HUH HHE u8 (HEHH I|$HuE1E11迸 HE HMMAoU fHnH5 y LC-H@06fHnflfAE H9HAHAHW HHKPLH)RH AVP1H 1Hy LK-A H ! 8C*<P1V AWRH[ H 蓛 UHSHdH%( HE1Ht?HGHHtHUdH+%( u(H]f D ( ҽHC 1' UfHAWIAVAUATSHHx HE LuDUDLe8LE(HHE0DHpHE@HxdH%( HEHH$~ A2 H=[y t H{ IG( L-y A} q @0 Dž H fɺ f.E M 1AA LAL?f D x & H5o L AHAI8D9x$g HLW HNy x tIUH5vo L1A LcDJ IL)HIff. HhH8_f(H9u D H Dž ff.IGPH f. n h LhfLAM[ H{y H e x ux H n tH `e H LHH1AH H{ H IGPH] f.zJ H L-Ty A HD H5n LZAA} IGPD H HHH D L1H5m AD fɾ Dž f.EքtH\ff. ffLAH LHHHQ HH1AH{ d IGPH f.z L-%y E1 D L-l 1 LH qV LAHy DPIGPE) Ht HHH H HH U LL1 AIG08 H譣H HfHt,HHH fH*H fH*^PfɅt!@ffH*H*Y ^HHB HIŸ 荽L$ LH5 1Af D L1LLAIG08 uULLH))1AHEdH+%( Hx [A\A]A^A_] MO(I L-cy IGHA} E HH HLk HHH81L誼 o 7 LHHL1AԋHLIGH Hx H X A | IG(- I9G HxLHL1AHAM HHD@EHܤHLH)))1Ag @ EGXE A} A} HHHMHHi HB1; HL1A @ @t;Htff.U O fLADž gDž Hfɺ f.Ef H' HH H DLhALH+ IUH5h L1AHAI8D9x$ HLA\Hf(Hy x ux ] IU H5 h L1A Dž IGPHfLA) HL譕LAE Z <HHL Hg HH@10 D L-y H5@ 1 LHHAA} IGPHy Ht9HHHt0 H5+g L1AJL-g EaH5ђ H L1Af. H5f L A,IU H5f L1A H5 y L1A2 @ HEG8H@EtHy x ^ HL 1Hqf H߷HL1AԋIO0LH)))1An @7H Dž f D LhH{ IGPL-˼y He f.z"HԶ HH HH E1HHf H( L{ @ H L-/e HHLHHH$e L@ 1DH蜶 LLH1ADE= E1L-d HuH L1AH HHYH d LL1 AHH<IGPHH| HH3 HL- d EuH5ߏ S+ 1 D 1 H5c LAH H/. BHHl LhHAHHH1%AwXLHpHL1AԋHLLh|HHs, H 1H H腴ff(Dž IGPHHуfHH H*XWHfHH H*X'd @ UHATSH dH%( HEHy @H)H IHt+H{ tLHEdH+%( H H[A\] D H u臮uHHthfHnfl I$s Hc HCHt1H5H=HCHtI $t H{> D I$ Onff. UHAWAVAUATSH(dH%( HE1R LgHAH L9f LFM: HGML$LM9 HHK E1Hy HW 0j 1LcXZM H~y LL{ @H)HH H@IL$H I9, IT$ I9 Mt I9 I9 D)M9 D1E11)HHH)DHȃ@lHPH9PsHPHH HtqH9rlMupxp u HhHPDAvm@xpH0HPD@h1HEdH+%( He؉[A\A]A^A_] @ L H)k HP MtHhu@HPA 1DH\(f. M HGML$E1L^ xp t2L L9r*I9;R @ Lv Mf)f D HrftfHrvfLv M-LFE1MHGML$LfE1 I|$ x HMH)HMHHCf HLy ٿ H^ 01 E1E1` D D @ UHHdH%( HEHH9u-ff. fH H9tH9p(uHUdH+%( uÐ1 UHAVAUATSHdH %( H]HHHt\H IILs p[HHt;HEdH+%( uJHsH{MMA$ H[A\A]A^] D HEdH+%( uH1[A\A]A^]5 D UHAVAUATSHdH %( H]HH HtaH III͋p詒HHtAHEdH+%( uPA$ H MMH H[A\A]A^] D HEdH+%( uH1[A\A]A^]}ff. f UHAVAUATSHL/dL4%( LuIMt^I}HtDHG Ht6E1HWJ Ht H{ΨH[HuI}HG II9rZI}覨LuI^Ht.H{茨HEdH+%( u2HH[A\A]A^]ufHEdH+%( u H[A\A]A^]菅ff. @ UH5HSHdH %( H]HH=e8{ H=a8{ HtT t$H|Jy7@ H)HHH HUdH+%( u+H]Hwf HEdH+%( uH]քf D UH5HSHdH %( H]HH=7{ PH=7{ HtT t$H|Jy7@ H)HHH HUdH+%( u+H]HYf HEdH+%( uH]&f D UHATSHHHϰy dL$%( LeI@H)HHHt HcP Hx1HmHHx_HCHt(HxHt ID$ I+D$1HHH)H0HEdH+%( uHH[A\]Ѻlff. UH5tHSHdH %( H]HH=E6{ H=A6{ HtT t$H|Jy7@ H)HHH HUdH+%( u-H]Hf HEdH+%( uH]1贂 @ UfHnHHdH%( HEHFH~fHnflH8HEdH+%( ue D UHHdH%( HEHH9u-ff. fH H9tHx( xHUdH+%( u1 UHHAWAVAUATSHXdH%( HEHy @H)HG H+GH9HMLL92 HEIf M I9 Iy(tHLLELMzLeLMHLEtL`(HEH8MtIQhMLff. @ M9 tM9 uMc Mi(1LHHGI9u LME1LuHEHMHULEL}ME LHLHL 5tHEHt D(H@HEHEIH8L9uL}LMEHEHMHULEH0Ht6EEfHJ0I*LR(Y8z fH*^AD t#ffI*Yz H*^BH@Ht5HI fH*Yy H fH*^BI0 HtyH fH*Yy H fH*^M?H8BMLM I9HEdH+%( HX[A\A]A^A_]f D M?H8M IfII I*XfHfHH H*X]fHfHH H*X#fHƃfHH H*XfHIfHAL H*Xf D E1 ~ff. UfHAWAVAUATSHHHxH"y L{dL,%( LmIHu@)p)EfnHMy )E)EHE4HIyIH HIH H@HHt+MtMd$0L`LLL`A MtMM DnMM)M,$M E1M;m t(HEdH+%( c HxD[A\A]A^A_] HCoLpHExHCH{HpH[y x t=_IE8HpLeAD EwMB f oHCH LpHExPIHtTfHnfl I$Y HYy MH Ǥ 1H> 01L`af I$ A D H`Hy 1MH n HR 01>L`] |ff. f UHAWAVAUATSH LgdL<%( L}LHHLIW H`ViL-wy HLIA AEH)Hc It$H HxHHAHhH y A} HH`CtuA H \HXH { I^ A} tHH9 [ C@ Hy HHhA} LG H 8 HD RH5 DP1AVH H5$Q H֨y L 1HCy HxHHBH9u+ ff. ff. H@H9 HH(HtHHH HH1赡HxHL:L9uSDžt HXiHEdH+%( tHe[A\A]A^A_] @ L:1L9tt E1E1L`A Džt EMAMi D RHELHH`AVAWPH Dh7 | A M?HxM$$L9 S@CDhDCMuRHELHH`AVATP@H AÅ M E1ۃtf A} LpN LEE fLhLxMA A @ tM$$M;&TC@DCELHHPHhAWCj PH uAf D Gl E1E1A D AEMIT$ I)HI>Lc LHHGI+T$ E1HL`HhMMIHP IM9toI?LHHhHL 譕tHHtL MtH` H5M HH1LI M9uff. L`HPL H |M 1 H5|M J H谍I HNj L`LLD[L`h Hqy H[D A H L L`H81pL`H: 8Džt9vAff. @ UHcHHHdH%( HEHy @H)HHcP HxHHHEdH+%( u19xu @ UHAWAVAUATLcSLHHdH%( HEH%y @H)HL:HZH L9tpILu4 HMIU HtH1H H)HHHM?I9t3Iw(HtHHzLL QuIU M?I9uf D HEdH+%( uH[A\A]A^A_]tff. f UHAUATSHdL$%( LeIH?H I9t3 @ HGfHnIHhflHCHGhuHHM9uHEdH+%( u H[A\A]]"tf UHAWAVAUATSHdH%( HEHH9 IILpE12 H L1nHHIIFhLpI9 I HtTM1HTJ L KnMNHcA9 t L L)H%J 1nHHpI HQ L1 mHIIFhLpI9lff. fHUdH+%( u HL[A\A]A^A_] E1rff. UHATSHdH%( HE1Ht=H Ht3It'{@ t!{A uHS8HxID$ I+D$H91HUdH+%( u H[A\]Qr UHHH ey dH%( HEHy t/PCy PBP@t HAT P@HEdH+%( u y uPDqf UHATSHHy dH %( H]HH~B B HVHRL#Hքt*UTID$8HEdH+%( uHH[A\]1Sdq @ UHAWAVAUATSH H $ H H $ H81HGLoH@ dH %( H]HIHHDž UAą HLզHy x uPL5y LH&AFI)I} EHEdH+%( H8 D[A\A]A^A_] D PL5Ey LHy IAVHHH)H HHH u_HD LHA HҬIu-H1H==> 3o UHHH=y dH%( HE1:uHy @,HUdH+%( uo @ UHHLy JdH%( HE1r0r(r rrE@@APrDJDB H@HEdH+%( u%o D UHAWAVAUATSHHHh dL$%( LeI\Hx HE IHCHH-1 HxH5 IH{ L=by A tM9$ - HCHKM HIE LH@ H-L 1iAGLcHDž ~y LI)HfHnH,flfHnH)~y Hfl)I$HH9tJL5 y LA> tH{(t&LLHSL xƅ I$HH9uL1+{Hx]HEdH+%( uOHh [A\A]A^A_] @ A$ L LLBR맃 mff. UHAWAVAUATSHHLgHy dL4%( LuIE IL$ x XHMIL$HMt M9 L8QEt)HEdH+%( EHH[A\A]A^A_] @ MLLZI)1Mu M>fAFFIF( M9 1۾ LeLmDAL$ D AF,AHAN,C`HI9t=EfFH{00wI9sfAFFAEH{(En(C\uC`HAI9uLeH5ڽ LmI|$-}H I]Hn H{ c HMHE1LH)HELx:H I} 1H9t f D HP(HtI9r H H9uIEsfLL@ M LeAff. ff. ff. ff. ff. H IUHHHRH)L4MtI~ tI} HhIHd HxP ! A~p AFltIF1It$PHfHnAFFIF HFHxff. LeL蔡I|$ I+|$]Iu ЈƈF@fVBI|$ ]M} AW0AGD c I AGAI9 E1f D H{(tH{tA9DLHI9uEEwELAG$^KAL$+ 1I_MLHDHhjI} t#Hs8'I} HtHXQPX;W0~W0M?I9uI D A~p MM>I} LީH5I} H9(E1 D HP(Ht H9r AH H9uEDE AVh҉U MNMLM fA~r LcH Iu H9 LM}fUMH*I fI*fE1H*^^fZf HP(Ht H9r HPPHt. z uAH H9uLDEEuEt0Ht+DEEFhA~Fo DxfInflf @ MAfM>I} LqH"I} H9f D A OȉM ID$PHHHELeIIII)IH9|'ff. f D HIxL9IELHHtHy tI} H诧HtHxP蘉 E1 1LAfHL H*XELsf UHAWAVAUATSH H $ H H $ H 1HGHX HGdL4%( LuIL HhHDžx 贬\J L%7y A|$ HĒy H`LL LYHhL LH-AD$@ Hrx LH gy HL1H< H;AUH`H`L+HDž ~Kx Hh@LH)HfHnHSflfHnH)~ x Hfl)HZYL8L9thLff. A<$ tI(t%LHLJL 藫ƅ HM?I9uH`Lh@I)M?L%HEdH+%( \He[A\A]A^A_] D AT$I~LLxH}y H y PH`H)LH L_%f. H!y A H y: H1 LPH81^LPL \ LHHxHhH1H=1 H-蜗Dž\xc Uf HHdH%( HEHoy H@@ fP@ @ @@ @@ @0HEdH+%( uc UHSHdH %( H]H y H{(荅HEdH+%( uH{ H]pb @ UHHdH%( HE1HEdH+%( uH5y H=8颚mbff. f UHATSHdH<%( H}H CHtw- HHzHtZ L`HL耯t3H,y E1B@HQHEdH+%( u/HD[A\] HL=uAAa U1HHdH%( HEHy Hx8 tHx0 tHEdH+%( u$ɉH.y H{ 101tHa UHAWAVAUIHATISH(dH %( H]H-|e Md$XM fH[ CMt$8E|$PHM E Au[LjyH! C D{AEZ A:s Hu1LH}CAuZ$yHEHHtgCAIHtZ1H1LGP{ t@HEAuZHxxHEHHt"@IHtH1LCP}u+1HUdH+%( H([A\A]A^A_] Mt$HHZ E|$2HMtE f D I H56 LHE it H5w6 LW L1@IH- A:EZ A:E\ L&O H5#6 LuMAPЀ jbAu[#f D AFIPЀ @8@8u. H55 L WuC f1Lva MwHu1LCHEI98H/C& @ C IHu1L躮CHEI9)H C ^f UIHcHHHy MYdL%( LEIPLH)H HHHhI9t0IPhIHr(HBHt"fHPhHr(HBHuH9uHcIs I+ LHHEdH+%( u IyU] D UHAWAVAUATSH H )y H dH%( HEH H H I H y y H- H HHHH0H(IA Hry M @MI)IHL`H9uX ID$hL`H9tBI$ HtIFH9uLswtdID$8 uZID$hIHL`H9uH!y @1HEdH+%( Hĸ H[A\A]A^A_] Hy @HEH y H8L;M4$I9u M?I9 IL踟uH8HHLOp HHH52 ctOM4$ H5r2 LSl Apu A~oM ruA~e ff. H0I$ f~HA )UH`I H8fo)pHpA )U@xHր} HMHh)Pu } IA> I H@ { HPٖHH AGHy x( EA |IHL:IGH HCL{I IGL8JA~pAGH gy ADž )p} @xH})UH}u} tIH~aH Ny QH)H HHhI9tDID$pHx(Lpt/Gff. ff. IFpHx(LpuI9uH y AG @I$I6fH~tM!HHH5/ jA~ _A~ TIcFA Hp=fA ME@HߋUH(GAVH0LHpHHH5k/ Lt8A~ u1A~ t*A~(u#AGH y 1A~tB AG Hy AG @ WLGff. @ UHAWAVL}AUATLeSfInHflHhHxy HUPHdL,%( LmI)EfInH)flH)EHLpH9u#y ff. fIFhLpH9[ I HtHCH9uLQr1LL$' HELEHM9 LeMLxMf D IEL`I$ L9u' ff. ff. HL9 HJHyH; |HIH; IEIu LHFH0HELhIE HEMuLmLmI9oMAHHIL9tNfo-@b )mff. ID$foUI|$IHCHA$xLIFHM9uHEdH+%( HhD[A\A]A^A_] D H=y IWI)MIzH(HW I|$hI9tcLmMMIHt`HEHsH9 M9r LZb Lڌt&MMLmA|$A IEL` M$IEhLhI9 Hp( D I LYL9jHH(HWt$Cff. HJpHy(HQ$I9u- Hy I|$8PHH)H0HHPH9u(Tff. ff. HBhHPH9t.H H9uHtHHUuoHUH}LEI<$H5ʟ efHIHpHhL9ID$hHx(HPu H9HBhHx(HPtH}LܧLEMMLeLxI@LLp D HCHHHPfInH_HQH IU fHnHBfl IE HGHHBHgCHuLmI] M9tIfo%M_ )ef IEfoMI}IHCHAM uLICHM9uHEE1MLmAARf. f. f. f. f. UHHdH%( HE HUdH+%( ukRff. UHHHH dH%( HE1HuHUdH+%( ÐxfH fH*H@ HxvfH*^L H HR YH,HxgfH*^YH,H) @ HЃfHH H*H H@ XHyHfHH H*XuHуfHH H*XPQ UHHdH%( HE1HEdH+%( u)H HR LNL H1LxP UHAVIAUIATSH L H}y dH %( H]HH @"I$It$HpH BH It$H@I$H HpAH@HHIHzy H I9t+H9t&HPHq' 1Hw. HPIL$1MD$HJ' HwH@轊HH豊IuI} 1A HQ IqwHUdH+%( uHĠ [A\A]A^]Off. f UHfHHdH<%( H}HH HtH BtuCH|y umHEdH+%( H5 LcHB 1IHxWfH*HxgfH*^YH f. HEdH+%( uRH5T O HfHH H*XHyHfHH H*XjNf. UHAUATISH(H 1dH %( H]HHcHtH@ HH=?B H= wdLmH 1H^% LuA$ H;1MHsHO uHUdH+%( H([A\A]]f Lmf H*H$ L ^?G 2uHx;fH*Lm H$ L^F tQ HfHH H*X M UHH dH%( HEH Ht H@ Hu4HEdH+%( uTHFH>L2$ HN H1mt D HUdH+%( u LNH>HyN L 1L9tL @ UHfHHH dH<%( H}HHt3H HR HxafH*HxqfH*^YE Hyy uhHEdH+%( uzH5 W HփfHH H*XHyHʃfHH H*Xz @ HEdH+%( uH5$ zKf. UHAUATISH(H dH %( H]HHH H?B H w[LmH" 1LrA$ H;1MHsHL rHUdH+%( H([A\A]] Lmf LH*H" ^_D RrHx;fH*Lm H! L^C rW HȃfHH H*X@J UHHdH%( HE1HEdH+%( u ɿx lJf D UHHdH%( HE1HEdH+%( u9Iff. UHHATSHdH %( H]H H;Ht>L I4$Ht)H-H-|uHHSID$H9t*H) HUdH+%( u%H[A\] ID$H+C D HI UHHdH%( HE1HEdH+%( u HHZH D UHAWAVAUATSH8HuHUHMdH%( HEH H H IH ffHn)z )z )z fHnH uy flHH)sz H)H@Hc HXHV Hr HzH9+ HE E11<ff. ff. ff. D AHDH)H9 HHH)L4AFlt?7IH I 1IcH}A~FA~fHnIIFHMflfHnAOflAGA~FhIOhfpf~fAGpAoN(HcHAO(AoN8AO8AoNHAOHAoNXAOXLH5,z HERHtNI Hp Hx HE fHEHtH]H1HUdH+%( u H8[A\A]A^A_]LHFff. UIHAWAVAUI ATASHhHUHc~=x LxdH%( HEHLM}fHnfl)} HH LMI I9 L A L HMLIHpLMMIf D IFE( HHEIHHEkH}Adž E~ IV`HEfHnIVp fHnflflAN`A AFpwcH5m Hc H> D H5IIv0 D HH5'x foUH}HHHuAVH@I A %A I HEI fHnI @fHnflflA AH A H=m Hc H>f. H5Iv(@H5Iv00H5H oy Iv(H5IN8IvH f. H5 Iv0H5Iv0H I fHHx fo]H}HHA H@IP AL A I HEIh fHnI @fHnflflA A A H=l Hc H> HI E D H ny HH=I I I H I D H=aI D H iI D HI f. HHx foeH}HHAp H@I A 覙Av Ip HEI fHnI @ fHnflflAp A A Hj Hc H> H=I E D H YI - D HaI D H amy H=2I I H =I H iI H I@ ff. @ HH Wx fomH}HHA H@I A VA& HEI I0 fHnfHnI @flflA AX A0 Hi Hc H>H$I8 HH=1I@ 5H H'I8 H !ly IX IH H=oI@ H,I@ HII fHH='x fo}HHH}A H@I A &HuH}M ILLH~8LFIHuE~WfInAA At@AX At2A At$A AtAh AuA 1HLHEHI HUH9U I0 L IVH /I HHx fouH}HHA H@I` A\ AHEI I fHnfHnIx @flflA A A H[g Hc H> HuH}苚Mr D HpHx]HEdH+%( Q HhH[A\A]A^A_]HuH}3MfInAA =H=xI H5I H BI H Giy H=H1I I I gH=PI TH=I !H I HI H H=I H hy I I H I H Iǰ I9<ff. UHAUATSHdL,%( LmI~/LcLMi Mff. HHð 衖L9uHEdH+%( uHL[A\A]]K,F<f D UHSHdH%( HEHiy tQt$HEdH+%( ucH] Hhy @ HEdH+%( u9H]< @ Hhy 11Ҿ A @ Hgey L /; UfHHdH%( HUH HBhHuHEdH+%( u}fHRHx/fH*Y5 Hx?fH*^Zf D HуfHH H*XY4 HyHfHH H*X:f. UHHdH%( HEHHgy H ff. fHtH;x s H@HuHUdH+%( u H9x(sH@W: UHAWAVIAUATSH(Hfy dL$%( LeIHHu)O ff. f HCHSHt&HL{ IM9rL9s( HCHSHuLL9s(P M9l LX HUfIH 1 LHUHHr3 I] LMu H5fy LMe(IE0L* M9r C0 f X HH 1 Hs0oC8HIFLz HB(HCr0B8Ls C0 HC@ H* fHH@HuHCfHH5Zey HBHSM}(M9 ML{(M9 IM9 LMHH0 HP I9# M~(IL9tX HUIH HHU 1HMy HIQ(HSH fHHRHuHPIH5dy LL 苩L{(M9KX 脅HH6 1 HoCHDK4Hs8HID$BHfHB HCLz(DJ4Hr8Lc(C4 CHH D HH@HuHAfH H5cy HBHvX HH IF( HHP1HHS Lc(IFC4 H8 f IH@HuIGL;H5ncy HHkH\cy H@LHHMdH+ %( H([A\A]A^A_] HSH @ HHUHUHHLx X HuHuHI 1 LIHMu M}(HFAE0 Htl HH@HuHFIu H5by LL(芧2AF4 L H HCHaIFHCLHF5E111ff. UHHdH%( HE1Ht`HGHtiHby RH)HPHtRHG8HxWfH*HB HxgfH*^HEdH+%( uf Hay fHx u/ @ HfHH HB H*XHyHfHH H*X4f. @ UHHFdH<%( H}H=D_y Dt] ff. @ HH't6LDu !HUdH+%( uf. 13 UHHAUATSHHVvdL,%( LmI{K SH=j sDCI1`6MtLL'LhHEdH+%( u H1[A\A]]g3 UHH HhLpLxt )E)M)U)])e)m)u)}dH%( HH1H Dž0 HEH8HPH@HDž40 Ht<IL0 HH(HHdH+%( u&f. H0 Aϸq2 UH~HSHdH %( H]Hz=H1Ht HUdH+%( u.H]f. H]y K DtCD1ff. f UHAUIATSHHXR sdH<%( H}LyHtdLmILfHLL DHtHEH@ L#Lf1HUdH+%( u/HX[A\A]]HYy AM HK 101X,1ff. UHAWAVAUATSHXdH%( HE1 @o IH u K1S L;1 I E HEA LsDkHfH} I I I\$@fA D@HE)EHHUDEHEE )EGHUDEC$HuLfDmU$ DEfE8xHuIT$HLdHUdH+%( HX[A\A]A^A_]f D A vXI E HEA H}1XLsDkf D 1yf HH@0HHE:IP/ UHAWAVAUATSHdH%( HE1 H tjIII1L= ED LL1H IH9I;]rM)AD$HUdH+%( uH[A\A]A^A_] D .ff. UHAUATSH H $ H8H H? dH %( H]HHHLHDȾ L1LULL8x HL4HUdH+%( uH8 [A\A]].f UHATSH]H0dL$%( LeIHEUx LH֑HUdH+%( u H0[A\]-f ULr HHAWL= AVAUIATIԺ SHLHL5Yy dH%( HE1WHAWM聥1H^_taAUH 1AWML LHJ1HZYt*1HUdH+%( u He[A\A]A^A_]f. H,f D UIMHHATISHH}H H HuH .Yy HdH%( HE1x+MtHH9r HEHUdH+%( uH [A\] 1?,ff. @ UHATSH H $ H1dH%( HU1 9H L HHL+H~!/ LƄ rHH9r.E1HHEdH+%( uAH L[A\] D [ t I<I I @ E1V+f D UHAWAVIAUATSHHhHuMdL$%( LeE+A @ L}AHEI LHxL117IH H% L9 EtvH}LH 1H>xBHx tHH9r1LHEHUdH+%( u{Hh[A\A]A^A_] HE f D 1 @ LG Ez} L H LE_ D H}LH 1HU)ff. UHHdH%( HE1HEdH+%( u AEy)f UH HAWIAVAUATSH8D%J? 0 dH %( H]HHEHuDetE LuL-I( LL!.EuWM MuI @ L~IHt5AL}H]Det > EI LL-tEHEdH+%( uEH8[A\A]A^A_](ff. f UHHdH%( HE1z HEdH+%( uX( UHAWAVAUATSH dL,%( LmAHDžX @ H Ty 11HPH 1oi 11P<HHH HPH5V IH L`M HXE1HHH H@E8 L8L`MD$HP1 H@HHn HXH5Q IH LxMu/ LH5 xHLy|IH HML$AwL) LL ) 1 ^_(~L8LjYHHUIH1TYLLYHPHEdH+%( HeH[A\A]A^A_] 1aO8 @ L MD$HP1 H@HH[m6 HXH5 IH# LxL`HuM H(H0* @ A>/N LL.{IH HML$AwL) L 1) 赝ZY( fL)E)EEbIHtH5h HKikH0H=% H8詎SH8LiL880LH L L(;HP H IHfLy E$01~A<$HXHHE1HELHH8ڄ< D LWHHFLyIHL8 @ L(LVHHFLuyIHL IL L EHKy HXD 12H }"L8#ff. UHAWAVAUATSHdL,%( LmI.H(wBIHthH )Ny LKt% ff. ff. HH9t7Du1HEdH+%( HH[A\A]A^A_] 6PIHtHXHtUE1fH{LLuMu8IH xHHuMt I~gHL<Uk 1g" UHATSHH dL %( LMIu E H E H L E1ISH Ny H5 H}P 1+iZYyHE LHEHUdH+%( He[A\] D LHLMUHLMItmHL LEH p E1H EtL ܭ HLX H HLF 6H9 E1I#f D HtH IIHf D H HI UE11HATSHdL$%( LeIHH1HtWH5;Iy HHI$E1Ht,HHEdH+%( u*HD[A\]f }D AAV f D UHAWAVAUATSH H $ H H]IHMEEH HH HdH%( HE1HDž oBHAEHDHLIHsHHg H? H躀 L E, HHپ HH1H= f H1t[EB MtL2 HH lt&q|8t HH09 E E LL)ID8. HDž geIH HH HtL LPLHKy LL H _PLH HH H)I<IAPL\ 17LLL1LB?HZYHt H/ L跋L LM LLG@1Hپ L Hk LdA H1 MtL1 HLjthz8t^HLa!tKff. fDžHH f. HH= ! E1H L)Ht/ LLp L IIt L}pAE /H=Iy 'LLlAE ../.LAE. H HLmSIHtHH LHH\H LuHAމE L L Cy A1H Hu6 1 uH L H L HEdH+%( \ He[A\A]A^A_] D H EL H= LEf D x8 Dž xkUxo'F L By L D1HG A1LtLjLxHfL HHLr D H LHHH Ƅ L%^L Ay HM1H4 A1tHHHff. @ DžHE1 H;< Dž1E1HLLbE D DžHE1Dž1tH@y LHl 101s UHAWIAVIAUIATMSDH(dL%( LELE LEtk1L:LEHH APDLLATE1LHU$iHUY^HdHEdH+%( uRHe؉[A\A]A^A_] @ HL5LLEH @ APHA 1AQDhXZ릻ff. UHAWAVAUATIS1H D dL4%( LuI&M$ E$ HDžX OAA, A$ A AAMt A~ Mv(A> 0 1A E1E1L! H`I$ HH0sHpLH8m>H0@@H8L3 /1L牍8H] I$ HI$ H@zHHMAVH@LDO8BLx/XZHXZHEdH+%( He؉[A\A]A^A_]f D A~Mn0tuMv(A> tHXML1H D@4]ÅxMD@LXE f E1E1 E1E1 L爅@.@t @ U1HATE1SHdH%( HU1h"HHt1HAH(HEdH+%( u HD[A\] UHAUATSHdL,%( LmI i7 I\7HM H HL!H 1HP LHXHx{H uo/ H hLHu HxHH)H 1*H(EL#HHEdH+%( u HD[A\A]]f D Aff. UHAVAUATSHdH%( HE1='z t%HUdH+%( H[A\A]A^] D HH=&@y II־ t p8uSH LL膎H AHt( HLLbHA hHHuA`Vf D UHHdH%( HE1HEdH+%( u1H5'Df UHAUDATDSHdH %( H]HH( AH Ht/ff. fH D HA gHHuHEdH+%( uHD[A\A]],ff. UHAUIATISHdH %( H]HHw3HLLI\$HEdH+%( u=H[A\A]]f D H;y A H B H H81V ff. @ UHHdH%( HE1Ht HWHuHUdH+%( uf D 1 H,f. f UHHdH%( HEuz tHUdH+%( u @ -Lz UHATISHH2dH %( H]HTt"HEdH+%( u(H1[A\] HsHSLPC(ff D UHAVAUATSHdL$%( LeIHt : IHu=H7y Lz L0M H* 11!jyf. 1HuLuHA> tHH5I LyPteH5 LfPtbH53 LSPn @ @ HIE 1HUdH+%( u>H[A\A]A^] D f HZ* 11Yi3/ff. @ UHAVAUATSHdH %( H]HHt : IHuUH6y Lz Hً0M H) 11hHUdH+%( H[A\A]A^] @ 1Hu _LmIA} t_H5 L OtdH5N L OtYH5 LNU @ HI) 11Hhb IA$1P @ 搸 @ UHAVAUATSHdH %( H]HHt : IHuUH~5y Lwz Hً0M H( 11gHUdH+%( H[A\A]A^] @ 1Hu]LmIA} t_H5 LMtdH5 LMtYH5 LMU @ H( 11gb IA$1P @ 搸 @ UHATSHdH%( HE1H > H} IH5p H+M H5 HMtpH5Ir HMt]H5 HLt*H5y7 HLtH5 HLu4 @ HUdH+%( u@H[A\] f H}HLFxU1 ff. U HATSHHdL$%( LeIH5, H5F H ;utt H5; H H5+ H H5@ Hh 1HUdH+%( H[A\]f{iu{.uH5 HNuLH6Hu7y @ H5I HNtmH5L HNv 1LWH7y Yf HEdH+%( D HLH[A\]mf. 1LH3y v H5/ HN H5% HM H5" HMLH5y H @ HEdH+%( HLH[A\]Tf. H5q HqMYMt`H=5y L ƀ 4 @ HLn"Gf HL~3H0y H 101b UHHdH%( HEH`z HtHUdH+%( u!f. H= t~H-z vf D UHAWAVAUATSH(HudH%( HE1H> HHEHEH H}H5` cLmIM H} HLpH9u f. IF LpH9 I>LKuM~IFHXI9u : f. HCHXI9 H;LKuH=<z H|KH}AFC7IHt?H{)Lc13H.y H ;0 H 01;aL H}HEdH+%( H([A\A]A^A_]f D 0 b)IHtLxLfInfl@IHcHCfHnIV HSfHnflAF Hf. ( (HHJL2HHtXIFfInHSIVfHnflCHH-y H 6/ H 01!`H-y H . HW 01_HfUHAWAVAUATSHHXHudH4%( HuH5 ohH HOz E1I3z E"z E HEH z H L(Aă K H EV L5/y AA f A# A; A[0 z U HcUH5Qz H]HuDDjMcDIL-\z M L'Aǃ = 5z u#AA4 A-* A_ AH]HED L%z MtNA t A L:'Aǃ = uL%z A z MuA t ff. A Y f D 1HUH}!I HQz E1IH)H Lm=z t1LHz HEdH+%( HX[A\A]A^A_] E<$ IM]HUAN H]IŃHЄX A D < HC H9 bz AŅ L=`z MtL1%Aă @ D L% w z Ez Ht- < H H9tLmMH D D8/ H H9 1EL=z M7 z Ht)t"< HE LmH9V LmG L$ <z A D L$ LMH=z {LmEz V Hz A I D-z E`L=z M LH EuL5+y AF L=yz MW2AH]L%]z M L# s : y A uÃ"unLeIcAULcA.M D Lp# v " \1 C,IA L5z MuLmz EH'y Lz 1H 01Y] ez H=iz A A f D A HA A A=1E1H]E1LuLMAE XfUe EtHtHz HA\R A" Hz E1D,HL5z MtzL"AŃ H XEuHMA `E`A;t A#PL5.z A Mu IH]I MH5z B. I݃z H]I v @ z IH]I vL! tLH %x A D L%iz M@L b n t H z H @ uE1N @ AA H]z @ L< L=z LHH[ @ L E lz E1H9z E1H]HEID L-Iz Mp L Aă b D z EV] A A-t A_ E'IMjDz LmLcEAN ȉʃ HM A B!If Aif D z D z z E AF PA uA.< 0A. f D%z Et z Lm D L _LDnz E m H& HQz I/z LLm\ A A=E1 z Lm@Lmz Ez . L8 tLAF Jf L5z ML t]z LmKz EL PLf [" \ Lm[ELmML5z M.LJ tW T]AEIcտ. EHEf<FL ǃ LHLLmǃ {LMz Ez7AH]Exyff. f UHSHdH %( H]H Hg0HƸ HtHHUdH+%( uH] UHSHdH %( H]H z H0HƸ HtH2HUdH+%( uH]UHATSH H $ H dH<%( H}H=" /Htq8 Htit`HHپ 1H :HHIH HPHgXxlu9H u LE1HEdH+%( u<HĠ L[A\]f D {9tHx y LHF 101PHU y HH 101Pf D UHH=z dH%( HEHz uHtHUdH+%( u ÐHľz Huz UHHHdH<%( H}HH5z HUdH+%( u HH_f. UHSHdH<%( H} 0HHt#fHnfl Hy y H8Ht HHEdH+%( u\HH]t Ht t|HtrHHHMu UHATSHdL$%( LeI kHHtfHnHLfl HEdH+%( u HH[A\] UHAWAVAUATSH H $ H H $ H8dH%( HEHH9 IHLp1HLIFM~HXI9tdM LcMt@IM LL1H LHLLHЉ x/HKHYI9uMIF LpH9vA' D AHVy MLHa 101MHEdH+%( uH8 D[A\A]A^A_]E1H UHATSHHH=z dL$%( LeIHt"HEdH+%( uDHLH[A\]`_Hz HHuHEdH+%( uH[A\]f. UHAWAVAUATSH(H}dH%( HE1H HHLhLrH9 IM(fHnMeflHJHIEAE HHXLzL9tTff. @ Hs fHnHflHrHCH{HLIWHCLzL9uLLMIV HuIF HJH9t IK HEdH+%( u5H}H([A\A]A^A_]HEdH+%( uH([A\A]A^A_]_ff. @ UHHdH<%( H}H=z kHعz HEdH+%( u f. UHHdH%( HE10gH=z tHEdH+%( u D k]Hlz ff. f UHn HHHNy dH %( HMH101JHEdH+%( uɸP UHSHdH%( HE1HtWH y H1HQ H; t>HEdH+%( HH] H= N f D H q y ; uH= (IHt@H H߹ H L P1gXZƃ tf D H5 HD]ff. f UHH H`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEHfHH=HH(HP)0Dž Dž$0 H0&8HHdH+%( uw UHAWAVAUI ATISH(HAz U DdH %( H]LAI!M)K4A1g#H| IHuk t/IIH)t[O4'}LHLMHyTK8tM4 LLKHEdH+%( u"H([A\A]A^A_] M1˻ D UHAWAVLAUATIHSH HLdL,%( LmIHDž LH0NL[t:LLHEdH+%( y H [A\A]A^A_] @ H1HH 3 L/ LK@HH HH{HHP .HADž H` t DHLLuL11ygLAYExL`11DD(D)D!uHHZ9f D HLL HDž LHLH5 VNLHkYH$HH5Ug /NIH LL H Lt\Hٺ LLi3HLH HDD D LXH HDaE1}Llrf UHHdH%( HE1HEdH+%( uHѺ 3 UHHdH%( HE1HEdH+%( u1~f UHHdH%( HE1HEdH+%( u ɺ f D UHHHHdH%( HE1HG HLJ HH) HHEdH+%( u1P UHSHdH %( H]HH` HC` HEdH+%( uH] UHHdH%( HE1H u3HGpHHGpH HHtHUdH+%( u f D HEdH+%( u1 UHHdH%( HE1H u3HGxHHGxH HGHtHUdH+%( u D HEdH+%( u1 UHHdL%( LEL MuKH HH H HtL HGHt HMdH+ %( u!HL D HEdH+%( u1 UHHdH%( HE1H~( u6H HH HF(HGHtHMdH+ %( u D HEdH+%( u1 UHHH LG dH%( HEHHqH MtHMdH+ %( u HHAHEdH+%( u1 UHATSH dH%( HE1H~( u[H HIHH HF(HGHtHUHUu*HEdH+%( u3H LH[A\]f D 1HUdH+%( u H [A\]UHAWIAVAUATISHH(dL4%( LuIH HLLMt(HUdH+%( H([A\A]A^A_]f D LLHEH HLL*OuHEIE I9tWLLHLL QuMu6HuHL t#hHtLLHLJH_H1H4HEdH+%( u$H(HL[A\A]A^A_]4 @ I9u @ UHHdH%( HE1H u;H HH H HG(HtHMdH+ %( u HEdH+%( u1H UHHHdH%( HEHy @H)H9 u0H HH HHG0HtHMdH+ %( uHEdH+%( u1 UHAWAVAUATSH(LEdH%( HEHFH HH~Lp IIILHHJufI IL$IHtrHy LHHHMDx$u0HMH]L)HIL$IU IT$(H+QHff. fHUdH+%( uMH([A\A]A^A_]fI|$(1L 1ID$HHtLF^IL$HV1ff. @ UHHdH%( HEHG8HtHMdH+ %( u @ HEdH+%( u1@ UHI HAWAVAUL-xx ATMSHXdH %( H]H IT$IHtA4$HtL= Le Eu At}A ut @ L1MLû @ YDLH߁ uJ @ LML @ YDLH߁ }uM}IMhHUdH+%( uHX[A\A]A^A_] D UHAVAUATH(dH%( HE1H~ L.IM I} Mu MtaI~ uZI6HtH}H}ȅ H HPH IVHWHH H}LH}ȅ D H HOHHPH IUHtQH}LH}ȅuRH HWHHH ID$Ht0HEdH+%( u[H(LA\A]A^]HH ID$1HUdH+%( u)H(A\A]A^] HPHIUH ID$ UfHAWMAVIAUIATISH( LdH %( H]IH`HHE HhHpLxHDž H)E)E)E)E9Åt-HEdH+%( t He؉[A\A]A^A_]f ILHHÅuHHHHHLL HHvÅ H HHtH@(HEHMHULLI$ LEHI$ HErÅ0 M\$hM HLp M+ H y LLx h I Z HWy @(HGy @( HE1E1jHHLLH+^_HLL H LnH> HF HDž Ln HDž HDž o LH HLMLIff. fM L IEIMH8Ht#Q(f D q(9t BrvHH0H8Iu H(H0HHHtH8 HHLLLIM LI|$hLH8wLIHC H@PHCHC kHHDž HDž HDž H9CtLk MLLH:y H(M9\$ht&Mt!LLL+LICHEH tbLHMHULLELupID$`Ht6HLMLLPHMH?ZYu;ff. ID$@HtH`LЉH\ @ H`HM\$hLp Hx :H85H y H( UHAUATISHHHvdL,%( LmIu|I|$P uH HQH IT$PMt$IU HuH HQH IU IT$XHSPHt+HEdH+%( u6HLH[A\A]]f. HUdH+%( u H[A\A]] UHAWAVIAUIATISHXFHdH %( H]HHE fEHE BADžt+HEdH+%( HeD[A\A]A^A_]f D AvAV HHH4 x! " xE u H EHHu:HuLEHHLHEHuH}EH HuHM!H}EHMt A: D A} H!} I$ HpHEI$ E E1E1H L@(1ID$XHD}H1AfA `@f LRHAPMQLAH @ HP A} zAuAU H5HH E1~! E VE u F EHHuHuLEHHLHE^HuH}EH HM H} EMHM } I$ HUHpHEI$ E teE1HtLH(H" LB( 1I A} sf H ILH( 1E1fH LJ(LIH<f D 1E1;f D AuAU HHMHMHHtqx! IHHM HMf D H} Hx Iͺ 1E1E11T 1H HMJ E1LE1IHgf. f UHHdH%( HE1G)GX;HEdH+%( u1e D UHHdH%( HE1H> G)GX/HG HEdH+%( u1f. UHHdH%( HE1) uH) G)HG GX#HEdH+%( u1 @ UHHdH%( HE1) uH+ G)HG GX#HEdH+%( u1t @ UHHdH%( HE1) uH G)HG GX#HEdH+%( u1$ @ UHHdH%( HE1) uH& G)HG GX#HEdH+%( u1 @ UHHdH%( HE1) uH- G)HG GX#HEdH+%( u1 @ UHHdH%( HE1HEdH+%( uOff. @ UHHdH%( HE1HEdH+%( u H6H? D UHHdH%( HE1HEdH+%( u H6H? D UIHHHdH4%( HuHHUdH+%( uHDMHh L1$off. @ UHIHHHHHPdH %( HMDHt7LH@Mt;HM1RH HUdH+%( u LH@HPMuLH8 UHHdH%( HE1HEdH+%( u HDHL H 1Gf UHIHHHLHdH %( HMDMt*HEdH+%( u!LH2 L1f D LH-ff. f UHAWAVAUIATISHHXHy dL4%( LuELT HQ(HG y1 H, LEHUHHEaLS8HULEIMAI9s E1E H[@HL9sE1ɄuzME1D]LUMtgMO, LELHULMLULMHULEI9Ms D]EuH9su HtLHIA uMOHEI)RDH LuL1ZYHUdH+%( uuHe[A\A]A^A_] LIMHEdH+%( uCI-f D HEdH+%( u(L HeDLL[HR A\1A]A^A_] T @ UfHAWAVAUATSHHhHpL># LjLrLdL$%( LeI)E)E)E)ELmHpLHxqX< LHC8vHxHHC@ H9 1 LjGHHs LKA}4 M~HEIV uIu IMIHI)H)H9I<$HuL9 ЈC1 u H}Hu4 uHwH+7XHH;C tj1{1 uHEL)HC( C0HEdH+%( uJHh1[A\A]A^A_] H.Hz1 FH( HEHCf UfHAWAVAUATSHHhHxL&, LrLzLdL,%( LmI)E)E)E)ELuHxLHpqX< LHC8HxHxHpHC@Ht H9 H9sHu}HtxLb1 LEHC HHuo, LHx]HK8HxH9sHuFHK@H9sHu8Ht3 Hx1EEHC H @ 1L)EHC HHLA~4 MgHEIW uI6INIHI)H)H9I} HuL9 ЈC1u H}Hu4 uHwH+7FH;C t?1{1 uHEL)HC( C0HEdH+%( u Hh1[A\A]A^A_] @ HEHC UfHAWAVAUATISHHhLzH># dL4%( LuI)E)EL})E)EH HxHx CHx< HC At$YLh@ > LIH L貫HCA$>H{ tsHs LvI>HuHE6u H}Hu4 uHwH+7DH;C tB1HUdH+%( u;Hh[A\A]A^A_]fLHY HEHC1 UfHAWAVIAUATSHHhLzH>, dL,%( LmI)E)EL})E)EH HxHx BHx< HC YH AvYL`@ > L1IH LJHCA>H{ t|Hs LI} HuHEu H}Hu4 uHwH+7PCH;C tJ1HUdH+%( uCHh[A\A]A^A_]f. LHQ HEHC UHATSHH>dH %( H]H, DH H;I]HC8A$,H{8 IL=HCH LHu AH}HC L9tb< HtSL`> LHEHt9 LިHCHE >H{ t 1HUdH+%( u$H[A\]fH{~H{8uf UHATSHH>dH %( H]H, 4H H;IMHC8A$,H{8 IL-HCH LHu ?H}HC L9tr< IHt`Hx> HEHtI LA$ ɧHCA$<HE >H{ t"1HUdH+%( u*H[A\] H{^H{8Uf UfHAWAVAUATSHHxHxHhLzH;dL,%( LmIպ )E)EL})E)E?Lx< HC ILH L`HhpY@ > LIH L豦HCA>H{ Ls LLoI} HuHE.u H}Hu4 uHwH+7?H;C tJ1HUdH+%( Hx[A\A]A^A_]f D LHJ HEHCf D * LHPIH5 LLx H- 1L=HC I UHATSHdH%( HE1) t$1HUdH+%( H[A\]f D H IHtS H5h HOu[I|$@ H5b 5u+H C)HC /+ Lc8fCXt lLff. LDf UHATSHdH%( HE1) t$1HUdH+%( H[A\]f D H IHtS H5 H_u[I|$@ H5 Eu+Hj C)HC ;+ Lc8fCXt lLff. LDf UHATSHHG@LgHdH %( H]HHtDH Ht<LH{HUH{LHEdH+%( uEHH{[A\], D MtI|$8I|$@I|$I|$<ff. UHAUATSHdH %( H]1ۃDu*Do@A v IHH5 Ht)f HEdH+%( H[A\A]]H5U LA HtH5 LH H5#8 L HuH52O LHyH5j LzHaH5V LbHIH5N LJH1H5& L2H HtH5i L Ht H5p7 LH D f UHSHhdH %( H]H{) uRH C)HHC Ht;HHEHMPHULM1LEH5$ ZY~$EC@ CD1HUdH+%( u H]ø UHHIHHHQdH4%( HuDHuzL HA H LIMt1HEdH+%( ɉH H1L? HUdH+%( uzI1HH L HMdH+ %( uJL LJ-H" H1L HEdH+%( uL H 1HLf. UHHAWAVAUATISH(H_HGdL<%( L}ILoH9thIH荟IMIH HM~I\$HEdH+%( H(HcL [H #A\A]A^A_]5 D HuHuMu:L LLH謤IHt?I\$HMMl$Mt$T @ HMHItA HEdH+%( uH([A\A]A^A_]½f UHAUATSHdL,%( LmE1>b ~cIH H5 Hҵ H5 H趵 Hvxʃ+ EHltL-z atkru|lL-Rz tL-z LHLHEdH+%( HL[A\A]]f. E1 ~dt' D |luH5Η HL-_z tH5 H vH5 Hp _H5 HY HH5 HB 1H5q H+ H"z LE @ UHAWAVIAUATSHD.dH %( H]HAb H5 HL%z ff. H5 HH5 HAAEtH5 Hx EL%z H_z LELHLMHEdH+%( v HL[A\A]A^A_] {tt"Ab6{f,{ t! { uL%z 6f D H5Q HYE M\efH5 HH5ߕ HH5ϕ HsH5 H\H5 HEH5 H.vAbu{ru { `H5o HL%z BH5k H+E1# L% z i诹ff. @ UHAVAUIATSHdH %( H]Hj H H\ D3L%)z H5ޔ HZtH5Д HG L%(y Abu {r H5 HtH5 HuBL%y LHLHEdH+%( HL[A\A]A^]f. H5O HtH5; HtH5/ HtH5! HxnMluf{ .L%z "f. H5 H1Hy LD D3IAbu{cu{tuL%z ;b~{rtsǷ UHATSH dH%( HE1) upHIHt_HMHULLEH52 F uafnMfnE LH5 fbfC@誯HC H HDHCP1C)HUdH+%( uH [A\] @ @ UHAVAUE1ATISHH5q HdH<%( H}HHt#HEdH+%( HD[A\A]A^]Ed$DAvҺ H5)- HA ۮtD3Acu {m A9 Aau {d Asu {u Aau#{nu {dA Zff. fAi Adu {eu{cA 'f. ;ou{rA AxuDsAou DsArEA D {dA B {pH5 HH{bA {n8{cA k#f E1U UHAWAVIAUATSHL>dL,%( LmIE'E 裟LHff. DcHEt IDB t L|IED#I} AvXH-HHt{`I}H59 HHt^HHu H-H}IE H9t<< Ht-HX> HIHt HIEA$>1HUdH+%( u H[A\A]A^A_]L+Ƴf D UHAWAVIAUATSH(H>dL$%( LeI, ;H M,$( HLHt0,I<$) H x, @ M,$HXLID$8,I|$8H E~ZE1Et8Av[@% E1 AHxDHuAAEl$PL{LAvXLIbHEH HXI9s3gHff. HI9tHIDA uD{C L8ID$D{I|$H A^ZE1t8Av[@g D1 HxDHuAHEE|$2H HL5 I|$8LHXHt[HHu *H}ID$HH9t<< MHt-Lh> L7IHt LTID$@A>I|$LHt\HHu *H}ID$ H9t=< Ht.HX> HIHt HID$AE >1HUdH+%( upH([A\A]A^A_] D HHfkHHf. LȻHI|$8=w UE1 HAWAVL}AULL- y ATISH8H_8dL4%( LuIH{@ I\$ID$M|$H9tqHLHLHUӐHUHHt$HLjH LI\$Hc HEdH+%( H8L[A\A]A^A_]f D Hu M H LHHUHIHtI\$HUM|$IT$GE1L LHL-Hy H5 LL-Jy %H\y LD IH" |֮f D UE1 HAWAVAULmATLISH8H_8dL4%( LuIH LH{@E1 LL-<y I\$ID$M|$H9t{HLHLHUHUHHt$HLjH LI\$Hc HEdH+%( H8L[A\A]A^A_]L-y u @ HuMuFH LHHUH,IHtI\$HUM|$IT$A @ E1{ QIH` Yf UHAWAVAUATISH( dL4%( LuIju A~a A>j A~r L- y I\$ID$M|$H9 HLHLHU諍HUHHt$HLjH pLI\$Hc {HEdH+%( H(L[A\A]A^A_]f D H5 L輤Tr A~e A~t L-~y 0f A~lL-$y f HuMuFH LHHUH\IH5I\$HUM|$IT$ IH f D AL-My <byE1e D UHAWAVAUATISH( dL4%( LuIbu A~l H5 L& L-Wy I\$ID$M|$H9 HLHLHU蹋HUHHt$HLjH ~LI\$Hc HEdH+%( H(L[A\A]A^A_] @ A>b b H5A L蹢 H5* L蝢 E1A~ L-4y f HuMufH LHHUHlIH7I\$HUM|$IT$ A~ ?L-y f qIH f D A~euA~qtbA~nu A~et bA~lt(bA~gA~el @ A~tXf D UHAWAVAUATISH(>bdL4%( LuIu A~aX H5 L L-y I\$ID$M|$H9= HLHLHUWHUHHt$HLjH LI\$Hc 'HEdH+%( V H(L[A\A]A^A_]f H5 LlX H5 LP< H5ۃ L4 H5ƃ L H5 L H5 L H5 Lğ H5p L訟 H5Z L茟x H5D Lp\ H5. LT@ H5 L8$ H5 L H5 L AL-]y <bE13f. A~lL-ty f HuMuFH LHHUH謌IHI\$HUM|$IT${ IH ٥L-"y (ff. f UHAWAVAUATISH(dL4%( LuIH5 LtH5 L L-wy I\$ID$M|$H9w HLHLHUHUHHt$HLjH LI\$Hc HEdH+%( H(L[A\A]A^A_] @ H5 L[H52 LJ H5 L3 H5 L H5ʀ L A<c <b E1<fEA~b:AVS B<"QhHAF, g( l n <e <z E1 @ HuMu>H LHHUH4IHI\$HUM|$IT$A aIHl f D L-y @ L-y AF<r tX<a <c <e& <gr AFt/<t E1<eAFt<uA~ L-y pAFE1w<AFIUAFluAA~z <lt E1<gAVE1e <gkzbx<zuA~ soA~ c_AFE1<c&A~ <<e0A~ L-y AF E1<qޡ<eA~ A~zA~ <lu"AF<t.<u~!<nt$<btAE1<vgAF<cW,AFk<et)E1<z6 AFE1<pt*<zAF1E1<g A~oA~s0E1uP Hs A~ <gt E1<lE1A~ef UHAWAVAUATSH(H}dH%( HE1=Aiz A E1L- y ff. M9s4K<H}IHIJ 0HLH3&x2t M~M9r1HEdH+%( uGH(H[A\A]A^A_] @ M H ` H=y hz T誟f. UHHH?dH%( HE1HUdH+%( ubf UHIHHHHwdH %( HMDLNMt&HudH+4%( uAAHHLA HudH+4%( uL LHy HL1ٞf UHAWAVAUIATISHHHy@ dL4%( LuEt[LDHz LL11HKHLH{8AHEH)I42DHUdH+%( uJH[A\A]A^A_]ÐHEdH+%( u+L LHD[LL1A\Hx A]A^A_] UHHdH%( HE1Ht HGPHtHMdH+ %( u D HEdH+%( u1訝 UHy H y HHdH%( HUHWH9H9 H py H9 HUdH+%( uBf UH$y H y HHdH%( HUHWH9H9 HUdH+%( u UHHdH%( HEH`y H9GHUdH+%( u賜 UHHdH%( HEHy H9GHUdH+%( us UHHdH%( HEHy H9GHUdH+%( u3 UHAWAVAUATSHhH}( HudH %( HMHcOHM HELeE1Lh D M9s6K 4H}HHHM| I7T ^ LsM9rHEHX0H L}L踦HHH HM AtHHxH HxLuHMLLH: 1t 07 tD0fD7Ht07D E1ff. @ HEI9sGI LLEHHIHI\ H3LE HEMD$I9rfHEH@ H HUdH+%( HuH}Hh[A\A]A^A_] @ Ix IGHtHUdH+%( } Hh[A\A]A^A_] D HHHκ H C(1H]ƃL3M69rI<H @ LeHCr1p貙f UHAWAVIAUIATSH(HUdH<%( H}ȿX IEHH I} IQ8 H HXI D`Et?HE H}H"ff. HI D#Et IDA t yIE8HtdID I?VLIIu8IE@Ht>H@HtIuHHULЅx$ @ HEdH+%( u H(1[A\A]A^A_]I}H>耘 UHAWAVAUATSHH,x dL4%( LuIx b IF A H9 n 轺HHQ Mn0I~8L xAV@H IVHD H HW Iu'HEdH+%( M HH[A\A]A^A_]fH8 I L`LcDhEt'UHILcE,$Et IDB tA$ L6xHH HCD(H{誰M&H3HCLHCHDH@H7IVHsLЅ"HC @ A lHH1 D D EDNIcH H)H< dH =H1|rf UHSHHGdH %( H]HHtH HtH{.f. H{HH{PոH{̸H{ øH軸H H 裸H 藸HEdH+%( u HH]ą迕ff. @ UIHHHdH %( HMDu0H t)HEdH+%( uBHGALH/ HEdH+%( uLOLH$p 1L+ff. UHHAUATSHHHdL$%( LeI̅y+H@Hp ' - H HcH> LH͖HEdH+%( 9 HH1[A\A]] D H Hp LH1- H H LH1 fo HE H )Ef)E)E @ H LH1N H LH1褻2 H) LH1脻 H LH1dH~ LH1I @ HEH LmHLMlff. UHAWAVAUATSH H $ H H $ H HM ~*x fHnHf LnfldH %( H]HII} HDž` Hh HHDžp HDžx )Pu H111袵IH HGx L H HHIHLOL'sIH HǾ/ HHtQH& H vQL LLʑx"HH5? LƄ Hz H @ HH t 9/ HOx H H HSH {t8 HDL,A}4 IT$ ID$uIu IMHHH)H)H ȸx Mt$- LM1RH B Hۯ P1M 1LH5x H M 6L4$LA ZY | v Hr/ ƅ/ ƅ. L5gx Hl HhMV8MQ IV0Hl A" H`H H A~ HtHl HHtl A~ HxtHM HxH? A~ HptHOl HpIt$ LDHLPHX It$LI MN(HXLl LPDHMD IN H5 HHHDH ARhASRHc AS`xpAWP1'H`AHx 0E\ HH}k 1LHfLH`HHpHPHDž HHDžƅEAƅ H5<i rHxHQ HHDž HX HDž fnDžP fp HDž` DpL )ff. Hxp HxHX HLH M LLL肟IHtLrA<:tL裦HIXHH H@H Hʿ fLfffHfHnJ42flfo fofDofDoHftfdfof`fhfofefDofDofDafifofefEffDafifAofAbfEffEjffAfDofDffDofofAbfAjfffAofDofAofDofDffAbfAjffDoffAofEbfAjfAffAoffoffH9fofsffI~H9^ A< uIHBH9F A< HBH9. A< uIHBH9 A| uIHBH9 A| uIHBH9 A| uIHBH9 A| uIHBH9 A| uIHBH9 A| uIHB H9 A| uIHB H9skA| uIHB H9sVA| uIHB H9sAA| uIHB H9s,A| uIHBH9sA| uIff. MY J L@L)HHHDHHhHHL@HI E1HILL1ME1MIM9 M C>LI< uH)H<LL0L8H@HHnHHH@L8L0HHZ t HD uILM9kfLMIIHMLH)LLMHI$nHB8 yHhLHHCE1 LH@H=Qz HhHx DhI HL}HHL9t 8:5 HHC0H`HLs8DpHCHDs@ALcDpIHb x@ txA t!It$HhMw0\AG@I)Mw8I tLt I( * LIhL)H0@P4 @ HcH 1LJH`pwLhH`E11fI H @J HH x It$HhHHnIt$ HhIZHHL9H9|HHL)Lvm HIt$LH HfHnID$ I+D$AD$HRHH 螡ƅ/ ƅ.5LWA> H\A~ E11H8f D A f. HEdH+%( o HeD[A\A]A^A_]L } MHn A H`LU LhHH kH_IHSH H菠Lwu2H# 11/ u . ,HPH|Hx H1AHa 01'HtHH 1OkL LtH`tL'AŅ P H Hx{aLH HLn@ H Lƅ. H߫x H1AH` 01UHx HH` 101"HLsAHLPAHix @I)M<$M9? DL5` ; D H tuIM IEfInHflHAHAE 规M;?tKMoI} I]uMe0LLTHuH5+` L@HuH5 ` L,HuDgL LHhfH{H ) HIG0)) H)0 HH H9pmIG(dA 1HH kHt y ƀ AAHx H 1L 01LHx H1AH 01&虁f UHHdH%( HE1HEdH+%( uɸZf. UHAUATIH=8` SHHx dH %( H]HHF0DhaHC8HC@ HCH 聠HtM)HxhI4$,H{8芣HEdH+%( u H1[A\A]]貀f. UHSH dH%( HE1H t 1HUdH+%( uGH] HH`1ctHCHuƸ D Hd aHC! UL@ HSHHdH %( H]HHH@ Hu D HPHxHt HHPR9r9sQHPHxHuHVfHFFLHHFH HUdH+%( u2H] D H1x Hr^ 01t1L1D @ UHAUL ATSHLHdL$%( LeIMHLtLxHEdH+%( u H[A\A]]~ UHAUL ATSHLHdL$%( LeAMhH@ f D HtHC@A9s/H[HuL HEdH+%( u%HH[A\A]]ÐD9s H[ D H5~ D UHSHLP HHP NdH<%( H}HHu* ff. f. HPHpHtHЋP9r9sEHPHpHufHGH>LRX HUdH+%( u.H]ÐHAx H\ 011L1T} @ UHAUL ATSHLHdL$%( LeI]HLL舦HEdH+%( u H[A\A]]| UHHdH%( HEHP HtP9s$H@HuHUdH+%( uf. 9sH@| UHAUL ATSHLHdL$%( LeAeHDLHHEdH+%( uHH[A\A]]| D UHSHdH %( H]HH HG8 HGH CPHEdH+%( uH]{f D UHAVAUIATSHc HHdL$%( LeIZI HtPIޅ~WH< 1$ff. ff. D HH9t'I4 H4HuI ՝ EuT1HUdH+%( u H[A\A]A^]zf UHAWAVAUATSH(dH%( HE1H t*1HUdH+%( H([A\A]A^A_]f D G$IE ] Hcþ HHE7I IH ~XE1 M LDFuHDIAD$ M IDI IA$aCL9}uEAE$* @ CEAE$P yff. UHAWAVAUATE1S1H(dL,%( LmI @ AHHHuE EelADLeL} L5X L= / @ H S1LL轪x9 LLIx%HHHu1LnI 1 LHUdH+%( u9H([A\A]A^A_]Hfx HW 01뿸vxf D U HAUATLPSH dL$%( LeILÅt"HEdH+%( u6HĘ [A\A]] I|$0hLXID$0Hu» w UHSHdH%( HE1Ht Ht#HQ HUdH+%( uH] HCw D UHATSHdH%( HEGPt HUdH+%( H[A\]H H5V HIo H5L& Leo H5T LIo H5>V L-otq H5-V LotY H5S LntA H5V Lnt) H5U Lnt1CP1 D CP Bvf UHSHdH%( HE1Ht G$HtHUdH+%( uH]kC$u UHSHdH %( H]HH聘H{ xHEdH+%( uH{H][uff. @ UH HAWAVAUATSH(dL$%( LeIHHE蘏M$@ L(iHt5HHILkLLHLҗLeHuADŽ$H M$P LhHHt0f. IHULLHgLdHuADŽ$X H}%LLLI|$BI|$8I|$.I|$($I|$0I$ I$ I$ I$ I$ ٖI$ ̖I$ 迖EL$tE~*1ff. I$ H<H蒖A9\$tI$ ~I$ qED$dE~31ff. HHHI$ Hx$lA9\$dI$ 'A$ ~'1fI$ HHH<A9$ I$ At$h~(1 D I$ H[HH|轕A9\$hI$ 評AL$x~<E1f D I$ LIHH|I$ H{kE9l$xI$ E1TAT$|~i @ I$ M1IL~&f D HGH<HI$ L9 HIM$ I}E9t$|HEdH+%( uH(I$ [A\A]A^A_]鸔qff. UHAUATSHdH%( HE1HO H_HB H5Q H軵c ;i: H5!Q H蛵S L%N HLid H5 Hih L%bN HLi) D#Aau {rE H5P H8 L-1 HLGitcL-cP HL,itHL-M HLit-Ap {p {c ff. @ LR =<z twH <z {8{6ff. H CG H oM HEdH+%( HH[A\A]] L H=;z Ru1H L {mH D L%L HLht;su{hu C0 v"L%L Hߺ LgID;H /So UHATSHH dL$%( LeAHt%HUdH+%( uQHD[A\]f HhHH HuHEdH+%( uHH [A\]n UHATSHdL$%( LeLg0MtHEdH+%( u HL[A\]H}uLc0inf UHATSHdL$%( LeDglEtHEdH+%( u HD[A\]HduDcl nf UHATSHdL$%( LeL Mt HEdH+%( u&HL[A\] D HPduL mff. UHAWAVAUIATSH(u dH%( HE1 Wd1E1/ LHI Hxy9LIE9edڃHcAHȺI HH ~Hc۾ H |oAEdE HE ~p D HU1E1AHI HzI|Hc& I IADD4|HcID9HEHEA9EdMx^HcEA9 ~QI HUdH+%( u?H([A\A]A^A_]ÿ ϹI HHtA k @ UHAWAVAUATSHdL,%( LmIH AEl~OIE1L}3H];:u:HLH蘯tLHAvH|E9el~1LSPHu1HUdH+%( uH[A\A]A^A_] D ,kff. UHAWAVAUATSH8H}dH%( HE1H) IH HIvxEIHc[HH IcLHIHHEOB3=H5 L蟮HEuoLchtE AL IE1Mc IM9 K<>LHbuH8ZHEHMH J8HDZf D Hc@|~BHMDeHL ALHEIcHEI~Lt;HEI I9uHY1HUdH+%( uaH8[A\A]A^A_]f D IcIN~IL< @ IM9tI<$HUHauHcYI$HMHDOif. D UHAVAUIATISHdL4%( LuI}RAt1<u I4$L1҅u Mt$ HEdH+%( uH[A\A]A^]h UHATSHHHH3dL$%( LeI裬1u Lc HUdH+%( u H[A\]eh D UHHdH%( HEHȃttJ : H G HG HEHUdH+%( HHG 1bfHUdH+%( udHH 1bf. HUdH+%( u4ɉHǾ H 2 1Xb HEdH+%( u1xg UHHdH%( HE1HG RwHw H4 HHHDHUdH+%( ug UHSH(dH %( H]HHuHuHHE x~ HEH1HUdH+%( u H]øff UHSH(dH %( H]HHuHuHHE wx~ HEH1HUdH+%( u H]ø9ff UHAVAUATSHHVdH%( HE1HteIIL%h 1 @ H H@AF8CHH9s4HLHHHtCvHuKH@AFCHH9r HEdH+%( uMH[A\A]A^] @ Hx AF @ H1x L101{IUsfH@Ae?eff. @ UHHD H L@HH@ dH<%( H}HHEʋP RDHHD 1_HUdH+%( uHd @ UHD HAWAVAUATIHSH8HuM|$ AL$ED$ EdH%( HE1D}+_HcE IE1 f D EEEuM|$M $A9thDLMI8LMH}DIH PHC 1AW^Y^HHAuH}HC 1^HHfLELMDILMH}DIH HxC P1AUP^HHXZHEdH+%( uHeH[A\A]A^A_]cc UHH<C L@HHHH1dH<%( H}H ]HUdH+%( uHcff. UHHdH%( HE1HEdH+%( u H-b UHHdH%( HE1HEdH+%( u Hb UHHdH%( HE1HEdH+%( u H-Hb UHHdH%( HE1HEdH+%( u H]Fb UHHdH%( HE1HEdH+%( u H=pa UHHdH%( HE1HEdH+%( u HHa UHHdH%( HE1HEdH+%( u HmVHa UHHdH%( HE1HEdH+%( u H a UHHdH%( HE1HEdH+%( u H=` UHHdH%( HE1HEdH+%( u H}` UHHdH%( HE1HEdH+%( u H H` UHHdH%( HE1HEdH+%( u HM` UHHHPHdH<%( H}HHp(f V f҃rRHg p pLHD@ 1bZHUdH+%( uH_f. UHAVAUATSHH`dL$%( LeIG@ GDLGHG@sɃᵃx҃ⶃwHAPrV QLRH Ps8s0C,PC(P1s sLKDC YH`HHUdH+%( He[A\A]A^] W(LuHw,LmL>LLCDLCH{C@APsV Ƀᵃx҃QLwRH~ ໃrP1AUs sLKDC XH@H8]f D UHAUATSHdL,%( LmI蚬H= I1LqXHcMt9LLnHLNHEdH+%( u1HH[A\A]]f D H~ L1XHHN]ff. UHHAUATSHdL$%( LeI@H`Y I1LWHcMt5LLuHLUHEdH+%( u-HH[A\A]]fH9~ L1jWHH\ff. UHHdH%( HE1HEdH+%( u HyX\ UHHdH%( HE1HEdH+%( u H g\ UHHHPHdH<%( H}H RDH H3 D@1VHUdH+%( uH[ UHHdH%( HE1HEdH+%( u H x[ UHHdH%( HE1HEdH+%( u H 8[ UHH H LW HHLHLPdH<%( H}HH5 AHDAHDAIEVL@ Q1LRHe| xUHUdH+%( uHZ UHH: HHHD@ dH<%( H}H1 'UHUdH+%( uHOZff. @ UHHF: HHHH1dH<%( H}H THUdH+%( uHYf UHHGdL%( LUI uY G DOH 9 L9 HH9 LP1PTZYHHUdH+%( @u#tfG DOH 9 L9 tSG DOH Y9 Lv9 @ H Q9 H=& L1SHx @ H 59 H 9 Xf UHHPHHHHdH<%( H}HRP RDHHz D@1WSHUdH+%( uHXff. @ UHH8 HHHDH dH<%( H}HD@ 1RHUdH+%( uHXf UHAWAVLuAUIH|8 ATI SHHhHOLdH%( HE1RLcMtwLHsI$` SHEHtMH腄xAH}Hs4 uHwH+7HuctHEHtLLH If LIKDC 1H7 LQsH{MM LcEH Hx,sMMHHxH ICE MHHLHUdH+%( uHh[A\A]A^A_]Vff. @ UHAVIAUATSHH?dL,%( LmI^H] H1LQ;LcwH HcH> @ Hμ L1PHLff. fHUdH+%( P H[A\A]A^]LH6LLHvLLLHrL D LHL LH%LHKH 6 L1 &PHL\ @ LH譽LE D LHL- D LH L D LHEL D LH]lL D LHwL D LH5L D LHELT UHHdH%( HE1HEdH+%( u HvXT UHAWIAVAUATASH(L7dH %( H]HH}LVxIH{z3HC H{)xHC H;YH H}L{(HDc2C1 M A AtAA H|x 8 " HXx C0gM` D`%A Hx 8 . C0LdHs(LHC0OHCH 1HUdH+%( H([A\A]A^A_] Hyx 8 Hx C0kM` D`%ALdHs(LHCNHCHtEt HHCx4 HS(uHPH+HS(`Au=H{x u : H fS04 H fC0 MRC0H @ UHAWAVA@AUATISHH(dL,%( LmI͉u6eH;I;vuLH]Mu8D8t3HUdH+%( uEH(LLH[A\A]A^A_]d D HEdH+%( uH(L[A\A]A^A_]Qf. U@HSHdH %( H]HHA dHt-Hs(H{0nHCHUdH+%( uH] HCQ D U@HSHdH %( H]HHA "6Ht-Hs(H{mHCHUdH+%( uH] HCP D UHAWAVAUATSHHHH}L-E}x A}$ dL4%( LuI Ht AvH}薤IMe E|$ L]NH=0 HD1RIHLA 3cHCHn Lx Ma I 1H=0 RI t LMI H裸HZ I HtIct$$0H; I HtIct$ 0H LԄAFXfC8CC4x&HMH HtH Ht HC8H{I H Ht%M I HH H{Hs(kI HCHt H Hp-諷HtVf D 1HUdH+%( HH[A\A]A^A_] @ E1{0HH5-/ H5,/ HCHtQLHHCx4 uLL+HLe 1 LL2 ^I LHVI HtzHCHtqx4 Lc(uL L+`Lh.H A, tDI HzHt4LcHGI9r LI9HHuff. K1 AV AvH}蟕I K1 HtK1I yK1pI I; u H{ff. K1 I ԵH{Hո Lf D UHHdH%( HE1uGuHUdH+%( u HqL UHHdH%( HE1?uHWHBHHuHEdH+%( u!2HUdH+%( u Lf. UHATSHHHdL$%( LeIHRA$ 1AD$XH{HC C4Ht Hs(hHCHEdH+%( u H[A\]Kf D UHHdH%( HE1HEdH+%( u@KKff. UHHdH%( HE1HEdH+%( u` Kff. UHHdH%( HEHH}dH+<%( uHzHHJ UHAUATISHHdL,%( LmI6LHL薇ǃ ǃ Hǃ ǃ HEdH+%( u H[A\A]]>Jff. UHSHdH<%( H}迨 lHHt 11HHwHEdH+%( u HH]Iff. UHHdH%( HEHH H HEdH+%( uI UHATISHdH %( H]H r L A|$tHEdH+%( u+H[A\] HEdH+%( uHL[A\]! Iff. UHHdH%( HE1Hdž HEdH+%( ueH UHAWAVAUATSH(H}dL,%( LmL.L9 Iff. fInflM9 IU IELH}HBHAE uM>I MM9u HIL9tGIHLLtIGIfInLflH}IHAHAtHI9uM.M9ZHEdH+%( uH([A\A]A^A_]MGf U HSHHxH foYX sdH%( HE1hHH B H`H`sHt"HHt1HUdH+%( u H]ø G U HAUAATIHhSH foW At$dH%( HE1XHHA HPHPjrHHt3H8` H= D ƀ q'HLH OsHEdH+%( uHĘ H[A\A]]ZFf. U 1HAUATIH= SHdL,%( LmAH5- HH= w3HǾ n H}nD HLƃ rHEdH+%( uHH[A\A]]Ef UHAWAVAUATSH]fHnflH(dL$%( LeI)EH IIE1(f D HUIHEILj HHPHM9tNAt$LDpHuH}L'H9t ff. f;7LM$$H9u HLUu1HUdH+%( uH([A\A]A^A_]D UHAWIAVIAUATSHdL,%( LmIHt(I1ff. LHIĈ }I9uHEdH+%( u HLLL[A\A]A^A_]8D UHHdH%( HE1HuHEdH+%( u 1 D HEdH+%( usJCff. UHHdH%( HEHH9u5ff. fH H9t xu;puHUdH+%( u @ 1oCff. @ UHAUATSHdH %( H]H H9tJII fHI9t8{uH L#uHEdH+%( uHH[A\A]]f1B UHAVAUATSHdH%( HE1HtKIIHE1ff. fH3LHtH u6HSH IHM9u1HUdH+%( uH[A\A]A^]øDB @ UHATSHHH1HdL$%( LeI̹ H= w4L HHn1HUdH+%( uH[A\] A @ UHSHdH %( H]H H s HCH CuJHHCH;BuՋCps;s}/HHz HCQH{ C Ht)4s HC HEdH+%( uH] HCA D UHAUATISHH8H~ dL,%( LmIHuHE HE <HEELmH9t~HUMt4H{ 1PH}ЉƉE脬HEuH EtIfoEHEA$foEID$ AD$HEdH+%( u'H8L[A\A]]f D E H}7 @ UHHdH%( HEG9GHUdH+%( u? UHAVAUATISHĀH_dL4%( LuAH" LmL H`LH]L_+o`HE)EopHE)EEub H(6H ulH}H9 uH tՃ uC7H tu.7H5Hn H}H; u LhI$I9uNAƄ$ HEdH+%( H[A\A]A^]f D H t xt ƀ H I9tH9 uf D Hx tƀ H *LؖI$I9ukf. H I9UH9 uH tƀ 1H&N4E1@= UHHdH%( HE1HEdH+%( u1=f UHAWAAVAUATISH dL,%( LmLoL˔ LmL趵 HPE1H]HHHHLL(oPHp)Eo`HE)Ef. H3HP 8 H} uH9 uH t A9uuGXGA AƄ$ HEdH+%( HĘ [A\A]A^A_]fHPE1H]E1HHHHLL(oPHp)Eo`HE)E H2Hp H} uH9 uH tȃ D9uuGWGA f D EtAFA WLI$I9ufH I9H; uH tƀ EtAFA L谓I$I9ufH I9tH9 uH txtƀ fH Hx u 1LJKE1W: UHHdH%( HE1HEdH+%( u1Y:f UHHdH%( HE1HEdH+%( u ɾ :f D UHAWAVAUATISH H_dL,%( LmIHI H]H4 HHM$ HPƅG E1H]H8HHH8LZ%oPHp)Eo`HE)E/ D LLtA u M9 t.H0HADŽuWL}AuI u I tA A9uuLF&UFG G tAFA HH8I$HI9u0 LHt H9 HI9t {uH{ uHI9u I$I9uR E1E$ HEdH+%( HĨ [A\A]A^A_]H t tHI9tH9 uf. H ^ƃ Rf D 1HGHDžH D HPE1H]E1H8HHH8L:#oPHp)Eo`HE)E D H.Hu<H} uH9 uH t AD9uu5SE EtAEA XHH\I$I9u;ff. f D H I9t"H9 uH tƀ H I9uAƄ$ Cc6 UHHdH%( HE1HEdH+%( u ɾ K&6f D UHAWAVAUIATSH H_dL4%( LuIHY L}LD HPLLeL!oPHp)Eo`HE)EMu&f @ LH t H; tpLH,L H]{uH{ u D H tu^-L,L H}H9 u H tuH-vf D Aƅ HEdH+%( HĈ [A\A]A^A_] LHI] I9u' D LH-t H; t HI9t{uH{ uf H tƃ D 1H~DUE1a D LIE I9u#2ff. H I9H9 uH tƀ 3 UHHdH%( HE1 t H]ax HUdH+%( u Hqax 3f UHHdH%( HE1HEdH+%( uE1 1+A3 UHHdH%( HE1HEdH+%( u 3 UHHdH%( HE1HEdH+%( uA 1*2ff. UHHdH%( HE1HEdH+%( u{2ff. UHHdH%( HEH냵FaHH8HD`Huf H HtH9puHUdH+%( u 2ff. UHHdH%( HE1Ht HtH@HUdH+%( uÐ11 UHHdH%( HEH H>@: NLFHH Hc H9 H)I HtFH냵FaHH8HD`Hu( H HtH9HuH@ff. HUdH+%( u7 uNLFHHHc H9} I s10 D UHAUATSHdH %( H]HH Ht3S0~lE1E1 @ H LAI =D;c0|H Ht4C0~-E1E1 D H LAI O=D;c0|H RHEdH+%( uHH [A\A]]R/f. UH= HHdH4%( HuHuTHy x E ) 1Ht HPHuHUdH+%( ux HHH HtP HH8uHHH<uHHH>uHHҸ H?)H @ H0 H¸ . UHHdH%( HEH9t=1HuHUdH+%( u1 D HWHuHy HGH @ Hq. UHAUATSH dH%( HE1H HIH5_y HSHM Hy HHDHH!1HHH HCH HH b H H H9: HHH8uHHH9 HHH> H?d Hhy LpLHHI3IL1HUx HSO 01ZHH } A $1HUdH+%( HĈ [A\A]]f D ? HHH>`HT HHh HHh8 HqTx HN 101跆f,/ ? f UHHdH%( HE1HEdH+%( u H\x7, UffAnH fHnHHAUAATSHHxfnUfnMdL$%( LeA)E)Efb)E)EfAnfbHE flHEE~w fl)p( H HHC8HFSx 01蕅Hs8ADH}LeLHpHM-HUdH+%( u Hx[A\A]],+ff. UE1E111HHdH%( HE1j jRHHUdH+%( u*ff. U1HAVIAUATSH~/ dH %( H]HtK,S(HsH;/hIH {. ueH{ tvaIM H{ LLLAF]gL"L]1HUdH+%( ufH[A\A]A^] {/ uH{ I @ H; uH{ y{, uH{HuҀ{- u_L) UHAUATSHdH %( H]H H9tbII fHI9tPH8 Ht HGu@H8 H98 tI] HUdH+%( u H[A\A]] D 1 @ I] %) D UHAUATSHdH%( HE1Ht_H IIH9uKff. HI9t8{uLHwotHUdH+%( u H[A\A]]f 1ٸ( UHAUATSHdH%( HE1Ht_H IIH9uKff. HI9t8{uLHXtHUdH+%( u H[A\A]]f 1ٸ ( UHAVAUATSH dH%( HE1HtnII1H}H nxs1L- HI9t9EHMH}L 1nH}ȅx9|HEHHEI9uHEHUdH+%( uH [A\A]A^] C1:'f. UHATIHSHdH4%( HuHFhLHHX$HAHEdH+%( u HD[A\]&ff. f UHH u dH%( HUHUHUdH+%( u& UHATIHSHdH4%( HuHgLHHHA=HEdH+%( u HD[A\] &ff. f UHH u dH%( HUHU{HUdH+%( u% UHHdH%( HE1 tD 1x8 x.HH9u :f. ; uH H9t ; t1HUdH+%( u D D% @ UHHdH%( HUH Hu HH9t H P(H H9uH HEdH+%( uH$ @ UHHdH%( HE1HLJ HEdH+%( uG$ U1HHdH%( HEHH9tff. fH PXH H9uHEdH+%( uHK$ff. UHAWAVAUATSHdH %( H]H Lc0Lk(H9tJIML5iF . HKx LL 01}HI9tLC0M9uHI9uI AAAEHUdH+%( uH[A\A]A^A_]#ff. UHHH?dH%( HE1G:u HEdH+%( u"1f HEdH+%( u&#f D UHHdH%( HUHHH9t<J: ff. ff. H H9tP:1ʃt1f HUdH+%( u" D UHHdH%( HEH@:HUdH+%( ud" @ UHATSHdH %( H]Ht+Ht&HnIHtL`H8u @ L#HEdH+%( u HL[A\]!ff. f UHHdH%( HE1H HEdH+%( u! UHAUATSH H_dL$%( LeIH Hx LmL H`LH]L o`HE)EopHE)EfH}uTHHttLyI\$I9t'ff. HHH[I9uLkff. @ HEdH+%( uTHĈ [A\A]] 1H0ff. fI\$I9tf D HXH[I9u8 UHAUATSHH( dL,%( LmI I] I9tff. H舅HI9uLlI] I9u] D HI9tPH H HzAąyL}DډHEdH+%( usHD[A\A]]fE1 I} YHIHHt8[ IHt#HHLE\LMH HAj UHAWIAVAAUIATMSHH dH%( HE1LJ H HdH(yd5y Eg 1 % ,( 1 H5 1j$h( H VÃV oJf D Mt7HH8 1H0L0H E [I} $( H LVH, 1 , 1HUdH+%( H [A\A]A^A_] D : @ I} LI} AA}, 6I} +H{(Hta 1ޔf I?LyMz0 HHZ HkFx A H G H> H81(u,j _$Tff. UHATSHdH %( H]H y'E1HEdH+%( uIHD[A\]f Hu E >{Aą8 ǃ g UHSHdH %( H]H x# Huǃ mHEdH+%( uH]ff. UHAUATISHHdL,%( LmI褖HtbHHLlÅu HCx 8 u HEdH+%( u:H[A\A]] Iu HtL HtH@,I 뾻Q UHATSHHdL$%( LeI Ht%HHEdH+%( u0HLH[A\]pHEdH+%( uH[A\]ff. f UHAWAVIAUIպ ATSH@H dL$%( LeIIǃ tL LH{ LL1 AHEdH+%( HĨ 1[A\A]A^A_] D H<H= = I z=xHc<LK II9rLH = LL1@f. LH; LL1y@bHcLHq H)AL1U@AEHcLH; 1H)L3@LDH; 1HcH)I| @ D HcLHc; 1H)L?5 D UHAWAVIAUIպ ATAH@SDH dH %( H]HIAtBHHy HL1{?HEdH+%( HĨ 1[A\A]A^A_] @ Mv8H<H= ;LHLD<I H; 1E?<AD9~&IcH< 1H)LH>l HcHD1H)H< L>A f UHAWAVAUATSH8H dH%( HEHEfHnHEfl)EH9 L;IIH9u{ D IM9tJLIHLII9uHCH HUHAHHEH]HHCHIM9uHEHuH9tIU HMLhIE HHJHEdH+%( uH8[A\A]A^A_]ff. @ UHHdH%( HUHH9t3H"ff. ff. @ H H9t tHHEdH+%( uH UHHdH%( HE1 u'HH9t @ H9t+ƀ H H9uƆ HEdH+%( u @ HH9u! UHAUATISHdL,%( LmAǀxtAALUHHt HLrHEdH+%( u/HH[A\A]] D Hx HuEtHLff. @ UHAUATSHdH %( H]H H9t+II @ H tLHu HI9u1HEdH+%( uHH[A\A]] ff. UHATSHdH%( HEH Ht( HAC w1 HEdH+%( l H[A\] @ u[uLJ O0~E1H LHL)H| x11 $@uK0ID9 y D ff D LJ O0KE1 f D H LHL)H| x 1 $@ K0ID9f LJ LJ Hq<x H= H`{y ,ff. UHAWAVAUATSH(U@dH %( H]H HD HtDLceLHL)HHHEdH+%( H(H[A\A]A^A_]f. HcG0IAHHH)H4HHtAV0~YA1H &H߉EIR A~0~5A f LUI AH L E;~0|Et-A I L D I UHHdH%( HEHH9u%ff. fH H9t@8 u1 f D HUdH+%( umff. f UHATSHdH %( H]H,ztHEdH+%( u H[A\]L#H7AƄ$ D UHAWAVIAUIATSH(UdH<%( H}HM~H H HHx7x D 01iM>M9thA @LhIt,ED Et LpDeHLfAƇ M?M9t HM9uL IAĄtE1 @ u ǃ HEdH+%( uH(H[A\A]A^A_] UHAWIAVAUIATSHH(dL$%( LeI ?fHE H5 HAƅ CH{ <, RHH , H 'H HHE1誉HU. z AE A$ H f D dPDwA:AHOLe1HLHMHMAE LmL9 , Hd&Ht3I9 I1LLAHEI9 8 HEdH+%( H(D[A\A]A^A_] 1 H豈x=AE A$ Lb1 L腈xLAf H4x Hً0He 11g_jD0A @ AIH4x L0 A+ UHSHdH%( HE1: u HEdH+%( u9H]f. xHEdH+%( u H]2 f UHAUATSHdH%( HE1tSAA 1HA xLD D 1HUdH+%( uWH[A\A]] @ Hy3x H*1 01eH[3x H41 1ǃ 01ek ff. UHHdH%( HE HUdH+%( u& f D UHATSHLgPdH %( H]Hht%Hc Iǃ Hǃ HEdH+%( u H1[A\] UHATE1SHdH %( H]H t H5s "jAăt"HEdH+%( u4HD[A\] H 2x H/ 101Id" f UHAWIAVE1AUATSH Lc LoPdH %( H]HRt"Ol AEftu; 1fAEHEdH+%( V HĈ D[A\A]A^A_] @ H{ fE1Hh)E)E)E)EA Hh -BAƅ2 {< < 4 BD%IT$I> H0x HX0HE Lp A? H`H1H bH` H5:h !i EE~{ q r EHU < HXH 1A01ibPvO AE`LZf D ue to uzE1H/x HXHX0I?{ L uL HEH H`H1aMLI D HA/x A H[- 10HX1yak @ H` H5j r D HXH 01a @ AwLPZ Eƅ Dž{ t=< Of}-v f}-g f}-F+} !ƅ{M7M9 L%0x ff. @ I$HhL4M6M9uE1 H` H5# H` H5 `uB >EHUpL蠂HXH 011_uH` H5@ HX H 01_LHXH 0LbLhLDhHI LLuwLo HXI Hu 1E101 _H` H5h& . } ƅ|#`L E1} ƅ}HXL1E1H{* 01z^ Nff. UHAWAVAUATSHhH}HudH%( HE1t0E1HEdH+%( HhD[A\A]A^A_] HEIԺ HLHEETHU: HP H9 HMA4uff. A<$ = M1LeH5 ILuLmLL}I1MLLHV E9E LcEELIT$H5 ; u( LLeHU%HUHHE H HUIHHEHxH A<$ > HU LmE1HxMIHUH5; fILEHU1LLHU UfnMfnfb9U HcEfC u C9T IH5 IG1A} uHxHUL9 H] HSC^Cƃ H}A 1AHED@ E HMHH H@HM A4 HE@4 AHEDEHx $DEH}DEXDEB A0^8AADE;H 1HH(x 01+[DE닋xDEIDEvA Ap D UHSH8dH %( H]1Ht^HWf1B+HG HcЉ)EHiMb H&)Hci HM1)HUHHi@B HEMx!HEdH+%( u@H]f. ]8:H 1HH'x 01$Zff. f UHAUATSH8dH%( HE1Ht!HH?1HcS HGPHPfHu*1HEdH+%( H8[A\A]] Lc A =mL-.'x 11H Au rYHCLHHPH9 ILHH9sHS{f1BB+DLc 1HcЉ)EHiMb H&)Hci HM1)HUHHi@B HE0L C\8*9Au 1HHu 1X @ S(L-T&x 11H IAu XLHCHH90 @ f{11)EHUf)EKx f. [88Au H 1H1 Xf D UHSHdH%( HE1Ht7HH?Ht,Hr HEdH+%( u)HH]V HEdH+%( uH]~ff. UHSHdH %( H]HHǠ aH H HEdH+%( u HH] ff. UHAUATSHdH%( HE1H IKLLI<$H I9t8 HGfHnIflHCHHLJ HHM9uAD$ LHEdH+%( u5HL[A\A]]If HEdH+%( u H[A\A]]! UHATSHdH%( HE1H| IH5 LH HE[&uGA|$L~ I $I9t H1VAHI9uHEdH+%( uHH[A\] L1off. @ UHSHdH%( HE1?Ht2HH[uHEdH+%( uHH] H1ff. @ UHHdH%( HEHH9u5ff. fH H9t 9 uHUdH+%( u 1ff. @ UHAWAVAUATSHdL<%( L}L?L9 III1H D HL9 LH j5 IHcLH 1H)L!M?M9tMAt6LHuHL9syLqH Sa I D I uM?M9uHEdH+%( uNH[A\A]A^A_]HcH 4 I)IHu LL1 ! H ` 1Nff. UHAWAVAUATSHdL,%( LmL/L9 IL= f D Mm M9twLogIL9tH HtL HtLff. I9$ tL9 uHHoǃ HHuMm M9u HEdH+%( uH[A\A]A^A_]]ff. f UHAWAVAUATSH H8H0dH%( HE1Hz HHIHc L#L9uE. f D Lx0LLXLHH t?H_M$$L98 L@IHtvx uVIf D L@ LLL(:VLL(MH x H12PHy 1H0SQXZe @ cVLHIXLHHG8L@ LLL(ULyL(L nf D HEdH+%( u7HeL[A\A]A^A_]; HEdH+%( uHe[A\A]A^A_]u D U: HAWAVAUATSH(dL4%( LuIfE] I L= I9u HI9txH tL / LHuӾ: LIHt~ L H 1H}MMML <u/AE :HI9ufHEdH+%( u7H([A\A]A^A_]fH tHEH D @ LmUf. f. f. f. f. UHAWAVAUATSH(dL$%( LeI E ff. fA$ E AD$0 E E1E1 f D EI EA9D$0 I$ LHu f D H LHA v:H~IHt>LLpHt H HuHx H 1011N HS E} HEdH+%( u0H(1[A\A]A^A_]þ L8AT$0 UHAVIAUATISHHdL,%( LmIF*tNAvH HHtYL LL 1HUdH+%( u9H[A\A]A^]f D Hx H 101'MK*듸 D UHHdH%( HEHH9tSff. ff. ff. ff. H8 @ @@ H H H H9uHEdH+%( uff D UHAUATSHdH%( HE1H H]u<{eL#L9u M$$L9 HS(HsLyHwHUdH+%( H[A\A]] @ L#DL9t#ff. @ LDE7M$$L9uH>Z ǃ 1H HH;^_1e H<L#L9u 멐M$$L9tL?t UHSHdH%( HE1Ht?LJ H1H 4HEdH+%( u*HH]8 HEdH+%( uH]f D UHHdH%( HE1HEdH+%( u1Mff. f UHHdH%( HE1HEdH+%( uff. @ UHHdH%( HE1HEdH+%( uHIо H 1| UHAVAUATSH H $ H dH%( HE1HH HL- f D HH xux.L`uA|$ t׀x.u!AD$. 9uA|$ tf. L MLH1LHHL&nLH= LLAE?A H HEdH+%( u$H D[A\A]A^] E1E1Yf UHHdH%( HE1BHHH t HHHQ @ǀtH@IIAAEHQX t HHHQ(@@t HHHQ @t HHHQtH fHn@u fAHEdH+%( u'f. HȉH fnfnfbpUHAWAVAUIATSHHG8dL$%( LeIԨp O8 A LLG 1H)H{G LAC: L=H AE :HEdH+%( H[A\A]A^A_]f @ A L=G Lh L1H)L AƋK8Ic 6C: e D McLG LL)K|5 1>f D G: )It$I}G 1HG L=G t A L=F Lu L1H)LVAC8@.Ic I}It$k 1L=F L!DpC8Ict@ m A L=^F @ HIcL1H LH)LC:#A O8 G:ff. UHAWAVAULATLALS H( dL4%( LuI13 D HHxHЅ DBA w<I1HHTPHIH9uʺ LD#H IL L맄 H9 ?(HWt! HP )t+HH9u LD"H` IL LH9 : HB@ H9 8HP* H9 : HB f 1A 5f D HHxHЅxaDBA IE1HHTPHIH9uɺ LD!H IL LHHxHЅyf } E1A . @ HLOHЅxYzЃ KLE1LDPMH9uκ LDf!MH~ LIL HLOHЅy IMHUdH+%( H( [A\A]A^A_]E uȋ9t H D EuILM1럺 LD HH~LL LD HH[LL LDz HH4LL LDS HH LLE1Off. @ UHAWAVAUATASH( dL<%( L}Iυ LALL @ Hp tD toHH9u LD H~"ILHp uff. @ HUdH+%( H( [A\A]A^A_]f D D9uH9 >cHFuH9\ 8pHxuH9# ?uHwtHp t t*HH9u LD H^ILHc1H D H1A 2 H8HpH DGA wCI?E1H<H|xHI?H9uɺ LDi HIL E HH9m1L LD HHLL LD HH\LL LD HH5LL} D UWHHdH%( HE1w Hw HHUdH+%( uzf. UH5| HSHdH %( H]HW(tCH5q HD(t@H5h H1(1t9HUdH+%( u1H] @ f f @ UHHdH%( HE1HEdH+%( uff. @ UHHdH%( HE1HtH;=/y r2H=/y HtH5/y HtH/y 1HUdH+%( u ø)f U 11HHdH%( HE1ff. ff. D HH@u HUdH+%( u UHHdH%( HEHG( u|@} HHHHHHHu3 DΉ HEdH+%( u-f D @ 1ҹ ĺf D UHHdH%( HEHG(HtHEdH+%( u( H HG(HEdH+%( u5G UHHdH%( HEHG(uHEdH+%( u-f D փ H!Hw(HEdH+%( uF.ff. UHATSHL%. x dH %( H]HA|$ tHcXA|$ tHc0A|$ A|$ tCl A|$ t c;Cl A|$ tHX A|$ tc:Hh Ht urA|$ tHcX?A|$ tC8udA|$ tc;A|$ tc;A|$ tHcXA<$ tc:HEdH+%( uQH[A\]f c:f. Hc0f H߾ @ s HLff. UHSH@@ dH %( H]HHt6L HHK0HEdH+%( uH]f. T @ UHHH dH%( HE1HtH=m -#HUdH+%( uf UHAUATISHHdL,%( LmA耱H=VF E 螿HHǃ@ HP H Hǃ HH H H H H( Hǃ fHnH8 fHnflǃ fl( 8 j*y I|$TH߉ Cƃ fHǃ Hǃ ƃz ƃ~ HEdH+%( u H[A\A]] D UHAUIATSHH=)y dL$%( LeA$ HHtDLHj{t$HEdH+%( uqHH[A\A]] HCH uI} ufo C 뽐Hu/HP H=s HP H HH Htff. @ UHAVAUATSHdL$%( LeL&L9 II) @ IEfInI]fHnflHM$$M9t[( 9*HHt>Ao$ AoD$@ID$ { HC tI|$$HCHuH3 @ 1HUdH+%( u H[A\A]A^] D UHAWAVIAUAATISHH <H='y dL<%( L}E1JH IHHLM HE M H HDžD HHLDž@ HDžX "xsH@HH0EDHEuq<H0LHHHDžP HEdH+%( uaHĨ L[A\A]A^A_]f D HLLI @ HL %I0 HH= wHc@iff. f UHAUATSHdH%( HEHcx L(MtcHILuH1Ht I9t&{,t HUdH+%( u5H[A\A]]f D L8H, 1 UHH 7 HHHH@dH4%( HuHH wHFx H H HHDHEdH+%( uH,; 1&q U@H HHdH%( HE1 HH#HUdH+%( u"f UA@HEIHHL x dH%( HELI u4HUdH+%( ueHH5x H= LFH1d @ LEdL+%( u1HH5x HHx LHL 1H kff. UHAWAVAUATSH dH%( HE1H H HHt)HUdH+%( 0 HĘ [A\A]A^A_] @ O H HcH> HOL@H 1 LgH HH)I41LyH Hhf H S @ HG< HH$ IH j IA L@H8 1LHc HH)Lc @ L@H H8 L16 h HCH c H wH x H HK HHDL@H98 L1+f D L@ L HOHDwD 1L@H LAA A AufMc HL)K4,QL@Hɺ 1L/;9L@H @ H p @ Ic HB 1H)L<Av @ Ic HrQ 1H)LAH @ Hc HX 1H)LA @ H DDDD;H AA DDL@L3&f UHSHdH %( H]HNHHHUdH+%( uH] @ UHHdH%( HEH` HtHUdH+%( u2f. h H@ tHEdH+%( u7 D UH HHdH%( HEH HHDHUdH+%( uff. UHAWAVIAUATIS1H(HUdH%( HE1K,A MA @ M9 tkM9 ubH x x) t A@ tALEHuHcIH : H HDI<H)1H E1Mm MuA tBHEdH+%( uSH([A\A]A^A_]fHuHHȷ L1h4HuHcH I<H)1Dff. UHǐ 1HHdH%( HEHH9tf D ;pHDH H9uHEdH+%( uH( UHHdH%( HE1HEdH+%( u ɾ @ {f D UHHdH%( HE1HEdH+%( uff. @ UHATISHdH<%( H}HYHt2I$8 HdI$8 1HUdH+%( uH[A\]Ã8 UHSHHH8 dL%( LEIHtL1H} H -~QH8 HEH8 1HUdH+%( u0H] HEdH+%( uH]LL @ ff. UHSHHH8 dL%( LEIHtL1H} Hw }~QH8 -HEH8 1HUdH+%( u0H] HEdH+%( uH]L @ ff. UHHdH%( HE1HEdH+%( uff. UHSHdH %( H]H>+uƃ HUdH+%( uH]If UHHdH%( HE1HEdH+%( u? ff. UHSHdH %( H]Hnuƃ HUdH+%( uH]f UHAUATSHdL$%( LeL'I $L9teIfIn @ LpHfHnL9tBIHID$flHCHA|$ A$tI|$L.HfHnI9uHEdH+%( u H[A\A]]f UHHdH%( HEH Ht^H@HcHcH;pRH;P RH0oHPHT(Ho oAHP@Hq Hp oH)QfHEdH+%( ug UHAWAVIAUATLcSHcHHdL<%( L}Dh E= Lo0AukH IcHcHIH;A H;Q HHQHD(HHEdH+%( HHDL[A\A]A^A_] L L}`AM8Hc| M; o M9 I H;X L;` H0HHHIH|(- LH IIc IF0H9 HMoHUt IWMoHUHHUt IU IHUM9 E1 f H HFH;XPL;` PLHH8A~E HMMHEI|9(HHHH@ HFH;X/PL;` %PH8HpIAHIHD(D9} IuI LHSHUdH+%( . HH[A\A]A^A_] @ H IcHcH@H;P H;H H8HpHHHt7(L 0A AGwMp I;U7 I;M - Iu IEHHHD(II LMH;P*OH;H OH1HHH1ҋD(ljE Ax LM 1A}HU@ƃ5LMH]I+] LM1LMH ʚ;HHfHnfAAfl1IA A @ H HFH;XfNL;` \NLLHA~E I}LHMMEOL (LHHHx HFH;XNL;` MH8HpIAHIHD(D9}thIuI (HWf. 1f % E1 +& f1f A fHu LMHiE ʚ;HEI+p LMfHnE1 HcUIHteHEHcULx8 @ I] H+ @ EuI LM11A}HMTLMff. UHAWLcAVLcAUATSHHdH%( HE1H HHHL;xVLL;p LLAHHpIIHL(< H HMM DMDEL;p LH0HHLmIIHL|(DEDMH DDLHOA1LaH H@L;xKL;p KL8foELpLL@(foEH@8HEHBH1HUdH+%( uvHH[A\A]A^A_]f D # D DuD}HU x2H HUDEDML;xKf 노{f. UHAWAVAUATSHDw dH%( HE1E G8` H u Љ` S8L5w L-3w H C8A>Au 11Y A} A L-8w L=aw L5+ 1L II} 輿IM H= .I} Hs1H輤II} L 1v @ % ЉG8E1HEdH+%( u'HD[A\A]A^A_] @ 1 .bf UHAVAUATISHHHdL,%( LmIOAHEw x tC;ux usM M H h vUHX t HX H1HUdH+%( H[A\A]A^]À{; y Hp uL DSHp Hz L%Ay M6+0H,y IH f D H=y X'Hy Hf D LXDH߉˖of UHSH(dH %( H]H w { u GZW { u G0 { u G+ { u G*o { u G*@ { ti{ u GZy { u ; { usG;@tmHw C H= 0Hw 11 f. G<tHw C H0 0HGw 8h { u G; { { G;J { u X { G:u ; | { u GY { uvG8tpG0tjH9 uaHw CH 0Hw Hw CH 0H]w DE| 111HUdH+%( T H] D G; HWw CH 0Hw t( H1w CH 0Hw D Eu 1a| @ Hw H C018 Hf D Hw CH 0 1 f D Hw H C01f D { $G;H]w CH! 0H w t~f D H1w C H& 0Hw }f D Hh H ƀ Dl E Hw H 0Hw DE(Hw C H) 0H]w f D Hw HR C 01 HYw CH8 0Hw vf D H)w CH$ 0Hw DEUD @ Hw CH 0Hw 'f D { Hw CH$ 0Hkw D EfHw H 0H>w 8H}H}Hh HZg:XHBw CH 0Hw p_Rf UHSHdH %( H]H.0HEdH+%( u HH]U ff. f UHHdH%( HEHHG8HEdH+%( uʼf. HHHUH=H!H?H HHdH%( HEHH HH;H HH9H HHH( H HH H HH H HH <H H H!H HUdH+%( u UHSHx LO(dH%( HE1A > IHtpH HHA@:uHUdH+%( H]ÐA HLHHDž HH1 VHH9rGHFHA HDAHFHEAHFHEHH1c D TJff. @ UHHdH%( HUHW(HHHE@HEHEHE HEHUdH+%( uq UHHdH%( HE1HEdH+%( u H0 4 @ UHHdH%( HE1HEdH+%( u H0 @ UHSHHdH4%( HuH HtHp8P(H @u"HcHHUdH+%( u0H]f D Hc<9 tP,f. g UHHHcG(H dH %( HMыW,tR t[u>HfHDu#H HHHEHUdH+%( u" 1 @ ɉD Ƹf D UHATISHHdH4%( HuH֧Ht1HHEdH+%( u9 HL[A\] HEdH+%( u H1[A\]A UHATISHHdH4%( HuHHt1HHEdH+%( u9 HL[A\]( HEdH+%( u H1[A\] UHAVIHAUATISHdL,%( LmIϦH H=^y Ht H9Jy tHHAy HtlH -y LLLAR t*L-y 1LXHCHH9rEd HEdH+%( u HD[A\A]A^] @ A? UHAWAVAUATSH(dH%( HE1w&D HIMHAE Gt1E1HEdH+%( k H(D[A\A]A^A_]f HGHuƀ~, G H T uH~ u H T HCLH L1H y fG8 \舯AǃKHtC8</ HHEiHML7 Ht\1H} H H A xHEDLHG LH 1K8`HϾ: HML Htx L sLm g ff. UHHdH%( HE1HEdH+%( u1ʹff. f UHAWAVIAUIATSH dL$%( LeMDž< = ~)=w$H HcH> LLLu>L֡H@ I0MLIH6 L1 @ HUdH+%( HĨ [A\A]A^A_] LHH 1tH<H=֙ A.u<T .IcLH H)1L"m D H LLH1G H LH1' H H LL1 HW(Hw t x @ t#x t HN LL1q @ AF;t!x tHd LL1Gfx x \ x S ~, H~ LH LLH19f H~ H ^ f G( u 1H= 诛rH LL1| _gG) ; c H 0 H fG9lGH #Uf D H) LL1O IcLH H)LA ~y LL1H> H9 LH1 LxH9 LLH1qA&f KH$ LLH1D H LL1$o H\ LLH1G H LLH1 H8 LL1 UHHdH%( HE1HtH Ht H` HuH w HUdH+%( u諯ff. UHAWAVAUATSH(dH%( HE1: u'HEdH+%( # H([A\A]A^A_] D HIIHAWH HIAD$A}\ fC|tK:@A}] tK: AD$ t ElH w E HJ H=I ' LA LMHE$HUII L9 LLIT$H 1H w IML k`01NAD$K:@Ch D I}x uqC8 H w H 111AD$ @ H w H 111HMHM1HV 11K:@- @ H aw H 111AD$ D H C`<f. HHCX AD$P<ff. UHAWAVIAUATSH(H H dH %( H]HD`aLDeE I HH HP E1DmE~{E1I91I91HHPLHIIHDDD(Dx2I IHP HHD9u9}If. EHEdH+%( uEH([A\A]A^A_]E f. UHAUATSHdL,%( LmIH HtfHG Ht?E1 HWJ Ht H_H[HuI HG II9rHEdH+%( u)H[A\A]] HEdH+%( u H[A\A]]Nff. UHSHdH %( H]H^H%HQH BHX FH 芣H ~H H }H qH8 eH YH( MHP AH` 5HH H Hǃ Hx h v HEdH+%( u-H] HEdH+%( uHp H]ff. UHSHdH%( HE1Ht'HHEdH+%( u%HH]髙 HEdH+%( uH]莩ff. UHATSHdH%( HE1H D H1HIH* H nH I$ ZH I$ 覙H I$ A$ fA$ A$ Ht蠉I$ H H Ht~I$ Hr H Ht\I$ HP H( Ht:I$( H. H8 HtI$8 H H` HtI$` H HX I$P I$X H0 I$0 H I$ H I$ H@ I$@ h A$h 蚗HP nI$P HtfHt H H I$ Hl I$t } I$l A$} Hh A$H I$h yLC E1HEdH+%( u HL[A\]ff. f UHSHdH %( H]Hޭ1t HUdH+%( uH]蔦 @ UHHdH%( HEH HUdH+%( uZf. UHAWIAVE1AUATISHxdH %( H]HA|$. HxIGHhA wtEt$/AEL- w AT$B LAL$_IG0 AE AW8 ȁ% AG8 LAp ) Ax IG ? HtA|$tuI$ t AD$hS AO9IG AG9V A|$D tIG A|$@ t IO0AO9A|$F a LytAO:@H ; A I$ u3I$ Ht&A u AT I G` LA|$, u I|$ LA|$K t A} A|$E tA A|$F L A|$G ( A|$A t Ag9AG@ I|$x tA E A|$J wAG9ڃރ AG9AL$VAT$WAt$e AEA8% A|$f AG8 A<A<@ A|$c AG; A} @AG; AE HAD$h* D HLL肑fI$ H*A OAw IGp LEI$ H" HI!G8@ AG;AG; AG; A|$H A|$I A|$X twAG; AG;A$ A|$Q tIO0I L9/ I|$ 4 A tfAg8A$ A$ ny t AO;AGlAw tAO8 A|$[ tAG8σ AG8A|$Z tAG8σAG8I IO0Hw fE1M I )EH N @)EDžp EDžx )E)EL9Z ff. @ A} AEHcH> I$ IG AG9 LL AG;AG;/6A<1 A<LA|$H @ LA|$I L D A|$B t0A|$, u(I|$ u AuA|$L ff. Lf D A<A<@lAu AG;߃ AG;A|$c UAG;`AG;Y* xol x b Lo H h Mm L9KpM x tufEL5( HuLEO= }AŋxtxCEHdw 8 } tE HULLEAD$`A|$P A tA|$O L A HEdH+%( HhHxL[A\A]A^A_] @ AuAG; AG;Mm L9%IEH8n LI}IwXMm H L9 AuAG; AG;Mm L9Z D IEMm I@ L98 AEMm pL9i @ AuAG8Mm AG8L9;f D AEMm xL9 @ MuMm L9f. A} LyhMm H L9t A} t A|$tMIEAO9 LIG Mm H L9w'fA} tI$ IEAg9 LIG P Mm H E L9, fEMA>nA~oA~ E E1E IGH z H <H5 LI~%Ig(! @ LwAG: AG:s @ L:f D L1LHx IO0Ag8f D L| L{f D Lcf D AO8I|$ I<$ I|$ A|$, I|$ L9AL$4AO9} IP D LKAIGe E1M wf D LHlw @ L L L3ID$xIGX D L L L, @ A|$M I ~I L Lw AG: AG:* LHbw IgX@Hw I H 101蠘UHAWAVAUIATSH H@HD dH%( HE1h Džl u[H Hp ֝Hip ʚ;HxIp 1HEdH+%( He؉[A\A]A^A_]HA Hw x t AE;" Hw x t A}; H@IHG H I Ah IX t IX H@HHDCdy H@HHHD"dy HHCDžH<IX Ht @(HIEH(L˵L胄H/} HHw 01Hw 8 H5w t A9wIc܃D MD)H0HHH؋<L<E1D8ED9< HlHff. IX Ah C LwHM9 L_LItLث Lȫ Ly H HH;BL;r HJHIHʋ\( Hw MX LH@ yHA1AHw HHQ 0AT1.A\XLH@MX 2H* AH(M1AI H0H;zL;r HJH:AIHD(< H D H H<w D0Hw ۉDE 11oLW H@8HXzA A A 3 A) HXa DXA9K D9B I LL9 DX M9 X LPE1IAf D9~zHPH L;H^Hx INL H9w L HpMHIt0(HH9"DH0HL@ILHHET0(9ID9XpLPLDM9t ML9"8HX蔨 HMw XH8 101<f D D9<3H0H9"HH0H @w L=iw L53w 1L IH;ŌH H=w H;1H(H١qIH;L 1f. 1f ۡHAًHAHLw H 0AT1AZA[Y @ 1t A /8HwAh HCI DHE Le@ 1LLAw @ L11; AƇx AI H0H;xL;p HPH8IHDd(E1 Ip H0H;x L;p HPH8IHT(L,H\ 1LD@ƃe; MI L@I L I$ R Ai HDLL M+ LXL MH8XADLLXMLP8Z HxLIMHA|9(x `I L;h L;` HPL(ILD(sAx+<XI LcMcL;hsL;` r% LXPLArHNw I MHt 01IH&w 8 Hw DH 0Hw D E 116A ' H w Džl x x ID9<y @ Ip BL" މ舰Ip H ZfH=xZy HaZy H.f D L5QZy M;H<Zy IHf D 1H=s 1~AFLnL`_ 1ھ$@DwB8HXMHA 1IH[w 01LX f 1IE1 L8MEH D A LHX芥HXDž8 IҺt @ I L1҃LDTuLH@MX ͛HADH(M&fI҉ @ MIUf. UHAUATIHSHHdL,%( LmIqAHEdH+%( uHLHL[1A\A]]5Њ UHHdH%( HE1HEdH+%( u H1k薊f D UHSH(dH %( H]Ht.HEdH+%( uRHH]DB1f. HHuHuAHEdH+%( uHH]11m UfvHAWAVAUIATISHHHHHW(DFdH%( HE1D H{H Hǃ` HH)h HHCCXID$ HCC HC0Ff H! HC` ǃ > tSAD$:u+1HUdH+%( A HH[A\A]A^A_] A$ I|$(HL蟚 D A$ NHH9 HN t HHHt/HfHnEtHȉH fnfnfbfCHt HHHCt HHHC@t HHHC t HHHC(tHEHHEHCXt HHHC0EOT= HAI9 It$0H9IIH8 AA M @tHAI9a HIH0 H H9C HHHHHI9$ HI9 H@ tKHAI9 H H HH= HI9 HI9 ff. t{HAI9 H1Er HΉs\HLUDMHUHM2{C\HMHUDMLUI9e HqH I9T H ff. f ~ LqM9! HH H It$`LUDMHHUHuqH I9 LULI9 HuHUL DMH D t;HAI9 H1L)f Hz Hǃ Hf. @ t4LiDMM9LUS HHHUTwLUHULDMƀtHAI9" H HK`H tHAI9 H HK@HHǃ tqLiM9 HH H1 Md$pLUDMLHU-H I9 LULI9 HUL L DMHCh t HHHChHǃ tHHH HCp @ t HHHCpHCx t HHHCx LaM9 L)M9 K,I9 E@ LP LX D HAHEI9 HH H H9 L4@J4 HuAD$Z@ HHHuEtZHtUE1ff. fHyLUDMHUHMHMA~HUDMLUIHAH HH;8rHEI9 HMDMHUHLUI9HM LLUHMHHUDMHEqI$ H`L0L9u Sf. M6M;$ 8LLUDMHUHM'H9EHMHUDMLUuAFZtHAI9r0H H H HI9rHI9f. f D HFHNHC {lf D MuS@tHAI9rHIH0 HHI9rH8H@ HHI9rH@HH k HAI9kLYL( @tHAI9MHIH0 Mt s\ƃ HML^I9H<0I9HOH I9HH H9a=Ny H%w H=g HMy LDL-u UHHdH%( HE1H9 HUdH+%( u腀 D UHHdH%( HE1HEdH+%( u H-H UHHdH%( HE1H HEdH+%( u U1HHdH%( HUH HH9u 0ff. f H H9tH; uH H9uHEdH+%( uɉff. UHHdH%( HE1HEdH+%( u1Mff. f UHATSHHdL$%( LeIL9t<u HEdH+%( u1H[A\] HHǃ A$ ~f. UHAVIAUIATISH HHLPLXt&)`)p)U)])e)m)u)}dH%( H(1A} H LxHEL LHHH0Dž Dž0 H /H(dH+%( u5H [A\A]A^] H L1rxAE s} UHHdL%( LEIHUdH+%( uHHɴ HH1X} UHAWAVIAUIATSHdH%( HE1~ E H9 t'HUdH+%( Y H[A\A]A^A_] D E1䃿 ~.H HW LHd HHD1qwALL=k ?jHG LH1FwI] AHucf. A * L %AD$< L9 uHiL LH1vHAHtI9 u @ HL= iL LH1v{ A ; t3AE9ME HuLHc H HEHc 1AĀ{ 3A} I0 HX(H HKLmHc D HKLLL1HAHu @ Hh L1uAf. HMIuLH^ZAĀ{ R HuHc L1 Aa HuHc L1AAzff. UIHAWIAVAUATSH hdH<%( H}Lωlq H A I MoIIG Mo H ADLA ALpXÃL@\ÃHx`ÃPà dDAA UAMD<WE1VH1ff. MR I]M}HtC+t U hHx1L o H AsAEu&V t HxHea 1sAE1MtA4 Me uMgM+'DXE D\E `* H C+ d HxH` 1 sAƋl HAD"W* HpHLh H@MmPHpHLn HFH9HEdH+%( HĨ D[A\A]A^A_] D A H x MHEdH+%( K HĨ H 1[A\A]A^A_]Kr Hx<LL谅AƋdw HV C+lHx1 H qAHAD"WH@Hs-HHpE1HLh H@f. LmLHxH 1 jqLeAMt'AW( AO(9t BJvDPL}E LxHLH߹ FoALhf D ME L1H^ Hx pAO @ l D HxH]^ LL/XAh HxHLH蘌A]HxH^ LLWA) E1kH _uff. @ UHAWAVAUIATISLHdL4%( LuLuMt8HEdH+%( P HMȉM[A\A]A^A_]f. AЉL " LH 1~oAu> ux uSHEdH+%( HD[A\A]A^A_]f D I $H\ L1 oAf Iu(I}LH\ VA @ IU(I}L XAhHW L 1nI}Aǃt M LlA!f D LL譊As UHAWIAVIAUATSHH H(dH<%( H}ȋ>脶D IH H H H PLL^ 1Lm_AXH(LH5e LADK$E LKLLLLHuF I O H@ JcH>H[ H L PL] 1Y^H(LH5 LAD$LKAM HSH HS H DK(Dȃ Aa A A A5 A | A@ E DK)DȃL A A A Af A A@ DK(A 6 DK*Ax A A AL A A@ E! DK+Dȃc A A A6 A} A A@F E DK,Dȃ A A( A At A DK0E DK4E LK8M3 LK@M HSHH9 LKPM DKXE LcK\ER LK`M DKhE DKlfEi DKpE LKxM HEdH+%( HeD[A\A]A^A_]f. LL? 1 LZ @ AwH; JcH>f L1L=? H(LLH5 A$ f D L1L> 8H(LLH5N] AAf L1L> H(LLH5\ AA L1Lm> H(LLH5\ AAX L1L-> pH(LLH5W\ AA L1L. 0H(LLH5\ AA L1L o H(LLH5TZ AAo L1Lm= H(LLH5t[ AA" L1Ln pH(LLH5#[ AA1H0* HHX L0Dž0 H8 H;Z HHH4Z HXH)Z HhH Z HxHZ HHZ HHZ HH Z HHZ HH HHY HHY HHd HHY HHY Dž@ DžP Dž` Džp Dž Dž@ Dž Dž Dž Dž Dž Dž Dž Dž @ Dž H(H:Y H8H6Y HHH1Y HXH-Y Dž0 Dž@ DžP Dž` HhD$IHLLM D Ic$Lt6MD$H߾ H_ H S HDH:: 1h1HHII|$ uLD$H5X LHH(LAA( L1L H(LLH5W AA L1LN PH(LLH5:W AA L1L9 H(LLH5 AAA L1L9 H(LLH5 AAALX9 L1A H(LLH5. AAf AL9 L1A 8H(LLH5V ADK,A@ @ AL8 L1A H(LLH5U ADK,A @ ALh8 L1A H(LLH5[U ADK,A @ AL8 L1A IH(LLH5U ADK,A3 D IL7 L1A H(LLH5T ADK,A D ALx7 L1A H(LLH5ET ADK+AEsAL(7 L1A XH(LLH5S AA,f AL6 L1A H(LLH5S ADK+A @ L1L}6 LH(LH5 AHSAH+1H02 HH: L0Dž0 H8 Hϔ HHH*f HXH HhH۔ HxH HH HH HH HH HH HH.Q HH-Q HH)Q HH&Q HH#Q Dž@ DžP Dž` Džp Dž Dž@ Dž Dž Dž Dž Dž Dž Dž Dž Dž H(HP H8HP HHH}P HXH_ HhHE HxH]P HH^P HH_P Dž0 Dž@ @ DžP Dž` Džp Dž @ Dž Dž HD$IHLLMff. Ic$Lt6MD$H߾ HX H 3 HDH3 1H1HHII|$ uHLH5 LD$H(LAHS AH(1 H8HDž4 HDž L0HH Dž0 H8H HHH HXHC HhH Dž@ DžP Dž` Džp HxD$IHLLMIc$Lt6MD$H߾ HJW H HDH1 11HHII|$ uHLH5:N LD$H(LADK(ADȃIL1 L1A H(LLH5D ADK(AAAL1 L1A H(LLH5Q ADK(AAYAL=1 L1A mH(LLH5 ADK(AAAL0 L1A H(LLH5t ADK(AAAL0 L1A H(LLH5 ADK(AA ALJ0 L1A zH(LLH5 ADK(AA@=AL/ L1A )H(LLH5 ADK(AEAL/ L1A H(LLH5K ADK)ADȃILW/ L1A H(LLH5 ADK)AAnAL/ L1A 7H(LLH5u ADK)AA(AL. L1A H(LLH5R ADK)AAALe. L1A H(LLH5tJ ADK)AAAL. L1A DH(LLH50J ADK)AA SAL- L1A H(LLH5b ADK)AA@ ALr- L1A H(LLH5K ADK(AA AL - L1A OH(LLH5 ADK*AAAL, L1A H(LLH5H ADK*AABAL~, L1A H(LLH5 ADK*AAAL-, L1A ]H(LLH5bH ADK*AAAL+ L1A H(LLH5 H ADK*AA mAL+ L1A H(LLH5G ADK*AA@&AL:+ L1A jH(LLH5G ADK*AEAL* L1A H(LLH5jG ADK+ADȃIL* L1A H(LLH5 G ADK+AAWALH* L1A xH(LLH5F ADK+AAAL) L1A 'H(LLH5F ADK+AAAL) L1A H(LLH5QF ADK+AAALU) L1A H(LLH5F ADK+A7 AAI Hޅ Hc1H>fI Hۅ JcH> D H[A k @ H^A [ @ HA K @ HA ; @ HCA + @ HAA @ H L1L~ LL詍LHI H LPL|C 11XZLGyHB ff. LH H H5B HFLH #H)H HLB LP1V R H HA nH[B bH7B VHB JHA >HA 2H@ fH ZH? NH+@ BH8@ 6H/ *H<@ Hǎ H HK@ H]@ H@ H^@ H H+ HN@ H`@ Hr@ H Hw@ H@ vf D L1L H5 & @ H5A Uf. UHHdH%( HUHHt'G t H9t:fHUdH+%( uF HW1HtH9u t1f D G!G G!G Uf D UHAUATISHHHwdL,%( LmIHtLhHHtyC HsHtLKHCHt 1HUdH+%( uWH[A\A]]LCH !L HL L7OL: H=S ~LCH < ET D UHHHdH%( HU1Hu* ff. ff. fH@HH9s\HHtugH 0 fuHuHuHuHH HH9HGHUdH+%( uf D 1rSf UHHdH%( HEHH| 1E1 @ I@HI9sdLL#tEulI 0 fEuIEuIAuIAuIAI LH9HGHUdH+%( uf D 1Rf. UHHdH%( HEHH 1$ff. ff. H@HH9s]HHtufH 0 fuHuHuHuHH HH9HGHUdH+%( u D 1Qf UIHHdH<%( H}HH9sdHHHHHH4 I#uVHIL0H.ff. ff. D HHp@HHu HH9rHEdH+%( urHHu\H 0 fuHuHuHuHH HH9HGf. 1Pf UHHdL%( LEIH9sYHIHHHH#HH!uPHHH&ff. f D IHy@H#u2HHL9rHEdH+%( | LHH u\H 0 fuHuHuHuHH HI9LGf. 1Of UIHHdH<%( H}HH9seHHHHHIL HH!uQHVKLH)ff. f. HHr@HHu/HH9rHEdH+%( uyHHHff. uTH 0 fuHuHuHuHH HH9HG @ 1Nf. f. f. f. f. UHAWEAVAUIATSHXUMH}dL4%( LuEVYLHEJYpEHEHcH uHH]趛HHE誛HI蟛HUuDUHMHÅ ? fAnA Lfp fofoxY Hfs fAnLfp ff. ff. ff. fofofHffs ffpfpfbHH9ủt0DHcL A49~DCt9DCt qDE1ɉ E(IADL9 IHELeIHÉ E~HuDRE1 HEEɉMAB<11f AT4DD9O9OщTHPI9tSHAT M@8ADA LHtEtHuB:TuA:|uHuUT9~T D MH}IADI9t5H}ILeI܉H=LLeH]Hff. @ HELDl;H;H};HEdH+%( uHXD[A\A]A^A_]1TqK U HAUATLSHLH H?dL$%( LeIsoHLKHƄ Hrw H|9 0AU1MXZHEdH+%( u He[A\A]]Jf. UHHdH%( HE1HEdH+%( uWJff. UHHdH%( HE1HEdH+%( u1]Jff. f UHHdH%( HE1HEdH+%( u Jff. @ UHHdH%( HE1HEdH+%( uIff. @ UHHdH%( HE1HEdH+%( uIff. @ UHATSHdL$%( LeIH e9I$ (*A$ I$ ~S1fH< L HI$ H<kI$ A$ H HI$ 9Ht I$ kI$ kI$ |kI$ t$L袄I$ H2kIDŽ$ HEdH+%( u(HI|$`[A\]Z D H9$nZHf. UHAWAVAUIATISHHdH %( H]ȉT EL$ E How 8+ IcD$At$I IE8!p| ED$EtA IU It$I}`9Aƅ! AD$A HEdH+%( HHD[A\A]A^A_] AZ HcЃ?I pIHcI H AD$ IcEI HHHH Hnw 8ff. fI H5G Hcؾ H耍I H HcI H HFI H cA H 1Du1MHUILe:fI E L)HHIƨ BA9 LL, ȁE1E11M Hƹ" {MI$M I} HEEo@ kv/]I LHHEVDI& LcAE@DmpIHcMHIH L H}E1HHMELI L L]薠L]Hu}L4LȀE1E1" Hƺ 1zI H(Hi H[lw 01語1I A D H1lw HMM1MHN A0N!1cL;4f D Du . AD$ A}%E;IHHWLe]DAfLTAL%9Eu I IcĿ DHHH <ƃA9uLe]{HGkw IE H~ 01肝ؠH} H kw 01Z谠HY} Hjw 012舠Hi} Hjw 01 eBHjw H~ 101BH} H|jw 01Ɯ!H} H} ff. @ UHAWIAVIAUATSH(dL,%( LmIQLHEIHEH3x tiAą HEIW(MG IcwHIHLM)HH!H!NI9t6HLLHcH)IMG AՅxlIW(IO IcGIH!I)IW LHLLAՅx?HELIG躇HEdH+%( u3H(D[A\A]A^A_]f t A A SA UHAUATISHH_ dL,%( LmIC?H^pIHcIE Ht8HS?I4$HHH %1HUdH+%( uH[A\A]]ø@f. f. UHHdH%( HE1~!F@H @ HȉGH9uHEdH+%( uJ@f. UHHdH%( HE1~4F@Hff. f HHHHGH9uHEdH+%( u?f. f. UAHAWAVIAUATSHH8E LmH}LEL}LMEdL$%( LeLe(Mj I}0M覩LIADU EU 3LjIH LL QI M1 AE I} A AE Mh A EAy IHEM HtH I HEHtH{ I` Mt9II9t1I IwfInI flHxI HHqAH]Ht HCfHnLsfHnflAL0HEdH+%( H8L[A\A]A^A_] MLM2DUIEL Idžh 1fA EAy IvHU1LL DU*Iv8HULL} *Iv@HULLo s*I HULL^ T*DU L5=f D UHAWAVAUATSHdH %( H]H H9t}IIL%j ff. fC$wPIc( L>f D ?_H H@@ S1H{ P IVIFL0HPH@HI9u1HUdH+%( H[A\A]A^A_]f ^H H@@ D ^HEIHk H@@ C1H{AG IFM~M7IGL8 IGH" AGQf D O^H H@@ f/^H H@@ S1H{ P IVIFL0HPH@]H H@@ S1P IVIFHPL0HHSHP]Hr H@@ S1P IVIFHPL0HHSPmfo]H2 H@@ +fO]H H@@ f/]H H@@ ;f]HEIH H@@ [ \H H@@ f. \HEIHtH@@ \Ht^H@@ f D w\Ht>H@@ f D W\Ht H@@ gH}\\ D +9UHAWAVAUATSH dL<%( L}IHK HIIo/D LfA9DGbDAHIcԃ L HHcLI4ADIG6 A)fE9 H! fƄ L%bw 1H 7' H(' I<$Q3 HEdH+%( $ H [A\A]A^A_] @ L LLH?AID9y5 HV @ HEdH+%( Hbw MH ,t Hv& H8H 1[A\A]A^A_]2 D L%aw H K& H<& 1 ! I<$^2I<$1KML H*& :2MI<$LH& 1 2M7ff. f UHHdH%( HEH& t"9H tH H HDHUdH+%( u! H H% HD6 @ UHAWAVIAUIATSHH(dL$%( LeMM }I|$0輠LIDM HDaHHk L LsI<$H AD$ AD$ Lh ƃy IL MtLH MtLH` HEdH+%( H(H[A\A]A^A_]f D HFaHH Hǃ 1踟ƃy H 1f Hǃh WHsL 1LLDMT"Hs8LLL' 9"Hs@LLL " LLH L "DM~L @ H1f-4ff. UHAWAVAUATSHHXH}uHUdH%( HE1?HE HDHEH\w L`@ Ml$ff. Mu Mt-L_?I9~H}HcLIADIM9uʅ HEHEI@Hu3 @ HEHcHuHDHEH9rIHEHMHeu$1HUdH+%( HX[A\A]A^A_]HEHMH H ˋEE EH]w H@HEIfMt$ff. M>Mt-Lp>I9~H}HcLZADIM9u˅ EEI@uH,aw E1Lx@Mwff. M&Mt1L >9} H}HcLHEHMDIM9uDž[ AEI@A uE1E1HELp M&Mt5L=9} H}HcLHEyHMDHEII9uÅ AHE@AuEEAA IcHE4u}踘DuMHcHEAD HDMHMHEH9suH_w E Lh@M}ff. M7Mt-L<I9~H}HcL誉ADIM9u˅xEI@E uHcEHEuHEHcHuHDHEH9}Dח EEAAA E IcHE DuEAA IcHE0 UHHH@dH%( HE1Ht$H6tHUdH+%( u f D 10ff. @ UHHdH%( HE1Zx HEdH+%( u80 U HAWE1AVIHHAUIATASH dH%( HE1HE HDžD HDž@ HDžH uH= $IH@H賘AvHG[HH AFLL 跙ƃy H 1f Hǃh Hǃ Mt IEfInI]fHnflHDh AAv(1HUdH+%( uNHĘ [A\A]A^A_] D HP H=L HP L`'. @ UHATSHdH %( H]H H9t<IHH3H )QL HEdH+%( uBH[A\] Rx uHWXw ) H=j HF$x . D UHAUATSHH dL,%( LmIH9 I1$ff. ff. f D HL9tNH uLugH HtoHI9t-H tIHI9tH t7H L9utF1HUdH+%( u?H[A\A]]f. LH Hu D L - UfHAWAVLpAUILATIHhSHxdL4%( LuI)E)pE )E)E)EFÅu}HhM L?dHhLIMPHhL3HhLHh!9u#HEHH9tIM H@LjIU HHAH}NHEdH+%( u-Hx[A\A]A^A_]ÐLHhLO+ UHHdH%( HE + HUdH+%( u+ D UHAVIAUIATSHH dH %( H]HH9 D H H9t4 A9tAD)HUdH+%( M H[A\A]A^] @ A9uH( I( ouHEdH+%( HHL[A\A]A^]闗 L? Hr^ H E&H9 A9"uf D At H^tAD9: D9( @ H E H9t A9D)ff. @ UfHAWAVAULhATSHLH H(GD0dL$%( LeLpEEEEEEHMfInLE flLEEHUE)pJCLp4uiHhH`HhLHLHhH߉4A@0HhH!Hh5LpEu M9 DžhM9 Dž\ DžX L@XM/MH LDLW I( HW \XL9Pq A M6M9 \L谖LHP衖LHqHH L/B uHVaHpIHJ L : 0LpM9 LH @ M?M9D L9tLH9uLzpIH L uMm f KzHH5LH HHNw 018 HEdH+%( < 4Hĸ [A\A]A^A_] D XA h{A mLZ]A M6hM9Pff. L@HLL7)LpM9n E111L8ƅ@ MMAƅ\ H4 D LL M6H8I9 D\LDHLE1nhI( HPtLHHYHHAE9 E Adž @AGMM HMDI9t\ 2 E) I$( li D\IL9PM6H8I9 HpIE1H9t) H舓1H9H AL9uD9X @t0 t } H(L*U4H(H@ƀ D 1wIH 1iwIHM?M9LH @ MHKw H` 101?~QHsLL&LpDžX M9 ƅ@ E1x tDž4#HMw $ H=,` H輌x UfHnflHHdH%( HE1HEdH+%( uS# UHAUATSHdH %( H]H L#H9t;I @ H{EH{ EHHCHLHBHM$$I9uHEdH+%( u H[A\A]]"ff. f UHAUATISH]HH(dL,%( LmIpyHLE1j 1A HLaHAHEdH+%( uHeD[A\A]]D" @ UHAVIAUATSHdL$%( LeIH HH ( ADHtKHfHnDhLpfHnL` flHB HHEdH+%( H[A\A]A^] @ HiIw MLt LMEH^ 101{LvHEdH+%( u9HL[A\A]A^]S HaKw 2 H=^ HP)!f UHAVAUATSH H $ H H $ HdH%( HE1HtlHL5 EHt L5͙ H LELIHL ]LuLIjLDHH1HEdH+%( uH [A\A]A^]U D UHAWAVMAUIATISHH8WO8LErdL<%( L}L}wLLpHH= MtYLeLHEfInLfl)EHU HEL9t$H HuH HxH HHqHCfHnHSfHnflH1HUdH+%( u:H8[A\A]A^A_] EGH}LLEE뾸' UHAWAVAUIATISHXHEH}HHuLELMHEdH4%( HuH5 <HT LTTHEH H>HH E L= ~ D H>H x.LpuA~ tހx.uA~.uA~ tf. LLUbtH5* LBbtLLqtHuHuLLMLLEH}Y^ u?H߃EI>HaE1҅u!HEH}LL D@H}UTH:UHEdH+%( ~ He؉[A\A]A^A_] HEdH+%( u[HELMLLLEHuHEH}He[A\A]A^A_]HEXzH}LL0Ao H} THEXtzH}LL0Aff. UIAEHAWAVAUATISHHH}HMdH%( HU1Eu I;I9 AAA߃AAA@@uƃE@uEEUHQEw Eu2E@uE EE, Leff. @ E7 } 5 U1 E8 } E E1MA @Dl AW8 D %p ЉG8Dʀ % ЉG8EtƇw } tO8} t LJp } H9 } tƇ{ E Ƈ| H?I91HUdH+%( HH[A\A]A^A_]fE UD1E E "ME1@Dl AG8 A %Ap A DG8EtƇw } tO8} t LJp } [ } t H; c } tƇ{ E Ƈ| H?I9EuB } P E' U1 MA E1f. DG:W8Dl D։@ADɃADMAA DEA EɄ } }} EuDD1Exff. f} E 1A A Tf. H?I9 H9 O8} O8 @ 1} U uE E1E ff. MDEE UDо E& } E 1f D E u1ɸ E } u=} E } 1 f "Uvf} tjE } w 11E1+ E 11f D } 1E } N fEum} 1E1 EuM} 1E1A {1} 1g D 11} z1M 1M1A E14f. W8O:Dl @DDEAA A E } = E UD1EtVE "ME1fH?L94I } H9 O8 } 9E A 1A *f. E E1ɾ } } E 11ME1A E "UE> } 11E} E1f D } EA DD1O8} D } & EH11} fUDָ R1Ehe} tJ1Ҿ EME1A 1E} 111c1E111yf. LeH} HQ H1=[~HEAt$1HUHxQ% EL1} A E1 D E$1} f D "U1f D "U13f D 11} E M11E 1DEE1M E1A D 11*U!^U! H=5P At$1HHEHx1$1z UHH HMdH%( HE1HEdH+%( u&EMA HH MHH W UHH HMdH%( HE1HEdH+%( u#EME1HH MHH /f. UHAVAUATSHdH %( H]H H9tPHS IIHs{L HI9t/L5;w I6 cXHS HsL{HI9uHEdH+%( u H[A\A]A^]W UHAUATSHdH %( H]H H9tBII fHI9tH{L<#Ht HUdH+%( uH[A\A]]1ff. @ UHAUATLeSH(H_LdL,%( LmIgHHHSLA E1H8j LkvZYÅu+LHEdH+%( uAHe[A\A]] LL + HI:w H=- H=yf D UHAUATSH8dL$%( LeLgM,$I} tSnÅu(HEdH+%( H8[A\A]] I$H84I$H UHuH}H}HuIE I$UH8 uHx9w # H=, Hdxg:f. UHAWAVAUATSHdH%( HEHGL(AU I]E H 1{L}IL5]r uW C9G| OHHuEąt_LH ax0H[L9ti u`1{E uLH ?yHz8w ( H=YL Hiw fLLH56 1<x1HUdH+%( u8H[A\A]A^A_]E H8w B H=K H w f UHAUATSHXdH%( HEHGL(AE~bI]HtYLeM @ k}@ LL A@ 1 訅LH >xmH[L9t` uW{tHR7w ; H=aK HAvff. HUdH+%( u7HX[A\A]]f D 1H6w ( H=J Hu D UHHdH%( HE1G$HUdH+%( u @ UfHAWIAVEAUATMSHhH}HMdH4%( HuHuHE )E)E)EH E1MtEl$E1HtDf8 YH L}foE]HM@H]DmDefoEDuHU@ fHnflHP0HXH 1HUdH+%( uLHh[A\A]A^A_]fH= w Hv H<HxKHxI6P UfHAWAVIAUAATS1HXH}dL$%( LeIHE )E)EMtAXE1MtEy8 XHtgLufoE]HU@H]E DmD}foEHP0@ fHnflL`H 1HUdH+%( uHX[A\A]A^A_]øt @ UHAVAUIATASHH=d HdL4%( LuMƃw HOv H<HHEdH+%( u HMMDH1[A\A]A^] UHAUATISHHoHF0dH %( H]HH~)EoFHE)EoF E )EHtxHEH Dk H[E HRHH 8 WH foEHU@foEHP0@ fHnfl@1 Au+HXI$1HUdH+%( uxHH[A\A]] Hf 8 VHt5foEHU@foEHP0@ fHnfl@1 H}S+yff. f UHSHG dH %( H]Hu,H{ +HEdH+%( u HH]7 H{* UfHnflHHdH%( HE1HEdH+%( u UHAUATSHdL,%( LmIH?H I9t. @ HGfHnIflHCHQHHM9uHEdH+%( u H[A\A]]g UHSHdH%( HE1Ht'H74HEdH+%( u%HH] HEdH+%( uH]ff. UHAWAVAUATSHdH%( HE1H L?IL9 HL-Yh L5 <A2 IW LH68xbM?M9 , H.xEAG tuIWHto1H5\ H7xIW1LH7y D HUdH+%( uUH[A\A]A^A_]fIOLH17df. AG$wHv Hx 1 UHAWAVAULATS1Hh HpD5x dH%( HE1ƅ Eu" 8 LLE1 ?HHt[~ H HsHQv L$MtA<$<tLILI>IDH=7 wEu, fCD= HpHH 1M H K HHUdH+%( Hh [A\A]A^A_] H v A L *f. 8 LLE1 >HL9XL#MtA<$<tLYLHxJHxHDH=7 Eu, fAL 1L H K 1 f D UHAUATSHHF$dL$%( LeIԃt H 0 HcH>␋N =zx MtCH|v H}о H 1HA Jx HU1ɾLf. HUdH+%( A H[A\A]]À=x tw~ H Hx1 @ ~ tH=- M" 렃~ A @ DF Et MwH= D^ EuHFHG81U~ uHV:n} HwHH1x C$@H= 1ɾLHf. V e~ 9 = x 1 Dn E3HFHG1 @ ~ H~vH=: {s,1LHff D v {w1M DN EHFH 1&DV EHFHG@1 @ 1 H=% IŋC$w H v H<s(LLHVzoyz j H=^ H=' f. UHAWAVL0AUfInATflSH H(L}HHHʹ H dH%( HE1HE HDžD )0H@LHEt M$ H(M/H@L`M9u IMm M9t?LLH tHEdH+%( He؉[A\A]A^A_] @ LL} II9 H @ HI9 z$uLB H I9txx$uLHH(j H@j H AVHOH LHۃ:)5 D I M LHME1E1듐E1 E1x UHAWAVAUATASHH8HuHMdL4%( LuMEtp0ADŽtdE E1< LHu&HEEDLAVLMHHuZYuLD}L QIHu} t 1. D DAHHE1AVHuHDLMA^_HUdH+%( uHe[A\A]A^A_]ff. UHAWAVMAUIATSH@HH H HHH0fHndH%( HE1flH( )0HHxH <w <x <r Džt J w x r Rt w x rucu_tM LEDž@ HDžP M M>MeM9u pM?M9thLLHtHUdH+%( He[A\A]A^A_] Džt MuA jf. H(LѾP II9u_ff. @ H I9tHx$uL@j H IuE1j H(j ǻH H 12 E1 Džt J wURtgfDžt J Rt# MGA 3 rt D ZtM>MtpUHAVAUIATSHHF$dL$%( LeIԃtC t`t[HEdH+%( S HL[A\A]A^]Jf. ? =IH H3u1C$ C21HUdH+%( H[A\A]A^] @ HsLd6uAE HEdH+%( AvH{HIU[A\A]A^]8G ?i<IHtBHsH6\HCAE IE8+JAFH I E9AM H}1H7 4@xs(HU1LO AM H}f D UHAWAVAUIATL@SHH8 HHOHDdH%( HEHHƅ fHnHH w fl8) 1 LHIE(HtLLAE@H$ H; LLtL3H L9P LMIH3 H HHL8HHHM$$M9 LHhtHUdH+%( He[A\A]A^A_] 1LA} IU tHt H; H5 L1(LHif/ L| H-!w HP H H81L Z Hj E1E1DH LHAWj AUH H 1 LHL5m L9 L HL9tu{$uHsL3H{ L HCS 1 HCHxnH{IH LcC2 HC HL9uHHLLpL9u 3 HL9t(LHLJtL" @ HHx0 s HO w 8~ tEHHHPL9t.If HL9tLHLt{HLa I}( HL9 1LIMIH MDHL9t1C$uHsLOuHsLHI L9u LMLHtN( H H@HH@ H@ H0HPHHXf HHx0 F HL9h HfHL9 z$uLJ H L9D x$uL@HHj LQ HpAUH HH H tƀ} H H H9u H H9 x u@v HLHx0 : 1 HCC2HC HCHC f. H 1HOHL$bH w IM H1 L0 H81|HU1E1ff. E1 1/f E1 k HP _H 3HP H u t 1LHLLH +>e8f D HHLLL/H D L f D H5V L1?#n D UHAWAVH0AUfHnATflSHH HHHdL$%( LeMH) M I$I9 H HI9 z$uHRHfH I9T x$uH@HHDE1E1HDEHH ff. L mIH fo LH)0uHL- E~ EtH HHHHH H)H1HE HDž@ AvH= M j LH@ LHj HAVH H HELlIHE 1, L_LLHHDHUdH+%( He[A\A]A^A_] D M,$HKH@M9tSDIHLI HI9t LHL t DHHL花Q11 @ HDž 11HDž 11Nff. UHAWAVIAUATISH]HHhHuHxLEdH%( HE1H tMt_M>M9tWLm HEHUHEHHPHM?M9t2LL^tHUdH+%( ) He[A\A]A^A_]ÐH}gHEHH HLM 1j H}A 7\ZYU HEHU HEHHPH:fHnIflH) E E1 ff. LiIH LLQuHuL)tLu\HLLDLuLu1LLH[HTw MHX LMHM 01FLOLEhIH`ff. IT$0HtA HLLbtNHEt+HxL(1Kf D H}HE1L fLe1L"LHZHxw LML HMHp 01ELNH|hrf UHAWAVIAUIATISHH(LEdH<%( H}ȿ 8I$H fHnHS0Hfl HK E1LH= E E1ff. LpgIHt`LH5uLL(tLZZI4$LLDHuCILEgIHu Et)1HUdH+%( H([A\A]A^A_] D L LELLLH3t1H}L H( E1x^L}H= H{LHHEpKL bf LhHHI4$HE #f. UHAWAVIAUATMSLH HEH(H H8H0dH%( HE1M M9M9 L@%f LLL9u`M?L9teAW$vԍBvՉ8Mt<H=' 8H= Hà Aw(HLH! H5 LH0 IH ff. @ LH x.LxuA tހx.uA.uA tf. H5}G L,tH59c L+tH53c L+tLLL;tH0LIH8MH H(wZY= f 1L8p8HEdH+%( He؉[A\A]A^A_]f D HEdH+%( H0IMLH8H HEH(He[A\A]A^A_]8MLH=% 8HHv H<H0X-DH8LL0Av" UHAWAVAUATSH HhHpdH<%( H}H= qb HH1aHHDž Alj| E H1lAHcL< " A~ u4HI9tkHH<HDž uր.LwtA>.uA~.tx|1 L#yoHH<HkI9uf D HT|HEdH+%( He[A\A]A^A_] A~ <xL w 1LE1䋽|HxIDxLcJ L LHIHPLDxLX @ Ay u-HL97 HH<u݀.LOtA9.uAy.uAy t L1L> L`i\x11LL`A E1 LLH`LMAL@1f D HxH xL0 KL E1LlHHH9uк HDx H~HHHxH yIH`DHH<HZL9DxLXHPDH'fH w HR" 101'=fDMIH`rDL)H 1L@L L AQLHZM& LL & 1ZL<$E1E1H j L1j Hh1PHpj PHH0H<9f UHAWAVAUATSHH H1HdH4%( Hu1dH I>HH LhM Hff. I}1HHtjLpHXLL9tQHfMN Au LAv 1L YLLyM6XZI9uHsL6IHoHHE1I\$HuVn f D HHD E11j E1j j R1j HHH0H96HH H{@ E1LHDž Ht LhMtL{LL$tWH5IH Lp@ LH IwH{H8$H@uzL{L TIHt;HKIH1MH6 "'y HDž LMHHH@HHK @ Lsf. HEdH+%( HeL[A\A]A^A_]' L{LLa#3yHEdH+%( ujHw H 0He1[A\A]A^A_]+9<HUdH+%( u,Hw H 0He1[A\A]A^A_]8f D U HAUE1ATHXSH dH%( HE1HE HDžT H1PHXxBHtFHP1HA IHt 1HHx;A LEH-HEdH+%( uKHĘ D[A\A]] D AL$8 1HLyAL$:H1LAA ff. UHAWAVAUATSH HHdL4%( LuE1f. LX0IHt]A~ uE1A~tff. @ E1L DDCuOAAuAAuL/IHuHEdH+%( He1[A\A]A^A_] H1HDDA@ L-AvHL_* H tvHMH@1AU L H~TIH H$ j LE1Lj HH5X PHj PH0C 3 UHAWAVL5O AUL-A ATISH(HudH %( H]H |v L{0HHKHH}j E11Lj j AVLCj AT$H0L9uHEdH+%( uHe[A\A]A^A_]G UHAWIAVAUATISH1H PDXdH4%( Hu1lH XPIE1 HHLAL@MIR @ HH` d PL( d 1HXRHXLXZIHM9t9H; tLDtHCL 8 uLLIHfM9uHHL@M}M DPHzv LPJL5 HXC D H IOE1j L@j j Xj 11LSLH02/IHt:MoLLHuHE1E1Lj j j Xj f LPHEdH+%( uSHeL[A\A]A^A_] @ HEdH+%( u*H w H 0He1[A\A]A^A_]'3f U1A HATSHHH w dL$%( LeIʸH w HA L譸LHbLHLH MHE1E1H j 11j H Lj Pj SLHH0HE1E1H j 11j H Lj Pj SLHH0)LH@HEdH+%( uHeLH[A\]f D UHSH H $ H L dH%( HE1HHIVH߾ O1H1RZYx!1HUdH+%( uH] Lff. UHAUATSHdH %( H]HJHx$H ILu,@ff. ff. HHt<:uH/Hu/id LE18 HHt H$AHLHEdH+%( uHD[A\A]]E1^f. f. f. UHHdH%( HE1HEdH+%( uɸ f. UHHdH%( HE1HEdH+%( u1ff. f UHHdH%( HE1HEdH+%( u1ff. f UHHdH%( HE1HEdH+%( u H H UHATASHdH %( H]HH5> H H5L H H5 H H5 H H5 H H5ރ H H5 H H5[ H~ H5 HguPD ?f DHt0HUdH+%( H[A\] D HuH f. D'f D DHf D D8f D D9{ DHk D[ff. UIHHcHHdH%( HE1? L LHuoLOIslt*11ff. fLH9uHcHHGIL HHDI 1HUdH+%( uf HDڸff. f UH5Y HSHdH %( H]H H5 H H5 Hi! H5 HR H5_ H; H5R H$ H5 H E H5( HN H5 H Hv 1HH 01+HEdH+%( ! H]1HEdH+%( H]$ HEdH+%( H] HEdH+%( H] HEdH+%( H]@ HEdH+%( H] HEdH+%( ujH]駺 HEdH+%( uJH] HEdH+%( u*H] HEdH+%( u H]Wrf UH5W HSHdH %( H]HW H5Y H@ H5H H)! H5V H H5 H H5 H H5 HE H5~ HN H5 H HHv 1HH| 01)HEdH+%( ! H]1HEdH+%( H] HEdH+%( H]* HEdH+%( H] HEdH+%( H]S HEdH+%( H]S HEdH+%( ujH]w HEdH+%( uJH]7 HEdH+%( u*H] HEdH+%( u H]2f UHHdH%( HE1.wH HcH> D 1f D HUdH+%( ! H H- H- H- H- H- Hy- | @ Hd- l @ HO- \ @ H;- L @ H'- < @ H- , @ H, @ H, @ H, @ H, @ H, @ H - @ H, @ H, @ H, @ H, @ H, | @ H, l @ Hw, \ @ H, L @ H, < @ Ht, , @ H_, @ H( @ HS, @ HK, @ H+ @ H+ UHHdH%( HE1HEdH+%( uɸ zf. UHHdH%( HE1HEdH+%( uɸ :f. UHHdH%( HE10 H HcH>f H9 f HUdH+%( H7' H+ Hj' H* H H Hj' | @ H l @ H \ @ H L @ H} < @ Hq , @ He @ HY @ HM 1 UHHdH%( HE1HEdH+%( uɸ f. UHHdH%( HE1HEdH+%( uɸ Zf. UHHdH%( HE1w8H HcH> D HZ HUdH+%( 1 @ HK) HC) H% HJ' H>' H2' H t @ H d @ H T @ H~ D @ Ht 4 @ Hj $ @ H` @ HV @ HL @ H& ff. @ UHHdH%( HE1HEdH+%( uɸ f. UHHdH%( HE1HEdH+%( uɸ jf. UHHdH%( HE1 0 Ha HcH>f Hh f HUdH+%( H Hr H] HH H3 H H | @ H l @ H \ @ H̸ L @ H < @ H , @ H @ H| @ Hh @ HT @ H @ H @ H @ Hk @ HV @ HA @ H, | @ H l @ H> \ @ H) L @ H < @ H , @ H @ H @ H 1 UHHdH%( HE1HEdH+%( u1ff. f UHHdH%( HE1HEdH+%( uɸ f. UHHdH%( HE1 H HcH>f H f HUdH+%( HU HA H- H H H Hݶ | @ Hɶ l @ H \ @ H L @ H < @ Hy , @ He @ HQ @ H= @ H) @ H @ H @ H @ Hڵ @ Hǵ @ H @ H | @ H l @ H{ \ @ Hh L @ HU < @ HB , @ 1!H ?ff. @ UHHdH%( HE1HEdH+%( u1ff. f UHHdH%( HE1HEdH+%( uɸ f. UHHdH%( HE1: H HcH>f H f HUdH+%( H H H H H`8 HM H9 | @ H l @ H \ @ Hv L @ H < @ HF , @ Hͳ @ HN @ H9 @ H$ @ H @ H³ @ H @ H @ H @ Hj @ HT | @ H> l @ H( \ @ HV L @ HA < @ H, , @ H @ H @ H @ H @ H @ H @ H @ H˱ @ H @ H @ H | @ Hw l @ Hb \ @ HM L @ H8 < @ H# , @ H @ H @ H @ Hϰ @ H @ H @ H @ H} @ Hi @ HU @ HA | @ H- l @ H \ @ H L1E蠽 UHHdH%( HE1HEdH+%( uɸ jf. UHHdH%( HE1HEdH+%( uɸ *f. UHHdH%( HE1 0 H HcH>f HC f HUdH+%( H HF H2 H H H H | @ H l @ HM \ @ H7 L @ H < @ H , @ H @ H @ HC @ H @ H @ H @ H˭ @ H @ H @ H @ H7 | @ H l @ H# \ @ H L @ HЮ < @ HM , @ H @ H[ @ Hi 1 UHHdH%( HE1HEdH+%( u1荺ff. f UHHdH%( HE1HEdH+%( uɸ Jf. UHHdH%( HE1!P H HcH>f Hƭ f HUdH+%( H Hɭ H H H Hy He | @ HQ l @ H= \ @ H) L @ H < @ H , @ H @ Hݬ @ Hʬ @ H @ H @ H @ Hլ @ H @ H @ H @ H | @ Hq l @ H] \ @ H} L @ Hh < @ HS , @ H> @ HG @ H2 @ H @ Hkw 1 UHHdH%( HE1HEdH+%( uɸ! 芷f. UHHdH%( HE1HEdH+%( uɸ Jf. UHHdH%( HE1?wH9 HcH> D 1f D HUdH+%( H HZ HE H0 H H H | @ Hܪ l @ HǪ \ @ H L @ H٪ < @ HĪ , @ H @ H @ H @ H @ Hݩ @ Hɩ @ H @ H @ H @ Hy @ Hf | @ HS l @ H" \ @ H L @ H@ < @ H , @ H @ H+ @ H @ H @ H> @ H @ H @ H @ H @ H @ HϨ | @ H lg UHHdH%( HE1HEdH+%( uɸ *f. UHHdH%( HE1HEdH+%( uɸ f. UHATISHH HXL`Lht#)p)M)U)])e)m)u)}dH%( H81HEIL H(HLHH@ Dž Dž$0 H0<L9sEf;./HuH{/u H8/tH8dH+%( u)H [A\]f LH5 H讟Dz UH HH: dL%( LEL LEHEdH+%( uI1HH if UH HHdL %( LMIH 6 A9 HE: APL LEHPHL 1HUdH+%( uf D UHH dH4%( HuH`(1ux% = HUdH+%( u藱 UHSH H $ H LV dH%( HE1HHIVH߾ x)HPHX1Yuh% = @ HUdH+%( uH]f UHSH H $ H L dH%( HE1HHIVH߾ (HPHZ1Yu h @ EHEdH+%( uH]H UHAWAVAUATSHXH}HudH%( HE1H HMIMHE ItmHH / ? LH0uILH8uILH<uILH>uII? DHHELH11LMLLAH} HELME1HLMHEqf D LL ADLLÿ DuALL HEB40AH} HEHL9t>IL9u5 LEM!tHELELL B40ALEL9EuLDuHH#EHEt?E1LuMff. @ LL AIHEI9uLuLuL ALELmM!Mff. HEHML B4(IAM9sHELmHt5E1LuIM HMuL AIM9uLuLmLL AIL9uLL AHUdH+%( u8HX[A\A]A^A_] D HE I v1G UHHdH%( HE1Ht`t\N< u8t/NH Hv t3HGH9t Hu HUdH+%( uf. 1跬 UHAWAVAUATSHdH%( HE1f IIE11L5v ff. L L1C< A$ D)0ID9HcHUdH+%( uIH[A\A]A^A_]f D HG L1I 覦A$ D9r1ǫ UHHdH%( HE1HEdH+%( u1荫f. U HSH(dH %( H]H]HutHEdH+%( ubH] @ H HeHeyfoEH fs)EyHv H0 01۪ff. UHAVAUATSH dH%( HE1?v!1HUdH+%( uyH [A\A]A^] LmHL D0I艳u)HEȅt H HEL HEt E4$f D E4$xf. f. f D UHATSHdL$%( LeIH?Ht"Lf D ˙HHC H;HuHEdH+%( uHL[A\]阙蓩 UHAVIAUATSH? dL$%( LeI 1ff. @ ;HDŽuq{Hc IH MtA $LA> tLutH HEdH+%( HL[A\A]A^]f. H v C @ WHt t? txRfXf H qv I @ AVIt tLHH)/HtHHC4 1L艓E14{Hc f. f. f. UHAWAVIAUATSHH(LcdL<%( L}I1I9t}A$O ID$Ht o Ml$Mt AE I $H Hw"HEdH+%( T H([A\A]A^A_]HHHLcI9uLcA$ ID$Ht Ml$MtAE uIELID$MeLkHtIL$HHULLAHUIEHJHCI]I $Ht H0HH0HIE H Hj HH;Xo HPHEdH+%( o H(LHL[A\A]A^A_]Ml$HCLkI\$IE HI$L#HvrHH;XtL`LHMAl L`fMl$HCLkI\$IE HI$L#Hv*HH;Xt(L`LHMA M& M& L`fHH2 @ IELID$MeLkHtIL$HHULLAHUIEHrHCI]I4$Ht HHHHIE H3HILMIHPLMI3f D UIHHHdH %( HMHH Hu\HrH9tlHt HpHH9 HrHPHtHJHH HH:HvcHH;Q HyHEdH+%( @ HrHtt2HpHH9 HrHPHtHJH @ I8 HJHHH HHH HH D H s @ HqHpHAHtHxH>HqHHHHrHPH D Hy& HqHpHAHtHxH>HHqHH,q UHHHWdL %( LMIHwH HZ HFIHHu f D HHHPHuLPILQHpHHHHWHPH2LH2HH5 HHH;~D LFM H0HtHHq1H9tl HVHt r HFHt HHtpHw HEdH+%( HHHpHH9uHA HpHt x HPHt HHuHH덐HHI @ HVHAHQHNHHHH1HvNHH;H HpH @ M LVH @ LF I1 HHv/HHH;y HqHu! I1HH @ HpHQHqHHHHHHHviHH;Jt+HBHHHHvHH;xtBHP]HBIO HpHqHv)IHPHPHHVHpHAHtLFLHHHFLGHAHNLHt HHHHHLHvHH;HtHxHI9HxHrHHpHBHQHtL@LHHL@LWLAHHLMt IHIHHLHvHwH蔟 @ UHHAVIAUATSHH?dL,%( LmIH H HSH9 Ht HWIH9 HSH_HtHCHHHL#H} HH;X L`HEdH+%( A HHLH[A\A]A^]HSHtt:HWIH9 HSH_HtHCHyf M& HCHHHHHHHH D H HEdH+%( H[A\A]A^]f HPHWHxHtHOH IHHAIT$LHSH_Hf D L` HPHWHxHtHOH IHHAIT$L蒝f UHHdH%( HEHHt/ff. @ HH@HuHEdH+%( u H17 UHHdH%( HEHHt/ff. @ HH@HuHEdH+%( u H1ל UHHdH %( HMHH9tHHWHt2f D HHRHuHUdH+%( u" H9xuHHHHHw1^ff. UHHdH %( HMHH9tHHWHt2f D HHRHuHUdH+%( u" H9xuHHHHHw1ޛff. UHHHodH %( HMHH7HHyL@Mt I8HI8L@Mt I8HI8Hv/HH;FtHNHEdH+%( uHNf. H 6f D UHHdH%( HE1HtNH1Hv HHH9xtHEdH+%( u+H @ HBHt HH@Hu1蹚f UHHdH%( HEHHt8ff. @ HH@HuHBHuHEdH+%( u H1Nf. @ UHAVIAUIHATSHdH %( H]H?IHt"I9HCLLIBHH~AD HEdH+%( uHL[A\A]A^] UHATIHSHdH %( H]HVHHtHLH~HHEdH+%( u HH[A\]]ff. f UHHdH%( HE1H| ytM~N H HHu=H HunH HuLfHEdH+%( uWɉ D G<ft8><Ft2<Nt f D f 0t1u1 1롐<ntu D UHHH Ev dH%( HEH t @ PH uHUdH+%( u ff. UHSHdH %( H]H HtaHDH9r1H v ff. ff. HH9r u@ HEdH+%( u+HH]~f D HEdH+%( u HH]kff. UHHdH%( HEHt.ff. ff. @8t#HHuHUdH+%( uf D HHu UHHHdH %( HMHH7 tp )@:8 tU@:x tF@:x t7@:x t(@:x t@:x t @:x HH)HH I@IH D HH9 H90t@:8E @:xC @:x @:x8 @:x @:x- @:x, 1@:x ff. fHEdH+%( - H HHff. HH9ts@:2tHff. ftW@::utM@:zuWtB@:z t3@:z t$@:z t@:z t@:zu+1=HP4H+HP"HPHHHPHPHPHPHHHH[f. f. UHAWIAVDv?AUATSH(dL,%( LmADIDEtsI1Ldf D I>IM9uA?u'HEdH+%( u<H([A\A]A^A_] DuDHHK#<1臓 UHcH?HHHdH%( HE1~eAvnHFH9teHBH9t\A1AIff. D oo fHL9utHH HHEdH+%( u9É1ff. ff. f D LL LHH9u褒 @ UHAWAVAUATSHHuH}HUHMdH%( HEȍHHEO9 EIAE1G HEHuDH J<8L)1йHIE9rvEA9 E]EHuH}AVUmMIŋEA9D9 } uHEHuH J<8L)1]HIc HEHuDHپ J<8L)10HINjEA9eHEdH+%( u-HHL[A\A]A^A_]f D ]8 E1.ff. UHHdL%( LUAA AB HBH9 HFH9 A1fAEIff. ff. f oofHfI9ufoEfsffH~E9tNN#NL ?t$EJ4J#4HHHH!JH HHUdH+%( u> EE11I @ N N# N IL M9uf D 1 UHHdL%( LEIt=DH fHxI9t'HHLI9Lt1HEdH+%( u4ɉ ?tI H3 HHΉHH>ff. UHHdH %( HMt>D@ HPI9t'HHTH#Tt HEdH+%( u)ɉ1?tHH#HHH覎f D UIM HH?dH<%( H}HHDD8ExnELAEKtff. HH!HHH9uAOLE)EtHHH!HI!HEdH+%( uÐAf D UHHdH%( HE%UUUU)lj33333333%HUdH+%( uvf D UHHdH%( HE%UU )lj%33 33 HUdH+%( u ff. f UHHdH%( HEU)lj33ЃHUdH+%( u豌 HUUUUUUUUUHHdH%( HEHHH!H)H33333333HHH!H!HHHHHH!HHHHHHHH HHUdH+%( uf UHHdH%( HE1=Xx Xx tHUdH+%( uE @ HuH= x }Xx Xx f D Hs茋ff. UHATASHdH%( HE1@u"HEdH+%( uFHD[A\] H蠴tWHHEdH+%( uHH[A\]Շ UHATSHHdH%( HEHGHT0H9r5H9sTHDI0HHH9HC1IHu2L*qHt7HCL#1HUdH+%( uH[A\] @ H{ȸn UfHHdH%( HE1Hv HGHuHEdH+%( u 1 HEdH+%( uff. UHSHdH%( HE1H? u HEdH+%( u9H]f HH[HEdH+%( uHH]1聉 UHS1HdH%( HE1H? tH_HtHGH1襍HEdH+%( u HH]( UHAUATISHH(H7dL,%( LmIH HH+GH AoE H{MMH EIEH)HEH{~x8HcHHtHH+CH9`HsH; I HCLcB 1HUdH+%( H([A\A]]f@ HuH3W HuH{H3LMMH H)H{~HcHHtHH+CH9RHv Hl 01L @ 1H~'1蜇ff. UHATSHHdL$%( LeA 4u HSHKHrHsD$HKHS HUdH+%( u H[A\]# UHAVIHAUATSHHdL,%( LmIAąt(HEdH+%( u\HD[A\A]A^]f H{LH{LkLkH; tHCLkB( @ 1HVtAx UHH H`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEH0Dž0 H8HPDž40 H@HHdH+%( u轅ff. f U HAWIAVAUATASHHLoL7dH4%( HuHHD=t+g IG~ Hþ LI_u>IwDHIwHIHHyMtXI? t\IGMoB( HcHEdH+%( uHHH[A\A]A^A_] @ IW I_L) L1L|t衄UHAWAVIAUAATASHH(?D>dH%( HE1@uz A?tRA[ A\u E~IE Hv A@D8 {E~HI@ EA* AtJEqHv @Hc umA OE~IVIEtA*u A* 1HEdH+%( % H([A\A]A^A_]D8O D {HSH@ @m AV! INE1HA@8~ Q]AA u) @ H@8t[ʄ@ƀ]@ Q H-u׀] DXA8@@8@ uGA8PH @ I]@!t/ff. ff. @ HH]uLpE8{DxH@2A*t%E@f D H@- E11 E~IA*t EOAʼnE@tMLAHLkƄ#{L@u|f D AVINEdxfE%fA*7\G UHHdH%( HE10 Hu 訉HuH~H}HtAJ2w\L Ic L> H H v t ~bu) u#HUdH+%( u]f~Btf. H ~ t H f. Hf. H({Bf UHHdH%( HE1HEdH+%( u 11l UHHdH%( HE1HEdH+%( u ɹ 1) @ UHHdH%( HE1HEdH+%( u 1ɺ @ UHAVAUIATSHdL4%( LuI腊HLcLwߍP)HI)HcKD% x HAt@8u)y1HUdH+%( uH[A\A]A^] D )~ @ UHAWAVAUIATSH8H}HMdH%( HEH H)L$ LVH IH ns Ljs E11M LLEMHMI% HMLI< 1H)HN LcLHELELI< HMH)Hs F 1I貥LcLM9tI9uLmE1HUdH+%( u+H8L[A\A]A^A_]f D H r Lr 9} UHATSHHdL$%( LeI @ HXHt?x\u9x\t3LHxH9t#HSH9uҀx\uHx\uf. HUdH+%( u H[A\]} UHAWAVAUATSHdH%( HE1]IHtv\ H肕IHtax L`u)~f D ILLM)LcLMi{ tWI|$\ 8HHuL訇LLHPiHEdH+%( u!HL[A\A]A^A_] AE 4| @ UWHHdH%( HE1@ǀ v)aP7@FHUdH+%( u 0{f D UHAWAVAUAHATSHH8HUdH%( HE1ʆHIAʼnƉE6H E~E1f D uHxAHuEAMcHxJ< HEIHtuuHؓIHtWMcff. fII_LHLL)_LHuLL)LH_uHN$0聓IHuHL螆HEdH+%( u"HEH8[A\A]A^A_] @ A =z UHSH0 dH %( H]Hu HEdH+%( uHH]AjH{0z UHAUI ATSHdL$%( LeIHtEA}0 Hu#LcHHUdH+%( u)H[A\A]]fLZIHuHi1yff. @ UHHdH%( HE1HEdH+%( u H|gy UHHdH%( HE1HEdH+%( u+yff. UHAVAUIATSH dH<%( H}HH5S H IH L H耠Ht[HHtHLƄ ^AƅtL,HEdH+%( u/H D[A\A]A^]f. E1D0AIxf UHHdH%( HE1HEdH+%( u xff. UHHdH%( HE1HEdH+%( u0wff. UHAWAVAUATI8 SH(dH %( H]HNH( IH D;Ls[ALaH*E}0~ v fHnHA]1L=1l IE(flHEHEAEMuJ 1` A}1 LL]AH}f,EurLc, LvHH LLHE ntsMtH}ML HsN 1蹽H}]hf,L]fE1f. HEdH+%( & H(L[A\A]A^A_] It$LKA4 H}f. HuL$A @ E11A o A<$ u H5j LHE ntmMt7H}ML H}M 1üH}x914_tIA}1 u#LL[H}SeH}=eIt$L[HuLKuf UHHdH%( HE1HtHEdH+%( u;[ HEdH+%( utf UHHdH%( HE1HEdH+%( uptf. UHSHdH %( H]HRHƄt(Hp|t &t!t(w-ff. fH3HUdH+%( uH] HP>f. |t;&t6!tA(t,)t'H=Ȟv uf. HJHruz\u zOvosf. UHATSHHdL$%( LeIHt=HsHt4<&t}<|ta<!tEHEdH+%( uwHL[A\]f D 1HUdH+%( uPH[A\]f D H{Lt H;L]uH[nH;LEtrf. UHAVAUATSHdH%( HE1H~ LwIMn AH<& <| <! A 1H IUHI}IcE1HH (HsiAąxHA D)EGd5 HEdH+%( HD[A\A]A^]f. L}AHtHPLHV I} H Ht\(HsAąxHEt$D)AD$" I}E1H AEHAą=@ D A HzAADpEE1A qff. UHAWAVAUATSHdH%( HE1H HGHHt <|<&t<! L#Ms ID$Ht <|<&t<! M,$M IEHt- <|<&t <!tI}ff. @ Mu M IFHt <|<&t<! M>Mt;IGHt <|<&t<! I?IL_M~Mt;IGHt <|<&t<! I?IL_L_MuM IFHt <|<&t<! M>Mt;IGHt <|<&t<! I?!IL_M~Mt;IGHt <|<&t<! I?IL^L^L^Ml$Ms IEHt% <|<&t<!tI}> Mu M IFHt <|<&t<! M>Mt;IGHt <|<&t<! I? IL^M~Mt;IGHt <|<&t<! I?IL]L]MuMtvIFHt <|<&t<!G M>Mt;IGHt <|<&t<!m I?eI\LT]I~KLC]L;]L3]LcM ID$Ht <|<&t<!3 M,$M IEHt- <|<&t <!tI}膏ff. @ Mu Mt;IFHt <|<&t<! I>I~L|\MuMt;IFHt <|<&t<! I>II~@L8\L0\Ml$M IEHt) <|<&t<!tI}貎ff. Mu Mt;IFHt <|<&t<! I>I~L[MuMt;IFHt <|<&t<! I>yI~pLh[L`[LX[HEdH+%( s HH[A\A]A^A_]/[ HEdH+%( C H[A\A]A^A_]f D H讍L#MEf D I|$荍NI|$}I~nafI~^fI~NfI~>qfI~.fI~ fI~fI~fI fIތ?fIΌ-fI辌fI讌fI螌fI莌/iff. fUHAWAVAUATSHXH}dH%( HU1H LmfLeILHE )EHEH <) HM1MHM @ <! <&0 H IT$H HU蟋IH_ HUH] IG IGIHUM|$Mf HLEIWHEH <) <(tc]<| LeH M IH HK] M'HUMIGIG L}s H HuH{jH]IGHt}H ;) HS2fH 聊H HUfHHEH@ HIGH)HUOLEHUHI@fLeHE 1fI M ID$Ht <|<&t<!1 I $H HCHt+ <|<&t<!tH{ff. fL+Mt<IEHt <|<&t<! I} I}LVLkMt<IEHt <|<&t<! I} I}LVHVI\$H HCHt( <|<&t<!tH{f. L+Mt<IEHt <|<&t<!+ I} I}L VLkMt<IEHt <|<&t<! I} I}LUHULUE1HEdH+%( HXL[A\A]A^A_] Huc Ht$H fHUHH IGIfIG 1LeHE D I|$݇Le LeHsI GI}詇I}蛇I}荇 I}I df D UHAWAVAUATSHdH%( HE1Hs L'HM5 ID$Ht* <|<&t<!tI|$ff. M,$M IEHt <|<&t<!) Mu Mt;IFHt <|<&t<!6 I>I~LSMuMt;IFHt <|<&t<! I>I~LSLSMl$M, IEHt <|<&t<! Mu Mt;IFHt <|<&t<!f I> I~L SMuM IFHt <|<&t<!N M>Mt;IGHt <|<&t<!D I?ILRM~Mt;IGHt <|<&t<! I?hI_LWRLORLGRL?RHEdH+%( HH[A\A]A^A_]Rf D HEdH+%( H[A\A]A^A_]f D I}薄f. I}~qfI~nfI~^fI~NfI~>fI.fI ]aff. f UHAUI ATSHdL$%( LeI趃HE HHtBHuLFHHt.HEЀ8 u%HEdH+%( u/HH[A\A]] MtHEI$H1yi`f UHAWAVAUATSHdL,%( LmIHE Mh HH\ HuILeHH A<$ uk Mu тIHa fInfHnH U flID$1A$Me HUdH+%( w H[A\A]A^A_]f. MtM&HCHt <|<& L+M IEHt <|<& Mu Mt&IFH I>rI~iLaOMuMt&IFH I>CI~:L2OL*OLkM IEHt <|<& Mu Mt&IFH I>I~LNMuM IFH& M>Mt;IGHt <|<&t<! I?I{LsNM~Mt;IGHt <|<&t<! I?@I7L/NL'NL NHNMt2 <!>H{覀0f. f D HE <|<&`<!XI~QJ D <|<&<!I~! D <|<&<!I~ D <|<&2<!*I~ D <!I}f. <!HI}:f. MM& IVf. I>:}\ff. f UHAWAVAUATSHdL,%( LmIHE Mh HH\ HuIbLeHH A<$ uk Mu ~IHa fInfHnHP flID$1A$Me HUdH+%( w H[A\A]A^A_]f. MtM&HCHt <|<& L+M IEHt <|<& Mu Mt&IFH I>2I~)L!KMuMt&IFH I>I~LJLJLkM IEHt <|<& Mu Mt&IFH I>I~LJMuM IFH& M>Mt;IGHt <|<&t<! I?DI;L3JM~Mt;IGHt <|<&t<! I? ILILILIHIMt2 <!>H{f|0f. f D HE <|<&`<!XI~|J D <|<&<!I~{ D <|<&<!I~{ D <|<&2<!*I~{ D <!I}f{f. <!HI}F{:f. MM& I{f. Iz:=Xff. f UHATSHdH%( HE1HtMH HtEIHsHt9<& <|tb<!tFHEdH+%( HL[A\]C 1HUdH+%( upH[A\]f D H{L H;LuHEdH+%( u+H{HL[A\]f D H;Lt:Wf. UHAUATSHdL$%( LeL'M HI|$H <& <| <!ufA I|$1Lgxd1M<PDHckIHt H;HHEdH+%( uVHL[A\A]] aDžyff. fE1 I<$1Lox1MDlP[.Vf. @ UfHHdH%( HE1 HLJ HLJ p HEdH+%( uU UHAWAVIAUATSHHHp H~v dL$%( LeI8H @ ff(f(H LL f(L H Lx bLcM9MGH H@ xC H MM)BK<.LH H1IkHI HL9IGMI1M)K<.L"kLP LI HL9IGMIM)K<.M 1H LHL9IGIH@ M)HxH` K<.H L H۵ HLMHL1RLNI EHL9IGIXZH?HEdH+%( * HeL[A\A]A^A_]f. Hc H1HH fH*H 1HH ffH*H ZH fH* 0M YH fH*^ZZ@ f.zq ZYf^ZZHfHH H*XCfLX M LG ? @ HH9 tH HLJ MK<.PM)H1LLG Y^HL9IGI_fHX 1H LhHL9IGI9Lh LQG M1HIG LxhHL9IGI HffHZH H H*XHVHfHH H*XAHfHH H*X@fffHc AK f((H 1HH] fH*(H 1f(\H^ZY\H fH*(H 1\f(H^ZY\H fH*D(ź LLD\^fHLp D^f(f(ZYEZDY\f(A\LcM9MGO H ALHҷ LE HMHH1R f (\ @ HfHH H*XfHfHH H*XfHfHH H*XOf> @ UH/ HHHyv dH %( HMHH81'J }{ff. f UHHdH%( HE1f. f D UHATSHHH dL$%( LeI9L HEdH+%( u H[A\]Nff. UHHdH%( HE1Ht0 t$H} HUdH+%( u ! dN @ U HHdH%( HE1 <w p HHEdH+%( uɉN UHAWAVAUATSH H $ H H $ H(dH%( HE12 IHHHY MHcH> @ Hizv I LHH E1HEdH+%( HeD[A\A]A^A_]H!zv M HLHH 9 I LH1HѮ c Hyv I LHH (HHH9uff. HH9t8/uH)L HLHIUHBƄ- Gy A f D 1LHLoHE @ ېH!yv LHH A H p~LM L$ HH H)H<1Sf D Hxv H RA LHH ~I HLH<H H)17b:fM LVH H5 LCHLxv H @ LHH }I HHzf M A LL9u HL9t8/uIHwv H LHH /}I LLcLH)L)HH9CJ<;H 1zrLLH$@ Hc1LH)HZr D A @LI L茮H=wv LHH " H |LHMH L" HH)H<HP1gXZL HL jADžyL u HHL1AUMM HL HDY^4LHu IL9uI UHHdH%( HE1 HUdH+%( uPI UHcHAWAVAUATISHH8HUHIfoZ LEdH%( HE1)EH-XXXXXX HEH[v L4AV~ L}L*:AŅxzHAVu6Mt|HULLcHEdH+%( uYH8D[A\A]A^A_]ÐHED ?L@Af D 1HAԥH] EHL?ff. UHATSHHdL$%( LeII*t5t t+HEdH+%( u9HL| L1[1A\]qjHEdH+%( uH[A\]Gff. UHAVAUIATISHHdL4%( LuI)tKt tAL| LLLiÉ> HUdH+%( u H[A\A]A^]ff> Gf. UHAWIAVAUATSHH(H}H߉UdH4%( HuȾ/ tH߾. IdMfIID$AHE;[, M}L5iYv A H5T MuH} 1HUdH+%( H([A\A]A^A_]f Iv0IAHtL7uHEID`L9srAE .uAEkuAEoH}G } uuHDIؾ )HQ; tIHE_ - H8蚂8 D } )H}1HH5 輌u D H5 H= H5: H= H5 H|= H5 H`= H5 HD=e H5 H(=IAG ?f D H%HMHH+ Dff. UHATISH dH %( H]wru%1t(HUdH+%( H [A\]f1t1H}LHE܅tHkv LH} 101 x uHmv پ H H81>x VCff. UHSHH dH %( H]H'HEdH+%( u HH]9TC @ UHAWAVAUATSHH dL$%( LeIt 6H H h"H\ 趐IH. H5Hd MtIT$( A LHٮteH[L2 u4AHEdH+%( Hĸ D[A\A]A^A_]f D H \f. L(=u:迟8uH wLHIH`LM 2HB$ADŽ L5~7 L1QAą QH@ 8ICL HHqiv 01H= x A<$ L%w A|$x8ID$I$AD$ID$ fInHBflHHx A$H HHx 2fL@ LHL+ LLLf D AEq HYL0 t H 贮EH w H H w H x Hw H H HH x HtzHH9 x H w {7HCHCHC fHnHBflHHw x H HH` x ] H0 H H0H HH x W x pHiv " H=R H袨H x x : @ L 7 D| Apf Hgv H4 101G H? x fH- x j x Hiv " H= HH3 x x t H 觬A> UH HAWMAVIAUATISHHhHuDMdH%( HU1HEHUff. fM f MtI@I9v M@MuM( I LU`IH A LU H= x LELU;H8 E LULEHEA A Lm+ LxMMILUH]LEIA I A$HLA A xLULELMLxAdž$ Ip(LѺ LELUxLULEHH= x LEHULx<6HULEH- LxHMPLI@ LULE/M LELUMu IEIUHt(IIEI9rH I9 IEIUHufM(HuLA@LLEܭL4ULEMhLL)Mh M)M9MG} trIt (LH MxrtLmLMM)HUHEdH+%( HhH[A\A]A^A_] H I9yM@`I| (LH MyLLLEzTH}a+M9A I LULh(HEJLEHx HLUHh B Hr(I9? L)H9HGL։s4 3AP($LfAL HIx0HIU HLILI)B(L)HLHU*LUHUMLf HHuLLULEA Adž$ LELU虗LELU Hc LLULEMLxHUE1AM LAL L)H9Adž$ L)UHAVAUATL%x SHLH0 dL,%( LmI\7He4 Dž H y7 L LH ǃ$ Hei HE1H0 LT2HEdH+%( H0 D[A\A]A^]f D I t+ALH߈ G xk ǃ$ D(Azf D ەHP 8AU:H- 1AHH_v 01Fǃ$ +8f UHHdH%( HE1Hx HEdH+%( u7 @ UHATL%x SHdH %( H]HL5 y(HEdH+%( HL[A\]0 D .H H ǃ Hǃ0 fHnH flHBHHx H~HH{x vf D "x uHav " H=z HH?x x 6f D UHAVAUATSH dH%( HE1$ L%x HILl4 Hm1 E HEȋ y, LutHLH xVǃ$ HUdH+%( u^H [A\A]A^]I t#ALH߈ x ǃ$ L>/ 뚸5f. UHHdH%( HE1HEdH+%( u H=x .t5 @ UHH( dH%( HE u 1ɉ( HEdH+%( uɉ 5ff. f UHSHdH%( HE1H0 u[$ Htp t HEdH+%( u_H] @ H }Ht)H Ht!@ H0 1HUdH+%( uH]ǃ$ b4f UHSHdH %( H]H~%HuH0 HUdH+%( uH]4 UHAWAVAUATSHdH%( HE1$ tcHIIIM%uKL90 rBLLr:HEdH+%( uPHMLLLHA [A\A]A^A_] HEdH+%( uHH[A\A]A^A_]V3f D UHHHLHHx4 dL%( LEMuHPH+HEdH+%( u3 UHAWAVAUATSHdH%( HE1$ tcHIIIM#uKL90 rBLLr:HEdH+%( uPHMLLLHE1[A\A]A^A_]f D HEdH+%( uHH[A\A]A^A_]F2f D UHHHLHHx4 dL%( LEMuHPH+HEdH+%( u醗1 UHHdH%( HE1Ht0H? uH uH HUdH+%( uf. 1 @ UHHHoFdH%( HEHG(HX ` Ht@H HEdH+%( u>1ff. UHATSHHdL$%( LeI蹂t%1HUdH+%( H[A\] L舂uϋ A$9r¸ 9rKAT$9r 9rHKIT$H9r H9rHSHsIL$HeH9Y1H9LJ0f. UHHX dH %( HMX 9~ 9ru\ \ 9r` 9rWH` H` H9r? H9r5Hh 1Ht'Hh HtH9r1H9f HUdH+%( uz/f. UHAVAUATSHdH%( HE1H Lo(HIAMtsLkI L L?:Df Ј AEH HEdH+%( HL[A\A]A^]AXD A ujL LA9Df A D HEdH+%( umH[A\A]A^]f H T 1 H < L L]9 f D Ј . @ UHAVAUATSHdH%( HE1H Lo(HIAMtsLG L L8Df Ј AEH HEdH+%( HL[A\A]A^]VD AujL LA_8Df A D HEdH+%( umH[A\A]A^]f H 1 H L L7 f D Ј , @ UHSHdH %( H]HHtzth ~ tFu; H> HHEdH+%( u6HH] H t f +ff. @ UHAUIATSHdL$%( LeAGHHt%H1LA A D HEdH+%( uHH[A\A]]h+ UHHdH%( HE1Ht8HSv HUdH+%( u *ff. UHHdH%( HE1 HUdH+%( u* UHHdH%( HE1 HUdH+%( ux* UHHdH%( HE1Ƈ HEdH+%( u8* UHAVAUATISHdL,%( LmI55H LHH% L LL{Lc(MtAoE X IUHh M LC \ L L4 Lf AD$H R1LH HL%\$ HC@ f% HCH AC0 1f L ƃ Hǃp CPC`Cp虘H ǃx Hǃ L H H HEdH+%( HH[A\A]A^] D u$L)L f D H dL L3 f fH 4*(f. UHHdH%( HE1HEdH+%( u1n 'f UHAVAUATSHH( dL$%( LeIt!HwOv I$ Hk 101赁I|$PlI|$`=I|$0I|$@ID$H JI|$pZI|$xCA$ LM$ UI$ 芌LLHHt(fIHu|LLH臑LHuL?L9I$ tII$ LIDŽ$ HEdH+%( uaHL[A\A]A^]yf I$ IA$ A$ I$ HA$ '& UHHdH%( HE1Ht+x x 9t BJvHEdH+%( uH%ff. UHHdH%( HE1Ht,x J9rx 9tuHEdH+%( u uHEdH+%( u2%f UHATE1SHdH%( HE1*=HtH1H踂HI HEdH+%( u HL[A\]$ff. f UHHodH%( HE1 oF @ HEdH+%( uq$ UHAVE1AUATSHLndL$%( LeL M9s-ItGHEdH+%( uhHD[A\A]A^] M9uHǐ LA @ H LHލuL1J<+L)(HA#ff. UHATSH H $ HdH %( H]HHt(Fu!HEdH+%( uTH [A\]f D LF(L1 LH 肚H L-u @# UHAVAUATSH H $ HH L`dL,%( LmIHLL-AT L PLf 1MۚH L,ZYu @HEdH+%( uHe1[A\A]A^]\"ff. UH HAWAVIAUI ATSHHH LdH%( HE1 I LcI; tH L1 HILL}AH LHB H HE1g I LHc襅L LH2 1< H LHH1! LLcII^8Ht-ff. @ HL>HIvHHuHEdH+%( uHHL[A\A]A^A_] ff. UHATE1SHdH %( H]H虄x2HA HEdH+%( u HD[A\] UHATSHH| dL$%( LeIԅyL' wYHcH/u H H LH1G1HUdH+%( u-H[A\] D L "HH9uf D @ UHH5 HHdH%( HE1rHUdH+%( u f. UHHdH4%( HuHu~xHUdH+%( uh UHHdH%( HE1 HEdH+%( u1& f D UHATSHL&dH %( H]H I$ H bt HUdH+%( uRH[A\]f D I$X HX #uHEdH+%( u I$ H H[A\]b UHAWAVAUATSH8HuHUdH%( HEHG8HEH H H Dk@M E1f. xnLcM9smHEK ,H}HL4M>I buH}IX #x+uHEdH+%( I>H8[A\A]A^A_] TIM9rE1HEdH+%( | H8L[A\A]A^A_]Ät,s@HǺ H JERHC8CHHE @ VH7HUHuH߹ HIFHq UHAUATHuSH(dH %( H]HH utOM1H}HK dxLeк HLHEdH+%( uXH([A\A]] H dIHtHt3HLLIHE] Mt LHxA UHAUIATSHHHFdH %( H]HHt sЄu9LeI LH;L M Hg 1HHCHEdH+%( u HH1[A\A]] UHSHdH %( H]HH6 HCHEdH+%( uH]1kff. UHATSHdH%( HE1 u!1HUdH+%( u;H[A\] HH I1$DuHhQI$ UHAWAVAUATSHH(> dL$%( LeIt ~ @t-AD$HEdH+%( H(1[A\A]A^A_] H LmL LH LA~3AD$ @L. @ t @uw8uH tH HcIHt LHJA~ AD$ @L f. UHSHdH %( H]HN^HC@ HC8 CHHEdH+%( uH]` UHATSHdL$%( LeI|3AD$@t$1ېID$8H<HHG( 6A;\$@rI|$8;AD$HLID$@ nBHEdH+%( uHL[A\]f. UHAWAVAUATSHHHW8_@H}dL4%( LuIHU;_DC HExH p A܉]A IX 1HE DHUI )D<IcL,HEI 3\ xEgD9"D} A_A9}HcEHEIHEP@D)HH]HEHH4H|HEL@@HX8 NHHEIF(1HUdH+%( HH[A\A]A^A_]ÐHuIX HUHR8HUAI I Y[) @ u\ HHEHtdHUHB8HEZDZ@xH HƍCLF@HEH \MH7 @ 4HHH뢐Hc1HE UHATSHHdL$%( LeI0HLHA?HEdH+%( u HD[A\]S UHAWAVIAUIATSHdH %( H]ȉ E}@1Eu'ff. 1O @ E}@ @ HD9sIE8LL$I$ Yu1I$X uL LHLUOHEdH+%( u*HH[A\A]A^A_] @ 11LLHg UHAVIAUATISHdL,%( LmIr/ LLLHtZHX Hfu'L>HEdH+%( uXHH[A\A]A^]LfuLH s LL5 HHtHHL UHAWIAVAUATSHH8HuHUHMdH%( HE1.Dc@M/E E1 IE9 HC8LN<I ,Xu1IX :uFLnJIHtFHn=HEdH+%( H8L[A\A]A^A_]f Dc@IE9r HEL(1L IHtHHUHuL/H}VL HV LHA$ A$ I:f. UHAWIAVAUIATSHdL4%( LuIAG@tXE1 IE;g@sFIG8LJ<AՉÅtLzLHEdH+%( u H[A\A]A^A_]f. 1 UHHdH%( HE1HU@uH5E ]EHUdH+%( uC UHH0dH%( HE1HuH5HUHUЉMHE HEHUdH+%( u UHH dH%( HE1HUHuH5HE HEHUdH+%( uff. @ UHHdH%( HE1HEdH+%( u1H5GBf UH5HHdH%( HE1HUHE HEHUdH+%( uf. f UHHdH%( HE1HEdH+%( uH6H?H-H-Tff. f UHAVIAUI( ATSHdH %( H]H2H LI)I\$ ID$IH I] LHu. D HCHt_HHsLTyHCHuHCfI $LLAD$L 苁1HUdH+%( u'H[A\A]A^] D HCLff. UHHdH%( HE1H9t[^HUdH+%( uRf UHAWAVI AUIATISHdL<%( L}I\HtkI7LHlHCHtLL LhIWL`IGfHnHXfHn1I_flHUdH+%( u H[A\A]A^A_]Hff. UHHdH%( HE1~tHEdH+%( u 1 @ HEdH+%( u黊>ff. UHAVAUATSHHdL4%( LuIUlt)1HUdH+%( H[A\A]A^] H|uH\uHkuHhuHC L+I L HtHsLQxt)H[Hugf D H[f. L;k E? ff. @ UHAWAVAUATSH H $ H dL4%( LuI8 ZL%8v I$H` H 7v IH= Hc H H IH(H IH AEH=$ jH(ID7H H69v AD+H 8 M IFH HL=uu H(M 1L H( GHc I$H(L,IIE HtKAVIH=u L9u1HUdH+%( uhHĸ [A\A]A^A_] I$HH<P.yL 9. D H0LxHH P UHHdH%( HU1HUdH+%( uH ff. UHHdH%( HE1HEdH+%( uN ff. UHHdH%( HE1HEdH+%( uɉ f UHATLg-SHdH %( H]HL1Hv'{-St?H vQ H5 L1҅HEdH+%( u+H[A\] @ A|$yuA|$S t몐1 UHAWAVAUATSHdL$%( LeLgM LA6_HHz E M|$ M;|$t( D HI_H M|$ HM;|$uMl$-[ L "[ H{-I!MHH8 M I H0v ML$ MH > H I܋01cHo^Hjf D HCH9C tfHEdH+%( H[A\A]A^A_] @ H(^HtIHID$I9D$ uHCHID$ ^Huf H H% H HC MtLSLLK fLH# UHAWAVAAUATSHHH}LHudL,%( LmM HHHEH4v HUHHt1HMINIHtwHMLMM HUHfELeHP/v LEAHM̋0D 1MOH $= fAW(H Mg A_*ATiaHUI-L9XZHEdH+%( uHeL[A\A]A^A_] UHATSHL%3v dH %( H]HAD$ftA|$ u'HUdH+%( u+HH)H[A\] D HH)HAD$ UHAWAVAUATSH(dH%( HEH/3v x u:LgIMt.L[HHt ID$H;Ct:IL[HHuHEdH+%( H([A\A]A^A_] D IL$ HS H)H)u?H~:Ds*AA uAL$+I;][ HL`pHhz^ E|$*HuEH~@AA Y L [HM;eh LLpLIzfDs*DD< Y< u <DuA|$-_S-I|$- Hff. H8_tH)HK-H_ HfH:_tH)HcH9"HMH}HEHUH9H9HL E|$* HYIE <K+1XHK-1_5SLYIEff. @ UHAUATSHdH %( H]H_HtII @ HLUnH]xMt(LH YII;]uH YIEf D HEdH+%( u H[A\A]]a UHAWAVAUATISH LndH %( H]HY {-.Ls.tLs-H H=w ~mu HE fHnH flfHnH (fHn~=u H fHnH flfHnH 8fHn~u H'G fHnH flfHnH* HfHn~ߣu H HEflX~ɣu flh~u flx~u flE~u flE~u flEH LjHC+ ЈC+I$Htg HHHL;hrHH1HHufHCH@uEHEdH+%( Hĸ LH[A\A]A^A_]s fH CI $I\$f D 11L(H5 Hw Hff. @ ;I7IH=}w Hu ff. UHAWAVAUATSHdH %( H]ȉH+v D4ACDÃB<wm $ Hsb>$ItZIIAWMLȸ AE1yHHtB[ L1I|$0HH61HUdH+%( uH[A\A]A^A_]ø UHHdH%( HE1HEdH+%( u1 6f UHAWAVAUATSH H $ HxHfHnHflHpdL%( LEI)`Ht"AP( AH(9t BJvHH L`8 HL[#H5v HHxHMLA HHMDž H0DHHDž Dž HC HQ+v z o IW LpLH HnB L9i H <u H LB"HLcIH I ^tHxH H A4 AoEuA~WAoflflffAEL9 HMw H;X8@ HHhI~0LU;Mt LLMRLs- LIH tH5 L"A L9 Hp tAoEf`AE HDL <tL H 1 tHLI M HL A A I}YIH @4HH=Y L9\MLM9tH < L HEdH+%( J Hx [A\A]A^A_] HxM H"@ HH(H #v 01nUH t4HV( N(9t BJvLHH;X8 HHeLo H HL%IHHxM Hc? HH(H`"v 01TFf. HOHHA8i Hxp4Ƃ (fHOHHA8 Hp !AoEf`AE LE1 H HV( N(9t BJv胅LH H@IG ƀ L L}`M1D @ UHAUATSHHdL,%( LmIuWH5 ; IHtCLI)(HcL9DMHEdH+%( uAHLH[A\A]]86 HEdH+%( uHLH[A\A]] d UHAWAVAUIATISH8HUMLEdH%( HE1MtI M E1 D IM9s-K .UHuHM<IHx-:t4LsM9rE1MHEdH+%( H8L[A\A]A^A_]HEHtHM7MtEuHtH} uB HEHHtMMtIu-I~-bt HnMMtIu-I~-btS E1CC UHHdH%( HE1HLJ HLJ HEdH+%( uf U1HATSHH dL$%( LeIH0 -H ID$H9rIL$ H9tH9sL HEdH+%( u H[A\]u D UHATISHdH %( H]HH;w8t8HIt$0`HjHEdH+%( u#HL[A\] @ HKID$8ff. UHHdH%( HE1H; t\H HG0HtHPH9s"H@HuH HUdH+%( u1ÐHH H9r H9tH9uH@ H Hu]ff. f UHHdH%( HEHG0 HtHPH9s"H@HuHUdH+%( u# HH H9r H9tH9uH@f UHHdH%( HEHG8HUdH+%( uff. f UHHdH%( HE1HEdH+%( u H0 g UHHdH%( HE1HEdH+%( uI+ff. UHHdH%( HEHHH;GHs"HW@HHHUdH+%( u f D 1ff. @ UI1HAUATISHHHwHH@dL,%( LmILHt HUdH+%( uAH[A\A]] D HEdH+%( u"HsHH{@HM[L A\A]]*f. UHAVAUATSHdH %( H]HHOt,HEdH+%( HH[A\A]A^] D H{8H E1+HIHHuJ< R@IHtfH{8IHt"ff. I>IGHHuLH r L%'Lk@HLcH59D1E1$1HC@-f UHAWAVAUATSH H $ HXHH5 HdH%( HE1HDž THn ILLL LL9H$ HH D Hx EHtHHx HjH H Ht LHH$ H L1L1HIxHH < t< (HHLHЅPfHL'HEdH+%( u/HX [A\A]A^A_] @ L1VtHDff. @ UHATSH dH%( HEH v x tH1]IHu 1HUdH+%( u-H [A\] HH3LEEfUHAVAUATSH H $ H HdH<%( H}H HtCLH IL// LCHHtHxH5 I3t5AHEdH+%( H D[A\A]A^]f Hmodules LH5 HDž HChuLH6LLudLLH5z)LAzHHt1fIHDLLHYI~%LfHuE) L+HH IHCLLHXI}LHuf D UHAWAVAUATSH H $ H HpIHIdH<%( H}H[HtkHIHH`KtMHL IHHh-/ LAIHtLpH5 L_1t3AHEdH+%( ^ HĈ D[A\A]A^A_] D e HAD$kcorfAD$\GIHtH Ht4H0Ht,HpHuI$HH9HmHpHVHhL1LLLLg|f s,LLH@OAƅd A A L9 HH5lLH`HpHH5 ƀ HuaL9t\HHE1E1f. Mt%H L9t+HpLHNL9rH9sL)L9sH IIL9uMu LBS( K(9t BJvHLLXXLXHLAo I@HCA@4C4,HHA!ELX HL9tjDXMHPHӐH HCfHnHsflHAHI9tL: HHL9uDXHPH`H5 8 A LhL<A LH|\Hv 0C, LHW/ 1Df D AfHL9t; @ HHCfHnflHBHH{ HHL9uɋ|4f |Af. HhHV 1VCHpHH5 H`ƀ Hv Hh H- 01Bff. @ UHAWAVL5_ AUATSHH(dL,%( LmILHE HE LeL=HLL LL LuLLL+ LLHIHuJ IE H9C IuH{+ HU=LHJ=IH MuHLEHHt2 IH=LLH'RI5 LvHuLIHHt0IH<LLHQI~ L6HuHEdH+%( H(D[A\A]A^A_] @ L GL?LHHt/IH]<LLHoQI}} LHuA=LHHt/IH<LLH%QI}3 LtHuA3_ff. @ UHAWAVIAUIATSHH8MdH<%( H}Hz@H5 LIM? 7 I|$ + HHL I$H H0H HELHi I$HUH+PIH{0 H}H} < } uLLHPAŅt9HEdH+%( ~ I|$H8LLH[A\A]A^A_]U D ID$oC0Lc8HE)EH1 fC0M HEHE HuLdOM7I- cHt IwH}IH IO L@HpHx H+0IwI9sMG LHtHIO H0LAC"L{Mt6LMM9IL;u[L9HEJf. HEdH+%( uBH8D[A\A]A^A_] E1F LxXx A UHHdH%( HE1HEdH+%( u1 yf UHAWAVAUATSH H $ Hx HhIHAdH%( HE1:/ Hv LHپ LH /A 1LLLpL<u HALLLLA Hh<E1A L~'H? v LAƆ H 01w<HEdH+%( uVHx [A\A]A^A_] @ LHѾ HC L D EuHff. f UHd' HAWAVAUATI SH(HudL4%( LuL5 v AHH_ v 01;A~SL= v E1 IE9.~?IHu1LJJ&Å~HEdH+%( ufH([A\A]A^A_]1fH v x u111L%HHtHEdH+%( u HuH(L [A\A]A^A_]%f. UHAWAVAUATSH H $ H H $ H H $ H HxHdL4%( LuL aLNL AHHE M LtnLLdL LA 1AXHLR LHM) L]5IHA LLMLW LLy LA 1WL D HLA 諾H AAAAEg ߈ E D,IH @D HDž L5 1E1E HDL- HpHhDcLfE&A# DIcD L>H : H DDcLLHAHg H AE IcHHHLPLABHHHI)fLIP M9uLE ƃ HHKHEdH+%( HĈ3 D[A\A]A^A_] LH5e HDž &@IH] HHpE1HfL" HHL U%H H D`L IcL HHULHI)A@A9vAL IcHDxHH:UHDxDHA)A@A9"HA McL>HHk HpAHx0LHpHLsA @ HDL- HpHhDcL E&Aw'DIcD L>f A9 IH I9uHhHDDcH L LAH H5V "H DE6 <yHA DHH8B FRHcHHL<HpIIYa 78AD$H d HH#H HHXHX HbHXDbE HDHLs dAwH HE[Hh u H L2f < @ HA DHH@ iEHcHHL<HpIIGHI 68 H HCf D uff. @ HA DHH/@ DuMHcHHL<HpIIT 58 ff. IH I9 <Y < HA DHHg? CuHcHHL<HpIIEH 58 H H"fL @ HDHL AEHh i H Lkf D HDHL A? H DHv H LLH LLDLHD AD$H d HH H HHXHX Hb"HXDbE HDHLdAH H p V AHx.HH5 HITHL @ df D d8f D L7K H H L, HDž Lh~f D L7SH L+wL7 H AD$d fH \AD$dfLX+ DHhLDcL L +uh HpHp AH 0L* LLL M-HHxAHIHDDAtEOLf* DLLLDcHH HٳH D LH}DAT DOEL H"HDž Lh9L Ju E1Mq8MQ HxLH@AŅ LMHxܽHtLp8IM+ LxLHLAŅjHu L H 01, 8ƃ It$01HLL, HHpHPu L H 01+Lh ƃ 1H5j~ H-LxL^LAy T IQ0H Ay G Hu H8 t0HxHD DL u A'I 8 @ LH=b DLD LH DLLL\4M LH u Lw H 1H5L6DHIK LhM HHpLHxHDhLL:%IH MELH 1 LAH)IHtH Ht+H0Ht#HL"uIHH9HuHLyLL LHp-LLIMcM@ LMD$( 1H LFAy 1E111HD DL Xu HHt5Hx HD]DL &u AAy JHu HPXHuLp`MHx1HAmL- LخILDhL- HpLD DEuH L3H: LrILHDDAH= 11HDžx`Hx'IHtGH H H0H L- HLuI$HH9H LH LLL0M LH Yu L H 1TH5 L赱IHLhEMHL-g *e`H!u HH 101`&Hu<H t2HHL- HxLWHA:H!HDHLcAHDHLFAff. UHATSHdH%( HE1Ht#HH1IHHt%Hu @1HUdH+%( u,H[A\]Hu LH 1014% UHATSHdH%( HE1HtHHI?HHt1HUdH+%( u,H[A\]Hnu LH 101$ D UHHdH%( HEH(u x ux u f@@1HUdH+%( u"Hu H" 101?$ UHAWAVAUATSHXdH %( H]H u CEt,1HUdH+%( " HX[A\A]A^A_] CIfC>{ 0 HCHHt 8. HsxH~L H W H Hv H 5i H Hv H ; H HO H H H H L LuM< 1,H H M~M& LE1 I &IHEHEE H Lٿ H}LA1BM LM IIHu AE IAE uIOHUH9t: HUtHLMHM HMHULMHDH9]H5u ff. HH9; uH9)MP E H H+ H ]U H 1HH 8/ x H. H H9t H5( H=z )IHtILmH¾ LHt(" 2 1L KEL\W~" EECCfH Z @ H HHǃ L(k D H ?/ ELH H H H H H tHu H 101 V UHAUATSHdL$%( LeL%Cu A|$ u#HEdH+%( H[A\A]] D I$ I$ I$ I$ I$ I$ I$ H u L-u x&ff. IU HH<xyL afAD$ IDŽ$ IDŽ$ A$ u D UHHSHdH %( H]HHE #Hu H HtP1H}L HH O x+H}R H}1HUdH+%( uH]f @ UHSHdH %( H]H wu H{0Ht \uRH{8Ht Eu1HUdH+%( u0H]HK8H'u Hܻ 101m HK0;f. UHAg HHP*dH<%( H}HHp-уtEAAwHHHL@ 1VH 苽HHUdH+%( u UHAWAVMAUATISH(dH%( HE1HAHurtNEtIHN(HB L1 LcHEdH+%( H(L[A\A]A^A_] H L1ҼLc D HAϾ DEHO-H# L覼LcEtDEEtIL$(HCH;K rIT$HH)H L1 dHIF D UHHdH%( HE1HEdH+%( uIй 1VQ UHHdH%( HE1HEdH+%( uI1 UHHdH%( HE1HEdH+%( uI111f UHAWAVAUATSHdL<%( L}LHMtBII1E1L- IF@L LH 1HH-.HII;^HrHEdH+%( uHL[A\A]A^A_]=f. UHSHdH %( H]HH?{H H{+HC HEdH+%( uH]ٿf UHHdH%( HE1HEdH+%( uP;蛿f. UHAWAVIAUIATISH(L=u dL %( LMIAxu;LL1n LELMNLMLE A A<$ tLLL1H LELMLLELMHcHH)LLLAtA<$ uWHEdH+%( uoH([A\A]A^A_] LELMkLMLE]A HcLH H)I| H 1<ff. UHAWAVAUIATISHHL=su dL4%( LuIAxLuaLL H AAtA<$ uVHEdH+%( u|HD[A\A]A^A_] D 1 t@A A<$ tHL? D Hٺ H= & D 3uA Q>ff. UHH LpLxt )E)M)U)])e)m)u)}dH%( HH1HEL0Dž0 H8HPDž40 H@ HHdH+%( u苼ff. UHH HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEH0Dž0 H8HPDž40 H@HHdH+%( uԻ @ UHAWAVIAUIATSH> dL$%( LeI H I-f D L K HHL)I)tiIL LAHL9tLLxbHL LL)HID=$Hu?LH= ȿx,Hs1HUdH+%( u9H[A\A]A^A_] ؐH LL#H謺ff. UHHfT dH%( HE1f/ HS0 sf/L H@ H! HFHUdH+%( u<ff. UHATSHH dL$%( LeIEEHHEdH+%( uH LH߸ [A\]u й UHAUATISHH(dL,%( LmIE菼EHHEdH+%( u H(LLH߸ [A\A]]ۡff D UHH t)EdH%( Hx1EHEDžd0 HhHPHpZHxdH+%( u UHAVAUIATISHH HHt)`dH%( H(1HEDž H`H0DpH Dž0 WELLHH߸ 趠H(dH+%( uH [A\A]A^] f. D UHAUIATSHHdL$%( LeAHtDH5ư H H5 Hn¸ tTH5 HTtHLtaExdEtGH={ HHtCH5l wHUdH+%( u7H[A\A]] D u 1 @ >A @ UHATSHHdL$%( LeIH5P t HEdH+%( u*H1[A\] @ LH`Hu 蠶 UHHdH%( HEHFH9Gt HUdH+%( u 1W UH~HSHdH %( H]HHEdH+%( u HH] f UHAVAULn(ATSHH^(dL4%( LuIL#L9t<ff. fH{nH{@eH{8\HL蚥M$$L9uHEdH+%( uHL[A\A]A^]nif UP HSHdH %( H]HHt+o oC@oC @ oC0@0oC@@@HUdH+%( uH]ff. @ U8 HSHdH %( H]HyHt.oHH( oC@oC @ fHn@ fl@(HUdH+%( uH]lff. UHAWIAVLuAUATS HHFdL,%( LmIH8AĉILHA uIE H8AljPI}LHA uDD)HUdH+%( uH[A\A]A^A_]虳f UHSHHdH%( HE1Ht#H5i HHt@t09rHEdH+%( u H]1Ð' UHAVAUATSHdH%( HE1H tgH0 It]II1Hu/HHtEHsHtI|$0btHEdH+%( u=IUIE HL[LA\A]A^] HEdH+%( uH1[A\A]A^]mff. f UHATSHHHdL$%( LeIHvAu-HEdH+%( u6It$ H{ H[A\] HUdH+%( u H[A\] UHATISHHvHHzHdH %( H]Hu-HEdH+%( u6It$ H{ H[A\] HUdH+%( u H[A\]c UHAVAUL- ATSHHdL$%( LeIMtbLL7 H L>LHLcL- tI; HHtHXMuff. 1HUdH+%( uUH[A\A]A^]fB3;tf. f H5 L!e D UHb H5 HAVAUATSHHL/L2dL$%( LeIMLLD'tLL1uIt$H{1u"HUdH+%( uSH[A\A]A^]f D ID$o oC@oC @ oC0@0oC@@@oCP@P 胯 UfHAWAVAUEATMSHH HhHMH0H(DLdH%( HE1Hu H )EHE@ E|$E A|$ ( A|$ N EuH;|H @ HE Hp H H}ƅK 1A H@L5ק H D IHPH<H L=7u H8L`Iff. H`I HQ 0H1NHV6 E L @ HH" HHLHXH)* / L% HX@ \HXLHIH)HqHܾ H5 Lu| LXLP7! LuOLLL)r0u:CH DLDIHuDLXt @ HUdH+%( He[A\A]A^A_]ÿ 4H蜍HH H;A|$ HjHH H;LXLP H5V L螽VMt"ILeLLHw/Hh t%HhH6HLHH E1MMH H8H Hp HH97D At"Et H@1H5 GK LmA| EtcHI膶H@LH蔼LHCHy A| R HH_ Ed E H@, Tt ƅKD D : HsIHt{HH)HL H5ɣ L, Lcvf D { LCVf D HhH{H:HOE|$E v HފHHt%H;^H=A 轊HHS HEH@谋IH6 Leu HM 1HӢ LpA2L`LM HHu1j L0E1LL<ZL`Y H u Mu f)EHMM9 LH]L%I LPLXMf I` H} HEHE I` H H`Ff. BLr0HH AHu'AFIV <!tHItىLX\ M?M9DLHLXhI hH(L)E1f D LhRLzH@ h I` ėH}蛈I` H I H5Š ȹHOI :H}@ H` H`H ff. /Hx@ HuHh t'LhLQLHHc H}I HLXH߉h h 1H LXLPH`H 1LXA2H1 H nLp]HuLh+h@Hh -: ؾH: Hr H}h$ hHHb!ѥH UHAWAVAUIATSH HdH %( H]HH cHPHhHz LhL5t ff. LL HH $Me8 fH)p)U)U)U)UfInfHnflLpHEL@HHXttH}˔HXAoEAoM8@8H(IU(HPHS fL)p)])])])]]fInfHnfltf. LHLHHx @ HP,1HUdH+%( u$HĈ [A\A]A^A_]f I}off. UH V H5 HAVAUATSHHL/L2dL$%( LeIMLLDtLL1u Md$H{L¸ t$HUdH+%( u&H[A\A]A^] H{L*f. UfHAUATSHHdH%( HE1)EHE Hu)E)EHtoHAHtH HtHELmHLHt HUdH+%( u5HH[A\A]]f D EtLH@LH 1g UHAWAVAUATSHHH HELu(HHHH5 HHE DHHE0 HEDDH0LfHnfldL$%( LeL@fInfl)HHDž E )0EVEd HLHH H(H(E1HLH@L9 H0HHH0HHzHHq AHH5. HH : HE1wHt LxHfoL`H5> HLƅ HhHL`HE HpELxEE E)@؏ EfHPH=)EHC HPH)EHhH HEHHE HE EHL`HEHpEHLxHELX! H@Dž L9t'H0HHH0HHpHHJHu HH> 101;HH0ALL#HL9tiEff. fHSfHnH{PMflIT$L"sH{3H{(aH{`1HL薎M$$LM9uEHEdH+%( HeD[A\A]A^A_]H@ L9<AHD(H0D D LH!~?u fHnHflIF(AFgHύ=Pkw E H1HIt 8 H0HIH9 H HHtA|$X tZ Ml$(HID$`LIT$ED$XPLMHZYA/ ID$`HID$H Dž H HH} H HI HxHuIHN HHH9 LE1L D u6H t,HTt H H= D HxIET H AFILl IM9+ I?;LHuHH9\HLL I9 E1H twL L O4AƆz LM HfM6M9t*LHHUuKI M6M9uIL9uL I7H fP IHH& ID$PMD$(IL$ HC@ID$0ID$P HCM 1H` H H`HCH ID$AoD$8L{8IU(fHnҋ@C CHID$HHC0AE IE(fHnHXHflI](M$$I9H HtHH{H蓚H0LL9 Hs`HU HCHL9uE1H0 @ HH`L H2H L IHAu 01H IFJ HH9r HIH9}HH9hID$H5 HHt Dž 2 HyHC=HC L迈H0AH0HH9^L9UMl$(I]HtCLu7I|$HsHtaHt$juIt$H{X Ml$(HL9L9H{` tHs(MuHuI|$HsHuHuH )LL .H LL資Av Hiu H 101HL9HH14L0HI9tOH`D}DmH ]A܄ E\ E M6HEI9 L0ILH*LM9u M6M9 A~X uI~( uIFH HP Ht1HHL<Mu fMM I?[wHH LAtLDџH0D< 1H I~HHu E EtTE M6HI9EfIFH HP HH9$ H`H I~HHDu EA Eu+ I~HHMu EA M6HI9?EEe H`EtM6HI9u A jI~HHtWM6HI9Eu˿ 5I~HHtZEtM6HI9uf M6HEI9|E M6I9Fb EEAIHH9;L0I9* Hu LC H IL$ 01HC`HHfI<$vHu'LJ.EH`A HH E11PHLML1L牅AXAYDEAH H)E1LAHu HK HH 1LC0D01*H0DH`DHgAԒH0Af UHHdH%( HE1HEdH+%( u苒ff. UHAWAVIAULmATLSHXdL<%( L}ILH~3u fHnHflHEE0HtLH5QH詁HBHuLmH=HE芼H]HtBHS LK8LILC0HK(HssHs@AVH4LLHXZHuHEdH+%( uHe[A\A]A^A_]|ff. UHHdH%( HE1HEdH+%( uɸ :f. UHAWAVIAUATESHXHEHNH}HUMF H HEHE LMDmHEHu 01dL<%( L}L}(I~? dH Ls ALuLuEEE1]ff. HEAAWuuAUAVDEMHUHuH} H0D9~tHUdH+%( uQHe[A\A]A^A_]f D HAE1AWELuuPuHUH}" H0 @ 1Ϗff. @ UHA H5g HAVAUATISHL/LrdH %( H]HMLLDtLLw1uTLkI|$LtbC@K0LHSH;sXLK8sPDC1sHPH uHS(HS HUdH+%( u+He[A\A]A^] I|$L{1t̎ff. UHAWAVIAUATSDH HEL}(HLnH HEfInω fInʼnHE flDHdL$%( LeLe0)0Mub MMtRI7L,uHٵu LHO 101 HUdH+%( 9 He[A\A]A^A_]H t[HHxPHh H7H\ I HHSHI4Hx HLu1{fh HIH .IGIH IH~? HHDH fHnAFAGIFPIG( HHDH IGHt H mHHA(Ht\AoFHH A0IF(fH~fI~HA@IE tbfօ(HnmH(HIEu>HH{P%H{H{(H{`HK|JA]1ۀ AE HXXH@P H@` M H H01LLg I6H> HHDHHxHLH M E1H(11D$ff. HHL<M HL`L@ MM ~(LH5LALP)@ztÃ$Hc$HH@HHHHgqHHH fo`HD fop@foE@ foE@0foE@@foE@PIMHP`M=HHHxHLH HL9D$E@ IcH(LIHRHL, I~Hs`Hh?I9uH(ML0D( HLӉ$ HhL9" ATLHD($AVH HAWUH tH(Hhy(H ]H(H{PH{赒H{(H{`賉Hy(sLIHcH{oHHAPHI~A~FH1HQfHnflB8fDHD¸HHxH HHHfHnfHnHx1flH9XE11۾ @M~EAF\t]t6I(1Hxp^M~ IVHLh茧u"HM~ IVLh覇Hgu INH 101HUw M~ IVLhHf. UHAWAVAUATSH(dL$%( LeE1H L/HHRIIHc9 H5̸ MHHULDtHuLuMLkIL{t_{( tlHSH;C+LAVj j C*PLK DC)uH AHEdH+%( u@HeD[A\A]A^A_] D ILE1 t IHLJf. UHAWAVAUATSHHH}LmHuDeHUD} DEDMdL4%( LuLu(H IEuRHEAPAVj ATAUDMDEHUHuH}RH0HUdH+%( u<He[A\A]A^A_]HEHMu H 01LE눸^ff. UE1E1HHdH%( HE1VH5 Q15vu j j HUdH+%( uff. @ UHATISH dH %( H]HLeH1H]HtHUH5GtHUdH+%( u H [A\]腄 D UHHdH%( HE1E iH1HtHUH5sEHUdH+%( u&f D UIHAWAVAUATSHXdH%( HUHʋB; E IMHuHUuH}LHH@ gIH HLIH HEE H C M HtHH H.u HG LU01mLk(HS(L9v LUHUMLeIB(LUHEP IH IFI~IEIF IE cIEHf IF(IE(AFHAEHIF@HX IE@ IF8H8 H1HӃHx u{ HclIE8H E1HcHIU8J"II9tgIF8LJ HuI}8I}@L*r D HUdH+%( HX[A\A]A^A_]f D HMHA(fHnLhHEEAE Li(M6I9LeHMEE;A1f D yIE8HuI}@>LqU D H8 tJ 1HHvH< uHc IE@HHt"Iv@H(fc 1L q UHHdH%( HE1HEdH+%( u1̀ff. f UHHdH%( HE+HUdH+%( u荀ff. f UHHdH%( HEH+HUdH+%( uLff. UHAWAVAUATSH H $ H H $ H A dH%( HE1LD¾ H ILH脧M HHHW 1cH0Ht0HEdH+%( H D[A\A]A^A_] HLH y LH^u( HLHx It$H6tAw HLHx 試It$Huƾ HLHx 聦It$ Hu HM|$LHx L(MLLH?eIT$H( I|$ݗ HLID$HVx 1ID$LHHHusIT$H( I|$臗L HID$Hx 1詥LIt$ H虄Aƅu1IT$ H( I|$ 8ID$ LmH\LTv} UH HAVAUATSHH=w HdL$%( LeI qH ~KE1L-kw f. L LIHH8 LHL@1wHD9 HEdH+%( u H[A\A]A^]| UHH w HHH dH<%( H}H D D tH v HEdH+%( uH 1&wa| UHHdH%( HU1HUdH+%( u(HH H H H HH01v |f UHHdH%( HU1HUdH+%( u(HH v H H Hi 1nv{f UH HAWIH=u AVAUATSHdL$%( LeI I ~m1L5D L-u fL LKIHH LHH HLLHL@p 1uIZY9 HEdH+%( uHe[A\A]A^A_]zf UHHdH%( HE1HEdH+%( uH H=u wz UHHdH%( HE1HEdH+%( uH2 H= L'z UHHdH%( HE1HEdH+%( uH% H= y UHAWE1AVAUATSH(L/dL$%( LeIAEdE I EE~:ff. HH#t L1 A#tH苄H\E9uE E1 I E1HHs L1 AsH;H\E9uE I E~=E1ff. HHs L1 AsHH\E9|A I H; u~SLcE1H v @ I LHD HLIHHDHD@ P1rXZM9uHEdH+%( He[A\A]A^A_]f D E I E f I HtWu~LcE1H 8 f D I LD LHIHHDD@ 1WrM9uUHEdH+%( uhL5 H= He[A\A]A^A_]wHEdH+%( u2L= H=\ E I E-tw UHHdH%( HE1HEdH+%( uHIо Hq 1qv UHHdH%( HU1HUdH+%( u!HHq H H HHx15qpv UHHdH%( HU1HUdH+%( u!HHUq H H HHp1p v UHHdH%( HU1HUdH+%( u!HHq H H HHh1pu UHp HATISHHdH %( H]H H`1HRpHEdH+%( u%I$H߾ Hp HdH1[A\] pYuf UHHdH%( HU1HUdH+%( u!HH~p H H HHX1o u UHHdH%( HU1HUdH+%( u!HH;p H H HHP1uot UHHdH%( HU1HUdH+%( u!HH p H H HHH1%o`t UHHdH%( HU1HUdH+%( u!HHo H H HH@1nt UHAWAVAUATSHH dL$%( LeILH L]H gHtAHL5fo ff. HI%AOLLHþ 1LnHuHEdH+%( uHL[A\A]A^A_]]sff. f UHAWAVAUATSHH dL$%( LeILH L\H fHt.Lk@HÐHIuILLHH?HuHEdH+%( uHL[A\A]A^A_]er UHl HAWAVAUIHATSH H dH%( HEIE Hc L0 L( 1m H[L IH`Hff. I~AvIIE L0 2 LIwI~AvHڹd INIMHHm 1xlL9uHEdH+%( uH [A\A]A^A_]qf U HAUATLeSH8L/dH %( H]HLI Hp ̀L 1Hl HkI LHx 虀L HHl 1kI Hx H+p xIfH*H H߸ ^<j okHEdH+%( u+H8[A\A]] D HfHH H*Xpp UHAWAVAUATSHdL$%( LeL'I$ L0L9 HE1L-a_ E M6I9toM9 uA ~L]I HIHd Hk HHD1jA M6DxI$ I9uff. HEdH+%( H[A\A]A^A_]f D L]L HH1jAt%I$ M6L9tM9 u1 Hٺ H=1 7I$ M6I9cM9 nff. UHAWAVAUATSH(HdL,%( LmID E H HEL5j HEL=s ff. Hu1eSH];:ulHAL IH{j L1 iHMnyH|AuL HEdH+%( umH([A\A]A^A_] L H=$ D HEdH+%( u'H(L [H=и A\A]A^A_]m D UHAWAVAUATSHdH%( HEH ~pIIL= E1LL LHH 1ILKLC g H[i 1 LgH{L΅IE D9 HEdH+%( uH[A\A]A^A_]lff. UH HAWAVAUATSH8H}HH=h Hc dL$%( LeI H E1L-h HEf D HEH H J 8H&MHEH I# @ HXLL L1If' L贄HuLLH; 1 fH}[IL9}oHEdH+%( u4H8L [A\A]A^A_]uHHq; LNfk UHAWIAVAAUIATSHc1HHH7dL$%( LeMH Hu HHHPHt1fx I<$LmE DuEEu3HEHHHEdH+%( HH1[A\A]A^A_] A|$ uHHH} 1ae HYu Hf 101 H9u IAH 01vjLjff. UfHAUATISHc1HHID$dL,%( LmMHuI4$EEE MHuHE襼Hto BH+u HHH@HtHH}LHUdH+%( uaHH[A\A]] HYu ٿ H{ 011f D H1u I $AH 01m1Di @ U HATSHL'dH %( H]HL H{ ubHLGÅx)L1gHEdH+%( ucH[A\] D Hu H 01f. Hu H J H H81<cph U1HHdH%( HE1VH?HUdH+%( u1hUHAWAVAUATSH dH %( H]H H9tgIIHu HI9tH{uH0 usLIH H t?L0 HI9u 1HUdH+%( He[A\A]A^A_] @ HLHHpL@ L1LK L HH ZYHuBf. HI9t{uH0 uHŎu Hcc 01@Hu K H0 01f UHAWAVAUATSHHdL$%( LeILc E H 1LH Hb aE~@N<H L55 L- f D LL L1H`LL9uHEdH+%( uZHL [A\A]A^A_]鵬 D HEdH+%( u+HLH 1[HI A\ A]A^A_]f`e UHAWAVAUATSH dH %( H]HH7 h H L HSZ/D L D LHH HHHS㥛 H HHi ʚ;H)HHHHLH HHHH Hi ʚ;II)RH H}L@ Hya HL@h@ L1DHHMa 4DE HHH3a 1 _DȧHLHPH 1AUATDL^H HEdH+%( urHe[A\A]A^A_]f D HEdH+%( uNHeHٺ [H={` A\A]A^A_]f. H<error> L@H@ cff. UHSHHw dH%( HUHJc[Åx HEdH+%( u)H]f D Hu H" 101G c UHSHdH%( HE1H uUHH Åx HEdH+%( uYH]f D Hu Hү 101ϼ D Hu H X H H81?]xb UHAVAUAATISH HL5u dH%( HE1 H_ A6HEt[HtHڸHH9u AD$A61H3 1 1HUdH+%( H[A\A]A^] D 1HP H PH9t HX H XH9u/AD$A A6Hٮ 1荻y H`teH `H9t HptKH pH9tHxt"H x H9z ff. @ ED$b` UHHdH%( HE1H u HEdH+%( uI6_f D Hu H 2 H H81<[HEdH+%( uɸa` UHHdH%( HE1HEdH+%( u1-`ff. fUHAWAVAUATSHH dL,%( LmIwH 蚚H ICf f f Dž\ LL.IH f{ A yDs Hs HpLH?HLoIA \ H]I HF MIHu I H 01-L%HEdH+%( HĈ [A\A]A^A_]fu" D Dž\ Dž\ H`f LH)`u l u1A \A H`]N LHL>;^ff. UHAWAVAUATSH H $ H H $ H H HH(dH%( HE1H0H9D H`IAHH8L0 @ H8LL~fHH0H9 H8$ D-H$ A~ fLDLzLL9Y Hnel.kallI9$uHallsyms]I9D$`H(1DDž0 赯H H HH(H9 H@LH8 FLDLbLTI9 H@oHHLHHLH f؉HXHHH(H9sIH8 DȀH u%A~ JH8~9f Dž0HEdH+%( uC0Hĸ [A\A]A^A_] H8,< Dž0 [ff. @ UHHHWwdH %( HMHO H?uHEdH+%( u'1 D Hu Hڨ 01,[ D UHAWAVAUATSH H $ H H $ HXdL,%( LmIIHسH߾ HW H1OHzH HDž IE1HDž fLzH_ x.Hxu t߀x.u.u tff. f1HH51W uHI9r-HIw yH HHHHHKH HβLHH H 1>HyHH| Dž HyHtcx.Hxu t x. 1HH5NV uH9CmyHu H@pIHc赟HHAH HHHHHH2fHxHtsx.Hxu t x. 1HH5~U 1uH HHHH% HFH xHu HIuLlxH LtHM} LH c I<$E1貌HEdH+%( HX D[A\A]A^A_]f. .P A . H(u H1AHz 01aL9tMt%HKHYLlH;HGI9uHG,H~u Hp 1A01LsH~u IAH H 01˰VHAs벐 UHAWAVAUATSH(H}H? dH %( H]H HE L5/ HEHH@ Lc(HHE LxHR 1H߾ PE~3O,H L%k% ML H1IPLM9uH 蒜HEHEH8HE9 fH@ wH5, H螙tBHEdH+%( H([A\A]A^A_] H H1 PHEH5! H Hx@HEmtHEHt H5a H8H@KHx1 HsaHEdH+%( u'H(Hٺ{ [H=k A\A]A^A_]սT UHSHHOdH %( H]HHtRHCHS H)H~jHHHCHUHx u HPx1HUdH+%( uQH] D H {Hu xHt!HHHI t HUS D UHATSHHWL'dH %( H]HHt]HKHC H)H~yH I$ HCHx u1HUdH+%( uUH[A\]I$ HI$ {I$ xHtHHHI t/Sff. @ UHATSHdH%( HEHL A|$! HWHHtbHOHG H)H H ID$0HGHx u&1HUdH+%( H[A\] ID$0HID$0ːIt$0 +wHtHHHHЉЅufHa|u A7 H ]O H> H81LhR UHATSH HOL'dH %( H]HH HS HCHH)H H4HHCHuA|$ uaH)H ~ HHCfMHx uI~EI$ flp 1HUdH+%( H [A\] HHuHC fH~HfHn먐{Huغ uHuiHHKx uuHu7{Hu uHt0HHHI t e @ HS ~ ~M$f D HHHI uPHEHHE{ UHAWAVAUATSHhHOdH %( H]HH HCHS H)H HHHCHUH3~ | H` HKH HS HCHH)H; H<HHCH}~ # H)H HHHCHU~ H<RH3rIH E1H} L]I LmLp HKH HS HCHH)H H4H;HHCHu t HHuHCHH)HY H4HHCHu t HHuHCH)H+ L,HHCLm tILmAE? pIHc菕IH IE?H LeMLxIff. @ LkM; HCHS H)H IT HHCI$H; t I$HI$HULJ?IM9 M* LILeL[HcLxLS H f HHCI4LH)H% I HHCH tHHHBHL9rLmfoEIILuAGHEIGHEI9LmHHML( H0 1HUdH+%( Hh[A\A]A^A_] @ { LqHHHHI xVHUHB?HI9Y IId @ HHHI tHLmL<Z LLm<f{Hp 9qHuH;HK Hup{Hu qHuyH;HK HuS{Hu pHt HHHI Hf D LmH; @ HS HS HHHI l D HH}HCHHUxHHULeLxI{Hu !pHtHHHI HU{Hu oHuTH3HK~ ufHu9{Hu oHtHHHI 7HUH3'HS +HHHI 1JHEHHEHEHHE`HEHHE#J UHAVAUATSHHOdH %( H]HH HCHS H)H HHCUHx upALݗIH HsHtXLsHC L)I9mLLL.KD5 HCHEdH+%( HL[A\A]A^]f D ʉU뉐{LH_nI9tHHHI tL9E1f D {HuԺ $nHtHHHI űUBIf UHATSHHdH %( H]HHxp9L#HID$pHHxp t1HUdH+%( uH[A\]øH D UHATSHHdH %( H]HHxh8L#HID$hHHxh t1HUdH+%( uH[A\]øeH D UHATSHHdH %( H]HHxX58L#HID$XHHxX t1HUdH+%( uH[A\]øG D UHATSHHdH %( H]HHxP7L#H:ID$PHHxP t1HUdH+%( uH[A\]øG D UHATSHHdH %( H]HHxHU7L#HID$HHHxH t1HUdH+%( uH[A\]øG D UHATSHHdH %( H]HHx@6L#HZID$@HHx@ t1HUdH+%( uH[A\]øF D UHAWAVAUATSH8H}dH%( HEHGH] HO HWHH)H HHHWEHz H|hHEH EčxHhHEHtlE1E1uO HEELN,HEL,HPLLHPI*LGd45;]smH} IHuH}5H}5ff. fHUdH+%( H8[A\A]A^A_]f D ȉEf D HEHMH H HMH 1 Huĺ iHtHHHI aHEHuHH EDf. UHAWAVAUATSHHHOdH %( H]HH HCHS H)HW HHCUHx v { Lm LH HEL5# HEEL= HCHS H)H HHCUHx tEȉEHTIH UHL1Leu LLTxoH5G L蚇u HU Lr3m HKHK{Hu hHSHHHI =LRff. fHUdH+%( HH[A\A]A^A_]f D ʉUHju H " 01ߜ1 {Hu dgHtHHHI iU H1Lc8H 1U`BUHAWAVIAUIATSHHHMHuLELMdH%( HE1 H HOH HGHW H)H <HIF}Ix tω}u+1HUdH+%( HH[A\A]A^A_] H9dIE H E E1V H5> H聅 H5> Hj LIF1H>1EA9r LHH LIH IH}1HH_ - IE HUH5q HJڄB 1L3HM( 1LHM4f D 1LHMf D LX0HP0A\$HEtfIE H<H/0HuI} 0HEIE + @ Hu dHtHHHI uɋ}1ff. fHM? UHATSHHdH %( H]HH H H L L Aąu HH t"HEdH+%( u1HD[A\] Hfu HJ 014 ?ff. f UHAWAVAUATSHHOdH %( H]HH HSHC H)H HHSEHz H aIH uą IIE1f EAI A9snIOIWLHMO MG HIGH AuHHeu 1A I 2H_ EA9rHL@ 1HUdH+%( H[A\A]A^A_]f D ȉEąH\eu H 01蟗1 ME1tXff. A$1ۅ~ f D ID$H<H>-A9 $I|$AI &-I|$ -D;mrL-4{Huĺ aHtHHHI u͋E(1<ff. f UHAWAVAUATSH8HwdL<%( L}IH^ IGIW H)H <HIG}Ix H^HEHL u IIHEE1HE D IGIW H)H HIG]Ix tˉ]ĉH蕉IHO IwH MOIG L)H9& LHLLM LMILI_M$LuID$Ht[AIA9 IHAAHu _H HHHI uI$ 1ۅt I>I*I~*;]rH}* HUdH+%( H8[A\A]A^A_]f D AHHHEb_LEH9HHHI Lz*I$ uVf. ]k ω}1 @ IHM H8 1E D AHu ^HtHHHI } 9ff. UHSHHWdH %( H]HH HK HCHH)H H;4HHC uuOH)H HHC u9fnMfn1fbfG`HUdH+%( H] @ Ήu몐 @ {Hu ]HuaH;HS Huz{Hu ]Ht$HHHHЉЅwff. UH;F D HHHHЉЅCf D 1q8HK HCEȉEg UHATSH HOdH %( H]HH HCHS H)HO HHCUHD@E ' HSH HK HsHH)H <2HHs}E HH)H H<2HHsH}x HH}H H)H H2HHsHUx tHH ƀ 1HUdH+%( H [A\] ω}܉ c ʉUf D {Huܺ [HtqHHHI t_ f D H 7 @ {Huܺ L[HtHHHI uUn HMHSp@ H Le{ LZHtHHHI RfHHMHSx uvH HuS{ LZHt HHHI HHUd @ HK Hs HK Hs&ɉM8HHM{5ff. UHAWAVAUATSHHOdH %( H]HHN HCHS H)H <HHC}Hx HWIH^ Eą1 ME1 HKHC H)H) A$HCHx t A$A$HSH/ HKHC H)H H ID$HCHx t ID$HID$HSH! HKHC H)H H ID$HCHx t ID$HID$HIHtnH(LID$#I|$ tQEAI A9/ HSH{ LXHHHHI L#HUdH+%( H[A\A]A^A_] {It$ XHHHHI u D {It$ WHHHHI dω}f D {Huĺ WHtHHHI )}1f H 1L 2f. UHAWAVAUATSH(HOdL,%( LmIH> IEIU H)H[ <HIE}IE x xIH Lp 1 IU IEHH)H 4M} HIEAvA t AvIEH)H HIEAA tAAEăI9 LIFHtnIMHjA}Iv UH M} IMA H A} LUHt{HHHI tiEAM1ۅt#ff. @ LIxS;]rL HEdH+%( H(D[A\A]A^A_] M} IU HHHI a D ω}ĉ &HWu H}- E1016]A}Huĺ THD HHHI . A I HE E11L6L9u M6I9t@9sHLJA9 t_EtHuLArI M6EI9u9u E1EhHWu H, 01T> LLHUHUH5~, H HHMsHUtHMI H R EA 9sE{LuI Dj @ }}E1M.AFAFa @ UHAUATSHHWL/dH %( H]HH HKHC H)H A HCL#A|$ $ HSH4 HKHC H)HZ A$ HCL+A} L HSH^ HKHC H)H A HCL#A|$ d HSHt HKHC H)H A$ HCL+A} | HSH HKHC H)H A HCHx 1HUdH+%( H[A\A]]f D A HSA H{I$ QHHHHI f D zf D A$ HSA$ H{I QHHHHI u @ A HSA H{I$ PHHHHI FwA$ HSA$ Hr{I jPHxHHHI ] A A M {I PH HHHI *+f. UHAWAVAUATSHHdL4%( LuL7A~ HOHH HGHW H)H HHGUIF@E1HEIH HHEDHEHEE ff. HKHB HS HCHH)H H;4HHC ut ΉuHCH)H[ D<HHCD}Ā tAD}EI} wIH& fnEfAnHsHx fbf@H% L{HS L)I9 LLOD= LCH}LrtMAD;e1E1H}SLyHEdH+%( HH[A\A]A^A_] D LADD;esHKH{Hu MH H;HK , H| {Huĺ MHt%HHHI tE1<f D D}H; @ H{L_MI9HHHI 뱐HS 8 HHHI uCf HPu Hw 11ۋ01UHu LHt!HHHI t D Hx .EȉE!'EȉEff. UHAVAUATSHHOdH %( H]HH HCHS H)H` HHCUHp@- 9 HKHo HSHC H)H HHSE@ H<HIIH EЅd ME1T f. HKHC H)Hy A$HCHx t A$A$HSH HKHC H)H1 AD$HCHx t AD$AD$HSH HKHC H)H AD$HCHx t AD$AD$HSH HKHC H)H AD$ HCHx t AD$ AD$ HXID$HtuHFID$HtcH4UID$ HtQAI(A9 HSH{ L6JHHHHI UЅt/I]E1H;AH(;H{2H{)D;erLHUdH+%( H[A\A]A^]f D {It$ IHWHHHI e<f {It$ [IH[HHHI %@f {It$ IH_HHHI Df ʉUf D ȉEf D {HuԺ HHtHHHI Un {Huк HHt!HHHI ff. HpEm1ff. @ HL 1Sd# @ UHAWAVAUATSHXdL$%( LeL'A|$ HOHH HGHW H)H HHGUM$H ID$@LHE#=M HELuE1HEf HKH HC HSHH)H} L34HHSA~ ut ΉuHSH)HO HHSEA~ tEȉEċM }ĉMIH oIH HsM DxH> HC L{HIL)H+ J<>IML$L{I|$A~ tHI|$L{IL)MLEH9 LLHUHUMLEIM4 LsI D}HsI$ M)M9 LLMOL{ oIHu L-M'H}LF AD;mHLuL|J1f. HUdH+%( v HX[A\A]A^A_]f D {Hp tEH5 HMHsx t ID$HID$ML$H {LHULM*EHULMH9tHHHI M w?ff. f IH)Ѓl | ff. HsD}I$ H LC Lsqf. LALD;mHKH{Hu QDHu^L3HKA~ tEȉEH {Huĺ DHtHHHI u(f D L3 HHHI tLuE1 LLHf D H{LCI9HHHI x Luf. IyI ID HI)B 1H~f D HHHI LuIf A D1fAT5 D HEu Hn 1017x1 Hu BHtHHHI Hx EȉEf HEu Hm 1Lu01wf D A AD HC HC b fUHAWAVAUATSHXHWdH %( H]HH HK HCHH)H H;4HHC u H)Hp D4HHCDu DHHMjHEH: D} AcHMHI A9AFAE HsE1AD$LmEIE Hd LKHC L)I9 H}LLLM5LMMLKHx ] IEA/ A EtHMAUA A}<? fA}~ E E IM(H IE0H 5 tIMXH ^ HKH HCHS H)H HHCUHx tEAƅ ȉEHI HtrDUEu Iŀ AD;u# HsD}E H{HuL?I9HHHI f. LmAEI f L E1H} HEdH+%( HXL[A\A]A^A_] ΉuWf D ADul @ HBu Hj 1Lm01CtAEI pH<H{HÀ <uIf HuHJT&JT MHH}DfD DU`HDUI LmE ILeEL{M HCHS H)HIHHCIU H3~ t IE HIE AIE9% MtELLeLmL[H{ .fIHHCH~ tHHAHE9HCHH)H { Le=Ht"HHHI ff. DU3 {Huĺ =HHHHI Lmzf D {Hu <H} H;HS 2 H {Hu <HtHHHI uPfDuH; @ H?u HBh 1Lm01q{f D HHHI mHE D H1?u H11Lm2H-h pq( HMBT!BT FH>u HCh 1Lm014qHMBT!fBT LmLeLmOHK HCEȉE D UHAWAVAUATSHdH %( H]H6H IHH Dr AUE L Mff. I Ht2I $L9t)A fHL9t; uH A Iǀ uEu5I @ H8H{HÀ 8uLHEdH+%( u8H1[A\A]A^A_]Lk(4 kH mzf. UHAWIAVAUATSH(Lg(dH %( H]HM ED$Mt$L- EC LeML}9 @ L1HHIĀ H [AL$ I$ H߾ 1HS }A$ t Hٺ H=D }A$ M$ tDE1+ K L H1I E;$ sEtH, [Hٺ H=| G}fLeL}AT$t1I$ H6H{HÀ 6uLIG( HEdH+%( uVH([A\A]A^A_]KIHdHEdH+%( u'H(Hٺ. [H=d A\A]A^A_]|d @ U HAWAVAUATSHXL7dH %( H]HHE Ic~dLu}YI H HKH HCHS H)H HHCHEUx HELu L EA E1L}HHHE HuLHP#x9H}A LH@HMd5D;mshHHEHuL_uL4H}H 4HUdH+%( HX[A\A]A^A_]ʉUf D 1LHMH HKH HCHS H)H~HHCUHx HEI E1L}O HHE HuLHP"H}Ao LH@HMd3D;msdHHEHuf D ʉUlf D {Hu 5HtHHHI HU1LHMLC H M9 LyX Mt& H5 LLE1LE E M,HEE1HExf D HEADMH FL8 HCH)HHHCU@tʉUtt 9U^ HEIH B8IM9v HsHtMHS HCHH)HD HHCHDMx@MHEH FL8 O{Hu M)4MHt"HHHI %ff. HUHsx@tʉUHEH BT8 HuS{Hu M3MHt%HHHI ff. @ HUxHS {Hu c3HtHHHI sU H5 LLELC M9r1>HCH HSI)IHHSEHz tȉEHME1L} u: @ H LLHP1 LA0D;esPH?HEIHuwHH V01HY5u H*_ 01gP1LLeE1VHMH EDxLsM HSHC H)HAHHSEHDBEtȉEHMLHH DM9IUM LSLK AuHHCLH)HA HHCMEtɉMELH9r1u { L-1HtHHHI -E1{Hu 0HtHHHI EI f. UHcƺ HHHdH %( HMHH T HEdH+%( u ff. UHcHHHHdH %( HMHH!T HEdH+%( ui f UHcHHD HHdH %( HMH HHUdH+%( u f. UHAWIAVAUIATSHLwdL$%( LeIM HOHw I H= HH)L9HsfHHH)L9r H9HHFH9r6I<LLMe1HUdH+%( ufH[A\A]A^A_] LHIHtFIEIMI] L/HHHHL9LEL뒸 | D U HATSLeLHdH %( H]HE xUH LHߋ Ex5H HH xH HH HUdH+%( u H[A\]C U HSHHdH %( H]HH /tHUdH+%( H]fH HH uH HH uH HH uHEdH+%( u HHH] H off. @ UHAWAVAUATSHH dL$%( LeILH LH L5ADžxCH H- D Hp]S HsLIHADžxLHuLsAHEdH+%( uHD[A\A]A^A_]ff. f UHAWAVAUATSHH dL,%( LmILH L H LeAąx]H HG D H\H{IDg`HsLI LH{AExLHuL@HEdH+%( uHD[A\A]A^A_] UHHdH%( HEHH ~! t'HEdH+%( uXH0 f Hq0u A H m HN H81 HEdH+%( uɸff. UHHdH%( HE1HEdH+%( uH H ff. UHAWAVAUATSH]HHXdL$%( LeIH=uW HE HE HE p,t,HUdH+%( HX[A\A]A^A_]f. LmH}L0uHu L;AHEHEE HLADž LLHUADž H HEHE LhHEHEff. Iu LADž LLADžxmIE Hu LMuHEpADžxIHE1H?Hu" @ HEHIH?HH9sg LL'ADžyHUHt(HEHRHXL$ H;HI9uH}D}ENf. HEHUIHEH9E1ff. U HATISHdH %( H]HHp mx1HEdH+%( u:HHx L [A\]>f D HUdH+%( u H[A\]ff. UH5 HAWAVAUATSH8H}H=y dH%( HE1HE HE eH HLmLe" H5: LADžt]Hٺ LLJLuHALCHHEdH+%( uUH8D[A\A]A^A_]f. Le1H5 LLTtLuH} LAAff. UHSHdH %( H]H%T EQ HxDHu H߉ExHu HHUdH+%( uH]f D <ff. UfHAWAVAUL`ATISӉH HHh 8L@dH%( HE1)`h1)p)SI$ L8L9u M?M9$ 1 ISA I LI HyAH"(u H# 0 1eZHp9HEdH+%( H D[A\A]A^A_]Ðh 1L`RHH0HHL8L9 (ILLH HI9 { wC oK LL~ )oK H)oK0fHnH fl)oK@)oKP) oK`)oKp) o H@)0H!9AH&u HP 0(ID$H/ IT$8 H IL$9 M|$ f Dž LLfuAƅ Hc >EH(H ID$A1҉IcH4HHP L 8A= " HH@ H(H8 L Hf HD H (u McKD L$M. H 1=PHH@H Ht3H $ H@HPDHPH8HXЅuHHH8AԅH 1HOH+CHCAV LHcm A= L H1҉OHH(H8Aƅz HH(AoD$ @ fHnfHnM|$ flHHE1AoD$ fH0L`Hc@Mfo - EAoGHHxHP1)`HEHDžp HENH`h LHpAExBAoD$1҉E1fofsffH~bNd 1ONID$HF#u HG 01U+L@I͉ @ HDAtvH %u IcHL$M H 1 MHHH8IE AԅP 1IMI+EIEAV LHc3 A= UL@ H$u H 1 HF H81/H D<ZHl$u H 0 HaF H81H@DX<\H!u HML 01'THH(HH8H ($u KD H HLH{!u 01SH31ZL&Hk(H#u Hk HLH:!u 01SIu 1L AC UHHdH%( HE1HEdH+%( u H, UHAUATISHHdL,%( LmIt HUdH+%( u?H[A\A]]f D HEdH+%( u HLHL)[H5/ A\A]]}ff. f UHAWAVAUATIS1HdH%( HE1 D EH߉EtHHuHu LmL2x~ff. HtHH| Hs LxGL;L LLIƍ@@Ex MAVLLJ,yf D HUdH+%( uH[A\A]A^A_]f1g UHAWAVAUATSH(dH %( H]HCH! HHI: HEMfE1HEAu= HMELHߍQH+ AI E;. LHxiIt$ HuSIt$ Hu=DHM|LHu HH@@HMEjRLE[EHUdH+%( u H([A\A]A^A_]f D 1ʸ UHAWAVAUATSH(dL,%( LmIfLH HLI HEE1HEAus HMELLQH0* L{L Hu LHÍ@@Eox]MčSLL)xHAE;&smDHLL{LG Hu LH@@HMEVLE#EHUdH+%( u H([A\A]A^A_]f1θ U HAWAVAUATSHH8FdL$%( LeIHuE Hu HE t M4$HEHEM9uR f D EAULHH( A I HHxvM6M9 UIvHxWA Hu H߉Ex8LOHIHuĺ HIō@@EOHUdH+%( uH8[A\A]A^A_]Ð1W UHAWAVAUATSH(dH %( H]HH=n H HI & Iut H IUxIuxHuLbH9 Luo MAWLHf' Ml$L LHIǍ@@ExUMAWLH 'x?IT$LbH9Ut0M,$L LHIǍ@@ETdHUdH+%( uH([A\A]A^A_]øf UHAWAVAUIHATSH(dL$%( LeI[Hu LE I $I9u f D HI9 H9 u닃 ~L H EMULDLHuĺ LIƍ@@EZxVEAVLLH%x=Hu L,x(Hu LOff. @ HUdH+%( uH([A\A]A^A_]f1 U HSHuHdH %( H]HE@ xMH5u H%HUdH+%( uH]If UHAUATSH dH %( H]HHPxlLTL-HL HIč@@LxLAT$LHp$HUdH+%( uHĨ [A\A]] @ UHAUATSH dH %( H]HHP@xlLL}HL HIč@@LJxLAT$LH#HUdH+%( uHĨ [A\A]] @ UHAUATSH dH %( H]HHPxlLLHL HIč@@LxLAT$LH#HUdH+%( uHĨ [A\A]] 4 @ UHAWAVAUATSH H $ H8 dH %( H]HHXL%/u HIAD$TH߉ L HIǍ@@HHH AWLH"xsAD$TE1, AVLH!xFIE9|$T~\I$ N,LHH HIƍ@@yHUdH+%( uH8 [A\A]A^A_]1 UH5 HAWAVAUATSH8H}H= dH%( HE1HE HE UOHtXILuLmL=u @ LHt\L LL4H]HH LHEdH+%( N H8[A\A]A^A_] : HHt x HoHt tpL=u I @ AE tWMIA tLqAE L9t1ff. f. ALHuAE uf D HhH}Hu Iō@@E:xNMH}HAU H}L x HX D H}LWff. f UHAWAVAUATSH(dL$%( LeI&?H HLHzxnD E HEE1HE$ D MAVLL x:ID;;siHCN,L9Hu LIƍ@@E yH߉E]EHUdH+%( H([A\A]A^A_] Hs LxDCEthHEE1HE& D MHuAVL x?ID;{s5HC NLLE{Hu LIƍ@@ENyL5ku L+A~$~^E1 I M LILH I LLIE9n$sHs LKtqHEE1HE* D MHuAUL mID;{s:HCN LLMgHu LIō@@E:y)AV$ E1fL LHI HIE9n$ff. UHAWAVAUATL% S1H(dL,%( LmIE ff. H dHHt/H;Le+tHI~H߃EcHHuHu L@8 EM ff. fHcHH, H;H5, *tH~Hst L HCxHSxLuHUL`H9 fHMELLQH( M|$L LLH@@HMEcx_HMELLQHxCID$L`H9Et\M<$L8 LLH@@HMEPHUdH+%( uaH([A\A]A^A_]f1 @ L;L LLIč@@ExMAT$LL*rkff. UHHdH%( HE1HEdH+%( u1-ff. f U HAUATLmSHHXdL$%( LeIHLudE1LHMк LMFLt HUdH+%( uIHX[A\A]]LHE+EHH9fHA u HH6 101>]ff. f UHHdH%( HE1HEdH+%( uɸ& f. U@ HAUATLeSHhdH %( H]HL%uZLHuHߺ E@ IxMAULHQHUdH+%( uHh[A\A]] t @ UA L~ HAUATLL@SLH dH%( HE1\[LLqD1t)HUdH+%( H [A\A]] Aٹ LLI5 ZLLD¸ u L1AL85 ZH8H0L x0H0 12H0,G,3)-ff. f UHAWAVHEAUATS1Hh}HudL$%( LeIHEuH}a E<$EA EDME1DUD]ELu @ E; E;V E;^ EA;F IvH}D|DUDMj%DMDUD|uIvH}J%DMDUD|u_Iv H}*%DMDUD|u?E9tKH}P1HUdH+%( ufHh[A\A]A^A_] D AI(E9HMEKHfoEHU foEHP @A$HEq UHAWAVAUATSHHdL$%( LeIH HHHH H)H9tH H$ H9u% H)H E HE1LuE E AŅuo AE9t_LHDQ3tUt"E1 H߉EAH( OD;eErHUdH+%( $ He[A\A]A^A_]fuĺ( HH ^u&Hu LU HuL<UgtHEIE1HE f. EčQLLH'MGLLEHu LH@@HMEþHMLEEčQLLH/MG LLEHu LIǍ@@EjLEMAWLLUwAI(A9f LL KIu L2Iu LIu Lս DHL<MGLLEHu LH@@HME葽HMLEq @ HL QH Uf HSHuHXdH%( HE1)E)E)Efo }H})Ex'H}1HEdH+%( u-H] D Hu H/ 016 UHHdH%( HE1HEdH+%( u E1:e D Uh HHdH%( HEHH9t,ff. ff. @ H HH9uHcGH HHHHUdH+%( u UHHdH%( HE1HEdH+%( uIȹ x UHAWAVAUATA SHH H8HUdL4%( LuISR u-HEdH+%( H8[A\A]A^A_]f Hc E "HEIH UHsDA1-IcLDHW { ( HS HЃ f' H A uHAѨuAHuAHL}HA Eff. DLEDHLA։ xyAMA tm HHH#C HtVfuqH A uHAuAHuAHIHA Evf D 1H}UUmf. E1f D H}D E1 UHAWAVAUATISHH H dL4%( LuAրx# a DhH0DH D(p HEHH8H) HH1A $ 1H H}IL$H1H bIL$H1H GIL$H1H ,H DLH lOI$ x t-1HUdH+%( h H [A\A]A^A_]f D Hٺ H= AIt$ H H H Hf 1҄uHʨuHuHA I H ALE H H HfF H A uHA֨ HAV$ H u HcҾ HHH HHH1ANLIt$ HHH HmH D HxKA DDBH5 u IcHf HHD Hƾ HH1.D AHA UH H ] D E1 AAVdHcҾ HHHK u HH HH1AN @ E5 U HHdH%( HUHPERFFILEH9t"H2ELIFREPHPERFILE2H9H9 HUdH+%( u[ff. UHAUATI1SHHdL,%( LmA1D'h HDH HPERFFILEHH9 HPERFILE2A$ H9 H2ELIFREPH9 AD$H H HCHh HH fLkHCHAEoCH1AD$ AoEAD$0oC(foAD$fsffAD$HUdH+%( H[A\A]]f D H{1LqtuA|$ OHCLkHHhXnfA|$ LkH\ L3HCHt[HCH;fCHAEHKH$ Hat H\ 01- @ *f D L L!Off. @ UHAWAVAUATSHHX L dL4%( LuAA|$# E|$H H% HS@H fDx H` H DLLHDž Y H HHHPERFFILEH9t{HPERFILE2 H9t|H2ELIFREPH9 CHHEuh1H AD$ HUdH+%( g HX [A\A]A^A_] D Hھ kot { tH L LLɱyL-bt Au H 1+A|$ ZH`DH@Ds { t A|$$ H} HpH( HE1HxDH1Iĉ#1LE LH1 H@ HDH { tʉHtH H@G HH D8H { 1D#H1HH IH^ CLA HP LHHxAą HH1D"1 @ H D1LLAD9th LDMH { t LfI|$CAaL- t H5 1Au `) H1D!9%DHH0 H duFH0 H fH ^Hǃ Hzt @ H" 01(, xf. HPHHHPHHHHHr D H D @ Ht IL$HM! 1012(Ht IL$H! 101(Ht Hx H " 01'Htt H 101' UfHAVAUATSH@dL,%( LmL( )E)E)ER HVHHzH 3 H t H H HKH HVLuHEHUVL1HHUAąu;HCHt8A8 t-H t { H9u HL @ ALmMtCAUI t,f. H?H{HÀ /uLfHEdH+%( uuH@D[A\A]A^] Ht H 101G&E1HKH 1THt H 1A01&|ff. f UH HAUI ATSHH(HOLdH%( HE1RHSLcH wOH C L H HLHUdH+%( H([A\A]] D HuZHv L1H{HIƮHH LHHLHEHEf. H5 L1zHL]HKH L1VHL9 @ HKH H jf. UHAWAVAUATSH(L"dL,%( LmIM I}1HH HLAUA+U H߃ UoEunAM DuE1IEt" @ ODD1HLI课M9uHEdH+%( u3EH([A\A]A^A_]ÐH舫HIHJEkff. UHATSHHHt dL$%( LeIԀ8 M% I<$H Hs?IH HCH w3Ht~CA$H 1HUdH+%( H[A\]ÐHuH{qHH I$ 8I$ f D HAt HH0CI$P cH{:I$P n D I$ ;H{I$ F D Ht H 101'"#f UHAWAVAUATSH H $ H H $ H(H D~x# dH %( H]H Dhx x H0 D*HDL`HIMI)LHH x urM9 H0 H ^DHUdH+%( H( [A\A]A^A_]f D 1D 1DHp >f D L k&~ HL9rHmt H Ho 101 gfHx:AH H!t H HK 101` Ht H H 101> UH HAWAVAUATSH dH %( H]Hv H ICf f f E1HC$LHHXIH f{ A yDk Hs HpLH赥HLZA E H]I H6) MIHt I H 01 L,HEdH+%( HĈ 1[A\A]A^A_]f D fu D A D A D H`HXf H)`-u l u-A D A H`D LHLڤ# UHATSHdL$%( LeI0 H5 H9HHFLB H5L LH9HF tk H52 LH9HF tl H5 LH9HFHuZHt @ 1HUdH+%( uBH[A\]fHt @ Ht @ Ht @ 봸 @ UHAUATSHdL$%( LeI H54 H9HHFL0 H5. LH9HFI tfLH5fB Ltp H5 LH9HFHҺu^Ht @41HUdH+%( uIH[A\A]] Ht @0 Ht @0 Ht @0 뭸 @ UHAWIAVAUATI SH(dL,%( LmIcH\GL HH@IWHEHCHCHCHCHC I)щKh H9! Mg M IHFI$AoD$IFID$AFIN IF(Ht#Q(f D q(9t BrvIN I~KA|$) IFID$ IF0tRIT$8I~`IF8 H H AD$0tIFh tIFp I $It$0t HC~ELsfHnflAL0IG L`PIGHMg IGI;Hǃ LkxHCl HEdH+%( H(H[A\A]A^A_]f. Ht? t AD$0IFHIcD$@IFPID$HIFXI D rIF`HHwEIT$8 @ Ht H 101IWI 薿f D UHAVLwAUATSHH_dL$%( LeIL+HL9u G @ IHSfHnH{flIUL*:H{`HL!IU LM9uI\$Mt$L+HL9u If D IHSfHnH{flIUL*:H{`HLIU LM9uIXL色HHt2HILkLLH$)LLtHuHEdH+%( u H[A\A]A^]Nff. UH=̋v HHdH4%( HuH5< uHEdH+%( u Ht H 101!ܽff. UHAWAVIAUATSH(EdH%( HE1H HG` Hp fH*YE f(fTf.v3H,ff(%/ fUH*fTXfVf( ٶ f/ H,I~XMf`IM IELMHEnEH}I AoGPfofsffI~I9rIF`Hu ff. HHH8HH@HxHPL9HBH HuIfIGLAG H:.MXHEdH+%( uTH([A\A]A^A_] \H,H? D HfHH H*X{fL1x UHATIH~SHA^ dH %( H]HHChI$HEdH+%( u H[A\]蓻 UHAWAVAUATSHHXH(dL$%( LeIHG ;HtKILk`IGLMHEH}LIAoFPfofsffH~L9s0MuHEdH+%( H([A\A]A^A_]f HC`Hu:}ff. ff. ff. ff. f HHH8HH@HpHPH9HBH HuI~fIFLAF H:,M D L1Lff. UHATISHH{HdH4%( HuHHChI$HEdH+%( u H[A\]ff. fUHXHAWAVIAUIATSHH(dL$%( LeM荭H IM IGLL}HEH}HMLLILUIBIJH9t@ff. HP8IMtHPhIU HtHPpHMt;HPHH I$H9uMzHEdH+%( H([A\A]A^A_]H H9uMG D M IGLMHE<H}HML1IIFINH9tmHPhIU Hu %f H H9tMHPhIU HtHPpHMtHPHH I$H9t$HPhIU HtHPpHHPHH I$H9uMS ff. fHHHH I $H9uMLMwMh 1MH1LIIEIUH9tHtEHHpH Mt+HHHH I $H9tHuff. fHHpH H H9u|MuH H9uje D UHAWAVAUE1ATSH dL4%( LuIHXH7 IMI0E1H LeLMILuI0Ҫ1IH L}II|$0質1IH$ LmHxLpII0E1脪HH LhL`H{0E1^IHJ I0IHE H H]L}MILuMI}0E1HH H{01HHtCHyHPHXHXHPHHXd HXHHuHKPHsXHH H)HHCPI/ HHxIUPMeXLH H)HHEIEP IH-MMH]L}LuIWPHuLH IwXH)HIGPI IHHSPLsXHH H)HHCPI HHlLhL`IWPMoXLH H)HIGPIB IHLLmHxLpIT$PIL$XLH H)HID$PI IHL}LIOPIwXLH H)HIWPH IH8LeLuMIIWPMoXLH H)HIGPI IHMIVxM H H)HIFxHUdH+%( uHĈ [A\A]A^A_]謳ff. UHAWAVAUATSHXH}HUdH%( HE1H IHvM!HuL9 Iy LwXLXM ML}LMhMpM9 L}1M D _ I}0Iv HH MLELMLEM LMA~) t]IV8IE8I}`H* H AF0tIEhtIEpIIv0LMLE3Ls L{LELMIFPMm IL{HC M9 L#1 M9 Ls M Ht @0IvHW IU(HJ B+ F+ IE I~HtiH@ H< H;G tbf D r~~ I@MhHZ IL}MhMpM9] v D HtH u$HFHrH9H9sff. LMIHuHI^H)HEHAF@H9 HULHHpHEHu@pH 1HUdH+%( _ HX[A\A]A^A_] IE IVHt3H@ H H;B IIuH9H9$ @ HtHz t$I@MhHL}MIHUH}L!HHx(fLp(L@0I} ! Hu5H D H-Hz-MLMLELELMMfHIIuH9fHt? t AF0IEHIcF@IEPIFHIE@IEX I98HEAFDIFP> D LMHUIH4L`HH@L`IXL`IGIG IF0IGXIF0 覢HULMHHt/HULMff. LHHuHULMI(fIF0LMAG0HIG( I~0HUHE IFI}fInHMLMH0fHnHUflH7H~A~HAGAoFPMefoL AF@fsAGx)ffAFXfH~AGhAFDAN@I AGlApAFHH9 HUIFP AFD HAFHIvXI;IG II HLHMHHHt Mf0HM@0Ml$Z IE HQH H@ H H;B p ID$H{(fLc(HuC0H8 f. HEAFD IFP MLELMWLEMHIE`H2IV8LM I}0Hq HHtktg HMy) GHQ8IE8I}`H H A0tIEhtIEpHHq0HHuHuuMHqHI}(HG+u F+ H-H-HMHMMID$HtHz uHIUH9!H9i HHFHrH9 H81Ht? t A0IEHHcA@IEPHAHIE@IEXIU HAH HR H H;P HFHWH9qKHt H=W HGxv ?Mu HM,IE`HHf0HMHQ83HtHx sH=eSLMIل#Z @ UHAWIAVIAUATSH HUdH<%( H}H~XܝIH^ LMeI|$0I踝H LxLmILM6I~0I芝H LL}LpMMILLmLEIIx0NLEHHEV LhL`HUHHUHUHEHz0HUH LXHHLPILM~I|$0IќIM LLuYHMIHy0詜HMHHE LmLeIHHUHHUHUHEHz0iHUHt~HUH]HHII}0H>Ht8HpHH8H8LLH@H@HuIUPHt L9W HuH]HUHrPHt L9 H} ;HLmLLeHQPHL9HHHu-ff. f HHpH9P8sHpH>HuHyfHAQ H>H M~ID$PHt L9I M>LXLPHHHzPHt L9 H} LhL`IHPHt L9 MbMMLpIINPHt HEH9C MLmLxIL$PHt HEH9 MINxHt HEH9V HEdH+%( HĨ [A\A]A^A_] I$LHufHHHH9p8sHHH9HuHzfHBLJ H9HHHuHHJH9B8sHJH1HuI|$fIT$HAd$ H9rm D I$LHu#f. HHpH9P8sHpHHuI}fIEA] H>LWHHHuHHHH9x8sHHH1HuHzfHBHj H9 HHHuHHPH9H8sHPH2HuIxfI@HAp H:ILHu%ff. HHPH9H8sHPH2HuI|$fID$LAD$ H:8ILHu/ff. ff. HHPH9H8sHPH2HuI~fIFLA~ H:`ILHu 2ff. ff. HHPH9H8sHPH2HuI~@fIF@AFHH:HEdH+%( uHĨ L[A\A]A^A_][覣f D UHAWAVIAUATISHdL,%( LmIH H~`EHHt"HL{LLLHHuI HtL9s*HEdH+%( H[A\A]A^A_] I$LHu+ff. HHpH9P8sHpHHuI~HfIFHAFPH>HEdH+%( uHL[A\A]A^A_]>艢f UHAWAVAUATISH8HudH%( HE1HE xLhLH HLLH"L}L5] HLL虣HHHDH}?f pu| uvHE1LL@ ^Ht)Hu1H諆IC I9s HEfD` E1H蕑HEdH+%( M H8D[A\A]A^A_]H5 H}pH}AtMH5{ Y 1LLĢH Ht He 1012 D H! HML1LHAHt rIH61HuH踅HU: u_HHHPH= wKHMA D HYt LH 101AHE@ M 1AHt HR 01Y10A D UHHdH%( HE1HEdH+%( u0ff. U HAUATSHHdL$%( LeIH5x H H5H H H5= HAŅ H5- Ho H5= HX H5W HA H58 H* H52 Htff. @ E1HEdH+%( H HD[A\A]] @ 1HuL誃HUЀ: HHHPH= Ht B HuLHt H,ЉPL9ekLHY 3 HuLHt @L9eLH Ht 101*e HEdH+%( [ H5nt HL[A\A]]ğ @ LHt LH 101A L踨 H5o LH9HFHʕtnHH5V L贕uoHt @( @,If L/Ht LH 101#[f D Hyt @( @,Ht LHѝ 101 M 1AHqt H 011荜ff. f UHHdH%( HEG tOw-t8u(H HG 1HUdH+%( u4 D t @ HyHG HHG ff. UHAWAVAUATSH8@uL%\t dH%( HE1Ht HE A$@H E E1LuE D LH5 HH H蝦 H5 HH9HF貓 H"1tdHd H5 HH9HFIv LH5 H\u(AD$( AD$,E11O E1@HtH H5 HH9IHF H5f HI9IFے H5sS HI9IFH赒u%AD$8 Z AD$( AD$,CE"EA E } Hutn1H~AD$H9]tnE1Vf D AD$8 fL 1HUdH+%( H8[A\A]A^A_] @ H0AD$H9]u @ AD$8 f. LHz4A|$Dm1A f D Ht A$ AD$ @ Rf1HuH}HU: u<HHHPH= w(AT$Ht H 101:H~t Iع 1H 01蒘f UHHdH%( HE1HEdH+%( u1nYf UHHdH%( HE1HEdH+%( u ɾ +f D UHATSHdH%( HE1Ht]H> Hu$1HUdH+%( uJH[A\]f. HFHF IHHF tHI9$sI$문脗 @ UIHAWAVIAUMATSHHHHEL}MDMHEHE HEdL %( LMLOM!M M $I|$AoAD$IFI>ID$=IvID$Ht'V(f. ~(9t BzvEIt$M|$HAD$)EAD$@HEID$ Mt IE ID$0HEIL$PID$81HHKHUdH+%( u>HH[A\A]A^A_]Hu X LM)IHtLML]I , D UHAWAVIAULjATSHXHGLzHuM'dL%( LEIHEHHEM9 LEfInH] foIfHE fl)U)MۦIO HEHt&Q(f q(9t BrvHIwHME1Aw0E11Hj Lj IGIH fo]HHBHA II`÷LMI$fInM9t I+ LEIPxHt)IFH}LLEIF IF LEtbIXXH膈IHt=LMMgHLI!HuLLRuLfMu1LcmH]M.I^HUdH+%( uHe[A\A]A^A_]-ff. f UHHdH%( HE1HEdH+%( uHH UIHHH Ht dL%( LUItPfz uHrt @(uz t HI HLAQMMHZYHUdH+%( u D 1z uQ UHAVAUIATISHLvdH %( H]؉Mt LWII|$zrI}AI|$ID$"IMHt!Q( @ q(9t BrvIEfHnfHnflAD$IU IT$ IU IT$(HtyI` I|$rAVt@ AD$2AD$0g HUdH+%( H[A\A]A^]f D tKHdt 8 t'AD$2AD$0u붐1uHx AD$2AD$0Hf. AD$2AD$0.t AD$2AD$0k\f UHAVAUIATISHHH%t dL4%( LuAHO(@0 H LG0A+L y H LDM H-H L1HEt5IU H 3k Ht HR H HLHP H)H<1謸HEdH+%( urHH[A\A]A^] D Ht;A+L Oy HJ LDH-MLH'` H1Rg D IMH L1H0Evf D UIHSHHHt WldH4%( HuHHOxx t H Wp@8 u6LHA H1踷HEdH+%( HH] @ fHt(HxbfH*Y HxlfH*^H LH߸ Pf D H_ LH14w HȃfHH H*X D HfHH H*X8 UHHHt HOxdL%( LEIwlx t H wp@8 u5HEdH+%( ɉH L1yf fHt(HxrfH*Yi Hx|fH*^HEdH+%( u~H5 L`HEdH+%( u_H<^ L1f. HȃfHH H*XyfHЃfHH H*Xoff. f UHHdH%( HE1HtH HtH HtH MtI HHEdH+%( u1t @ UHAWAVIAUATSHHH HG`L8dL$%( LeAH M 8 HOhLWp HLLHLBoLHA Hcи I| D)L9` MtN I| D)M fI*YMw fI*^ Z Z/ HcH 1DDF<' D M HOPL_@HwXHGHHHAMHA!L9 E Lƅ HtDLH H1 胆HUdH+%( HH [A\A]A^A_]f D IcLH: L11 LH 1L uf D L9 MV( fI*Y M fI*^ Z/ LH Ѐ ZB @ L9H1LE1 LH IIH HH HHL 1.1Ҿ HAHL D)IcHHHcLI1AǾ IcH 1D)LHcɱAE, 1LL IDLH LIH' HH1eDAEiHLL9R1Ҿ IcID)LHcIH HH H fH* YM fI*^¾ LH ~ ZZL HT DL菰DLAMtPIcf HcH ZL H D3DA IcD)Lf D H fH* YMxmfI*^HcH t ZZ f LAfHL H*XsLAfHL H*X=LLfHH H*X{ HʃfHH H*X<f. LLfHH H*X7 HȃfHH H*Xf. LAfHL H*XLAfHL H*XL zff. @ UHHdH%( HEHxt x uHEdH+%( u$f HEdH+%( u Hrf UHAUATSHdH%( HEHt x u HEdH+%( ujH[A\A]] IH`E1yHHt H{HI}HHuI$ M$ H H)HI$ Dž UHAWAVAUATLeSfInflH(L/dL4%( LuI)EM ff. M}I]I9 ff. @ HH Ao AoG@AoG @ AoG0Hp @0AoG@@@AoGP@PAoG`@`AoGp@p@y Ht'V(f. ~(9t BzvHEHq HMHAML!HI9EMm MHMI^fHnHQHL9u f. HH1foHVH2Iv IF fHnflHHHrHL9uI^fH~H9t$Mf@LH¸ Ht/CyIF@y 1HUdH+%( H([A\A]A^A_]LKHIFfHnH]L+HL9u J IHSfHnH{flIUL*-H{`+HLisIU LM9u^Nff. UH=Pv HSHdH4%( HuH5Á=Pv HHt HEdH+%( u^HH] ( jHHt=`Pv H`f D Hyt H H 01莂ff. UHATSHH2t dH %( H]Hx tDH t:Lf0衩HHEdH+%( u?HH@ L[A\]e x uHEdH+%( u H1[A\]ff. UHSHH_dH%( HE1HGH HGHt ff. H{GH[PHuHEdH+%( uH]t @ UHATSHdL$%( LeII\$HtfHH[P4qHuHEdH+%( uHL[A\]q ff. UHATISHdH %( H]HyHtvHCH; HC HC t`ff. HtMHDH@H)HPH0p L@0Lp8pHSH u HC H{H@PHWHSHC H9u1HUdH+%( u He[A\]?ff. @ UHHHt dH%( HEHfz t>HHҀ0tc t{Htt @ D HEdH+%( ui HIt zuH5\ HuHyt @ Ht @ H[t f D Ht B c UHAWAVLwAUIATSHH_LfdH%( HE1I9t~L~ @ M9t H{0HtbIt$0HtXt'1HUdH+%( uHH[A\A]A^A_] M$$ HL9uMtIM9! @ M$$1~ UHAUATE1SHdH %( H]H_0HtJf D H DrHHt E1f Lo8HHuMHHHuHEdH+%( uHL[A\A]] ~f. UHE1HHdH %( HMHH9t, Hy0 tHq8Ht HAH1HIH H9uHEdH+%( uL}f. f UHATSHdH %( H]HG @ @ HC HCȟH{ HC0tiH{ tbHt] C HC IHC(HtjMteC 1HUdH+%( u}H[A\]f D Ht H 01H{RH{IH{0@HCt H 01H{ H{( M|ff. f UHATSHwdH%( HE1 O H ~E1HC0J<I覞D9#H{0蘞H{菞H{膞H{ }C~&E1ff. HC(J<IVD9cHEdH+%( u2HH{([A\]0f HEdH+%( u H[A\]S{ UHAWAAVAUAATISHXHMLELMdH %( H]ȋ HGHcE1 II9twF;,uIt$F;<uA\$Ml$ l Hc1ff. fHH9K HMI;L uL< x{ID$0HM1N<Igf D A9\$} ID$0Ic|$ LcJHHUHUHID$0J< ID$F,ID$F<CA$9HEdH+%( m HX[A\A]A^A_] DI|$IcDEH HMHT`I|$HID`HMI|$0HH4 +`MH@@ HDE I\$A $ED$Mt$ID$0 A;\$ tCID$(HECHcH}AD$HEL< HUID ZHMHUHLEHHHHE_IH: I|$(Hui_HEH A$ ID$0E14f D UH<1)H E{ID$0J IE9<$~BJ<HuJ HM^HHtgIcD$ 9EID$0H}IH 8E9<$EA\$Ml$ AD$ HEID$(Ht H 014H˟t H? 01H}gLgHt H 01H Hwt 01wLHEgHgH}}gH. @ UHAWAVIAUATSHHdH %( H]H E1A A HC11L H F 1:L} HA9DLHC11F 1 A9DLID9#CDmD}s A E1A E HC(J<賁L`E HA9DLHC 11N 1A9DLCID9ED;Dm1A E LuIHD]~df D L< E1 D IF011LE H J8N 1A9DLAFID9KA;}HLD]LuH LH@w L: PH7w Hw AUPH*w ASD]PEPH PDM1MpD#H@E CD}Lu1Dm f. HUL$ HE1L4 LMIff. fIFH Hv F IF0HB4EPIF B4AWIF(B4EIPIFB PDM1MH}SoAFH@D9HULJA;} HKHEdH+%( 9 He[A\A]A^A_]f HcSH< HUIIH EHU~0Lk(H]LID II} IH CM9uH]DE E1E E LufHC11L; H N, F 1u L H9M11EHCF 1UDS9ME1EE~Lf. HC011L$C H J(N 1VC; CID9sID9;1LuHL E1H L} PDMHt 1ML-t smDK_AXE~/ HC(C L LN1I>mD9{L I83E1҅ ff. IGHLULH t E1FIGBPM1DMlLUAOXZJ ~ELUff. fIG0C LHs HN1IlE9oLUL LU{LUIE9JHEdH+%( ulHeL[A\A]A^A_]ua D ID9s"ID9;_CE E E A A xqHEdH+%( uHeL6 [H=j A\A]A^A_] @ UHAUATSHdH%( HE1 IԉH HHcH>f D HEdH+%( H+ HHH5E 1[A\A]] HEdH+%( H HH߾ 1[A\A]]j D HHcV 1jAL$H HAH5}E 1葿DHUdH+%( 0 H[A\A]]HEdH+%( HU kHEdH+%( Hq HHH5 E 1[A\A]]f HEdH+%( H9 fHEdH+%( H# HEdH+%( uvHW D Ht @@uC. HEdH+%( u<H G HEdH+%( u H ? D @. Hnf D UHHdH%( HE1H=F<v HEdH+%( uhn UHHdH%( HEHt @8HEdH+%( u'n UHH HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEH0Dž0 H8HPDž40 H@HHdH+%( utm @ UHHdH%( HEH;v HtHUdH+%( uYf. HAt H8q:v tH:v f D Hɔt Hn 101:v lff. UHAWAVAUATSH dH%( HE19|eHt IHˋ~ \:v t8fIHt 8 udE1fHL H虾D @ HL D 1HUdH+%( HĨ [A\A]A^A_]f L01L߀uL@LLYHlLuL@ Hm L腷LL L8Hm 1efA,k UHH HXH`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEHH0H8 HPH@Ht Dž0 Dž40 0 HHdH+%( uj D UHH HXH`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HEHH0H81HPH@Ht Dž0 Dž40 0QHHdH+%( ui UHATISHH L`Lht#)p)M)U)])e)m)u)}dH%( H819}%H8dH+%( H [A\] Dž HEH(H@Dž$0 H0cLM HH HSZ/D HHH Hi ʚ;I)HS㥛 II1IH k IcA(cH Hھ HD,h @ UHSH HHHPHXL`Lht#)p)M)U)])e)m)u)}dH%( H81HEH t HH( H@H 3H0Dž Dž$0 :31H H8dH+%( uH]g UHH HXH`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1Ht : u HHdH+%( uZ HEH Dž0 H8HPH0H@Ht Dž40 H H"fff. UHHdH%( HEHt 8 uHEdH+%( u>f. HEdH+%( u#H:t wIH L鎷Yff UHSHdH4%( HuH5u LÅu$Ht w6tAuL kfHEdH+%( u?H]f k @ ~ keff. f UHHdH%( HE1H=ݛu t/Hԛu ff. f HPHH8 uH͎t 3v Ht H!t HEdH+%( u1e UHHdH%( HEHt H8(HEdH+%( uH=H*HRdff. f U HAUATSH dH %( H]HPH HLcLoL H5~f I1DMt!1ff. fI<HCI9uLTHEdH+%( uHĘ [A\A]]c @ UH5 HSHdH %( H](s1*kHEdH+%( u H]cf. f. f D UHHdH%( HE1tN1ff. ff. f D i? Hu1HUdH+%( u D 1c UHAWAVAUL-0v ATSHdL$%( LeI/Hi?%CH$k=)HI\ HuO HHt@H{L褦uD{HEdH+%( HD[A\A]A^A_]f D LLLAumHxLIHi?%CH$k=)ЉMtI~LmHcE~ID IHtLpMt ID IFTaf. f. f D UHHdH%( HE1 HUdH+%( u|aff. UHHdH%( HE1HEdH+%( uHHVHFH0a UHSHdH %( H]HH6tHCHEdH+%( uH]1`ff. UfHAWAVMAULmATILSLH EHXH0L} THEH8HHHE(H@dH%( HE1)`HDžp 蚕fE EME H vdH HX H H܇t HH L`01HX脨 A6LHLVHEH Ht J(tH0H? HKt t-H8 t#HEH=t E111Hp- H!t x t H} $ M AMw8H}ipHMH`Hm Q( q(9t BrvHyt fHnE@0hD La L}H0ID$`LHH(0H0Hp HTD8L`PLHHL@HXAV5H LPLHEdH+%( He؉[A\A]A^A_] A1L`f Af. LHLcHEH,Ht x fAf. Dž8 E1|f D HDžh HEHp1 H=1t E111Hp-HEH0Hf D H8LHXեHt E1HLHpx0AH0DP.M1LDPH0H0H(LHH0H0\f D UHAUI ATSHdL$%( LeIBHtILHRfInHCID$I\$fHnflH1HUdH+%( uH[A\A]]ø(\ UHATSHHdL$%( LeIHtHxH5S t HEdH+%( uJH1[A\]f D I<$HsWHH9t4 HCtHCAD$HGH+[fUAHHQHHAWAVAUATISHHXHuELELMHDH HuL8dH4%( HuȋuHUEtHHC HSH/ @j DC HcHuMcH @I)LtH LHKIGN, MHPMHEHEHE HEMOHLLEHM0HUj AWjH M M$ M I HLH9C] HC H@ H@PHC HHS I oL oB@oB @ oB0@0oB@@@HRPHPPHC I HxLHU kHUI HBHC LHHHHt+Q( @ q(9t BrvI LHO@(HCHEIXII9HuHMLLEHUHLNHHMPHFHj PjIH D HUdH+%( He[A\A]A^A_]f D HC G( n HCHC 1tH@P tH@PH@P9uHC @HEHuLHMHULHLhH HHuHuIHPj AUjyH -I$ t&HCH;t HS H HRPHHS HCEd AGHuMIH@E1HD(HE D HEMNLLLEHM0HUj AVjH I$ H H ILI9G IG H H@PIG H'IW H oL oB@oB @ oB0@0oB@@@HRPHPPIG H HxLHU[hHUH HBIG LHHHHt+Q( @ q(9t BrvH LHO@(IGIIXL9u1 IG G( HSY|Vff. UHAWAVAUATSHHHHt LgdL,%( LmIx t H x! Ls HSMQ HHU IvLLI+6"MN HIAPLMHHuHEaHuLMHHUIK H;ffInAV(fHnfl Av(9t Brv)EIGIOL}HE HMLpH9u D IFLpH9E IHE1E11LLLHEAvj j H tLsLcMt@H|t @0 M~ MfM+&IG`LHHEPH LcIHE1E11AVHLLj j pH HUdH+%( He[A\A]A^A_]f. LIHOH}H v E1 L1 @ H{t E1LLHSx0AHUDE7DEHUMH1L?H}LHI譺LcL|LsLcSf. UHAWAVAUATSH H $ H HIӉ dH<%( H}HsH Ią5 D LsIHB LI^ LLHNH0LouH% = @ A~.u{ tA~. H5$ HޖvH5iU Hǖ_H L =ff. fLroHEdH+%( A H [A\A]A^A_] L HLY u, uNLtLfrIH o {.{ H HiHHtL2HHHu Ly HLf]H5 Lǰ(Ht$A փ@ uAt A HZu D Dž Lff. @ LXqIHrHX LLHH0L&uH% = @ tXL HLɹ, L-sLpIHv D A~.u { GA~.t0 HLPx D {.uʀ{ f D H HEgHH WL0H HH HY H[H5+ H(H t! փ@ ut HsLrSHwt MH B HQ 01MDžOHAsLqDžf. UHAWAVAUATSL$ H H $ L9uHh dH %( H]HHt s LK( 1LL5Q LH5#Q LC} H1 HLQ|] LC( LH P LmH5%) LIH LH¾ uLI[M H5P L_H L` LefHt L.IH H L LLUP LPLK(1LZ=H` LHmHZYH 1HmIH HHMu ILHH LH=Aąu% = @ A}.uA~ tA}.uA~.uA~ if H5a L葐IH5 O Lz2HlHH~ H0HȌ HlIH HHMu HLHH ~HH=Åu% = @ A}.uA~ tA}.u A~. HkHH D HkIHH HHMu ILHHЌl}LH荬Aąu(% = @ A}.uA~ tA}.uA~.uA~ if HЌ$kHH HH،f D HkIH8 H،HЌMu LH|HHǫÅu% = @ A}.uA~ tA}.uA~.uA~ t @ H،djIH LXjIH H،Ml$ LL |HȌL!uH% = @ A|$.uA} tA|$.uA}.u A} tfH LÅbfLAUfff. fH4fEH fH fH pt He3Hߡ 1 f D L LLÅO LQk D H LHI覱Aą n L kL LLiÅ Lj D L LL)Å * Lj D HH _IHL(HH IM HHuSHH5 Ҧt(H փ@ ut Lhk L LLIAą Li @ HH=^IHsH،'HH I^ HRH5* Ht у ut LjfD HH]IHHЌ'HH Mt$ LQH5 LXt#A у uAt A Lif D HH]IHHm&HHc Mt$ L_QH5 Lt#A у uAt A L[iDf D HAb @ HHM\HHH%HH Ls LPH5: L t#A у uAt A Hhn HDYa!I @ H<auHHEdH+%( |He[A\A]A^A_]A~ _Hpt L`hxH kt Dž|L hLfH`H`H`MLgL>fL`Hs`Hg`KH #kt L،1H K{ HE 3XH,`H `H`H jt LЌ1H z HE 3H_H_H jt L1H z H<E 3辜H Zjt LH z HE 3葜|H -jt LH Wz HD 3dH8_7L[fLdbLFfLdBH,fLdH^H it ff. UHAWAVIAUATSH H@Lc}HHH8L0dH%( HE1} ƅ_ H_E1MH0LfOLSLL0H8j HHH@j j PH t IE9}E1HEdH+%( " HeD[A\A]A^A_] L MJ Lu LzL`ff. fLkLHDžp )`ufE EI viI I I H)ht L H* A 01cHHL2L f_H@LL~HEH Hgt J(tH8H? ; Hjt t y Hlt x t H} H}PHMH`H Q( q(9t BrvHft fHnE@0h HA HuH(HH`HH H薡H(H HHHE11PE1LL0j 诎H LA01LxEHL9 D Lƅ_0LA Lƅ_0L! Lƅ_0L HEH=et E111Hp-譟dH L覷HH誆D D Hjt x FLG0L菹f. HDžh HEHp1 A H=Igt E111Hp- HEH8Hf D Hdt HpE1HH x0H(ADbL 1DH(HH\hH HHH(迣H(<ff. UHHdH%( HE1HEdH+%( u H@錜< UHSHdH%( HE1@w H Htf_ ؑHHuHEdH+%( uH]6<f D UHHdH%( HEHt.H 1Ht JHz9}#HzHDHHuHUdH+%( uH;f D UHAUATSHdH %( H]H Ht IIHLAHHHuHEdH+%( u H[A\A]]X; UHSHdH%( HE1fw H Htff_ 藐HHuHEdH+%( uH]: D UHAWL@AVILAUATASHdL,%( LmA&HH DHMDL٥} It@LHw LHEdH+%( HH[A\A]A^A_] D PA9uAtEeE;e tDLL D PA9uAtDcD;c wDHL df D Hat DH< 101ܓLLqLo*9ff. @ UHAVAUIATASHHHHPdH%( HE1HG HLJ HH) HH]H` H HH !]H{@h#DcfLC Hǃp Hǃh HC(H A E Lk01D H; L H{0 DH贀IH LuEL; 1@ @ L聰L11LlLmHǃ 1HUdH+%( HP[A\A]A^] D H=; HC0H[ff. @ Lk0H` wZH{(nZLfZ D H= |HC0He D HC0 벸Wo7ff. @ UH5؞ HSHdH %( H]H2if HEdH+%( uH] 7ff. f UHAWAVL AUI ATSHdL<%( L}I腄H LHIh I H ff. @ 9X~HPHt"H9XHPHtiH1f. fI$AD$L`tM LLاM$ HEdH+%( u^HL[A\A]A^A_] fI$AD$L` @ fI$ M AD$ D L%E15ff. UHAUATSH H $ HdH %( H]؉IuHt 9X CvfHbt L@pMtV Aپ 1LH v8 Lq L Lt$H=v HtqLHt41Hr LbHUdH+%( uVH [A\A]]fH\t LH8 101ĎH=mv L1벐1HHRv Hyu4 D UHSHdH %( H]HtHtHUdH+%( u(H] @ HEdH+%( uHH]1n 4ff. fUHAUIATISHdH4%( Hu؉|HHttH8HtYI$H9t&HtH tI<$H;DI$HEdH+%( HH[A\A]]h D LWHHHuH [t AL$H 1ED$ 01Z HZt AL$HU 1ED$ 01-Y3 UHATASHH@H dH4%( Hu Hu HUdH+%( uJH [A\]f D HA9uAtD`D;` tHDHHE{HEp2 UHAVAUATSHPdH %( H]HH H ArHDI]zHH H8) u%HEdH+%( HPH[A\A]A^]fLD@EIHtVLuEL4 1@ @ L11LHRfH;Iu QLAfEmHf1^^1ff. UHAVAUATSHHPdL$%( LeAqHIDkH HD9yHH H8u)HEdH+%( HPH[A\A]A^]f D LDDIHtVLuEL3 1@ @ L蹨11LH*eH;Iu PLAeEiHe1Z60f D U11HATSHdL$%( LeIHxHHt11H5^3 Hdt9HWt AL$H^ 101HEdH+%( u HH[A\]11Hdu/f UHHHx dH<%( H}HtHEdH+%( u!.f D HEdH+%( u黩6/f D UHAWAVAUIATSHHdL4%( LuIV v:wICf% f AftAE H5]t 8 uPMtcIVHsALwcÅuILdHEdH+%( uGH[A\A]A^A_]f H9Xt HH0E @ H= 11N.ff. UHAUATSHHdL,%( LmIՋV vQvIHCH HvrHS\t 8 uNM IuHL薣Å L4cHEdH+%( H[A\A]] @ HYWt HH0 @ Ju uHWt a H= H~ u U u @HKWt ` H= H:HCu H= 1/ , UHATISHH'[t dH %( H]H8 u:HsI$ HS}Ht41HUdH+%( u*H[A\]f D H1Vt HH0o벸X, UH=/ HHHVHvdH%( HE1.HEdH+%( u1 ,f UH={/ HHdH%( HEHHVHp 1.HEdH+%( u1+f D UHHdH%( HEHYt 8 uHEdH+%( u 1 H)Ut HH0zW+ UHHdH%( HEHYt 8 uHEdH+%( u 1 HTt HH0M* UHHdH%( HEH0Yt 8 uHEdH+%( u 1 HiTt HH0ޖ* UHHdH%( HEHXt 8 uHEdH+%( u 1 H Tt HH0nK7* UHAWAVIAUATSHHqXt dH %( H]H8 HsI` C %IH Hx L{5`IA|$4 s I<$M11-HH L1 LML蝐HEdH+%( H[A\A]A^A_]f ;%HHt$I;h 6 I` H觖HOM1 HRt HH0覗 I|$Gf D L{LAIH L1A zIH f{SuAƅ I0 Aƅ HCI` LHfHnfHnflA$蔅 Aƅ H5+ L t H5+ L ^Aƅ 1H5 L3@fx4 L` t&H0LˇHHLWsfHpf. )' UHAWE1AVIAUATSHH` dH %( H]HHve#IDkHtLx HUt 8 f{ tMAAusM CLLlTHKLMDKLL_S9u L(KHEdH+%( H1[A\A]A^A_] @ HNt H ^ H 01̀ HaPt LHHS:f D HINt HK H 01舀c H!Nt HK H 01`;6&f D UHAUATSHH HdL,%( LmI/H IHt#H Lq/HIV{HHuHEdH+%( uHL[A\A]]%ff. UHHdH%( HE1HEdH+%( u H 9 d% @ UHAWAVIAUIATSHHdL<%( L}AH IHt2ff. HDLLHItzHHuHEdH+%( uHL[A\A]A^A_]$f D UHAWAVAUATSH H $ H(1HdH%( HEHh L` A$ @ L-XOt AE ~RL=yOt E1f D IHH ( A$ N1DI HHE9u HEdH+%( ufH( H[A\A]A^A_]f. L1ɺ LLFHOHL 1Hk' a Hc*# @ UHHHdH4%( HuHHt<Wu5HUdH+%( uKHPt H1HJ`H Jf HUdH+%( uHO(H ' H1J#f D UHAWAVAUATSH H $ H8HHI HHdH%( HE1HDž 9H5& H% H Pt LL9IMu M~IM LLH 5uMtM} HLHHH5% H9ju5HHH1HUdH+%( u:H8 [A\A]A^A_]ÐLH5% Hit ! @ UHAVAUIATSHH:dL$%( LeIBH AoD$HH@{It$ LpL]<I` Hn~Aąt'H_EHEdH+%( u@HD[A\A]A^]LKLL HHt H| 01 {A ff. UHHdH%( HE1HEdH+%( u1 ff. f UHAUATSHdL,%( LmLh MtOHLzH` LIɍMtI<$Ht BLBHh RDHǃh HEdH+%( u H[A\A]] UHSHdH%( HE1HtHPH` +H Hǃ` ԋH H{(JBH{0ABH 5BH{8,BHEdH+%( u+H{@H]! HEdH+%( uH]6 f D UHSHdH%( HE1Ht'Hw/HEdH+%( u%HH] HEdH+%( uH] ff. UHHdH%( HE1HEdH+%( u / ff. UHAVAUATSHH dL,%( LmIAOHtLM HLՈH+Mt(LHsII; uHsI HEdH+%( u H[A\A]A^] ff. @ U HAUATSHHh dL$%( LeILj LXÅ~Aƅ I$` \HEdH+%( u H[A\A]][ ff. UHSHdH4%( HuHh H^ HCY~ƃ HUdH+%( uH] ff. UHHdH%( HE1HEdH+%( u1 ff. f UHAWAVAUATISHH}H8HULHMdH4%( HuHu`_ Lm LL}L者 H LLHIHtkHLyIH H` H5yADž LL>HUHUI|$ Hs(IT$/{L? D 1قLh>AHEdH+%( uNH8D[A\A]A^A_]f. L蘂L'>f D L?LxL>If UHAWAVAUATSH(HG0dH %( H]HL5Gt IvX H HHHDnIAMh A @ HHE HE HEKHh >L1QxHh HH^ @4H` wAą A~ HMHUHHuD HuL}HtHh L Lh LeMt!AV(fAN(9t BJvLh H` LQHh HLL8M LDL`H` vLA=Ex!LH LuI L荀HEdH+%( E H(D[A\A]A^A_] HHH@t K0 Hu 1'sfHLE )Iv0 H HHHDlIf H@t Ht 01rLuI!H` Hh cHHH HUHh HH IDHA<HA2I D Hs 1ErA UHSHdH<%( H} eHtWHHǺH5^ IHXx,HAt H HEdH+%( uHH]f D H1 UHSHdH%( HE1OHt:H5K HH(K~ HEdH+%( uHH] @ H$1 UHHdH%( HE1QHtHHEdH+%( u WHEdH+%( uɸ UHAWAVAUATSH H $ H8HdH%( HE1H:Ct HDž HxX H1辍HCt E1HxpHI 11H HLE1HLL$ Lk @ HBt ML H L@pL1 Ls H HIM9 J7B0 wHzL eHHHN 28 MiuL9tr8"GH<t LHq I014oHM9{E1DDHEdH+%( H8 D[A\A]A^A_]f D Hxh YHx` NW D H[<t H L01LnHD`AhQ UHHdH%( HE1HEdH+%( u H@o UHAWAVIAUATSHHdL,%( LmIՋVvJ'Ss LI \IH Bt 8 At$9s t7AT$ H=@p 1YLLLHSs L[IMtLLLHSsL[KIHtjMteIULH#zxO1LHL}HHEdH+%( uCH[A\A]A^A_] D H<t HH0H=o 1}f D UHAUIATSHVdL$%( LeIv%HH@t 8 uRHtH.?t x& t0C HGHEdH+%( u9H1[A\A]] HLe H;t LH0 UHAWAVAUATSHHxdL$%( LeICIHK HLmM<$LHxFHxLL[~xEAFEAF(H}"HMIHEIFHt Q( q(9t BrvINfLAF0oKhHCLE|$2M$$)`HxJFALLLxLOfInEAFXEAFhH}"HMfo`IF@HEHIFPt Q( q(9t BrvINHLANpHC`I HEdH+%( uHxL[A\A]A^A_]Vf D UHAWAVAUATSH HxdH%( HEH HhH HXtHhHHXHh HHVH`H H E11H] HXH@HL,H`HHPMeL<HxH HpDHpLH EfInH}EAGhAGX HuIG@HEIGPHt#V(f D ~(9t BzvIwHfHAOpSHxMe HH HpDHpLHEfInH}EAG(AG HuIHEIGHt!V( @ ~(9t BzvIwfHAW0 IEHhI AFIH;HEdH+%( uH`HĈ [A\A]A^A_] ff. UHHdH%( HE1HEdH+%( u H@T UHATIH@SH dH %( H]HHuHE )H H1H0HUH55LHcHEHUdH+%( u H [A\]7 UHAVAUATISHHdL,%( LmIBAƅu8H Hu* D H`bHHtLLH tAHEdH+%( uHD[A\A]A^] ff. @ UHHdH%( HE1HEdH+%( uHH5Q UHAUATSHdH %( H]H L#H9t2I @ H{AHHCHLHBHM$$L9uHEdH+%( u H[A\A]] f D UHHdH%( HE1x1HcH; s%H HUdH+%( uf. t @ UHAWAVAUATSHdH%( HE1E HAAALcL; sMH HDDF,LSHHtOD`k@1HUdH+%( uCH[A\A]A^A_] H LEĹ LH _t뵸 f UHSHdH%( HE1Ht H HVHHuNHUdH+%( uH]F f D UHSHdH%( HE1Ht H H+HHNHUdH+%( uH] f D UHAWIAVAUATSH( EH(H LL dL4%( LuL MVuMVH ƅ7H HBXH% H Hr M H0t E1x4 H Hx(tIHDH3ff. ff. HLLI y担 A9 H7EeLE1HHMc {( AD)HcMTPI X Hc)ff. HMLI yf D D9A9Iu1HUdH+%( 6 He[A\A]A^A_]f D Dž HL1LHtHDH//t HDž8 HD@(H H 9NЅh HFE1 D AHD9 H8 uD9 E E A H D H H8DLLL(H L j PLLQ^L_uDH LLL8HL AUj ZLY xMt Hx4 uJE1H 9HoM<H-t x4 H$Dž IIH9ADNIcHvHHJHH I)HL9tH H$ L9u H)H HIHIHHH H)H9tH H$ H9u H)HtHL HH E4 H{(J H@LILLff. @ oHH@Hq(HpH9uE1HL1E1LHLfvIHI냵Fa)ELDL)@)P)`)p)E)EE2 @ @H @HI H;_ IHIE9B HHIH9HiH ))Ɖ)H@@uD@f ALxHcLI| j H MLHH(j j j ТH O OAT$IA { j H L7LHH(j j j dH O+ I?LS'H5- HLL7H LLL{!LLHIL9LH LHH(j j j j L蕡H LLf D H D En AE1LE1HLH(L AULjHL'AZLA[dH MHLL H jH8P0AXLAY EM Me M9~LM HI9jHDKPK9HSHss0LC@H(sHsXQH tM H(t E1Hfj H L7LHH(j j j 1H NuAHL< I H H HB H H L[LL^LN@MDLHv Hm LKH;H^MYMI)LIH)M)LNH;NLBH IIH90 DɉD_D @ @ HIcH IH4HDHH IH 11HAH9Fu/HAH9Fu%HHA9 A9 HH9tH {9~ LDH4HH qLH4 DADIII$ Ly( I L@HI9 II@fo HAHI$ ALoLA@oAA@ oA A@0oA0A@@oA@A@PHIPIH`I$ J|0LI@I$ J|0Ht O( W(9t AQvIx I$fInfHnL@flA M$AIXD9LLADHH HxHHHH` H` H)H)Íh HHA I L'L9iDHML(Lf D Mm L9& HEMPAM9LIuAu0IUME@AuHAuXLH tLf. DLE IcMcH@MI IHff. fMMAuE1LH j HH(AUjH tDt^HfMMj E1LH HSAUH(juH tuIHM9gD D)H D @ED9 EIDA)M)1$ D HH)J4H90fHD9t4:A9DAA)D)>HcHLHL@HIHHF u MH1ff. BHHL9uH~MLcLLLLHdKLHHQLLI냵FaH1HtfE1"I<H9s HH9AHH9AoAILILIcHLH vAff. AoAILILHH9uZH "t HW 1E101aTHLD 1HL1E1E1DD)ALIIA DLO LDHI H X DLyI@HDHLH DtbL HBfHnD fHnflHB flA I H BiL[LdH1DLI LDHm t 1HU DL01RDAƇ H LACH 'ID$fInMD$fHnflA L h HEHHI?LLLADDHH H9 H9 LHDHDIH{PsHL9uLLDH DHH9t'HrHzLJfHnHqflHJI9LOH HxHHHHH` H` H)h H)HAt0D MH DH H qHVHrHKf UHAWAVAUATSH(LELMdL<%( L}D}HN IHIIH?H t x( IF(H0tHHEdH+%( D}LMHLLEHeLL[A\A]A^A_]*f. H tH tE1EHLLH=ftHUdH+%( He[A\A]A^A_] HHLLAWLMLLEZYuIV(HҀ0uH tH tHEdH+%( u3HeEHL[LA\E1A]H=ŞA^A_]kT ff. UHHdH%( HE1Ht HEdH+%( u$H 4 @ HEdH+%( u1 UHAWAVHAUATSHHX H` dL,%( LmIH5Pƅ HM/ u t+1HUdH+%( HX [A\A]A^A_] @ LIHtL5 L>IHtAG*<uMg-LL7t&H5 L7tH5 L7uMMSHd HLI ` HL4PIKMHHH HI I9tm1L# HHu HH5 LL LLH LLH!y @ iff. @ H UHATSHdL$%( LeLh Hp MtGHLL tHUdH+%( u-H[A\]H5 Hu I$Hp f1 UHAVAAUATSHdH%( HE1 t,Hp IIHtYv<w I9AAHEdH+%( uFHD[A\A]A^]f. tI9AA )I$p w_ff. @ UHHdH%( HE1HEdH+%( u H y @ UHHdH%( HE1HEdH+%( u1.f UHAWAVAUL ATIH5SHHHHU1dL4%( LuLw0L AD$LE{HEHP M|$LA LKZ }/ H[kernel.I3D$HkallsymsI3T$ H b }[ H5c H; H5 L3$ Hh Hp H HEdH+%( HHLH[A\A]A^A_]z f. M|$LA LzY }/V I$Lu LLHEtXC LLHLIH H}HLIH H` H(L LVLID$I+$IE H}IEI L1HUdH+%( HH[A\A]A^A_]f}/&LIH A H߃D A E Hh yL1KHh HH @4H` LK I H5 1 Ht1H53 LLh MD$M $Mt AV(AN(9t BJvH` Lh LLMLE[LMLELHh HLM LDL@H` JLEE% H}'H IT$H CuHh L;L3TXf D 1!TL; Hs0Hl@IH^f D I} Huf D HE A D HuLH HuHh L][7 LxSLR LpLXSL2LCS%f UHAVAUATISHH` HF(oF0dL,%( LmIHH-t 8 m E1C@@ A < < S sL3IH HK HSLLHsPHCHPCDAVPDK@H HH HLc L HPHEdH+%( He1[A\A]A^]f D oC1# HsHH LHfoHC HfsfHfl)LLLmH=G 1?Zf. LS(Hs,L @ H t HH0R|f HXL H=G 1 UHAUATISHH( H?t dL,%( LmIՀ8 F A < < S sL1IH CHK H(E1HSHsAULSj j D H HH HL"a L HZ f. HEdH+%( He1[A\A]]oC1# Hs(H LHfoHC HfsfHfl)1LLvH=/F 1Hc H9t HH0$f H L H=E 1 8 UHHdH%( HE1>w@HH HcH>f. HEdH+%( G= HEdH+%( ɸf D HEdH+%( H @ HEdH+%( Hb @ HEdH+%( u w HEdH+%( U H @ HEdH+%( 5 H @ HEdH+%( H[ @ HEdH+%( H @ HEdH+%( H @ HEdH+%( H- @ HEdH+%( HD7 @ HEdH+%( uyH? HEdH+%( uYH8 HEdH+%( u9 HEdH+%( u!3 HEdH+%( u H UHAVAUATISHH6H` dL,%( LmIHUW3HHt,LuLCtOHU1z4 IE HCt+I$H-HEdH+%( upHH[A\A]A^] @ HH+B LXTuL 4uL0CuLd@HUЉ1{HB H kff. @ UHH dH%( HE1H}H HuH5?HUHUHUdH+%( uff. UHHdH%( HE1HEdH+%( u H` 9 D @ UHAUATSHHHx dL$%( LeIH| HtRI9r L; rAL; r L; r*H HL9 H HL9 1HUdH+%( H[A\A]] @ LmH` H5 LH} HUH@z4 uHH+BHx H` LH5 KHUH@z4 uHH+BH H` LH5 HUH@z4 uHH+BH H` LH5c HUH@z4 uHH+BH H` LH5A Ht*o@HEЀx4 uHH+PfHnflf H` LH5 pHt*o@HEЀx4 uHH+PfHnflf Hx D L; FWf L; ?Hǃx ,ff. UHHdH%( HE1HEdH+%( u H Q @ UHSHHdH<%( H}LH3HSHKHC C( HC 1fC4HEdH+%( uH]-ff. f UHAWAVAUATSH H $ H HEDmH] HHE(HHHHLDHdH<%( H}ȿ8 ].H H5Y HIA H5U HA j$t= H5> Ht% H50 HDDEH5l H$ H5 H߉PHH j El$0HAD$,MIA Mt w E HHHZ IM HHMLHH+EtAD$4uAƆ LLL\TL$LL95 LLL FHEdH+%( HeL[A\A]A^A_] D LX4IHtLML] HHjHDž I H5x HHxHxlH5Y HHx@"HxGEl$0HAD$,KIEV9 H5 HE19A_f D HH1H HHt HDf D / H+1HDžx HhHtHHxH=o IHHe H5 HHpz HpHdHxH= HDHx#H* HHpHxLpHtH hH 1AVHߺ L T^_f. H5D HH= H= HXuHXHH`HwH=H`HP*LPHE?Hp 1EAa_ A~rT A~mI Hb HxAt HcHHH HhH1RL:9 H`Q XSH0f. LH L HA 1>SRf H LA 9 @ LLE1 Hx HhM1Hx H L HRZYH5 LHPLpDLLpHPH5P t8DLAxqA~8fA~6[ H I H<f D UHAUI ATSH dL$%( LeI<HHHH e HHtM11LHKHEdH+%( uHH[A\A]]If U HHdH%( HUHW t$H 1Ht H5Q VHUdH+%( uff. U HSHdH%( HUHW t-H 1Ht H5/ H¸ uHUdH+%( u#H]f H5 H@ U1HHdH%( HEHG Ht HEdH+%( uɉf. UHHdH%( HEHG H@0HHUdH+%( u UHSHdH %( H]HG(H >HEdH+%( u HH]kff D UHHdH%( HE1Ht!W( J9rO(9t uHEdH+%( u!f D uHEdH+%( uf. UHHdH%( HEHG H@8HtH@HHEdH+%( uff. f UHSHHG dH %( H]HHx0HtH@ HCHEdH+%( uH]?ff. @ UHAUATSHXLg dH %( H]HLM$ kt'1HUdH+%( HX[A\A]] HLxYuLHHus D H vI| H5 LH3 D1 /sA$ @tRLEI$ LLEU9LEL1H s H 3B/3H 1-/H s L 1Hq 3 /MKH2 D .Yf D UHATSHHdL$%( LeIx%HEdH+%( u0H{ HL[A\]R4fHEdH+%( u H1[A\]Q UHAUATISHHdL,%( LmIx8H[ HHEdH+%( u9HLLH[A\A]]- D HEdH+%( u H1[A\A]] UHHdH%( HUHU莿HUdH+%( u U8 HATSHdL$%( LeLg Mt A$ <HHHH "HHt@( L HC HEdH+%( u HH[A\] UHHHHLHdH<%( H}HHp L@1H RHZ gHUdH+%( uHff. @ UHHAUATSHH=-s dH %( H]HIHc$ FHHHH% I)HL9tH H$ L9u H)H IH _ HtHB HtH HtB t<L%3 uCL H1HHUdH+%( uAHe[A\A]] H L%A3 tLL1HL @ HL gh UHAWAVAUATSH(HUdH %( H]HH IH @ H / AH H1I H5s HAċ$ BHHHH% H)HH9tH H$ H9u H)H IE HH HtH H ~ ~ L-2 L H1 LAE H H1DHHUdH+%( x He[A\A]A^A_]ÐE1 E' [t t/ L-h1 Hc1H}LFHM@ H@1 H1BLAff. HMH: H1 Af D H$ H1I HAHs $ BHHHH% H)HH9tH H$ H9u H)Hu;HE1H 1 [f H F @ HL D HL UHSHdH %( H]H%C HEdH+%( uH]Mff. f UHHHW dH%( HEH t; ut&HGHUdH+%( u9Ð4 u*H D H+ 4 uHH+Gf. HG D UHHHdH%( HUHW t$ u6t>HG4 t$ff. HUdH+%( u" H+HG H+ *f. UHH4 HdH%( HEHFuH+GH1H9rH;GHEdH+%( uɉff. f UHHHG dH%( HU1HtH8 HHEHUdH+%( ut @ UHHdH%( HE11Htx HEdH+%( uɉ*f. UHAVAUATSHHdL,%( LmILs HtHxH5 ItUA L t#A uctf{4 uL+L+kLH+CHUdH+%( uLH[A\A]A^]f D I|$HtHtHh HHE @ H+CfI Bf UHAUATSHdH%( HE1HtKIHI=EHHEdH+%( uOH{ HML[A A\ A]]' Hs H HUdH+%( u H[A\A]] UHAUATSHdH %( H]1HtKH tDI1IHEIHs L; tLHř L1 H} HEdH+%( u H[A\A]]ff. @ UHSHdH%( HE1HHt HEdH+%( u+HH] Hys H:( 101# UHHdH%( HE1#HtH@HtHUdH+%( u ÐHs H ( 101W#1.ff. UHSHHW dH%( HE1 tH菴H'H9h HUdH+%( uH] UHHdH%( HEHH7HHHH9t#H9HUdH+%( u) HFHQH9u1H9tD Kff. UHATSHH dL$%( LeL'HC H ID$ H u I9tI$HH9t-H9HUdH+%( u/H[A\]f. ID$HSH9u1I9D ff. @ UHATSHHdL$%( LeIHvuID$Ht\HHtDI4$Ht.Ht&S(f K(9t BJvH f D ID$ 1HUdH+%( u H[A\] UH HATISHHH> dH%( HE1hH3LHHC藭HCHTs 8 HEdH+%( u?H1[A\] D H3I|$ ۪HCH;1H; HHC4 @ UHHdH%( HEHGHHUdH+%( uff. f UHHdH%( HEGdHUdH+%( uff. UHATS1HdL$%( LeIID$@ڃH<L9rI|$@ AD$q HEdH+%( u H[A\]D @ UHAWAVAUIATSH8HF Lw8dH %( H]HLg@HEGE}hDHE9sjE? A LMDMHuQIHp MDMMIE8t#HuL)DMMHIK Me@E}hϋS(HM> s(9t BrvIMt#S(L s(9t BrvH EMdHA AEpu[1AEpAMqH9Sr;HEHt uY1HUdH+%( H8[A\A]A^A_] D AErf AIH;PC4?IHH HtLh D M _H9s Hj" 101 aUTI}@ LMDMff. UHAVIAUATS1Hp Lg8dL,%( LmIt `M9,t-L 9rHs H 101 HEdH+%( H[A\A]A^]f MN8HtME 1 L9s;HzH9sHHI H3HI9uIMLVL9uL9tI9 D H I9rL)HYff. @ UHAWAVAUATSHHHHG@Lw8dL$%( LeIHE H߉ELM,II} uAGLNI4ƉʉMD)HɮH} E1{q Ls@% HE1Aff. @ M9s{K/HI H HUHEHA HMH ID$ H HU HMI9 I$H1H9 H9 IM9rf D Hs H 101LeH MII?ULLHɭkdHEdH+%( HH[A\A]A^A_] DAMH4 M;$tSAHA9rff D JtNLj D ID$HqH9 I9 @ ED)EHEL$I9 HE}H)ljƃ}H}HL$I 調f. UHAWAVAUIATISH8LW8Lw@udH %( H]HLUA E}hLUAHADA9ljEs}E A LDMD]Hu虥IH MD]DMIE8t4HuLDMD]HEdLUD]HDMIg Mu@E}hEDDMLUM<)AHI<LܫMLUDM AT$( @ At$(9t BrvM'Mt+DAT$(I<At$(9t BrvL'HtaES(I< s(9t BrvH Mt+AAS(I4 K(9t BJvH EAEq AEd1HUdH+%( uFH8[A\A]A^A_]ÐC4?IHcDI I<MFL'>eI}@ LDMDMD]LUqff. fUHAWAVAUIATSH8dL$%( LeIWA}p HEp LMu8,Eǃx`II4$E H;prL1 H;0 S9| HcIH;prՍK9}}ff. L9E EM}8M4I HI;D$ H s H5 s 96 ~.H 1AHuLHuH HI;$ HCI9D$ ELPU U9y IHl I|$H98^ LHL9E+HEdH+%( uH8LL[1A\A]A^A_]f ID$ H H 1aHI;$8HHH I$HBHs 8~Hus HCI9D$ I>HUHUEIPE1HUIH ID$IIAH+]IAHds 8~Hs I>M LMLMM>LLMLɉLH}xHEdH+%( 7 H8[A\A]A^A_] @ IK HuHHU HU HuLLMMI>LM]LMAT$(LM @ AL$(9t BJvM&1LLM0 D L I}8 H IAEpg I>AT$(f AL$(9t BJvM&1 @ ]L8f UHHdH%( HE1HUdH+%( uHG`軸ff. UHHdH%( HEHGPHUdH+%( u}ff. f UHHdH%( HE1HwPHEdH+%( u;ff. UHHdH%( HEHGXHUdH+%( uff. f UHHdH%( HE1HwXHEdH+%( u軷ff. UHATSHdL$%( LeIx HHtJH7LcHfHHCP HCX C8 HCd Cl fCpHEdH+%( u HH[A\] D UHSHdH %( H]HHt-HH 19t BrvHEdH+%( u HH]褶 @ UHAVAUATSH dH%( HE1Ht1I1H f. Z9r9t/uHEdH+%( H [A\A]A^] uID$8HEID$@HEE LuAIMI>HEI HtII} IE L 9rH}eH}\LHEdH+%( uH L[A\A]A^]zu D UHATSHHdL$%( LeIHLHAHEdH+%( u HD[A\] UHATSHHdL$%( LeI)HLHEdH+%( uHH[A\]?躴f. UHATSHdH %( H]H<HHA)EHUdH+%( u H[A\]Vf D UHHdH%( HE1H9HUdH+%( uf UHAWAVIAUATL%6SHHdL<%( L}IA @ HH{p u HH{8L CpHHC{p tE1$ HS8DLH<AAąuAHA9rE1HHEdH+%( uHD[A\A]A^A_]&f D UHAWAVIAUATIS1H(HUdH%( HE1+M|$8L 9s$HuM,I} Aքu5L9rHEdH+%( u%H(L[A\A]A^A_]Iu L}ff. f UHH dH%( HE1HUHUHuH5HE %HEHUdH+%( uff. UHH dH%( HE1HUHuH5HE HEHUdH+%( u迱ff. @ UHATSHHdL$%( LeIHLNHAHEdH+%( u HD[A\]S UHAWAVIAUATSHH8HudH%( HE1]LŚLMf8IHA> E E I<$mIHtU1HHHAŅtQLH}`H(HEdH+%( H8D[A\A]A^A_] 1A븐LHI!LAEEEuD9[ HExhL< ILHEH HEH@@HEHt LHEHEDkhE1HC8HEHC@DHEEtIK<XIH 1HH/AŅuPHEH} N4uyAGICdL9}uHEHM@pCpAlCl1H} tAqCqE1 LHE@pCl Cq Cp| D 1YAѐAV(f. Av(9t BrvHEN4Q D UHAUL-ATSHHdL$%( LeI@ HXH{p u HH{8L _CpHH{p tHH{81H9siH0HH L;!rpL;asJQ(Ifq(9t BrvHHEdH+%( u9HL[A\A]] HrH9rHE1f. Hsí UHAUATISH(dL,%( LmI臩HHtWHwxK{4 t5LHbMt<I] HUdH+%( u;H([A\A]] LcL+# 1MuHHEUHEf. UHHSHdH %( H]HHvH{H;7rH;wr HtXHHCHHtDHs4 t*Hs HHCHUdH+%( u H]fHwH+7 t @ UHAWAVAUATSHH8HudL,%( LmL- HDslHl A9 HC@HtzN4IF HtmH Hu uYAV( AN(9t BJvHHEdH+%( E H8L[A\A]A^A_]f. {q H >H{q u'Ls@Mt/HL L=CqH @ {hHIH0 HL{8dLs@t1L I ?Ht Q(fq(9t BrvI >HL9u_f D 1AHC@HEff. L9s>M,HEH}HMIN$M<$IG H HMx t#IML9rHE1 D MMMt,AO( D Aw(9t AqvHC@HEHEMHI)IDCl1HxH蠓HLk8$Md D M} IG HtH HutIM9uAO( Aw(9t AqvMrf UHAUATSHHdL,%( LmI{p u\L%zf. HH`{p u HRH{8L CpHsH蛒{p tLHE1HDh A9s0HC8N$Mt#AT$(fAL$(9t BJvH>HEdH+%( uHL[A\A]]lff. UHATSHdH %( H]H|{p HLc8fvqHLMDf D H HzHqH?HtH9sHyHL9uۃIHx t=Cr HEdH+%( ubHH[A\]:f. tf. H@f D HH{8 H QCp6c UHAWAVAUL-ATSHHHdL$%( LeID HHX{p u HJH{8L CpHkH蓐{p tHLs8AAŃxJII<$E1H;xr:1H;: HA9| HcIH;zrԍp9}EHLs8HA9sDIL$IH9r5 HEdH+%( HHLH[A\A]A^A_]T @ HS{p I HLk8=EAxXIE I<$E H;xrC1 H;:7 HA9! HcIT H;zrӍp9~DEHLs8ME9 IL$HEHHELHEH H9x EKhP9EljEHIH H{@ HC8Cpt<E1 f HC@DAH<,H4A9rH{@Cq E1ChEt9 I >Ht Q(fq(9t BrvI ?HH9}uDmLHMDkdDEHML}D)HMlff. I7HI!M9uEM, D I<$IcID$ M9uLE1HHEdH+%( u{HHD[A\A]A^A_]ÐAn LHHAJ HH{8 H Cp E胣HA^ UHSHdH %( H]HHu"HEdH+%( u!HH]f D HC8H8 f. UHSHdH %( H]H< hHtfXHUdH+%( uH]豢 UHHdH%( HE1HEdH+%( u递{ff. UHHdH%( HE1f? HUdH+%( u8 UHSHHdL%( LEIxf D HL9Dt@fuHEdH+%( uyHs H]H ' 1H 01 @ f9rf;HEdH+%( u9H] ׃HK)HHcH|HH4討x[ff. UHHDdH%( HE1fD;Gt*DMcfJtHEdH+%( u: HEdH+%( u!Hs H 3 H 101ˠff. UHHdH%( HE1ft-fHTHD HEdH+%( u+HfH1s H H 101p1G UHHdH%( HE1ft HHDHUdH+%( uf1f. f. UH= HHdH%( HE1yHEdH+%( u1衟 UH=å HHdH%( HE19HEdH+%( u1a UH= HHdH%( HE1HEdH+%( u1! UH=C HHdH%( HE1蹡HEdH+%( u1 UH= HHdH%( HE1yHEdH+%( u1衞 UHAWAVAUATISHH8Hp HUD LPdL4%( LuIMN Mj(M+j E11O|+0A" LLUL]tL]LUHI HEMqA0 MyIAIA M K 1MIt$LMEl$Hp IHxLKLMHI IA(Hp H8 HPL LHHLs LHѣ 011HUdH+%( H8[A\A]A^A_] IB Iy0LL]LMMu0It0 LML]Mi(&f D M{0E11A" LL]3L]HIt\HEMqA0 MyIAIA LLL-H^s H̢ 101H;s H 101Zf. UHHdH%( HEHs 8 u+1H=Q ݞHEdH+%( u"1f. Hs HH0ޯ UHHdH%( HEH s 8 u+1H= mHEdH+%( u"1f. HIs HH0w UHHdH%( HEHs 8 u+1H=q HEdH+%( u"1f. Hs HH0> UHHdH%( HEH@s 8 u+1H= 荝HEdH+%( u"1f. His HH0.藚 UHHdH%( HEHs 8 u+1H= HEdH+%( u"1f. Hs HH0' UHHdH%( HEH`s 8 u+1H=! 譜HEdH+%( u"1f. Hs HH0^跙 UHHdH%( HEHs 8 u+1H= =HEdH+%( u"1f. Hs HH0~G UHHdH%( HEHGHHGHGHHGHEdH+%( uff. UHHdH%( HEHGHHHwHt"11H@H HAHHABHH9rHEdH+%( u茘ff. UHHdH%( HEHGHHGHEdH+%( uFf D UHHdH%( HEHGHHGGȉGGȉGHGHHGHG HHG HG(HHG(HEdH+%( u D UHHdH%( HEHGHHGHGHHGHGHHGG ȉG G$ȉG$G(ȉG(HEdH+%( uh UHHdH%( HEGȉGHEdH+%( u)f UHSHHls dH %( H]HӀ8 u'HEdH+%( u.HH] f D Hs H0赖 D UHHdH%( HEHGHHHUdH+%( u HpЊkff. UHHdH%( HEGȉGGHUdH+%( u Hpf. UHHOdH%( HUHWffOHHWWffW@uHEdH+%( u>f D HHT HH|HUdH+%( uPH4)}ff. f UHHGdL%( LEAȉGG ȉG HGHHHwHt?HG1ff. HHHHHPHPHHPH9rH HEEuHEdH+%( u, @ HHHUdH+%( uwH)譔ff. f UHHdH%( HE1HEdH+%( uwHɃň`UHAWAVAULo0ATSHH( dL$%( LeIu"A|$ A A A A HcC@I| HtHs8}HcC@ID H-u 1Hs81DHC`HHHCXHS`DHCXIDH oKXHcS@HCHA$y foID fsC@ ffCPu'1HUdH+%( ujH[A\A]A^A_] I$ fA$ @ A A HѺs Hq 101r UHHdH%( HE1HEdH+%( u諒ff. UHAVAUATSHL H( dL,%( LmIH ls I$ H9HHJ H=s H9xP L5Bs L9pX` A$@ A$H A$D A$L I HH9t @ B;H!H9ut A u>HV|A$X HEdH+%( H[A\A]A^]f D H= 1H=Q 1貀e D A$ H= 1蒀5 D H=a 1z D H= 1b D HEdH+%( HH=Z 1[A\A]A^]+ I$ H I$ ( I$ HoA$ H= 1T @ I$ A$ HH fH*H fH*^f/m Y H=x vI( f. A$ A$ H= 1:I( f D HуfHH H*XH\HHfHH H*XD D HuH=% E \} H tH A$ I$ H=! 1~I( L9pX @ A$ H= 1j~I( L9pXBff. @ UHAWAVI AUILATISHHDDFH5@ dH%( HE1H@; Mt$L; IubAǀ A ;IHEdH+%( KHL [H5 A\1A]A^A_])f L8uHͷs H= HfIh HILHL9IUH5o 1F @ AUXH5K 1 菍ff. @ UHHf dH%( HEHGHHGHGHHGHGHHGvHG HHG HG(HHG(HEdH+%( u UHHWdH%( HEHffOf + f f P ffp f fA DEAf HHHff. ff. ff. D oB HfofqfqfBH9u܉Atk)Ov-JH H~fofqfqffʃt4fDH J9s"fDH 9sfDP f@ f@HEdH+%( ÐP ffH f t;f ttHEdH+%( HBs H# 101 P ffp ft1 LɉLH9rcf P ffp f@1 @ HLHHLH9r 1ڊf. UHHO wdH%( HUWfnfnO Ήw fnWfbfnʋWfbʉWHW flGHHW t HW(HHW(vWpʉWpWtʉWtHEdH+%( u,ff. UHHdH%( HE1?uGȉGG ȉG @uHEdH+%( u,f. HEdH+%( uGHɍp~諉ff. UHHW OdH%( HEGfnfnfnGfbfnHGfbflHHGG@uHEdH+%( u$fHEdH+%( uGH ɍpp} ff. UHHdH%( HEGȉGG ȉG HGHHGHGHHGHG HHG HG(HHG(@uHEdH+%( u' D HEdH+%( uGH8ɍp|kff. UHATSHdH%( HEGȉGG ȉG @u HEdH+%( uQH[A\] LgHL1HHI<HEdH+%( uCHH4[A\)]/|ʇf. UHATSHHWdH%( HEʉWW ʉW HWHHWHWHHWHW HHW G@u&W(ʉW(W,ʉW,HW0HHW0HW8HHW8u HEdH+%( uMH[A\]f D LcHLDHHI<HEdH+%( uCHH4[A\)]B{݆ff. f UHATSHdH%( HEGȉGG ȉG HGHHGHGHHGHG HHG @u HEdH+%( uPH[A\]f D Lg(HL聑HHI<HEdH+%( uCHH4[A\)]zf. UH=3 HHdH%( HE1詈HEdH+%( u1х UH= HHdH%( HE1iHEdH+%( u1葅UL_ HAWAVAUATISH(HUHdH %( H]H^Hw H,s LH1Hٿ H5 3H H E1fuHAՄuAHuAHuAHMt$HA E1 @ HuDDM<͵H5 HL1AMA?tr HHH!tb H 0 A fuHAՄuAHuAHuAHHA A_ HEdH+%( u>H([A\A]A^A_]f. H 0 A @ E1hփf D UHAUATSH H $ HdH%( HE1H~7AHL @ H)H~ LDH9HNQHHEdH+%( uH [A\A]]Jf. UHHdH%( HEHGHHGHGHHGHEdH+%( uff. UHATIH= SHH dH%( HE1者I$ x tx# Hsu(xHCHUdH+%( u"H [A\] @ HxHuHu؉ff D UHHdH%( HEGȉGG ȉG @uHEdH+%( u#ÐHEdH+%( uGHɍp`vff. UHHdH%( HEHGHHGHGHHGHGHHG@uHEdH+%( u"HEdH+%( uGH ɍpu{ff. UHHdH%( HEHGHHGHGHHGHGHHG@uHEdH+%( u"HEdH+%( uGH ɍp`uff. UHATSHdH%( HEHGHHG@u HEdH+%( uNH[A\] @ LgHLɋHHI<HEdH+%( uCHH4[A\)]tbf UHSHdH %( H]HH חHUdH+%( uH H]餙ff. @ UIȹ HAWAVL`AUIATISHH L( LdH%( HE1HH x# DPA$QtjHs : u @H HcH>H LLLDTLX]A$DTLXf I HBH9 LXLLLHAƅt(HVs : t H LLLLXIc0HxLX LXA1ff. HUdH+%( HĈ [A\A]A^A_] HѬs H : C @ LHA H Ao$ID$0LH@ AoD$P AoD$ Hp ` A HW H LLA H5 D LHA H @ LHA H @ LHA H @ LHA H @ LHA H @ LH譼LHA Hf H x LHA( m D LHA HT @ H x LHA H+ LH LA Aą IcLHA H @ H LLA H D LHA H @ LHA HI At$1DL 1LD f D HH HH9u3ff. @ H H9t @;t H Q1{ UHSHdH %( H]H HGyHUdH+%( u(H]f D HEdH+%( u HH]L7{ UHAUATSHdH%( HE1H IM$ I$ L"I$X Ht D HHHwQHuI|$@LZI$ Ht (tWI$0 HEdH+%( uMHL[A\A]]dj @ HEdH+%( u(H[A\A]]f D I$ zI$ $z @ UHAWAAVAAUATIx SHH(dL,%( LmIuH HDx H@ LhL Hh HX LHp H fHnfl 航H 1H5 tH{@蚨M L A|$(L H 8 AD$(uH{ A|$ tTHEdH+%( H(H[A\A]A^A_]f D H=!s H }H߈8 MtA1 tA0 tH H= >{Aƅ0 fH1s H 101w?fL舙tg @ H߉EHc]! @ DH< Ht HŤs @&A|$ tQH 5A|$! uL5s I~8 I~0 LHH IF8Xq H蓊u<H b H O H k A|$ VH_H HH9uLff. H H9t6@;t LHs H ~ 101+1vH Hs 101xH} H} H}} ff. f UHHdH%( HE1H? H H H H( H0 ) H8 4 H@ ? HH J HP U HX ` H` k Hp v H H H Hh H Hx H H H H H H H : H H H( V H d H r H H H H H H H H HEdH+%( D HQH HHH HGHH HGHH( HG HH0 HG(HH8 HG0HH@ HG8HxHH HG@Hs HP HGHH\s HX HGPHs H` HGXHhs Hp HG`Hs H HGpHas H H qH}s H H cHQs Hh H UHxs H HGhJHHx HG?HtH HGx4H[H H &HH H HH H HH H H{H H 0 Hrs H H ff. fH)H H H H( H HH H( HH H HiH H HH H rHQH H dHH H VH9H H HHH H :HH H ,H%H H HH D HH =p UHHdH%( HUʉWʉW HOHHHO HOHHOl HOHHO X HO HHO 0U O0ɉO04vyO4ɉO48vlHO8HHO8@v\HO@HHO@HvLHOHHHOHPv<HOPHHOPXv,OXɉOXhv OhɉOhlvfGlpvWpʉWp~H(fnƾfofp fqffofnξ????fqfp fffnξfoffp fqf~<j ff~4j fffnfofp ffqf~j f~j fffH(HEdH+%( u Ã((n UHATLgSHdH %( H]HL腙C sI<HEdH+%( uHHH)[A\)]b1n UHHdH%( HE1HEdH+%( u Hǐ km @ UHSHdH %( H]HHt.H HstHEdH+%( uHH]fN/A m UHAWAVAUATISHHxH}ED$ HMJVH5 dH%( HE1At$At$0M $7Lk(Y^A u L tjI$ HEH@Y6 1H5rt E11H; L=Et t$HLDL 1AFIH;rHEH@( HE A t#I$ tHUI$ H= A t#I$ tHUI$ H=~Z A 6 A @ I A x A A @ A A A HEdH+%( He[A\A]A^A_] @ I$ A$ HX H}M$ HGXIHEvA HEI$ HM" 1Hr H5r HI$ H8 f LmLx f D HMnĦ{SH5T L g DKHLC@L LD@H LD@HDAH; HAWQRASARPH] PHLEH5n 1HI$ H@HI9 M{L= 7@ I&f D H1Hq H5q "I$ H8 @ HKL A 1H5 1I$ LCHHvLL5q Lm MMMIHL H1II HH9rMLmMHEH5 HLD@H1fI$ H8 1L5q ff. I HL 1H&I$ H;ry @ HXj HAWQRASARPH: ? LmLxCHEH= q Lh0A" A= I$8 I$@ A~ HH5$q H1 uA$8 AL5 q A # ff. H HSL 1HA" 8E;$8 |+f IT$@H55p 1 IT$81 H5o A A IT$`1 H5xo A pIT$h1 H5go gA @ XI|$pHu\H5Vo H16A 4I|$xHu+H5=o H1 A$ I$ H5P 1 M$ A$ MQ H1E1E1fEpMLI9s J| uH9wIHkAP H5m LpUHT1L=m LxDE9UE1DELxLptYLMLxDpLhMܐJLDL 1LIL9uLMLxDpLhIJUL1 DpE1LxLUDpLxLUA@1I9 taLmMH]LLxEAff. H@C4L IL 14AD$IH;rLmH]LxH 1H5m A @ MQ" A$ H l 1HH 1A$ @ I$( 1 H5l uAI$0 H5l 1PI$H H5 m 108L=l @ H HSL 1HAHSL1 E;$8 |f D 1<c @ UHAWIAVIAUIATMSHH8Hs dL%( LELE8 tLHLIw L虑IHs 8 tA <v#; H HcH> A utF tAAwHΏs LULx$ t褝LUI CLUIf. s HEdH+%( ID$pH8LLHL[A\A]A^A_] @ HEdH+%( I$ HEdH+%( ID$0f D HEdH+%( I$ HEdH+%( uvI$ d @ HEdH+%( uVID$hG HEdH+%( u6ID$(' ID$PH;ts HUdH+%( af D HEdH+%( uID$` ID$XH;ts uHStI tI tI D CtAX HEdH+%( tID$e D M LUM I ^H Gs LU9 tLHLH=LUAB( IB0 A$5 M@ * A8 E HHHHHElf D IQIW IHH+H8IO0HP8H@Ht\Ht#LMMHLHLA$LM HEEIEA;8 IqLLM2FLMHuAH H1s 8 tdLLkLU\MK S IMH5h 1蝿LUMt,Mj0A A A Aj HEdH+%( ID$MLH8LHL[A\A]A^A_]HEdH+%( rID$@c HEdH+%( RID$ C ID$HH;s HSI f D HEdH+%( ID$ HEdH+%( I$ HEdH+%( ID$x HEdH+%( ID$8A@ HUdH+%( xH8[A\A]A^A_] @ AH 1 @ f{ 7HSI ' D HEdH+%( "I$MLtf D I@ LCHtI@ IW I8 HH+H8IO0HP8H@HfHeHUdH+%( M $H8MLHL[HA\A]A^A_]AAL 1~H s 9 H}HLHu1HS0 1LUH5 f LUrHS( 1LUH5e 迼LUDHS 1LUH5e 蛼LUHSH5te 1{LUIqLLMBLMHEIQI IW HH+P8IW0HH8HHH H HEdH+%( gI$Mff. UHAWAVIAUATISHH HXH LPdL<%( L}L`LpAŅ LLHLb uLHHMLI PI LXAXHs Z8 ufff. HEdH+%( u]HeD[A\A]A^A_] Hɂs DHG 101 f. A H} tLL9Zff. @ UHHdH%( HE1HEdH+%( u#HNHFH LFH( Hs^Zff. UHAWAVAUATISHH(HU L L( dL,%( LmI A4$R I ЭA<$? A0 tkHULLHETDPv,HHUdH+%( H([A\A]A^A_] HMHUMLH芼u D HMMLLHkf LhA $H s HHH(LHEdH+%( u-HUH(LLH[A\A]A^A_]H*Xff. @ UHAWAVAUATISHHL 6dL,%( LmIL( I iA<$?wBHLLE1j H MLZYHUdH+%( u!He[A\A]A^A_]Ð11LH1*Xf. UHHdH%( HEfGfGȉHEdH+%( uW UHAWAVAUIATISHH(LEy dL4%( LuMt K I$ x x# O DxI 1D'H HD |H A|$ Cf I9 LhHsDL{L9 A|$ u<Mt;?vbHEH1HUdH+%( H([A\A]A^A_] I$ Hr HHtH I$ LHktf f H H H+ H>f. HxHucHuAVf UHAWAVAUATSL$ H H $ L9uH8LHIIHLdL,%( LmL,Hff. HE1ML HÚu3HHLHAԅuHJI:Gt)M9rHUdH+%( u$H8 [A\A]A^A_] LrM9{U @ UHAWAVAUATSHHH}dH%( HEHp LhM Mu M}(M9 f Hy}s EċEą HEI]0PIFI9rnL DcK4MI9 Het 1ҋLHLH)L9s2H|s HEHҺ MH P 0AW1HXZ1HUdH+%( He[A\A]A^A_]fHDcK&MI9sHDekDE^fIEHEI IEHEHEx L L( u~3RS I g;? A0 HUHLHE=PvaHHQ IMu M}(MMu M9k f D L8H r HHHcHTfLEHMHHUH}u LEHMLHH}HH e] HMHUHH}f. IE3HEIvAIEHEHEL L( Rff. fIEDCMu HEHHys AL1H 1+3Mu Hɋ3Qff. UHAWAVAUATSH8Lo`HO8HULgHVdH%( HE1IEH9? HIM E|$KD= MH9 Hht 1ҋ0LHHH)L9 HMEɿ Hys Hɷ A0Q1H ? BY^HEdH+%( E HeD[A\A]A^A_] LHM|E|$HMKD= D}H9 EI wI HKHSPLLS HxlN$8oS`LcPLfInflfC`nAŅ H}LBfA 5 D LDMHM A蜊oCXH1Hws E $foED$2fsPH f1fH~ XZf D A AO UHHdH%( HE1HEdH+%( uɉH }Off. f UH HSHdH%( HE1DHH譄HHUdH+%( uH] Off. f UHAWAVAUATSHH dH %( H]Hs L Eu E A}! t AE@ L 1 A}# LHT AE IEL L( oCH(HH@AE$Lf)0H菳H0HH H HmW HHtfo0foEfsffH~H ƃy fօXLm1HDžP Lu HELmHp LLHL-tRb tH4vs fo0fofsffH~H9p LHLIyAHX LHp DfA4 D LD yHZLeDMt EfLM$$Hw@oMuELDi-ƃy DHEdH+%( V HH D[A\A]A^A_] HDžXzAHX LHp E" LRwA LH AAH 1H5 RA @ H8D @ H( L HHH H:- z ~ H DIHF Hƃ E1DžH HLl D HLLHDž5P HH MIHs Hss p H L蝃IH { AL$If 9 t!It$H HKHW H( { L H A4$RF I A<$? H0 HLLHLv, HH MH L( LLz,LIH LHR HHzpAM@ AIu8j HFfffoHRHHff. ~ H`@fvfvfpȱf~@@fvfvfpбfʈfH9ufofsffofsff~Dxȃt;HcHRH|H< PA9~H|>(A9~ H|>@AIcHH<H%kHIHw H x# PMp$L@L1 oCHHAt$(1fAD$AoFA$MD$foID$ MfxfsIF0 LAF`ffAF84p= M HHL oA AM@> D E1DMAff. IW8KvHHpH IcDXLH H H HDH$1ILHLHHE $IL$xIt$HIt$81MT$ID$ EL$(ID$0 H4o6 HHHHI$ Hd AO@AID9DDDL-Kos E AE uQIcHHL$ILp oGfofsffH~H9GPx GpuL L7qAuH 1H5LAD_HD4 LDE1qIcHX ƃy Hp HDL4I @ LMI$ Ht f HHHwgHuI|$xIŨ &M9uHDgD HpHuH HAN HHkH 藒IH ƃ E1DžH LD @ HLLHDž/PG HH MIHG HLHls H L|IH' { AL$If5 9 t!It$H H|H H( { L H A4$R I \A<$?! H0 ɈHLLHL% IHH MH D L蠵T L牍HHm)Hy HHpIFLA$H r HHH^LA4$M @ H % LLHf D HLLHL$ lHR/f. I}wL L谴" L牍HH}(H HHpILA$H r HHH,LH HHHp a > LI|$h ID$h AFAA H # LLH;f D HLLHL# $H^D1LIE1MB LkAu8HH5Au"H 1H5FAf. LD0EDuHH4 tMLD&KH^NDLL30ADYDHDiDLE1Hgs AL1ED$H¦ 1A4MLE1Hxgs H,I 1L01跙LLL|/ALE1Hx虳LH HHLҪAL 3LIE1Hfs 0M He 11 AQLDILDMDLH[fs HG 1L01蚘L A HG 11LgLLDKLE1A4$ A 1'AqLDIDAL HX AHp DAL LDlLA]Dž MLE1H es H 1L01^L譚D A =MDLf UHHdH%( HUH HH9u f D H H9txu # Hyds HH7 1 1躖1HUdH+%( u<f UHAVIAUATI SHdL,%( LmI^HtbLH HHHtD] THt LkLtHtH1HUdH+%( u H[A\A]A^]H+;f. UHHdH%( HE1HEdH+%( u H )@; @ UHHdH%( HE1HEdH+%( u H iT; @ UHAUIATSHdL$%( LeI "NH HD H HD1L5I LHcH |HHUdH+%( u H[A\A]]:ff. f UHHdH%( HE1HEdH+%( u H ,t: @ UHAVAUATSHHds H bs dL$%( LeIH8D3$O L-@ds H=C IM 3Iu I$x D3HEdH+%( u H[A\A]A^]9 UHHdH%( HUH HH9u&f D H H9t9puHUdH+%( uf1w9 U HAWAVAUATISHHDwddL,%( LmIA9DOE1DHHt @( AAuL-IH 1H1.IA5f E9~cIcD HHLI T HAL 91L>1HEdH+%( uzH[A\A]A^A_]f D H9`s DH 101w D H`s HZ 101WH_s HB 10178 UHAUATSHdH%( HE1HtkHHtcIAH H=A AHLYHEdH+%( u@HHٺ [H=A A\A]]飠 HEdH+%( u H[A\A]]a7 UHAWAVAUATSHHVLFdH%( HEH HHHHEL9n K@IHHH9` HYes E18 HA E1M LEDM& f. H} IH HCAE HCAE$HCAE(M I$It$EAE,Au0 u9' I HHEpHH A8 HHMA +HHk kI u`HMSHA8AE,AL$EH_s H}uM~HH MH0kIHUH IGI9 IHcs H38 L-J_s HH? 1 I} 00HKI} 1H? 0HKI} 1H? /I} HK1H? /I} M I $H? 1/I} IL$1H? /H3H}IH HCAE HCAE$HCAE( HHHL9 LHLdHbs 8 }H#^s LH> LEH81/LEP D I HEB H zH3H}GHtBHSP HSP$HSP(E1) D 1HUdH+%( u^HH[A\A]A^A_]øf LH5= 1蓓HH5= L1 sl3ff. UHATSHdH %( H]HH %.Aąu-H Hu H蘈HHtH-tAHEdH+%( u HD[A\]2 UHAUATSHdH %( H]HH` #TIH` XMtOLH= IvtYLH= vMt%u! H5, L*t9f HEdH+%( u=H[A\A]]f D H ^s Hh HH9tH\s Hh 1f. D UHAUATSHdL,%( LmIH~HHt0IH5q< CHHtHUH5`< 1mÃt&1HEdH+%( u.H[A\A]] EA9E uI|$=IER1f UHAWAVAUATSHhdH%( HE1> t'HEdH+%( He[A\A]A^A_] D HجIHtDc\EtH HtIOH H H uH |; A Ih " 1IL9W HC ET ML HEIGfAMh IE҃ Hdi HcH>A f EL: HE Mt:LHU DUH LM-LuL: DULMMMEHYs DHHB H58 H81IL I9rlH] AB@g AB W A D @ D8 DЀ AB HEdH+%( HXs H H5 H8He1[A\A]A^A_]~H 9 7 @ Ih IH D11f D H48Nff>Y HLH9H HH9rH`1 D HxL-2Xs MHp HxI} L$ET$A\$DfffA<$fE DHMHw EAAH5 1DU}HMH DUfE fA fAHEHM1fDuHEfDUHU C@f EEHE M HUH Lk+LuMLL 8 MIMEI} HH˖ 1H5 H|L) HEH9t`Mf tEf}bESHE f} EEMbMLE1L7 I뀐 . D HMHH HHpH9>rf HEdH+%( m H>Ts H 10He1[A\A]A^A_]vf D H1H)HDH Ss H11H 3BHEdH+%( 3HeH 1[1A\A]A^A_] HEHM1HEHUg @ HUH L)LuMLLm6 MIMEI} HH 1H5 H {LvHEH9t-]HE MuMLE1L6 If HMH{ @ uf D HEHME1HEHUc HUH L(H]OLL5 HILEI} LHP 1H5D IVzHL9ut(AF HE EMuOL1LK5 I뫐HMHUAzmDc\Ih H M$AD$MIT$ED$ I8fM~0I\$ HHUAV8DDfAHIωփH]Df<DEL$ fuM\$EMd$(AɃL<DI҃Ĩ݃C<ӃMAAEHASAAQDKSAPEBTAVVH5 RH\ P1 yEH@MI} H H5 P1AWLEHMxXZH=: Dc\Ih IH C )f. UHAWAVAUATSH dH%( HE1> u DB\HEu(HEdH+%( He[A\A]A^A_]f D {Ht@;qt tK;et uL A\$Ш HEdH+%( HPs HA 0> D L Et$ DШtBHEdH+%( k HOs Hّ 0Heؿ 1[A\A]A^A_] D Hf3 I\$~ r fHnH\3 fHnHi3 fHnHg3 flfHnHk3 )fHnD~ r =kt flfl) fofl)Pf)0~ ~r )Efl)E)@E E1tHH5L HH3L=t Lm AL s tHL 1 H8H1 LEHHHH9H8HIH7AH ( MLDH4MLDHI AUAEASAW VH5 RHAWPHH2ARPHH1PHH0P1-IT$ H`1H51 AD$ IT$ HEdH+%( A HeH5 1[ A\A]A^A_]Ʌ=t Mt$LmHE HE A LH 0 MMH HS A HERLIHALPLH H5- PLHP1/H AD$@ IT$HHHHH(IH'H&H%I A AL/ L/ MDL / AL/ MDAL / L / MEWDڿ VH5 QDP1APAARAvH0=Wt . =Ft ! AD$&! 1I\$$fHDžf fnHE HE )p)E=t wHLfH!uYIٹ 1ILf AL/ LAٹ LA 1L/ HLpH HHIIH0IHPHIH H5 PHHAUAWPHHAVPHHPHHPHHPHHPHHPHH PHHPPHHPHHPHHPHHAAP1袂AD$&HĠ x S AD$ IT$<HHEdH+%( HeH5. 1[A\A]A^A_]7IT$ =t ? HIH r IL AH <\ 1H5 1fI\$$=t fnHDžf HE HE )p)E=yt Z HE1H5L@cHLILH=I;* * A PHL0 H<P1aYL^ L MMbIT$H5, 1L a IIA LɃ H5or HcL & H H + H+ HEIT$ H5, 1gCMLd, L1I AwIT$4H5, 1IT$,H5q, 1AD$&eHA 1HL), LA 0E1E1 UHAWAVAUATSH8dH %( H]H` HH][MHAHEt{EeHLmL}L5+ Hh*H\ArM1LLLHquA} ibs_ Hibs_fetcI9E uA}huEt D H}H+ H5$ zHtt t 1 t uMHEdH+%( H8[A\A]A^A_]f fA}oplEJt % D Ft t H}?DH t H t HH5* 1ptHEs H* 01 x f. f. @ UHHdH%( HE1HEdH+%( uHvHa UHAVAUATSHdH<%( H}ؿ 6kH@ L-r ffII` Lfoff. ff. ff. ff. foH fvHfvfpffofvHfvfpѱffH9ufofsffofsff~ۃLcLHsjID$HHtq11fIL HtHcƃHHHHHH uH LBQA\$ AD$ HEdH+%( u HL[A\A]A^]L- E1# UHSHdH %( H]HH>HEdH+%( u HH] f UHHdH%( HE1 HcHr HHUdH+%( uf UHAWE1AVAUATSH(HuLwdL,%( LmLco ff. @ M9s/K\= H}HIIMIt$+_x7t=L{M9rѸHUdH+%( u&H([A\A]A^A_]f I A$ff. f UHHdH%( HEHG9w ~ HcH0HUdH+%( u t @ UHAWAVAUATSHdL$%( LeLgX;_ }@HcIIIHI IA9] ~I|$LmtA A$HUdH+%( uH[A\A]A^A_] UHHdH%( HE1HEdH+%( uJf. f. UH 4 HAVAUIATSHGtL&dL4%( LuIH_`Hw`D@H^Cs LDGt 01WH IU(L;#raHC H9t!ff. HXL;`rvHC H9uIE0fHnIN IM0fHnflAF HMeg D HXL;`svHC(H9uIE(fHnIN fHnHHflAF IM(* HPfHnIN HHfHnflAF H HEdH+%( udH[A\A]A^]fHfHnIN fHnHJflAF H D IE(IM(IV fHnfHnHPflAF IU(Mef D UHV HSHHN HF(dH %( H]HHAHHG8HO8fHnfHnHPHFflF ot HW8tHu HC HEdH+%( uH] PH)W HHAUHAWAVAUATSHxudL %( LMDOtE" If @ W > HO`Hw(HG(HH9U HFHH)HHHW EH fr LH@s H 01LpTH@s IUH 1 01TIE`MeHDžh Ht H HhM } IE(I}(H}HLxH H9 L5>s MM;'g LLAUhAÅb LLoIHK IIE HC H H9M' HAEċEątMe}IELuIEHEE1AExH?s EMtD]H Lp 01SHs?s IU H 0 01SD]G @ t u6H7?s H=h0 H&~t ff. E1HEdH+%( HxD[A\A]A^A_] } HWE f EIEH IU HEAut1Hǂ HHx0;IE(I}(H}HHXLyH9 L5<s \ L;# HLAUhAÅuHLmH LHxIE `~IG Iw H H9ut~IAEċEątf E IU E HEI;E(t^HhI9IE0H } IE` -f D HEI;E(tHhI9rIE` f D IE` MetIE` g D UHHdH%( HE1HEdH+%( u1f UHAWAVAUATSH8HMdH%( HEHBH HIIMH; Lc8 M HC8MI9 HHPfHnL`flHQH M\$LHM,$HEM|$ID$1HUdH+%( H8[A\A]A^A_]f L%;s H S- 1A4$"PA4$H1DCxH ~ Lc8 PC| )HCH9C suAvLh,IH AFHC HC8I9 f D HKXH HcSpHHRHCpLd=U HCX H3< F M HC8I9 HHPfHnL`flHQH Mt$LHM,$.f HK LKL]H HML9 LM2^LMHMHHCXL]B Hr:s H; A L]01SjHCHHSHLcXfHnHC L]fHnL`flA$LcHICp H :s Lɿ H~ 01i H: HCH9C sFAvL*Ht4AVIHS H: uff. fKf D HKXHt7HcSpHHRHCpLd=U `HCX S D Lc LKI$ L9 LM\LMHHCX H8s L H} A 01hHCHHSHLcXfHnHC fHnL`flA$LcHICp @ [H8s Lɿ Hh} 01gh= AFLI)Lc 9ACLH)HK UHHdH%( HE1HEdH+%( uH x UH(HHdH%( HEHH9tH@HUdH+%( u f D 1g UHHdH%( HEHG(HwhH fHnHG8fHnHGHflfHnflW(flO8GHfo! GHEdH+%( u UHAWAVAUATSH(LHdH%( HEHGHHEL9 HWXIHtyH HBfHnflHAH LoXtEGpt>I](H@HMtXff. H;HtGI)D$ :H0L9uL)M|$HM/fInL9}tvf D IWflIUL*A$ At1I_(M H;HtWI)T$ H0I9uLMIU fInL9mtIfHEdH+%( uH([A\A]A^A_]} ff. f UHAUIATSHLghdH %( H]1I}LIE IDž HH) HHHEdH+%( uHLL1[A\A]] f UHAWAVAUATSHHHuH5 H}HUdH<%( H}HHE HE wmH ILuLmL=.& ^f. H]LH Ht,H߾ ] 1HZHMHUH]H5% HQ HuLL LLiRHuLH}1HUdH+%( uOHH[A\A]A^A_]fH߾ s]1 HH1ZHMHEHH9HE 딃 ff. f UHHdH%( HE1H w HPr HHUdH+%( u6 f D UHAUATSHdH%( HE1Ht[LoHII}+IHtH@HxHsLHEdH+%( u4HL[A\A]]f. :+IHtH@ff. @ UHHdH%( HE1HEdH+%( uPKff. UHHdH%( HE1Ht W O9t BJvHEdH+%( uH UHSHdH%( HE1Ht(WH J9rK9t uHEdH+%( unH]fuCu%H{#*HEdH+%( uCHH]PBt uHW1s H=" HFpt D UHHdH%( HE1G HUdH+%( uff. UHHdH%( HE1G HEdH+%( uff. UHHdH%( HEGHUdH+%( u^ff. UHHdH%( HEGHUdH+%( u ff. UHHdH%( HEHUdH+%( uff. @ UHAUATSH H $ H H $ HH fo t dH %( H]HfHDž )JH H0! 1L LHLf HH@sfxHHH9tHC HDž HCHLIL L A 1|LHS HsH{Af. AH~HEdH+%( u HH! D[A\A]]f D ANff. UHATSHdH%( HE1tnA JHHtTfAn@ HD`fpf /C Ht*HEdH+%( u%HH[A\] 1 @ H`/f UHHdH%( HE1G HUdH+%( u[ff. UHAUATSHdH%( HE1H I IHIHtz@ LGLa+LC&%LCLC I|$C HtHCHt HEdH+%( uHL[A\A]]HE1f D UHHdH%( HE1G HEdH+%( uKff. UHAVAUATSH H $ HdH%( HE1HtHIHHt u*HEdH+%( H [A\A]A^] fo t Lf)FIHtL11|AƅxNI|$11|Aąx! E"x6LkD3Dc_LHDI L09L#DkDc f UHSHdH%( HE1HtTH?tJ{tDH{ t= !H{HtwuLH{Z#;x {yHEdH+%( u_H]f D CfNt uHg*s AO H < HD %t H81q UHATSHLeH dH<%( H}HLBH18!LHmHEdH+%( u H H[A\]ff. f UHAUATLmISHLH(dH<%( H}HHL`LXmHEdH+%( u H([A\A]]7 UH 0 HH dH%( HE1HUHuE H}EHUdH+%( uf. f UHHdH<%( H}H=t kC H Ht nEHt HEdH+%( uqUHAWAVAUATSH8dH%( HEȋt+HEdH+%( H8[A\A]A^A_]f HH5FH=t H=#t >t7HEdH+%( V H8H=t [A\A]A^A_]J'f. Ht Lc%t E1HEHCDeHEff. @ M9s1HEK,H}HL<HM7IvyAxtLkM9r邃 D I Mt@Af D r9rA69tvuLHht HEft EHEI)NjEIXA9}+AHMIcAHE)HtH<J t uLHt HEt Ef UHAWE1AVAUATSH8H}dH<%( H}H=tt Lc%t L-t Deff. fM9s0K <H}HMt Iv"@ L{M9rЋE9Vt LuLHxHIIH HxHSLD% t EA DeE1 DHuDED)DUF4IcID Hxw?DE EVE9 Du I MM)A6 A>9t ƍF~vH=t t$A A79t BrvHEdH+%( H8L[A\A]A^A_] DUEFE9Hc]IDD)HcHH It I|Ht t L<U D L Hc[IHtt H}t 4H=9t E1#<1Ic UHAWAVAUATI0 SHH(dL,%( LmA_ HEH Dh H5E1H=t HXPH=t DHt Lc-t HEfM9s+HEK\5 LHL<Iwo=xKtQLsM9rH=it 2LHUHHucH( HE If D I MtAf D A79t AqvH=t 2HEL8HEdH+%( uHEH([A\A]A^A_]f D UHAWAVE1AUATIH5SHHH}HUMdH%( HEHH=\t HEH=lt Ht Hc t HE D I9s-HEJ3LHL<IIw <x9t?MuI9rH=t 1LjIHuN L MMtA A79t BrvH=t D1HEHt0 J9rH}9t[uH}HEHM} L(HHu&1HUdH+%( u4HH[A\A]A^A_]f D @ f. uH}ff. UHSHdH %( H]HH?Ht( J9r9t/u3HEdH+%( u HH] uwp UHHdH%( HEHHHUdH+%( u:f. f. f D UHSHUHdH %( H]HHE H{o: uUHEdH+%( uH] @ UHHdH%( HE1H=t HEdH+%( u UHHdH%( HE1Ht W O 9t BJvHEdH+%( uH' UHAVAULo8ATSHLH(HdL4%( LuE1L#LI9MD.HEdH+%( uHL[A\A]A^] @ UHAWAVIAUATLg8SHLH(HudL<%( L}E1Lk(HC(LHEL9MD YHtWHS(HufHnHBE HC(Ht MtH Hp1L HEdH+%( uH([A\A]A^A_]ûf UHpHHHdH %( HM1HBH9HDHUdH+%( uff. f UHwpHHdH%( HUHWpH9tbHBE1$ff. f D HPHJH9t#IHȀx tHUdH+%( u$f D MtHx uw 9wID1ff. @ UHAWL AVIAUIATSHLHdL$%( LeA H;m{! AuQLLHAAąuC!E1L HEdH+%( uiHD[A\A]A^A_]f. LLHt5HSpHspHHfHnfHnHJfl@HKpEtH; 8Aff. U@ @ L HATSLeHhG dH %( H]HHE PDO1LiHUHuLZYu7HUHE1HD Hu1:&HUdH+%( uHe[A\]fT @ UHATL SHdH %( H]HLHkHHt HZ%HL*HEdH+%( u HH[A\]ff. @ UHAUATSHdL$%( LeDg$Et!HEdH+%( uVHD[A\A]] @ L HL&HjHHt$HHt C$AL)?ff. @ UHAUATISHdL,%( LmI7AL$ H0 I1LI<$LHckHHUdH+%( u H[A\A]] U1HATISHH?dH %( H]H4t HUdH+%( u4H[A\] HEdH+%( uI<$HH[A\]U8 UHAVAUATISHH ~! dL,%( LmAt(HI&HH 1LL#u9C AD$CA9D$twH3I<$ Eu.1ff. HUdH+%( He[A\A]A^]HEdH+%( H3I<$He[A\A]A^] D H!s f1)E: tI<$HUH5 H})Ezf. Hs HAL$H1] 0C PDK1ED$ GX1Z5+f D UHAWAVL}IAUIATSH]HdL$%( LeIE3LLL,I|$ u HL9uHEdH+%( uH[A\A]A^A_]A UHHdH%( HEF;F t7tHUdH+%( u;ɉq HEdH+%( u!1 D HEdH+%( u Hgff. UHAWIAVAUATISHHhHpHp DxdL,%( LmMH 1H9Lu@L|!LHL|rH H}L M A$ HEx4 tcMtA AE LDHLLLcxHpHUdH+%( uPHh[A\A]A^A_]f. HXH+ H#I$p Ld @ UHAWAVAUATSHdL$%( LeL M I $IL3L9t9ff. @ H{fHHCHLHBHM6I9uI|$M|$H L9t" @ HGIHCHHHM9uA$ 1ۅt, @ HHCI$ HH|2fA;$ rI$ " I _IDž HEdH+%( uH[A\A]A^A_]1 UHAWAVAUATSHdH %( H]H?H;Ht iH Lc8Ls(L"H{(L/HL9u/IHWfHnflIUL*5IU LLM9uLL LspLHCpHHxLzL9u5IHOfHnflHJHGp<IWIGLHJL9uLH (H Hǃ LLHY2HZt Ht H HEdH+%( uHH[A\A]A^A_]f. UHAWAVAUA ATSH8dL$%( LeA H HDhH@(L}D`LspH{8H@@ƀ fHnflC(fInflCp,H , L1 E LC 6`11LHtuHSpfInHHDfHnHJfl@HKpC #Hǃ H ǃ HEdH+%( u-H8H[A\A]A^A_] H. 1W UHHdH%( HE1Ht!W J9rO 9t uHEdH+%( u!f D uHEdH+%( u_.f. UHATSHHdH<%( H}Hs9s t6t1.IHtH8LHHf. HHHUdH+%( u H[A\]E D UHHdH%( HU1HUdH+%( uH ff. UHHdH%( HE1H9HUdH+%( uf UHAVAUL-ATL%dSHdH %( H]HL H1LLGH{8Hx#*HC L9uHEdH+%( u H[A\A]A^]5 D UHAUL ATE1SHdH %( H]H_8 @ HH{HHxI L9uHEdH+%( uHL[A\A]]f UHAWAVIAUAATASHHH)HHdL$%( LeAL| 8LLHL)I|pHt D;g HE HUIcI< L H]Ht9LJLHL)M$I|$pbH^LID$p] H]HEdH+%( uLHH[A\A]A^A_] ^HEH{^f H}g^HE[yf UHAWAVAUATISHcډH(udL,%( LmI͉E HHE HH)L4 N|78LK}HEHt_ME1E11LHH0H}uo]AE HEHHt(EHHH)M$I|$pH~]ID$pL HEHUdH+%( uRH([A\A]A^A_] HHULHE H]zH]HEHf' UHAWAVAUATLeSH(dL<%( L}II Mw8HE LI^E1I~881\IF8IFHtF @ IVN<Mt, L1HLH0M H}MuIFII9rLIx HEI9uHEdH+%( uH([A\A]A^A_]2f UHATSHdH %( H]HHL @fHH{8HxI9uHEdH+%( u H[A\]f UHAWAVAUATSHHF dL<%( L}IAŃIAII)INt'8LLHL)L,I}pL9uHuDIcw 1HMJ<#jH}L HEdH+%( u#H[A\A]A^A_]f{1ZIEpf UH HAWAVAULo8ATISH(dH %( H]HHELaIEHE HtrIUHML<MuQ D MMt?IHAAƅtLHEdH+%( uGH(D[A\A]A^A_] D IEHEHMH9rLIxHEI9\E1 f. UHHdH%( HE1.HUdH+%( u D U HAWAVAUATSH 1dH%( HE1HDž 4H IH H=0 H IH H(H HHH f D LxH L`H Lw.IH(8 uM 1L L LUDAt$H0L?zD9LmEEL 1 LL UL1HHMAƅ H GD9) @ 9~ǫH H McE1ff. fH 1J<HU-H wDITM9uIE1HLITM9uHH LDpHaLhL HEdH+%( H L[A\A]A^A_]f Hs D HK 01161f. HH<HA9HH Z_ff. UfHAWAVHAUATSHh dH%( HE1)HDž HDž ƅIH LxMp HLp1E1HHHHHxf. IH k+IH H t<,2 LH o 1 LQHx1LHAą AHD H HAE1f D H 1J<0H*HރRRHLID9uHHDhLk/IHLp L LMtA HEdH+%( u]Hh L[A\A]A^A_]LpH5Lp1 HH<HA9HKD @ UAH HAVAUE1ATSHHH dH%( HE1HDž :PH1HHb 1ArMcIHt?1ېH 1H<H)LHPI9uEuAE I1ff. HHHL9uH<HEdH+%( uH L[A\A]A^] D U HATSHdL$%( LeA1虦HHtHD1 PH HHEdH+%( u HH[A\]f D UHHdH%( HE1HEdH+%( u ɿff D UHHdH%( HE1HEdH+%( up+ff. UHHdH%( HE1u@u#t HEdH+%( u<ɉ鿽 HEdH+%( u ɉ;HEdH+%( ukf D UfHAWAVAUATSHHdH%( HE1)EHE EH HuIH HXH HEE1HEQHE t<,uaH}EeDŤHHtIDDHE*NHEHD`j+HHt+EH{Hu M&AvH}nLoLuMtA HEdH+%( u"HHL[A\A]A^A_]f D Iif UHHdH%( HE1Hu0HuuVu:HEdH+%( uZH*f. HEdH+%( u8K HEdH+%( u HEdH+%( uɉ驻 @ ULd6 H HAWAVL5(< AUI ATSHHOLdH%( HE1ML*LcC~p1H&L LL5 A1LHIă{~<A DHAL LAH 1HID;{|H: L1HLHUdH+%( uH[A\A]A^A_]f UHAWAVAUATSH(dH%( HE1G IL}L5 1J H}_H r DHB 101c-HEHHHIDA9] LHE AătcEL HL1.tH}HUHu(hHUHE H}+H}j D H=@= |X HEdH+%( uH([A\A]A^A_]mff. f UHAVAUATSHwdL,%( LmI1IHtkIEE1AFHtTff. DDLAH[HAT!JH[ I| 讹HH؉HITI;]rA HEdH+%( uHL[A\A]A^]ff. UHHdH%( HEHcG~'HHf D HH9t9wu 1HUdH+%( u0 UHAVAUATSHdH%( HE1I9G~bLcHAIJ|/CDpE9} D)Jt+ J|+PHHDs1HUdH+%( uH[A\A]A^]øf. f. f. f. f. @ UHg HHH]r dH %( HMHH81 A UHHdH%( HE1Ht?HGG HG@ HGG( HGHF(G8 Ht HVH;<tHEdH+%( u&ËG HF4HGHVHF@H F0 UHHdH%( HEHHUdH+%( uNff. UHHdH%( HEHG(Ht&HWHHt@,HUdH+%( u D 1ff. @ UHHdH%( HEHG(Ht&HWHHt@0HUdH+%( u D 1ff. @ UHHdH%( HEHGHUdH+%( uMff. f UHHdH%( HEHGHUdH+%( u ff. f UHHdH%( HEG8HUdH+%( uff. UHAWAVAUAH ATIH}SH HdH%( HE1HE ~+HL}HA,C1LLA)C4.HEdH+%( uH[A\A]A^A_]% D UHHdH%( HEH HUdH+%( uf. UHHdH%( HE1H>HEdH+%( uff. UHHdH%( HEHF(Ht!HVHHtx,HEdH+%( uH=< Lff. UHHdH%( HEHF(Ht!HVHHtx0HEdH+%( uH=; ff. UHHdH%( HE1H~HEdH+%( uff. UHHdH%( HE1H~HEdH+%( ukff. UHHdH%( HEG|HUdH+%( u.ff. UHHdH%( HE1~|HEdH+%( uff. UHHdH%( HEH HUdH+%( uf. UHAWAVAUATSHH(H}HdL$%( LeAp!HIeI'1L IDCAu0I HUdH+%( H([A\A]A^A_]f D HEH}MDH HE Lp1# HLmHA?D1L)L UHHdH%( HE1H HEdH+%( uh UHHdH%( HEH HUdH+%( u*f. UHHdH%( HE1H HEdH+%( u UHHdH%( HE1HEdH+%( upff. UHAWAVAUI@ ATAHSHdL4%( LuIH D`A|$LHHcxHCH C %LHD8InIF(L+C4 Ht IVH; tHC, 1MtL*<C$E<$HEdH+%( u HH[A\A]A^A_]H=7 Gf UHATSHdH %( H]1H I1 I$H HxH fHǀ HH) HHI$H@( H@@ H@H H@T H@` Hǀ ǀ @ @1HUdH+%( u1H[A\] ;$ f D #$ f D UHAVAUL ATISHLH dL,%( LmE1*H L oHH HxH Hǀ HH) LHLH3\*HfH@( H@@ H@H H@T H@` Hǀ ǀ @ @1HUdH+%( u=H [A\A]A^] " f D " Vf D UHHdH%( HE1HEdH+%( u頫ff. UHATSHdH %( H]HH(HtlHC HPH9Ss HEdH+%( u}H[A\]f D L`HJ4 .HC(HtVHS fH @@ @0Lc fH HC(Ht fo2 H CtMH=4 UHAWAVAUIATSHHF(dH %( H]HH HSL$M u!HLD8I4HC(M,$AD$4 Ht HSL9$t ID$, 1MtL71҅HC(AT$$HSE>HЋB C4HBHHC@H HS C0HEdH+%( u\H[A\A]A^A_]f. H(HSHC( @ H{L$H(I$HC(HAIHSL$ UHAUIATSHH~(dH %( H]HH HC HSHHH9 HHL9tZHt'HC@S0HSHC(HK@HHHJK4J L(AE IU C4IEHSHC@H CP C0HEdH+%( H[A\A]]f D L`HJ4 ,,HC(H HS fH @@ @0H{(Lc HuIMtHCHS D H HC(Ht*H fok H{(CHtHSH=1 @ UHAVAUATSHdH%( HE1H |7 IH |7 u|Hֿ@ ILIHtnLhLHfnLhH fpH@ @( H@4 f@HEdH+%( uHL[A\A]A^] E1H=1 :f. UHAVAUATISHcHDkMcHLdL4%( LuIHh HDž Cڃ+ It$HH)H ( 1Hff. AoHH9u9 )rvI4 H4уȃtvHcA P9~dHcA P9~RHcA P9~@HcA P9~.HcA P9~ Hc҃A 9~ HA1LLf ǺHt_@ HUdH+%( uDH[A\A]A^] 1f D AHH9u11H=/ xӾH=o g UHATSHHdL$%( LeIHUdH+%( uHLH߉[A\]5p UHAUATSHdH%( HE1H IH~(HH HF HNHpH H9 HH8 t8HC@S0HK(HSH{@HH0H~{4~ Ht HBHCHL AD$ I$C4ID$HSHC@H CP C0HEdH+%( H[A\A]] LhHJ4 'HC(HtrHS fH @@ @0HCLk H H{(HHS FHC(Ht fo H 1CH=*- D UHHdH%( HE1HEdH+%( u鰬諼ff. UHSH(dH%( HE1HtgHF(HHt HVHH;8t&C u-HEdH+%( uMHH] H C tH{HuHu HEdH+%( uH]ff. UHSHdH%( HEHG(HtlHWHH<Ht\HHS(HCH HtHHCHt2HHt)P S4HPH HS@H HCCP C0HEdH+%( uH]G UHSHdH %( H]HH(Hu: D HHEHSHC(HH H{(H HCHHuH+HC( H{`HHC` H H HC( HfHC@ HHCH HCT HC` Hǃ ǃ C CHEdH+%( uH]1f D 1N ff. UHHdH%( HE1HEdH+%( uɸ ڹf. UHAWAVAUATSHhdL4%( LuIH rHH u~I AFH ANLuAFL I~ u I~ IF(H IVHH P AV4HPH IV@I IFAF0LPX(HE n Mf@AV0]L-X LL= Led L M L c MAH MDCLHxH HD IcHNADU D A6H=c <7HA4GA9t* AQf/~A<;HcADU HfA;4GuH=R! H HIHGHIADU QAf=HFHH IR)ff. @ HcH IHIIB tAMcCB9~LH m L L)L AS8AS0A Ls@`tHcH LeLLud! H= HcH>AFL HEIV@( IF(H@0 HEdH+%( ! Hh[A\A]A^A_]Hr I~ H IF}Hr H IFIF(HoLIVIF( @ I~H Lw IVHIF(HGAFL DL 虷I HH=*' D HcK8H Hff. : uH{Hs(H4F,F0 HH9uH HKHߋBB HC(H ȋA0BC8A0 HI辽8'HH3 芖I$ H HKIދBB HC(H ȋA0BC8 A0HExH t LX LIM8'IH IE H HKHߋBB HC(H ȋA0BC8A0 HI8'HH ĕI$ H HKHߋBB HC(H ȋA0BC8A0 HI螼8'HH. jI$ hH HsIBB HC(H4F0BC8F0S0H HKBB HC(H ȋA0BC8A0, H HKIދBB HC(H ȋA0BC8A0HEdH+%( H}HhL[A\A]A^A_]"]H HKIދBB HC(H ȋA0BC8A0HEdH+%( * HKLEIHH LeLEBB HC(H ȋA0BC8A0CL 5 LH*HIIVLHIF(H 8LE)C0IcF8~ I HЀ: uk,HH9uAF0 A$MF@M AF8 A AF0A MF@H HKHLeLuBB HC(H ȋA0BC8A0CL k HcHSHHC(H HM{HML] L YG L \ )A0HcC8~ H HЀ: ui,HH9uC0AMLc@L C8 A$C0A$ S0Lc@!H HKHߋBB HC(H ȋA0BC8A0H H HKHߋBB HC(H ȋA0BC8A0jH EH HKHIދBB HC(H ȋA0BC8A0)LH HHC H H HKHIދBB HC(H ȋA0BC8A0LHƸH螑HC HH HKHIދBB HC(H ȋA0BC8A0LHvHNHC HSH HKHߋBB HC(H ȋA0BC8A01H CL HLeLuHHSHHC(H HM HML[ L D L 5Z )A0HcC8H HЀ: ui,HH9uH HKBB HC(H ȋA0BC8= A0bH HKBB HC(H ȋA0BC8A0CL ,H HKIދBB HC(H ȋA0BC8A0 AFL/ H HKHcs8H PP HS(H ʋQ0PQ0HK Ls@S0LYZ L C L Y H HKBB HC(H ȋA0BC8: A0cH HKBB HC(H ȋA0BC8A0CL H HKHߋBB HC(H ȋA0BC8A0H H HKHߋBB HC(H ȋA0BC8A0H H HKHߋBB HC(H ȋA0BC8A0H H HKHߋBB HC(H ȋA0BC8A0oH QH HKHߋBB HC(H ȋA0BC8A06H H HKHߋBB HC(H ȋA0BC8A0H H HKHߋBB HC(H ȋA0BC8A0H UH HKHߋBB HC(H ȋA0BC8A0H H HKHߋBB HC(H ȋA0BC8A0RH H HKHIދBB HC(H ȋA0BC8A0LH HHC HH HKHIދBB HC(H ȋA0BC8A0LH踳H萌HC HH HKHIދBB HC(H ȋA0BC8A0pLHeH=HC HBH HKHIދBB HC(H ȋA0BC8A0 LHHHC HH HKHIދBB HC(H ȋA0BC8A0LH迲H藋HC HH HKHߋBB HC(H ȋA0BC8A0z VH HKHߋBB HC(H ȋA0BC8A0= H HKHߋBB HC(H ȋA0BC8A0 II INBB IF(H ȋA0BAF8A0 H HKHIދBB HC(H ȋA0BC8A0 HI蒱E I1LfE譴1HHb 1H5: AD D<1w\HcH>& HEH= Lh IHt'LlLA D1L)Lm H HKBB HC(H ȋA0BC8} A0H HKHߋBB HC(H ȋA0BC8A0H yH HKHߋBB HC(H ȋA0BC8A0^H @H HKHߋBB HC(H ȋA0BC8A0%H H HKHߋBB HC(H ȋA0BC8A0H }H HKHߋBB HC(H ȋA0BC8A0H DH HKHߋBB HC(H ȋA0BC8A0zH H HKHߋBB HC(H ȋA0BC8A0AH H HKHߋBB HC(H ȋA0BC8A0H H HKHߋBB HC(H ȋA0BC8A0H `H HKHߋBB HC(H ȋA0BC8A0H 'H HKHߋBB HC(H ȋA0BC8A0]H ?H HKHߋBB HC(H ȋA0BC8A0$H H HKHߋBB HC(H ȋA0BC8A0H H HKHIދBB HC(H ȋA0BC8A0LH褭Hx{H zH HKHߋBB HC(H ȋA0BC8A0aHIV8'HH "I$ C0LELeA$I@HC@C8 L APS0A@ H HC@HKBB HC(H ȋA0BC8 A0H HKHߋBB HC(H ȋA0BC8A0 "H HKHߋBB HC(H ȋA0BC8A0i H HKHߋBB HC(H ȋA0BC8A01 H HKHߋBB HC(H ȋA0BC8A0 zH HKHߋBB HC(H ȋA0BC8A0 BH HKHߋBB HC(H ȋA0BC8A0 H HKHߋBB HC(H ȋA0BC8A0Q H HKHߋBB HC(H ȋA0BC8A0 H HKHߋBB HC(H ȋA0BC8A0 bH HKHIދBB HC(H ȋA0BC8A0LH蛪HsHC HxH HKHIދBB HC(H ȋA0BC8A0SLHHH HC H%CL S0IiH HKHߋBB HC(H ȋA0BC8A0 qH HKHߋBB HC(H ȋA0BC8A0 9H HKHߋBB HC(H ȋA0BC8A0 H HKHߋBB HC(H ȋA0BC8A0H H HKBB HC(H ȋA0BC8A0CL { H HsL BB HC(H4F0BC8F0A EC0HSHC(H<HwLfL9s_HcGHTC4HHH9s(pHH@2Hs(H{H<HwH9rLfH)HcHIGC4G L9 ELqA< uHSHC(HЃh,L QLs@S0CL eHMHH+ EC0H{Hs(L$AD$8 HcC4MD$HK@I IHUH I9 ID H9 AD$4H)I΅ H3 HUIH HMDCLHpHK@H D I9 HHEA H I AIcADM HA<GD9t=HB4 DHfA/a HjI HcIcADM AHfE;GuH IDAHEH HD@HEHEI9^HMHH)HtLeLuIcH HKHߋBB HC(H ȋA0BC8A0k H HKHߋBB HC(H ȋA0BC8A03 H HKHߋBB HC(H ȋA0BC8A0 |H HKHߋBB HC(H ȋA0BC8A0 DH HKHߋBB HC(H ȋA0BC8A0 C0LELeA$I@HC@C8 L APS0A@ H HC@HKBB HC(H ȋA0BC8 A0LeC0ILEA$ID$IPH9r 8 uIvIN(H i,HI9uIV@M AF8 A@AF0A@ IV@IcAADM HA<GA9h A <觧H{Hp:I$茧H{Hp I$qI|$HpYH{HpI$3HKIcD$ C4I $AD$8 DaE q HJLH)H q D1HoA HH9uDH}I 8H4:A D)Dwv&H}H<:HUI<DDHHte>@9xA9~W~@yxA9~G~@yxA9~7~@yxA9~'~@yxA9~~@yA9~FAHs(H{L4A~8 DAF Ev$9NE IcDeE1IH}HI|$MVML F L / L D MD$I|$(AJ<H HD9uLDe f D } ! MƀHH9UEŻ fA$EAD$Eƨ@N @EEƨ m EEƨ EEǨ EEǨ EmEƨ EVEƨ E?Eƨ0 E(EǨ EEƨ EEǨ EHEL Lu Hx HELn LD HxHELZ LS HxHEL= Lb HxtHEL Lk HxQ1EHLH}1D14A4 HH9u7HEL LP Hx?HELt LH Hx HEL= LG HxHELu LI HxHELG Lh HxqH=g fCP H1LB L c, L A CLH pHK@ aH=+ HcEH HUIL5MA H LFHEHHK@HMKLLEL NHEI9 A$ t H=BA HcAD} HEGA9t2H+ x/ ~HcAHcAD} HEGD9uH n H IH ANoHE1HuH=B+ LEHH9uHBL wHcATu HcEWD9uH DQA/ tPHpH D E LuILs@Le {P t Ls@S0H{HD@H 裠H{Hp6} H=* PLDeH{0 DL@ L G* L ? K4H{Hs(E1C4H A A4;qv HAs4Hc0 HC(HKH HcC4HID HKHC(HHPH AKHUA H IHcUDCLM4HpLs@H D M9HHUHEHuA$ H > IcADM HA4GD9u2If HcHv> HcADM HEGD9tH) 4H/ @H IDAHEH HD@HEM9THUHuH4 NHcC4IHHEHyHHMD0IcDEHMDEL> L j( L = HAHKHC(H Hy t9s4A@AD'1C4AF Et%H C4A A8 H= H{HA 5HsHK(Lf> C4L ' L = H H= @HpHxM E1HxHpHD HcEDeHEIcIHHER I|$6L= L X' L < ;t I|$It$(I|$HIL$ HUH}HxL= L & AD$4HL (< rLDeHC(HKH ȉq H= 9LDepLH}ANMcHsHC(DeHHxB7 AHELR LW HxAHEL Le Hx` f. UHATSHdL$%( LeIH?H HI9u 2 D HHWfHnflHSHHHHL9uHEdH+%( uHL[A\]销菐ff. @ UHAUATSH(dH%( HE1 ~ O H Y HcH>f ~{ H \ tRHEdH+%( H>H([A\A]] D HEdH+%( H>H([A\A]] t3tff. HEdH+%( ? H([A\A]]fL.I} H HI9t>ff. HWfHnIflHSH葁HLHM9u HEdH+%( H(L[A\A]]+ L.I} H HI9tf D HWfHnIflHSH!HLHM9u두L.I} H HI9zf. HWfHnIflHSHрHLHM9u>f D L.I} H HI9"fHWfHnIflHSH聀HLHM9uf D L.I} H HI9fHWfHnIflHSH1HLHM9uf D H>Hu}HuHEdH+%( W H~ @ L.I} H HI9RfHWfHnIflHSHHLHM9u f D L.I} H HI9fHWfHnIflHSHaHLHM9uf D HEdH+%( H>H([A\A]]鳜 L.I} H HI9f. HWfHnIflHSH~HLHM9uNf D L.I} H HI92fHWfHnIflHSH~HLHM9uf D L.I} H HI9fHWfHnIflHSHA~HLHM9uf D L.I} H HI9fHWfHnIflHSH}HLHM9u^f D L.I} H HI9BfHWfHnIflHSH}HLHM9uf D L.I} H HI9fHWfHnIflHSHQ}HLHM9uf D L.I} H HI9fHWfHnIflHSH}HLHM9unf D L.I} H HI9RfHWfHnIflHSH|HLHM9u if UHATSHdH %( H]H^HtH;t HEdH+%( uGH[A\]f D IH=, jHHEdH+%( uAt$ HH1[A\]Pۉff. UHAWAVAUATSH H $ H fodT E1A EHLL HdH%( HE1H LLIHHDž Dž DžH))HE/JI9K LHH)HLpH' G" H۸' H9HNHHHH| wHw" LLHIH[ LmHILHLHIILHLH`mLHLHHH HHIHHH4mLHHI9t$LLHxLHHLIN$3ILPMKI9(! HHLA)E McHU B A= HHdS < HT F EJ D f HcHR < h Dž H_S D,EAE foDžAD$foIIA HcH5T <9A= HH=4R D: dHS F Eu <HS F E HP McfAnNfAnV B )AHHLHH@H? HҸ H)HLfn fnXfbfbAflA=wwHvN JcH>HAL$E1MLPI$H L`)pj _AXfopL`LP HIHLHI)HH)HpL`H54R HX H)HIHO BAA H wHcH5P : D HQ D,IE fofo HQ F E D Dž f. tGD HYQ F Ek Dž Dž HHH HLpLӣLDLpH[Q B LDH 5M MAff. @ t wHcHO <d L9 AEEu HjN B <+ HcH> D M $I9HHI9tnL`LpMLPIff. HWfHnMflIUL*tLLMm M9ufML`LPLpL rMGIIIH(P B f D I<$q D I<$ z D I<$菑 D M $I9HHI9tL`LpMLPIff. HWfHnMflIUL*sLLMm M9u D M $I9HHI9L`LpMLPI HWfHnMflIUL*1sLLMm M9u D M $I9HHI9L`LpMLPI HWfHnMflIUL*rLLMm M9u= D I<$opI|$ep@M $I9HHI9"L`LpMLPIff. @ HWfHnMflIUL*1rLLMm M9u D M $I9HHI9L`LpMLPI HWfHnMflIUL*qLLMm M9u= D M $I9HHI9:L`LpMLPI HWfHnMflIUL*QqLLMm M9u D M $I9HHI9L`LpMLPI HWfHnMflIUL*pLLMm M9u] D M $I9HHI9ZL`LpMLPI HWfHnMflIUL*qpLLMm M9u D M $I9HHI9L`LpMLPI HWfHnMflIUL*pLLMm M9u} D M $I9HHI9zL`LpMLPI HWfHnMflIUL*oLLMm M9u D M $I9HHI9 L`LpMLPI HWfHnMflIUL*!oLLMm M9u D M $I9HHI9L`LpMLPI HWfHnMflIUL*nLLMm M9u- D M $I9HHI9*L`LpMLPI HWfHnMflIUL*AnLLMm M9u D M $I9HHI9L`LpMLPI HWfHnMflIUL*mLLMm M9uM D HAH D EfoDfnMfnfnIIA$fnLfbfbDž flAEEfLt)HcH= HI <WA HI9tLjHEdH+%( n HeD[A\A]A^A_] HHHL`pLrfL`pL ZHF D, HG F E(cDHL`pL9L`DžpL`f D H)G F ED s Dž LA HcHG < I<$I\$HH9tHKHWHHHHHSLPL`)phfopL`LP1I\$DDž 3LE1 M9xH C fILII<M9uMI $' LPL`)pfopL`HLPI$H% HL@LPHp)`,qHSHpfHnfo`LPfHnHCL@flHI\$I<$H1 HCfHnH{fHnflH8M LPL`)pfopL`fHnHHHLPfltGAT$HLPL`)p9fopL`LPILHI)HI)HHHH ē A ܖ LPL`)pfopL`fHnHHHLPfloIL$IT$L8M $MD$L@)PHH`謯I<$p nI|$epH`foPL@L8HDLeHHI)HI)ԃpA I\$1LPL`H)pfopL`LP0I\$I|$LPL`H)p觀fopL`LPI\$I $LLPHL`H)p蜿fopL`LPILHI)A HI) I<$HH9HHWHNHHHH2HVeHI $At$E1LPHMNL`)pAV1Y^fopL`LPIA LHI)HI)̃W HLPA4$HL`M A )pj s LPL`)pfopL`fHnHLPHflIT$M$HHL8L@Hq)PH`I<$p#kI|$bDpL`foPL@EL8LDL D H L@LPL@)`Lp Lpfo`fHnHHHLPL@flHIFM $L8IL$L@IT$)PHPH`qI<$pjI|$aI|$aAXAY LPL`)p]fopL`fHnHHHLPflIT$M $E1H1L8L@H`)PI<$pgi_ LPL`)pþfopL`fHnHHHLPfl*IL$IT$E1L8M $L@)P LPL`)pHfopL`fHnHHHLPflIT$M $1MD$HL8L@H`)P LPL`)p軽fopL`fHnHHHLPfl"IL$M$E1AT$HL8L@H`)P!V L@LP)`-fo`LPfHnHHHpL@flL8L@)P1 H`ID$HxL`foPL@L8A0FI|$L8L@)PH`^H`M$E1HpH I<$`f`foPL@L8gHpDL?^HHI)HI)ԃ` @ I$I\$HHI$ ML`HA LP)pj A[[HLPE11L`I $MNHIT$)pAVbfopL`LPXZkDLI|$F]HËA HI)HI)ԃ I $IT$1MHMFLPL`)plfopL`LPI|$DL\I<$YI $L@LPH)`cMHpHH/ E1HMHپ lfo`LPL@CI<$DL \Hp\HL⋵HHH)LH) IIzfHHx v HI$HF A$At$INMHLPL`)ppI $H= LPL`)pCLMMHHH j,LPI $M1L`At$MFH)pI$It$MFHHLPL`)pHDž rI<$cI|$ZfopL`LPIA LHI)HI)ԃIt$I<$LPL`)pͥI $fopL`LP=EHL IHI)HI)p I\$I $LLPHL`H)p蠁 HLPM1L`I$ H)pA j pAYAZrIL$п L0L8H)@HpPAA D`D`PfHnHHHfo@L8flL0NHcpMD$AHL8L@)PH`N~I|$p`DpH`foPL8EL@HDL_f. HIt$1HMFLPL`)p I|$fopL`LP LPL`)pWHfopL`LPIL$ L0L8H)@HpPAA D`>D`PfHnHHHfo@L8flL0HcpHE1AL@LP)`|fo`LPL@ILHI)HI)̃i9 @ HcH5J5 MA 8IDDž 7DLI<$DL^H7fLDLuDLHH H HXHH1y 1HHH= HFAvHHHA wI|$UHHI)HI)ԃ @HLIIf. UHAUATSHHHdL$%( LeI(pHHILG]1uVJ<+ tF1_Lr 1HH!f D @u 0 @H: t- ADu1HUdH+%( u(H[A\A]] @tH)HMdff. fUHAWAVAUATISH(dH %( H]H, HE |H LDHEHH L}L5$ LLceHInLLH\t: @ MtcLMnHLL1 eHLIuHHu1H}oSHEdH+%( u?H([A\A]A^A_] LH f HL c1 UHATSHHH?dL$%( LeIHvt HEdH+%( u3H1[A\] @ HEdH+%( uH{HCHL[A\]b UHHdH%( HE1fw HHGHEdH+%( uTb @ UHAVI1AUI ATSHdL$%( LeIHBHHtYH5 LLA$E1 HٛHQHEdH+%( uHD[A\A]A^]Aa D UHATSHdL$%( LeIH=~ 赙Ht`HHBHHtP=1t t HEdH+%( uJHH[A\] @ Hr Hٿ H~ 0191t LHHu`f UHHdH%( HE1HEdH+%( u1G`f U HAUATLmSHHXdL$%( LeIHLxfuDE1HMк LL1 EtFL>oHEdH+%( uCHX[A\A]]fHr HH 11ۋ012L8kHcUH9_ UHHdH%( HU1HUdH+%( uHH6 HHH@_ UHHdH%( HE1H t&HEdH+%( u(HH=D% HEdH+%( uB_f UHHdH%( HE1 tHXr H HEdH+%( u^ff. UHATSHdL$%( LeI [H H= H?HHtxC C H HC0HC8HC@HC8HCHHCPHCHHCxHCxH ID$IT$L H HHEdH+%( u HH[A\]H'N 1^ UHHdH%( HE11HtP HEdH+%( uɉ]ff. f UHAUATSHH_8dL,%( LmLo8I9t&IHI9tH{L茡uH{Hu'1HEdH+%( J HH[A\A]] @ H 1fuHфuHuHuHA H 1LQHH ƃ?vLHHH!bukH 0 fuHʄuHuHt`ucJLHH LHHH!tff. f 1 H 0 D t LHH ;f D J \ff. UHAWIAVIAUATI SLHdH %( H]H5Ht`LhLLKIu%HHIT$HEHH1H!H1I\$HEdH+%( u%H[A\A]A^A_]f LLEKN[ff. UHAUATLg8SHdH %( H]H_8L9t%IHL9tH{L u 1HUdH+%( u H[A\A]]Zff. @ UHHdH%( HE1G HUdH+%( uZff. UHHdH%( HE1 uHUdH+%( uf [a.Zff. UHAUATSHHL/dL$%( LeILt={ u'C t4H5 L f LLutʐ HUdH+%( u H[A\A]]Yff. UHATSHdH %( H]1ہ wGw)HEdH+%( uZH[A\]f D tL'H5v L tH5 L tH5 LXf. UILcHAWAVAUATISHH " dL,%( LmM7 H8Mq8A L9u+ ff. ff. @ H?L9 DG fAwHwAA!HtH 1fuHфuHuHuHK H LDyHH ?4 LDHHH! ' H 0 A fuHAτuAHuAH AOLAHH 덐AA"Ay! tK٘ HL!HXu=HEdH+%( He[A\A]A^A_] H 0 D L`d @ HXL HMMH H HDH~r H10ATH1ʰXZf K 3 E1 t ADLAHH AOmRVf U HAWL=s AVIAUATSH(L'dH %( H]HLHLkjNL LLETNID$LLDL HH5Rs EsMHHt1LLMyMtnMfMtEL LMLID$LDLMuHt1LLUyHEdH+%( uH([A\A]A^A_]ù $U @ UHHdH%( HE1HEdH+%( u FP T UHATISHdH %( H]H٭Ht4HHEdH+%( u<HHL1[H` A\]6|f D HEdH+%( u H1[A\]aTUHAUATSH H $ HdH %( H]HLI LPoHHu!HEdH+%( uQH [A\A]] @ IM L I<H)Hjq 1{L11;ǃtCq KS @ UHAUATSH H $ HdH %( H]HLI LnHHu!HEdH+%( uQH [A\A]] @ IM L I<H)Hp 1zL11ǃt_JCpS @ UHAUATSH H $ HdH %( H]HLI LmHHu)HEdH+%( H [A\A]] IM L I<H)H-p 1 z1L1AŃtHsH +DIHx+IB|#G tBD#H o BD#G \`ICH NRfUHAUATSH H $ H( dH %( H]HLI LlHHu&HEdH+%( H( [A\A]] D IM L I<H)H?o 1 yL11AătH譁x<LP DLHx O t#ƄP HSh1LoDUHJƄO P UHAWAVAUATISH(HZdL,%( LmIՀ{s t {t 4 LKMt$M<$M MtLLLM:B LKMt$(M MtLLLM LKMt$ M MtLLLMސ AD$@I|$ CptMH{ }IEIt$1Hx 4Åt*HEdH+%( He؉[A\A]A^A_]f D I|$81HtIEHuHPhknÅuI}HM 1H> HHe @ Mu HLqHLfHLHLI] HLML Hvr LF H 0AV10H{qL/HCI]_M<$LKMt$(AXMnML/LKHCM<$Mt$ Mq ML/HCpf D HLML HAvr H LQl 0AV1耨H{qL//HCI]XZHLML Hur Lk H 0AV10H{pL.HCI]YM<$^ @ M]L.HCM<$HM D UHSH H $ HdH%( HE1賦HtDHH1 HHE u H1HUdH+%( u H]ø>Mff. UHAWAVIAUIATSHH(dL<%( L}I-hLcMt(L XLHEXHUHIDHH9r%HEdH+%( uRH(1[A\A]A^A_] D HEdH+%( u-H(L)K|% MHL[1A\Hk$ A]A^A_] tgL UHSH H $ H( H +j dH%( HUHHHHHHZAx6HHD HHUdH+%( uH] 1K UHATSH H $ H dH%( HE1~" t$HEdH+%( H [A\] D HLHH i L tLsVLI</ fHHsH)H 荋LH5"& IHnH}tLXQ D HLaHHBHFzC"LJXJ UHAUATSHdH%( HE1 H;=sr G ItvH_8Lo8L9ug HL9tXHL}DK fAvHEdH+%( uLHqr I $H 1LC0H1[A\A]] HEdH+%( u H[A\A]]I UHAVAUATSHH_8dL,%( LmLo8I9tSII HI9t@H{L蔍uHLC HUdH+%( uH[A\A]A^] D DI @ UHF8HAWAVAUATSHhH}MMdL4%( LuL2HpEL9V HuLo8A HULxA~0 % L' HEI^HH8I9X HMI M?M9 IH蘌uH}LAG f* H]fLKLEpAF D A~2 IvIHuLMTLMHu ? A III9s } F 1} E 1 IGHsHs LHI HHH@uf M6L9u1HUdH+%( Hh[A\A]A^A_]HMH]fE1Hpr Lx)EHEL}MMIHEH HSLH5i6 HD1x HAI9uMLL} @ uHMFA8? Hnr Lx0 H=6 Mt'HAv,1L#Xf 1" @ HHI#IHHH@IWHsHLsHI fuHEL E1?HELH@Ax :HEHH9tCLMHLmMIf. S uH{Ht IutsHI9uMHmr IVH5 1谥ILMɓLMSLxH=~c MMLMLmC0Hs#Hnr fLxH])EHE1H ;IHUHEINHH3 L 1DyHE LNHUIM Av(HLAVL4INHb 11ОLH H}1HK LxƋHUH=b iDf MLL}E1!Hlr Hѿ H/b 01OH}&4P UHHdH%( HE1HEdH+%( uI1H( 8Cff. UHAWL8AVIAUATISHH_8dL,%( LmIL9uVf D HL9tHHLS HsLHKAՅtHUdH+%( ujH[A\A]A^A_]f 1A~ L=rq t"I41Hv$1LAՅuHHu1f. LAՅuHBf UHSH H $ HH l dH%( HUHHHpt HHUdH+%( uH]wB UH5 HATA SHdH %( H]HOtH5? H<u HEdH+%( u"HD[A\] D H AAAf UHSH H $ HHdH %( HMHH H耎t$HtH5 Hq 1HUdH+%( uH]lAff. UHATISH HXL`Lht#)p)M)U)])e)m)u)}dH%( H81HEDž H(H@Dž$0 H0 HHtCLHH 1THAFNH8dH+%( u H D[A\] D As@ UHSH H $ HHdH %( HMHH H 1tH耎HUdH+%( uH]@f D UHAUATSH H $ H H $ HdH%( HE1IItp tdIEHIHHXI9uIf HC0HXI9t3H;L8uHEdH+%( H H[A\A]]1 @ HHH] HfLbJHtLH5jr HH<ff. ff. f BHHȈBH9uHLVlueLIHtEH5ir HH<ff. ff. JH HBH9uHLkA}p H H~YHHIM H<H\ H)1eH߾ 1膹Ãt1L N5=f HH9C^AEp=ff. @ UHAWAVI1AUIATISLHhEHMLE|dH%( HE1HE tHt/E1HEdH+%( / HhD[A\A]A^A_] HO IHC(HEHC HpHC8HEC@zCAH[0{HtHH5 ID߿x q_IHT H@ HHEA6H 6 AGH HUHuAGq IOhzH}AOp{AOr AZ LR IM& L> H} IG H}& HEIGHpHtH HpHpIGHt H HH}I_@Ht0IWhHuZt HMIH 1H ;R| I|$XAGsHt&LELLLeH L}6L AD$`ID$PI\$HIW0fHnIT$PfHnflAG0Hf. H} IG HE @ Hbr HMHqY 1DE01 L*DEf D HDžp HE ƅz ƅ{ fAD$h= D AD$d- D LxHEM AD$lAL!]I]I]I]I@\H}=gL5*A%: D UHATSHdH%( HE1H tHH0HtH2Iu HEdH+%( uFHe1[A\]f D It$H{R}tHHSHKIH3jE1LXZ9f D UHAWAVAUIATSH(udH<%( H}ȉTHY Hf HYH/ x.LpuA~ tހx.uA~.uA~ tf. L(DIHvI|H5V |tItdK|&H5V |{IvEK|&H5WV |\I t&K|&H5"V |=ff. f}1L1hAă H5] 7 IH H11E1j ILL`ZYxJLEHjXHHTAEpHEdH+%( umHe[A\A]A^A_] D H_r L HHV 01ё Hi_r L HV 01詑DD.7r7fUHATSH H $ HdH%( HE1p t$HEdH+%( H [A\] D LH L9RHHtH I<HHU H)1^L 1FAăt H߉DD .s Cpc6f UHATSHdH %( H]H DchDc`{q t.CdIC LHUdH+%( u.H[A\]f H{XHtH?aSlI)I 6ff. @ UHAUATSH H $ HHIT HdH%( HE1LI Lu]11 LRet5L!,HEdH+%( uH [A\A]] D AD$pk5ff. UHAWAVAUATSH H $ H f@1HHdH%( HE1H@H`H8HH0hx+9L8Azp 9 IrXHt Azq IBHIRHLH`HXH9i HL(H - HPHDžH HC0HXH9 H{@H HtH(x ;?H{ HDžp H8 HA ME1Ls Hh{H ChHDžx u f.- ztQLLLKH LKR H L LxA 跫L HLM,I)oCH0LL)PL1H LD8LQ LHCH HHHPHCrHZY H@ RH01|<L H(H8Xf k#H{ HDžp H8pH(x L u(L6#IH(L H(L LN=I3LP 1AT LLs 3Lc AXAAYM9u eM$$M9t[A|$ uID$ML$1A D)HcHIcLIP HPL 1ʩM$$^A_M9uA ƅ H(Lhx tHLpHhLA e<LXO, M)Q D L(1Az H08*8HUdH+%( } He[A\A]A^A_]fIcƄ/AELHƄ D @ LL8Y[L8ABq L LKL8HHI I<HN H)1W1 L螫L8 LL8T'L8? M 1HL L8HhL8fƅ H)pH`I))HHbABp_/ff. @ UHH dH%( HE1Hu1HUHUHMH -HUdH+%( u/ U1IHAWAVAUATSH H}L6LXdL$%( LeLe fBIH HB HxfInfl)@L9 HpHEHUIH`fLx uTAF ulA~2 tEHEI^Lx8HH8L9tmLuMI @ M6M9D I~H(ru @ LxIL9p" Hx뀃uI~H5; nuI^H} HIHV fAnf(Lfpf] 'I_ IO H9 LhIH0f D HEHMHUHE@1L HP(HHHM?L9tfLLctL5ZH=K Av(HX1H>HEdH+%( HĘ [A\A]A^A_] D LhfInHEfl)UL9t!IHuLpfo@IHHq)}LYH`A^( As t7At u0H}LzH}LnH}LH}LHEH8 t AH HEff.hztffA.h HuAGq~ tk AH AGhfIGHHf.zt HE@Ap tHE@IIFLfouHBHA6h; AH tIOHHAGhff.zt H]CtHE@f L}Aq AIXH4MH HL;L1HIHXf AGhff. LuLMI9 AIt3ff.zt1 @ H2 IH$ 1IAH IH= \ HX1H»;KH= H=7 H* UHATSHdH%( HE1Htm IH H¸ Ht HUdH+%( uEH[A\] A|$q u(I|$XHt E11HLn: 1) UHAWAVIAUATSHHL/HGdH %( H]HL1HE LHEHTHt'HEdH+%( ? HH1[A\A]A^A_] IIF(HEIF HEIF8HEAF@EAFAMv0EMtH5 LlMEx iKIHzH@ HHE9"AFH Hu1H " H}AFq INhMANpMANr LU IM LA H} IF H}) HEIFHEHt H HEHEIFMt LIH}Mf@Ht0IVhHuF HMI~H 1H G>HCPHKHIV0CdfHnHSPfHnflAF0HY H} IF ;HE? @ HAOr HMA112HE 老LX L(HELII~II~II~II~@IH} TL& UHAWAVAUATSH H $ HH r dH %( H]Ht.CtHUdH+%( HH [A\A]A^A_]f D Ct HLH HE L3s HL謇 LFIH HfLxFH/ x.LhuA} tހx.uA}.uA} tf. 1L1nUAƃtH5 HH* L@H¾ LQMH HCx HHIH L?IH L{0LHp IGHtgH IO~H HfHnflAGHCt2LSEHf. LACrL~GLff. @ HD2 Cr1~$DQ UHAUATSH H $ HdH%( HE1LIAH HL KDLHUdH+%( uH [A\A]]#ff. @ UHHHH0dH %( HM1XMx$HEdH+%( u&H5 vf D HEdH+%( u1h# UHAWAVAUATSH H $ H H B ~ q H AHfHnʺ LflLdH%( HE1)HDž HHH=fHDL2IHtHbLH70Hu'I\$IHuĀ t趁H讌HHEdH+%( uH H[A\A]A^A_]B"f UHATISH L`Lht#)p)M)U)])e)m)u)}dH%( H81HEDž H(H@Dž$0 H01HHtBLHH 5HA-/H8dH+%( uH D[A\] @ A[!ff. UHAWAAVIAUAATSHXH}HUMdH<%( H}ȿ CH LHHH 1LEH DH% HAy HKHHC8LDfHnHEfHnHCxflflɹ CHfHnH> flK8Cx*JAƅ ;IH Ee L@H x.LpuA~ tހx.uA~.uA~ tf. ( BIH L IGHL HC@~EL{@LfHnflAL8 @HxL<L}L胈LDC 2 LDHC0EHV> C!IQ C LHCLuH т D1MH > HEwEDHHR C$a.HE HE IHU H}H LAgH0 tHUHD8 u D LX,HEHCHHHCX RHMH HHAfHnHQfHnfl HT} t5DHH(f D LH; H@H01HEdH+%( HXH[A\A]A^A_]f x.u:~.u4~ u.LF>H&x.HpuӀ~ t߀x.t ( HuF@IHVH}}HuHIG HC@~EL{@1DfHnflAL81MDž H5a E:}H H}HEPHUt!H*. @ C HuH茈HuLpH}wLHUAG"Hv*LzLU9Uo L@*1L L9D Lr9ff. f UHAWAVLw8AUATSH(Lg8fo ;( dL,%( LmII $)]M9tDff. ID$foEI|$IHCHA$>LI HM9uIUHfo%' MuHHHZ)eL`I9tlf D HS8foMHHPHK0K>H{B>H{9>H{0>H{@'>H{ gHHL\ ID$0HS0L`L9uIUxfo->' MuxHHZ)mL`I9tHf D HSfoUHHPHS=H{=HL ID$HSL`L9uI}0uL=I}{=I}r=HEdH+%( uH(L[A\A]A^A_] UHAWAVAUATSH H8dH%( HE1H IIt$XHt A|$q ID$HMl$HLxI9t]H@E1ff. H߹ IW LHH@LHWuH8H9HtPIG0LxI9u1HUdH+%( u7HĨ [A\A]A^A_] LXDAD$qR D I~f. f. f. UHAVAUATSHLwHdL,%( LmIH~M;u K IHI] HHtHH{I|$HtHH{I|$HtHH{I|$ HtHH{ I|$(HtHH{(I|$0Ht~HH{0I|$8HthHH{8I|$@HtRHAD$PIH{@CH1MuHUdH+%( u7H[A\A]A^] @ HH?r I1H08 019r ff. f UHAWAVAUIATLgSHHG0dL4%( LuIG0 M I>evy@ IL)L=7 ILwL=7 L1L"IA1{0 1҅OEDIHEdH+%( HD[A\A]A^A_]L5x L1LLHA1{0LLH1H @ , LK?{0", H4? LLLHgHOff. fUHAUL-Ses ATSHHEes dL$%( LeIL9thHx/ H{Ht L_Zt"H HxL9t0H;L=ZuHEdH+%( uyHH[A\A]] @ Hds L-ds HxL9u.D @ H{Ht LYtH HxL9tH;LYu 1xff. UHATSHdH%( HE1H H~ 8t.)HUdH+%( ! H[A\]f. IHv8HH8HtMHH| HDYuHI$H H Ht-:J H5R| Huf ]It$@H{@HtuHH$| HDX4HEdH+%( uYIt$H{H[A\]uX D Htрz f. H9uf H5{ Hu ff. fUHAWAVAUATSH(dL,%( LmA" AX/HH Hubs L5~bs HEE H4Htsx.LxuA tx.u A.Y LHuĀ=s uLC| =s H= bs u1LDMH3HuH(0M96 H x 1LHHu1HM96tos Eubs HEdH+%( H([A\A]A^A_] x.tBL{tLHtAH2H_x.LxuA tހx.uA.uA t =s uL/{tk=s H=`s u1LDL @ A m L/HH9r H 101lH=`s H=y`s yHEdH+%( uH(D[A\A]A^A_]f. UHHdH%( HE1Ht@ uQH H `s HxH9ʺ HDHUdH+%( uD =s u1H=Q_s H H _s HxH9uH= _s UHATSHdH %( H]HILc~WMcD1H8JL ff. f H ƃt HGuA9tHcʀ| _HAtLHUdH+%( uH[A\]@tA)A~;ff. UHAWAVAUATSHdH%( HE1H L/Hw Dw HMLDL AE H L=x^s L5Jw HxL9 H;HID A9u H3IcLHID HEdH+%( HH[A\A]A^A_] =s u18L-v E1H o]s H L=]s HxL9tKL5v H;HIDA9uH3IcLHIDMeH HxL9uH \s f D H HxL91"ff. f UHAWAVIAUATSHdL,%( LmISILHLLI9HHIFI9u<u8Mt3LIE1SI9r>LHBH1H9r@L9HUdH+%( uEH[A\A]A^A_]ÐK<& 1I 1I| I9s f D UH u HHdH %( HMHHxHHDHxHHDHEdH+%( uG UHATSH H[s fo" dL$%( LeL%[s H)UHxHxL9t@ @ H foEHPH ! HH H HxL9uH][s fo L%N[s HHx)]HxL9t@ @ H foMHPH HH H HxL9us s HEdH+%( u H [A\] f UHAVAUATSHdL$%( LeIHHHt(HEdH+%( HH[A\A]A^] D =.s uLtAƄ| =s u^H=GZs A1LD7FDHHu=s uEt =s u A7HEdH+%( u)HL[A\A]A^] @ H=Ys A f. UHAUATL%Ys SHHYs dH %( H]؉L9tMHx @ H HxL9t-;XuHUdH+%( H[A\A]]f. H)Ys L-"Ys HxL9uyf D =s uw1@H Ys HxL9u0kff. ff. D H HxL9t=;Xu[ H HxL9t;Xu; 11f HyXs HxL9u0ff. ff. D H HxL9t;Xu~ ff. UHHdH%( HE1Ht0H H Xs HxH9tVHUdH+%( uK D =s u=s u HWs HWs H9tH- f 1 UHAWL= AVL56& AUATS1HdL,%( LmIff. H HHt`L#LLLtN LL uI|$L]Lt) LL uI|$L8Lu @ HEdH+%( uHH[A\A]A^A_]f. UHHAWAVAUATSH HhH}HxdH<%( H}HR AĄuH 2r E1E1 D LIALIHuMcK<LEH *LEHHE DmL5MMHELEHE HUALL LIHuDmH}P LH i;EZ EAe E E1DmD} MH= IEJuIw@H}JtJHMNMFLH& Iv8Av0HUAv(HxAv PAFHPHEPLuH0II~(H}HH(H}HH(H}HH (H}HH((H}HH0(H}HH8(H]H{@(EME9}JHELN4 IPN< IN@MnIwHMHLH5 Mf D DmAIcLeLxH HHEHH=% AHLHL@HHHP@Hp8p0p(p @HWLPAT$H}HH0H'H}HH'H}HH'H}HH 'H}HH('H}HH0u'H}HH8e'H}HHPH@Q'E9.H}?'HEdH+%( u4He[A\A]A^A_]f. H!,r Hx 101g^@ UHHAWAVAUATSHhH}HxdH<%( H}HR HuHH/r HU1gH5?$ L15H52$ L1~5HuE1H] j E11AVHx1PHEj HMPLH0fLfHHEHH H;fE1LeH,r )ELmEHEHEE /{ H LAHw H5t# LED14H DLH5V# 14HLHMH}H56# L14 D HEdH+%( uHe[A\A]A^A_] D UHSHdH %( H]H.Ht)HHEdH+%( u.HH]?f. HEdH+%( uH]14 @ UHHdH%( HEs u)1f os THNjas HuHUdH+%( uff. UHS1HdH%( HE16f D s1H t HvTHHu 1s HEdH+%( uH]>ff. UH=s HHdH4%( HuH5Iys HUdH+%( u UHOs HATSHdH%( HEHvOs H9t1HUdH+%( HxH[A\]jf. KÅ IH ff. L Htcx.HXu{ tx.u {.u{ tѐHhtHLH Ht$HEdH+%( uNHH[A\]ÐL HEdH+%( u*HH= [A\]HEdH+%( tf. UHHdH%( HE1HEdH+%( u1^RYf UHSHdH%( HEHh HtHUdH+%( ubH] D HBKt#Hu 0t%{ Aff. fHh K @ UHHdH%( HE1HEdH+%( uH H=$Ms /9jf. UHg8 HHH](r dH %( HMHH81 A* UHHdH%( HE1Ht?HGG HG@ HGG( HGHF(G8 Ht HVH;<tHEdH+%( u&ËG HF4HGHVHF@H F0 UHHdH%( HEHHUdH+%( uNff. UHHdH%( HEHG(Ht&HWHHt@,HUdH+%( u D 1ff. @ UHHdH%( HEHG(Ht&HWHHt@0HUdH+%( u D 1ff. @ UHHdH%( HEHGHUdH+%( uMff. f UHHdH%( HEHGHUdH+%( u ff. f UHHdH%( HEG8HUdH+%( uff. UHHdH%( HEH HUdH+%( uf. UHHdH%( HE1H>HEdH+%( uLff. UHHdH%( HEHF(Ht!HVHHtx,HEdH+%( uH=j ff. UHHdH%( HEHF(Ht!HVHHtx0HEdH+%( uH=~j 1ff. UHHdH%( HE1H~HEdH+%( uKff. UHHdH%( HE1H~HEdH+%( u ff. UHHdH%( HEG|HUdH+%( uff. UHHdH%( HE1~|HEdH+%( uff. UHHdH%( HEH HUdH+%( uJf. UHHdH%( HE1H HEdH+%( u UHHdH%( HE1HEdH+%( uFff. UHAWAVAUI@ ATAHSHdL4%( LuIxDH D`A|$LHHcXDHCH C ULHD8In_IF(L+C4 Ht IVH; tHC, 1MtLJl#GC$E<$HEdH+%( u HH[A\A]A^A_]H=g gf UHATSHdH %( H]1H I1 zCI$H HxH fHǀ HH) HHI$H@( H@@ H@H H@T H@` @@1HUdH+%( u5H[A\] sT f D [T ff. UHAVAUL@ATISHLH dL,%( LmE1EH L _BHH HxH Hǀ HH) LHLH3HfH@( H@@ H@H H@T H@` @@1HUdH+%( u9HĠ [A\A]A^] @ KS f D 3S f D UHHdH%( HE1HEdH+%( ukff. UHATSHdH %( H]HH(HtlHC HPH9Ss HEdH+%( u}H[A\]f D L`HJ4 `HC(HtVHS fH @@ @0Lc fH @HC(Ht fo H CtH=d 1 UHAWAVAUIATSHHF(dH %( H]HH HSL$M QHLD8Id[HC(M,$AD$4 Ht HSL9$t ID$, 1MtL<hC1҅HC(AT$$HSE>HЋB C4HBHHC@H HS C0HEdH+%( u\H[A\A]A^A_]f. H(HSHC( @ H{L$H I$HC(HyHSL$H UHAUIATSHH~(dH %( H]HH HC HSHHH9 HHL9tZHt'HC@S0HSHC(HK@HHHJK4J L(AE IU C4IEHSHC@H CP C0HEdH+%( H[A\A]]f D L`HJ4 |]HC(H HS fH @@ @0H{(Lc HuIMtHCHS D H =HC(Ht*H fo H{(CHtHSH= b d @ UHAVAUATSHdH%( HE1H |7 IH |7 u|Hֿ@ I\=IHtnLhLHfnLhH fpH@ @( H@4 f@HEdH+%( uHL[A\A]A^] E1H=ga f. UHAVAUATISHcHDkMcHLdL4%( LuI<Hx HDž Cڃ; It$HH)H& 8 1Hff. ff. f D AoHH9u9 )rvI4 H4уȃtvHcA P9~dHcA P9~RHcA P9~@HcA P9~.HcA P9~ Hc҃A 9~ HA1LLf '#Ht_@ HUdH+%( uDH[A\A]A^] 1f D AHH9u11H=_ H= UHATSHHdL$%( LeI HUdH+%( uHLH߉[A\] UHAUATSHdH%( HE1H IH~(HH HF HNHpH H9 HH8 t8HC@S0HK(HSH{@HH0H~{4~ Ht HBHCHL AD$ I$C4ID$HSHC@H CP C0HEdH+%( H[A\A]] LhHJ4 XHC(HtrHS fH @@ @0HCLk H H{(HHS F9HC(Ht fo H 1C1H=j] D UHHdH%( HE1HEdH+%( uff. UHSH(dH%( HE1HtgHF(HHt HVHH;8t&C u-HEdH+%( uMHH]3 H C tH{HuHu HEdH+%( uH]>ff. UHSHdH%( HEHG(HtlHWHH<Ht\H HS(HCH HtHHCHt2HHt)P S4HPH HS@H HCCP C0HEdH+%( uH] UHSHdH %( H]HH(Hu: D HH% HSHC(HH AH{(H HCHHuHHC( H{`HHC` HfHC( HHC@ HCH HCT CChHEdH+%( u H]1Ð1 UHHdH%( HE1HEdH+%( uɸ Zf. UHAWAVAUATSHX^HdL<%( L}IH ! IG@HEAG0H L5> L L L% LmAE EWLLIcS H5 fA<V 4tEWhIpHA @A9t+ @ ASf~HcA44HcSHfA; @uH5ҹ HHFSAfH}AVuIGpHEIcGhAFH}M HL)AW8AW0H I@ H=ĸ HcH>E_LAGH EuAGL I I IG(Ht:IWHHt-HXP H AW4I_@I IGH]AG0zL IWIG( @ IH LIWHIG(HHUAG0Y1HUdH+%( HX[A\A]A^A_]AG0H}IGpHEIcGhAFLXLIRIbE 1L HDH¸ EvI$ h ^, TIOIcw8 I PLt L - IG@HEAG0rH}HI+ EAG0IWIG(HLAr8e AW4IJLcI@J HMHHUI H9 HMNL I9c EJ4H)ED H HUHHEIcWLIL r IG@H9 As H=ҷ HcfA<v tAwhMWpsHE,@A9u0 fHcH~ HcsHE,@D9 Aq@- : Hr I H IG1Hr H IGIG(H TAGP LzLõ L | AGLI HIW@ }DODME G LRHL)Hv Y D1HoHH9uHHMMȃAN J4 )ǍOv JH}JʉσIHփtc}AP9~SVAQP9~DVAQP9~5VAQP9~&VAQP9~VAQ9~FAAIWIG(HLAz8 AJE) IG@MLmM] AIAGLHcLM>OLMHIGtBIIIQ(Mc}LL<IA@AO)JIAw H)IŅuIG H=pX c IOAR AW4I AB8 ~LmMMϸ 9OAB$E LUU@LmLUI HcEMHEHcEHEQf. I' L0 L A} AE Iu IWIG(LHUIO H}IzLز L AG4HƉtIOIG(LmH ȉq #AG4 AB HE 1A8 EHyDD;Qo EW4McB IG(IWHIcG4HRD IWIG(HHPEI UHUz HcEEWLHHEIG@H9 IL AE H=( IcfA<v tAwhMopsHA@D9uF8 ff. ff. fHcH HcsHE@D9 Aq@Hc}1LmUALH}IHzHUHUL5 L LRHz(AJ<HB?ID9muILmUAW4IOIG(E HHQ ?U!IL4IOIG(E AW4L L S H f. H=ٰ IGAL9mhLmH}}H= IGHcHEI9AVLmLU &HMALIcDUKHMIWL DUL HAIG(HHxH_ ADPDUEW41IcG4HHHEHMAVH}2IIcH}LmIwIG(QE HHx IOIG(AW4H ȉQ LmAW4DHzDmILm UL L ï DHLM1E1uHM1<@<HH9uEVAG4 AB AGP4ILL L G H=O H=p H=3P H=O fHcEEOLHUHHEIG@H9 IL- A H=S IcfA<N tEOhMWpKHA<@D9u-<f D HcH HcKHE @D9tA|M @H= ID GL9UjIcAvft H}EOhIpsHcA<PD9t H= H4wsHcE PD9uH= DWAtEu Lm HEHEIG@f. f. f UA AA HAWL= AVH AUIATE1SHHx HpHxdL4%( LuLHDž LKD D#H9 L)DLsI' M' I9LOK|L)H LLHILHLHLMPLHHLIIILHLIHDI9t9LHLL}HLDLMXHOt2JH9 LIA IcE$DA A% El A A AT$ HcH5 49 H utEw @ H I9tLHEdH+%( ; Hx [A\A]A^A_]H9 u E tH H $f I9wHKHIE$AtAA wMcB< uF$"E~HIDž I @ H D$DE LcH=4 J )IHcIHw`H HcH>f D LhL1LDLHpc"LDLLhJ LL)H)HH5ӫ LpHPH B H wHcH5| : # H D$HAf D 1E1A Hj 3 @ H IcA nH& AfAIHIF D HxHLhLHD#LhLHAf D HY D$ I HDž HHHH ո?f D LhAvLLDL II FH D IHf I>IFHDž HtoH9LHHff. ff. HA HHIL H9uL^A 1HH1H Iͻ 4f. f. UHAWIAVIAUAH5R ATASHdH %( H]L8Hԫs H HH s Haw̫IHBzՔHHi H)Hs HH sq H9}ACD-ff*A*XY f/Y H,HEs ' H= J O>I H s H=J 2>L s 1H=s HIJ / H ۪s H=wJ =) H s H=J =m H s H=J =m H s H=J =m H gs H=CK ~=m H Js H=K a=m H -s H=K D=m H s H=<L '=m H s H=L =m H ֩s H=L <m H s H=5M <m H s H=M <m H s H=M <m H bs H=.N y<m H Es H=N \<m H (s H=N ?<R H s H='O "<R H s H=bO <R H Ѩs H=O ;R H s H=O ;R H s H=P ;R H zs H=NP ;R H ]s H=P t;V H @s H=P W;HEdH+%( uNH s H [H= A\A]A^A_] ; D \H,Hs H=ߧs ?HEdH+%( uHq L H H8H1[A\A]A^A_]X UEEHAWAVIAUAATISHHH dL %( LMDMf/w$ * f/w f/w H s H Hq fL=$s *(Hs L)p fH* eH=m m]DMDED]9DMDE1MH=s HvO QfM)]A*meY Hs Y fI*YH^L)L fH*YH5q ^\f*H) fH*Hs YH) fH*^LH=ӥs HN HEdH+%( H s HH [H=6 A\A]A^A_]8 HfHH H*X{fHEdH+%( HH[A\A]A^A_]f D HЃfHH H*X1f. HڃfHH H*XfHуfHH H*XfLAfHL H*Xaff. UEEHAWAVIAUAATISHHH dL %( LMDMf/w$ : f/w f/w H 's H Hq fL=4s *(H!s L)x fH* eH=} m]DMDED]6DMDE1MH=s HL a]fM)A*meY Hs Y X \ fI*YH^L)P fH*YH5 q ^\f*H) fH*Hs YH) fH*^LH=עs HK HEdH+%( H s HH [H=: A\A]A^A_]5 HfHH H*Xsf. HEdH+%( HH[A\A]A^A_]f D HЃfHH H*X-f. HڃfHH H*XfHуfHH H*XfLAfHL H*X]ff. UEEHAWAVIAUAATISHHH dL %( LMDMf/w$ : f/w f/w H 's H Hq fL=4s *(H!s L) fH* eH=} m]DMDED]3DMDE1MH=s HI af]M)A*meY Hs YXf(\ fI*YH^L)L fH*YH5q ^\f*H) fH*Hs YH) fH*^LH=ӟs HH HEdH+%( H s HH [H=6 A\A]A^A_]2 HfHH H*XkfHEdH+%( HH[A\A]A^A_]f D HЃfHH H*X1f. HڃfHH H*XfHуfHH H*XfLAfHL H*Xaff. UAHHH=s dH%( HEHH HJq fIH ts *"Hqs H) fH*H) fH*Y^HMdH+ %( fA*Ya H) fH*YL HF ^ C \IʃfII I*XH)hHfHH H*XSHEdH+%( u' HfHH H*X[E D UHAWAVAUATSHdL$%( LeIH s H HAA H= M 0Ls H=xs H)H= vAH=?B H fH*P H M ^ =H=}s 1L s DHE (Mt H=Ts L 1H H LHDHEdH+%( H s H [H= A\A]A^A_]/ HEdH+%( ubH[A\A]A^A_]fHfHH H*XffP H*H = ^A <zf. UHAWAVAUATSH(}dH %( H]HH 9s H Hq MIAII)L= H Ho H= LE.LEs H=s I vBI?B m M fI*P H Y ^% ;H=s 1L(s DHC 4Mt H=`s L 1HC L5+q Hds ffHMs *UY A*&H) fH*LH) fH*HY^H) fH*YL H=s HB U^ ' \fHs fHs A*&UH) fH*I)_ fI*Y^H)p fH*Y^\A ~Y ҽ % d ] ff. @ Y܃ f/rf/ ? HEdH+%( H s H( [H=P A\A]A^A_]+L9Hr LB~ D HуfHH LH*XH)^HуfHH HH*XY^H)NHЃfHH H*X9 LAfHL H*XY^H)HfHH H*X{ HуfHH H*X*fH=s AM HFA X\ P f('ffP I*H ^ 8 HEdH+%( uBH([A\A]A^A_]f. LAfHL H*X&f(f UAHAWAVAUATSH8udH<%( H}H=s H8 IHIMI)I H[ s L=s HEI n H/q fH\s *HYs H) fH*HH) fH*YL^H) fH*YӸd ̹ ^ \]H f D YӃ f/rfɾ UA*Y H~? AI Us vOI?B MF fI*UH ^ P L r6UM1 UH=s Ls H? 费MUt'L 1UH=̔s H 船UHq fHɔs * HƔs H) fH*I) fI*Y^H)a fH*YHMH=Qs H> U^\ Uf/ k HEdH+%( a H s H8 [H= A\A]A^A_]& D H js L=cs HEM~ fI*DMH Q ^" LP 4H=ts DM HЃfHH H*X]fHуfHH H*X fHуfHH H*XfHfHH H*XfLAfHL H*XOHуfHH H*X fH=s Lf(H= Ll fH I*^ * HEdH+%( H8[A\A]A^A_]f D LLfHH H*Xj LMfHAL H*Xf D I?B fDMH s I*^w f. f(袻f UHAWAVAUATSHx dH %( HMH ls H H5ls Lc H= H^s d$H-s H Icf% hD *YHq f*Hs H+s ; fH*f H=Ős YH; HpY^^ / \^EP HH 11His H IcfɋD *YhH/q ffX * HLs YH+Is S fH*^HH=s H ; L= Xl 觴LH= vs IH HL-η D LHUH L HLHuL- s LLH=: I IHtLH& 1 H2H9@s 2 L HHuLHs H BfɍD *YhHq ffXhX F \ V * Hӎs YH+Ўs fH*^LH=s H: X 5 H as H= x!HEdH+%( Hx [A\A]A^A_] CD6f5 *hYf. Hs @ L-s H LPHfHH H*XfHfHH H*XfHfHH H*XfCD6f*Yhif D CD6f*YhL-ϋs % D UHAWAVAUATSH8MLEdL%( LELs M Hq ILcHIMI)H H L= I9 Hs H BfɍD *Y Hcq fHs * HH) fH*Hps YH) fH*^LǾ H"6 s H=s I vBI?B M fI*źP H ^Y -LEM1L \s H=s Hn7 dMt H=s L 1H 5 BH[q fHs *Hs H)l fH*LH) fH*HY^H) fH*YL H=s HB5 ^\ z 譯Hq fHs *Hs H)7 fH*I) fI*Y^H) fH*Y˸d ^e \ ] Y f/rf/ HEdH+%( } H s H8 [H= A\A]A^A_]! HQq L=x H0H4H}DULELcULEHH LEHs H CDf*Y D HƃfHH Hs H*XYH)HfHH H*X D HуfHH HH*XY^H)HЃfHH H*X D HуfHH H*XfHfHH H*X fLAfHL H*XHуfHH H*XfHM H=Ss H<4 f. fP I*H ^ѫ d)C HEdH+%( uJH8[A\A]A^A_]f. LLfHH H*X f(b誱f. UHAWAVAUATSH dL$%( LeAH is H LcIH= HӾ L@b LA9H E DO1Eh(Hs H Icf%Y D *YHq fHs *(Hs H)D fH*LH) fH*YH^H) fH*YL H=is H2 8^ ޫ \ H&q fHSs 8*HHs H)? fH*I) fI*Y^H) fH*Y Ʃ d ^e \Y]9 YӃ f/rf/U / H s H= HEdH+%( x HĨ [A\A]A^A_] D CD-f% *Y@f. HfHH H*XfLAfHL H*XHуfHH H*XfHfHH H*XfHfHH H*XfHfHH H*XfHIs HtEBfD *f(YXDf(ž H= s H0 ԨCD-f*f(Y f(Jf UHAVAUATSH dL$%( LeIH s HM LcHIվ H=/ Hs fHt0M fI*Hs fH*^Y֨ H7s H Bf D *YX L5q fH(s Hs A*&XXh \H) fH*I) fHI*Y^H) fH*Yľ H=s H</ L--}s U^f(61 LHMH } L #I U L;%Ds Χ H?s fA*XH)Y fH*Hs YH) fH*^LH=́s H. HEdH+%( E H s H [H=0 A\A]A^] CD6f Ϧ *Y@fHEdH+%( H [A\A]A^]LAfHL H*HXY^H)^HfHH H*XI @ HfHH H*XfHfHH H*XfHfHH H*XfI$ H LHS㥛 HH1HIк !I` UM fI*H Y L X U^ N!U @ HfHH H*XxfLLfHH H*XC >zs Turbo f6zs _ D LLfHH H*X6bf UHAWAVAUATSHHH}dH %( H]ȉH )s H IH= AMź M&H MH=~s IH , MEMIE1蔣Mt H=~s L 1H rH=~s A9|V E HEdH+%( H s~s HH [H= A\A]A^A_]w E tH|+ = L= q HE-ѣ }H5~s HEff*Y]A*H) fH*H}s YH)E fH*^f(HU \ Mf(dMMtgH}s HEfA*H)- fH*H}s YH) fH*^LH=A}s H* EfA*YeX% @ H)}s H]fA*H)C fH*H|s YH) fH*^H=|s f(H/+ h HEdH+%( HH[A\A]A^A_]f D fHEf5ġ A*L=8q Hq|s uA*Yf(EX% H)y fH*H1|s YH) fH*^f(f(- H() eXHEH¸ mf(耠Mem ] H{s fHEA*XH) fH*H{s YH)w fH*^LH=H{s H( meem H={s fL=q HEffH{s A*Y%I A*H) fH*Hzs YH)N fH*^f(f(H=zs e\ ; H' f(;Me]Hzs HEff(A*\ H) fH*HLzs YH)w fH*^LH=zs H( e赞e L=q fHEfHys *Y " A*X - H)| fH*Hys YH)? fH*^о H& MXf(MHgys HEfMA*X H) fH*H,ys YH)w fH*^LH=xs H& 蚝7 D HfHH H*XfHfHH H*XfjEoee D HfHH H*XfHfHH H*XfHfHH H*XfHfHH H*XfHfHH H*XfHfHH H*XfHfHH H*XrfHfHH H*XfHfHH H*XfHfHH H*XfHfHH H*XofHfHH H*X fHfHH H*XtfHfHH H*X[fHfHH H*XtfHfHH H*Xtmff. f UHAVAUATSH dL$%( LeIH .vs H HAAվ H= . Mt H=us L 1H+ 謚fffHA*0 L%q A*Hus H=us A*$YYH) fH*Hus YH) fH*^E9/ X%ܚ f(ef(f(¾ H" HVus feA*$H)> fH*H&us YH) fH*H=ts HX# ^f(蓙HEdH+%( H ts H [H=D A\A]A^] HfHH Hts H*XYH)HfHH H*X^E9X f(e HEdH+%( uOH [A\A]A^] @ HfHH H*XfHfHH H*X轝ff. f UHAUATSH(dH %( HMH ss H IH AH= % H Oss H= " fMt H=2ss L 1Hc L%q ffHH+ss A*Y ^ A*$H) fH*Hrs YH) fH*^¾ H=rs L-! ML`Hrs fMA*$X H) fH*Hrs YH) fH*^H=@rs L HEdH+%( H rs H( [H= A\A]] @ HfHH Hqs H*XYH)HfHH H*X D HEdH+%( uWH([A\A]]f D HfHH H*Xf. HfHH H*X=ff. f UHHdL%( LELqs M HH qs HEdH+%( Hq ff*Y / * X 3 H)xFfHps H*YH)xVfH*H LǸ ^>f D HfHH H*Htps XYH)yHfHH H*X @ HEdH+%( uf. UHATSHdH %( HMH os Hd H=o L% 1 - H=os L L f( H R H G H=^os H d H=>os L] L f( H H=ns H K 豓 Y H=ns L L f(耓8 H H=ns H H , H=lns L7 L f(ϓ H $ H=#ns H ߒ LH= ns LM f(讒f H K Ó H=ms H rk vHEdH+%( u?H ms H [H=+ A\] fHEdH+%( u H[A\]c UHATSHdH %( HMH 5ms H4 H= > L%O 1 } H=ls L[ L f( H _ 袑Z H ? H=ls H j d H=ls L L f(9 H ֑ 6 H=Els H H=%ls Ly L f(А H m Ց H=ks H L 蘐 @ ^ H=ks L L f(g H H=sks H / א & H=Sks Lܶ L f( H # H= ks H Ə n H=js Lѵ L f(蕏M H 2 H=js H < ] LH=~js LI f(, H ɏ a H=8js H HEdH+%( u=H js H [H= A\] HEdH+%( u H[A\] UHAWAVAUATSH(dH%( HE1H=is H is His H9 H!"Kgf(Ha * HHH9 ~ A I!"KgHm.:BGH K HH H9r e A Ia * f/scHÀ H9W H A IHI9sHm.:BG H K A HH H9rf/rL%m Ia * H=|q Hhs fH*H)a fH*YH)+ fH*^HeLAPE H <hs T HÀ H= hs f(H.hs ZeYH9sZH 7 A IHI9Hm.:BGsrH K HH H9$ A @ HEdH+%( He[A\A]A^A_]f D h A D H K HH H9 5 A %fHfHH H*XfHfHH H*Xff. f UHHdH %( HMH fs Ht- H=r H=fs IHfs HEdH+%( u舐 U HAWAVAUATA SHxG dH%( HUHHcXD9|}DNIZ`HU] HcHEIHUHEH HuH HuM H HE E HUHEf. H}HMt ~IH 1H1֟A,E9~kIcD HHLI 訟AL9|LH]HuHEHDH]HEHE9CX~mLmaL踇H)q # H= HH}衱H}蘱HEdH+%( Hx[A\A]A^A_]Hڋ[` HE HU LuH}ILu[IHg1H1賞A5f D E9?IcD HHLI |AL9|LņH]HIHEHDH]HEHE9C`ZMcJ< Hcs HH |~ DH tE1E1D DeEIHH}MLILk9E LhLpfu Hc|E1HHHEЃ?E ff. ID9~~H}MHEIMLHH HsL9E~ADMAff. fHcH}HHcL8tgL/9EEuID9|HpLH}Hc9ELhID9m1` D8AwuL辚9E~D}^f D DezHHHHDHND9Hq H= H轋f. UHAWAVAUATSH H $ HXHdH%( HE1HH ff. H踫H xux.LhuA} t x. LIHtH^IH fLXH xux.LxuA t x. HL苧uHML H| HBH11DžxH HH7Hm 蓁H 1ВHH9 LLH 蒬HHtfHL%` 1M L 1H{M L y H]Hyff. 1HEdH+%( HX H[A\A]A^A_]f D A}./A} $H袩Hf H(f D A.OA DLbH f LL{&̈Hx/ff. @ UHAWAVAUATSH H $ H H $ H( dL,%( LmII=^s 1HDž 1LI1 M Lff. L=M E1JHEdH+%( H( D[A\A]A^A_]fLc=]s LLLeL9tA =]s HL;L9MAv =]s HLLxHKHq H& 01S끐Hq L H 011D Aff. UHAWAVAUATISH dL,%( LmIDž$ HH ff. HH xux.LxuA t x. M MvMtIvL[u1H(MLH] g H(H0lH(AuETH߃$EHMff. =[s H$ iHtsHtq H A01H艢HEdH+%( Hĸ D[A\A]A^A_]ÐA.A D H H舥H xux.LxuA t x. M MvMtIvLu1H(MLH H(H0xH( AƅuKH(ttH̤HD E1 A.OA ?H()tAHګq L H 01uD0Aa D UHATSHdH%( HE1 HE HHtWHL@H}1Hg xSff. IH[I|$&L L_sHuH]HEdH+%( uHH[A\] HE )f UHHdH%( HEHH9u%ff. fH H9txu 1HUdH+%( u UHAWAVH AUATSH L7dL$%( LeAԉ5Xs HL9X IH1DHMH ʤ: LIHϚMf H] HLHL)iLIIxHbHIFH H MuMM$$L9 A|$uM$ MMI|$IEIHuH8q H 01{HHt5ff. @ IH[I|$LޣL qHu1 L迣HHx诣H裣LMuMI$ : vH0A LpIE f D DoHH_@ /HHED`H E LuED=`Vs fUL EtracEcingH O =1Vs H5K H& =Vs LE H =Us LEfH H5s =Us EH L= L IH H LHH" =qUs LH u Hq H 0 16LAEtCD%$Us L 1DDI+vTs Etf. Hk @ IH[I|$VLNLnHuHHUdH+%( H [A\A]A^A_]f D fo Hx @ G o6 H Hx 1DžD Lu ED+Ts L EtracfEEcingH A E L LL5 虴L!IHb HH =Ss L H L L4H= 踲IH HH!LA覷EH=6 Dž HH H IH LH xux.HPuz tـx.u z.uz tH5 HHtHIMmHMtIu HHMuكmHq L Hi 01.LH£q H, 01Hk1OHq H? 0 1L讲=Qs H BHt5HMq H 01LhHILff. @ L蘛H xux.L@uAx t x.uAx.uAx tff. H5~ LLtHL H3Lž& H[HuHXAL芗H EmH =Ps HDž H H= mIH HH L]L蟴 H= IH/ HH* L LAJEH]q H& 0eHHM1H`Q LHLHH LxEHL=>Os HLhLH I9 H H hHH HH H|q 01Hh1=Ns HDž 'LH EALHq L H 01PL(Hq H 01'1 A=Ns HHDž LHt8eEAHrq H 07-E|H@q H 01^EHq He 01WH Hq 011 H H fLH胱YH HŘ AHq 01 Hkq H 01EAwuv D UHAUATE1SH dH %( H]Hu&H>fHEdH+%( u*HD[A\A]]ÐLk 1LbLAm v UHHHdH%( HU1ɑHtHHEdH+%( u HEdH+%( uɸu UHHdH%( HE1HEdH+%( u1muff. f UHHdH%( HE1HEdH+%( u/uff. @ U H=r HHdH%( HEHq HHEdH+%( uɸtff. U H= HHdH%( HEHq HHEdH+%( uɸltff. U H=j HHdH%( HEHGq HGHEdH+%( uɸ tff. U H= HHdH%( HEHq HHEdH+%( uɸsff. UHHdH%( HE1HEdH+%( u1msff. f UHHdH%( HEHH HxH0 H HtH?H8HpHPHH L@(LH0HEdH+%( urf D UHSHdH %( H]H q H; tQH5rq H= tRHsq 1H 01HEdH+%( uVHH]4 D @ .HHt @ H5 q H= -uHEdH+%( uH]/rff. @ UHSHdH %( H]H /q H; tQH5q H=Ŕ tRHq 1H 01HEdH+%( uVHH]d D @ ^HHt @ H5q H=I ]uHEdH+%( uH]_qf. D UHAWAVAUATSH H $ H8dL4%( LuII諦L-dGs HDž H LHHMH L1芘HҧHHL ft(HHUdH+%( u\H8 [A\A]A^A_] D HHMLHHd`H HFpf D UHATSHdL$%( LeI<Ht7HH̍I $ID$1HUdH+%( uH[A\]f o @ UHAUATISH=Es dH %( H]Hu?H=Es vucL-Es Lς1LE1LkEs HEdH+%( uDH=Es HLH[A\A]]Yf HEdH+%( uH[A\A]] off. UHSHH7dH %( H]HH7jHEdH+%( u H;H]nf D UHAUATISH=Ds dH %( H]Hu?H=Ds uuSL-Ds L证1L%1LKDs HEdH+%( u6HHL[A\A]]HEdH+%( uHH[A\A]]mf. UHATSH=Ds dH %( H]u?H=Ds tuYL%Ds L1Lk1L葋Cs HEdH+%( u:H=Cs H[A\]E D HEdH+%( uHH[A\]<mf. fUHAVAUATSHdH%( HE1H FHLftE1 t*HEdH+%( * HL[A\A]A^] Lv IMtAF tzLc(MtAD$ uNIt$ LQHt L;h It$(L5IHgL;h]ff. @ E1F Iv IHt L;h#Iv(LIHSL;hIf D M9l$uI MfI9~IkUHAVAUATSHdH%( HE1HtUIHC E1t#HEdH+%( O HL[A\A]A^]LcMtAD$t t(E1 M;l$uf Lc f. Mt$ MtAF Md$(MoAD$t uIt$ LHtL;htIt$(L~IH/L;h`s Hs LIHH[(Hf D M;nf1Iv LHt L;hIv(LH0L;h& jff. UHAUATSH }@s L/dL$%( LeItBHc5c@s It$L\IЉHEdH+%( uGH[A\A]] @ L蘤HHtH5] TxHtHcp(X,5?s ?s Ui D UHAUATSH ?s L/dL$%( LeItBHc5?s It$L \IЉHEdH+%( uGH[A\A]] @ LHHtH5 wHtHcp(X,5B?s 8?s h D UHAUATSH ?s L/dL$%( LeItBHc5>s It$L\[IЉHEdH+%( uGH[A\A]] @ L8HHtH5 vHtHcp(X,5>s >s g D UHSHdH %( H]HnH1HtHUHHEHUdH+%( uH]gf. UHHdH%( HE1HEdH+%( u H?]ZXg UfHAVAUILuATSHpHHpdL$%( LeM)E)E)E)EuMHU I} 1LLaH H HjMHL?ZH藫HEdH+%( u Hp[A\A]A^]ff D UHHdH%( HE1HEdH+%( uH/q L ֬af UHAWAVAUATSHdH%( HEHGHX8Hj I HHQ C @ uLcMtAD$ uMt$ ME AF. / M~ MtAG 4 Mv(M AF Iv LEHtL;ht*Iv(L.H L;h ff. Lc M ;s fH ~;s )w;s );s I|$11I1Ҩuff. Ht ID$Hc M$$MuH #;s HEdH+%( HH[A\A]A^A_]M;nTMd$(MfAD$ OMt$ MtAF Md$(M!AD$tO It$ LHt L;hIt$(LHL;h D M;l$Lc M Ls MtAF t Hs(LIHepMfMtAD$tz uM|$ MtAG f Md$(MtAD$ uIt$ LHtL;ht It$(LH`L;hVMf MDIv L5IHIv(L IHM;om D M;nOYf M;o. @ M;l$mIw L4Ht L;hIw(LHL;hIv LHt L;hIv(LHL;hIw LHt L;hIw(LHjL;h`aff. UHAWAVLuAUL-4 LATSH8H}dH<%( H}HLHE HE bH IHEHEN 1 IHEHxA1LLHbH}LHIHPMt2HULH57 jbHHuHq H 01ۺHEdH+%( uH8[A\A]A^A_]` UHAWAVAULmATL%" LSHHH}dH<%( H}HLHE aHtTHH]L}L5J 1LLaHHt+1HLL۲uUH}H跶 D HEdH+%( uHH[A\A]A^A_]_ff. f UHHdH%( HE1HEdH+%( u H # YP_ @ UHHdH%( HE1HEdH+%( u PK_ff. UHSHdH %( H]H0 \ HH=* - HH={ HH= > HH= Т. HH= 蹢 HH= 袢 HH= 苢 HH= t HH= ] HH=с F HH=Ɓ / HH= 1 HUdH+%( H]ø ff. HHq HHD @ HEdH+%( uWHH]11h 뺸 본 문 른 랸 뗸 됸 뉸 M]f. UHAWAVAUATSH(udL4%( LuD53s IA MA)tXIcLDʕHÅ~s=|3s LctLL w~9tH q Hu 13ö8E~jHcEH63s HUdH+%( uKH([A\A]A^A_]H 1q A3MH 1 k @ H q E1/\DEH q fUHAVAUATSH H $ H H $ H dL$%( LeA LL!f D IT$C& Iԋ=_2s L肔HHxz =-2s t L )~HH9tH/q H@ 01r1HEdH+%( H H[A\A]A^]f. Hq HZ 01$fHq H~ 01fMcL%~1s L莨HHrLLH?H\Z UHAWAVAUATSL$ H H $ L9uHX dL,%( LmIL= 1s LfƅD0s t,f9tZHہq H~ 01 H HEdH+%( HX` H[A\A]A^A_] 8u Ldttract#HTq H5 01藳tfßcingu?HHQ Lr LD9` I] H`lAHt1Hv L L DL LHKADžthAHODHGH HH6t1Hheader_pH9tnH q H| 01bfHtL賩HH H+ Hq H'| 01 f. ȿage u LE1t LHJILtIHhDH]K H<LLH߉ LlGH Hheader_eH9t'H q H{ 01Cf D Hr_event H9ſuƾ LtT LHIHHAąt/ff. A HE9ENDdE)u߾ LR) LHyI Dž R LLH L牅4F9 LE1t LHHIL蝣IH DHeH~}q Hz 0 1LET @ HQ}q Hz 0f D HЋH߉VL L LH:H| Dž HH L LHG Dž K D HLLHtAą LDEuq9 LE12t LH]GILIH DHjL*DH Df H{q Hx 01LCf. HC9ff. Lct1 LHFt Aċ=1*s L4L%*s L ti LHKFIDžtLxIHHrEHLC< mLBH1f/O s$s)s H t)s HB LitL HEIHtHxCIHtmDH0t~HHDLA 趎LNBoH zq Hqv 0Hyq H 018RHyq H˴ 01Hyq Hv 0+f. f. @ UHHH dH%( HEH @ +B HUdH+%( uH{Qff. UHH dH%( HE1 1u( H)HUdH+%( u H)Q UHHH dH%( HEH H@H+BHUdH+%( uPff. UHHH dH%( HEH H@XH+BXHUdH+%( ukPff. UHHdH%( HE + HUdH+%( uH#P UHHdH%( HEH H+ uH H+ HUdH+%( uO UHHdH%( HEH H+ HUdH+%( uO UHHdH%( HE + HUdH+%( uHSO UHHdH%( HEu1x 19 HUdH+%( uO @ UHHdH%( HEH H+ HUdH+%( uN UHHH dH%( HEH Ht4Ht? 2 ЃHUdH+%( u! HH DN @ UHHH dH%( HEH Ht4Ht? )HHUdH+%( ufHH M @ U1HHdH%( HEH HtHPXH 1HtHAXH)HUdH+%( ujMf. U1HHdH%( HEH HtHPH 1HtHAH)HUdH+%( u Mf. U HHdH%( HEH Ht H Ht )HHUdH+%( uL U HHdH%( HEH HtH HH HtH H)HHUdH+%( u Lff. @ U HHdH%( HEH Ht ? H Ht %? )HHUdH+%( uKff. U HHdH%( HEH Ht H Ht )HHUdH+%( u!K UHHdH%( HEH H+ HUdH+%( uJ UHHdH%( HEH H+ HUdH+%( uJ UHHdH%( HEH H+ HUdH+%( ucJ U HHdH%( HEH Ht H Ht )HHUdH+%( uI U1HHdH%( HEH HtHPpH 1HtHApH)HUdH+%( uIf. U1HHdH%( HEH HtHPxH 1HtHAxH)HUdH+%( u:If. UHHdH%( HEH H+ HUdH+%( uH UHHH dH%( HEH Ht,Ht/ 2 HUdH+%( u HH H @ UHHH dH%( HEH Ht,Ht/ 2 HUdH+%( u HH H @ UHHdH%( HEH H+ HUdH+%( uG UHHH dH%( HEH HtDHJ H+J1HtHP H+P1H9HHOHUdH+%( uf 1HuRGf UHHH dH%( HEH Ht<HJH+ 1HtHPH+1H9HHOHUdH+%( u 1HuFf. UHHH H dH%( HUH H Ht4 t0Hty4 tH)HUdH+%( u ÐHH+A HH+WRFf UHHHHdH4%( HuHHUdH+%( uH H@ Fff. UHHHHdH4%( HuHH HBHtHUdH+%( u @ HBEff. f UHHHHdH4%( HuHH HBHtHUdH+%( u @ HBMEff. fUHAVAUIATH HHLPLXt&)`)p)U)])e)m)u)}dH%( H(1HEILHH LH0HDž Dž0 H :L5Jqq AIFHE~ HHu9AEE9DMH(dH+%( u.H DA\A]A^] .IFH0\HHuDf. UHAVIAUIATISHH dH %( H]؉ B LL9CAHH AHHDI HEJ PHuh 1THUdH+%( u He[A\A]A^]sC UHHHHdH4%( HuHHUdH+%( uL Hz 1$C @ UHHHdH4%( HuHHUdH+%( u#H AH1L Hg Bf. UHHHdH4%( HuHHUdH+%( u#H AH1L HSg /jBf. UHHHHdH4%( HuHHUdH+%( uL Hj 1B @ UHHHHH dH4%( HuHLH-HHf LDHEdH+%( uAHf 1tAff. @ UHHHHdH4%( HuHHUdH+%( uD AHKf 1QA UHHHHdH4%( HuHHUdH+%( u H L 1He @ff. f UHHHHdH4%( HuHHUdH+%( uD DAHe 1e@ UHHHHH dH4%( HuHHtZ t7L L r HEdH+%( u;AH e 1 tL F L Ώr @ L r @f. UHHHHdH4%( HuHHUdH+%( uL Hd 1y? @ UHHHHdH4%( HuHHUdH+%( u D L 1Hdd !\?ff. UHHHHdH4%( HuHHUdH+%( uL Hd 1? @ UHHHHdH4%( HuHHUdH+%( u D L 1Hc q>ff. UHHHHdH4%( HuHHUdH+%( uL Hec 1T> @ UHHHHdH4%( HuHHUdH+%( u D L 1H c =ff. UHAWAVAUIATIHb SLHH dL4%( LuA LHXp1_L Hb LcI1L)K|= ;LL H}q Hc1LELH)I| H) HHI9sCD= HEdH+%( uHD[A\A]A^A_]=f D UIHHH Lr dH4%( HuHHt t5L Lor HEdH+%( u(Hp L1ff D L" L:r <ff. UIHHH Lr dH4%( HuHHt t5L 9 Lr HEdH+%( u(H3p L1f D LN" Lr ;ff. UIHHH dH4%( HuHHt-HUdH+%( uFL@ L+@H= 1L\ @ HEdH+%( uL L1HS= 0k;ff. UIHHH dH4%( HuHHtHx u.HEdH+%( uGL$ L1H< f D HUdH+%( uL@L+ H< 1L: UIHHH L dH4%( HuHHtx4 t(HEdH+%( u"H_ L17 L L+@b:f UHHHHdH4%( HuHHUdH+%( uH H4n L@81: UHAUIATISHH dH %( H]؉.nIHEdH+%( u#HA؉L[LH^ A\1A]]i9 @ UHATSHH dL$%( LeImHI$ mHHj}HUdH+%( u HH[A\];9ff. UHHdH%( HEHH H Ht)Ht,H-H-|HHUdH+%( u @ HH 8 @ UHHdH%( HEHH H Ht)Ht$H-H-|HHUdH+%( u @ 1H tHHHO8ff. @ UHSHdH %( H]H H tHEdH+%( u H]HSHs H{_)H 7 UHAUATSHHL dL$%( LeII tKM$ I HtWH H {HHUdH+%( u\H[A\A]] IUIu I}(I f D I}IUIu (I I$ H 7f UHSHdH %( H]H H tHEdH+%( u H]HSPHs`H{H/(H 6 UHAUATSHHL dL$%( LeII tKM$ I HtWH H dzHHUdH+%( u\H[A\A]] IUPIu`I}H'I f D I}HIUPIu`o'I I$ H 5f UHAVAUATISHHPH dL,%( LmAHG Hhbq RH)H@H HfHt,HHH fH*H fH*^PfɅuiLu@ @ LFZ L b1MDH&i LHHUdH+%( HP[A\A]A^] @ffH*H*Y . ^qf. ff(Z HfHH H*XH HуfHH H*XHEdH+%( u*HPDLHL [HHh A\1A]A^]"4f UL L5Y HAVAULuA@ ATLIԺ SH@ HXdH%( HE1AQ 1MDHg LHpHUdH+%( u He[A\A]A^]3ff. @ UHAUATSHdH %( H]H HtlL L HLqHH{ LATHA 1A HXH[]q ZH9t : HKHt; u6H"H g s HEdH+%( u HeH[A\A]]f. 2f D UHATSHHdL$%( LeIH Ht2I$ HtEvHHUdH+%( uKH[A\]f D H I$ HHu @ LI$ HH 2ff. @ UHHdH%( HE1HEdH+%( u!1ff. UH ~ HAUIATSHH dL$%( LeIHu1HEdH+%( uOHLL1[H A\A]] @ H UHH mH C HtHH &1f D UHAVAULuATIԺ SHLH0H]q H dL,%( LmÀ8 t@H 1MDLHyHUdH+%( uH0[A\A]A^] D #@0ff. UfHAUATLpSHx L dH %( H]H)EEH L)E)EHE)E5H\q Ix tI H L,0|HppgHUdH+%( u1Hx[A\A]] D H9HUL2 1H ` L9/f UHAVAUATSHdH%( HEH HP L IM H8$ 8 LpHIUHLH M H Mn Hr LM tUAF0uNAX uCA\ u8I` u.Ih u$I$ H @9B |W H M$ H ]q HX`D"-aHEH HEHH!I#E`H9rAH9 f D HUdH+%( u%H[A\A]A^] H @ H.f UHAVAULuATISH H H LdL,%( LmA1MLH4 HDuHUdH+%( u H [A\A]A^]- @ UHAVAULuATISH@ HPH LdL,%( LmA?u1MLHSa HDHUdH+%( u HP[A\A]A^]- @ UHAVAULuATISH@ HPH LdL,%( LmA蟌1MLH` HDuHUdH+%( u HP[A\A]A^], @ UHAVAULuATISH@ HPH LdL,%( LmAo?1MLHS` HDHUdH+%( u HP[A\A]A^], @ UHAVAULuATISH H H LdL,%( LmA_1MLH4 HDuHUdH+%( u H [A\A]A^]+ @ UHAUATISHHuH8H dL,%( LmAHxxerHa_ LHI1DHUdH+%( u H8[A\A]] +ff. UHAUATISHHuH8H dL,%( LmAqH^ LHI1DHUdH+%( u H8[A\A]]* UHATSHHHc dL$%( LeIHt:HEdH+%( uCIt$I<$I1L HH%O [A\]Qf D H Hp8e(*ff. UHAUATISHHHc dL,%( LmIHt5HEdH+%( uBH IT$LI4$H@ H[A\A]] H I p8') UHHdH%( HE tHUdH+%( u @ H Hp8u'+)ff. UHAVAUATISHL dL4%( LuIAE8uDA}(AU,I HI$ ͒HHUdH+%( uUH[A\A]A^] H HUHLdHUAE9t AE,AE(9 s b(f UHAWAVAUATISHHHuHUdH%( HEHc HEH A$ ukHEH H I$ LpL 3I I_ Hw@LLHI Muх H]H譞HEI$ HH 21H]HEHMIHL H8HpI1 OHAPHEdH+%( HHD[A\A]A^A_] G|u5H H{A2A$ K,9MC8T D9LAD$|HHEH2L<J|+LH)HH:HEdH+%( u\HEHML jw HK HpH8HHI[1A\A]A^A_]$N @ HII HHRH& UHHdH%( HEu1Ht 1H9 HUdH+%( u% @ UIHH dH4%( HuH֨tfH J <w.uzHEdH+%( HJ L1M D HEdH+%( ubHJ L1' HEdH+%( u:HҌ L1 HEdH+%( uHgJ L1%f UIHHH dH4%( HuHHtUH@HL = Ht H@ HtHLq ~OL HEdH+%( uBAH|I L1T @ HEdH+%( uL q L b$f UIHHH dH4%( HuHHteD A t-HEdH+%( unAH^I LE1 @ HEdH+%( uAL L1HW HEdH+%( uLp L1H XK# UHSH(H dH%( HE1u%H HHt]H Ht)HagHHUdH+%( uNH]f. HHuHuHH H D HuHuH "ff. f UHAVAUATISHH L dL,%( LmAA# LPƅP LA* A4 AG Au^A uoA@n Au|M H[V 1MDLHHUdH+%( P HĐ [A\A]A^]fRETRHGRY A tCON H A@ AtHCAP-READH HG fGA LH [I H F H1 ܘ8 HSLPDžPEL ATX HA SYNCHfWAASYNHGNC HNEITHER G HHG> D HCAP-WRITH HGGTE ff. f UHHdH%( HEu=1Ht6H Ht%HyPHt H-H2H HUdH+%( uJ f. UHHdH%( HEu=1Ht6H Ht%HyHt H-H 2H HUdH+%( u f. UHHdH%( HEu-1Ht&H HtH-H1HHUdH+%( uZ f. UHHHHdH4%( HuHH Ht:HMdH+ %( u]L LB-1L+JHaD f D HUdH+%( u# L DA1ɉHD v UHHdH%( HEu*1Ht#H HtHIHHt 1H9Q HUdH+%( uN ff. UHHdH%( HEu*1Ht#H HtHIHt 1H9Q HUdH+%( u ff. UHHdH%( HEu!1HtH Ht 1H9Q HUdH+%( uw UHHdH%( HE1HEdH+%( u@ ; ff. UHHdH%( HE1HEdH+%( u ff. UHATIH8H dH4%( HuHփu7L Mt[HEdH+%( uvLLeH 1Nf D HEdH+%( uKLLeLi 1H D @ MHuH}H}؋MHuIH {) f UHAWAVAUATISHH(H dL,%( LmAH HHHp H@ Lx1HM HHuLvLLcL)J<3M H} AG*< DMG-Hu 1L)-HMLcMI+O DHUdH+%( H([A\A]A^A_] @ HEdH+%( H(EDLHL h [1A\H? A]A^A_]f D LE H<@ 1LcMmf D LJ<+H&@ 1L)hHIEf D H@| 1IO-FHULcIGMƀz4 uHH+BHMLJ<3H? L)H)1 LcM<ff. UHAWAVAUATISHH8H dL,%( LmAH HH DP(LxLpHAq HM ~sM IW H HDUHUmHUHMDDU IȨ A4 IIM+G HE1HAHU> 1LELELLcML)J< M$ M AF*<; DMF-Hqs 1L)LMLMHN,AF+ DHUdH+%( P H8[A\A]A^A_] D IA! LH߹ 1H> DUJLDULcL)J< HEdH+%( H8EDLHL _e [1A\H= A]A^A_]f D LJ<+H 1L)HI,f D LE 1LMHN= LMHN,f D 1IN-Hry LMzLMLcIFMA4 uII+GHMLJ<+H = L)H)1?LcMoff. @ UHATSHH dL$%( LeIKHI$ uKHH*[HUdH+%( u HH[A\]ff. UHATSHH dL$%( LeIKHI$ KHHZHUdH+%( u HH[A\]ff. UHATSHHdL$%( LeIH Ht2I$ HtEPZHHUdH+%( uKH[A\]f D H I$ HHu @ LxI$ HH ff. @ UHSHdH%( HE1H tHEdH+%( uEH] D H]HtH f. H1Aq ǃ H Q UHATISHdH %( H]HH H HtCHtVH-H-YHHuI$ H+ HUdH+%( u+H[A\] HHtf. @ UHHH H dH%( HUH H Ht4 t0Hty4 tH)HUdH+%( u ÐHH+A HH+W2f UIL HHH dH4%( HuHHt H@ HtH;q ~0L HEdH+%( u#AH8 L1} D L f. UIL HHH dH4%( HuHHt&H@HHt H@ HtH ;q ~/L HEdH+%( u"AH 8 L1 @ L f UHAVAUATISHL L dH %( H]HMtOMtrIv8I}8VHHuA$ + HHUdH+%( H[A\A]A^]f D ZIHt;I$ MuL D HZIHt0H r @ L->q ADŽ$ M$ L5=q ǃ L 1ff. UHATI SHdH %( H]H_H ~wp HHID$H H HF HHfHnFx HpHF(flH!HF0HfHF8HHF@H- HFHHEHFPHJ- HFHFXfHnHFhFHF| fHnfldž flNXFh)h1HUdH+%( u'H[A\]H8q HY6 101jff. UIHHH dH4%( HuHHtUH@L Ht H@ HtH-8q ~OL HEdH+%( uBAH 5 L1 @ HEdH+%( uL 3] L f UHAVAUATSHL L dH %( H]HMt:MteIv8I}8SHHUdH+%( H[A\A]A^]f D IWIHt@I$ MuL f. HWIHt0H L-;q ADŽ$ M$ L5:q ǃ L >ff. UHAVAUATSHL L dH %( H]HMt:MteIv8I}8RHHUdH+%( H[A\A]A^]f D IVIHt@I$ MuL f. HVIHt0H L-9q ADŽ$ M$ L59q ǃ L > ff. UHATSHdH%( HE苇 tHUdH+%( uMH[A\]fG|HuL I|$ AL$,9MAD$8T D9LC|Y f UHAUATSHHL dL$%( LeII tKM$ I HtWH H QHHUdH+%( u\H[A\A]] IUIu I}/I f D I}IUIu I I$ H f UHAUATSHHL dL$%( LeII tKM$ I HtWH H 4PHHUdH+%( u\H[A\A]] IUPIu`I}H_I f D I}HIUPIu`?I I$ H f UHAUATSH(L Hc dL$%( LeIMMHt8HEdH+%( ukIt$I<$H(I[H0 A\1A]]2 D O|Hu3LLMZ AU,LM9LAE8DD9LʉK|Hc f UHAUATSHdH%( HE1Gt%1HUdH+%( H[A\A]] D H IAUXHH ~Ap HCLH H HF HHfHnHBFx HF(HflHF0H4HF8HHF@H& HFHHHFPH& HFHFXfHnHFhFD fHnflHF| flNXFheHCHx t AD$$ C Hf1q H / 101c @ UHHH dH%( HUH HttH@ Ht[HR HtsHtnH H H0q H H ~HHMHHUdH+%( u;f D HH Ht1Hz H tHHH1 @ UHHH dH%( HUH H HRHHtwHHHH HB H HQ H H H H H/q H H ~HH#LHHUdH+%( uFHtHB HH HtHHHHt1Hy f D HH1H tHHH D UHAVAUATSHdH%( HE1H t$HEdH+%( He[A\A]A^] @ L HMtoL L LLXHI|$ 1AULHA A IXHA1q ZL; t!: L HtA<$ u"LL%Kr L K ff. UHHdH%( HEH H+ u`H H HtdHR HtsHI HtrHtmH.q H H H H ~HH)JHHUdH+%( u:f D Ht1Hy HHH tHHHf UHHdH%( HEH H+ u`H H HtdHR HtsHI HtrHtmH.-q H H H H ~HHIIHHUdH+%( u:f D Ht1Hy HHH tHHHf UHAWAVAUATISHH(H dL,%( LmAH HHHHp`H) LxP1HM HHuL6LLcL)J<3M H} AG*< DMG-H^ 1L)HMLcMI+O DHUdH+%( H([A\A]A^A_] @ HEdH+%( H(EDLHL P [1A\H( A]A^A_]nf D LE H( 1QLcMmf D LJ<+H( 1L)(HIEf D H e 1IO-HULcIGMƀz4 uHH+BHMLJ<3H( L)H)1̽LcMff. UHHH dH%( HUH H H HHHBHtbH@ HtqHQ HtHtzH H HF*q H H ~HHoFHHUdH+%( uG @ Ht1Hy HH H tHHH1ff. UHHH dH%( HUH H H HHHHBHHtbH@ HtqHQ HtHtzH H HF)q H H ~HHoEHHUdH+%( uG @ Ht1Hy HH H tHHH1ff. UHATSHH dL$%( LeL M H ID$HSH H@ H HR H H H H H2(q H H ~HH[DHHu HCI+D$HUdH+%( uLH[A\] HtHz tи D HHHtHH tHHHff. UHATSHH dL$%( LeL M H ID$HHSHH H@ H HR H H H H H'q H H ~HH;CHHu HCXI+D$XHUdH+%( uLH[A\] HtHz tи D HHHtHH tHHHff. UHAVAUATSHHZdL$%( LeAHJH9t,IIDff. C0D9C4D90HH9uHEdH+%( H[A\A]A^] HC(Ht6EHe LIH U LHEH} 1%1HI)IHSH[H9tH9tff. @ C0A9|C4A9| HH9u[LC(Mt`@H)e LLH H HE11%E1HI)IHEdH+%( u#HDHL[LA\A]A^]D?ff. @ UHAWAVAUATSH H $ H8L IZ(dL<%( L}IIR(ƅ IIH9t~D C0A9| C4A9 HH9uLE IJ81EH;" LLNHUdH+%( \ H8 [A\A]A^A_]f ƅ D Hno fieldLH LC(M LH c 1LH LL# E11LHLH)I<HSH[H9t+H9t&ff. C0A9|C4A9|0HH9uE A LLLC(MtgHb H LHEH 1LHH"HE11HHLLH)HHSH[H9Wff. @ C0A9|C4A9| HH9u+LC(MteH:b H LHEH 1LHH,"HE1HHLLH)HDEHLLE LLrf. UHAWAVAUATISHH8MH D L L dH%( HE1H!q HM ! MtLM~ MtCLDUWHMDUDA IȨt$ t A~4 uIIM+F @ IA! LH߹ 1H DULDULcL)J<;AH& 1ֳLLcML)J< M} MtxAE*< MME-HNS 1LML)茳LMHN4AE+ DHUdH+%( H8[A\A]A^A_]fHE1HZfLE 1LMH %LMHN4f 1IM-HY LMLMLcIEMA~4 uII+FHMLJ<H L)LEH)1軲LELcO44 LJ<3Ha 1L)萲HI UHAWAVAUATSH(MdH%( HEH H}HHXLpHIHLhPH: q HM U~^M M~ M L LEDA A~4 MM+F f HE1LMH 1襱LLcML)J<;M M AE*< MME-HQ 1L)[HN48AE+ DHUdH+%( H([A\A]A^A_] D IA! LH߹ 1H LLcL)J<;5 @ LE H| 1ѰHN48|f D 1IM-HW 记LcIEMA~4 uII+FHMLJ<;H8 L)H)1wLcO49! LJ<3H! 1L)PHI UHAWAVAUATSH(MdH%( HEH H{HHLpIHLhH q HM U~^M M~ M LLEDA A~4 MM+F f HE1LMH 1eLLcML)J<;M M AE*< MME-HN 1L)HN48AE+ DHUdH+%( H([A\A]A^A_] D IA! LH߹ 1H 辮LLcL)J<;5 @ LE H< 1葮HN48|f D 1IM-HbU nLcIEMA~4 uII+FHMLJ<;H L)H)17LcO49! LJ<3H 1L)HIA UHAWAVAUATSH8MdH %( H]H H~yLsHHE IIMtIF HEHe!q H}D8HC`HE%EH}HH HE HH#E HE M AF, L{PEHCq ! I^ HL H HMD IȨ LL 1H LHcH)I< MH 1ˬLLcIL)K< M M AG*< MMG-H?L 1LML)}LMHcLAG+ HUdH+%( H8[A\A]A^A_] @ MH8q ~L{PLEEX A! LLX 1HE LLcL)K< LE 1LMHx ϫLMHcLX1IO-HR LM誫LMLcIGMA~4 uI+FIHMLK<H0 L)LEH)1kLEHcL @ AF0HEDX E H:q L{PEs 8ff. fLL1' A~4 IIM+Ff D LEA! f LI< Hy 1H)訪HH6f D \ Es u'H` u Hh uEff. fHaq L{P 6 UHAWAVAUATISHH8H dL,%( LmAH HH`DPhLxHLpPHq HM ~sM IW H HDUHUHUHMDDU IȨ A4 IIM+G HE1HAH 1LEQLELLcML)J< M$ M AF*<; DMF-HH 1L)LMLMHN,AF+ DHUdH+%( P H8[A\A]A^A_] D IA! LH߹ 1H_ DU蚨LDULcL)J< HEdH+%( H8EDLHL : [1A\Hh A]A^A_]>f D LJ<+H 1L) HI,f D LE 1LMH LMHN,f D 1IN-HN LMʧLMLcIFMA4 uII+GHMLJ<+HP L)H)1菧LcMff. @ UHATSHHdL$%( LeIHtyMttL9 G+tEH{-It$-w0 HSIL$I9T$ r1H9K sIH9tbHH)<f. AD$+uHWIL$H9t: 1I t HHHHUdH+%( u+H[A\]f D ID$ H+C D H @ 1ff. @ UHATSHL dH %( H]HM H HH P0uqH H H H@ Ht|HR H H H H Hq H H ~HH/HHu7HEdH+%( H HL[A\]HtHHUdH+%( ubH[A\] @ H H H+ f. HtHz u H eHHHNff. UHHH dH%( HUH Ht\Ht_HzHpHtHEdH+%( uJ D HuH@H+Bff. HUdH+%( u HH @ UHHH dH%( HUH Ht\Ht_HzPHpPHtHEdH+%( uJ] D HuH@XH+BXff. HUdH+%( u HH @ UHAUATSHHL dL$%( LeIM H HH P0uvI$ H H H@ H HR H H H H H/q H H ~HHX,HHu$I$ LAHuH I+$ HUdH+%( uqH[A\A]] I$ %I$ H+ HtHz t D H~HH lHHH UHHdH%( HE1HEdH+%( uH H H Ff D UHSHdH%( HE1H tHEdH+%( u H] D HH f. UHATSHHdL$%( LeIH Ht2I$ HtE*HHUdH+%( uKH[A\]f D +H I$ HHu @ LI$ HH ?ff. @ UHATSHHdL$%( LeIH Ht2I$ HtE *HHUdH+%( uKH[A\]f D {H I$ HHu @ LXI$ HH ff. @ UHHdH%( HE1HEdH+%( uɸ Jf. UHHdH%( HE1HEdH+%( u1 ff. f UHHdH%( HU1HUdH+%( uHff. UHHdH%( HEH H9GHUdH+%( u UHATSHHdL$%( LeIi>u HEdH+%( uCH[A\] D H;`HUdH+%( u H Lp8H[A\]Fff. UHATSHHdL$%( LeI=t5H H@0Ht%HUdH+%( u.HL[A\]f HEdH+%( u H[A\]s UHATSHHdL$%( LeIY=u 1HUdH+%( u,H[A\] L0=tI$ H9 UHSHdH %( H]H<tHq H9 HUdH+%( uH]ff. @ UHSHdH %( H]H<tHC q H9 HUdH+%( uH]Off. @ UHSHdH %( H]H.<tH; q H9 HUdH+%( uH]ff. @ UHSHdH %( H]H;tH q H9 HUdH+%( uH]ff. @ UHSHdH %( H]Hn;tH+ q H9 HUdH+%( uH]/ff. @ UHSHdH %( H]H;tH3 q H9 HUdH+%( uH]ff. @ UHSHdH %( H]H:tH q H9 HUdH+%( uH]off. @ UHAWAVAUATSHdL<%( L}IH HH9 IAHXA H:t,H H@(Ht LDL1EAI DIHCXHXI9 uHEdH+%( u HD[A\A]A^A_]f D A UH HHdH%( HE1H9 HUdH+%( uNff. UHHdH%( HEH H9G0HUdH+%( u UHATSHHdL$%( LeIu 1HUdH+%( u,H[A\] LtI$ H9 UHAWAVAUIATSHdH %( H]HSu'HEdH+%( H[A\A]A^A_] D A uL M M M~L;If D t;Lc LLLLH:HuՅnLI KD4H)A H9JA > D HH IHfs UHSHdH %( H]H^7tJ H-HHXHPhfHnfHnflflHX@hHUdH+%( u;H]f D Ht H D Hff. UHHSHdH%( HE1Hwr H ЋCt 1HUdH+%( uuH] D H{ RHƸHtHFXH=q dž fHnHFhfHnHflHFPflNXFhC ;3z UHAWAVAUATSH H $ H H $ HXHIHdH<%( H}H=V { LH=E | LL-r 1MII6HQ LLH37 HH= D H[M| M'Mt_LH= LH= Mg H[ID H0L`H= u I<$@I$H[IDH;q H;q H;q , H;q O H;q * H;Cq M H;fq S H[Md AL$ 'HH ID$L~Дp H H LHF HHqfHnHկFx HF(HflHF0HǓHF8H HF@HAHFHHHFPHHFHFXfHnHFhFfHnHF| flflNX Fh5ID$Hx tAF$ H[AD 1HUdH+%( O HX [A\A]A^A_]ÃI H5r LL 1 H5r LL1^ H5r LL0 H5r LL0M H5r LL0P H5r LL0@ H5r LL0h H5r LLh0Z H5r LLN06 H5r LL40 H5r LL0 H5r LL 0z H5r LL/ H5r LL/0 f. MgI<$I7I$MgHH= cbI<$I$H[ID H0L`HLdLBu LAt L%Yq I4$H6H= q H@( `Hq H:A, BH [HH2fH[MdI<$I$9 D H@0 D H@8 D H@4 D H@< Hq @'1H@H r H ЋSH{ HH H@XHfHnHFhfHnH/flHFPflNX FhC 17 qH r 1IIu HtrLLt-H r u\H*q 8L H[HDH;p H;<q H[HH< I uH5 r H LL,1 Hq : L% r HkMlL;- p 3 L;-p m HkHI<` NH@, ( 1 'H5p H H]1I $I1Hp H 01-H5 r HtLL+¸ H5 r HtLL+¸ H5 r HtLL+¸ H5 r HtLLu+¸ H5 r HtLLO+¸ jH5 r HtLL)+¸ DH5 r HtLL+¸ H5 r HtLL*¸ H5 r HtLL*¸ H5 r HtLL*¸ Hp H Dx Z LIHF . HHH LpL/ LHt. L`H5O# A LLH ~ p HH5 LfHnfl)_ H ;% : HE1HHH HHHHuaHH9tXH uL HHLL3HHtML I멸 IM* A|$ LH5@& I$0 Lw(H v G HHy 1L E1E1ɉ foL IFLF H=p HHާHF(HHFH(HFHHHFPHFXfHnHFhH^0fHnH^8flH^@flFx LN| D ~NXFh+M6M*L賿w1H{1! H;A HL M$$HH EDžL ff. ff. M$$L9[ A|$uI$0 LHHt˿ HHH E1L E1foH H=p D HAL^ HHRHF(HHFHHFHHaHFPHFXfHnHFhH^0fHn1H^8flHF|flH^@ Fx D vNXFhi*1HH L ff. ff. M$$L94A|$uI$0 Lp( L foL 1H=p IFH^0HH?HF(1HF HHFHHFHHHHFPHFXfHnHFhH^8fHn1H^@flHF|flFx D nNXFhT)M6M HH,Hp H| 01'LL̼ LUH/ H[HHHtL 1foH 1H=;p HB1HV HHHF(HHFHHF0HF8HF@H(HFHHHFPHFXfHnHFhFx fHnHN|flD fl fNXFh(L˻HH H}p 01%L5cp A6HH 1 %H>p MHHyU 01{%xMM QU 5 +Hp H 101%%H@, L5p H1M$ HT A6$ff. @ UHAVAUATSHdL$%( LeL%9p I$L9t9AAHXf D HX$tH @8D9t,HCXHXL9uHEdH+%( uH[A\A]A^] Dsxff. f UHAVAUATSHdL$%( LeL%p I$L9 IHXH4 ff. H#AńtHH @8<~ < H/p H Ht E1DkxHCXHXL9uI$HXL9t`ff. @ H(#t{x t?HCXHXL9uI$HXL9t% @ H" HCXCx HXL9uHEdH+%( H[A\A]A^] Hip 1H HtxSxHCXHXL9<H"tH @8<) < tH >p 1҃9u< $ Hm HcH>HCXHXL9 ;f. Hp H H1HH J L@ Hp :`< UH^ HcH>HQp H H) 1H t L@ Hp 1H HfHp 1H Hf1}Hp 1H H]_Hp 1H H?A16H q L@H L1eSHap H H9/1H L@ H)p H H1H L@uHp H H1xH m L@= Hp H H18H & L@ Hqp H HI?1H L@ H1p H H 1H L@} Hp 1H HHp 1H Hfhff. @ UHAWAVAUIHATE1SHdH %( H]HH5q HIH H5 H1y DH@HKq H ЋKt(1HUdH+%( b H[A\A]A^A_] @ H{ HHN H@XLdž fHnHFhfHnHflHFPflNXFhC s H5q LHA H5q LHA H5q LHA H5q LHA H5q LHA hH5q LHA HH5q LHA (`H5q LHA @H5q LHA H5yq LHA H5qq LHA H5iq LHA H5aq LHA hL=q E1I7HZ LH?G KdH q H S HH ~|p HCLH H HF HH,fHnFx HHF(flH={HF0H{HF8H{HF@HHFHHaHFPHfHFHFXfHnHFhFHF| fHnfldž flNXFhEC f H=1K DvHp Hi 101f D hf D AIA H q E1II7HtYLHH q uCHtp 8 KdH C LHe7w AIA uH5kq HtBLHK1u/Hp : HkH 8q HÃ{ H55q HtLH¸ tH5+q HtLH¸ tH5!q HtLH¸ gH5q HtLH¸ AH5q HtLHm¸ H5q HtLHG¸ H5q HtLH!¸ H5q HtLH¸ H5q HtLH¸ H5q Ht#LHu ^ ff. f UHHdH%( HUHq q H0ff. ff. f H0@ H9uq q q q q q $q 2q @q Nq \q jq xq q q q q q q q q &q 4q Bq Pq ^q lq "q 0q >q Lq Zq hq vq q q q q HEdH+%( uX UHHdH%( HE1Ht?+HUdH+%( u @ UHAWAVAUATSH HxdH %( H]H p H;H ,(H; H0p Hp LGHx H HUHEHp HEHXp HEHp HEH2p HEt:HxHH9u%)ff. H H9x xtHp HLŐ1H} H? E H}H;H țH`H Hyp H8HX"'u>Hp 8t2H A H`HHB HTp x fL`E1E11A ff. H5 LqIHt9 AEA <{ <}A!A A? MPuEM D A? tZMHxH=p DLLhLp0LpLh Muf H`褩" Hp Hp H9t)HxH=Kp H5b 躙Å HLp 8tHXHH HHpH8 Hw%Hp<H ? LuL= LL{IHH L-p (f D > LL1JIHD LLõÃuH= L1HpHEdH+%( { HĈ [A\A]A^A_] A D Hp H8HX$Hp H4p Hx H HUHEHrp HEHp HEHDp HEHp HEt)HxHH9ufH H9xF xtHp H|ŐHp苧ff. L-Ip LLHxLZ HAp H B Hp x HD H= 1"Hpu"L H5 LH LH= 1H`踦4 H= L1H`蓦LH= 1HplHp^L`1H}HHo Mm H`H]Hp H`x tfHtoH H`HH]L`H}HH yHE H`覥HEH`H` HNp HO@ 101H[p H=\ Hp x HDUH=;@ FH`*L H= Hp H|? 101xHP@ Hp 101UHj? UfHSHHPp dH %( H]H dp H HFp H C$HEdH+%( u HH]U D UHAWL= q AVAUATLeSH(dL,%( LmILH, LXhL0LLMP H;2f LH5 L1|L\IM9t/M7MtJ~ʺ H5 L L=!q M 1 LH5 L1 L脾\IM9t/M7MtJ~ʺ H5x L q L=qq M8 1 LH5< L1L\IM9t/M7MtJ~ʺ H5 L L=q M 1 LH5 L1,L褽\IM9t/M7MtJ~ʺ H5 L 1L LHSHEdH+%( uH(H[A\A]A^A_]f. f. f UHHdH%( HE1HEdH+%( u1譱ff. f UHHdH%( HE1HEdH+%( upkff. UHHdH%( HE1HEdH+%( u H@ $ @ UHSHdH %( H]HH09CHC HUdH+%( uH]˰ff. UHSHdH %( H]HH(ڦHC( H{0@H{87HC HEdH+%( uH]1\ff. UHAWAVAUATSHH(udL,%( LmL M L%p A|$ 1E1AU IH A|$ H HHHfD I I I Ht#N(f D ~(9t AyvI I 1I HHW H o o@H~Fo@ F o@0F0o@@F@o@PFPo@`F`o@pFpo H H Ht%O(f D DG(9tADAvM H~IpHHt"N( D ~(9t AyvIpHfA t_A|$ tWIP fIdžH IP IX I` I` Ih Idž Idž@ A I Ht A I H I Ht!H/p H;8t轎I Hl Ic$ t I H: IF0I fHnflAF0i(fA|$ I A A0 HEdH+%( o H(L[A\A]A^A_] D A AU IH)E1 H I H AoF@} AoFP@AoF`@ AoFp@0I Hp@Idž fAF@AFPAF`AFpfAƆ ! L-r L QI I I Ht!'I Hx@'I I Ht'I Hx@'I 'I LE1AU~۫ff. UHSHdH %( H]HH誏HtHC(1HUdH+%( u H]ø~ff. UHAUATSHLo0dH%( HE1M LcgD9'"HUdH+%( H[A\A]] @ H~H|KIDMd I|$@5H{HCIL$HHt&Q(f q(9t BrvfHnAD$PCID$XHC( \f D 1O脪 @ UHATSHLgdH %( H]HL%Ht2I$ C HHC01HUdH+%( uH[A\]øf UHSHdH %( H]HNHtGHPH@ HP H H< Ht"C HC81HUdH+%( u H]ø薩f D UHATSHHdL$%( LeIHt<HH9Ht3Hp Ht*HEdH+%( u5SPHL[A\] HEdH+%( u H1[A\] f UHAWAVAUATSHdL,%( LmL IH HPHH9toIIHZM9 LLHS@HuIIH HHShHZH9t/M$ {x uHatLHu @ 1HUdH+%( uH[A\A]A^A_]3 UfHAWAVAUIATSH8L?dL$%( LeI)EM HA D HCHHt'IIwLHHHCHE1HuI|$fM|$AD$ H;E L<A$ ulI$8 HEM$0 HEHtAHLkII;$8 | LHH}LMtL foEA$0 HEdH+%( uPH8[A\A]A^A_] @ I|$AD$ ID$ I} I}; H@I$8 o讦ff. UHHdH%( HE1HEdH+%( u1mff. fUHAVAUATSHdH%( HE1H IIMe Mtff. I HPHHZH9u vf D I HShHHZH9tXLLHS8HtID$IHD$IHuL<IH}HEdH+%( ucH[A\A]A^] @ IF8IN0IT$0I( fHnIV8I$ fHnflAD$0HLIH 9f UHHdH%( HE1HEdH+%( u1ff. f UHHdH%( HE1HEdH+%( u1轤ff. fUHATISHHGpdH %( H]HHtH HtH;B t ID$hHtH; t I$ HtH HtMH-dHt?A$D x; uHEdH+%( u%H[A\] @ f UHHdH%( HE1w HUdH+%( u襣 D UHHdH%( HE1fw HEdH+%( ue D UHAUAATISHdH %( H]؉u1f9r HUdH+%( u"H[A\A]]fDL f D UHATS1HdL$%( LeIff. @ 1L14uHEdH+%( u H[A\]菢ff. @ UHAVAUATSHdH%( HE1H t$HEdH+%( H[A\A]A^] @ H HIHj H p @(9PP1HL5p I$ HA I$ HtHx HI$ HtP( HsI$ H H@H% H &p @(1P Ҿ H-I$ H@Hx HI$ H@PHC H p @( P Ҿ HI$ H@HHx HI$ H Ht ͫ" H}I$ H Ht褫# HTI$ H# H@PH Dh( HAU AU H I$ H@H P( H߃I$ H@HH Hx H H H Hy Hg HU HC H1 H H ' H H H ( H ) H * H + H , H} / HkA> ! HOHߺ =I$ Ht.kIHp H8Y HI9ICI$ Ht0 H I$ I$ Ht$ H M$ MZI$ LH } Ht Hx 诨HEdH+%( " HH߾ [A\A]A^]@ H. f P P- AU H|0 Hf D HfI I~H I H HVtHߺ > H, H Hߺ H?fZI LI~H AI 3 H< 1 HיL5Xp fI I~H ~I p HͿY H - Hߺ HOfI I~H I HL H. Hߺ HϘfI I~H I H̾BfUfHAWAVAUATSH8HuHMLEDMdH%( HE1LbM5 ILLnIHEL8M[ A IIwHIOHIOE1HHuH{fL{S H9E$ Hu4 H HPHLjH9t9ff. IUH LHH IUhHLjH9uH} tH} IFH } t)Hzp x HUH@ H HP MHEdH+%( 6 H8[A\A]A^A_] D IUhLjH9/Wf. H{fHC C H8HEHx @ IFPHL <DMLEH0 H HuLC Hp z uCHS@@^ʑ HxTfH*Y f/s"H,HM @ H H @ \H,H?HMHуfHH H*Xyf UHH dH%( HE!Hp x H H HV@HP@HVHHPHHVPHPPHVXHPXHV`HP`HVhHPhHVpHPpHVxHPx uDƀ% ƀ' ǀ H Hu t5HEdH+%( uo @ H HX Ɔ% Ɔ' dž HF@HGPH HEdH+%( uf. UHAVE1AUIATSHH_0dL$%( LeAޙHu 7 HADHHt E9} uHsL"HEdH+%( u H[A\A]A^]ff. @ UHATSHH0dH%( HE1Ht)A1fHHtA9uHG D 1HUdH+%( u H[A\] UHAWAVE1AUIATASHH(dL<%( L}IHt+LvMt"AV( AN(9t BJvHKHMH{HMEHHS MAą HC@LHAą HC@LHPAą~ H{ t'HCHHt L LHAąuW HC@LHPHS@t{LHRAąu+H{ tHCHHtL1LHAąt HC@LHP L۷HEdH+%( u*H(D[A\A]A^A_]f. LHR Amff. f UHAVAUATSHdL$%( LeL I$H HPHH9tdIIHZ2 LLHS0HuAI$H HShHHZH9t&HΗtLHuf 1HUdH+%( u H[A\A]A^]蝒ff. fUHAWAVIAUA ATISH8HUL MI dH%( HEHF@HEHu* f D ILzxLzE1IH HLHHuр} HȾp HEHEx tH HM@@HI$ I$ IDŽ$ ZI$ Ht*W( J9rO(9S uIH IDŽ$ @,txH I$ H9tdH HtHrH-H H ZI$ Ht%Q( q(9t BrvH HE} I@ t8HEP2I$ x Q u HMHH HEdH+%( h H8L[A\A]A^A_] uL IHtĀ} Hp HEfIFHIv I $AD$M'EtLfLHE} @6HMQ2 t~MHMIL$P<I$ $ f Hp HE`x VA$ I$ HuHpX5Hp`, HMIL$HI$ HMHHfHMIL$XI$ HMHHf. AoT$PAoL$`Aot$pAo\$@ocPok`oCpo{@A$ ff Hp fff [@HESPK`Cpx H HMHHXHH`| HMIL$`I$ HMHH t*~ UIH HHP oFdH%( HE1HHHFHULHLpHPHH)@)HUdH+%( u裍 UHAWAVAUIATLSHH EHHH>LuLpHPL} LxldH%( HE1H`$H LA~F8HXH`AoMHIF0Dž HA fHnA flAoE HfofH~ff)) 'LXLPfH0HHMtAoAxIF@H59p H8A~ INH(HXIFxAE(H L0HhIF8HA~E4HpA fpHxA fօ`HAE2I` HAE0"FA E1IE HHt H1HH)HxH8H@LLHHHHplL}HXI HDžP H`AF\h@ IuRHt"f tƃ@ Hͷp u;HEdH+%( HĘ L[A\A]A^A_] Huf A$ 9T1Af +D9r1fAnFXfAnf IFHcfbHI$ HfBgfBA$ Nff. UIHHLMHSHLML]dH%( HEE H]dH+ %( uLU H]EL]E UHHdH%( HE1Ej PuHUdH+%( u蠉 UHSHLG(HGdH %( H]HHKMtNH HA8 HHDHS E1HA0jQ1ZYHt"HC1HUdH+%( uH]ø U1E1E1HSHHW HGdH %( H]HjH sBZYHtHC1HUdH+%( u H]ø褈 @ UH HAWAVIAUATLSHH oHWdH%( HE1oNLLo8LfoHHffHfH~)) HHH0IF(HPAF4dIF HHC H(I H@H@H H`B\hH@HH r,H o {)Po@)`HP HpHH HPH)PHXHIPHHH HP E1| ID9{ K| LHuHC 1HUdH+%( He[A\A]A^A_] @ H H9Pu LpHtID9{~1K| H H HH tHmHuK| fHS j 1E1HH@E1LZYHtUHcSf HCJKID 5Hp z $HHHPH@ HS0if UHAVAUATSHdL$%( LeL I$H HPHH9tdIIHZ2 LLHS8HuAI$H HShHHZH9t&HntLH菨uf 1HUdH+%( u H[A\A]A^]=ff. f UHATSHL dH %( H]HH nHǃ H H HtG H Hx@v H H 胿H H pH KH Ht,3 H Hx@# H zHǃ H HtH Ht7W(t$ J9rO(9 uHǃ H 賦H 触H 贾H Ht8 uKH@ 7H rH fHEdH+%( uBID$HH[A\]f D H 3f. UcsKYf U HAWAVAUATSH(dL,%( LmLn@M J IHL)HHF@ )HVh H H)HVpHHFhH H)HVxHHFpH H)HHFxHkp x tsH HH H)ʋH@HH )HH(P@H H)HH0HHP(H H)HH8HHP0H H)HHP8H@ . HC@u HL)I$ uI$ L8 Mu @ M LM}M8LLIZtI H H H0 L;~ LHUHUL;r HLIl$HA uIl$PLMkHC@HHUdH+%( u~H([A\A]A^A_]f. I$H It$8@$uIt$ IT$(U D LHUHuHHuHUHF9 L(HUHB7薀f D UHAWAVAUATSH(dH %( H]H_0H HG(IHE @ ImPLMtjLHLsIH HtpH L0 L;vt|LI;_ LHImH tLMuHEdH+%( uvH([A\A]A^A_]f D IH Iu8@$uIu L}L;vuLHuHuLHFI;_pf. HIGUJf. UHAWAVAUL ATSHdH %( H]HL<H Ht5L LqLLH LH HuH L Ht= L L!LLH /LGH HuH L Ht= L LLLH LH HuL H Mu L9tt @ IUMeHHzLxI9tx HW`HPHmLIGXHWXLxL9uIU IELMHBHmII9t I D HEdH+%( uH[A\A]A^A_]fLv}f D UHAWAVAUATSH8UdH %( H]H_0H I@ HG8HEl H H0 L;v LHUHUL;j HLIl$HA uIl$PLH, HLsII*} Ht A .uLL<tI HXI$H HuH$uIt$ IT$(L;vILHUHuHuHUHF(HG(HEu"G Il$PLMtuLHLsvIH HtH L0 L;v LgI;_ LHRIl$H tL[Muf D HEdH+%( H8[A\A]A^A_]f D I$H It$8@$uIt$ L}L;vrLHuHuLHFI;_^ff. HIGB LHUlHUHB HG8HEjf D H H0 L;v LHUDHUL;j HL+Il$HA uIl$PL-HIHLsIA .HtLLtI H^I$H HuP$uIt$ IT$(L;vOLHUHuoHuHUHF.f D LHULHUHB)yf. UHHATSHH dH %( H]HHXH9H t IHP9| HEdH+%( uZH[A\] @ I<$It$Hc)؉HH)I<$It$HEdH+%( u HLe H# 1[A\]鵠 y UHAUATL SHdH %( H]HLkLLk HSIEH9HBHC HEdH+%( uHL[A\A]]xff. @ UHAWAVAUATSHxHpdH%( HEHH P$u$1HUdH+%( c Hx[A\A]A^A_]HGH H}4L`MtL]HEI[8L]Hx @ Hp EċEĉEuLRHHEL;`I HuLUHvp Lxp HELu@ Lx8A Mu E f D IFIE1Ht%ILL oHtUM6yIFIHuHEfH@HM<$AD$M&E HxLH}LU AoT$PAoL$`AoD$pAo\$@AooPAow`AopAog@A$ ffA Hvp ffAWPA_@x AO`AGp fA$ tH=p x L#HpHt HHIIfH@HI$ AD$L`8HEL`@LP HP HEL9tHhE1@uff. fAFP" A~T HEL(M EI^ L}I߈ELMIIE HXI9uO HChHXI9t;LLHS8HtMNxE MNIH0 IIE HXI9uLMAod$PAol$`Aot$pAo|$@IAoUPAoM`AoEpAo]@A$ ffA ffAUPA]@AM`AEpI MHEEA EM6HEI9HhM'fA AƇ H<p x śIH7 HLI$@ I@ *L f. LL}MIƾ LLMH HMI~LMHAHH p H H L . IvH^H9 LMLeIHf D L HLeLMH u5Mt0ff. D A M Muff. H p H tsH H7L~H9 H]LILM HCXHXI9 HctLMH]LI A z HH }p H tyH H7L~H9v H]LILM @ HCXHXI9 B H蓀tLMH]LA uHt H HuH HLMM~ HEgIv HELMI9H^tzLMLmI H8} IDŽ$ H\ IDŽ$ HzttIDŽ$ HChHXI9uLLMLmf} L(`ItHMHAHuHHE Lm H Hu| IDž HChHXI9tHh|0Hu IDž H}! D IDž L0ID$XL`H9 LeLMHM~ A H @ 8LHMHALMH]L HR H @ mLMH]L H. @ I$ I ojoPor oz0ooH fo@0o(PfR@P@ffH @0H H L3 ˖IHHLI$@ I@ 0LAEL H IEEH @ $@ nff. UfHHdH%( HE1GH HEdH+%( un UHH dH%( HEHF@u HGPH HGHH HEdH+%( u,nff. UHAWAVIAUATSHXHMH ǚp HuLEy UH qp A^g dH%( HEHG`HDGXH fH*Yf/Xg H,HELhLqHJp x IH @$ IF L@fIN(AF(Mr LEHMLuff. H}H} ItHuH}HEЅ } H]Lmt-Hzp HUx H ep H@ H Q HELx(MK LeA ID$IHt)IIwHM$$HID$IE1HuH{fL{C I<$E HuH p HQLaLrL9t% IFH LHIFhLpL9uH}H HEHt H_MHEdH+%( HX[A\A]A^A_] @ \Xe H,H?HEIF8* @ IFhLpL9GdfH{fHC C Hx(HEHx0 MiLLmI H}H" Hїp x usHC@H p A^d HxbfH*Yf/d s(H,HfHH H*X\Od H,H?H H HfHH H*XLEHuIN(IV8DL fIF0A ff. fHQHH蜿HS(I uI Hu!ifUHAWAVAUATISHH8HuHUdH%( HE1H f Lk0HC0I9 M}I9u#lff. f MG0MxI9tKM9 uꀻ u H( I LLXtH軾HHu1 HUdH+%( H8[A\A]A^A_]ÐHEL8M2 Eff. I HPHLrH9u$ I IVhHLrH9 HLLAV8HtIWxE IWHHtI뗾 HHUH5HUf} L8@IH HuHHEHEfLƀ HL Hǀ H@HPH`HpfHEIO0fHnI IG8Mo8fHnflAE L(T HaHHMfH @HHMIHAD}gff. f UIHHHH p dL%( LEIPHtu*HMdH+ %( u? PHHǀ LfHuG( u f UHHdH%( HE1HEdH+%( u 11|f UHHdH%( HE1HEdH+%( uH7p E11P@[fff. UHHdH%( HE1HEdH+%( uHp HE1P ff. UHH dH%( HEHu Hx耿% uHUdH+%( u" D H0 \ Hxte UHSH dH %( H]H_u9t4 uu&H Hu$f. H HtH{諺HtHHEdH+%( u HH]ef D UfHAWAVAAUATISH8dL<%( L}IHGP LJ HLJ )EhI\$0Hu1` / DLLH߾ 謟HHtWLkLDLWyD fH HCh K(K8KHKXUHHuID$0fA$ H fHHuHS(I$ uI$ HuI\$0H HEM|$(HE%f D LHEH}LiMtdLHLkII;\$0uHID$0 @ DH߾ 耞H fA$ foEAD$(HEdH+%( uH8[A\A]A^A_]cf UHSHdH %( H]H΄Hu)H HPHHEHUdH+%( u$H]fHHEdH+%( u H]餌bff. @ UHATSHH2p dL$%( LeIx t4HEdH+%( IT$hHL [A\]' ADŽ$ LID$P IDŽ$ eI\$0HuDff. fHEdH+%( uNH[A\] H1HHtID$hHt H; uHs L~aff. UHATSHH"p dL$%( LeIx t4HEdH+%( IT$pHL1[A\]f. ADŽ$ LID$P IDŽ$ dI\$0HuVff. fHEdH+%( uTH[A\] H HtH;B t! HHHtID$pHuHs1Lh` UHATSHHp dL$%( LeIx t4HEdH+%( I$ HL [A\] @ ADŽ$ LID$P IDŽ$ cI\$0Hu\ff. fHEdH+%( ubH[A\] H-qHt:Hs LHHHtI$ HtH Hu J_f. UHATSHHp dL$%( LeIx t4HEdH+%( HI$D L [A\] @ ADŽ$ LID$P IDŽ$ bI\$0HuLff. fHEdH+%( uOH[A\] ; t# @HHHtA$D yHs L=^ff. f UHHdH%( HE1G0D0HEdH+%( u] @ UHHdH%( HE1 HEdH+%( u] UHHdH%( HE1 @u HEdH+%( ul]ff. UHATSHHGdH %( H]HLcMt^1H A$ @mHsL譾AH{(ASHC( HC HEdH+%( uHD[A\]A\f UHAUATSHHcWHGdH %( H]HHOH0LL HJBL׀{P tMbMtnMbPMte HA0 L HDHS E1E1HA8jQL萪IXZMt@1LA$ @lCLcC1HUdH+%( uHe[A\A]]ø[f. UHATSHdH %( H]H_HtKHG HG1 Lg@H lHEdH+%( u-HLH[A\]HEdH+%( u H1[A\]1[ U1E1E1HAWAVAUATSHLHGdH %( H]HHW Lw8jAWL LPZYHtqIHCHcCLLPSM$YHtHPH@ HP 1LA$ @k1HUdH+%( uHe[A\A]A^A_]ø\Zff. UHHdH%( HE1 HEdH+%( uZf UHAUATSHHp dL,%( LmIx HH P$u~H LgMtS IH @$ I]8f. HtLH@QHxCtIH[HuLIHuHEdH+%( H[A\A]]H8 @ H[fID$8IL$0HS0LfHnIT$8fHnflC0H萮IHDfIE HTHEdH+%( uH@HIu8[A\A]]nXf UHAWAVAUATSH(H}dH%( HEH[p x HH P$ Hv L~Mu D LحIH I_0I;_0uHMHH @$\ HA8HEIMu A Mu' D IU LjxLjE1IE Ht~ILLOHuIF8IN0I^8LfHnfHnflAG0H1IHY1HUdH+%( / H([A\A]A^A_]ÐH8 LH HMfHǀ P@H H p PPy P`PpusfL0XIE EtHMHAHuHHEHuH}zHEƀ I HA HEIf D H HF@ VV V0jHEdH+%( u HN@H(HW81[A\A]A^A_]q\Vff. UHHdH%( HEHH @$tYH8HHt9ff. HG0HW0fHnHG8flHBHG0kHHuHEdH+%( u 1H U D UHAWAVAUATSHH(H dL$%( LeMHxuHxHtH; u%HEdH+%( H([A\A]A^A_] G tHM vIHtHAAxfDMMHHP M| 1fA LAׇA Iw@I I$AuHE11Ht3 HHPMt I~@JLBAD$IH;rHEdH+%( H(L[A\A]A^A_]\D @ A L1AI &A I$AuUf. uDM| A LLAMg@I ɆAu f D Md A$ L1AI 荆AuSff. f UHAWAVAUATSHdL<%( L}L?L9 H p IIE1 EH E M?M9 {) tA@ u AH tL@H)~ LH1ME@ HIEtH H_ L1 yMEH HIEtH H- L1 GMM?HIM9RHUdH+%( u HL[A\A]A^A_] D E1FRf D UHHH~p dH%( HEH z HD HUdH+%( uQ UHATSH D EdH%( HE1E H8 H_Hu HHXHtm uH Lc@EH H.~p z t H L"MxYfI*YK HxjfH*^Z/EAHEdH+%( ucH D[A\] E1 LAfHL H*XYJ HyHfHH H*XfPff. UHAWAVIH AUATISHH (D@ L0 dH%( HEH H8H H@ H 4=fH |p H ))y ))fo9a HH)`fo3a ntE M y t I9XY y tKHHH5z aHt3( H_L识LHH`1 @ ( H_L|LHHyv A`L ~L ð AWH HLP1APHD_vMNxH AMt)HcH1HH)L z L AH@HtFIH Q!@8 DA H f IcHHy 1H)LvAH8Ht$IcH 1HH)Hy LuAŋ4x IcHy 1H)LHuAHEdH+%( HeD[A\A]A^A_] D H b IcHH(y 1H)LguAN LIH%y 1LǾ@ L(-uH_L讄L(HHt - A`L H LLH02ILHH yp HtFy IpH uc!H; u'@ L0 H IHtH9uf. LH @ H9 u狰D L8 H IHtH9u LIHw 1LǾ@ L(tH_L膃L(HH`H@TJHK @ H@DH5JDHHxK UHSHdH %( H]HH5fw Hԏu(Hxp @1HUdH+%( uRH]f D H54w H虏u HFxp @ H9sp Hٿ Hw 01yMKff. f UHSHdH %( H]HH5v 'tHEdH+%( u,H]1 @ HEdH+%( uHH]11阁J UHATISHHHHdH%( HE1HLJX HH)h HH[ H oCHP ǃD LH HP HX HEdH+%( u H1[A\]*Jf. UHǀ HHH5qp dH%( HE1貇HEdH+%( u1If. UH5 HSHdH%( HUHcλÅuHEdH+%( u+H]ÐHsp ( H=H H耲YIf UfHnflHHdH%( HEHGfHnflGHEdH+%( uI @ UHAWAVAUATSH H $ H 1ۉ$H0IHdL,%( LmIH(tugLI@K hIH LhHt#u x.HXuW{ uQL1hHuLRex L&UHEdH+%( ? Hĸ [A\A]A^A_] D x.u{.u { tf D Mt7Iu H M} I7IH HHtLIL1H LQoH(LrÅxnH% = @ u:$$LLpX> @ L>L#dHnp L H< 01 LcF D UHSH H $ H@HB< ~zp fHnH^I L fldL %( LMIVH HH1HDž )蛾H1HJHUdH+%( uH]0F UHATLfH5 ~ SH]H ~p dH%( HEHq HE fHnfl)E H3HHt LDtHUdH+%( u H [A\]E UHHdH%( HEHlp HEdH+%( ugE UHHdH%( HEHlp HEdH+%( u'E UH=p HATSHdH %( H]H]HQiL%qp uEA$HH= 0iu Hmp UA$HUdH+%( u H[A\]Dff. @ UHSH r dH%( HE1t! r HEdH+%( u6H] HuH=?p hxҋEr È r D UHHdH%( HEHhrp 8 uO*Hmp 8 uO*G HEdH+%( uCf. UHAWAVAUATSH dH%( HE1?/ L0AILLȤ H;/t / H[IHt|A$ LLI\$膤u"A|$/A$/u D H;/t D DL@tA$/ HUdH+%( u6HĨ [A\A]A^A_]LLu1DL?Bf D UHHdH%( HE1HEdH+%( u 1ҾYTB @ UHHdH%( HE1~.HUdH+%( uB UHAWAVIAUATSHdL<%( L}I3bH 11I>VIH MtqLbHHt)HLAׄtHsL'LaHHuL|^HEdH+%( uBHL[A\A]A^A_] HpL|'LaHu D 賞 &AE1륐 UH*m H5fHnHAUATSH(~o dL$%( LeIHE fl)E%Ht2HXIHuL @ H0HHt8HsLtHU1LHUdH+%( uH([A\A]]L(sa@ UHHHdH%( HE tff. HHuHUdH+%( u@ UH=!l HHdH4%( HuHuGd¸uEHUdH+%( u? UHSHdH %( H] <t HUdH+%( u$H] @ & <u99Y?f UHAWAVAUI ATISH ek HH dL4%( LuI( E1H@!Åa Mt M MtYEuTL1H0H,L8LH5j x ,08A$HEdH+%( Hĸ [A\A]A^A_]f. HLL +CD5 T HDž0 HDž8 M HH5 HHy H8H0H ;HIpKM H8 HcH HxH(1H$L,H5i SH8Ãu5$(,A$R-A D Hep HH 01AH8-Af. {8dwH] HHdp 0 1H8, @ Hdp HHW 0Hldp L H 01謖}<8vH HH#dp 01rGff. f UHATSH dL$%( LeIH H=lh HuHuHE nPHtyHË@u/E1HnHEdH+%( ubH D[A\]f KKHHHmHh LHH1ςyA D An;ff. UHcHHSHdH %( H]HH=g ;~%H HEdH+%( u HH] perfC : UHAUATSH dH %( H]HtyL+L%8g MtH5<g L~ LrL%\bp Hg H1A4$蚔{ uDHEdH+%( uzH[A\A]]f. L%f H5ơ LT HEdH+%( u6A4$H11[HU A\A]]# LL`TH9f D UHAUATSH H $ HHH`f dH%( HE1LHL LHDž 2a LLR9~VHƄ f/tBH51 L{KHu.HIL H hx H 1HUdH+%( uHH [A\A]]8 @ UHAWAVIAUIHATSH(H}M} LdL$%( LeMMu/ H?w$HY?1HHH)H9r HH H9sI9tbLHNHEHtuM| Mt1LHEIHf LLI1 HLL9uHEHMHI] 1HUdH+%( uLH([A\A]A^A_] f HLHEIH0 MtI9e7f. f. UHATSH H $ HL dH%( HE1VLAHӾ L莯HLSHUdH+%( u He[A\]&7f D UHATSHUH dH %( H]HHuH, HUAHE H}HE#ff. ff. 4VԀvTHHHEuHHH5$ 1c~?H}&HEdH+%( u4H D[A\] HMH AA;6ff. UHATSH H $ HdH%( HE1 r r H HIL1L L = H5a r Lu=1ILCb L 躭= SH5 r LDt H !]p 3 r 11HF aHEdH+%( u2H [A\]f D H \p 11H 3"4ff. UHHNdH%( HEG9u GN9t)HUdH+%( u:ËG N 9uGN9uًGN9uϋGN9uŋG N 9u+s4 UHSH H $ HdH%( HE1 r ]H HI 1LL HJ= +H5 r HuPHEdH+%( uJH] H [p 11H 3ڍ3 b r 11H H a[p 3f UHHdH<%( H}Hvft?ɍA?I19|HEdH+%( uBɉ HHH#T @ ɍA I19} H#T 3 UHATSHdH %( H]VIHt~Hx H]5HEdH+%( u HL[A\]2ff. f UHAVAUATSHdL$%( LeIf f ftIHZp H 101X1f D HEdH+%( HH[A\A]A^] D A|$ HHtAL$ftQ ML$HLM9sIDLGI9 ? fvf1Hf. AoLfofofofifufafefofafifofoffff\GDGHH9uȃ)rvwD@f~+ C~ DfoJ4fufofafafpNfefofafafpNfofofffff fFzACTDfDBTP9PEDTfADDƃDD91ATDfD։T AT$AD$)AT$|HH1A|$ t @ AD$AT$f9J)ff. @ 0D9u D A\$, E1E1fK| }IAD9~fA|$uC|f. D(HH<El$E1E1E1A EAf D IED9fA Kt H/ H< H 0 fuHuHuHuHH AIcA AщLH?fLHHH!T H A0 fuHDɄuHuHuHtTHADAIA D9CTHtHָ 1f D A 1~ AH/ @ IED9 11f. ATDftTH9rsDH9r^HEdH+%( uH1[A\A]A^] 1I`- UH5$Z HHdH%( HUHUuEHUdH+%( u-f. UH5Y HHdH%( HUHUGuEHUdH+%( u,f. UH5Y HHdH%( HUHUuEHUdH+%( uz,f. UH5ZY HHdH%( HUHUuEHUdH+%( u*,f. UHHdH%( HEr tHUdH+%( u @ sr +f D UHHdH%( HE1gr t]r HUdH+%( u @ [+ @ UHHdH%( HE1r t r HUdH+%( u @ 4+ @ UHHdH%( HEHr HtHcHUdH+%( u) @ HRp HW 01* UHAWAVAUATSH H $ H H $ H8dH%( HE1O Hc=+r HFqHr H ~HǾ H,ZIHv L1 L>W LG= LDJIH0 HL=& HL5 W ff. LJH xuHXH1LHa|~HH1MS LY H蚡ZH= Y IHHu D HIHtBx uHxH1L{~ԋH r Hߋ FIHuHEL1IH LE1HUdH+%( uHe[A\A]A^A_] HQPp HU 101蒂H.Pp H2 101oH Pp H HLU 101J#( UHAWA AVAUAATIS1H8HuHUdL4%( LuE1sA LA 8EHMHuH@ L b LEHL) PJ<1Lnd 1HƟY^HIff. @ L~9- L~9mL7A A @ DLe7sA9 LQ7DLEC7UEHuH 8b L t LDHMRL)PL T J<1 1AE1HHIXZ>f D EDLD)E6U)9UsA9_DL6EH a L LDHuHMHPL c L)J<1e HMp HM HhS 010HEdH+%( uHeL[A\A]A^A_]%f. U HATSLH dH %( H]HLz1L H_ HQ HUdH+%( uH H[A\]o%ff. @ UHAWIAVIAUATSH(HuHUdH%( HE1ycM xIHcGIH 1LE1/5A>f. EAGD AIǃALDHAT 4AL|D9HM )) HAD Ep0PW< G uAt=A,HHE 1HEdH+%( uLH(H[A\A]A^A_]f D HyHEHH) LHEHuD0 1# UHHdH%( HEHPq HtHUdH+%( uf. {MH$q }#ff. f UHHdH%( HE19tHUdH+%( uKf D V9WuV9WuًV 9W uыV9WuɋN9OuN9OuN 9O uF 9G " UHHdH%( HE1?tHUdH+%( u< uu܃ uփuЃuʃuă u " UfvHHdH%( HU1G GHUdH+%( uH:"f. UHcHHAUATSHdL,%( LmAH< oIHt,D(E~$1f HcÃHI|,A9uHEdH+%( uHL[A\A]]! D UHAWAVIAUATSHXH}HuHUMdH%( HE1x>HH 1LE1Le{1H}AxD9~of. HEHUDLЋ LsE1 D AI$D9;~{LLDtH}AD 1H}A0xD9H}D# xA9ui} I LHEdH+%( HXH[A\A]A^A_] D HcfoEHHBfoEBMJ$eHcHHH4 IHt} wIc4$I|$$ H TX UHATSHH}H0dL$%( LeA%~D]EȋEfoEC foECHEdH+%( u H0H[A\] UHAVAUAATSHH`dL4%( LuIPH}DAĸ DDLxoEEH})EoEE)ETuDefoEEfoEC CHEdH+%( uH`H[A\A]A^] ff. UHAVAUAATSHH`dL4%( LuI H}DAĸ DDL袓oEEH})EoEE)ETuDefoEEfoEC CHEdH+%( uH`H[A\A]A^] ff. UHAVAUATASHH`dL,%( LmIH}DALUoEEH})EoEE)E]SuDufoEEfoEC CHEdH+%( uH`H[A\A]A^]Z f. UHATSHH}H`dL$%( LeAU?oEEH})EoEE)ERuDefoEEfoEЉC CHEdH+%( u H`H[A\] D UHATSHH}H0dL$%( LeAzD EċEfoEC foECHEdH+%( u H0H[A\]S UHSH8dH %( H]HH}zfoEC foECHEdH+%( u HH] D UHAUATSHdL,%( LmIz. 9LAăX?AHcHzbIE HtLHIc1t H WbIEHt!AE 1HUdH+%( uH[A\A]]L=;ff. UHAUATLcSHHdH%( HE1- 9LAt D9#HEdH+%( uKH[A\A]]f DHSICIA Hc1IN ,"IJLcM!,$ @ UHSHdH%( HE1Ht7H-{ uAH{<HEdH+%( uHHH]< @ HEdH+%( u(H] H9L1HcJf. fUHSH H $ H dH<%( H}HP1xTx86_t+Ts390tg1HUdH+%( ucH] fX64urHE1H H H1@1H Xxt1f D UHAWAVAUATSH H $ HHIdH%( HE1HDž HDž qAؾ H HHHHH1A@1HGn HH5 K{HH HHH `HI%M L L0Ht LIFA H IE1 AID9 I4$L[uD9n 1I~ pL DHH7 1L5?H5 LVzIH HHH _LI$M~L L/Ht LIFA^H IE1 D AID97 Iu LZuD9 1ff. oLD HH 1LD>1LJ HH5 NyHHH HH ^H~jL L.Ht LIF A^H IE1 @ AIA9tkIu LYuD9tV1Hh#HHEdH+%( O HH [A\A]A^A_] D f D HHHL A^HDž |fHHHL(A HDž HDž Z +nD HHH 1<dfmD HHHF 1g<1fHHHL A^1HDž HDž 2 U D UHATSHdH%( HE1H Ht&E1ff. fHCJ<I6D;#rStE1HCJ<I6D;crCt)E1ff. @ HC J<If6D;crHEdH+%( u2HH[A\]f. HEdH+%( u H[A\]c UHAUATSHdH%( HE؋GtZH_ L, - L+Hu HL9tL#, L+Htи HUdH+%( uH[A\A]]1 UHAWAVAUATSH(H}dH%( HE1H HHdIŋC HE HEHMH@ H<91HH"HAi~uDLE1AAHDm"HAiA9}EDLD8tH L 1HUdH+%( uAH([A\A]A^A_] D Hp HUHEHE;B<LR f D UHAWAVAUATSHdH%( HE14AX;H IEÿ HpIIH( XIH H@(IFLuqIF EtxA1ۉL tLtSE1A9uL EuCHEdH+%( u_HL[A\A]A^A_]f. IFL L8 LE1HL8p H 01jh UHHdH%( HEH q HtHUdH+%( u;f. dHq HuH7p Hb= 101j1Fff. UHAUATSHdL,%( LmIt Me1 LI X2A;] rHEdH+%( uHL[A\A]]zu D UHAWAVAUATSH H $ H H $ H dH%( HE1HHDžx HDž /h HH}< H16H5 HqH HH IHx WH Hx HS'Ht HxH\HPHQ HeljLHHH0IH ? LxHDžd HXL@L8ff. dHP> HDž HDž AG`fAؾ HXHH 1Hd5HH5 pHH HLHhLff. fHٺ LLUH L: L%HtHh1LHH5: _ HMemTotalH9D HMemFree:H9U I jI _HgeHX D`HH 1HK4HH5 loHH LH LTLHE L %H HIHI dd9LL@L8HxLHPHEdH+%( HĨ L[A\A]A^A_] f:HIGf. HIG M'. L@L8LLCHLpE1$HDžP E1L@L8 E1L@L8ff. UHAUATE1SH_HdL,%( LmIt!fHA[-H{HN-E;e rHEdH+%( uHL[A\A]]pk ff. UHAWAVAUATSH8dH%( HE1W' HcHH,HEH LhE11L= H;HE HE IE H LH aIH HuH}H QH~dH} <"Ht LAIHEIEHd\HHhHEdH+%( uLHEH8[A\A]A^A_]LHEMcIJ|0+H}H}7HE f. f. @ UHAUATSH H $ H H $ H(HZk dH %( H]HLL LIL Hb L01L1˃Ãt$HEdH+%( uDH( [A\A]] D HA2p L H5 H81f D ff. UHAWAVAUATSH H $ HxdL,%( LmIHHVj HLHp} H1ɺ HH5x lI1N L%{cq f I9ukI$@Lk, L HHuHpI9 H3cq @HEdH+%( lHx [A\A]A^A_] @ HL)LHxHH L L M<$M9t<f. Kt7>/u~HE111Lgu3AGM?M9uLFHxJH- @ M?M9uf D HCHxDžl UHAUATSHdH%( HE1t#1HUdH+%( ueH[A\A]] HHxIdSIHt<@ HxIUHHaq H aq L%aq I $ID$L `ff. UHAVAUATSH H $ H H $ H@Hg dL4%( LuILLJ MF LLH L1|,E1LHHDž Ax0HIFHEdH+%( u-H@ [A\A]A^] @ H T @ UHSH H $ H dH%( HUHHH`t HUdH+%( u-H]fH`H1jx1H`prgcf D UHAUATI0 SHdL,%( LmA&&Ht}@, LH[HC HtKEu-C(HEdH+%( uKHH[A\A]]f LXC(uH{ %H ff. @ 1 UHSHdH%( HE1Ht(W,H J9rK,9t uHEdH+%( u=H]fu{(xH{ >%HEdH+%( u HH]kff D UHHdH%( HE1Ht W, O,9t BJvHEdH+%( uH UHAVAUATSHH dL4%( LuIH9t*IfLX MtI|$ LEt3HI9uHEdH+%( uEHL [A\A]A^]3 LHtHUdH+%( u H[A\A]A^]Rf UHAUATISHH dL,%( LmIH9t @ HX t&HI9uHEdH+%( u(H[A\A]] @ LHX HL9u f UHAWAVAUATSH(HGHdH %( H]HL8 HHEM;?{ ff. , H#IH HH9 H)H IH HL9H II9txH *p ;w D HI9tU9uHX ALD+MtI^^f D H9*p @ HEH9tGH\ HILHUdH+%( uvH([A\A]A^A_] D H)p 8DoD(At1I7I9tHX H6I9tHX Q,Bzwy,9t؉LvH")p " H= HhLff. UHAWAVAUATSH wOH`HPHxdH%( HE1 HEHIHl Hc H`H}H.HxC H o)EoG)EoG )E$bHEHXHPH5+ H# H- HH Zq L-Yq I9. HH]HhA} HhI|?/uHwEHH HEL L9tqLHE1MLIH HX GHXI$X M9 LL(tLL)Mm L9muLHHTGHe'p Hx t!HXHxHLB H`L0-AF Mm HEI9HH`H; a H='p E1 J D LLusLL:)Mm L9mILMIHH]AH}LHX>*H=7Xq H9t fHHGHBHH;H9uHEdH+%( N HĘ D[A\A]A^A_]HILhL<H Wq , LSHHIIDI9 L)LRIH L3I9u4 @ M6I9t(I~Ld?uLHMtiMe D L`HxHEHHUHIk @ HxHLH Wq I LL5Wq IFL0MuL-Vq LhLI9 @H H9u1 D HH9tx/u x HH H9u >HH / @ fPHVq HHVq HPHHEHHX8^HD$p HP H ( H81 H$p H=' AHc" H#p H=߉ AHbLhgLLhSff. @ UHAWIAVIAUM ATL` SLH(dH %( H]HM Mu f D IFH IIFI9tvL9rIFHuIFLuHE0 FIH HIF H| fM~LLH AFIF(HEIHEL0IjL"HEdH+%( uAH(L[A\A]A^A_]IFLuHEjHE LmYLFE1<ff. UHHdH%( HEH @ HtHPH9tH9s H@HuHUdH+%( u H@ D UHAUL` ATSHLHdL$%( LeIMH f D HtHCI9tL9s5H[HuL 1HEdH+%( uHH[A\A]] H[=ff. f UHAVL` AUATSHdL,%( LmIL>I Ht<M ff. LLHHjaHAI HuHEdH+%( uHL[A\A]A^] ff. UHAWAVAUATSH H $ HhHX HdH %( H]HHt,HEdH+%( Hh [A\A]A^A_] H(1ɺ HH5HK xL5Qq H Qq I9tHHHH HIvHHL$Hw A<$ Dž LDE1|2 HLL8Mu f IGH IM9ot|rIGHuIGHx0 BHHptPLLpI@ H H fMhLM8HI@(HxA@L NfM6I9M6I9Zf D IIFLHBHjL3I9u1 D IGHxD HIL8MHxL j UHHHO HWdH%( HEHH HGH t0HG H , HG &f D H , HG G, H) H / HG HG uZh H fH H G,tyHG ! H / HG tG/ ff. HUdH+%( H 1Ҁ/ HWu @ HG / HG uf, u*Hb 1ɀ/ HOlw G, Hu/ XH MG/ A6f D G, H f G, Hf , !H / , o_ Ht[H t / HG t6| @ / tG/ t @ 11bfVf D / t, tG/ 11X UHAWAVAUATSHX dL$%( LeLgG(Mt@LLH LMLLLfHHt1@C(1HUdH+%( uhHX [A\A]A^A_] LH@HHǸ: uM LL$HHu ff. f UIIHHdH4%( HuH΅yh' wjHHo ' H v%H]Q L11HUdH+%( u7ÐMIIȺ LH1g͐HLu뿸W UHAWAVA AUIATISHH(UdL<%( L}L?Mu=f D HHCHHt'ILLAT$tXHE1HCHHuـ} tcLLAT$ IHtPfL8@HEtID$LLMJ`AD$HEdH+%( uH(L[A\A]A^A_] E1ff D UHAWAVAUIATSHL'dL4%( LuIM HA HHCHHt*ILLAU HE1HCHHuLLAU HHt{fL @HEuQLi_AE1HUdH+%( uQH[A\A]A^A_]LW HHt-fH GI} I}f. 맸Mff. f UHATSHHdL$%( LeIH;wt8HLWkHEdH+%( u(HC(HLH[A\]f D LXBHCff. f UHHdH%( HE1HEdH+%( u1>f UHHdH%( HE1HEdH+%( u ɺ Ff D UHHdH%( HE1HtG fHEdH+%( uff. UHAUATSHdH %( H]H_Ht'If D HI5ALLHBHuHEdH+%( u H[A\A]] UHSHdH%( HE1Ht'HwHEdH+%( u%HH]; HEdH+%( uH] ff. UHSHHdH%( HE1Ht;^f D [@HHt uHEdH+%( uH]H 1 U HHdH%( HEHGH9rH9HEdH+%( uɉ\ff. U( HSHdH %( H]H7Ht HXH@ HUdH+%( uH]ff. UHHdH%( HE1HEdH+%( u H UHHdH%( HE1HEdH+%( u@{ff. UHHdH%( HE1HEdH+%( uP@;ff. UHHdH%( HE1HtHEdH+%( u [Z HEdH+%( u1 UHHdH%( HE1HtHEdH+%( u HEdH+%( u1 UHHdH%( HE1HtHEdH+%( u HEdH+%( uBf UHAUATSHdL,%( LmI0 5H HHLH~2o fHnHflHC(CMtULe H0u/HEЀ8 Lht/L L 8HHE <,tɄtH/1 HEdH+%( uHH[A\A]]^ff. UHHdH%( HE1HEdH+%( u 2f. UHSHH dH%( HE1HtKH :/t HUdH+%( u4H]f. HH6U C 1 UHATSHdL$%( LeL MtxA<$ Hu6A|$0 u@A|$` uJHEdH+%( ugHH [A\] I|$A|$0 tI|$2A|$` tI|$b HEdH+%( u H[A\] UHAWIAVAUATSH L dH %( H]HM H;L0H5tL0Dž8 L[ 8 uWM H5T L|IMtZ @ HEdH+%( H L[A\A]A^A_] Hsq M HL"IMuHMq HH;LH5L0Dž8 H LIHYA<$ A|$ H5z H=b ?GIH+ H@ff. L H H 1H(LHL$H5* Dž$6uHc$xHHߺ 7uLkH(L0I)LHH Ml$LDžx%LHމ2CI9- Hf fA$ M H5D LuIHHo LHHKH6LHHLLI H=$o I IHE1t @ Ml$HIHSHLHH1LPL$ @ LH9 fA$(H9 p H= H(KW UH5nn HATA SHdH %( H]H H%tH5Ď H%u!HEdH+%( u)HD[A\]f D H5 H%At @ UHAUATA SHdL,%( LmAHt]( DDHHt.HC DDHt HC(f D H{Hff. @ 1HEdH+%( uHH[A\A]]ff. UHSHdH%( HE1Ht7HHAH{8HEdH+%( u(HH]^f D HEdH+%( uH]>ff. UHSHdH %( H]HHHEdH+%( uH{H]d UHHdH%( HE1HEdH+%( u H ; @ UHAUATSHdH %( H]H3IH LA6DH Ht 1HUdH+%( uH[A\A]]ø"f UHSHdH %( H]HH Hǃ HEdH+%( uH]f. f. f. f. f. UHHdH%( HEHUdH+%( uoff. @ UHHdH%( HEHH9HUdH+%( u( UHH XdH%( HE1Hx`fH*gf(\f(^X\OYXGGH9wsHwH;w sHw HEdH+%( u"fHHfHH H*Xmff. f UHHGdH%( HE1HEdH+%( u*f. UfHH< dH%( HE1f/v HEdH+%( u9f(f. f(\ G^^f.wf(QHEdH+%( u ff. f UfHHdH%( HE1f.zuHEdH+%( u f( @ Y f(^)f UHAWAVLcAUMATISHdH %( H]H H9t;ff. fL MtEo(0 L"IG0Ht(HI9u1HUdH+%( uH[A\A]A^A_]øf D UHAUATSHH dL,%( LmIH9tZ L MtI|$0I|$8H H\ H Hǃ HI9uHEdH+%( u H[A\A]]ff. UHAWAVAUE1ATSHdL4%( LuIHtH HtD(M&M9 MctJ] @ fo Hx0fH@ HHu|L M$$M9o @ HH I$ EtDh(L0 HC0HHK fo HC f[HcC(1H@HelDh(L0 HC0HH fo-7 HC f#kHcC(1H@HL9 L-H0I$ b߉iH I$ M$$M9tW@ HHt}I$ E<fo= Hx0fH@ 0xHcK 1HUdH+%( u6H[A\A]A^A_]IDŽ$ H @ L'|ff. UHATSHH dL$%( LeIH9tWf H fo fHx0H@ HHtHc@(1H@HHz.HI9uHEdH+%( u H[A\] D UHATSHH dL$%( LeIH9t4f H Hx0Ht8Hc@(1H@H HI9uHEdH+%( uH[A\] D HI9uIf UHATSHH dL$%( LeIH9t"f H Ht,3HL9uHEdH+%( uH[A\] HI9uf UHAWAVAUATSHdL<%( L}L?L9 Iff. @ I HcE1f D E1ff. fL*H-D9 I H@L;hs~L;p sxHHHIIHT(H4I H@L;hp\IML;p b\HPL(oIHLI@(oFHP(@8HF HB ^f D 1 @ II93M?M9HEdH+%( uH[A\A]A^A_]d @ UHAVAUATSHdH%( HE1?ucL.HL9tXI fH,Mm HL9t9M L萺f/ IF0r\ Mm H,HL1 L9uHEdH+%( u H[A\A]A^] D UHAWAVAUIATSH u L dL<%( L}I I LLc(H+E HE E1HxL`LXMK@LpE1HHh H I$ DLuLLA HEx( 1H]LLuIIH H}Lr HMKvA$ IHH]HA0@(u3I$ :t&A} k H{ tH{ Y f x, uH@ f@, IL9x I$ EHXL;{ HpH;C HCHHIHD(HI$ LHEI$ HE'DHHEA$u E H} H} H{ H{ }9E }0Er HH\ UHcEHuH}H H H1ZHu H}E1E11ɺ D A$t Au1HBHEA} H@0HHu A}( lHhIHHHS@(HPHSHPL9xKLpH`II9 DE f D HH q A$t QUHDLq; @ 1#x, oof HSHPf. HEII$D9p(If1H5'H=HEH= I$ MLXA} t-1HUdH+%( He[A\A]A^A_]f I\$0LH3>Ho ~LsLLcH落HI}0MAVHH: Iؾ 1XZv LBHto He` 101)Eff. UHAWAVAUATSH(H}dH%( HE1 L>If D HEx M?M9~ A uAy tI M7L9u f D M6L9tL舼LI}LHuAH fA.H zuIX I9X uIP IP uAAF IWHp H jIFH D I I M=I I HA0H HcI(;J($ ~MH4IHR0HHff. ff. @ ooH0f HJHHH0H9uAƆ HEdH+%( H([A\A]A^A_]f D 'IFHr1H8a @ Hz0 +AƆ @ L8I M7L9 IIF HuHo H] 101&f D UHAWAVAUATSH dH%( HE1 L>L9 H@HH(HEH Av z I I 1HvHDž Dž HpHI t#9 HHH@0|- H(1E1E1o@`1I EI )poPH )Ef)0 H H(1҉Lh0o@`HH)EoPE)Et$KdHIAoM fԍ0Mu)0I At$I$I F"D9]I 1L E1E1 H H(1҉L`0o@`HH)EoPE)E9t"H Mfo0AD$-ID$A $I AI0D\I ~!A9] I *H0 M?L9hHEdH+%( uH [A\A]A^A_]f UHAVAUATSH oFH^(dL$%( LeIH Hv)EH Et$HI HDG I IcL$HHRH;BsSH;J sMHJfoMHHD(H1HZ Aƅ HUdH+%( H [A\A]A^]f D L`AL$ED$1IHro HY 01"HTo HY 101"LAL$H 1IH o 01o"H UHY HAUATI SHHHODOdH%( HE1DGLHKLK(LLC Lc 1HY HLHUdH+%( u H[A\A]] UHL; HHHxdH<%( H}HtL HHH 1%HHUdH+%( uMff. f UH. HAUATH`SHHH dH%( HE1HH`I H1H- ` HLcH} 1h HLcHo 1dM HߋLcH_ 1M?HLHUdH+%( uHĈ [A\A]]X UHAVIAUATISHHdL,%( LmA4H¸ HC01A|$ uH( H9( C8HC A|$ C8tHC( A|$ t C8σ C8A|$ t C8σC8AF,H; t{t7A~/ t7HEdH+%( H HH[A\A]A^]bfI~ tHHHEdH+%( ugHDH[A\A]A^] K8I~ vI> lI~ a]I~ uAF4QK9H UHAWfI~AVAUATISHHH=Ao L1dL,%( LmLiff.z&u$HEdH+%( udfLB 1:f D HEdH+%( u@L" H ) A$H YfIn^HLHL[1A\A]A^A_]ff. UIHAWAVAUATSHHLw8L@dL,%( LmII>H HcL}I1HRL]HLmHE W 1 d Ha HEH&o Hx(YEI<A EH HH? H}EDH;I<H h A߅mH E1Mt:I$ Ht-I$h Hh H9tHULB8MI;h HMHH0 t=HH fH*E1EI<EA @ E1H H=o HEf H H=o HEf HfHH H*XjfM$ I I9(H;h t[H I9uHME1HH0f. L}LmMu` HEdH+%( HH[A\A]A^A_] @ L; uH A D DLmL}MtI? u II? tLLtx1̃u(Ho H 1011G肮H 1HHo 01ff. UHSHGdH %( H]H HCHt¸ L CT \HCHW C" *HCH5 C HCH C HCH C HCHt¸ P Cu\dHCHt¸ Cu,4HCHt¸ C HCHt¸ { HCHt¸ {z HCHt¸ W {G hHCHt¸ $ { 5HCHt¸ { HCH= ; { HCH= {uHCH= u`{uTuHCH= u5{u)JHCH= t= ¸ u1 @ HUdH+%( H] H{v1 D D D D D = = = = ^ff. UHAWIAVAUATSH(G8udH %( H]ȉD$ DDED@DEDG:DEDDHI L6L9 IŃu 9 I; t!M6I9 M9tI AV8ǃEljǃ@EljǃAF:EljǃHA9uIX I9X uL9uL1I9 I M6I9j D fHEdH+%( X H([A\A]A^A_]f. I9 uAAV8ǃEljǃ@EljǃAF:EljǃHA9tfM6L9zM9tI LceI KdHHB0H HxkfH*AYH .f. IX I9X uLhuHLceI KdHHB0H Hx5fH*HfHH H*XI )HfHH H*X蜹ff. UHATSHHֺ H EdL$%( LeI MfҺ f.Etnf.Et`^H / Y f/ U f(vwHEdH+%( I4$ID$H HL [H A\] HEdH+%( u]I4$ID$H Hf[L A\11] @ f/ ش H tf/ ˴ HB. H HFU_ff. @ UHAWAVIAUATAԺ SHDHH8HAEL9dL,%( LmIHEHߺ DEHߺ DEUM_ff.fH~ fL 11HELLffHnۺ f.Etjef.EtWLLAUHEdH+%( uzHEfHn^EH8[LA\LA]L A^1A_H u ]f. HEdH+%( u-H8[A\A]A^A_]fEL- H 5 ^0϶ff. @ UHATIHSֺ H EdH %( H]H:MfҺ f.EtNf.Et@HEdH+%( uc^H3HCH [LL * A\H $ 1]f( D HEdH+%( u#H3HCH L[fA\1L) 1]f UHATSHHֺ H EdL$%( LeIZMfҺ f.Etnf.Et`^HZ+ Y E f/ f(vwHEdH+%( I4$ID$H HL [H n A\] HEdH+%( u]I4$ID$H Hf[Ll A\11] @ f/ @ HX tf/ K H* HF HFU说ff. @ UHATSHHֺ H EdL$%( LeIMfҺ f.Etnf.Et`^H* Y f/ u f(vwHEdH+%( I4$ID$H HL [H . A\] HEdH+%( u]I4$ID$H Hf[LA A\11] @ f/ H tf/ ӭ HR) H HFUoff. @ UHATSHHֺ H EdL$%( LeIMfҺ f.Etnf.Et`^H( Y Ŭ f/ 5 f(vwHEdH+%( I4$ID$H HL\ [H A\] HEdH+%( u]I4$ID$H Hf[L A\11] @ f/ H؇ tf/ H( H HFU/ff. @ UHATSHHֺ H EdL$%( LeIMfҺ f.Etnf.Et`^H' Y f/ f(vwHEdH+%( I4$ID$H HL7 [H A\] HEdH+%( u]I4$ID$H Hf[L A\11] @ f/ H tf/ S H& H HFUff. @ UHATSHHֺ H EdL$%( LeIZMfҺ f.Etnf.Et`^HZ& Y E f/ f(vwHEdH+%( I4$ID$H HL [H n A\] HEdH+%( u]I4$ID$H Hf[L A\11] @ f/ ` HX tf/ H% HF HFU误ff. @ UHATSHHֺ H EdL$%( LeIMfҺ f.Etnf.Et`^H% Y f/ u f(vwHEdH+%( I4$ID$H HL [H . A\] HEdH+%( u]I4$ID$H Hf[L A\11] @ f/ H tf/ Ө HR$ H HFUoff. @ UHATSHHֺ H EdL$%( LeIMfҺ f.Etnf.Et`^H# Y ŧ f/ 5 f(vwHEdH+%( I4$ID$H HL [H A\] HEdH+%( u]I4$ID$H Hf[L A\11] @ f/ H tf/ H# H HFU/ff. @ UHATSHHֺ H EdL$%( LeIMfҺ f.Etnf.Et`^H" Y f/ f(vwHEdH+%( I4$ID$H HL [H A\] HEdH+%( u]I4$ID$H Hf[LV A\11] @ f/ H tf/ S H! H HFUff. @ UfHHdH%( HEHdo H@ @Hfo @@ @0@@HEdH+%( u}ff. f UHAUATISHdL,%( LmAHE HtZ1DHLH7xIT$H}Hru>H膴EHEdH+%( u,H[A\A]] 0 f D HE UHAWMAVIAUATSH PI1H0H}H(dL$%( LeMH H HM HQ(I9 HDž Mƅ HH MfHX r LXf11H@HHLHhM?H I95 A~ uNHX t?HIw0HHDHH H(P~H LAUIEMg8HHIGHXIGH8IG HIG(HAGHTIE H@HHI~ Ht щHCTPHLH0CAF(CHM$Mt!A} H( HX H8H`HuHHtjHpHuWpf.zIf(fT = L% f. w,f/ s"ff.z L% tL% HHtHX HX `X LXH H@HHLL H0H HXtf D 蛮H=$q AHtTHpuDA~%H0H=q L LI H 1LAU @ A HH}@ 1H HXHXHH LAUHHsq H0H HVq f 1HUdH+%( H [A\A]A^A_]f H0L HH}M1H| @ HXHXLf D HhHxx`Yh`H8? 蘾HxH}H LXDTH 1@ HX\HX`IH f D Lx(+ H A} HXH0H HXuLXHz @ 1HXHXs Lj UHAWIAVAUAATISHHHHA dL4%( LuME HEHHEtsHHHMDMAVE1LH MXZuHuHEfE111HHEdH+%( He[A\A]A^A_]f. HEH,ao MHHt Lf(DLHZ D DLMMf(ff.zuE f. Y 1H}E HE/secfuf(^ՊDMH}A t/ 1H}L EEH}IHuHE1H 9 H4 @ UHHdL%( LEIA tHHtHUdH+%( u H1L3HƢf D UHHdH%( HE1FHEdH+%( u苢ff. UHHdH%( HE1HEdH+%( uOff. @ UH HAUATSHHL. dL$%( LeML1 LHd L觜{ t!HEdH+%( u8H[A\A]] HEdH+%( uHL} [A\A]]j蕡 D UHAVAUATSHPL&dH %( H]HM H Lu @ MLIȸ @ rLI PЀ v<. LPHJЀ v.t LHHKXMPHy LI1苛XZHEdH+%( uRHe[A\A]A^] D HKXHEdH+%( u-HeLIȾ [Ho A\1A]A^]0Lmc UHATSHHdL$%( LeA{ t'E HEdH+%( H[A\]f{ tBEtHEdH+%( HKXH{0HH} [ A\ ]錚 @ fɺ f.EtAyHEdH+%( uAH{0H4 HEdH+%( u"H{0H H [A\]Rf UHAVIAUATSHH LnHdL$%( LeMtBI H H I9 t$HEdH+%( He[A\A]A^] @ HCPI9X uMtH5 LHuH5 LӰHu H5I LtVA~ uA~ H;t%MFXLHm 1 Zf D ANDMHQt 1 5LLH LATILp 1 M5XZhf UHSHdH%( HE1Ht_HH0I1H ]HUdH+%( u[H{0H]1 L )HN 1$ @ HEdH+%( u HH]1 H=/ S.ff. UfHAVAUHEATISH H0A|$ dL,%( LmIEEEEEfh~[o HPH4fHnH}flƅpXuwA|$ ; AL$8 A|$ A$HgZo H ;@tGff. It$0@, {H@uff. @ A|$ 4 I$` tIE HX HEI] M$ I9u)^ H; t'HI9tFff. @ A|$ uA$uHHPM1fLH]HI9uA|$ HEdH+%( HĐ [A\A]A^]f. H A$Hr Ho u I$` tI|$01L Hٜ 豕A|$ D L It$0 ?IL$XHn 1d! I|$XHJ;@.Yt @ UHHAWAVAUATISH oEx fA~oE D$(D,0f~4dH%( HUȋU0 x t+8 Lh0LxX DL Hp OcM>A D D(Lx0A L Hp EOcM>AfL@APAPL L繀 1 _AXHMcA MSHp LB H 1XZHEdH+%( He[A\A]A^A_] @ 8 Lh0wDL o OcM>AfHEdH+%( L}AMH HeL 1[A\A]A^A_]Yf A$v u x MHEdH+%( 5 Aй LH He1[A\A]A^A_] @ H 1WL@AQLAɹ APL =H @ VL@AAPLO a I$ D~I$ D^IHEdH+%( m ]HeLA [ A\ A]H2 A^1A_]&f D L@AL L1 vHL@AAPL @ DL@L f A$v t x HEdH+%( HeML[H A\ A]1A^A_]W HEdH+%( R L}AMH HEdH+%( " L}ML ]HeHm 1[A\A]A^A_]ߐ HEdH+%( L} DH ]L}HeL 1[A\A]A^A_]鏐 HEdH+%( }H L1L}( ] L}He[A\A]A^A_]C HEdH+%( B L} AH_ ]L}g I$ D|I$ DޫHHEdH+%( HeMAL[Hn A\ A]1A^A_]鮏f D HEdH+%( AH' Lo A$v u x R mHEdH+%( U He؉L [HF A\1A]A^A_]f. HEdH+%( AH' if D HEdH+%( AH& HeL 1[A\A]A^A_]鮎f D HEdH+%( ]DHD& HeL 1[A\A]A^A_]g HEdH+%( b } L1]HeH% [A\A]A^A_]# HEdH+%( " ]AHP% w I$ DyI$ DƩHHEdH+%( HeAL [H A\1A]A^A_]降HEdH+%( L}HeAL[H A\ A]1A^A_][VH@Aɺ AP L' 1 H IL Hn 1Y^#HEdH+%( uAH &f D U HATIH= SHHdH %( H]H H{HtH3蔖oC H0S LHsH$oC0D$C@D$ 7H0HEdH+%( u He[A\]膑f D UHHHx dH<%( H}Ht HEdH+%( fx trtLP0HHXH9 H1HHHH+ fH*HEdH+%( IIɾ H L 鏋 H9h_HUdH+%( Q H* fH*Ya H fH*^Hx0 HF ɸ L@0H9tWH1HHHHxqfH*HEdH+%( HHR# LǸ 鸊 f D HfHH H*XfHfHH H*Xzfp HfHH H*XfHfHH H*XMff. f UHAUI ATSHdH %( H]HH6H{HtH3输oC H0S LHsH$oC0D$C@D$ aCH0~ E1 H3I}XApD9cHEdH+%( u He[A\A]]苎ff. UHAVAUIATSHFdH %( H]HH IE1~ @ H3I}XAD9cIu0LޒH3 H{HtH3oC H0S LHsH$oC0D$C@D$ cCH0~ E1 D H3I}XApD;c|HEdH+%( u8He[A\A]A^]f D E1~H3I}XA0CA9|^ff. UHAWAVAUATSH(EFdL<%( L}L>F MU IHI ILÄuH L1詇ELAM LL eAHEdH+%( > % IH D)HeL 1[A\A]A^A_]@H}I L<I|$LMHt I4$LMAoD$ H0AT$ LIt$H$AoD$0D$AD$@D$ LMLMH0AtxI $1 H= f L 莆Af D HEdH+%( u@L3 & H f I $ H=c ilff. UHAWAVAUATSHh xdH%( HE1Mt IILIH5Y LAHt,HEdH+%( 5 He[A\A]A^A_]f. H5 HHu H5w HM} MH+ xHLD@ H߾@ MHXH PЀ Hv<.u*ff. rH~@ v@.t MFXHY 1 L̄AE fI}HwH HSIL\ 1 XZ迉ff. @ UHAWAVAUATSH8 dH%( HE1Mt#IILIH5 HM莛Ht)HEdH+%( A He[A\A]A^A_] H5 LQHuIE LEvDH5 HY LDPH9DBMtwLHEtHI HDLHLLǾ LpD 1LHH~^ *AE L% HIDI}HuHH AWILZ 1 HS XLZ UHAWAVAUATSHh xdH%( HE1Mt ILH5 ILHt'HEdH+%( o He[A\A]A^A_] D H5i H詙Huź H5 HM,$ MH xLLD @ L@ MXL I PЀ Lv <.u1ff. ff. D JHq@ v.t ; A9 A|$ H tH ' IH L1 EAD$ f. I|$HLsH LSIL Y 1LtXZ( UHAVIAUIATSHH0 dL$%( LeAN I}Ht Hs0蜊M6H IcHHH0I HP$oHo@HIHHF0UL@()M)ET$ $D$ Hܯo IEPH0H tU{ L@ H{0 { tmHEdH+%( HKXHeHT 1[ A\A]A^] H` uHEdH+%( He[A\A]A^]f D HEdH+%( He 1[H A\A]A^]aHw0{ b D IX tUH{ H{0L HEdH+%( u7HeLHB 1[ A\A]A^]~f D H` u @ UHATSHdH%( HE1HtyIH0HHѾ H ~H H= H{HtH3eoC H0S LHsH$oC0D$C@D$ H0HEdH+%( u He[A\]W UHAWIAVIAUATSHH Hh D\GHPdL$%( LeLfHL` L-XLtL-vLOI$X t AVH Hh I$ : H5LmLEHuLuE \HMLLHM 觏 f L LL-I HG Hh 9 I$ 8( LmLELMLuE A$ F AoF H0LLAV M E1$AoF0D$AF@D$ $HEH0ALH@HpHHLMDžp It5ff. fH`H mP LHh HLHMLAV\L@HHH`eIXZMX A IM Džp H= I}Ht Iu VH0AU IuHLAoE $AoE0D$AE@D$ H0AL)L iLL-HLL-uHh H I$ : H5vLmHuHELuE r D L Q A$ * A$ LmLELMLuE fL 11LLAA u@ALt%H`H 莝P1LHh1HLHEdH+%( m He[A\A]A^A_]f D HEdH+%( E HeL{ L1[LA\LfA]LA^A_] @ HL- D H{I}Hf I$ L8L@H0莅L@L8tkH0HH9uZf. H H9tH tA LmLELMLuE yA$ jƅ@ v A$ AGP A I$ HH9p AL$ f 9P H H9L Ptu߉ ƅ@AF@AoN LLAoF0H0AV E)p)ED$ $D$H0A A$ ;x %+x A$H f(f(fTf. A Iw0L H LEA H8 f.z H tH @ HH8@wM$P Mt AO@H8HX 1 wLi H8IHE 1vHo I$X u I` tAL HtL@ A I0} A R IOXHRK 1vALt"I$ P LBHh HL @ A A$ MfH AGT LmLELMLuE @ f D f.IO0MGXH8z HY tHI H 0 H HEȀ@ HH8L L0zuL0I$P HtH8HJ 1LuL$hH8H5EH,f%?t fUH*f(fT\f(fV= I0H Y HD HEȀ@ H84 H HV tI$P HtH8Hh 1tLWgH8 HQ H1Ztj D H 18t LHf 1t D H8HH 1L0sL0p H8 H O 1 s| @ f.z HO 5HN )f HM 1}sx UHAWAVAUATASH HG0L dL,%( LmIH HXIcL<@HIILz0oHI)po@HhO)E@$`EAM AE0 AE@AG(IuHAE t'HEdH+%( HĨ [A\A]A^A_]fIH H؍ M IWI HMLPLHHauLPM HhHa fɀ` H*q A~ I}H HXL`h{hL`M fI*HHLLEYH LHX 覽A~ } H HHHH輁HHP dHPHHHnH / IH" H 1H}HE dA ƃ PHHfɃH ` H*XM fI*HHELLYH Lh A>F h Hh Hx Hx01LP謅1HuL@D<IAL0A f D Hh ADHx0iAHh Hx0A9LLDA HpLΘtLPL@D<L0Hf A~ A~ A~ AF8zMFXHX1H M HC L`h ohL`2 LAfHL H*XQf H(H H}H IHSe H 1#H cHEH HX{ L`hhL`h4 @ LAfHL H*XZA~( IIH 1zR0s UHAVAUATSHdH%( HEH Ht3 ~-III1 LLL0I$ ;|HEdH+%( u H[A\A]A^]r UfIHAWEAVAUIATISHH F~ dL4%( LuMV8XHF0ƅH( k Hڛo LxH8A} Lx Jq upA} u<A} u5IE0AM8Hx0 AE H H HcH>1A} t+ LLLxl>Jq Lx1҃tPA} "Jq AE H}H HcH>X M2M9tzHMMH`f D Av I Ht48~.L`1 LLL0I ;|M6M9uM I}`GVAu8I]0 H I#EI A} r A}L^@j x9 I}`葎^!j f/1j `A o A} EDH H` x L% jx`wA} Hپ LAUP} AETS I]0H蓄HEdH+%( y He[A\A]A^A_]ÐHH MH@H: I` I HzI lI I9`LHhL= MLxHhHX H90 D H0E 1A} ƅtHxLLM&M9t$f D H0I9$X M$$M9uA} t@A} IM0t( 3 Hο} Hp HpHο I ;YHhH HhI9JA} q I` f M2LMM9 ff. H0IX H9trAMHtF A} I]0t H} VH IIX AMH0ƅt1LLL+I Ht-DE~%1 D LLLpI ;|M6M96H0 8A} -A} I]0t H} 蘳H 苳H@~ LAHH ~ Lx] LNXHZ @ 1 LxBH=S w Eq LxSA} A} tUA} }A} 9fɺ f.E I}0 H fA} fW1} f f f(fTf.v3H,ff(-ne fUH*fTXfVf(L,AA} *xDH}H@ @ Dp} DpO H IH< tD1L HH DpeAMLDp DTDXff. I JHM fH*^Sd Xf(\xH H߸ Aph ehY d p^,Hc HigfffH!)AADHE1Af H# A述E9uH I詰E9}L DTDXLC DH1H DpZdDp\H@HLLLL@_Iz1E1LxyLxD`Lxf. I|$9` M,$DXM9u @ Mm M9- LM THzetHxH H$E1"ff. f. AH$A9t9uIcH@HHh1HDpL(菳oEDp) o ) LHhIF0HHHPH H fH*AYH a LE1HxMm M9Eu>Hxx t1x HX0t H} `H S``I|$w3HI E1LM D A} ƅtDLLLI I9t"f HLDL?HI9uA} t2A} I]0t H} 苭H ~I AD; jHT @ 1Lx+LxNH$o HLpLO 4H= D H; Hx 1`LpXZA} rHH EM@LpPHx1L H `A^A_>q LpCfHxLLM$$M9f. HxƅL SDLLDp<Dp2HƃfHH H*X<f LHp7Hp H-I A 8 AGTIG0H@HHW I 1HDžx DE LXAHhLHLp IcHE1Hҋt$1舆DxE HhLcxLpKM$ @ I$M9toHLtHpAH D;(|LXHhLHLpST H@ 芪 D H`HXDHpHhKfoH@fo@P$xx?HfHH H*XHܗ H߸ ]A} L% *ffHٺ I*Ep p\ L% I*UhL^XfI~fI* ^fI*MxXfI~fInHH] ?]fInǾ HHP !]HٺV H= cvHٺ H=5 8XH xΨxlHDžh E1aE1Hff. DHLLI AD;(|Hƿ LpV Hx H= IL$ LpH Hw Hx 1[LpLx' LpLAMLLp~ H L1[LpHx H=i LpA} Lp* g9q +H0ƅLLxA} ƅt"LH1LLxBLxM"M9WI HuWI$I9>H I9u1H @ 1ƇLxHٺ H= OLMfDE~&1f D LLLI ;|M$$M9uHH LpA PL} H 7HH LpHxPA H jL7 HJ P1YLpH A} HxL 1 H LpYLpA|$, IL$H LpH \Hٺ H=/ 1Hٺ H= H@. H= irHx H= Lp@LpHٺ H= !ID$I $Ht6HtLpHC E1LpHH4 eHuI|$ uLpM IHx1H 8XALp4AGHpMfLMtL= I $HxL1 IWM9uIHp]H }? H f. D UHAWAVAUATSHH~+o dH%( HEHM HE fHnH flHE)E芆H H1LmHlH߉EU H\II} Mu 耦IH>HH LHuHD=p HELpM* MDAL1mPDžy'Aul8 sMp E1 @ SHEMM/p * ALHH( 1PDžy8H߃8\f1HUdH+%( u#HH[A\A]A^A_]RH[ G[ UHAWAVAUATSHH~{o dH%( HEH HE fHnH flHE)EڄH H1LmHkH߉EeS HH[II} Mu ФI<HH LHuHD=p HELpM* MDAL1NDžy'Au輷8 sp E1 @ kQHEML* AH;M1kp bNDžy<gH߃8 fZf D 1HUdH+%( u#HH[A\A]A^A_]PH3Z Y UHAWAVAUATSHH~o dH%( HEH HE fHnH8 flHE)E*H H1LmH`iH߉EQ HYII} Mu I:HH LHauHD=7p HELpM* MDAL1 MDžy'Au 8 sp E1 @ OHEML* AH;M1p LDžy<践H߃8 Xf D 1HUdH+%( u#HH[A\A]A^A_]KOHX W UHAWAVAUATSHH~o dH%( HEH= HE fHnH flHE)EzH H1LmHgH߉EP HWII} Mu pI89HH LH豁uHD=p HELpM* MDAL1]KDžy'Au\8 s=p E1 @ NHEML* AH<M1 p KDžy<H߃8 Wf D 1HUdH+%( u#HH[A\A]A^A_]MHV 7V U HATSHhH dH%( HE1HE HDžd HDž` M HtU1HHfHA]N* E1DH`A1 JDžxL 1HUdH+%( u HĐ [A\]^Uff. U E1AHH dH%( HE1HpHpH* E Džt E _Iy#f8HUdH+%( u L T D UHAWAVAUATSHH~o dH%( HEH HE fHnHX flHE)EJ~H H1LmHdH߉EL HTII} Mu @I6HH LH~uHD=Wp HELpM* MDAL1-HDžy'Au,8 s p E1 @ JHEML* AH<M1ۅp GDžy<װH߃8 Sf D 1HUdH+%( u#HH[A\A]A^A_]kJHS S UHAWAVAUATSHH~;o dH%( HEH] HE fHnH flHE)E|H H1LmHbH߉E%K HSII} Mu 萜IX4HH LH|uHD=p HELpM* MDAL1}FDžy'Au|8 s]p E1 @ +IHEML* AH<M1+p "FDžy<'H߃8 &Rf D 1HUdH+%( u#HH[A\A]A^A_]HHQ WQf. f. UHAWAVIAUATSHH(FbHHu1dL$%( LeIԈE?ayAFBCL3AL96 fHuLL9A t E~ M6L9uL+I9 f. LIƋp LHI;\ L;L9uo M?L9\ LľI9uL跾I9tM9ttI I 1H9 ff. f H H HcH H9uH% u Ae9IE H IG(I F(IE(Mm L9 HExR u @N ;L#L9t D D LD%M$$L9uHEdH+%( H(H[A\A]A^A_]S AN;M6L9OtAe9IE Ae;N LHL8FM{~2L#L9jIL$(LHH94H;J("f D } :L#Nf UHATSHDgtH dH %( H]HA H AtDchH H Ch H HuH=r vruCChMA 9s/Huo {a 2 AAH 11ECh1HUdH+%( H[A\]ÐCh ~ @ HDH If. 9sH=uo A112H ~EChHuo HU 101ZcHto Hj 1017H~ 11%Lff. UHAVAUIATE1SHdL4%( LuI.H LHH;wAąuuLsMtI}" uvIHt 1H\ALE蓖I* DIA1L@Džya贩8 t/E1HLHEdH+%( u`HD[A\A]A^] D +* D1IAL1N@Džx#CA I}1[AMK UHATSHdL$%( LeLgH HH5uh H%t1 1HAD$t1HUdH+%( u_H[A\] HuH= o oHro 2uMH1 110EH 11뙸J UHAWIAVMAUIATISHH(DMdH%( HE1HH@ LDHtL1`HILEHM Hs-L聎t.S*H{Hs H)MkNHHtH+L7:M HWro 8 DE1H}LH @ Le ~lH Hbqo HHHL`z(tiIUIufHnfHnHJfl@IM1HUdH+%( u}H([A\A]A^A_] L/ #HPHLEE IUI]IMfHnfHnfl@H D E1<1111tI @ UHAWAVAUATMSHH HEHHHEHDHDdH%( HE1HDž0 Dž, MtLDkHHtH0kHHt H0E1E1E1R8HSL MI IcA@ LL9s LqLsх A uM$ LLW.H fo@INjB foPBD fo`BD fopBD 0foEBD @foEBD PfoEBD `foEBD p1MA @ ML IcLN,2HIu-HB HH@J<0HH +LDžC) L0M L6MtLjiHHtHViHEdH+%( H [A\A]A^A_] @ {$ &S u/SHs;1H HKHHC$ H8Dž< 8-GHHu&聣ML n C$ >nHML f D Hqmo LH + H 01覟 ; L0 LE1E1J5L{LHDž LMI"f IcAD@A G LL9s LrLsD"EE" A uM HDL<+H fo@HDB8foPBD8fo`BD8 fopBD80foEBD8@foEBD8PfoEBD8`foEBD8pM1A d H V L0f. {$ u:S / SHs;|H HSHHC LMMcHO|5 Iw *H H J<0LH{(LDžC9 L0MHko LH H 01KMtH0\H#I$L0E1E1LeH02HSHLLLIHDž IfIcAD@A LM9g: LaMgD)EE A uL HDL(H fo@DHfoPDfo`D fopD0foED@foEDPfoED`foEDp1LA D@A %ff. LLIIcHM4HIv(H HH J<8Hj&LDžC1 L0M|Hio L H H 01:HH0H,HHHEƾ HYHt H5v HU : HnYH# 1Hx1%HHHtH0d!HL0cDž f. A$ AW u-AWIwA? yH IOHIG @ A H8Dž< 8 AHH LILLHU n C$f D H8Dž< 8@HH LM n C$ @ L0IA9,H0 bDž f. >LILLH聜 'f D >XLM F Ic I IEL0IuH 0000HfLfnfofH J ffp fnfp f o@fDoHfoftftftfDofDdfDtfAfDofAhfE`fDofEefEofEafEifDofAfAfDofDefEafAifDofDdfAffofA`fAhfDofDefDofEafAifDofAffofefDafifAfH9foHQfsffofsff~fofsffofsffofsf~fofsffH94 MI)IpII! A~l fH~/9 ~5/9 HftHʃftfofofdftftffof`f`ffpNfofdfDofefDafafofAfpNffofefafafoff`fpNfpNf`foffofofefefafaffpNfofafafpNffffofs ff~fofs ff~ A 0 HJL9 AL0l f HJL9A 08 2 HJL9A 0& HJL9A 0 HJL9A 0 HJL9sAT0 ldAD"D DžL0HSbo HD 01薔Dž L0L0A90uAyxuML :HJL9E[H0\HCHS HAHC HH9u܀{$ S SHs;rHH HKHHS렀{$ ES SHs;UrHH HKHHSHAHC HH9u렃HJL9RHJL9=HJL9( H8Dž< 89HHu{J n HCHSC$q H8Dž< 89HHue n C$)fLLILH~> q D LM~>荕 D f1ɺ 1fo1L L'HDž0 DžE17LH'1H0f UfHAWAVAUIATISLH HEH HH(HEDHdL4%( LuM )PHDž@ HDžH Dž< HDžp )`M =q D q ED t]M鹀 1L@Lgl LԮA~ L3D H H3co x" H@E1R&HHF&HEdH+%( HeD[A\A]A^A_]ÐH5k xtHbo @ LHDž L H. MIEHHk HH{k HH HHbk H-XIH H,LH@@HIhI =q L t D A~ H5j ۔HAFL Llj mH DI A, A0 Hao x" L-\o Au H 1ɎC @ Ha\o MH W 1H 01蝎 AFfInDLLhflL@HPPA LHjao LHL HDžT pH<HXPAWDAZA[ D E1H t*HHDA H DHHHt<H( t L(LD LHD AUL LAWE1 L^_tL(D HDtmf. j HE1Lj A DAXDtAAY t#Hq_o x" ff. @ E1H@"HHu"E&Hǃ A~t, {L趤AFA~ )A~|)L$" HYo H H q 01 q HA HHLEHH9t8HP ~ uAu H8 HMjH~H H H^o x" Dtf. HXo H H q 01 q HA f. HL1E1DIIHDž( IcAD@A LM9 D LpEE A uL H(DLD H fo@H(D DfoPDfo`D fopD0foED@foEDPfoED`foEDpL1A LhH~M$L @ DLMcH(D N4+IvD HI9 H<H@LD(?C7 D(L-Vo M11H H D(Au 'Au M1(Hd 1 % D H[o x" ?HVo MH 1H 01̈ HaVo M1E1H R H 01蚈Dt D L-)Vo A1MLHg 1Au dA~t, wL虠AFA~ h%A~_%L HZo Hǃ x" Au MH 1H4 1g L-Uo H 11Au Ň HD<HD LHH@H(1D LLDEH H f HAVL LE1AWH DZYuPH wD<LHH@HH(H u.Dž LDH LH <HDTo MH : 1H 01耆V,HYo x" ~1AE1H(1DLH(D E1 D ff. UHATSHdH %( H]H Ht I{u-HIDŽ$ HEdH+%( u5H[A\]Ð tHC{ "{"`+ UHAWAVIAUAATESHHHHudL<%( L}L}HE E urE M EIN-H}Hw H) HDM+~M1 r HEHUdH+%( He[A\A]A^A_]fH H ?[DMt;H}Θu.AVHMHUIj DMHuH}EZY p p {" H5=Eff. Mt;Et6HEdH+%( Av(HeI~-[A\A]A^A_] HTo H LMDEM HQo Lɀ8 u(LϾ/ DELM;}LMDEHHHID1H} LMH_ pLMxeHELHEEHEHǃp ef H LEH}H^ ) D H d @ 1( UHAVAUATSHdH%( HE1HE L HIIMtdA>[tnL֖ubj HULA j ILLZYt=ǃp HEHUdH+%( uSHe[A\A]A^] L A>[u p p {w 1 H;1' UHSHdH %( H]HH?HtHQo H;8tH HEdH+%( uH]'f UEHHdH%( HE1AQE1HUdH+%( u>'ff. UHAUATI( SHHdL,%( LmIIHI$HLhH ff. fH;ZsHJHt!HH;ZrHJHtOH1 HxfHP@Hz@tI|$HEdH+%( uMHL[A\A]]HxfHP@Hzf. HxfH@ @I<$!& UHHdH%( HEH @ HtHPH9s"H@HuHUdH+%( u H9s H@ D H@% D UHAUATSH(dH %( H]H_HtiILm HEHx>`L HHtAHCHHEzLHHEHxI;|$uH}zH}LID$ D HEdH+%( u H([A\A]]% UHAWAVAUIATISHL dL4%( LuIM A?[|Ll0 5GHHJH@L+1A fHnM1LflLCAVSXZHEdH+%( u!HeH[A\A]A^A_] L o/$ff. @ UHAVLwAUATSHHGdL,%( LmIHHXLbL9u&c HLIT$ID$HJL9tBIHKfHnH{flHJHCn^H;HtG+t;f HEdH+%( uHL[A\A]A^]]X# UHHHdH %( HMHH A fH;HsHPHt!HH;HrHPHtOHE1 HVfHFF HPEtHWHEdH+%( uMHHh HVfHFF HPf. HVfHF F Hr"f UHHdH%( HEH @ HtHPH9s"H@HuHUdH+%( u H9s H@ D H" D UHAVAUATSHH_dL,%( LmIHu BfLLeL Ht(HLsI)wHM;euLwIEfHEdH+%( u H[A\A]A^]o!f. D UHAWAVAUATSHH ,H dH%( HE1脕Hp ?L,HMu Mm M Iu HduIMIUIEHQH H }p H }p H|p HBIMIUAU8,9: IU(H Ht$IU@IU0 HH)e.H H)؉HEdH+%( H H[A\A]A^A_]Ðp L%s|p f D L-i|p IU IEfInMuflHBHIEIUAE HHtHPfo + Iu0I} H)5p AM[BI}yBI}pBLp p @ H=zp ~ M9$$^1H1Aą H0Oi H mIH H IE H H p E1E1H`IU@HL| I!LCTDIE07IM0Hu IE@H LcH1IN$L9rrAE8 1 HweHHIE( LHAI} &ALg 1f HxL9 L H) ,HuL A]8Hc dH HIE(mLpA HHLMEAH ) A9 HxAII}L9 L H)~+HuH DMcLJ H yp IEHyp HAHPp IMH yp IMHHIE HtLhHHp p L,HIEHHp J D HDo Hٿ 1HR 01vaf. LDDAE8 1 HucHHIE(1 f. L CH%Do Hٿ HBR 01ev; f. f. UHHdH%( HE1G0 HUdH+%( uff. @ UAIH Q HATSL`HӺ LH dH%( HE1ڒHL|u foHEdH+%( u H [A\]Lff. UHAWAVAUATSHhdH %( H]H HC(oC0LkHH HULHEEOIHt @ {LpVLHI LHu!BL& 衈LEfoE1fK @C<HEC) C(fS*C,M( A$ @ ff. LhHEdH+%( Hh[A\A]A^A_]f D HuH= E1}$ {H/uHAo HKH H 01s D o o 1C) fK @)MHEfK*C()EC,f~K<A$ @AHuL0{Lsif D EfoEC) fK @C<HEC,C(1fC*E15 D UHAVAUATSHDgdH %( H]HA AtEEu`HS(C1f:fB~L @ H;D)HK(IcAfDQD;c|% D HC( fSPS fPSfPHEdH+%( H[A\A]A^] HcCHS( E1 H;A H fr1Hf fBx(A6 EAV HC(DAIDH;AHc tD@(AH;eoA9|Sf D UHAWAVAUATSH H $ H8IILLdH%( HU1A HHA1V LM H߹ 薏XZ1H1踒Aą Ǻ HPDIsM HH5YM BƄ- 2)H52 HHHHD)H5-M HHIHD(H5M HIHEH(ƅ HH Hs HzzF HH*/Ht H! H9HG H IHt ItIvLHH)H)Hڃr%1AN N 9rff. A M I} 1bfAM I|$ 1EfHH1HUdH+%( ~ He[A\A]A^A_] A 1HLM1 H薍 @ A2T fAT H<o Hg 01 oMH<o Hd 01nMH<o Ha 01n H5J H&HH AT ATcH$<o Hٿ HJ 01dnH;o HV 101;n @ UIIɹ HHp fon% dH%( HE1HHFHLHDž&HHDžHDžAHUdH+%( ux UHAWIAVAUIATSHHhH}HHxLpdL4%( LuM\ HEL)L`AtJ; IBD AuE1HMHUHIE AE AF AE BD E fAEOk HEI}LIEHxH4sAV 1HL!H}LLHp軆D H2IHS E L2H xux.LxuA tx.uA.u A t @ H( LHE HUHDH= wHE|/t / fLH@H}MHLpHxL,Ex%HEL 1HMff. Lh.HEdH+%( uXEHh[A\A]A^A_]H9o Hٿ H 01HkEH8o HwG 01#kH8o Hٿ HhG 01jff. UHAWAVAUIATSHLfdH %( H]Hnt+1HUdH+%( H[A\A]A^A_] LuLL_uL`nuLkuMu H <o HSA R y# HA$ M|$H1fAD$LHKIULI A fAD$IE H)fHnAfHnAD$A flAD$HPHs1LOHKHSLH;̃ (A$ M|$(1fAD$LHKIULI A fAD$IE H)fHnAfHnAD$A flAD$HP lf D UfHAWAVAUAATSHHHH}HMdL$%( LeMFEpEA DuE DsL{ LAT$ 1HHHI<HMHMH}LAD$ Dk HލDHMfC脂uPHEdH+%( uIHHD[A\A]A^A_] HV1HMDLMLEu DuHA UHAWAVAUATSH8H}LELMdH%( HE1H 2 u&HUdH+%( H8[A\A]A^A_] @ AAQ H1HAE1H Dc 1HC D{L{DHM,0LDHBAFIH;CrHU HHMH}B fEf fC+Df1; @ UHAWAVAUATSH H $ H H $ H EHhIL`LdH%( HEH^5o jDž HXHtHYHHt D`E L LB LPPHLH(111L12ZY Hi@B A E1L MHHHHpDMHi ʚ;HHxf D AEH 1A @ IEHcHH HE1IEL9' HKP PЃ vȍP IUWHHH 븀 H IuHH AEH Hp 7HxHi ʚ;HH)H9 HIE8 ~t AU@fAEu fAEA}H t HXHHcX LLHIULHHHI)UHHύPHH)fAUV 1HG HF fAEAEAE HD6o x# 2 H`HLHh}= E1䋽 HEdH+%( HeD[A\A]A^A_] D Pw`IU7HHH LAH LM<HKf D HX Eu-uH1A Hf D IEHcHH HE1IEI9tSHZxxPЃ vЍPwIUWHHH f D PwSIU7HHH f D L@Hx LM<HZyfHHHE AE@ L9 HAr - L9 HH w -L9 HAx - L9 HP su p AEDL9 : HJaH1 IIE HcHH L1IE M9 Lr PЃ vɍPwdIU WHHH HHVAM@(AM@L9 L[?H~8M<LHHP6 IU 7HHH JLƅH LH>HH M<LG L>H M<LAM@r L LHx>HH M<LƅH L:>HM<L L>HM<LLb YL1A @ HHcH LE1M9tCLp PЃ vԍPwWHHH ȍPwB7HHH 벋 LDf=H| M<DLLE:A](L1A HHcH LE1M9tCLp hPЃ vԍPwWHHH ȍPwB7HHH 벋 LD<H M<DLLE A],L1Lƅ6HXH H x HЃ IE0ƅ HHTBHIU0I9u L <H~GM<LH*o L HQ9 A01+]ƅLBAEH Hƅ. L;HFM<LHX HI9uÐHD1Ha HH(HF*o Eȋ01\fAM A}H ƅA% AEH AEK(1L AMD AEH AEK AHAEH HHم=HILp HڅtO tJHHZHH)H 0CLM9u Ln:HM<L LUHAWAVAUATMSDÉH8E LuHuHMLmHLɉEE(LEdL%( LEMOtxHuMMLA?x[D9u6} t0EHHuDMMLP0BZY 1HUdH+%( uHe[A\A]A^A_]ø @ UHAWAVAUATSH H $ H HEDe(DU0H] HHEIHPH`DhHD_D^dH%( HE1Ep IHt DKE/ hHLL6 LPLK(1xL1HH=_AX HE1HHHHxv f DEL EgIA Hpu HpS 1HHHHHpS HpLL H fAOAw 1pHHڋp fnfAnA A9fAvs AEHF LfnfAFHfbfbflAFru LlIDH`HO=G HHHL~r& 9h IL9 HHx ƅ J<(H\NHHH8 ufۉlA A_DcDžA+hHIWLL[D ?_ 2^HDIPhLHPHt>ZYf. L1 HHH L9uHHEdH+%( He[A\A]A^A_]f. LEHHIDDL7KAŃtLIىDH`LK;wE9nEeHEdH+%( Du;AhIDELHPHHe[A\A]A^A_]@=ff. UHAWAVAUATMSHXEDr H}Hu]HUMn ELMDEdH%( HE1@IH IH I(IHEH LIHEH I HHH ED,~ HuHcLu @ I<G0 wRH LoKHU: u8UHHMAHuA LRURHUuuu"H0HA9HuH1H}H}L}HEdH+%( uHe؉[A\A]A^A_]ÃS뷃뻃 @ UHHDG(OdH%( HE1HWHwHLO APDG,APDGH)HEdH+%( u1UHAWAVAUATSH H $ HHELJ(I IHӾ H EdH%( HE1LF0 HqH1HH;~ A A D9DNIcH HH?HHC H0 ?HH/ AfnE AGH EDLHH@H HHHDL HH HL HH HL HH fHnHVfD fDfDfff. fLjH LLLL(LXLjLjLpLLL L0L`LbLbHxHHHH8HhHZHZfDfDfDffD@fDpfDBfzHHHHHHHxHJHJH9DAz HcDH@HLM(M`IXEPEpIH DGE9@ LD0M(M`IXEPEpIH DGE9 LD`M(M`IXEPEpIH DGE9 L M(M`IXEPEpIH DGE9 L M(M`IXEPEpIH DGE9 L M(M`IXEPEpIH DGE9~nL M(M`IXEPEpIH DGE9~FLP M(M`IXEPEpIH A9~ H L(L`HXDPDpHH 1E11tRHcf~1ҍHHF(L IMND( @ PH0ʉHL9uBLBLA9 EN A)A@Eà EHMb(I ;HH [H(HI9} I,L9 DH fnfAni(fp fo H@fp Hfp fnfDofDp ffnHfAs fp D fofDoH fffofs ffAfpfpfbfofAfbf֊@fof֊pfofjfpfDbfofbfDRfJH9qDAteHcH<HHf~W(AQ(ʉW,PA9~@Hc)ڃH<HL>fA~P(AQ(AP,A9~HT>0)f~R(AA(ȉB,LHIIMI f. II0L9 1LHL[`tLAIff. I<$1IqL9uLHLc1LIt @ HHHtI9uHHEdH+%( HeD[A\A]A^A_] LAIbfEHLLLPj wZYAU D T Af D HHHT(1ff. f D f~Ay(H0HωzL9ugNZ1AAA UHAWAVAUATSH H $ H H $ HhdH%( HE1H 3 Hu/HUdH+%( Hh [A\A]A^A_]f. LII־ HS LOxRL# H5 IH)I<MMLHpLHH a1ZHjo H 01J4~ff. UH HATSH0L` dH %( H]HHUH o HE z# H}Huu( { HHEHtL{ t fPLHUH5*H}؉HEdH+%( u.H0[A\]Ho H 01If D UHAWAVAUATSHHXDq H}HUHMM~ DELdL,%( LmE=H IH I<HEH L<HEHg I <HHJ sUAE1+ MHEU AD9{ DHLMHMLAEHUHuPEPuu H Aƅ El$DH?A9tC~& El$DH A9wAD9sELMLHMHUPEHuPED$uuH 6f D H}H}H}LHEdH+%( uHe؉[A\A]A^A_]H}1봃븃뼃 UHHdH%( HE1Ht BuHEdH+%( u&1f D HEdH+%( u ET/ff. @ UHHdH%( HE1HEdH+%( u1ff. f UHAWAVIAUATSH H(H}Ho x# dL<%( L}Iu( Mh M LFH8 I A HHH A t H o MO0fCIE y# H H H{(HPL 1FdAW HHHD(IT$fCIE H@HC I$H)fHnAGfHnflCCXZH}LLH_HAE HEdH+%( H}HeLL[A\A]A^A_]pHH{HH PL 1xcAW LHH HHDHIT$fCIE H@HC I$H)fHnAGfHnʺ CflCY^ Ho H- 01D Af. HEdH+%( uHeD[A\A]A^A_]zf. UHAWAVAUATISH8H}HUHMdH%( HEȋF@ Hc H IcT$ I IfXHP~JI]E1DL DLIHtgHߺ LHAHHCE;|$|H}HM1LHELHEdH+%( u@H8[A\A]A^A_]KfAHHCHCE9|$Z뛻Lff. UfHAWIAVAUATSHHhHMH}HdH%( HE1EHuHE b@1LAƉE"LAEDDeLAʼnE'ljED)ODD)9 HIcH L|HHHPI9r; u2H E HLxL IMu+^ IIIL IMtAJ IFH}fE~HEL}H}HM1LLHEdH+%( u:Hh[A\A]A^A_]f. E A = Ixff. UHAWAVIAUIP ATISHdL<%( L}I H H K P 1fCA$LLfo HC HHCAD$8CHC(AD$HC0 HC8AD$HC@ HCHAHAHEdH+%( uHD[A\A]A^A_]Aff. Ufnfn1fbHH@dH%( HEHL 0 fEAo HuHMHMEHEI@HEAHUdH+%( u0 IM UHHH dH %( HMLHuHuHU1LMHUdH+%( uff. f UHHAUIATISHdH%( HEHH HH҃H@H\HSHE@HSHE@HSHE@@HSHE HSHE@ƀHSHE HSHEڃt@HSHHDڨHSHEH HHHHH8 HA tI H H\A t AE\H\A tI H H@H\A tHI A tI HHTHHEHCA @ HEA HCHEA HCHEA tHI usHCA HEA HCHEA @ HCHEA HCHEA t IP H\HEdH+%( uWHH[A\A]] D I 1H x I 1H HCHHHDoff. @ UHHdH%( HEHG8HHEdH+%( u*f. UHHAWAVAUATISH_HdL,%( LmI t IU H_HWAt IU HHSAtIUHHSIAt IUHHSAt IUHHSA@t IU HHSA t IU(HHSAĀt EuXHLsA t IU0HHSA I8 HHHSH h H I( HSH I0 HHSI@ HHHH~_E1AHHSIHHJDJDHH)I)r1A˃O<N<9rHHAE;8 |A A & A X A t@I LsHo HI P/I LH HLA tM HLsMb A @ 5 A t IE`HHCA t IE@HHCA t@I LsH HI .I LH HLbA t IEhHHCA tI HHCA @ t IEpHHCA t IExHHCA 6 HEdH+%( H1[A\A]A^A_]f. H L_H LHw HtI0 HSHSI@ HZH IH HZHBA @ I HHL< LL@A AU\HH I L!H HCHAE\HA I HHH@L4 LL IP IX H{Hf HLLHf I HLnJ3L0HX|f D HtSI0 HS HK I( HSHI0 HSHSu H UHHHdH %( HMH@t HBHHA@t HzHHx@@t Hz HHx t Hz(HHx@ƀt zXHHx t HR HHP)HUdH+%( uKff. UHAWAVAUATSHxH}L"HuHMdH%( HE1L9 1fL9r A$ HM$$HL9u1HLEHM Ho H 016HMAT L9HMLFK<RLUHH IHO LUHMAE E MMUIIFM4$HEM9 DHx11L]LU1fEMHAL9} M6HM9uHx HΉHHEDIMH}1fAEHMLHELEEHUdH+%( Hx[A\A]A^A_]ÐA tE1DLUIHpLALhuf D ~@ fɋP,It$foHffHLIfbCD~@,LcP(HEffMT=@HLA HfbA; HEI9rB1EEfEMH}1LMLHMfAEAхHEH)xE1E1I MH}IH4LUKtLUHLu HpLUHELh. 1~H1HH@b UHHdH%( HE1HEdH+%( u E1-S UHAWIAVAUIATISDH8EDuHMLEEdH%( HE19Hu I|$ t=HEdH+%( HUH8EDL[LA\A]A^A_]m: D I<$ uI|$ uA|$, u I|$ HEdH+%( DMHuH8E[LA\LA]A^A_]EH o Hu 1323Hu 1123Hu 1123Hu 112HUdH+%( uH8[A\A]A^A_]1q UEHHdH%( HE1AQDHAPL o H15MHUdH+%( u ff. @ UHAWAVIAUATSH(H}HP dL,%( LmIII IT$0HL8HHUJHøHtKHUN H{HC IP fSIT$L{H}11HAH߉EaEHUdH+%( uH([A\A]A^A_];ff. UHAWIAVAUI0 ATSH(H dL$%( LeIL0HøHtDAH 11H0 LLsCN fCHC AH߉EEHUdH+%( uH([A\A]A^A_]}ff. f UHAWAVIAUATSH(H}HdL,%( LmIHdII IT$0HL8HHUHøHtKHUN H{HC I fSIT$L{H}11HAH߉EEHUdH+%( uH([A\A]A^A_] UfHAWAVAUATSHHhHUL H}LdH%( HE1EHE L},1LAƉEnLAEDDmMLAĉEOljED)ODD)9 HIcH L|HHHPI9r/ u&H E HLxL7I f D IIILIM IFH}L}HEH AN H fE~IF IFH}HE11LL&HEdH+%( u=Hh[A\A]A^A_]f D E A }I` D UHAWAVAUATSHdH %( H]H H9r IIIׄt4 H tLHLAąa HI91 tHP Ht 8 tLHL Aą= f.H ztLHLAąqHn Hp 101- LHLAąxH tLHLAą LHL=Aą HI9tW tHP Ht8 tLHL/Aąxg 0 f.H bqW E1HEdH+%( ucHD[A\A]A^A_]Hn Ho 101,Hn Hko 101+Hn Ho 101+f D UHHAWIAVAUL ATISH(H}LdL4%( LuMHUH Ao$HHUL@AoD$@AoD$ @(AoD$0@8AoD$@@HAoD$P@XAoD$`@hAoD$p@xI$ AH C H|ܵ@ fDkI v0HHEdH+%( u4H(D[A\A]A^A_] H}11HAAAx UHAWAVAUATSHdH %( H]H H9t^III HI9tH HsMLH AątHn H'n 01* E1HEdH+%( uHD[A\A]A^A_]ff. @ UHAWAVAUATSH H $ H dH %( H]1IH AIWH HIǹ HHHLDžB IHZHH؉H)1HH fAL2HH11fHP)P)`DX)p{u'HUdH+%( u HĘ [A\A]A^A_] @ @ UHAVAUATSH H $ HP1MdL%( LEE1 u#HUdH+%( w HP [A\A]A^]LLIHL L HH H9HGHsr AEf $ H fHHG@DžC H$fHH2L1LL L LAOTNT LL)I)ȃh1AʃO O 9rLf D D D/ED fDD f D D DED DD @ UHAWIAVIAUATISH(dL,%( LmIEt LLLDE+DE ALLL Iv(1LLÅxTIv1LLsÅx=1LLLÅxG1HEdH+%( utH([A\A]A^A_] D Hn H2j 101% D Hn H 101% D Hqn H 101%}ff. f UfHAWAVIAUATISHhH}HxdH%( HEH:ep )E)E)E HG HH!HHEHs LeI H LH]= HEL-5n HEb HE1H}H@ HULxHufP1 P HxЅ S LHc= } LcKID x! tCHE H}Lu H}sHn HU 01G$ D Hn ٿ Hh 01"$h D Hu H}11fFHxHF P H}EEHUdH+%( uHh[A\A]A^A_]ø UHAWIAVAUATISH(HUL HLdL,%( LmI(ÅxyLLLL Lt,HEx# pLLL#AÅ HEdH+%( H([A\A]A^A_]fHn H 101" D EHnn HGg 101"] Hx<g H1n H*g 1D01t"YJf. UHAWAVAUATSHdH%( HE1H H}E1LuL-G L=@ f. LL#HH LH~ H5 HgtsH5f HT H5X H=u A H5R H!u At @ H5_ Hu=AT @ E1HEdH+%( u&HD[A\A]A^A_] @ A A UHATSH H $ H dH%( HE1(tHH?HP (t+1HUdH+%( HĠ [A\]f. H tLL L L >L uJH;L8t#H8 MI1HHn H#e 012 OH 8 tw#8` HHn MHd 101 f. UHAUATSH( w$dL$%( LeIHa Hlj A|$" t9HH ID$HEdH+%( H( [A\A]]ÐDEtA9tHn IL$H/d 101 ff. 4f["HP L-n 1IL$IH 1Au t Au H@+ 11 / I|$H5 uAu H 1y Hn IL$Hc 101Y D/ff. @ UHSH (dH %( H]Ht6H{1 B Y?x5C1HUdH+%( uiH] H yBf. +!H` 8HKH 1IHIn 01 H{&c UHAUATSHLo8dH%( HE؋G@x?HcЉHRH@HHMdI\ I) @ {XHHL9uHEdH+%( uHL[A\A]]ֲ UHAWAVAUATSH(udH%( HE1! E J HcIAH<@HIHe E HLeE~xIDE1H H y%! D INj u\L$tMH;1 B y=x̓EHE CE9EuEIF0 E1Mn8AF@d AAċMAtGHcЉHRH@HHMtI\ I)ff. {ظHH3L9uLoHEdH+%( uWH(D[A\A]A^A_]H_n A+ H H< AH81AIA @ UHAWAVAUATSH H $ H dH%( HEHG0H ! I H$ H?IH Dž( E1f. LH HLp 1AVM $H L: Hz8H0H!ZYuH% = u H5 L_w(L,HH@HHH LIHm H HL|茠IHH 11;Å AGH`LIG,M(Hff. LHM (M|$8AD$@1HEdH+%( He؉[A\A]A^A_]ûLHc(MnH@M$f A|$&LIM9uL轮Hn Ag H L H H81QZAk Hn H Hu H81&((LM;ػf*! UHAVAUATSH dH%( HE1! t}G@I1L@`HpHID$A9^@~JIV8H[LL$A|$tHUdH+%( uRHĠ [A\A]A^]f 1 @ Hn A H Hf H81Bf UHATE1SH H(dH %( H]HAHo 8- C C# H1 {( C!H 1H{ H} S(uH; 誹 Hj 1HUdH+%( j HĠ [A\]Ðx X{# | {(H5B8 D#HCH( C C! H f HHCH HEdH+%( HĠ H[A\] D DcC A C( + H5 a @ HPDuh% = HC C# HeH HV @ H;HP h% = @ C!>f D H;xNDcC# g UHSH! dH %( H]HuMH{k{# t HEdH+%( u9H{H]1HEdH+%( u{H]ı @ H8*a UHATIHSHA|$# dH %( H]HtKIL$ HAHuHHUdH+%( uGH[A\]I|$Hf D HEdH+%( uAD$HH[A\]轹ff. f UHHdH%( HE1HEdH+%( u x UHHSH# dH %( H]Ht:HO HHV"HHHDHUdH+%( u(H]fHUdH+%( uHH]Hff. UHAVAUATSHdH%( HE1( MAHHIIHo L I4$H;J*u6EtVDcHEdH+%( HD[A\A]A^]f. H M$1H Hn 01@Eu{cH Aąx{1L Hul8ARL AIHn H 01K A8 D A(萷 UHHH0 dH%( HUHWt(HcO@~ HG8H IHH @ HHH9uHEdH+%( uH+ff. UHATSHdH%( HE1! t\IHLL H HL/x1HH9s*HEdH+%( u8HL [A\]鶳f D HEdH+%( uH[A\]~ff. UHATSHdH%( HE1HtsHL%A ff. HHt#Hx LrtA f D E1HHEdH+%( u HD[A\]յE1 UHH dH%( HE1! t\HH HXx=HXH`HXuHUdH+%( u @ HP1G UHH dH%( HE1! tlHA HXH& >xJHXH`GHXuHUdH+%( u f H踤 1觴 UHATSHdH4%( HuH5 XHtQH}H Hþ E1wHv H}AHHEdH+%( uHD[A\]E1 U1HHH+~dL%( LEDFHIHH1HHIHHUdH+%( u躳f. UHHH~! dH<%( H}HtHGH)H#WHHwHHH!HHHHWHHHUdH+%( u<ff. UHHdH%( HEH' Hf. tnP4o@@oHPVP2flfHPXFHVP(V P(V!ʋH9uu~ t61HUdH+%( u,HNn HR 01 ̸^ff. UHAVAUATSH H $ HĀdH%( HE1LIIL HHO 8 HM ILH`H) t&HUdH+%( HĀ [A\A]A^] Hin HZQ 01 dL1ohLLH`HHxHff @ 1[$ @ UHHdH%( HE1HEdH+%( u1ff. f UH HAVAUI ATSHHHOLdH%( HE1`HK LLcH 1CHK LLcH 1&MLcMf{ w&HEdH+%( HL[A\A]A^] HK H L1 ֪HK( LAH 1蹪IcK0LH H1IH 蔪K1 LLcH 1wMLcMS褯 @ U HAWAVHLAUATSH8 dH%( HE1HDž HDž0 HDž 膮1҅IADA LA* 1|I AA!q IEC 1ۃ t H߾H E1ɉڿ* 1ADLL LAljA E*D 1A tA At 1HUdH+%( H8 [A\A]A^A_]f D &p ]H@ L HM IHn H81蔨LLjp f D xD8 EDߤ 2 D zp t @ H@ DdD HM IHSn H81'p UHHdH%( HE1=p t Huo HUdH+%( u/ @ ;tHKo 1ʇp H9o 責f UHHdH<%( H}h !Ht+HP(@ fHP(HPHH@@ HPHHPP @HUdH+%( uG UHAUATSHHWHdL,%( LmIHH H MeHI9t1HH HPHHH H H H H L9uHEdH+%( uHL[A\A]]鯛誫f. UHAWIAVAUIATISH8dH%( HE1L9MLEHf H^@HN@Hu I9s+HCLsHt+HHCL9uHCL9 I9rHCLsHuIGXI;G` IPH H L@fHMGXHL<H|(I71MLEMgHIG MoAW IG@ I_(AG0I>F HEdH+%( W H8L[A\A]A^A_]ÐH HuHMUHH L H IGPIWHHufHnMGPHMfHnUfl H L IGXIG` L{aHGXH;G`sdHOPH H HpHIwX1HMLEL<HD(I MgMoIG AW IG(IG@ I~H UUHHt<H H IGPIHfHnIwPfHnfl H H0IGXIG` RE1' UHHdH%( HE1HEdH+%( u1nf UHHdH%( HE1HEdH+%( u逪諨ff. UHHdH%( HEHn 8 tHEdH+%( u!1 HEdH+%( u˿Ff D UHHdH%( HEHpn 8 tHEdH+%( u!1 HEdH+%( u f D UHHdH%( HEHn 8 tHEdH+%( u!1 HEdH+%( u膧f D UHHdH%( HEHn 8 tHEdH+%( u!1 HEdH+%( uK&f D UHffHnfInHHpHdL%( LULVHEfHnHx(FPH4H4)EHN8H+~ V0~^fHnHMHH H@0H+NflH+F(fHnɀ~@ fHnflF]MEUtX E Et}Ȁ~B tEH1H}HHDIRARHUdH+%( u D fUHAWAAVAAUATSHH8HUL G dL,%( LmEM AT$Xt>^ I<$ HEdH+%( k H8L[A\A]A^A_]f D wu EJ SuE~E;t$XsMcLHL)M$f. u4Gu x HHu%E1[f D x HHtA DAXLHM۔HMH I̋K RI<$ E E H;H H H;H HIHp H ID$8H5X{ LV AD$\ 1LIcH A w HH8 HH< HA H>u, f HA IHy A IMt D9DDǾx UDEHH~MDEUuO H ID$8HEID$H x U.HH,UA HLDEHHH)HDEH#f D DH@H< ID$`HEl$h> @ ID$L K<HHI$M|$ H H0 u HHH<uHHH>~f D ʐHHp 0UHAUATISHxH~H dH %( H]HM D HCHZ HHfLCHH EfInH4CPHK(HCHV8H+N )p~VfHnHN0HUHS H+VS@fHnHS0H+V(HMfHnflˀ~@ FHE UMEuz ~B UtMIPHtkHHpAPAŅ)Hn H 1010HC HEdH+%( ueHxD[A\A]] @ Hp1APAŅf D HC`HC Cl HtH E1菠ff. @ UHAVIAUIATISHpdH %( H]HIFH IH HLy HfI~(INHH4EfInfHnH4AFPfInIFHV8H+~ )p^0~VfHnHUIV H+VflfHnIV0H+V(fHnfl̀~@ FUME] ~B Ut}HQHtIHHpQff. HUdH+%( u@Hp[A\A]A^] @ 1 @ 1HpQf { ff. UHAWAVE1AUATSH HXdL,%( LmL MN AEXB ME1H` IH D IGHU HfA~G@MGHIGH4M~XAOP)`II(H4HV8~VH+~ HpIW flfHnH+VH~0fHnIW0H+V(fHnflˀ~@ H}FHE xME ~B Ut}IPHtwHHAP AHjn H 101IG AEXAIxA9HEdH+%( u}HĈ D[A\A]A^A_] 1HAPuIGHAEX =IW`IG AGl HoH cf UHAWAVEAUMATSH8LMDUdH%( HE1DE D](H IϋO Aԅ, W! H IHt ;BXsHHHH)H H; A1D]LMDUDE%DEDUHLMD]H LHDXpE ClShDHs`D@ClH@H D HA Ly CpLi A HH9syHH{H Htrff. E1HEdH+%( ? H8D[A\A]A^A_] H H HCL9t H LKE1H{H uEtA A HCHH ոH1ff. ff. H3HH4HHI9( HuH*H HHT ff. HCHHHH: uHDEDULM<DEDULM MEMM9A HSH;E1AH;S HHHD`AHSL0z Ah D AVMMHCHHո ff. H HH HHI9tDHufHSHL K4H HHtBHHSL{EHCH n H9 1A01`6Hn H9 A019H;1ff. @ UHATSHdH%( HE1HtmHӋW uCGu<H 1҅HHtI;pXsDHcHHH)L$I<$ u*f. L MtID$H9t Hu%I\$HEdH+%( uH[A\] LA UHAWAVAUATSHxdL4%( LuL Mq AFXHO ME1L`fIH D IGH HfA~G@MGHIGH4MfHnAOP)`II(H4HV8~VH+~ HpIW flfHnH+VH~0fHnIW0H+V(fHnflˀ~@ H}FHE xME ~B Ut}IPH HLAPHn H 101IG LA腹I`IxxE;nXL L訆Hǃ HEdH+%( ugHx[A\A]A^A_] 1LAPgf *IG`IG AGl HYH M"f UIHAUATSHdH %( H]HH[ O H W H 1IH+ ;BX" HHHH)L$I<$ 1M9$ H IC I MC H MD$ LkKH4ŸI D I$H<0L9HH%HL9tL9s'IDHI|HHHHH9sII9sIHEdH+%( H[A\A]]f D M9M1IIHvL MSMCM/ D 1M9rIHvICMC HoICIMCf D HGIC MC+ff. UIHATSHdL %( L]IH O HukWudH 1IHm ;BXd HHHH)HH8 J 1M9_ I E1H 3f M9 A Hǀ1Iv_H HtFHXHt=H0H۹ HTƸHL9rdI9uEuZHHHH9sff. fIz MBIHEdH+%( H[A\] @ E1H gMtH9rH1McH)HH4H9rIH>L9HH%HL9tL9sIDHI|HHHHL9rd 1M9r9HǀI8@ I3A Hǀ @ H I D UHAVAUATSHdH %( H]HH, W u}GuvH 1҅HH ;pX HcHHH)L$I<$ Ml$`H IE HuF D HEdH+%( H[A\A]A^]L H MtMl$`IE Ht9H{FAL$lHAD$h)9HGL4@H@IItLuAD$hI9E sAD$lJ|3IuH@HHEdH+%( u"H[A\A]A^]u D H ,藐 UHHAWAVAUATSH(dH %( H]HH ϋH P H 1IH ;BXw HHHH)HH8 ] HH`H HHUHuQf D HEdH+%( r H([A\A]A^A_]f D H H HtHH`HHUHtPlDxhAHRKLdLTM9HSAE!M9 LE L9r9HFHAL9Au#HFL9 L;@A L98 H1oIՃHAE LvMuIH9AL9sEuL9}r[HL9sREtME MtL;Ar M9 L9 HqHt L9 Hq9s IHL9rfH E LLFMM9AD u~HL9rA1L9}rHL9sEtE ff. oHHHLALFL9j9raH A1ff. ff. ff. ff. ff. @ oIӃHHALn9MkAL9#Euf 1L9}HL9 E ff. HqHt L9HL99rxff. ff. ff. L9GoHփHHLALF9r!H @ EIE111L9}HL9s E1ff D UHAUI ATSHdL$%( LeIƮHtMH蕩HHt-LkLcHEdH+%( u*HH[A\A]] H{ 1 UHSHdH%( HE1Ht/HH?$HEdH+%( u*HH]{ HEdH+%( uH]ff D UIHAWIAVMAUIATISH HULXAt$XdH%( HE1HtU_ z D_Em H IHt,;AXs'HHHH)H H; M ff. fE1 LL@L@HH DH\LPPA4 HK@\ H- HCHI $H8HD IL$H IVLC8HH@DP耐H@A~D$IfHnflH HCH;CH;DP5 HHHHs HS(H<HKHC0A fHn~XfHnLG8flfDW@OfHnflGB HG0 O bfI HH{H DK\HCPAK I9tAE A9EP HKHHs HS(HC0A~D$IT$HE$ HID$PHs HS(HC0fC@AO I$DPD@H It$H E$ IL9 L HHKHIVLC8IH9HH@HfInHAD$Hz HCH;CH;D@DP ~K(HHA HHAHK~XK0S HP8@@ DXA@B H@0 PH Au,IFHt#I;Gu H@I9F(tC\ ff. 1HUdH+%( D H [A\A]A^A_]f A MT$M M $MtA H H< LL IKDL; HQxB H HIpL; xB LPIHfօ@< ~B EtUHHQH`Q IL$HQH9 fIT$IL$HH~XMfInAL$P)`I$H4HF8~^f0HpID$ @H+FfHnID$(H+F fHnID$0H+F(fHnflՀ~@ NxUMe D C\ @ A ; A AIVI9WHHBI9F(H;HLC8IL$HHpHCHH8Mt$IH HCHSH;H9d HPH1HSHS HHXH HPHS(LpHP HS0HxHP(Lh8fp@H@0 @B= D IW AP HEdH+%( uhHXHLfH~H [A\A]A^A_]G HL HIx HQHSHEdH+%( 肄fIGIH LH H< HQHHIDL;xB HsHE1fH~LXHL ( M $MT$MOA~D$ @ IFfInLs8flHPHCH)0H H@M9 M9 HXfH~HLLLLfօ HCL~ LHLY H HHLbIWI9T$h HPLMLH@LL fօ;IH HCH;CH;L ~L ~K(HPLM~XHHSLD= HK0fo0S L`8H@LfDx@@B H@0 8PH LPfօ 茈IH) HSH;SH;LP~ k ~K(HfIn~XHflS K0L`8fDx@@B H@0 PH HSHEdH+%( ,LXHLE1H fH~[A\A]A^A_]h DCXHLH0LPD@,H H{`H{H1HH H)HCp xHD@At$XH0LPDCX@HLLPD@LPD@LSPx H L0H4H@H) gHH H@HA~D$HCHSfo L0DPb HgHHuHXH;xMHLC81HtHCH1H8`IA$ I$fHnAD$M HSH;H;S ~K(HBA ~XHCHHS K0H Lh8fD@@@B H@0 P HHH= D L H0K4) HeHH; Hfo HCLcH0DPD@ D LLXE1L~@HSHLPfH~ LLPf IP8H;BT M;u 1AxB hI HCH H HHLbA|$ t M9 L3H@8HSHHXMnLxL"MK I- H57 L0LPL@nvL@LPL0HX M9 HHKL )@K4H9dHH HSHLcfo@LH@IH9PaH@HPMLH貃IHO HCH;CA L#~C(HPH~Xfo0HSIC0K Lh8A fDh@@B H@0 8H@ KtLC8LLL&H HSLHIHBHv HPMLLfօ0H@ׂIHtx~0HCH;C& LHPHHXHSHS A IHPHS(H HP HS0HxHP(Lh8fDX@H@0 @Bf@' L LK4LPfօ HSbHHtHLHCL{~ LPfօ@L K4H bHHvHSHLsLP~@NHC E11HLXfH~L%HC E11HLXfH~LLfօ H{ L~ 5] HXfH~HLLLLfօ $HCIW~ LHLLHkHH La6f D HAL HCIKDH@HII9@IEI9F(2HHK2L K4H~`HHHHCLclH@HPMLfօ0HIH~0LcL9c HCHX1HPHSHS HkHHHPHS(Hx1HP HS0H0HP(Lh8f@@ @B Hx0f@cL H;fօ@IkH_H~@HLcHCL H;IkHt_HHHCLcI H;fօ@IkH@_H~@HLc UHHdH%( HE1HtpW t)H Ht]H@HUdH+%( uN GuH 1҅HHt&;pXs!HcHHH)HH8 uf. 1x UHAWAVAUATSH(udH%( HE1 HcIIHL$Hff. ff. @ HH9HGH9HBHI9uH)HE HHHv H$I$I$HH)HH HHEE1ff. I1ҋuH=5n IH)D)HHcHuH H Ic1L贞AM9uHEdH+%( uH(D[A\A]A^A_] E1vf. @ UHHdH%( HE1HEdH+%( u1vf. UHHdH%( HE1HEdH+%( uɸJvf. U1H HHdH%( HEHߝn 01.HEdH+%( uɸu UHHdH%( HE1HEdH+%( uuff. @ UHHdH%( HE1HEdH+%( uuff. @ UHHdH%( HE1HEdH+%( u?uff. @ UHHdH%( HE1HEdH+%( utff. @ UHHdH%( HE1HEdH+%( utff. @ UHHdH%( HE1HEdH+%( utf. f. f. UHAWAVAUI ATASHӉH5 H( dH%( HE1!IExH fH*HCH fH*^LHYm HHH ^E L% Hٿ 1L5 LLLL H 1MeeM}LM9tC D L1ɺ LL HIH 1ҚH:M?M9uHEdH+%( H( [A\A]A^A_] D L%U HMu1L L 1HT MeM9tLL= ff. L1ɺ L~L HH1HM$$M9uA HfHH H*X=fHfHH H*X rff. fUHAWMAVI AUATIH5c SHH( dH%( HE1IFxH fH*HCH fH*^LLH Ԫ YOk 蚂Hھ LH ID$xH fH*IGH~ fH*^LLIYj &HL HH H LHL 1H 1H C H; M>I\$M9tzID$H`fLH1ɺ |H1ɺ HI|L LIH 1LMM?HM9t HH9uHEdH+%( H( [A\A]A^A_]ÐHfHH HCH*XH-HfHH H*X @ HfHH H*Xmf. HfHH H*X/]off. f UHAVAUATSHLcgL7dL,%( LmIE~"ILM HH 軑L9uL^HEdH+%( uHL[A\A]A^]^nff. @ UHAWAVAUATSH8H}Dw dL,%( LmADuH Ic IHIHH E~JHEHMcIHEHþ LI$H El$I AD$I9uH}EI?IAGHEL0L9 I 1HzM M I aHH AD$ M$L_A;D$ ILBx IJE1ɺ ff. ff. f D H1HvxL9sILcʃH9uL;G8sIO HHtLIH@HI \ID$A M6AD$L9uHEdH+%( ueH8L[A\A]A^A_] D E1u HcЃHM AD$ cLmLeLI ;I9uLw\E1mlLe\ UHHHcWdH%( HEH~,HH H H9t9puHUdH+%( uÐ1l UHAWAVAUATSH(H}W dH%( HE1} IE1 HELHHAG Iօ~WE1 fIE9g ~'LI>HI H3tHIFIHCHEAU@ 9}If. HEdH+%( uH([A\A]A^A_]-kff. f UHAVE1AUIH= ATE1SHdH %( H]HAM *Hf D H8ALIDIAM D9~ IU LHHHpHuID9H= E1E1AM ~ IU LHHHx t_ID9H= E1E1lS ~ H LHHHx tQID9HEdH+%( ubH[A\A]A^] @ H8A1LDIAM D9g냐H8AHڹ DIeS D9tif. UHHdL%( LEIH+t%-tx tk1HUdH+%( @ LHHLHQv HIHQwa IAH D HfLHHLHQv#f u+HIHQwa A IA 5h UHAVAUATISHHp y dL4%( LuIt >G} 9 t; t+1HUdH+%( Hp [A\A]A^]f D LpI$ HLf}uH} tHM1LLI$ H)LP @ Nf/v3HEdH+%( u.H LH1H@Hp [A\A]A^]Hgff. UHAVAUATISHH dL,%( LmIH5 H薃HI$8#u$HXI $P߀Gu6HI$AE 1HUdH+%( ulH[A\A]A^] {1HuH IKHAu"HEI9$t HwI$AU D @ f @ UHAWIAVIAUL- ATLISH(HMdH %( H]H H蠂HI $0 wnMtAHu1H IIAE ~ HEI9$t I$1 @ HUdH+%( uXH([A\A]A^A_] D HLHuHI $HI _HtHI $; t 1I$fe UHSH H $ H(dH %( H]HHHH H =L Htq{ LC8HHKu<HH P1TZYx>HHUdH+%( u?H]fP H 1AQLK@^_y1 @ HJ Ixd @ UHATISHdH %( H]HMt4A|$ tJIT$Hfo H HH HDH)I9D$sID$HEdH+%( u H1[A\] @ AD$ HI\$dff. UHAVAUATSHdH%( HE1H9 IHIIHH9u u HI9tDHI9t<I9u HI9t(H I9tHH9u4 +I9uIU HI9tI9tHI9t I9t*HI9uHEdH+%( uhH[A\A]A^]f D LH t I9tHI9tLHuLHA$ NA$ bff. UHAWIAVIAUATISHH(DEdH%( HE1H H pH MIŅ E1 IH I<$ t-1HUdH+%( Q He[A\A]A^A_]f IMH)I $uLˬIHuI> uL5Ήn A6MIH 11 A6H; 11uIu-H4uAD9}uIMIIE H)I$|I> 8L5Vn } A6~upHH 11茻z IHh I<$ u IEH)I$Iu-HtCL۫IHuI> L5ڈn A6HH 11 `fL5n H11H3 E1A6LHnE IHui @ AG*Ag t <EAAwHEMG1EA6ATH^ A 1肺XZLIHt5Mg-HLtEuE1A6LH$ 11=A61HH 1%A611H Iu-HQIMIIE H)I$IHt[I<$ u IEH)I$Iu-H uAE*<L0IHuI> L5/n A6Iu-HuAE*<uIMIIE H)I$ff. @ UHAWDAVAUAATISHDH(dL4%( LuIVHtBHLHHEu\{! Hn EB( {" f{$ uZHEdH+%( He1[A\A]A^A_]f D H}iHuLHHEVuHUA< utHn C$ L1H' 01@f D {" tbC KC 9^ff. Hn H1K H× EM0AT1C$XZ f. K ]f D UHAWAVAUIATASHH( dL4%( LuI HGHu LH+GHG{" t.HHUdH+%( Q H([A\A]A^A_] AFt?L3LL L%hLLHIDUu C|= 18FtL;LLƠt2LgLLHHETuHUA| u {! uZ{" tC C ;CuC 1Ls {! uJ{" tC C ;C^fC# fHn EB u{" u1Hn EB u{" u1[ff. UfHAWIAVHEIAUIATSHHdH %( H]ȉH HH HH}H=r_ EHEEEMEnmxJ} ub} HEE1IHEIHEdH+%( HHD[A\A]A^A_] @ AHn H 101H n L11H} 3HuHH=^ E l3H/ 1L1ô3Hb 11豴AML%Gn H 11A4$苴A4$+Lu=H 11nA4$H 11ZMH, 11CH- 111 Zf. UHAUIATISHH(H? dL%( LEA It$ID$ LkA~$HC HC(fHnAD$(flC0CHtA|$$ u*H 1HUdH+%( H([A\A]] ML$AT$ 1fInflA0 艎HHuHn H 0141Hf. 4p &Hn H= DEHDE3p Xf D UHSHdH %( H]HH?HtHs{H HEdH+%( uH]aX UHHHdH<%( H}1tnHpH5+o ҋ6H1HPHt HrHHEH0ɃHHEdH+%( u>Hn Hѿ HW 01 D H@ HEdH+%( uWf UHAVIAUATISHHH~dL,%( LmA{A S$t,Dk uDI|$ DgI|$(C(HtJ1>C HEdH+%( u:H[A\A]A^] @ C(I|$(D=C C Vf UHATSHdL$%( LeIAt$fff Hc( 葝HtltFHH H ff. ff. D fHnHB H(flBH9u1I$HEdH+%( uH[A\]f12Vf UHHdH%( HE1HEdH+%( u ɾ QUf D UHAVIAUATSHH?dL$%( LeIA;v r6 A ED9sDH <HH IEn ANAAFu%xff. ff. fo tUȍHHHHHL;br؉L`1HUdH+%( u-H[A\A]A^]þ A c @ HøTff. @ UHSHdH %( H]HuwHC HEdH+%( uH]Tff. UHHDOdH%( HE1E EQDWH?A 1 f. o q D9sMЉDAHHHHE9 DHHL^L9YroC Dq D9rIJHpD ;ff. ff. ff. ff. @ o t ЍPHHHHH;qrHDHwHEdH+%( u D o HwDAS UHHdH%( HE1Ht HEdH+%( u$HGf. HEdH+%( u1R UHHdH%( HE1HtHEdH+%( u6HGHkzn 1Hb 01豬HEdH+%( uɸvRf D UHHdH%( HE1Ht HEdH+%( u"HGf. HEdH+%( uRf. UHHdH%( HE1Ht HG HtHUdH+%( u D HEdH+%( u1Q UHHdH%( HE1@t'Ht"HG(HtHUdH+%( u HEdH+%( u1PQ UHHdH%( HE1Ht HG0HtLUdL+%( u D HEdH+%( u1P UHHdH%( HE1Ht Hw`HEdH+%( u H HEdH+%( u1P UHHdH%( HE1Ht HEdH+%( u$HG@f. HEdH+%( u18P UHAWAVAUATSH H $ H H L`HhI1HH`EdL,%( LmMHxZHxIFhL LpE Lx1M9 H\wn HA H 0LL)P1荩IVp^HpHx_H I~x1HHH1HHH9rIFxH)I9 E HHX\HpH9xHXIr L9 L)IL9r IFxMI)HL)M CPt1LHI)I)LIE H)HHLEH1HH0 LLfI MLHhHA DžG H`LVLZY HpI Eu-IVh$| H( HCHHtA HЅx HUdH+%( He[A\A]A^A_]fH!H!HffA IV`LHLxLp u`Lp @ L)MM 7E11 @ I- I~p LI~x1HHHH)5f D : Mf UHHdH%( HE1Ht0:euFTHHt6HG8Ht-HMdH+ %( u> 1HUdH+%( u' D HYtn H 101蟦sL UHATSH dL$%( LeLg`M HGXHt~I $I9tu@HI9th9Cu1 u]I|$u u܄uaI|$ :\H Ƹt%HEdH+%( uMH H[A\]?HUdH+%( u(H [A\]HEdH+%( uH H[A\]`Kff. @ UHAWAVAUIATSHH(H}dL4%( LuIHX H 1HuL0IHEL8 H M L#L9uN @ M$$L9t'M9$ uL%6M$$L9uff. L;I9 E E1ff. fL5 LMEHt%@A MttLLH?EM?L9uEM A H} L#L9u>xf D A EtJE- L xrM$$AEUL9t<E$ M9$ uL 5AE$ L 跶M$$L9uA}U u V 1HUdH+%( H([A\A]A^A_]fE$ M$$L9M;$ uL4o @ HM DyTMLD Hpn A D1H 01` @ L>L90I Hpn H 101ϢHnpn Ho 101财fHQpn 0EtH 11蒢H! 11耢mH pn LH 101_LHon H 01C0Hon Hx 101%Hon H 101Gff. f UHAUATSHdH %( H]H H9tEIE1 @ H2 H߄LEHt8Mt3HLL]HL9uHEdH+%( uH[A\A]] HI9u9Gf UHHdH%( HE1 HEdH+%( u1F UHAUATSHdL,%( LmIH?H I9t" @ HGIHCH6HHM9uHEdH+%( u H[A\A]]F UHAVAUIATSHHdL4%( LuIH;? LgIT$H wDHBAMHLLrHJ ID$1HUdH+%( H[A\A]A^] D 讓HtmL`1H@ HCHI$Iĸ f D vIHt2H@ HCfHn1LcfHnflA$L E|EUf UHAWAVAUAATSHHHudH%( HE1HHE H9t1 HPHMH H9uHUHu DjHt5耢 HUdH+%( HH[A\A]A^A_]f. HELuL L9t]E1I|$ I\$u>f D IHM;|$s)o LD)EiHt uM$$HEI9u1`YPD UHAWAVIHuAUAATL SHӺ H8dL<%( L}AhHs HEE HHHEHHI9K Lu. D HrHEHMHLHHHBHEHJ IwHPHUH LDChH L; L( IWH v H Lx 1H@ H( L IITHHHI9| Lu$f D HHfoEHADIGHEHPHUH LD~gH' L; L( IWH v LH Lx H@ H( L IIǸ _ IH H@ fIn1H( L( fHnflAL88 趏IHt^H@ fIn1H( L( fHnflAL8 @ 1HUdH+%( u H8[A\A]A^A_] A @ UHHdH%( HU1Ht HH9HDHUdH+%( u D HH9HD/Aff. @ UHSHHv dH%( HE1HtCHH ,'Ht/@ ;Cs'HHHHUdH+%( uH] 1@ff. @ UHHdH%( HE1UH @uHt>z u8H z u+H Ht0Hx t)HWHwLEH 1HUdH+%( u ø@ UHAVAUATSHLg(dH%( HE1҃Mt"HEdH+%( u^HL[A\A]A^] LO0LwHAHo 1 DhM!MM)LtHtN$(HC8Ls@Lc(h? UHSHdH%( HE1H( t5HH8Ht)Hs@aHC8 HC@ HC( HCp HEdH+%( uH]>ff. UHSHdH %( H]H^R{H uHEdH+%( u(H] CH H{(JaHCp HC |>ff. UHSHdH %( H]HOHEdH+%( u HH]2.->ff. fUHAWAAVIHAUATSHH(H A dL$%( LeMHRHHt@t;HcHHHHr'1HEdH+%( H([A\A]A^A_]Ðx XIH y H x ANA9 MKIx u IU @HPIVfHnHJINIU`HPLh fHnflAE L*fAF M:M,$1 ANH@0H+ H IE(A9nAG 9s t9r9C9 Mfff\ ھ( HHUYHUMHI6 HLIff. ff. D fHnH@ H(fl@H9utPIH LL HH9tHzHpHyHHHrHHH(H(HJHJHHHJI9uA^Mff ( M耂IHthM % x# I]uf@EHx;H+Ht.}HHHE`HMH9uAIM(AEH D IE( LdYf D HxOEH+IE( Ȼƻ":f UIIʹ HHĀoBdH%( HE1H}HHBHMLEHEHB$R LUHE)E`HUdH+%( uj:f. UHAVAUATSL$ H H $ L9uH E1HILIdL,%( LmIHLH߹ >u H:Gt&HUdH+%( uFH [A\A]A^] Jf/v L9uLE1HL"f D 9 @ UHAWAVAUATSH(dH%( HEH Htrx ulL H IHHEI9tOE1I} M}t%IOIHLu,IIM;urMm HEI9uff. @ 1HUdH+%( uH([A\A]A^A_]8ff. UHAUATL`IHS HLH dH%( HE1HHuHP Hr LEHpDžxHtYI$ HtNH(P E1L@$H߉|LEHUdH+%( u#HĈ [A\A]] ո7ff. f UHAUATSHOdL$%( LeIteI$E1K\ HHH8H9t?ff. HHGfHnflHBHAaI$HH8H9uAL$IA9rLZAD$ HEdH+%( u H[A\A]]#7 UA҉fnfnfAnfAnں@ fbfbHAVflAUATSHH Ls0HDm(De0dH%( HE1HG HGd H)xHH LDKHEHuC CHC HE HC(QEt<C x DkpDctfCHEdH+%( u%H[A\A]A^] LXA86ff. UHHdH%( HE1jj u uuJH0HEdH+%( u5f UHAWIH AVAUATI SH(HZ]n Hu01dL,%( LmI蕏I L6~HxIWHtc F HAFLfCLHL3kAąuH}11HAAH%HEdH+%( uH(D[A\A]A^A_]A4 D UHATISHH'cn dH %( H]H8 ujI$ Htx t'HCHUdH+%( He[A\] I$ Hte;Gu`I$( HLPHHy @ H^n HHKHZ H8C(PC$PC PLK1LC.H TH_3 D UHHI dH%( HE1I G fW GGG@t9G 1G8H0 HW0HG(HG@ HEdH+%( u fW c3 UHAWAVAUATSH8dL4%( LuI( IHV HuH1E L= ff. ft<PLoYwPIcL> LmAF GLuff. t} uAF8 IF0 1#fHaZn LH 101褌HUdH+%( Y H8[A\A]A^A_] D Lm<yd AFG<,t< } HW HHR< t<,tH}л 0 Hu ȪLEIF0A0@ t@,u&IPff. 2IH@ t@,tIxH}@ i@ L @IcL> Lm<L| AFAF,@ G<,t< HW HHR< t<,tH}Ѓ0 + Hu H}PH} fAF,f. Lm<G AFAF( G<,t< HW HHR< t<,tH}Ѓ0 Hu}H}PH} AF(jf. LmAFGLK LmAFGL3 LmAF GL LmAFGL LmAFGL LmAFGL LmAFGL LmAFGL LmAFGL LHu gH}IF@I9H}Zf. LmAFAFGL6f D AFlLmGL LmAFGL LmAF GL LmAFGL AF IV`Iv\H}LmH}fAF IVhIvdH}LmAFdtHU1H5* E H= i E @ DAFp @ LmAFAFGL&f D LmAFGL AF 1} @ AFf D AFf D AFAvLQT1;LLpL} AF8 1 Hi Hi IF0IxAxsH}AF8 A@EIAF8 A@E.AF8 A@E-ff. UHHdH%( HE1HEdH+%( u H], UH g HAWAVLw0AUATSHHDGL(dL,%( LmIA IcHm H H6g HHDH4g L1 'AċC t M H.g L1&AċC uZLs(C HK AVH LPDK1s DC&AIcHUdH+%( He[A\A]A^A_]ÃtKptDCtHf L1 Z&A|fL LHSZ/D H HHHTf H Hi ʚ;I)1M&A)E+ D UHHdH%( HEFwH P HEdH+%( u*f. UHSHH dH%( HE1tHe H=e t*HEdH+%( u0H]He H=e 1HEdH+%( uH]f*f D UHHdH%( HEHH Htx tHEdH+%( u 1 HSn HH0V)ff. @ UHHdH%( HUHWff. H H H H1H9rHEdH+%( uH)f. UHHHH dH%( HEHGu*$| H( 1HUdH+%( u $) @ UHHdH%( HE1HEdH+%( u E1E1( D UHHdH%( HE1HEdH+%( uMA w(f UHAWIAVAUATASHdH<%( H}ȿ0 KH A D IIL'oHtPDIE H(\(HMuHM}HEe(HIUHEdH+%( u)HL[A\A]A^A_]Lf. E1'f D UHHdH%( HE1HEdH+%( u H\u' UHHdH%( HE1HEdH+%( u H]X' UHAUATSH(dH%( HE1H HGIE1H @ I$J4Ht{H HVHHtDfo2 )U HSfo2 LMHHSHHHtHffo 2 H)]foMHL MID$II9kID$ L!IHEdH+%( u,H(L[A\A]]IHEdH+%( u H([A\A]]*&f. UHAWAVAUAATISH(HOdL4%( LuIHu\HEnEiGa A+L$(AJHIHtLrL0IFHEdH+%( H(1[A\A]A^A_] HG HPHHW H9sHWH E1ff. J4H H HVHHtDfo<1 )U HSfo$1 L)LHHSHHHtHffo 0 H)]foMHL KIT$I$II9gID$ $ @ UHHdH%( HE1HteiGa +O(HH4 D H;Vt HHuHEdH+%( u*[K HVHHtHPfo00 1"$f UHHdH%( HE1Ht>iGaH +O(HHu fH Ht9puHUdH+%( u1#f UfHnflHHdH%( HE1G HEdH+%( ul#ff. UHAVAUATSHdH %( H]H L#H9tBIfHCfHnH{PMflID$L AmEHLM$$M9uHEdH+%( u H[A\A]A^]"f UHAWAVAUL- J ATISHH(dH%( HE1> f D X EIHt fHnfl LJIGPIH LH>IALu0 x LLm>LIMwLZHR L8 HEt HMwHEH5 Lep 7 fAGHEIW LIw8HHEAƅ I tH}Iw0 Aƅ LuLL=IA>/s LL=H\ IA>@tpLH=fHnIHCM+wPL{MfHnflAL8CA<$ E1HEdH+%( H(D[A\A]A^A_] ILL=IALu0 fAMgPLeCIG( fIGH AGLDCLHMud H5 Lqdu AG H5[ LQdu AG _ H5d[ L1dY IfAGMw.fH}IIW(Iw@LLuDAƅ I( tH}Iw45Aƅ AGLu9 @ LL;HZ IHMwHL$XHIHZ A> A IAMgPF f D UHAWAVIAUATSH dL$%( LeL'L9 ff. I$8 LHXgE HH HEHU HhH1H5 D}Hq Eh IDŽ$8 LmLgHLÅ MA9 L}M9 HFn LPH`fI H I_HH Hn8IH HJ I~ iTLH BHm Iw H >*u ~ y LxEG0HhHLܺ HxA IG8 I@ Iw(H f D EG4HhLH芺 HjLrL`LX11H A6L9wA611H &wA611H wL HEdH+%( He؉[A\A]A^A_] Iw(LxH<HăL HH Ln M?M94LLP5qHXY H` I$8 HW 01UvM$$M9(16I(HoI_HHHHn x D LxAO4HhL Å HULxIw8JH9u H)IG@HIO(MH H`H? 0 H`HHw 101u] LxHEIw8LH9 H)IG@HGn x n ?*u H AO0HhLxL&Å HxA I(IG8t6I@ u/HHEIG@HMIN f HfH訁LPo9 H`IOHHF 011{t f D 1H H0 IG8 HIG@CL苴HHff. @ Lnf D LnHAn H` D HhfHH= HE )E)E+Å } t oEAG8 HEIG@H`1Hۻ 01rsJ D H`MO IO( Mt HHo 1V13sXZIH 11sH`1Hb 01rLmLmH@n H`LH`1H 01rL`mIHL@n 1EH@ 0H`1rL0mH`IOHHy 101^rHVLl$ @ UHHdH%( HEH HtLEdL+%( u H f D HEdH+%( u1 UHHdH%( HEH Ht3H@Ht*H Ht z uHUdH+%( uf D HEdH+%( uRf UHHdH%( HEH HtHUdH+%( u H@ D HEdH+%( u1 UHHdH%( HEH HtHUdH+%( u H@( D HEdH+%( uf. UHHdH%( HEH HtHUdH+%( u H@0 D HEdH+%( u:f. UHHdH%( HEH HtH@8HtHUdH+%( uHEdH+%( u1 UHAWAVAUIATSH(HDn ^dL$%( LeI8 u! H HcH> H1?n پ HP H81 LLEfEuDI HH9t5f. HL%M t H9 HL9uHEdH+%( EH([A\A]A^A_]LL@ELL{Em D LL=eEU D LLEE= D LL} E% D M'M9WE1HL%N<uL9tMLMDL*M$$M9uMt?I 6H I Hǃ A ǃ M E UHHdH%( HE1H\m HHUdH+%( uf UHHdH%( HE"w0Hn Hr8 uGt4 ff. HEdH+%( u UHfHSHDdH<%( H}HH AA A AY A E D@ D D 3 AA1 AA/ E1H9 DGHWHU x A LcI9 B< Z LcI9 B< ZtnLcI9 B< ZtOLcI9 B< Zt0LcI9 B< uH x u A EA A U L EOcM>A AAATH H@HGWHFOHEdH+%( H] AAAH] ҉WPWHD x ]+ f - D ALFb M DPMIA I AW I DPLH I A I DPLH I AX Iz DPLHHI A= IQ DPLHH!I A I( DPLHH(I As I pHHH/L ʃV I DHLHH6H A< I @ 5 f D H PAA AtX a' # { "U uHv7P HWHvx E g D `AADGD@A AD &H vH@HG DA WL IcL>HvPWP fW H4 f D WL IcL>H PWP fW Hf D WILr IcL>HPWP fW HS AYE A AH PW@G OWL IcL>H?PWP fW H @ HX H_H OHH@ HG -HP HWHtx HX H_H3rf HVP HWHuH6H@ HGNHX H_H D HH@ HGHP HWH @ HH@ HGHX H_H7v D H^P HWH M B 7 , b^&VL IcL>HH H PWPW HW HxH H@HG H h Hvx s H)H0/ (ff. ff. f s HH46HyH WHGH PWPW A DA HPm PHWHO PHWb!L IcL> Hx]xSxIx?x5x+x!x x x x x xx Ha PHWPD@ D WxH, P҉WP HWHWf DA DA DA C Sn 3 F HWH Lc LOI9sB< uZ6 뫺 뤺 PWPd N IHG HXH_Htx HWc HwH H=H H 9" PH@?WHE H P@UfEHEHGH PfWHP P WPHWzHG ?HG@ 2Hff. UHAWIAVAUATSHH(Lw?dL$%( LeI I" H5 HcH>f HL? AV HLL1 g|ZYHUdH+%( ~ He[A\A]A^A_] HEdH+%( Y HeLLL[He A\1A]A^A_]8 {eHEdH+%( L? HeLL [HA\1A]A^A_]{ @ HEdH+%( L@? @ HEdH+%( L? @ HL AVCP1!PHLL1 ={H @ MDL> IAPARHCMLt> IPARt @ HLx> AV^f D LL HPLH PLHPAVSf LHL H PAPAV(f D AVCL= P CL= PAVf D 1L LLH zDKHMII)E~I1fMHx MxHH LL1 MmDKHMII)A9 1LLL= HyB D)I%f. AVCL@= Pf D AVCLB= Pf D sH tH AVL< P @ LL~ HPDPLHPAV D HLq< AVfCL< PAVT f. D U@HHdH%( HE1H(n HUdH+%( uA U@HHdH%( HE1 DHUdH+%( u UHHH /-n dH%( HE1HHHHt@@ tuHUdH+%( u# D HcHHHt 1off. @ UAHHH5Z'n dH%( HEЉ% IIJ Ht tEu HUdH+%( u D IcHHHtڋ f D UHHdH%( HE1@ wGwB@H )n HHHHt'@ uu HUdH+%( u# @ 1 @ HHHtFf D UIHALHHdH%( HE1HG HH)pH IpX9IphOEHSA@PHcHAIP`A@QHEdH+%( u D UHAWAVAUATSHDdH%( HE1Et*1HUdH+%( H[A\A]A^A_]f D HGhHW`HHHH9P 8Q HHH9D x : HHH9- xx# HHH9 xe HHH9 xn HKhHHICH H9 8E1AB P vSR fusPAHChCHPHShHPH9S` xEA P EEt3D:#tAt(D:ctAt D:ctAtD8ctA IcD$ l{S CQ CQ\ f8 HHH9x HHH9xkHHH9xvHHH9xm @ CQEEtCD8t Dc{S HSh HBH9C`DD*DEHSh t?uTDkHJH9K`BC HKhC tCPC CCXHADkC HShtCPC HBH9C`:A3 PwHShHs`LBL9{SJ@t$DcKt+tpCKLChkAAAZHBH9BBHJCH9.BCHKhC@ CPHJH9BCHKhC@D:#uAiD8cuCAVD8cLCD UHAUATSHdH%( HE1 t*1HUdH+%( H[A\A]]f. HuHShHBH9C`j D"{ HChC Dc C SC ƃDk EA@AACL t{v{ x A| @ t{ # { CL C fHS`{ uH{ DCL`u&1 {@uSLAKMCL` HShHBH9C`rJD"HChC PS Dd{ t st{t@s@ H f D Ff D u @ s { x"D CLfH { At|subCuzDDcLCL CP{ A7 ` zCL |{t)s@H)w ws UHATSHdH%( HE1$ t$1HUdH+%( H[A\]f D H\uҋCLĀt)HKhHQH9S` D!HShC%Dc u{S t CNtCPC$ D { tjsu;CuuSLD { CLtWStCNu1CLA {tLs@ D f D Hf D HN {sX UHSHdH%( HE1S u 1HUdH+%( u0H] HX&uր{% tC < UHSHdH%( HE1, t 1HUdH+%( uuH] H%u{% t {QtC t <t C,f. HChHPH9S`r HShC-C(Ҹ|3 UHSHdH%( HE14 t 1HUdH+%( H] HNu{% t^S <tR<t^<@ƀ{QtjC(<u @t HShHBH9C`rqHChC5S0 @ C4i HChHPH9S`rB HShC5C0f@utHChHPH9S`r HShC5C0 UHSHdH%( HE1< t 1HUdH+%( & H] Hu؋CL u"ptUH HcH> @ CQ< < <uPHChHPH9S`rB HShC=C8CDC<i SPJ t!t\ff. :f D HKhHQH9S`r HShC=K8 tHChHPH9S`r HShCEC@HShHJH9K`rHKhC=S8fHShHK`HrH9{:HshHrC={8H9aRHshCES@yf D HShHJH9K`6HKhC=S8N SPl ! HShHJH9K`HKhC=S8CDC< @ SP H{hHs`HOH9?{8HyHKhS=H9H{hC<S@ fSDHShHBH9C`^HChC=S8 @ HChHS`HHH930HKhHHC=s8H9@HKhCEC@H{hHs`HOH9?FHShHK`HrH9:HshHrC={8H9RHshCES@HKhHQH9S` HShC=K8ff. UHSHdH%( HE1R t HUdH+%( u(H]f HuHShH+SXSRBf UHSHdH %( H]Ht^HH%u { uHUdH+%( u3H]Ð{$ t߀{, tـ{4 tӀ{< uf D 1HVff. @ UHAVAUL`IATISHĀdH %( H]H1Ʌ҉HLB$ EI9 d C C pu5x< <ov"Pv H f HcH>f UH S H<wCHSsZ f1HUdH+%( K H[A\A]A^]f D Ao$C @ LL I $H HKILHHLH)I)ԃr1҉уI4 H4 9rs A $K`ALfLPMH fnHHfnMfbfC D <3 HC UHHЉS f H UHHЉS H UHHЉS H UHHЉS x H uHfnH>H }HfnH$H UHHЉS $H }HfnHd UmH H S U UHf D uyH4 wm ugU vUH s H[f. hf D A $KALLK 5tWH s L8 H A S H H s HHU s HuctuH5 s HH+ s H[ff. UHH0dH %( HMHM~¸x U1HUdH+%( u UHAWAVL5& AUIATALSDHH OHPdL<%( L}M=xyED9pMtALsE1} CinsnA AFn: tAf D GL% HcIc1LL H aIEA)D9HEdH+%( uHĈ L[A\A]A^A_] ff. UHHdH%( HE1Hn HHUdH+%( uf UHAVAUATSHHGdL$%( LeIԃvrP1wIDwHj L-O ?ELO(RAV LAUIHHL % 1`ZYHUdH+%( uIHe[A\A]A^] ?QHHEdH+%( u HeLH1[HI A\A]A^]Wf UHHdH%( HE1 w HV HUdH+%( uf. UHHdH%( HE1' HEdH+%( u1X UHAWAVAUIATSHdL4%( LuIH?Ht^IHtVI^IFI I^H9rIF 1AFI>H)LL9IGHHIIFHIFI)uHEdH+%( uHL[A\A]A^A_]ff. UHAUATSH8dH %( H]H n ; H=o t$1HUdH+%( He[A\A]] @ =o Hn L L%o M =vo tf=fo HHE )EL-$o HEHIH=o )o HE3foEH L%o Ho H5_ L$foED$/H HtMHo f H5ci H=o =HIL%o M9 8L1Ho D UHHdH%( HEHo HUdH+%( uf. UHHdH%( HEHXn @=%o 5o HEdH+%( uf. UHHdH<%( H}H=o HtVHn HEdH+%( uFf D U HHdH4%( HuHH=o HHEdH+%( uɺ H5! f. UHHdH%( HE1H=o H=0o H o H= L=߾o H o H5ɾo H=o uP L H o H= iLo Ho HEdH+%( fHao HH)uOff. @ HHt6? uHpH KH 8o H5!o H= o U D 1 KH5o H o H=߽o Hu% D HH? uHH kff. UHAWIAVAUIATASH dH %( H]Ht&HEdH+%( H [A\A]A^A_]ÐH=yo L HD E McL5Q Iff. @ H=6o L1 HcI9uA+H ~ H o HAJAuH5o H %(HL :Hپ 1H=o H< E1f D UHAWAVAUIATSHHDw dL<%( L}IOt+HEdH+%( o HH[A\A]A^A_]f Ic A H9H]HFHEÐH5 o O'AuH=o 1LH E HEM}L%ê Mtff. AH=o L1 IM9uH}w7L% ff. @ LH Yo HuH5Ho H]&L HH=#o ~ HH 1I @ H H= Hf1ST @ UHAUIATSH8dL$%( LeIt#HEdH+%( H8[A\A]] D ff. H5io %uL 1 H=Do H L% qH )o LGuH5 o H]M%L HH=o ~"HHg 1 $ H H= GG ff. f UHAVAUATISH H8H@HHLPLXt&)`)p)U)])e)m)u)}dL,%( L(L-+ n A} tPH o HtpHEL HHHH0Dž Dž0 H |/H(dH+%( & He[A\A]A^]f =o Hn HH ro H =No \f=:o H{HDž )L5o HHH=o )o HJ*foH H o Ho H5$ L$fo D$p&H HHtIHo H5#` H=o >HH o H!AE L1Hjo UfHAUATASHH8L-Z n dH%( HE1HE A} )ELJH )EubHs(H}u5HUH HUH H HuȀ}Hx u4Eu/HUdH+%( H8[A\A]]ÐH= VfHEA} HǃP ǃ Hǃ` ƃ$ Hp HCxƃ/ uA} uuH=T 1vVH=6 hVUHATSH HHHPHXL`Lht#)p)M)U)])e)m)u)}dH%( H81H0HEIH L HH@ Dž H(L% Dž 0 HL Hn H81~HOn 8 u"H8dH+%( u H [A\] @ HL1CU|ff. UHAUATSHdH %( H]H( L( P HcH H H H@ HH)H H u;Hp H Hx H Hǃp H Hǃx H L≃ 8ML-In fnȉfpAE fփH u=( @1ff. HUdH+%( H[A\A]]fH H@ L( 1f H8uH H .H ƃ$ ǃ HH u c H H@ Le tA} tH=O 1VSff. @ UHAWAVAUATSH(H n dL$%( LeI8 I$ HtvL5 M$ LHLGH A Iff. L9rLLLL)@tnIuI$@ IDŽ$ M$p M4 I$x M$ L5{ IDŽ$p I$ IDŽ$x L I$p I$@ DIDŽ$ H I$x I$ IDŽ$p I$ IDŽ$x A A)McL9K4>LH}?H}fo L)I$ I$x LM)$@ I$p I$ IDŽ$ A$ _H=X 1LQ81Lu I$ M$ L59 *HUdH+%( uiH([A\A]A^A_]1LD}QuI$ I$ UL)A$H HEdH+%( uH(L[A\A]A^A_]uUHATSHH H0 dH %( H]HH Ƈ% Hʀ# H tH ƃ H x uNT H fH*Yh Hy@HfHH H*X.f D H fH*Yp HxfH*X f/ H,L%vn H` A$H9s} Hǃ0 HEdH+%( H[A\]f D HуfHH H*Xdf. HуfHH H*XfH` Hǃ0 tHEdH+%( uWHHH= 1[H5 A\]N \H,H? D 1H={ NH` A$ff. @ UHHdH%( HE # H0 , D % uƇ A!AD)AщHh EH H) D AH)Hm H HLJ 8 Ƈ$ Ƈ& t/HEdH+%( DD1H=${ M HEdH+%( S ( 1H` L Ƈ I9L) fH*H Y H fH*X f/| H,H9 H f D 1DD HIH)H1IHH) @ n~ ` S D \H,H?v D IɃfII I*X8fIɃfII I*X]ff. fUHHLdH4%( HuHH(F w) H" HcH> P H t Hr$t? HFHff. @ 1HUdH+%( K f HFW9t} A` GfɉH*^G8 2 uRH HG(H!H NH9s H H~$ WH H f. Hf D 0 6A LNW _ 1 U A G1 A)DD! ʉW D9 A D)A HGDO HGHO E Et&1E IIH1IMIIJ H;O(0~$ HO(m D 2 E ENHVA v A# HO W A H) 1A IHH)H1HIH)HO HG fO0f. )҉W A A )D9f HH @ fHnflG ~f D AT Ah WG8 H)Q D I+` S fH*H! fH*^O8H`m f/vf(^f/W ' Aƀx Ap HvH=ev ;Hff D HWI+` x~fH*HxPfH*^Hm Aƀx 8 Ap HvH=Ov G HfHH H*X D HʃfHH H*XmfHfHH H*XfHʃfHH H*XjHvH=t %GP[ff. UHAWAVAUIATSHH(" dL4%( LuIHE uƇ" E1F LK(HuMLHP LS~Uo o0 Afoflff0 taH2m ǃ\ ǃ 8 AADEHEdH+%( H(D[A\A]A^A_] D M MGfH~I9 E}EH AE C * Eu A ǃ\ AE D AoE U I H0 H` H H tkH!A H9H9snL r L9P Eu AP @ L L+ M4f. HH!H9sH ƃ H H)I @ HP H5rs H= 1DR Eu AuAUtJH IcHP Hl Hc B V HLxf D AU\ DHcҍA\ HP HfHnfHnHP flC@tP/ ;X s H;@ f d u%` H@ fnfpfփ` @ A D HP IcE C0 A HCH IHHS@HP f. tEu0H fH~H` H# H9 H f D K0" Hǃ H H Hǃ H01HH v @ H H@ H` f D H tG HHDH H9m 8 uoǃ A Ht.HH H tXbH E} Hu1f H H H5: H=& 1AEu sH H묿 HuHMHMHuHAU1HATSHuH@dH %( H]HZ HX 3 2 Չȃ2 8tK0 @ fK63 Eă HcELceHP IHCIfInfl)EH v Hs(LfoEY K0 ƃ# ƃ ǃ LP C@1HUdH+%( H@[A\] HCHt҃ uC0tHs(H{HЄtHX K0 ǃ\ 2 12 ƃ# ƃ ǃ sf D , HP tBǃ HS@uHCH 16HH HCHHP 1 HS@1ƃ# ƃ ǃ tHH HP K0 1HSHHP H(m 8 u;ǃ Hm 8 u+ǃ H5n H=I 1>H=_ 1>$ @ UHSHHHw0dH%( HE1HLJ f W0to fnL E1fnP fD C0 fb@ H H ǃ fփ t)3 K0 @ ƃ fC6ă3 Љ t3C0 ƃ A A@ ADC0 t"K0H ƃ H tK0H ƃ H tK0 H ƃ H Ȁ trC0 ƃ @C0tgƃ C0@tƃ HP HCH HC@ HEdH+%( H] t<C0 @tƃ f# S0 D @w ƃ j# c ) C0 C0HP ƃ# HC@ HCHA @ ! HE (# ) H;H " uƃ" H0 H` H H H!H9r%H9 H ff. H1LK(HuH}HP A S]EHP Hm 8 ;H5Oj H=W 1 ;! @ s0 H H ǃ fփ D ǃ fH H+ )HH!H9H ƃ H H)~Eo o0 flff0 tBu&H fH~H` H# H9s+H HcẼK0HHP Hǃ H H ff. UHAVAUL- ATLeSH0dL4%( LuIIH ff. @ HLLbG A8 t6~ AƆ HUdH+%( C H0[A\A]A^]f D AƆ uE Hm tIuAdž e D L18 @ Et8Hm AƆ u Adž M IP HcEHH9t-AƆ HFm 8 tH5g H= 1T8fA LAdž @@Jt,t(1IP H5g H=M 17R+IP jff. @ U H HAWAVAUATSHHHHuLLdL$%( LeL'LY,HtTIL)E I)tBLmLe UtPt#HII)tLLLL/ @ 1HUdH+%( HH[A\A]A^A_] @ H HSII!L eI9rKH LLH)H9LBHm 8 uMHM L;!sHCHAzf. H HL)H9sH I @ LH=&f 1g6蠺UHAWAVAUATSH H0 dL4%( LuI ~A& )9ލ CA I I I / HHI` H9 L-m A} & A% A# AƆ tvI H9sjHH) fH*AY I H4 fH*X 7 f/ H,I9 sI AP A Idž0 A} HEdH+%( HĨ [A\A]A^A_]I` L-m Hf. A 1E HIH 0H1IHH4 AƆ& )! 9 )A #f HEdH+%( HĨ H57 H=B 1[A\A]A^A_]3 Ih HM]HxI@ HEA$ Ao M I EA& I AƆx EA Idž LIcH HE HE IHUEHE LPpDžt Hh)EH)%HPLLH0HXH8BXpt"H0u<XtpHHhIH)tH8LHLi+I` f H=qb 12I` f D A )YHȃfHH H*Xf\H,H? D HfHH H*XE D UHAVAUATSHHp dH %( H]HƇ$ H H HH!H 0 H9 HHH)H H9HBfHnP Hǃp flL-Fm Hǃ0 ` uvA} H Hǃ ƃx t]HEdH+%( HH5D H=O 1[A\A]A^]1f D H` Hu<L-m P tA} uHEdH+%( H[A\A]A^] D I L-m I!L 0 Lh I9s%H AM L)H9 IԀ, t9L;x s LL; s'H uHH= H 1LH` Hǃ0 #H H)H9jH HX Hx I MHt'I9r" , tI[f uL, Lh L^M D LH5_ H= 1`/H` @ LH5 H=y 18/f D LH5 H=Y 1/H` RG UHAWAVL59 AUATSHdH %( H]Hƃ( ( L( L P HcH H H H@ HH)H H u;Hp H Hx H Hǃp H Hǃx LL≃ &L=m fn؉fpA~ fփH u*( C"-IcL>f D H H@ L貞( 뾐Hu<H H NH ƃ$ ǃ HH u5ƃ( HUdH+%( K H[A\A]A^A_] H@ H L tA? tH= 1, D A? ƃ$ W uA? 0 X ǃ Hǃ0 ǃ ƃ# ǃ HP f1 HC@1f 4 HǃP 3 Hǃ H0 HX ʈf1 mH0 H( ;T Pf` T *H` # Hǃ f(H ^^h % ~ fHnfl H( , ƃ# HH L H5 Hc H>ျ$ tH( aK0X0 D, H0 | 3 4 S6S7HH( H( 1;H= 1*H=S 1*H0 HH ƃ' Hh H H!H 0 H0 H/sH H H H!H 0 f1H 0 1>ff. UHAWAVAUATSH dH %( H]H tǃ ( L( L L5x P fHcH H H H@ HH)H H u;Hp H Hx H Hǃp H Hǃx LL≃ !L=m fn؉fpA fփH u*( C" IcL>f D H H@ L肙( 뾐HutH H NH0 fHnƃ' flH K0 % HCHu~ ` X Јf1 1HUdH+%( H[A\A]A^A_]f D H ƃ$ ǃ HH u f D H@ H L} tA? tH=h 1o' D A? ǃ ǃH @HP , HC@1 HH H HcH>A? ƃ# , HC@ 1HH O H \ HcH>H( H0 H( ;T f` T *H` # Hǃ f(H ^^h % ~ fHnfl $ tH( \K0SHP , HC@1x HH ; H ] HcH>, H0 | 4 H0 HX A? X ǃ Hǃ0 ǃ ƃ# ǃ HP f1 HC@1f 4 HǃP 3 Hǃ A? ǃ H0 fHnƃ' flH HCHHX K0 2 12 ƃ# ƃ fH0 fHnƃ' flH 3 HCHHX Ո2 ȃ2 8K0 @ 1fK63 H=d 1# HP H= 1#H= 1#aH= 1#MH H!H 0 8H0 H/&H H H H!H 0 f1H 0 H H!H 0 |H0 H/jH H XH H!H 0 ?f1H 0 0H H!H 0 iH0 H/WH H EH H!H 0 ,f1H 0 111袦fUHAWAVL5! AUATSHdH %( H]Hƃ( ( L( L P HcH H H H@ HH)H H u;Hp H Hx H Hǃp H Hǃx LL≃ LL=]m fn؉fpA~ fփH u*( C"-IcL>f D H H@ L( 뾐Hhu@H H NH ƃ$ ǃ HH ƃ( HUdH+%( ` H[A\A]A^A_]ƃ @ A? ƃ# ƃ ǃ A? ƃ$ u|HP t^ǃ x @ H@ H L FA? <H= 1 )ǃ H= 1 qH= 1 2H( H ( uA? X ǃ Hǃ0 ǃ ƃ# ǃ HP f1 HC@1f 4 HǃP 3 Hǃ =A? ǃ , H0 | 3 4 S6S70 $ tH)( a, ƃ# L' L -HP H0 fHnƃ' flHh H HA? 1H53 H=5 ( H@( H0 H( ;T f` # T Hǃ *f(^^h ~` f֓ A% 4~ fl H0 HX ʈf1 1LHP HH w}H=R Hc H>H H!H 0 HP H0 H/~H H lH H!H 0 Sf1H 0 D1=f H=M 1b H= 1O S腠 D UHAWAVAUATSH + dH %( H]H Le f D ` }f E ! < H@ HP P < HcEHF HC0a ƃ HP H + H@ uW1LHJQE+ 1HUdH+%( ? HĈ [A\A]A^A_]Ë< H@ @ ƃ+ )H艍`HhHm 8 fnH HpfnP H@ \H`L HEHcH fbL fEHIHUI) L\Lxg @ H HrBuzLULM@ D|A2IzD9DND)IDHI D)MJA2t=UHHEII)t,LLLL~xEtσ"q` HP C0 HCH HS@HhH Yf D ƃ+ G @ ~P H fofHnflH H@ H < HP K@W< H H@ @ H( , HH H > HcH> @ Hm 8 ǃ O @ H` H H0 H8 H HC` EHHs@HH@ HHP HCHfHC0 H@ Hs@HCH HP ~0 ff. @ HX 3 ƃ' ~P 2 Չflȃfl2 K@H 8YK0 @ fK63 CH H!H 0 fHn|~0 fH~H/dH fH~H fHnHH H!H 0 fHn*f1H 0 fHnf H=2 1H=P 1/Hm 8 ǃ ǃH dHzm 8 ǃ H^m 8 tfH~H5F H= 1gH6m 8 tfH~H5F H= 1?HP H5G H=o 1!UfH~H5F H=F 1Z.ff. UHAWAVA AUEL-Z IATL SH( H H@ dH%( HEȋ( ƅ AP A( I@ IcH I I HHH)I@ I I u;Ip H$ Ix I Idžp I Idžx A LHA fn؉Hm fp fAֆH 2I I@ H茅A( I tA tA tAƆ AA) " IcT L>A# AƆ Ao( AH ff. I@ z @ LXuBI I H AƆ$ Adž IH HUdH+%( H [A\A]A^A_] D A* t A( t H HcH> I@ AƆ' LIdžh I IdžH MUIh AF0 H AF0 IP I I@ H߾ 譃A Hm 8 H= 1LCA( AX A, AƆ# IH Mt H5 Hc H>AX A, IH M/ H5m Hc H>A, IH Mv H V HcH>Hm M8 ALJ LA( I@ I@ fA! Idžh HDž@ I )0 I AƆ' IdžH Idžh Ht7ff. HI I X #I HuAdž L] MIh AG0 IGH IG@1Ao( LAH NA( H 7m 9 I@ 1H5 H= :A( I0 I( AT 9t~fA# A` AT Idž *f(^^Ah A~` fA֎ A t A% uA~ flA A9X wAF0 1 1AƆ fA# I@ Adž I0 IX I@ Hm M8 AX 1ALJ ILJ0 ALJ AƇ# IP ALJ fA1 IG@A4 ILJP A3 fA ILJ IP AF0 IFH IF@I0 I 1IP AF0@ IFH IF@1L vA( H m 9 |I@ 1H5P? H=8 A( TI0 LI 蚸A( H m 9 I@ 1H5> H= A( I0 AƆ I I@ A I0 I I@ AƆ IP AF0 IFH IF@I0 I 1FA H fI0 E )EHUH )E)EA E HUE )E ʋTA x HcA MH .m 9 =1H== ? A( I@ @ A A, p g LcMH4CtH=m ? LC HI0 HT I I@ (A% AƆ# AƆ uA~ A` A AX ʈA, fA1 . H )m I@ 9 1H5 H=x , A( I@ LA( I@ tAF0 IP MIG@1IGH 'LQA( I@ 4A, I0 LA| A4 cA( AƆ ƅ A# I0 A( LH{A( H H m 9 A0 A dA$ tL~A A( I@ 3A, M IH 6 H D HcH>A, M{ IH H - HcH>A, 8Ao( LAdž A8 Kdf D LسNA( H m 9 TI@ 1H5O H= A( ,A, _ H zm I@ 1H5 H= uƅ A( I@ Ic I@ ? qA, HA I0 L H I0 IH AƇ' ALJ HEdH+%( uIH L[A\A]A^A_]:I0 IH AƇ' ALJ HEdH+%( tՋ D I HHxʈI@ fA1 A( IH H HcH>A I LPfAnH I fAnP ,H0HxIcH fbfօpHHHhH) H,HHH HXHLIff. H HLH'~ZXpf Lx"w9 q H HHU 0 + HL@ fo0IH MA( A, . A, H HcH>Adž H tm 9 1H=7 A( I@ AƆ ƅ H=6 1K,A" hI` AƆ" RIP 1AF0 I~HIF@1PfA, A rAƆ sAƆ ffAƆ A A AƆ 8H sm 9 A H=D6 1}I0 fHnAƇ' fA flAH AG0 LIG@IGH H1oH H!I 0 I0 H/s H H A3 fHnIG@A2 flAƇ' AG0 IGH AH 8AG0@ 1fAO6A3 H H!I 0 f1I 0 qI0 fHnIGH1flAO0 AƇ' IG@ A2 AH mH H!I 0 I0 H/sH H H H!I 0 yf1I 0 jf1I 0 DI0 H H!I 0 I0 H/ H H H H!I 0 1I0 A! IH AƆ' m A# _ A Adž L,1HEdH+%( 6H L[A\A]A^A_] H H!I 0 RI0 H/@H H .H H!I 0 f1I 0 H H!I 0 &H H!I 0 VI0 H/DH H 2H H!I 0 f1I 0 11eI0 H/H H H H!I 0 vf1I 0 g1`1 1I0 IH AƇ' ALJ I9P tLlqI ALJ ILJH ILJh AƇ' Ht)HI I Z tI HuALJ LALJ H H!I 0 %I0 H/H H H H!I 0 f1I 0 EXEAx D\EoXA@A tHHhHI)Sf D w HLEHEA@ H= 1I HHvA! A# 1LQAO0L4jIH sALJ 1MAx A@ APAPAPIP Lž fAƆ A I@ 1H5_. H= KA( 9Adž Llqƅ A( I@ A 1H=. LL L A( LCʃA I@ 1: L褽1IP AF0 IFH IF@1I H%m 8 H5 H=} 1/A3 MŃ8tAN0 @ fAv6A3 IH wH HcH>1fHnAO0 A) flAƇ' IG@ IGHAH 1I0 뵺 H0H!I 0 I0 H/s H0H 넺H H!I 0 lf1I 0 ]f. UHATSHdH%( HE1H? H I ġHH AoD$Ao $ @ID$ A~D$8AL$TAt$PHC ID$(flHC(AD$0f AD$h) * AD$2 ff, AD$lH*DIT$@X AD$dH 8 ID$H\ HHH HE` H AL$X A~D$\fփ f~uHǃ L%m ǃ A<$ HEdH+%( K HH[A\] fpf~օt1u H 1 @ HHuHHHH H . 1wf 1H=ڼ A<$ S 1H=* A<$ 4 1H=* A<$ 1H= A<$ 1H= ) A<$ H=* 1^f H |ff. @ UHHdH%( HE1H HEdH+%( u8| UHSHdH %( H]HH Ht, HH H tTkH Huǃ H |H pHEdH+%( u#HH]k D H HtH{f UHcǍHHHdH<%( H}HH5: w H +;m H4RHEdH+%( u1*{f. UHAWAVAUATL%9 SH H dL,%( LmIf. A AE0 ADž A HcH>f D Lдtb AU0ց ! # % $ t1҃ AU8IP AX M0 IE@K A2 A~ M8 I` fAM`fA֍ I AT I L8LAƅ' fAH A4 E1A! ADž fE A3 IDž L=m A? ff. @ L踟A( wA( IcL>I fAƅ# Aƅ Aƅ' IDžh AH Ht3f. HI I H hI HuADž LA, R I` Aƅ( u IDž` AE0 AT ADž AE8 A;X I` A I I0 I8 I IE` A I Aƅ fA( )p)E)E)E)E A( I( M ff. AP f IcH I I I@ HH)I I u;Ip H^ Ix I IDžp I IDžx A LHA jL={m fn؉fpA$ fAօH A( 9 H= Hc H>IP AE0 ADž IE@IEH AE8 AT A9X )AM0AX : A AM0I( I A% uA A1 Au0A~ I8 HIh HI fA}4A1 IuhtA\ t H1HA~ HflIEpIE0AEPHUdH+%( H [A\A]A^A_]L<L L uLhIH I9P tLGI ADž IDžH IDžh Aƅ' Ht+fHI I X dI HuADž L4$ Ih AE0 IEH IE@A 1AU8AT A;X A( Aƅ# D I@ I H`A( h* Ln I I D Hm Aƅ$ ADž IH ucAU0 AE8 $f. I HH I HHx I I@ H_A sA? iH= 1VHjm 18 b ADž AE8 i ADž AE0 )ADž A% Aƅ# uA~ A` A A, " A' ' I0 fHnAƅ' flAH A? # IP E1AX ADž IDž0 AU0IE@A4 ADž IDžP Aƅ# ADž IDž fE E1A3 1 AE8 :A? n ADž Au0 LSA, Aƅ Aƅ# A' I0 fHnAƅ' flAH I0 IX ЈfA1 w1Aƅ ADž fA# UI0 I( A;T 7fA# A` AT IDž *f(^^Ah A~` fA֍ A A% A~ flA I@ I IDžh IDžH I Aƅ' Ht/f D HI I _I HuADž LIh IP AE0 IEH IE@H A A0 A A, I0 A| A3 A4 AE6AE7A, Aƅ# Q A' 1 IH H HcH>A$ QLٳDL講7L *A, A' IH H B HcH>Aƅ' LADž aYIh IP AE0 IEH IE@A) ADž AT AE8 A;X PtA A, I M0 H I}(H9Ƹ L(HDAU A# L( AX H L@ MI` H M)HI!H H!I I9 H L)H9s H IA? < M; r M;x r$I uHH= I 1ܑA- M0 I Lp I0 A A I Aƅ( A# I Dž8 fAnH 4H8fAnP HhI@ IcH fbƅ< L@fօ`HHHXH) H4L(LHH IHLI5f D HsZ). dHHXIH) LLHL H`tHh v L(H AL<A# 8t A? - A( @Aƅ0 3A( a } Q } I H I}(H9Ƹ HDAU HI` HuIx H II!M 0 I9 H L)H9s H II HHb UL]HEHUDHHH )HHHA H HHHHA? H( H(LH)H E DxA H" HqHQ HtyH A( toA. E/ % EtRH H9 Hy HH= A(1DH;HDHQ H, y) 8 I0 H(H HL)HH!A- I0 A? E1 I0 IX 1Aƅ0 fA# I0 I( A;T fA# A` AT IDž *f(^^Ah A~` fA֍ A AA% 3A~ flA Aƅ( E I fHpfAnP )EM I HMI )EHMA HhIcH 8I@ )pI)EH)EfAnH L@fbHXfօ`H) LHH8H(LL MIIff. fLLLH ~RH`t0JLhw2H= Hc H>AA0 D dHHXHI)uH(L EUtuH=, 1}UA( A( I0 H H9jI ^LA( JA$ <LA( (LA( Aƅ# Aƅ0 IP H-A) A? A IE@ IUH AE8 AT A;X AM0AX IP IEH Iu@oHAA1AkH(L AA4EUxoHAA2AA4oHAA3AA I HHH=P 1"A( L(H L<%I )EHpfAnP )EM M HUI HhIcH HUA )pIlj8I@ )E)EHfAnH L@fbHXfօ`I)! LHH8L(MH ǻ MMIf D LLLL~RH`t0JHhw2Hc H>F0ff. fdHHXII)uL(UEtK A( oHF3F oHF1L(UF4EoHF2FuH= 1Au0 ADž AU0 AE8 IP H IP HJ Hu]H= 1H=q 1 Aƅ# A? 1H= TA# 1H5o H=q 2A LLH)H H9LB-I fHpfAnP )EI M HUI )EHUA HhIcH 8I@ )pH)EH)EfAnH E fbL@HXfօ`I) H8L(LHH IHLMLLLH H`tlHh tT tOL(H LuoHF3F A# VIX EHx?nHtdHHXHI)UL(H LE( E H HO H\ H HQ H1HH(AI9@A M HqH~H~y(A@uA"( AO I0 HH)H H!A- I0 A? t E!E. A 1H1E HIH1IMHLA( 0 } Aƅ. M; r M;x r0Ht HQ H H=# 1謃H= 1蜃LA# Aƅ/ A( A0 IH a H HcH>IH @ H HcH>H1H5S LH= HiA? HL1DH5 H= 9A? HH 1H5 H=ѝ A? HH1H5 H= H A? H ~1H5 H= A? H RH 1H5[ H=u HxA? H H1H5' H=Y KA? H1H5 H=J HA? HA H HHH5 1H H= A? H tH(H5 H=ڜ 1H LI9 M; ~ M;x q Aƅ. ix+ Ht HQ H H=' 17H=t ǀEI0 fHnAƅ' flAH ADž I0 H/H Aƅ' H fHnflAH AE0AE0I0 H/H Aƅ' H fHnflAH AE0fAH _H H!I 0 H I0 H/ H Aƅ' H fHnflAH H H!I 0 Hf1I 0 HH H!I 0 HH H!I 0 Hf1I 0 HH H!I 0 HH H!I 0 Hgf1I 0 HUM Aƅ. $H= H(~H(Ht1HqHQ HcI9rM; r M;x YI GHH=* I 1C~)I0 L H=1 1H xAA0 I PA3 Py(Af 3HqH= 1H}HA)1;1E 1EH 1A IHH1HHIHM; r M;x >HqH HE1I0 HH)H H!A- I0 A? ]HALA H= I0 H198HALA H= D I0 D(H1D D(IM; r M;x HI uHH=5 I 1N|M` fLLH)H H9LB(&0H HcH> RI0 HH)H H!A- I0 A? HALA H= I0 H1A0 I PA3 P,WH= k{8A(5Hy A()DAA0 t4 A. E/ u9E!U11҃T;D뗺 ,HHLL1H= M0 AX K E1d1H=, ~zI0 H(H HL)HH!A- I0 tuA? -I0 L H=2 1H yA0 I PA3 PA0 I PA3 PA0 I PA3 Pk @ UHAWAVIAUIH ATILSHLO|% HxEDELMEdH %( HMȹ H HLIH dHHtlLLL)H)HL)HuH)À} I HL9siHHf D HL)I)L9sJIt$Hx IHA HuHEdH+%( HxL[A\A]A^A_] HLLLHH MtIt$H{ Hؐ HtHH)HI)f HvIHSIHf H)HD HאH.L9huL9puHME HH)LmLuI)tgH]LLpIHx# U t HIH)tLLHLHxHMHHBIIHIH L)Hd LHNH9XuL9huLIL)LIE LmLuI)HULHx& Uu HIH)LLHL HEIT$HH I9@88= y@8xI x@8y2 x@8y x@8y( y@8xuIM8HTLxKLxBHEHMILpHELxHEHpLh E H HM Utht#HIH)tLLHL @ H]I H HsHtNHL)IH)H]Hvf D HEHMH9tSH9s.H)H H9r} uQIH HH)H H9g D HxH9PIHEHpLh HEIDH)IJD!A8AO8H HA8O AO8H AO8Hu~AO8Huk@A8GuXIHUHEIHxHEI=IaLxXLxOLxFLx=NI/I&I II If UHAWAVAUIATSHhHxdH%( HE1H{m HE Hu8 I}(HUH5AU HUH I H M H HLPIHthH)MLEMI)ME MtIL}LELeH]MM U t HII)tLHLL1HUdH+%( Hh[A\A]A^A_] @ I Ix IDžp I IDžx I9x I I@ Ip IDž Hu Lpt cHU Ix LEH H!H uH9 H H)HH HH9HCHxH9Hym 8 H]IpI IdžP I@ M H L)H{I I@ Adž Idž` AƆ$ LE_HvLEHHEH)I) H HH)H HH9HB( H= 1LE.LE& D H= 17HKf. f. f. f. UHHNdH%( HEH 9 HUdH+%( uJff. UHAWAVAUATSHdL<%( L}L AWHMw@ IG@E1O,IJ\( H H{hIHCh H{xHCx H H{ Hǃ $)H{@lH{8lH{0lH:IG@AWHJD( A9gHHEdH+%( u*HL[A\A]A^A_]} D IA9+I @ UHAVAUATSHL dH %( H]HI}XM }HLHǃ ;=Ht,H IHŞLLH׳L/9HuI ~I I kI kI kI kHEdH+%( uHL[A\A]A^]8Hf. UH fHnH7) fHnHAWAAVAUIATSHPHH ~ / m ~/ m dH%( HE1flfl)@)0HIEx( L jH A I A unA ud 誕IF@H} IEpM.E~H H2H9 A H H H9tx9Hu@8 u1nf A ` 9HBH@H< jIF8HlI~@jI~8jI~0iL=7E1 D fo0fo@A M IFPAFXAF`Lx)PhM A Hff. H H9t9HuLH#xt1 f D EH H H9t 9HuHx HuE1 f D A DEH9HtH H9u1f. H@HEIp fA EHtN@% H1ff. @ HtH9t E HD9H] H H9ufA| Al fAnx EA fbʼnMfEI fEHEA EEt4H9t/A f D H6H9t9FuF tu E fA ~Hn. H`H I# tDI0 H A8 E HE I|$0Ht H5 %=uMHEDIF HHHEdH+%( = HĨ L[A\A]A^A_]H#xHfHn A( H< fIF0H< A HEH3E HE E HE1A 1A E HHH1HHHHHEfo0fo@ AƆ fEA 1IFPAFXAF`Lx)Ph SC UHAWAVL AUATSH8HuH dL<%( L}IL9, H+ E1E E1DUHM# Eff. HL9 DkHsHE HtH}ʆuLK8M9rHC@I I9sH 1pm 9 t:EH} HMHuLk H= LDHLP1!DkXZEaHDmL9mDUHMEu*} u$Hom 8 tHuLH=r 1˽EHEdH+%( / HeD[A\A]A^A_] E1LE1E1Eff. @ HL9 CA H{H uLK8L9rHK@J4 H9sH5!om > t@L| Hd HuLEHH=y 1QH 5 HUCHUY^tHHAL9u D EIEEHnm 8 H @ A - D Hynm D EE1H@ UHHAWAVAUATSH(dH%( HEHL L H IL Hu D HCH HL;ct^rHCHuHCHE0 bIHt6fInfInMHfl@(LL@f@HEL(觱LHEdH+%( u2H(H[A\A]A^A_] HCHEf D 1Lut?ff. UHAUATSHHwPdH %( H]HLhp1I IAHGpHtD9`tWHCp H tHlm Hǃ x$ uMDL肢IHtbH4H HtNLcp1HUdH+%( u@H[A\A]]f D H{xGtHCx DLTMHCxf D >ff. U1HATSHHW(L'dH %( H]Hf ǃ t t A$ t1J@ Bu 8t @ @ HEdH+%( H[A\] @ t3Hz z z ǃ # Q D Hz uqǃ t f o X If ǃ ! HS( ǃ c <ff. UHAWAVAUIATSH~H^ dL$%( LeItZ uPHChHtpPA|$SPu@CXA } HEdH+%( H[A\A]A^A_] sXI}xCTP H{hqHCh STtI}xOHChHmA tfDcPEvHDHxpH M|IHTH;CptPHCp H{x:qHCx H &q11LHǃ OH H LkpHChH DxE} LDH{xAHt;G t)pHCx LDNHCxHHt8fnOfAnfAnfAnfbfbfl sCPfoL S:ff. UHHdH%( HE1HEdH+%( uH@ 1dz:fUHAWAVAUATSH H $ H Dd LuD% @ D$IDE,(dL %( L]D] ` E1 Hu@ DD L0LH?DHD HL LAS,APD(AVV AQD$yNH gm H08 t 3 ff. I|$pL1qADž HEdH+%( HeD[A\A]A^A_]ÐE1@uHu@ DD L0LH>DHD HLLAS,APD(AVV AQD$M H0u H fm 8 uGA 'fH`m DH 101T 蓞HtHLd 8ff. UHAUATSH(L dH %( H]HHucH~IE1HGHv/HEdH+%( uhH(I}@LH[A\A]]7 I HM蠪HMI HEdH+%( uH(I}@HE1[A\A]]X C7 UHAUIH5y ATSHHdL$%( LeI {t9H5x H {tFHEdH+%( uLH1[A\A]]f. LHEA$ I$ LHp6f D UHATSHH5|x HdL$%( LeIrzt HEdH+%( u.H1[A\] @ 11H贆HPHwA$ 6ff. U fHnIflHAWAVAUATSHH L3Lg(H`dH%( HE1HXL{@Ln(HI@ HtEI HJI 1H9s,HEdH+%( HĨ [A\A]A^A_] D A A fAWHCPHhtBI|$ A|$ ~ H ~ Hhf֍CXo ) fAB9u IB HA$ I$ H`H A|$ K I @ fAO@AtA A u.H Ht"I LP?aLPHpA tA A E$ A$ D IJp A$ H`H`LXA H)HP HPI$ L8HHH L@L@`LHHHf x9EAEt.ALt&M HcHLXI HOff. fHL9uHPHL@L8H !I$ HH L HX @t HHHOH H@uH A$ I$ H`HA|$ @ I; @ I|$ 4A|$ ( A A$ LK8uI$ | I MAM$ M$ I$ ALօtr ШuZHII@HFI@HNHHHH?H? HH> HH= I@IHuI IL9pL AtA$ A @ A$ & HH t!I$ HA A t3HX1LH#H1LfAGLmaI~pHXL谩H7Xm HH 1X01wX @ A kA$ \I$ H A$ t$t I$ tH HH!H HfI$ HH fH D ID$f D I$ L I$ HxW @ A I f D HH?H?pf@@ HS0sXLPA( H{hM L`蔆HC0LPH D HHA sXLH{h1LK8y. D UHAWAVAUIATSH(dL$%( LeIHvA|$I Mt$ f D M<$A % t{It M HspHz HKhHSXIu IMIUMD 2 A|$J AEtAD$IH Hm?A|$I It$Mt$D AD$I $HHA@H<蝏HH HP(ID$H7I$H@pH x# p1HiHC(HH HE IvLMA E I~(HKPBIXZMtA HKHK(LCpL)HKht } HCXME IMIE{I HC`HIE 1f D HKH~ @ Hx MtL>IE 1HUdH+%( unHe[A\A]A^A_] HCXCIME IMIEl H{(L1LEH).LEf. MtL=I\$, UHH HAWIAVAUIATL%b SHx HH Um LH;dH%( HE1Dž C{MS HHDž HpHHxHHh D HpHxLMHA . DOEAH;L1HH#m zIcHMl AH;Ha 1LItzM9u߃$f D H;HS L1AHzAu⋅~xLhHx L-~H;LH L1zHHH)HEdH+%( u.Hx [A\A]A^A_]f D H;H7l L1y* D U HSHdH %( H]HHEdH+%( uHP HX H])ff. f UHAVAUATSHdL$%( LeL A$ t&1HUdH+%( H[A\A]A^] @ H HIx# Dhx 1D{HH I|$@LELHuHHWm 8 qH}1DHZHEH= L`HX(ЇHLH}<<) 1 @ Hx远AH C ](ff. fU HAVIAUIATSHHdL$%( LeI fBHFPHAH tCHF(Hx x H ID$~ ~ fAք$ CXAD$X fA$ o A$ A HC(L@HPM$IT$M x H3 H; A$ A ID$0 A$ fAF A HEdH+%( ' H[A\A]A^]f Hx x f D HH?H?Jaf. x H L; 3 $ D A HS8sXH{ha)HC8I$ 7A( HS0sXH{hM H}HC0I$ f D H I SID$` LLH?H?%f. UHAUATISHH dL,%( LmIHt,HEdH+%( HD[A\A]]7 L $Hc o HÅtjHؿ HHH= ~ H= x P ۔I$ HHsHEdH+%( uFH1[A\A]] H5io H=J]Hc Vo tDo @ @ `$ff. f UHAWIAVAUATISHXGHHULwHHA@dH %( H]H_L,f. fHLHE )E)EHH HP(H M $A % t{It M HKpH HshHSXHMHuHUM EH( M;t$tM;t$tL"5HuH}IAׅ<Mt M9t$tM9t$tLE4EHUdH+%( ' He[A\A]A^A_]f HHKL]LMA E E IvI~(P8L]HXZH A N HsHs(HKpH)Hsht } HCXHMHuHE{I HC`E HHEHff. I;\$5I;\$*H3 D I$H@pH x# p1H2HC(HHI9 I;\$ I;\$tH3y D HC`E HHEHERfHsH @ HxtHCXCIHMHuHE H{(H1HMH)+$HMf1Mtf. I9tI;\$tI9\$tH2,!ff. UHATSHdH%( HE1 HH I9OL[@BAAKI;pt5 A1HIf. H(9 ;puL` Mt6A|$L t.AD$\ ~CuHMm 8 AD$` HUdH+%( H[A\] @ wED$`1AD$\ f D 9sK)IJHIT( H(H9t;puA D A|$H t!AD$\ \H= 1dIH L谒At$H{XI$ H'AD$Hb f UHAWIAVAUIATSHH IHHPL H@xdL$%( LeMHXH`HH06TC IU Mt I9W IL$(I$y IL$hH; R H Dž H L}HHP ACHE1ƅBH8HH0 }1HpH LO M A$ R IE 4 H H(uHGH+H(A taB tXH(HXLLH LHHt H HPH H9 IE HpH LHvJLHE ADL(D^f D CI L98 HcC IU HPHH9IU C HpH;Qs IHXHHLLA HH] DHLI HMJm 8 TIu HIwCH{LH o HB L HP ) HpH(HXHx rH 1j D H A ID$pHXHtAD$PA9$ HoIm 8 ff. H0HEdH+%( H [A\A]A^A_] E1HH01L H Dž HHm x$ A Lu}ID$pHXIL$xH AIU QA H + @ 1LLHό HpLH @ H1Hm 8 H=\ 1B D H Hm LH; 1LH=E LX ; 諀HXHgH Mm I)HpLp M M LV+IHL`(LLLh HIF(CAF0HC IF4oCAF<-LL1@f D ƅB H HGm 8 H=[ 1 AtHHFm 8 H=[ 1qC H= 1єLDž I$ IU RHXLHc cn IDžu-H5Un H=6PHc Bn u4n @ @ L HHH= ~ H= x P 0I IH_1f D HEm Hu#4 H0 hHEm tIu H= 1ȓ͈HHcS HMA HXLLH qEm DHHth E1DS?HHHP IU HP(HP0SHP4HS o@<HEm C8 JIu H1 H perf,pH3EHtwrite H3MH svH=D 1DH[H=Q 1ʒEIu H= 1賒)ff. @ UHAWAVAUATISHhHF(dH %( H]HDPE& H L3E1I Iư I9 E1E1 HL9 CA H{H uLK8M9rHS@I I9sH Cm 9 tXL[Q H D~LEHD1RLLH ̳ H= 袑CD~DZY HEL9a D E E H/Cm 8 tH i LL1H= 7E~fH;L; LshM LmLJLL Ld(H HEHH H x4 LtQH;H LLATHEdH+%( udHeD[A\A]A^A_] Ah HPH+ HEdH+%( u HeLL1[A\A]A^A_]6E1|ff. U HAWAVL`AUATSHH L/Lg@LdH%( HE1HI@ HtEI E1HVH9s2HEdH+%( 5 HĈ D[A\A]A^A_]f. HC(LLHL oH` u Dž HA Dž\ Dž ~ HC(@pfl) ЉTA A XHTHu>I}pLL_AƅH:m DH 101(m I 1LH<L1HfAD$LCAƅt D U HAWAVL`AUATSHH L/L@LdH%( HE1HI@ HtEI E1HJI H9s+HEdH+%( A HĈ D[A\A]A^A_] LLHLH` u Dž HHS(DžT ~X BflT) HDžx A Dž HTHt4IP 1LHL1HfAGL?BAą I}pLL腊AąH 9m DH 101Nkf THBHXAfU HAWAVL`AUATSHHx L'L@LdH%( HE1HI$@ HtDI$ E1HJI$ H9s(HEdH+%( a Hx D[A\A]A^A_]LLHLHA$l ~ HC(flHP ) {M H HHt$H H+ o H A$ H t5I$ 1LHL1HfAGL@AŅ I|$pLLĈAŅHJ7m DHX 101i H H+ H2f D HH+ {M Hu ff. @ U HAWAVIAUL`ATSH L'H_@LdH%( HE1HI$@ HtDI$ E1HJI$ H9s(HEdH+%( HĈ D[A\A]A^A_]LHLL H` IN(I~H fl fV )T U~MH HcHXHHff. f H HHJHHHJH9uHT HA$ uWI|$pLH跆ADžH=5m DHK 101g Dž f M$@ 1LL{L1LfCH=ADžu_ fUHAWAVE1AUATSH(dL,%( LmDn`A Hb:m IH8 sXI|$xD6AƋCHID$@L<AMo tpA$ udIEhH PAAUPu@AEXA$ C`HEdH+%( H(D[A\A]A^A_] AuXI|$xdAETuAEPI}h`AIEh AUTtI|$x@ IEhHTA$ i @ EePEXIE DHxpH KIH5I;EptPIEp I}x@IEx I @11LIDž I H M}pIEhH @E LcI}xHtm;G uUfnOfn]fnfAnfbfbflA ~f vXDH=6M 1l E@IEx ULU UHIExHufo A P U HAWAVAUATL`SHHx L7L@LdH%( HE1{M Ht;H H+ It(I@ HtLI HJI H9s5 D 1HEdH+%( Hx [A\A]A^A_] LLHL?HLL~ H H+ A flH)o u=I~pLL^ÅVH0m H 101)c6 @ I 1LH<HL1fAGL9Åt U HAVAULpATSHH L'Lw@LdH%( HE1HA$ t# t&I$@ HtBI$ HJI$ H9s)1HEdH+%( HĠ [A\A]A^]f A A$ fAFHCPHxtCHC(Hx R x H ~ H ~ HxfօCXo L扅 A$ f HC(o@HPHpf֕fH~HY x H; Y ~ @A$ HDž flɉfAF)t?H4m 8u3H@fo $ HDž` H0)@)P @ {M . HHt$H H+ o H A$ t4I$ 1LHHL1fAFL7ÅI|$pLLWÅH-m H 101"` D x H; H I$ 2H3H D Hx x f D H H+ Hf D HH?H?zfHH?H?y% D U HAWAVL`AUATSHHx L'Lw@LdH%( HE1HI$@ HtDI$ E1HJI$ H9s(HEdH+%( Hx D[A\A]A^A_]ø A A$ fAFHCPHhU CXo A$ f HC(L@HPL`HxM= x + H3 H; = A$ HDž fAF A$ I A$ H~ fl)t5I$ 1LHL1HfAFL.4AŅI|$pLLs|AŅH*m DH 101<]_ HC(Hx tmx tg~ H ~ Hhfօkx H L; D Hx (x 낐H I$ |/Hp0A$ HS8sXH{hXHC8H A$( HS0sXH{hM$ HYHC0HE D LLH?H? HH?H?Jff. fU HAWAVL`AUATSHH L'Lw@LdH%( HE1HI$@ HtDI$ E1HJI$ H9s(HEdH+%( 3 HĈ D[A\A]A^A_]ø A A$ fAFHCPHh CXo A$ f HC(L@HPL`HxM} x { H3 H; } A$ HDž fAF A$ A$ HDž DžT ~( HC(Dž H@xfl)HXHTHt5I$ 1LHL1HfAFL0AŅ`I|$pLLxAŅEHN'm DH\ 101Y$ @ HC(Hx tux to~ H ~ Hhfօ3 x H L; t D Hx x wf D H I$ +Hp A$ HS8sXH{hHC8H ? A$( HS0sXH{hM$ HUHC0H D LLH?H? HH?H?Jff. fU HAWAVL`AUATSHH L'Lw@LdH%( HE1HI$@ HtDI$ E1HJI$ H9s(HEdH+%( # HĈ D[A\A]A^A_]ø A A$ fAFHCPHh CXo A$ f HC(L@HPL`HxM} x k H3 H; } A$ HDž fAF A$ H` u Dž A$ HDžT ~ HC(H@XflDž )HXHTHt5I$ 1LHNL1HfAFL,AŅVI|$pLLtAŅ;H#m DH 101UfHC(Hx tmx tg~ H ~ Hhfօ+x H L; t D Hx x 낐H I$ (HpA$ HS8sXH{hHC8H O A$( HS0sXH{hM$ H-RHC0H D LLH?H? HH?H?JMff. fU HAWAVL`AUATSHH L'Lw@LdH%( HE1HI$@ HtDI$ E1HJI$ H9s(HEdH+%( # HĈ D[A\A]A^A_]ø A A$ fAFHCPHh CXo A$ f HC(L@HPL`HxM} x k H3 H; } A$ HDž fAF A$ H` u Dž A$ HDžT Dž ~ HC(H@`fl)HXHTHt5I$ 1LHL1HfAFL )AŅVI|$pLLNqAŅ;H m DH 101RfHC(Hx tmx tg~ H ~ Hhfօ+x H L; t D Hx x 낐H I$ \$HpA$ HS8sXH{h8HC8H O A$( HS0sXH{hM$ H}NHC0H D LLH?H? HH?H?Jff. fU HAWAVL`AUATSHH L'Lw@LdH%( HE1HI$@ HtDI$ E1HJI$ H9s(HEdH+%( # HĈ D[A\A]A^A_]ø A A$ fAFHCPHh CXo A$ f HC(L@HPL`HxM} x k H3 H; } A$ HDž fAF A$ H` u Dž A$ HDžT Dž ~ HC(H@hfl)HXHTHt5I$ 1LHL1HfAFLY%AŅVI|$pLLmAŅ;H$ m DH2 101gNfHC(Hx tmx tg~ H ~ Hhfօ+x H L; t D Hx x 낐H I$ HpA$ HS8sXH{hHC8H O A$( HS0sXH{hM$ HJHC0H D LLH?H? HH?H?Jff. fU HAWAVL`AUATSHH L'Lw@LdH%( HE1HI$@ HtDI$ E1HJI$ H9s(HEdH+%( 3 HĈ D[A\A]A^A_]ø A A$ fAFHCPHh CXo A$ f HC(L@HPL`HxM x { H3 H; A$ HDž fAF A$ H` u Dž Dž\ HDž ~ HC( fl)A$ \H\Ht5I$ 1LH6L1HfAFL!AŅNI|$pLLiAŅ3Hlm DHz 101Jf. HC(Hx tmx tg~ H ~ Hhfօx H L; s d D Hx x 낐H I$ HpA$ HS8sXH{hHC8H ? A$( HS0sXH{hM$ H GHC0H D LLH?H? HH?H?J-ff. fU HAWAVL`AUATSHH L'Lw@LdH%( HE1HI$@ HtDI$ E1HJI$ H9s(HEdH+%( S HĈ D[A\A]A^A_]ø A A$ fAFHCPHh CXo A$ f HC(L@HPL`HxM x H3 H; A$ HDž fAF A$ H` u Dž HHS(DžT ~ fl)A$ THBPDž HXHTHt5I$ 1LHkL1HfAFL AŅCI|$pLLfAŅ(Hm DH 101F HC(Hx tux to~ H ~ Hhfօ x H L; c T D Hx x wf D H I$ Hp A$ HS8sXH{hHC8H A$( HS0sXH{hM$ H-CHC0H D LLH?H? HH?H?JiMff. fUHAWAVAUATSHHHHudL$%( LeL'I$ u,Ml$xIp H A$ I$ Hrm HE + HE L;Lk(ƃ A A~E AE0 CMHDm x$ t fA} A1 AE t [ A t @ A t], HC( 9 tHAƅ AE t' @ ' t Ax A AE A t A t( A IUHsXH{h_ E MEIMAQE AQE AQD R nH A t5AEA8EtIMHt IUHo H7AE {L t%HIEH; Q H C\ H{ 'DpIE Af {L tI$ I9E A$ I}@H L31KPDCTA ) A t A} 1HMMAuWLRSXP苭H AƅIHEdH+%( HeD[A\A]A^A_] A AE( ;HC(Hƃ A$ t2IEI$ HtH9r IEHtH9 f. {L t {\ IU8H H9s H HL M A$ dHMH H;PH f D HC(H HEHM tH HP HE0 HEH8 HH H蒰Aƅ AE 4 Hئ I9$ H3Q; ƃ Ds\A @ I DEM%DEMf Ds`CL AiHE8 sXI|$xD\`CLHID$@H4ĨC`# D Mf H 0 A fuHAЄuAHuAHuAHHA IcHHH( H1 H0 HDEAƅDEAHA?L HHMHH# 0H E1J HH L*ƃ L L9 H3 ƃ HH LjL Mf S\M C\ if A$ +A$ ID$pH HH9A$ ff. H H99Hu@8 uA$ A$ ID$xIDŽ$ Lh Mt~LfurI IHHt^B*<uCHz-H5& HUO'HUu'A4 LrIu HI+OII9r M;w H-HHuHm IDŽ$ HE HH I9El % X{`Nff. HE8 IE@H = C\ HLKAƅ{ / H AƅAE @HPAƅAE @ H@AƅHAƅA HgAƅ KPSXH= 1sDCTE]HXAƅaAE @ H8AƅAAE @ LIp 4 @ H0Aƅ AE "HAƅAE D I; C\ f HAƅAE @ IE HHUHMAƅaHUIE HIUHMAIMQ D sXDH=" 1[F H8AƅAE % @ Hm H 101:HHE HE0 t<H f D IU@Iu8H=" 1j[GA WHSm DHA 1019ƃ L9m-{L u!H{ LATu LmA0H;H1C\ L MA$ H! HEu H! HEHuI}-"u'A4 IEIu HI+OHH9r I;G Lg)IHuH@ m M$ 8 HEuRA$ AƄ$ AL$HIt$@H HV H4H HtALH(H9urI$ 1LH= ! YHEA$ CAƄ$ AL$Hu,I$ >ff. fUHAWAVAUATSH(O`dH%( HE1 IHh D IGXHHEHAG`tIGXH@HHEH9sH]LL|HuL tfAEH AW` IGXHPH9 H IIG@L4H m Mn 8 gHDH= 1XNf D HUH}DPAyf. HEdH+%( u1H([A\A]A^A_]1 @ HUH}DEAMff. UHAWAVAUATSH H m dL %( LME1ɀ8 8 0 l H HzIIHGH ' HDžx A O f P1 L5b m E1A> IKd uh X A2ASXH=ޏ 1LxDhLp"WDhLpDxLpAA>Dxu$Ht HpH1Dx HEdH+%( HeD[A\A]A^A_] {L HDžx 3 IP e A tI % H E HCpIs LhLpH H; LpLh* AafHpH Hh6MLpLhHHx{L & L M HxHLhLpLpLhAf D AIsErHE HpsHE1A LhLmAL`H{@KH4Lf Mt-E;t$Tu&HpHI$ LLDCHIE9rLhL`-fAS AsLhH{xLp!LpH HNj( L AsXMHH Lp LhI t ff. @ I " A ABt L5m ef D HSpLH{@MzLhLp^LpIHCpIs H MLpLh@ IV H3 H* I@ IL56m LH( IC H0 A L5 m A> AJ ARLhAsXH{xLpQLpLhAI f HAKASXE1A Lh HPA PEC AsLpNH ALhLpAH +fARAփfA * E{X fE6EcAS L5m IKDH߉`LhLp LpLhA~8H{x`DDLhLpPLhLpA @ EA KHCL HDžx LpE1Lhff. fHS@KEL<M;? Mg Mc A|$H A|$L tA|$\to ufL=m A? e A$ tI$ H1 f I|$ vH@t\uA? ff. fKHIA9@ LpLhHx fHQ8HtA? I$ A$ IL$(AƄ$ t,I$ Ht I9$ sAƄ$ ff. L蘕I$ H{XD8A AD$H.f D DHMIH IG AGtAD$XAG ADŽ$ AD$Tt! u tAD$Jf AD$LH HADŽ$ I$ H AƄ$ HSpH{@LLhHE Lp Hk Lx LpLhMQISA~CAGI L5 m I PIA> L`xAWXfAGPc IhLhLp$AWTIGh LpLht5AwP LLhLpLhLpIGhHuLLhLpLpLhA/LxSHL FMMߐHK@KHH@ HtHx Ht L:SHIA9rMM 1DH= MA? AL$PAT$XD1ED$TH= UM[HBAƄ$ I$ f D Hɸ HP D`HELhLpH D`!A> LpLhIKLH>^ HLhLpL5l LpLhAA> E{X8 IKDDHLhLp芯LpLhAH{xDDLhLpJLpLhAyHCpA LhLpH ƃ ƃ LpILhd fEM AK ASLLhA Lp`JL5al LpLhA HCxIRLPL`EbHHH HXEjHhHEHHpL`HXLPfAz ALPEML|HHXAH`LHEH H; H;X Lx MtNI HtBx4 HuHPH+։DHt HP Hcp4HHI9T$w @,uH`HH9u HXLPMHpL`LhLhL`fHpHhHDWHt HE+I;\$rv D DH=' 1IKH I|$ BAf D KHCL @ fE EbAR 0I{H LhLp@LhLpH= I1AJ ARAsXMCILhLpAS AsLhH{xLpQLp H L HIAsXMdH LpLI 7LhLpAbA> VH= 1L`LhpDHL`Lhp Awfpf~1fA~H= LhLpGLhLp\I H DA> kI HH=! 1GNDH= 1H`GH`<L)LpLhHIGh>@AGP2I{H >LpDDIH=~ 1IK GLhLpH{@LmMfKHL` MtOHpHLhII$ HLLsHLhA9sH{@f. IA9rMHl H} 101$A EcEs Ex|sHtuVA9H{@ABAKHD;xt.& BE1Hk(HAH(D9 D;xuH@ Ht xL tp\@`Vw@\ H{xDLhLp"LpLhA9H{xDDDLhLpQDL5Rl LpLhASHƃ H{@E1MKHt Ht8FL HILpcSHLpA9sH{@KHt HuIA9rM)HHLHn u:H5n H=wH8+}n H8uhn @ @ HcHп HHH= ~ H= x P a8I HHw}HJl H 1LhLp01"LhLpL5l A9(Ik()JHk(HHT( H(H9 D;xuAHl H{ 1LhLp01!LpLhiff. f UHAWAVAUATSH(dH%( HEHl 8 0 H {L u7HEdH+%( H(HH[A\A]A^A_]G KHHE tqHC@E1Luf D KH4Ln Mt7IDž HILLKHA9s%HC@ IA9rff. @ 1HUdH+%( H([A\A]A^A_] @ KHCL E1f D HC@KT EL<M;? Mg M* A|$H ~ A|$L tA|$\tn ueL=l A? A$ tI$ H I|$ FH@t4uA? ff. fKHIA9@; HQ8HtA? I$ A$ IL$(AƄ$ t$I$ HtI9$ s AƄ$ @ L蘆I$ H{XD)^ AD$HaDHU|IHp IG AGtAD$XAG ADŽ$ AD$Tt AD$L hH HADŽ$ I$ HtoAƄ$ 71DH=q @A? QAL$PAT$XD1ED$TH=v ?,DH=O 1?KHj HBAƄ$ I$ f D 'AD$J I|$ 8QDH= 1HM\?HMzf. UHAWAVAUATSH( HdL$%( LeL I $I9$ If HI9 9Cu tH1 A HHDž LK(1 A I A Lu ALHC0S8Hp % ЉH H L ʚ; MLDA A t I LA tI H8 LA A8 I0 HDž u(A 1A HHH1HHHHL=l ML5~ H LHqv 1A7LLL1) LH LHHLHHELAY LfInAƅx IfInflA A A8 I0 HDž L=l ML5@ H LHu 1A7LLL1) LH LHHLHHELAp LfInAƅ IfInflA IA HDž L I A Dž L A A tC A E1 fA I D L=Il IM1fo L5 H*t A7LLLLVL1) LH LBHHLHHEAtfff. DA7MH Hs 11DHEdH+%( E H( D[A\A]A^A_] D LLAƅ ~fInIIflLA A 1A HHH1HHHH6 Hl Hr 01E17 @ L=l L5T M1LHr LA7LHDž L1) LH LHHLHHELArLfInM<$Aƅ fInflA M9t! @ I Ht L; M?M9uIL=l L5 M1LHq LA7LHDž L1) LH LÁHHLHHELA~fInM<$Aƅ flA M9t'f. I Ht L;^ M?M9uI0LL=l M1Aƅ L5o Hp M A7LLLHDž 1H) HH LHHHHEHHHLAlI$M I9t)ff. H Ht L; HI9uMrA7L1MH Ho LHDž LH1) HL HHHHHE-LA I$M( I9t+ff. H Ht L;0] HI9uA Mrt C MWL5l LM1H Hn LA6HLHDž L1) LH L~HHLHHE8LA ~fInflAP M,$M9I Ht L;) Mm M9uA7L UA7LM1H Hm LHDž LH1) HL} HHHHHEF L I$M I9t$ H Ht L;0 HI9uMrA7L1MH H m LHDž L?H1) HL3} HHHHHE}L I$M I9t H Ht L;0 HI9uMrA7L1MH ! HHl LHDž L}H1) HLq| HHHHHEL I$M I9t H Ht L;0 HI9uMrA7L1MH f Hk LHDž LH1) HL{ HHHHHEL M<$M M9t I Ht L;0~ M?M9uIH @ L5l LM1H Hj LA6HLHDž L1) LH LzHHLHHE%LA ~fInM4$flA@ M9t I Ht L;X M6M9uIA ir @ I t!I LLLLLL跕LLI I tI LWLLLjLI dDA6IH t(H LHLHLHLHLH A7L H t(H LHLHH=@ HL肔HLH EH t(H LHLHH= HL HLH I t I HI NA7L} I tI L}LHL萓LI jH t(H LH0LHH= HL1HLH A7L OH t(H LHLHH= HL趒HLH A7LM I tI LALH= LPLI @X UHAWAVAUATSHXHudH%( HE1fW I HIH Hǀ H HHEsLH=yAt]H}DEI kI _L蠠DEHEdH+%( HXD[A\A]A^A_] IG@HHEAuH ; 9 oA oCA oC A oC0A0 oC@A@ oCPAP oC`A` HCpIp Ae @ HEIGpH I}0 IGxAEAGhIEA IEfA IE A IE(A I}P I IE8I` IE@I IEHA I}X A Hl A 8 tIL5tol I]MfPff. IHtHl H H81迩IHM9uAEf= M Mt M9s H +l I: 9 A IGpI` H H H E E A H9 EHf D H H9a @( A 9puHH#p E1 @ IUpAoE`H wl Ax IUx9 Ah A| I I tOL%#nl Mu`I\$(f. IT$PHtHl I H81mIII9uAEf= H5l I > A L%,l H 1I<$EuM LMf= bHl M 8 Q I<$1LH LUħMLUtvMeLHI I90 HLHULULUHUHI HMy | H}L3 A IH l I 9 H'l HLUL LEH R 1H:HO LUX H=e& A sI { u { uA AƇ fE CA f D E AƇ E AƇ H9U E1A H @*t H H9u1A A E 6 E HEH HxP ' H9 A D H H9 9AuHqI#h tI H H}LueH}II HEA$ H}HE8 1LHx#E$HEE/ H}~HE8:H HEI E AƇ Eu ALJ AƇ A AƇ AƇ ff. ɚ;ɚ;ёI HH 11H5 A3 I DEI 7DEILJ DEOH}VHEDEHǀ f D f D AƇ E E H9E1A A HE1ff. @ H H9t(9puIL#H H A H9u E ^ @ DM Mf= M M ALJ IwxI AZ ~eil H~fHnHz~flfHnH]AfHnH:]~2il fHnHEflAG~ il flAG ~il flAG0L Hpl 8 kA d A A ʚ;1A HHH1HHA HHL$u%I$Haw̫HHHA H l ; L1HHS㥛 HHHA HEH XXL`P M A Hcþ DEHHEI H H{l DEA 8 LeM HE L}DE;M>E1M H,l M~8 c HEHEHEH9E= HELuE1IL HEHL`HtLH^I f ILL1H9sff. ILLH9rME AƇ EALJ oHl H HZ 101ff. @ AHLUHUI LUHU AEE9f Hl HZ[ 1DE01SDErf. A] D Hl HZ 101RfHH} E 1LH} E$HEZH M Mu ^ IEH II;]tSrIEHuIEHE0 HtXHMfHXHL(HuHH MHH(HMHH} HE8,HKH5 D A D IEHE|E Enf D Hl H H81xHtl H H 101HOl HX 101H1l H:Y 101wE1JHEHEAL}DEA t A " A t A fA tH l { A ? I H HtfAn, fpfAև A IGpH HH9t @)I H H H9uA DEH@H< DEHI IGpH HH9 A ff. H H9 9Hu@8 uA I HuLDEH HA A A ? A DEy IGpH HH9b מ D H H9H x; yH tA0 " fA0 I8 H H9u1LHH=W u Hl 8 sINIH=W 1u VLLI D ILLI9s @ ILLI9rIGpH HH9t@( H H H9uA( DEH< DEHI eAMAA~A/Ad Ap DE@CDE HEH HH9t @;H H9uH HV Hql 101AHEL MfM9 H E EMd$M9 LHH^uM EMIH 0 HqU tAƇ0 HEH x f A HMH H9 tvH}HDEDEAM tAƇ A Hml HFV DE01DE H H9H} DEDE~L1H=z DE; A DEH=i 1A DEA I H5 H=J 1DEH=Ul DECDEC fALJ Hbl HT 1DE01DEt1I 6h UHHNdH%( HEH 9 HUdH+%( u ff. UHAVAUATSHdL4%( LuL AVHMn@t=IF@1 L$IJ| HtF蹌IF@AVHHJD 9rHEdH+%( u#HL[A\A]A^]- D H9rif UHHdH%( HE1HEdH+%( uH@ 1W"fUHATSH H $ HXH NXDN DFdH %( H]HvL PLj H 1LH{pÅu HEdH+%( u.He[A\]f D HQl HPS 101nff. UHAWAVAUATSH H $ H L'dH%( HE1LHILHI$ Ht I$P E1HJI$P H9 IT$xM.LHp LHW I9> HC ~@ A~FHDž@ A$ HC$flDž (oCDhCTfC<f֍8f fugHI|$pLH@AŅt Hl DH R 101 HEdH+%( H D[A\A]A^A_] D I$H I$8 L1HHfeAŅj HHHH Hp Ff D UHAWAVAUATSH dH%( HEH HH9 HIff. HH9 9Ju tE1L LLHDž LB(J8AK p LH HHB0H% Ȁ u0E1HEdH+%( 8 H D[A\A]A^A_] D H fo HP L M ʚ;MLDHl I L0L1L) LLLf LLHHLLeAAąu[HfInƃ0 fHnfl8 HHHH H!l HO 01dH l H HO 101? D UHAWAVIAUATS1HdH %( HMȋOHu. A uA} u I} ANHH9sxIV@HAL$M;$$tMl$ MuX #IH L0X@ @$ID$ AD$uAE$AE$AD$AE jf. 1HUdH+%( uNH[A\A]A^A_]1LIEHEHPXI~XDiuAE' ܕff. UHATSH H $ HXH& dL %( LMAj LHPL APAк \H{pH 1Lu HEdH+%( u,He[A\]f D H l 112HM M&f D UHAWAVAUA ATSHxHudH%( HE1 w HHLgW Hxx HECH MHHA@HHEM A~I A Mn(HM M^pD4 M MNh0 I HELxMIHhML\ Ht=AFT I>AF< ufEt DA#FTtLLvv IID L)Hv|I $ID$HtI>H AFT AF< tHxMD$I $AVTH@`Av$j j H}jEN<HEHP萃H X LLxE1L諤H}LHCH HUHtH@XHH}iHEdH+%( o HeD[A\A]A^A_] @ ;HEH@C HxAV HpH}H LUHuHHpLhLA HELp8L]Lp ULIN0HcL]~H} A~0I>I $AFTHWxHp H H9IT$H9A~TAFTc f D L(I>AFT AF< AN AV Av$M$I> H} Mt+ u"A~I ff. @ IF`s$H}HP謂H @ {Nf D HBpH x# p1LIF(IH: H HAFI;ff. @ IFHMH9 LPIN1Hp(MI)L9LCM9 LuMLxIHhLHpH` II9w IK<4LM)L uLuLxO\= HpHhH`ML M^p M)ـ MNh[D4 x 1HIHH uCA MNM^(, H fC] LALxf D HHpHUHUI>HpH;p HOxIT$Hp HHHpHMvHMI>HpHp HxLuLxMHpHhH`A MrfUHAWAVAUATSH(HuO`dH%( HE1HE IH_XAF AG`HE IGXHMH;Hrq IW@HIHHLp 蜓HuLAŅxIuHUDH8AŅyHEdH+%( u2H(D[A\A]A^A_] E1 HUDHzf. UHAWAVAUATSH(dH%( HEHl 8 uO0 n L HzIH1HGHvPA}L u_LuA$ tc1HUdH+%( : H([A\A]A^A_] I A}L HtAEL LHuHut AD$tA tHEdH+%( H(HL[A\A]A^A_]2fAUHAL$LIE@HH Hff. @ L8MtA;O tH(H9u1fLu f. u LLyf. A$Hl HD 101蟋ff. @ UHH dH%( HEHйl 8 u;H u+0 tQL u4HEdH+%( uCH1HUdH+%( u% D GL H}H}yӸ D UHAWAVAUATSH8dL$%( LeL A$ A$ H HIx# Dhx 1D5HH I|$@LELHds Hl 8 | H}1D He HEH=_p L%_ L= LpH@(LuHELL1H l HB H;y1M HEf. HU . H9HFIHEH;HMLH 1'HuIMl5 ff. AH;HS 1LIM9uH}Luw @ H;LL1IIuH}H; HEH: L E L@HLDL@H 1HMHMH)MLmH}g 1HUdH+%( ujH8[A\A]A^A_]11f HxAH H L1tf. @ UHAWAVAUATSH(L dL,%( LmII~XKM AWHIG@HEtDIG@1ff. L$IJ| Ht^wIG@AWHHJD 9rH}WIDž HEdH+%( u'H(L[A\A]A^A_]ww H9ra UHAWAVAUATSH(dH%( HE1f7 IX H赩IH H@@HHEEt.LvHEdH+%( EH([A\A]A^A_]ÐH I|$0 I]p~Gl IExAD$AEhID$A ID$fA ID$ A ID$(A I|$8 I HtfHnHHA flfHnHAƅ AE fHn~^Gl Hl fl8 AE ~KGl flAE0L tSL5l IL=Fl I $I 1I>II肀HFl I9uHl 8 H 8 o A o@A o@ A o@0A o@@A o@PA o@`A H@pI( A t A4 " A t A4 HLAƅt%H}DuHǃ H}HAƅuA}M Aƅ D pI H @A HEwEk\f. f. f. f. f. f. UHHNdH%( HEH 9 HUdH+%( uރff. UHAWAVAUATSHdL<%( L}L AWHMw@tbIG@E1 @ O,IJ\( HtnH{PIHCP H{8H{ HOsIG@AWHJD( A9rHEdH+%( u)HL[A\A]A^A_] @ IA9sff. UHAUIATSHH^ H dL$%( LeIs4MH{PuDAD$C0HtGGA|$C,t!HEdH+%( uQH[A\A]] GC4C0طHCP S0tI 跕HCPHHt4 @ UHHdH%( HE1HEdH+%( uH@ 1'fUHAWIAVAUL-L ATS1H8OHdH%( HE1HEGL HEu ff. H9 IW@HL$M9$$tI|$ uf` )EIH IF H H | M>A^H}IF,AF4IFX ]LmLuIF8HH AD$Mt$ tAF4A~( u$A0 tf I~8y:uAOHH9 1HUdH+%( uWH8[A\A]A^A_]HW0uIXIVHuAF(AOHf. I~ LOpC UfHn¹ HAWAVL`AUATE1SHH L/HW8dH%( HE1L LHHCXIH HHCXH9s-HEdH+%( HĘ D[A\A]A^A_] D HCX A0 fHne HB fofHnflH`I; 0 HC,1DB~R8HhC4flB@Bс DAAA AE@Ǹ @A}j H}fAGB A fAwH)xt4I8 1LHpL1HfAGLaAąI LLAąH*l DH7 101mk Hz0HPI HXfօHIH ~HHpHX~PK}ff. UHH-7 HAWIAVAUIATL%2S SHX HH Wl LH;dH%( HE1 M3 HHDž HHHff. fHHLMA . DOE(H;L1HH IcHMl ff. AH;HAG 1LITM9u߃$f D H;H L1A(Au⋅~XHH Pt\HHH)HEdH+%( uMHX [A\A]A^A_]H;H7 L1f. H;HHI L{ UHAVAUATSHdL$%( LeL A$1 t&1HUdH+%( H[A\A]A^] @ H HIx# Dhx 1DHH I|$@LELHCduHl 8 qH}1DHZHEH=Ba L`HX(HLH}|) 1 @ HxAH C+ zff. f UHAVAUATISHdL4%( LuI& HSI$IT$H HAFIIvMnHHA@H<HHtZIFH@(HuIH H x# u&p1HHC(Hu1f Hx MtL3ID$ 1HUdH+%( u$H[A\A]A^] @ MtLI^pyU fHnHAWAVL`AUATSHH L/L8dH%( HE1Lg LHA0 Z IG H`I; 2 HC,1AA~O(HDž HhC4flȉAGҁ © AA AE@Ƹ @A}j HufAD$AG A$ fAL$Hfօxt0I8 1LHjHL1fAD$LÅuI LL5ÅuoHEdH+%( | HĈ [A\A]A^A_] I0HXI 蹤~XHp{ D HQl H0 101qkwff. U fHnfHnHAWAVL`AUATSHH L7Lg8dH%( HE1Lo LHA0 e ID$ H`I; < HC,1A|$A~T$8HDž HhC4flAD$@AD$ҁ © AA AE@Ƹ @A~j HufAEAD$ AE fAMHf֍x)t/I8 1LH^hHL1fAELɦÅuI LLÅu{HEdH+%( HĈ [A\A]A^A_] @ I|$0HXI HP葢~P~XHp` D H!l H. 101ee;uff. UHAWIAVAUATSH(HudH %( H]H H Iu L I$p HM H Mw80 urINHHthAw4I =t)HUdH+%( " H([A\A]A^A_] AGLHIE@H4xƃ Mw8M/A H, ff. ff. : H ;J9JAD!9@@ tANE1 t2 fA~PAFwSANPH5N Hc H> @ AF H d Hʀ D tHH H ʨ0t H9 H!¸ H IA@ tAF AA tAF AB tAF ! ? AC t AF@L AD t AFW AE t AFj AF I8å Mw80 x%IN0IWHH9sIOHHʄu HuH; M/1Rf H H!H H AF @ I LL=I8 JHl HW+ 01 IP LL6AF]IX LLC I` LLAF3Ih LLr H!¸ H zH Hʀ Z Ip LL^ AFIx LL8 I L @ I LLf I LL|xH@ B H@ HB HB zHB kH \HB MHB >HB /L I$p M/H1ooff. @ UHAWAVAUATSH(O`dH%( HE1 HGXHIHE0 D HuL S`AD$( HCXL9h H}HIHC@L<Mg ytC`tHCXH@HHEI9sLm uLHHuLYuHUH}DEMHEdH+%( u@H([A\A]A^A_] HUH}DxNjS`2 1n UHAWAVAUATSH(dH%( HEHGl 8 u60 " L HzHIHGH A0 u,1HUdH+%( + H([A\A]A^A_] A}L 5 ;uAMHDsHE Md$t1A; HEHE IU@HH4L~ Mt"E;w0u Mg@L)HuLAMHH9rP @ I IH*A}L A0 RLL\ A C K DsA\$X HEdH+%( I H(D[A\A]A^A_] E1LEA0 MOeIU@Lu HH4L~ Mt/Mg@LHLLAMH9 IU@fH9rHtl He% 101HQl H 1M01Mgk UHAVAUATSHdH%( HEHl 8 uM0 L A|$L A$0 uIHLuA$ 1HUdH+%( H[A\A]A^] D AT$HHE tIL$@1Lu @ HH4Ln MtOIE@LHLL@AT$H9|IL$@ @ H=9$ Y` H9rL L8 6, jff. UHAWAVAUATSH(H dL,%( LmIHxXHEM AOHIG@HEtoIW@E1f KL4 J\2 H H{PIHCP H{8踼H{ HWYIW@AOHJD2 A9rH}IDž HEdH+%( u-H}H([A\A]A^A_]Y IA9Shff. UHAWAVAUATSH dH %( H]H HH9 IIff. HH9 9Bu1H A$0 HHDž HB( % H I$8 J8HHB0p H% ȉH L( I ʚ;LDA|$~ s A|$ A$ A|$m r A$ A$ A|$k A$ I$ H6 L) H HI$H L1LH AƄ$F HLLHDž Lu謮u:M$ L#L9t( I$ Ht L;(z M$$L9u1HUdH+%( H [A\A]A^A_]f % H QHQl H 01fL1) AƄ$@ LHL HHLLuHLH輭FHM$P H9t! @ H Ht L;( HH9u1) L HM]HHLLLuLL>LL;M$X L9t,ff. @ I Ht L;% M?L9uIgL1) AƄ$C LHL HHLLuL蠬*L;M$ L9t% I Ht L;( M?L9uIL1) AƄ$D LHLb HHLLuLL;M$ L9t% I Ht L;( M?L9uI}f. L1) AƄ$A LHL HHLLuHLHlHM$` H9t! @ H Ht L;( HH9u1) L HM]HHL8LLuLLxLL;M$h L9t,ff. @ I Ht L;1 M?L9uI#f. L1) AƄ$B LHL HHLLuHLH<HM$p H9t! @ H Ht L;( HH9u1) L HM]HHLLLuLL辩HLL;M$x L9t,ff. @ I Ht L; M?L9uIL1) AƄ$E LHLr HHLLuL L;M$ L9t% I Ht L;( M?L9uIHl H 101AI$ H tH H讃HH= HAHH H tH HdHH=~ HsAHH H tH HHH=H H)AHH I t I ׂH= @I I t I 詂H= @I I t I {H= @I Hml H 101賹I t I /H= L@I -I$ t I$ H=P @I$ _I t I ЁH= ?I I t I 袁H= ?I ^ff. UHAWAVIAUATSH(H dL<%( L}IH` 腄1 HfA~ HE IH L`@LĦÅ I I~I M I AF HA A HEI H9t#ff. D B(H!H9uA0 IH fAF fA IP A IX I v1Ao` A Ap A( Aq A) HxL5l ~ l fHnHmflfHnH A> AE fHn~g l flAE ~^ l flAE0M I Ht 8 I}h1`LLAƅu&LLAƅuA}M t+Aƅ1 ! LD=ILJ LzLHEdH+%( H([A\A]A^A_]f D H l H Hi H H1VA> u2fo AEho@AExo@ A o@0A o@@A o@PA o@`A H@pI 8.[ UHAUIATISHH LPLXt&)`)p)U)])e)m)u)}dH%( H(1H urHEIu I<$IHLH0H H Dž Dž0 PxJIU HcI4$H9sJHH)I4$IU H(dH+%( H [A\A]] uΉf D D u뵐HEIu I<$IHLH0H H Dž Dž0 0P\IU HcI4$H9:D >Y D UHHdH%( HE1Hll HHUdH+%( uYf UfHHdH%( HE1H qf <B <C ȃ<d <H < 1 I A JAA HAEML9 IU A+ 3 A HJAHEdH+%( k D A IcAH9sf < uH AH9r Hf G < <G LGA G A HAEHLL9 A OHJA @ A HcH9ryH !)Af. A D AHADZHDHALL9+A? A- D HO O O D I A A Bb @ * 5V D UHAWAVIAUATSHhHuDoHULg?dH%( HE1衔HuHME A> HHuHMwEAHװ HcH> D HUHuI1H}H O E t6AFHHUME HuH}IPH 1EZYHUdH+%( # He[A\A]A^A_] @ HUHuMIH}H ~ 1pEx IFHuL}Lm HMHE莓DMLLHUI1E H u HUAFHU< < . H K LL HAHuMAUH}HUIH 1^E_ @ AVMNHuHME L% H? HEL}LMLmHHELH ś L1,LMH}LH5 LԚ AH LDL1E1 fAFMFHuHME < < HUHu1H}H ћ E HEMnL}HuHMHuHLHEH O 1E HueA A A A Ac A 9 A@ Aŀ A A A ^ A 1 A H H A utEEf HEL}LxHEHuHLH 1HuLxA0 A IuH ^ ff. HuH}L1>uf <<LL]HuI H?M!H}RLH H=RHl LL1AZEA[ @ HuH}L1H % fHuH}L1H fHuH}L1H ˘ wfHuH}L1H WWfHuH}L1H s 7*fHuH}L1H J fHuH}L1H fHuH}L1H fHuH}L1H Ǘ fHuH}L1H UfHuH}L1H o w+fHuH}L1H F WfHuH}L1H 7fLHUHuMH8I?H}H = PLH>PH I!1AXEAY AH H LxHEL}HEHEHuHL1HuLxL% H L% H0wDHL HcH>LxH 0 ff. HuH}L1>LxLȃ HcLHuH}LHA 1LxAH LxA> A H ǖ zLxH gLxH q TLxH M AH J 5LxH g "LxH L H LL1D{ H LL1$[ LmHELxL}HHELH L1LmH}LLHxA 1HAH Q LxA AH 8 @A A AHuH}L1H LxRLxf D HuH}L1H ( 'LxHuH}L1H LxPHuH}L1H LxLxNHuH}L1H _ Lx HuH}L1H 4 LxLf. UHSHdH%( HE1H? t>Hx unHtHHHSHPHUdH+%( uH]f 1K UHHdH%( HE1HEdH+%( up;kKff. UfHAWAVL5E AUL- ATSH8dL<%( L}IAG@Iw`IGP IGHAGAG AG0Le\ HEHuIGXIw`H ~uIXIWh茊IWXIw` HHH)AGhIWXIw` HuH [rl f1L )M3)M薤IwLAlHUdH+%( H8[A\A]A^A_]f3H 1KIw`CfAlIWp t IcL>fHHIWXIw`fAWPtAOtAO tAO tAOtAOtAOtAO tAO@ tAO oAO b@% @ @ AG HDAG IW0 AW @ < l%n HH 1H H F%n H{pl 01ʢIw`IWHHYpl H 101蟢H H!HyHH=HHvx IG =AO3AG E HDAGH HH HH!Ht'IG8H H Ѕ{IG(H H H H!IG@Gf. D UHHdH%( HE1HEdH+%( u1MGff. f UHHdH%( HE1HEdH+%( u1 Gff. f UHHdH%( HE1HEdH+%( uFff. @ UHHNdH%( HEH 9HXHUdH+%( uF UHHdH%( HEH HLJ HUdH+%( u H=68F UHAWAVAUIATSHH dH %( H]Hx# ? D`L{McL褓HH I x tKLHDzjA9uXHtl 8 udH51HUdH+%( H[A\A]A^A_]1 D1Huff. HX5Ӣ D H=+ \1H5 Щ HK D$I1H AE!L=nl McI?L蕔M@E1f DDH<t.HII)u HxA I?H H5 *D UHATSHdH%( HE1f H` IfH I$ HKL`H~l HPPSHXP@HfHnHflfHnH6 fHn~l fl@ ~l fl@0I$ H rl 8 u1HUdH+%( u7H[A\]HYml H H81C>ǐmCf. UHAWIAVAUATL% SHcM4 M| H(HUdH<%( H}ȿ. >L-ll 1H$ LH > I} 虒AI} HL1I耒M9u L=k ff. @ I} 1LLOuHEdH+%( u'I} HMH(L[H A\1A]A^A_]oBff. @ UHAWAVAUATSH8H}udH%( HE1 LcL% J 7. D;1DL1L-kl H I} 蒑HEJD0L5 HE I} LL1HfHEH9u L5j I} 1LL?uDHI} EAL /j LPHk H PDH % PH PD PH PD PH[ PDPHo PDPH` PD P1藐]L}HpH sLzsH Lhs H LV HUdH+%( He[A\A]A^A_] H vIsH Ls Hz LsHs LsHl Ls Hj L _ @f. UHHdH%( HE1HEdH+%( u?ff. @ UHHdH%( HE1HEdH+%( u1?ff. f UHHdH%( HE1~u H~ HUdH+%( u>?ff. UHAVAUATSH H $ H LNdH%( HE1L IHLLHVDSfnfpH LL HNFHDžP Dxfօ(AÃA@ @tH~ u f~ E A L-fl f @ fAu Dž ARASRRH QH 2 P1HLH0LHxh¸ uaHUdH+%( He[A\A]A^]f A G Et3A *f D Au H} 11脗1A EuA 1= UHATIH5v SH dH %( H]H1t HUdH+%( u|HĠ [A\] @ L H HHtZHPth% = @ t(H_dl 1LH 01袖H -_ ug<H(dl LH 01mff. UHATSH H $ H foM dL %( LMA)EfoM HELPH )EfL)EEAPAк Pj hH{hH 1LÅu HEdH+%( u.He[A\]f D HQcl HX 101蕕n;ff. UHAWE1AVAUATSH(H dL$%( LeIHxXHEdoI$ HC@HECHtoff. fH{@KL4 LLo Mt3I} Ht vHIE I}(Ht `HIE( H{@LH I[]D;{HrH}EHEIDŽ$ H 0]HEdH+%( uH}H([A\A]A^A_]S*N:ff. UHAWAVAUATSHH H L dL4%( LuIx# DhA$ uRH x uq 1D蒌HH HI|$@LL"ÅuHhl 8 uL1HEdH+%( He؉[A\A]A^A_]f D 1 @ Hx蟭A^ H1D/HtHH=q LxLh(L8Hbl LH H5 H81薈A E$ M fA} A A AA fAAfAuEfA W fA fA2] fA0o A@ A f AAfD HAHAfDHHHHLHK\% H HI93 HD Dž" HHHHH(H!Ef&H HA H A@ HH AH `fAA fD H HH H HH H HHH H{ H HH0H H!HsH HH# H HKHH8H HH(fA 6 EEE#A Eʃ)A AEEAAAPALT`l EAAMWAWAVH5 EAWLAQLATP1AVRH AUASAQD AޅHUHPH3D I 4HH fA ЈEfA } A yAI H_l H7 H5] EH81jH HIHø L H)H9I$ LHE H% LXIKD o oH )@o@)`oH0 )PfDfH~)pHxffFH@@)MHAЉHAHAI@}A HHIHuA Љf)MHDEffEfUHM)EfA 8 D׃E@L=@^l H\=DǃM?@HÃTAEAAAEHAAVAH5 ARAFSQLP1RH WL賃H@f. {XfE1H[l HH1H 0S1XZf D HTG Hi[l LH 101謍f. HA[l H 101臍 D H![l LH 101dAlfw/Ap A AfwAJ A AE AU A 2 UHAWAVAUATSHXdH%( HEHal 8 0 L IHHz u F7 H AL IGXH}HEAw` IGXLuL9p IW@H}EHHHX 7AO`LutIGXH@HL9IGHELsM I~( HH@hH x# O p1L誤IF(H IvHK IFpIvhH H觚H L->Yl H? 11Au 肋IvhIVf. HAE MN`H DCV RH 1AvP>H{H LWhLс uHWpf: @ IIFfInLHC flAHBHAZIuH}L! E1HEdH+%( w HeD[A\A]A^A_]DJ\EI GHtHx uA tDCXE;GHsI@DHHLh MIM(E1H C\H p!HRHWl HY 1A 01. IvhIVL-Wl l @ ffE ffE H L HIL)I% I MIM)O$III)JH IC L9e Mf Dm}L}HH]MHALuIMcHUHtAUEHHø Hځ H)L9r=L9 HUI4 H|uH]L}ALuH{ D H H HL9 I4 m H H HHH)H% H HHH)L$HHH)HH I! L9eH]L}HCHHpH)HhoHO0Au 1H 1IA H{IIFHGh fInHGp flLHC HBHA\WA uH}Lff. A CH 1HHA@H<HCIHHx(HK H HpHxpHphH L-Tl HH]L}IA LuH{f D H f= f= f=2 f- fJ fE fE Hx诠 AOHAGL MoX1ILm'H}LD衐AOHH9 IW@HAL$M;$$tI|$ u0 NIHv A L8X@tXI HEH}H AH(u 1rLU5 IB H H}LU{LUAD$MT$ $AB HpHp aHML-Rl H 11Au <- f=0@ fEfuc f- fAp A fD]fDe3 H]L}A LuH{ D AU A fDEfDM D LA D H}H5V LU,LUIB HEdH+%( J sXILRHe[A\A]A^A_]Hs 15qLUOHQl HMHr 1LU01AƇ LU2A LUAHaQl H 1A01衃I H}HtVHr 1pAE~H}H5G !IE(I}( tIH}-IM(H{)DHzr 1@pAMA-HPl HMH 1A 01 UHAWAVAUATSHdH%( HE1f I IKHH I$ H 8 H H#uH H#Pt\HOl H 1A01=H JH HEdH+%( HD[A\A]A^A_] @ H H#Pu@ L{@L2pAƅuI$ LchHUHCpAEH5q C| CxI$ E H` Hx011z1uE~Tk f HfHnH2flfHnHfHnHsUl ~k fl8 C ~k flC0I$ LLdAŅu8{M ƃ f. HH=v^ @ LE=oIDŽ$ _ @ AdAY]&f. UHAWAVAUATSHHdH%( HE1f LwIIwTHmTl 8 HMl H 101 HUdH+%( HH[A\A]A^A_] @ H Ml LH? 133 1H+o 1 HGDuH 1Ol L=k HEIHGEHE I $I 1H;II Hck I9uHEM}(E] E MHELd8H00000000ET$I98 H@@@@@@@@I9% HPPPPPPPPI9_ E AM,8MA9DUL=k LEDOE1LMI KLK 1H; LIE9}܋MDUDpLEED|IcE9~[LEMlH D}IDuMEMH;DL 1AI E9uD}DuLEEDD)EE9EHuHcH< L<f. E~AD$ L-jk DU9LeOI)E1MLcMʼnEKLKT1AH; IFD9} DULeMDE9TIcLEH ML LuED}MILeEMFH;DL 1AI E9uD}LeLuLEE)CL4 I@ EA MM<8DUA9L5k LEDOE1ff. KLK 1H; LIE9}܋MDUDxLEEDtIcE9GLEMlH D}EDuMEIMH;DL 1AI E9uDuED}LEEDD) E A LmMMf H00000000H;I9tH@@@@@@@@I9 LHk 1LE L=k HEH;Mg8Hk JL01HELENl0 H00000000I9tcff. IM I 1H;IIM9u݃E EuE9EHcHuL4 L f D ML-~k Me IIU 1H;II<M9u݃EMLH$ 1OH;I f UHAWAVAUIATSH(dH%( HE1H HEHH L5$ @ , H8IHt L=k L @ IwIHt+Hc`uIcWI U IU Mt\I\$ HQGl HHO 101yH}EcEHUdH+%( u(H([A\A]A^A_]HwIE H $ ff. @ UHHdH %( HM1Ʌu)HHwH> u/HUdH+%( u@H鬔 @ 1HUdH+%( u"HvFl H 101x UHHdH%( HE1MtA HEdH+%( u HS L ff. UHHdH%( HE1HEdH+%( u1 f. UHAWAVAUATSH8H}HuMdH %( H]1ۅ H? } DH}HH HEH Iff. @ , L#6IHt A<$?u A|$ "H0IHt+ D M~LtL] IvIHuڀ} Hh LHh H=> HE1C H} D HEdH+%( H8[A\A]A^A_]H}HHHEH8 uHH}1 D HEL 8MtMeL5Fl H=2h L-* Il HIHt4ff. ff. f D HI#D$u IL$IHuI6 bI>L 1II $Huͻf D UHHdH%( HE1HEdH+%( u H1 D UHHdH%( HE1HEdH+%( uH GBf UHAWAVAUATSH(dL,%( LmIHEHN L5HV HLHH ff. HH = HE1o3Ht L`Iu H MIwIH H^uMtf 1LjHIGH^ 1LtHHhH}? 1HUdH+%( H([A\A]A^A_] IG @ HAl 1HHe 01 tH H} HAl H; 101sH|Al Hw; 101sf. UHSHdH %( H]HH=t QHtBH1 iH=s fQHt 1 Hif; fCtfu 1HھT t P HEdH+%( uH] D f; tf{ t @ UHHSHXdH %( H]H1 8111HUo)EoCe)EoC fE)EoC,E1HEdH+%( uH]Uf. f. UHHH?H6dH%( HE1HH9t)HUdH+%( u!fHEdH+%( uHH[ff. UHATSHHdL$%( LeIH5c [t HEdH+%( u8H1[A\] @ HEdH+%( uHLHH=m [A\]QRf UfHAWAVAUATLeSHH=]H8dL,%( LmI1)EHE 6OLH=q L蔉H}IU AEH9s4H4RI}HHH9HBIu H>H IEH}HtOMEIE1L]IPJff. I4ˉIID)HHHpH9rMUI1H}9IuI} H ?l HE KLgI} u`L51@l 1HHu I>I} Z LE1nHEdH+%( H8L[A\A]A^A_] D I}E1E1f D J41H߹ A A H蝃I}IuHJEwMHI9rH ) ?JIMIuHL H DA 'ff. ff. AVIH9 HH9:tA5m H LLhmMHپ L%>l H~ 1I<$s=m fI<$ H * Z^ 71km d1xfL=q>l 1HLEH I?I} <LEA.I?A H '` 11H$` f. IEI? HM H 1HHD9rH=l < H=( H|I>H _ H_ 1 > A i1H _ Hy_ EQIEI? HAM H1H +f. UHHdH%( HE1Ht< t$G$HG(HUdH+%( u f. ! uր" u1ff. UHHdH%( HE1 t HG@HHUdH+%( u f D 1W UHAUATSH H $ H/ dH %( H]H*Ht(HHUdH+%( He[A\A]]f HtgIIHtHLI S L L 1L LNZYlLd @ LIٹ L] L萉If UHSHdH%( HE1>Wv?H^PHt6HFP HfHEdH+%( u,HH] f. HEdH+%( uH]f D UHAUATSHdH%( HE1H IH H8H? u7 ftsH HUdH+%( H[A\A]] @ fuMl$PIE Ht6H8Ht&Y4I|$8HtIu H#]I|$8 @ 1 @ HI|$HL(xIE H8Huf UHAUATSHdH%( HE1 E HH LoPI} tXI}E1Ht$Lg MtIu(芉LHUHkIċEԉHEdH+%( u9HL[A\A]]f D HW8HHL@'yff. E1f D UHAWAVAUATSHxHxdH%( HE1 LPHIAI? T IGHt;L; r6L;`s0LsHIp H Hs8I9L6I989 LuLCHC8I?LL {HMHt3y4 HsHLt`HAK|% AE)H9Hy HxMB LxL xHUdH+%( Hx[A\A]A^A_] @ HQH+ L8EHC8HsHM;p L0Hp HHoHpDHpoHp @ HW8HHLp%Hf D IGHsHLx4 uHPH+HHK|% AE)H9Hx HxMB UHAVAUATSH dH %( H]H_hr D3Et*HEdH+%( HH[A\A]A^] LoPII} IuIUX H H 9l HF y H HK( H K1HK4IM(HC8H oBHB-HCfH~CfH~H9 AA)B*DsfC0C@ CHID$8Md$HHKL0I$p H I9HW C2I} Ht HCHAE1C@ @ H H% HW8HHLx#1f HJAD+6A)<f LBI$p Z fHC 1C Cf. HC( 11C1 f D UHAWAVAUATSH dH%( HE1 HH LoPIIM} M| L0L?ID$8LLL H@DžpX HHH H6l HF z H HU H UPUHXHEHz oAHA-HxfH~EfH~H9 )tA*Md$HEfHUI$p E EH I9ƋX HpEH9HHG| WvU@ L $HCP1HUdH+%( l HĨ [A\A]A^A_] D H H L f D HpH{HH HLHLHH)H)Hbf D 1H+)f. L?I$p Džt f1HDžx E @ HE 11E 2 p LfL HW8HHL x M} Mcff. @ f D pDD gf D UHAWAVAUATSHdH%( HE1 R HG`I > H_pD3E LoXI} w IuIMX H H3l HF z H HS( H S1PS4IU(HC8H; oAHA-HCfH~CfH~H9 AA)A*DsfC0C@ CHID$8Md$HHSLhI$p H I9C2HEdH+%( HH[A\A]A^A_] D IT$8I|$HL> x I?Hujf1 @ H H HIAD+6A);f LH=I$p Z LPI?HxIT$8LIgf D fHC 1C CfHC( 11C1 |Ff D UHAVI AUA ATSHdL$%( LeIKH0 LHHHH Dk$ Lc(KHCHH H5t 'H{H5 Q HCxH{H5Q H H{H5? H H{H5P H H Ht:Hk HxH5k HHHk H H)H) HHEdH+%( u>HH[A\A]A^]H+l H H.P 01]H&H1f D UHSHdH%( HE1Ht'HGxHwHHtG!HHC! @ 1HUdH+%( uH]\ff. UHSHdH%( HE1HtOH HHtG"HHC" H{&fH%HEdH+%( u$HH]fHEdH+%( uH]f D UHHAVAUL ATfInISHH dL4%( LuDuHW8HUHw0HWXH@fHnHHO@flHWpG`HoXLGHHHPLOPHDž Dž@ Dž oP oH0o@@(HPP8oH`HXPXHo@p` hdH xHU U fUP\UH HUH HUH H H HMu~HH HU1HtHHHE1HUAD$(ugLEC H{HHELEt5 C HUdH+%( uIHĠ [A\A]A^] @ Hf I|$f @ HE Q ff. UHAUATSH H $ H0LO dH%( HE1VHI HII̺ ex H8GZYH H5eL HHkHtnH5L HWHt/HHt HIE HHt I$Hb HUdH+%( u+He[A\A]] @ H5K HHz1g UHAWAVAUATSH8H}dH%( HE1 Hl HHEL5 HEff. Hh IH Ml$L A|$HE HE tHvItLBuHMH}HULTtHMLH#f H57K HHD1^HA&l cH}jH}aH IHQff. fHEdH+%( H8H[A\A]A^A_] HELmL%d L=e HE @ LH5J 1]LLYHHuOHEdH+%( uH8[A\A]A^A_]ff. @ UHATSH H $ HdH<%( H}H=J |\H= K5Ht=IHL1LJ L YuLH 1")fUHSHdH%( HE1HtcHcHH t8HPHtJuMx xul1uHH=m d R$Hm HUdH+%( H]f1 @ HH .m d 1H$Hf. H)l HD u d H=sm 1#f. Ed I1H=Lm #`ff. fUHSH H $ H dH%( HE1 Ht:LHHIѾ HC H1I#HPH\HUdH+%( uH]kff. UHHdH%( HE1(Ht#HcHH HUdH+%( u @ 1ff. @ UHHdH<%( H}1 H u iwHHuHEdH+%( uH UHSHdH %( H]1 fH wHHuHEdH+%( uH]\ff. UHHdH%( HEHh Ht3H Ht'@1҅tH9GHEdH+%( u ɉ @ 1ff. @ UHAWIAVAUATIHSH(HudH%( HE1HE HXHVGHEH HLHHxL}HE1LH54 HH E1LDtHxHt Ha HtHM$l A AIIuLH5L4 1HHuH}Et)1HUdH+%( u<H([A\A]A^A_]H}H l HMH~ 101R UHAWAVAUATSHdH %( H]1f. H u6HtHHu1HUdH+%( uqH[A\A]A^A_]f D ;IHtHE1E1DHRsHx ItHPHLA $A$A AAuEuff. @ UHAWL=(_ AVL5D AUL-oD ATS1H(dL$%( LeILrH ^ L@8 HEIEMt_H l 8jLE1ɺ H5H!l H>Q PL1XZuHEdH+%( uvHe[A\A]A^A_]fHr^ E11I LHMHUHMLBMt3H5z l 6~A e @ E1ɺ TL^ E11> D UHAWE1AVAUATSHH HHdH%( HE1P HDž H @ I uVLrIHuHHt$%UHH+ HfH1 H l LpHAD+% l LDp; I 8 LD mIHteIUHLbtNL&HttHcHH=* H<HHHDIw0QHHL9QH 1HH l 01NHUdH+%( uNH [A\A]A^A_]HH H\SHM l H1H 01Nff D UHFHAWAVAUATSH8dH %( H]HHE H H HHȃHEHȃyHEI< E1E1L-k % D KT 1HIIIt>It8AtHuHMtHuIHJ<3 or L)@ ; H} u0H} uNDHUdH+%( H8[A\A]A^A_] @ HuJ<31H L)HIH} tHuJ<3H 1L)HI HE A HE D HuML)H? H1}LcO48:Hu D UHFHAWAVAUATSH(dL$%( LeIE E HE H HH II!Af?AV ` ۅ tE1E1L=k 12f D HuKK<,1L)HIŋEIt:It4tHMtLIL or @ f. LAN/A HUdH+%( k H([A\A]A^A_]Ðhi EtfEÀ +H% H1HELH(8 AH8k AJH H1HHHuHMI< 1H)" H)Q @ Emissۀ q HuHMK<,1H! L)CD HI|$ HRemote H(I$HA89H+H1k H HH 1HHHEI< H) @ HH= 1HH UHAWAVAUATISH8HUdH%( HEHF HEHS ÈEHx E1E1L=;k (f K15HIIHt?It9tHuLMtHuILK<4 or L)@ D HEHtd HtRt(LM Hu1H < HIHt&M HuLE1H; 1HIA<$ t,DHUdH+%( H8[A\A]A^A_] L)uHuH; L1/HI f D HuILK<4 or L)@ 1f. E1Ht+HuE1 LI$HuK<4L or L)@ f UHHdH%( HE1Ht8 u(tLHEdH+%( u[H: 1.f D HEdH+%( u7Hz: 1 f. HEdH+%( uH8 1-ff. f UHHATSH dH%( HE1 HtF AAt6u21ۨuTH9 1~HUdH+%( ugH [A\] @ HEdH+%( uKH H9 1[A\]; 1H9 HuH}"AH}HuvHcH)HzQ UHAVIHe9 AUIATISHdH%( HE1LHH)I<MtA 1 H9 1LH 9 1HcH)LwLLHcLKLH8 1HcH)LHLLHcH)LLH8 1HcH)LLLHcH)L@3LH8 1HcH)LLLHcH)LLHq8 1HcH)LLLHcH)I<{QHUdH+%( H[A\A]A^]f u<u udtHH7 1R D H7 1: D H7 1" D H` 1 r D H7 1Z8 UHHSH H^XdH%( HUHD D D A f?AAD Av@@t@p@v@t@ @ H fA 87 f v@,t@0t@<t@@ t@DAv@X@`@t A @L@TAv@X@`f 5 @hA X({x(f @lx( ufA ff. @d @H f v@ t@ HzH Hz 1HUdH+%( H] u+fA t$ @ t@4 D fA E tAFAvp~ ~@Pff@P փ V.ft@lA x( D @&@ f. AV~@\@d~ e ff@\7 @H4 X${x$fubfA (f fA ty P x$x$ fA f D @lf. @lAu*@$@8S@|f @l@( @lă@x˃@yf UHHo~oF oN0oV@owoo dH%( HE1og0o_@ffo~PoF`ffoO`oWPDoffo~poGpfo>wo fAg0?_@WPO`GpHEdH+%( u UHHdH%( HE1Ht+ 9t BJvHEdH+%( uHLff. UHSHdH%( HE1Ht+ H @ J9r 9t#uHEdH+%( u>H] uHH{@HEdH+%( u HH]f UHHdH<%( H} Ht ǀ HUdH+%( uX UIк HSHHdL %( LMIH,SHcH9MHUdH+%( uH]f D UHSHH HXL`Lht#)p)M)U)])e)m)u)}dH%( H81HEIHH( HH@L H0Dž Dž$0 TSHcH9MH8dH+%( uH]ff. UHATISHH HXL`Lht#)p)M)U)])e)m)u)}dH%( H81HEH LH(HH@Dž Dž$0 H0A9~%AT$ )HHH<Ic DHcAT$L9MH8dH+%( u H [A\] UHAUATSHdL,%( LmI6@tWIfAuI@tBLzHHt HuLHH9]uIcEHqff. @ HHUdH+%( u H[A\A]]jf. UHH dH%( HE1 f/v^K f/wHEdH+%( u!^f/v^G M ff. UHHHdH<%( H}HHxLfH* V f/s H,HUdH+%( u7f. \H,H?HfHH H*XP UHAB HHdH%( HE1EBKMGE H v9H H v!HѸ HHv HѸ H DDHEdH+%( uH. 1qf. f. UHAWAVI/ AUIATSHH8dL<%( L}I H % HI H HuHHuYHEWHH9] Hu I|$U^ Uu/HU: Uff/} Pff**LL)YYf/R f/@ f/6 f/, M fI*uH fH*YMU(*XEUf/ Ms_H,YI f()XEf/ sSH,I9t H9sHIF1HUdH+%( H8[A\A]A^A_]\x H,H? @ \` H,H? @ HfHH H*X'fLAfHL H*XU @ \If U HAWAVAULmATSH(dL$%( LeILUHuH.t 1.t<Hi ʚ;H1I $HUdH+%( H([A\A]A^A_]f. LvLLuH L} LLbLE H tPH00000000 )LrgH0HtHHHH)r1ǃH499rf D LLTHU: f ut 0t00 fL 0000D0000ff. UHAUATSHdL$%( LeE1Ht> u%HEdH+%( ? HD[A\A]] @ HH5IH , HIH fA<$ uoA} L HCH Ht H9 E1L-l H) 1Au 4HKAu 1H) 41f D HL*t, fA<$ rHL*_LkAH i D I}Hs[*L/A.A UHAWAVAUATISHHXuHMLEdH%( HUHc1H/ LHa - LlH % LVIH. LLcKT,I9 Hc6'IH LLHMY/1 LHHMHUfAE AE LEA&HEdH+%( HXD[A\A]A^A_]ÐLعH HHELMHcI<I9p LMIME1H}m @ A} H k l MD1Hq' 323MFDHj' 1A2DHMMl$II9O D9} , LIHtA} A LIH - HHHt H% LH[ HELHHEeRLELH9E+ % HU^n U<H HuHRHEHH9] LM^ " M@HEHMfH)f/E uf/5 ]f/ f/ H] fH*}H& fH*EMY"XEMf/X H,EYo"XEf/2 H,H9EI Iؿ 1H9L-!k H!Au DH)H % IF1W0Au MFDH% 1A50DMf LMAb @ \ H,H?<f \x H,H?Bf HfHH H*XfHʃfHH H*XE D L@IH H|HcM| M9 LmE1M} HMHLHUr L-k LD1H# HAu /Au LCD 1MoAH# .M9 D9e~\, LOIHkMHMHUHLLmu4LlA;LMLTfLmf. L5k LD1H# A6=.A6LCDH" 1A .L LmfH k LMD1MH" Eg3LM-3MFDH" 1-LML_ D LMLLMpLM E1cE1UA$f. UHAUATSH(dL,%( LmIHtbH}Ȼ <H}L$f, Ht HxL9rHcA] HEdH+%( u#H( [A\A]] UHHdH%( HE1HtH;7r+HWH9H!HUdH+%( u D @ UHHHdH %( HMH Ht 1HUdH+%( ugf. t>~3HcHH7ff. H;rHwHtH9sHH9u HEdH+%( u He* UHAWAVMAUATSHHXHu% HUHMdL$%( LeEHuHHIECH } I E H1Ʉ f. <,HuɉM H踱H MDIEh MLE1HELuLmIDeE̾, LCHxz I% D H ak I<, AuLH= AHE9c M HEH Hp HuHx MLx uHL EtKtGHEQHH IT~p Lflff. o Hf@H9uEHuHEAL(1HUdH+%( \ HX[A\A]A^A_] @ A I LmLUL0Hk H& 1017)LLmLULuDeLuux EFLmIcLULHHLuDeLLULUMaQIEHITf HxH98;HH9uLM_M|HLMHELUM9Hk H 101,(f UHHdH%( HE1HEdH+%( u E1-# UHHdH%( HE1HEdH+%( uUHSZ/D IHHLH HHH Hi ʚ;I)HS㥛 II1IHc I<ff. UHHdH%( HE1HEdH+%( u=HSZ/D IHHLH HHH H Hi ʚ;I)1y @ UHAWAVLPAUATILSH dL,%( LmI1d L`LL蘹HtsLuL H} LHtSDXLLLYHa L1I-HEdH+%( u HĈ [A\A]A^A_] D @ UHAWAVAUATSHdL$%( LeI- ALL51/ Mf<?tlHLLx@t*<\uAGHS IGHLx@u HEdH+%( HL[A\A]A^A_] D LH}D 1ZHcЅy0Hq H}7 rAЃ? HOHH)H+ K 1Hff. ff. f oHH9uЃAH9 AA)EPAv NN EADLA LcD@F D A9}pMcDHFDAD9~[McD@F DID9~FMcDHFDAD9~1McD@F DID9~ McFDA9~ HAH\3躹 D HK1f D HH9uH\3L"HE11 mff. fUHg HHH]k dH %( HMHH81 A UHHdH%( HE1Ht?HGG HG@ HGG( HGHF(G8 Ht HVH;<tHEdH+%( u&ËG HF4HGHVHF@H F0 UHHdH%( HEHHUdH+%( uNff. UHHdH%( HEHG(Ht&HWHHt@,HUdH+%( u D 1ff. @ UHHdH%( HEHG(Ht&HWHHt@0HUdH+%( u D 1ff. @ UHHdH%( HEHGHUdH+%( uMff. f UHHdH%( HEHGHUdH+%( u ff. f UHHdH%( HEG8HUdH+%( uff. UHHdH%( HEH HUdH+%( uf. UHHdH%( HE1H>HEdH+%( uLff. UHHdH%( HEHF(Ht!HVHHtx,HEdH+%( uH=5 ff. UHHdH%( HEHF(Ht!HVHHtx0HEdH+%( uH=~5 1ff. UHHdH%( HE1H~HEdH+%( uKff. UHHdH%( HE1H~HEdH+%( u ff. UHHdH%( HEG|HUdH+%( uff. UHHdH%( HE1~|HEdH+%( uff. UHHdH%( HEH HUdH+%( uJf. UHHdH%( HE1H HEdH+%( u UHHdH%( HE1HEdH+%( uff. UHAWAVAUI@ ATAHSHdL4%( LuIH D`A|$LHHchHCH C LHD8I IF(L+C4 Ht IVH; tHC, 1MtLJ7#C$E<$HEdH+%( u HH[A\A]A^A_]H=2 gf UHATSHdH %( H]1H I1 I$H HxH fHǀ HH) HHI$H@( H@@ H@H H@T H@` @@1HUdH+%( u5H[A\] s f D [ ff. UHAVAUL@ATISHLH dL,%( LmE1H L oHH HxH Hǀ HH) LHLH3茻HfH@( H@@ H@H H@T H@` @@1HUdH+%( u9HĠ [A\A]A^] @ K f D 3 f D UHHdH%( HE1HEdH+%( ukff. UHATSHdH %( H]HH(HtlHC HPH9Ss HEdH+%( u}H[A\]f D L`HJ4 HC(HtVHS fH @@ @0Lc fH HC(Ht fo H Ct蝿H=/ 1 UHAWAVAUIATSHHF(dH %( H]HH HSL$M HLD8IHC(M,$AD$4 Ht HSL9$t ID$, 1MtL<31҅HC(AT$$HSE>HЋB C4HBHHC@H HS C0HEdH+%( u\H[A\A]A^A_]f. H(HSHC( @ H{L$H;I$HC(H"EHSL$H UHAUIATSHH~(dH %( H]HH HC HSHHH9 HHL9tZHt'HC@S0HSHC(HK@HHHJK4J L(AE IU C4IEHSHC@H CP C0HEdH+%( H[A\A]]f D L`HJ4 HC(H HS fH @@ @0H{(Lc HuIMtHCHS D H HC(Ht*H fo H{(CHtHSмH= - d @ UHAVAUATSHdH%( HE1H |7 IH |7 u|Hֿ@ IlIHtnLhLHfnLhH fpH@ @( H@4 f@rHEdH+%( uHL[A\A]A^] E1H=g, f. UHAVAUATISHcHDkMcHLdL4%( LuIHx HDž Cڃ; It$HH)H& 8 1Hff. ff. f D AoHH9u9 )rvI4 H4уȃtvHcA P9~dHcA P9~RHcA P9~@HcA P9~.HcA P9~ Hc҃A 9~ HA1LLf .Ht_@ HUdH+%( uDH[A\A]A^] 1f D AHH9u11H=* H= UHATSHHdL$%( LeI HUdH+%( uHLH߉[A\]谹 UHAUATSHdH%( HE1H IH~(HH HF HNHpH H9 HH8 t8HC@S0HK(HSH{@HH0H~{4~ Ht HBHCHL AD$ I$C4ID$HSHC@H CP C0HEdH+%( H[A\A]] LhHJ4 LHC(HtrHS fH @@ @0HCLk H H{(HHS VHC(Ht fo H 1C1H=j( D UHHdH%( HE1HEdH+%( uff. UHSH(dH%( HE1HtgHF(HHt HVHH;8t&C u-HEdH+%( uMHH] H C tH{HuHu HEdH+%( uH]>ff. UHSHdH%( HEHG(HtlHWHH<Ht\HHS(HCH HtHHCHt2HHt)P S4HPH HS@H HCCP C0HEdH+%( uH]臶 UHSHdH %( H]HH(Hu: D HHeHSHC(HH M H{(H HCHHuHHC( H{`HHC` HfHC( HHC@ HCH HCT CCHHEdH+%( u H]1Ð1藵 UHHdH%( HE1HEdH+%( uɸ Zf. UHAWAVAUATSHhFHdL,%( LmIH uqE}LAEH EuAEL I} I} IE(H IUHH P AU4HPH IU@I IEAE0LH " M L5 L HEL LZ L 3 L= ID$@LeMHEHAE0H}AuLHcC fA<B A tAuhI}pHcE$VD9t`ff. ff. ff. ff. ff. fACf]~HcA HCHcfA;4VuIPHCf _H}MHEABuID$pHEIcD$hABH}HMHI$ H)AT$8AT$0H I|$@ H= HcH>LIUIE( @ I}H LIUHIE(H'Hk H IEIE(HH{k I} H IEH}HI+$ EAD$0IT$ID$(H4Hy8 IcD$4LiIT$@HELmII$ LpHEI9 HELmJD(H9 HHUDi4H)HxE HN HpHUHEA|$LID$@}H9E HEHEHE G A HcufA<r tHEAt$hID$psDmHAFD9uh ff. ff. ff. ff. ff. HcH HcsHE,FD9} H p]@Ѹ| ff. HUdH+%( U Hh[A\A]A^A_]MLeLEd$ʤLHH觑DHDHHH AD$0H}ID$pHEIcD$hHE1j/ `* V+ L- B> 8< .& $^ , ) ( % IL$Ict$8 I$ L_ L X L L YHULmH\ } s i _ UMLeLFLHKLH@!f. LH q H MLLIIn 1L H{)D3 EA$ A@HEH}EHEH9HcEHE IT$HcA AD$4HA8 DhE HE H}HEHWH)H, DHHH1oH}HH9uDHMHHHHMA x)qxv)HMHuH H xHMHσt{HM HA9~jHMIOHA9~WHMIOHA9~DHMIOHA9~1HMIOHA9~ HMIOA9~ HE@GIT$ID$(H4Hy8c QD) ID$@DmLI]6 FIAD$HcHUTHUHID$tFHzHr(McMLL$HB@At$)σ-I|$H)IAD$ uID$ H=! @ A͉LIԸ 9NƉA$Eq Ic1DmMH}AH}I}xյxLx L q L L I}Iu(AH4H}Hv>HH}D9uMDm AD$4 A HE 1A8 HyAD ;AC AD$4H ID$(IT$HIcD$4HRD IT$ID$(HH@HEI$ ER HcEH}MAT$LHHEID$@H9 H}AHE A IcfA<r t HEAuhIEpsHAFD9u(<HcH HcsHE$FD9tH4 p]@A@HEAHEH9EhDHEH}HE YHMLHcE诳HMIT$L L x L HAID$(L HHzH EBAD$4DRHpU+HpHE HcEHEIcHx_f D I|$fL L L? L r HE8R I|$IT$ID$(H HxHU HyIL$)L L { AD$4HƉL L [IL$ID$(H ȉq KAD$P L贫L- L & L} L V t?AD$LI$ HIT$@ $H}IcD$4HH}HEQA|$P I|$LL L L L H}1H}1DxAHuD1 H} HH9uDeMDmI|$ UL7 L 0 L L b AT$4IL$ID$(E H4HQ EI|$LIL$ID$(E AT$4L L H L L H= D DMH}DmIL$ID$(VE HHcHx IL$ID$(AT$4H ȉQ R1AT$4Q :H= H裦HcEH}AL$LHHEID$@MH9 LeIAE AAHcMfA<J t H}OhLopK}HA4F9u<Pff. f. HcHV AHcKHA<F9tH 4H]AA@IEL9mXLeHcEfA<B HEtAD$hHEID$pHECEHcA V9t#H=L HcH OKHcE,VD9uAP]tu!HEHEHE A HEHEMID$@H= A|$ H HHcHE_H= AT$49f D UHAUATSHdL$%( LeIuOHULA H LE1膔LfHnHUdH+%( H[A\A]]kIHtLH踈t$Hk 1LHr 01HL H q H}EtfH~g fH~Pܣff. UA E1A MEHAWAVH AUIATL% SHH HHH /dL<%( L}LHXDžP DžhL`J EI9! LD@H)HHLhI' ' MI9LOLL8HI|H LHHMȇL8IH`HLLMC L0HH8LIIN,L胇HXH8L0D@H9t+HL@D`LH8L@D`LHMKO|=J II9I L`HAT McCD h h h= = B= wHH < H B f. H) LcJ )IHHLL@ H HcH>f. HcH z < Džh H? DDElPfopDžhAGIP f. HchH = wHH @:4zH B P @ @! @uzHpL@LHPLhL@LHPLh6 H B \h PN DžhLPL- LH <uI?蔏MFIICDt wHcH <F L9 CD < t<!uI?߳A_~ / f(fTf.7 f.% f/{ sff.z? / AG9 fTf.+ I7IL8L@LH LHL@L8Iff. @ LLH5x M)HH)LPLx@H% AB H wHcH5 : H DIf D H! B ulPtqP H A 1j D PtKhfH J Džh Džh H4k Ht H L@01LHLP[LPLHL@CDe @ HQ fopLPIADžP LHA D h HchH < < MA Hp&M9tOH z $ <wI?IIM9t"IE <uI?II7M9uHXI9tL HEdH+%( Q H D[A\A]A^A_]f D H HpL0L8@LHbL0L8h@LH @ H DpP A H < < MIAE1HpL@LHPLh謯LhPLHL@+HpA Džh Hp躊MI)HchE1䁽h wH * D / HHAO/ AOAWE1]f(AGfW MMWAGA_~ f(fTf. V f. f/L sff.zT / AGtfTf. ^E1A_~ f(fTf. f. f/ד sff.z / AGtfTf.`H,fE1H,HHH*/ AGt ~ ] f(fTf. AOfTf.\E1;/ AO ~ f(fTf.AGfTf.XE1/ AO ~K f(fTf.aAGfTf.Mf/ E1A_~ ] f(fTf. AWfTf. 7 f/ 1f/n f1ҹ f.El E19f AW~ b ʑ AGf(fTfTf. f.df/ sff.z( MWf(AW~ g AGf(fTfTf. f.f/ A s ff.ztL8IL@LH=u E1LHL@L8/ AGE1A_GIG/LHL0HL8H@H@H HE1L8L0LhL8Iw L@/LHHLHL@L8IL8/1L@I7LH봀/ AO ~\ ď f(fTf.rAGfTf.^YE1AOf(fT f.M f.n ? f/h sff.z MWAGLIL0L8LH@GI??LH@L8L0LIG/LHL0HL8H@0/ AG ~ f(fTf.6AOfTf."Džh 'h HchH 4HϋP8@ D IwIL8L@LHIL8L@LHL8L@LHfE1/ uAGvHܺk H U H A 01HchA/ AG)HA Hch/ AGfA.GL8L@LH0 III?LHE1L@L80f. - f/! ff. f/ f. fE*f.zAGf. E19f.zAGf.1f.zAGf.nf.zAOf.f. f/sff.zf/D ff.8f._AOf.Jf/% sff.zL8I?L@LH:/ AGf/%4 ff.}I?L8L@LH%LHfE1L@L8HI?LL0H0L8LH@螮HLL0L8H@LHӉ I7IRIH"f1 f.Ef/# Hsk H L8L@01LH/ LHL@L8I E1LHL@L8AGMLIL0L8LH@蛣INIL8L@LHtLHL@L8赎Hvk H D`A 01H`HchHI)HI)f. U1HHdH%( HE1Ht5ff. ff. D HHHH)H HuHEdH+%( uHff. f UHHdH%( HE1HUdH+%( u襍 D UHSH H $ HdH%( HE1=km t. km ft7 HEdH+%( uPH]fHI 1L HV1Hvjm jm U1H5H={HSHdH %( H]1H=HCHUdH+%( uH]蛌ff. UHAUATSHdH%( HE1HtsHG IE1HtCff. IUJ Ht! HH{H[HuIE II9rHEdH+%( u,HL[A\A]]ZHEdH+%( u H[A\A]]ًf U1ҹ HSLMLEH(dH%( HE1HE HE H}{H}|{HEdH+%( uH]` UHAWAVAUATSH8dH %( H]HHE HE H IHH 譤HI袤I9 IF HMHE HMH IVHML<M| Le fMMtgIWI7M LMHH}AzH}zEtHܣLԣ1HUdH+%( uVH8[A\A]A^A_]fIF HEHMH9]L蔣H D HLI f. Hf D UHHdH%( HE1HEdH+%( u H?=nȉ UHAWfI~AVIAUATI SH(dL,%( LmAHE HE 6Ht{L8I<$LMLEDh HL@ H蕥Aąu=H}4yH}+yHEdH+%( u.H(D[A\A]A^A_]f. HxAf UHHdH%( HE1HEdH+%( u ɺ ˀ覈f D UHAVI AUATSH dL$%( LeIHE HE H M,$HL(iHH fInI>LMLEAD$C HC_AŅuWHȯk I $H MD$01H}wH}wHEdH+%( u+H D[A\A]A^]ÐHwHwA葇 UHHH?dH%( HE1إHUdH+%( uQ UHAWAVAUATSHdH%( HEHHP HtrIILmE1HHJ HuMf D H[Ht7H3LLt1HUdH+%( u+H[A\A]A^A_] D IHP II9r 褆 @ UHH H?dH%( HE1HMHUHE HE 莥H}\vH}SvHEdH+%( u=ff. f U HATSHdH4%( Hu HtP1H5HIH=*HH= w"HEdH+%( u HL[A\] HuE1覅f D UHAUATSHdL,%( LmIH?HG Ht>E1HWJ Ht% HH{H[HuI} HG II9rHEdH+%( uH[A\A]]鵝f UHAUATSHdH%( HE1H IH蒧I} HG HtIE1ff. HWJ Ht% H_H{VH[HuI} HG II9rHEdH+%( u,HL[A\A]]_tHEdH+%( u H[A\A]]@ UHHAUI ATSHHHk dL$%( LeIH 01HuH{¸uGHuLHM1HLIҲHuLHuLH}诣HUdH+%( u H[A\A]]|ff. UHAWAVIAUATSHHdL,%( LmI0' Mm M AAE tVu(HӪk AE HH 0 HEdH+%( HD[A\A]A^A_] D Hk MEHٿ AE HH 0 fL=Qk MEH1HG A7A7Hٿ H6 1sIULLAE A7uNAE Hٿ HpG 6'Hҩk Hٿ H 01AHH 1ʁf. UHHAVI AUIATSHH`k dL$%( LeIH' 01HuI|$jÅuEHuLxHMк 1LIRHuLHuLHH}/Mt LL?HEdH+%( uH[A\A]A^]ff. UHHdH%( HE1HEdH+%( u諀ff. UfHHdH%( HE1*GHEdH+%( uff D UHATSHH dL$%( LeIHH=u8 ? HH=u8 (` HH=8 y HH= HH= c HH=g8 HH=98 HH= 8 HH= HH= p L%k H11Ht A4$Zz 蛢fL%k *A4$Hٿ HT EEHEdH+%( ; H [A\]f ;trx L%k f D HtfHfL%[k *nf. L%<k S I4$A|$ 蹜uL%k f) D L%k @ [fL%k H* @ ;fL%ȥk @H* fL%k @H* +L%k L%tk }f UHAVATASHH?dH %( H]H1Hڛ E1Eu'HEdH+%( HfIn[A\A^] @ 3_IH @ HʕHt}H]HH @ H褕@ H /HL /fu v fI~HlLE}Q v fI~?f D HL u%av fI~f. w fI~Y|-w fI~f. UHATSH dL$%( LeI謝H脎HtWHLH!ft1HEkEHEdH+%( u*H [A\] u f D w {f UHHdH%( HEH~HtO@vIAAAth@HDAuH9spH H1H v H HEdH+%( uG H vH D v@H f. H z UHHP~Ek dH%( HEH fHnH flfHnH )EfHnH ~Dk fHn1fl)E~Dk fl)E~Dk fl)EwHcHDHUdH+%( u"zf UHH ~Dk dH%( HEHR fHnHL flfHnHbg )pfHn~EDk Hf fHnHi flfHnHl )EfHnHa ~Dk fHnH flfHn1)E~Ck fl)E~Ck fl)E~Ck fl)E~Ck fl)E~Ck fl)Ew HcHpHUdH+%( uxf UHHdH%( HE1G<v-ҁ tAHUdH+%( uRƝf D HEdH+%( u1H HEdH+%( u@@[xff. UHAVAUATSH oFoVoN(on8o^HovXfdH%( HE1ofho~xfffffffofsffH~Hu#HEdH+%( H [A\A]A^] L5 IHI LL H=S L L I$ H_ I$ H I$ H I$ H ID$Hm ID$HD ID$HR ID$ H ID$(H ID$0Hi ID$8H ID$@H# ID$HH ID$PH ID$XH ID$`H ID$hHS ID$pH ID$xH I$ Hj I$ H I$ H I$ HY I$ H I$ Hs I$ H I$ H I$ H fH*Yro Ha fH*^ EUEHHEdH+%( H L [H9 A\A]A^]o fH*Yn H fH*^ EEȾ LHH o fH*Yn H fH*^ EwEȾ LHHx 6o fH*Y2n H fH*^ EEȾ LHH n+u fH*Ym H: fH*^ EEȾ LHH rn fH*Ynm H fH*^ EQEȾ LHHR nE fH*Y m Hr fH*^ EEȾ LHH m fH*Yl H fH*^ E͗EȾ LHH LmID$`H Z fH*Y?l H fH*^ EbEȾ LHH# lID$hH fH*Yk H fH*^ EEȾ LHH vlID$pHP fH*Yik H fH*^ E茖EȾ LHHM lID$xH fH*Yj H fH*^ E!EȾ LHH kI$ H fH*Yj Ht fH*^ E賕EȾ LHHt 2kI$ H9 fH*Y"j HX fH*^1EEȾ LHH j fH*Yi H fH*^ EEȾ LHH ej fH*Yai H fH*^ E脔EȾ LHHE jID$ HQP fH*Yh H fH*^ EEȾ LHHڿ iID$(HC fH*Yh H fH*^ E讓EȾ LHHo -iID$0H fH*Y h HG fH*^ ECEȾ LHH hID$8H: fH*Yg H fH*^ EؒEȾ LHH WhID$@H& fH*YJg H fH*^ EmEȾ LHH. gID$HHT fH*Yf H fH*^ EEȾ LHHý g a fH*Y}f H& fH*^ E蠑EȾ LHHa gZ fH*Yf H fH*^H 5 LH fI$ H fH*Ye H fH*^H LH ofID$H fH*Ybe H] fH*^1E舐EȾ LHHI f4 fH*Ye H fH*^H LH e fH*Yd HxqfH*^H LH geSHHfHH H*XHfHH H*XHHfHH H*XwHfHH H*XCHHfHH H*XHfHH H*XSHHfHH H*XHfHH H*XHHfHH H*XTHfHH H*X HHfHH H*X\HfHH H*X$HHfHH H*X<HfHH H*XHHfHH H*XHfHH H*XXHHfHH H*XHfHH H*XHHfHH H*X6HfHH H*XHHfHH H*XKHfHH H*XHHfHH H*XHHfHH H*XHHfHH H*XEHfHH H*X HHfHH H*XBHfHH H*X HfHH H*XHfHH H*XRHHfHH H*X)HfHH H*XHHfHH H*XHfHH H*XvHHfHH H*XHfHH H*XHHfHH H*X=HfHH H*XHHfHH H*XHfHH H*XiHHfHH H*XvHfHH H*X>HHfHH H*X@HfHH H*XHHfHH H*XtHfHH H*X<HHfHH H*XHfHH H*XHHfHH H*X HfHH H*XHHfHH H*XHfHH H*XHHfHH H*XHfHH H*XHHfHH H*XHfHH H*Xcff. UHAWAVAUE1ATSH8oWoGUoO(oo8Huo_HowXfoghoxfffo o dH%( HE1ffffofsfo fH~o ffffofsffH~H H I E1H t1HuA H X H (2 HcL H1IA1ff. f H HDI| HHuI$ I$ I I$ I$ I$ K I$ I$ I$ M I$ tGHEuIcA^H W LͲ D)HH EHEHcH1 1AFAI$ t@UH}IcH ZW L D)HH EHEHcH0 1AHEdH+%( H8D[A\A]A^A_] HH 0 1HcuL H V HA I衈I$ AIDHcA )HEH Hf D EH}E~D)EIcHHU赅EH}EH5gV H ˇ IHDHcuH/ 1A @ HUIc1D}A^HE)HEEH}IcIH V Hk AHEH/ 1踇AI$ HUIcD} A^HE)HEEH}IcIH U H AHEH%/ 1SAI$ aHUIcD} A^HE)HENEH}IcIH =U H AHEH. 1AI$ HUIcD} A^HE)HEEH}IcIH T H< AHEH[. 1艆AI$ HUIcD} A^HE)HEEH}IcIH sT Hׅ AHEH- 1$AI$ _HUIcD} A^HE)HE EH}IcIH T Hr AHEH- 1迅AI$ HUIcD} A^HE)HEEH}IcIH S H AHEH,- 1ZAI$ HUIcD} A^HE)HEUEH}IcIH DS H AHEH, 1AX8] UHH0~'k dH%( HEH) fHnH1 flfHn1)E~'k fl)EwHcHDHUdH+%( u\f. f. f D UfHAWAVAUATSH(H}H H dL4%( LuIHG VhHEh LxE1E1IA7AI AE9fhMcK|m H~IHV IcFh LEH@E1M4ff. MHM MX118f IL H< M8AHqHy H Ly(Lx0HHI9tQHH< HIHIcH@HHIsEtILH9q uML9Q(uHHy HI9ufIM9SLLAHEHz E L}L5ςk 1L- ff. IO(A6L MO MG1HEH H IO(ff. ff. f D HPHtwHH;HrHPHuHPfIHuLAGL:I0D9fHEH]HX1HUdH+%( H([A\A]A^A_]f D HPf. HU1 IcIL<@IM911LR@HEHo=f7m t*1HE[^YLmEHk 3 H= H7m f D UHHdH%( HE1HEdH+%( u H{'Y UHHdH%( HEH @ HtH;ps%H@HuHUdH+%( u f D H;p r H@ @ @(Xf. f. f UHAVAUATSH dL4%( LuLw IH A AƆ 1LI H5ɻ H5{ LMMl$H "k H5O MEfHsHHtsL蛘u{A Idž HuueHiE ʚ;HEI 1HUdH+%( umH [A\A]A^] @ AƆ f D AƆ LH= 1FH!k HJ 101g D A W/Wff. @ UH[ HHdH%( HEH!k $ff. ff. HPHHt#9xuHEdH+%( uHf. H Vf UHAWAVAUATSHhHFdL<%( L}L>HE L9 H IHE1HE HMHIHEHEHEHL}Lx HIs HMmuIMHMH HEL}L(IEHEIff. LLHAԅ~"M/IE MHt)ILHLAԅM7IMHtxI Mu HMHEHQHMHPHLmHuHEHLnHuH H HMHEHHMHMH,I M.LuHI HHLyIHuL1INHEdH+%( Z Hh[A\A]A^A_]IMLmILxH( HEHMHELuM Lmff. LLHAԅ~"M} IMHt1ILHLAԅMu IMHt/If. M7LuL}IFLuHt HEfM>LLuLuMMIH @ LHLAօ~*M} IMoHMIHLLAօI] HLkHtIHHNHMLLuIvLvuS D UHATSH\H dL$%( LeIH/t6H` 8UH H 1IHzk 01%HL \t6H` TH Hg 1IHzk 01H(Mt6H` TH Z H% 1IHOzk 01螬HEdH+%( u HĠ [A\]^Rff. UHATSH\H dL$%( LeIHt6H` TH H 1IHyk 01 H4t6H` SH z HE 1IHoyk 01辫HLZt6H` SH 5 H 1IH*yk 01yHKt6H` JSH H 1IHxk 017HEdH+%( u HĠ [A\]P UHH dH%( HE18t6Hp RH _ H: 1IHdxk 01質HEdH+%( u}Pff. f UHH dH%( HE1=Nt6Hp FRH Ϲ H 1IHwk 013HEdH+%( uOff. f UHH dH%( HE1=It6Hp QH ? H: 1IHdwk 01賩HEdH+%( u}Off. f UHH dH%( HE1]`Ǹ t;t4Hp <QH H 1IHvk 01)1HUdH+%( uN UHATSH\H dL$%( LeIH_t6H` PH H, 1IHVvk 01襨HLz[t6H` sPH ̷ H 1IHvk 01`H舒t6H` 1PH H 1IHuk 01 HEdH+%( u HĠ [A\]Mff. UHATSH\H dL$%( LeIH?t6H` OH H 1IH6uk 01腧 Ht6H` QOH HŞ 1IHtk 01>HLZt6H` OH e H 1IHtk 01H!t6H` NH # H> 1IHhtk 01跦HEdH+%( u HĠ [A\]wL UHH dH%( HE1Lt6Hp FNH H 1IHsk 013HEdH+%( uKff. f UHH dH%( HE1]dt6Hp MH H: 1IHdsk 01賥HEdH+%( u}Kff. f UHH dH%( HE1}t6Hp FMH o H 1IHrk 013HEdH+%( uJff. f UHH dH%( HE1=t6Hp LH ߳ H: 1IHdrk 01賤HEdH+%( u}Jf. UHAVAUATSH dH%( HE1H 1ɸ ff. fIII9r HHH< MŗIHt"ML`1ۉfLHI(耹L9uHEdH+%( u#H L[A\A]A^] @ 0 1A I @ UHAUATS1HdL,%( LmIMef LHI(9AM HH9rHEdH+%( uHL[A\A]].9)If UHAWAVAUIATSHdL<%( L}I|Aą MG LGe萖HH6 LXL ` H ,S AOeAAA}H:IM 1f. A} HHD'Mu3LHDD3"7tDHҙ L1 B LE18H7HEdH+%( u[HD[A\A]A^A_] @ c茕IM @ A D LHJ cBIf D E1GAAvf. f. UHHHdH%( HEHH9r1H9HEdH+%( uɉG UHHdH%( HEHG HH9rHW HEdH+%( u1Fff. UHAWAVAUATSH H $ HXE(LuL}HE0IHM HIHHE8LLHdH%( HEIHtHBI+D$ID$HBH LH H5 L H AD$Ш HH HHǾ L AWL I1跽HL\IXZMZ I>rI {IM.Lki1HUdH+%( He[A\A]A^A_] H8 H ID$Ht"HHtHJHtHBH)f. HHID$ HBID$H B4 HBtfHR(f D N(9t BJvLLLLDZLLlL^hIHH*HrzIf. tHH ID$HG HH HHǾ L AWL I1ʻHLZY^IH M}` Hp[IH LL A H I fA A A 蛠IH A HID$HHtHJHtHBH)IID$ IGID$IG HLA H苟 HfLH 蜈Aƅ I>L HI;D$Yf M}HH ID$I D AG4[f D H(HHxLШmA UHAUIATSHHdL$%( LeI*t-[ LZHt;HC(HL9rLc(L9c0 1HUdH+%( H[A\A]]HCHL9rLcHCL9rHuLcH59 L H5D L H58 LЄx BcH¸H_HCXHJL"HPHKfHnfHnflBH0Lc0' L# LcB@fUHAWAAVIAUAATSH(Hl Hu8dH %( H]LčH 1LDI諒L9t6L/HEdH+%( H([A\A]A^A_] D Lu1DL_L9uHu"I HLD2HxL9uL)t)Hdl LDH9HG8xIHfu1b>?]f D UHAVAULmATISH z 7dH %( H]HLH{tg"Lu{ A4$LH{t=HEI9r1L9HEdH+%( u.H [A\A]A^] @ {hHE D khLu> UHAWE1AVIAUA ATISHH(HMv>LEdH%( HE1m1HOHu?P LL>Av>A$HdHHt H}t?ILHPDIHuE1HEdH+%( u$H(L[A\A]A^A_] @ HEHtL(=ff. fUHAVAUATISH dH %( H]HKM LmLLNvH LPLE1LH L覲HH 1H HHxHH9r( ff. ff. HH9 2BNzHL u׃uҁz GNU uɺ H9HG 2 t H1H) @ tU P LE1H = LLHHLE1H LL蜱HHHUdH+%( HĐ [A\A]A^]HHsHHHTHTHH)H)61AN N 9rH HD HKHH)ڃg1AJ<9rOTTH ck H H 101I D ;f. UHAWAVE1AUI1ATSH dH%( HE1<xZ1Ҿ lj訮IHt;L}HLsHt E1H@LLLHALu1HEdH+%( uHĘ D[A\A]A^A_]E: D UHHdH%( HE1HEdH+%( u1 :ff. f UfE1H $ HAWAVHH0AUATSHx L~dL4%( LuI)0)@L)P)`oFH)oF(HDžp )oF8H)oFHH)ȮH HHL(LHt$HHH9PsH;P ff. ff+ f= f= f> HhHHU Hu`k I H 01豒1HUdH+%( Hx [A\A]A^A_]f fF HDž f(! HDž0 faff. H HHL8 L<LHHN HIF0LHHuLf>y fo HHA HHHE1LH HLLHH t I; ? I; I E Hk1HHHT 1HʞHH: LD?fHH# 1蜞IH Hx H1H(@0Et(HHH;P HHf f> HLE1HHHLHHhL%bk HLL f> IL H 1 ˭L%L HL 9HH HLI8sD;0 H8DDHtB4@ HHM H^tHH訔HHDAT$LAD$ DE1tHHt\k 1LL @ƉQLHIK Hv^ MA9 Ll D HP G HDž HDž D HDž HhHCHHHH`HDž HHHDž HDž HLQVf. H8;VHE[k M H H 01z D HDž HDž D HfE1HpH LLLiLH H f> E1HH H! LLHLLs D ML H1 蕪HHIع LR6HHyLpLL; LLM{HH7L9# Hcu Hc>|%3PHcҋD HO1LHϋ LHff. H9H1HHHLLL9 I9! HpH9rLHLLLSLf HE1LHH LLLH f+ f HDž f( HDž0 f HHPE1HCHC HH @ f>CH rHHHǏHDHL8H\k P@M DE1t:HWk 1L@ƉqIH HY MMH1 L 诧E?Lc ELf D HE1LHH m 謤LHH @ LKIHgL {HILENI E0 LU+HP\f= f= f> HHCHHHHHH: HDž HDž L+JLHILϾ {LHILEHDž HDž j@ X%H`HHH1H HpHxHLpILhIS @ pu9HHH9HBHt HHH9r HH9 IL;sLDHHuHxLpLh*Ld~a1H赔HE1LHH ~ H LHHHHH11H DLH [LHHoHH,LHPB1HLH`[1HƓH LHHH H HI_rLHHH LE11LMH HʉHcHH HDAHHPHH; rMD D HHHHHFf D HDž HDž %HDž H8!MH3Aܾ LL qH8HHLtmC ڹ fo5 HfnHfp HfoHfHH9ut P9sу9sL0H s LLoN0LVHL!LLZ; HMDH HLD ^LWHDž HHHxLpH)HxLhHHxIH HH;P@*< t AA+I-+HLLs0L"_(H8 KL1mff. UHATSHHTk dL$%( LeIP@ uD HOk 1L @Ɖ葟HHt)HQu]HEdH+%( uXHH[A\]fLCHHuHEdH+%( u+HL [A\]lt @ 1 @ HxQ' UHAWAVAUATSH H $ H8fdH%( HE1)H HIH1H%U 1H1CAą 1Ҿ 誚IH LHADž~HIFL莗D ulHEdH+%( H8 D[A\A]A^A_] @ LHߺ Dž LLHDžxem L6 D H f D HMk IH g H2x A01A A7H~Mk IHN 01AA}%ff. f UHAWAVAUATSH H $ H H $ H8H1IdH%( HE1蓠 LL'f HcI L諛L9R L]H 9 DAAVAuAtMA ~HRLk HM HG H A V1~~XZ Xf L!]H GNU us HI9IFHH\HH9H 1H)Hуs| t HE1HP5 LLfI9ff. fAHEdH+%( unHeD[A\A]A^A_]ÉH HD1 HqHH)ȃh1AȃJ<9rPA111|7# UHAWIAVI1AUIATSH dH%( HE19A 1Ҿ A蠖HH H0tGAH艓DHEdH+%( HĘ D[A\A]A^A_]f LmHLA[H HH@E1LH t 蜗HHy1HiH0LLE1Yf. HIk MH Ht A01{& HiIk H HVs 101{ Ap! UHHdH%( HE1H tHUdH+%( u D HX !! UHHdH%( HE1H HUdH+%( u @ UHSHdH %( H]HuCH{赑HEdH+%( u {H] @ UHHPdH%( HE1E fHUdH+%( uQ UHAWIAVAUATISHH HHDdH<%( H}HM HL AŅ A$ D1Ҿ DHH LpHLXH1 A$ uA$ tvH?Gk H 101yADŽ$| HQD HH11蘚AŅ=| A$| @ A$ A$ @tHKk x V H6I LHILJ M H $q AI A t1I LHI M H p ILJ A t1IWhMG`LHI H p IG` 譓Alt1IGX A$ AH HHIH fopDI_EoAGfoEAG 1AG(foEAG8foEAGHHUdH+%( l He[A\A]A^A_] @ HuHH8( H8HcHPHH8H8L'XHDk LHH ) Hb 01,wA$| f. fopH@$foED$foED$ foED$0PH@HuDk LHH Hn 01vADŽ$| (H:Dk H s ADŽ$| Hn 01jv4y (* f. UHHdH%( HE1HEdH+%( uff. @ UHAWAVEAUATSH HH@HHdL,%( LmE HDž ƅ HDžX HDž8 HH*L`XVfrE o L ) o )o ) o )0HE1H@H l HxHp]Ht.foPoXHfoff HH@XHPHt1H^HP1LhHH (LIHH 17HxH HHxpVIHH 1 H0H LuIHH 1ҁHhH H 1fHDž )H8HX I HXHHH HtH8 tHx Y HHtH@HH+ HAHH H b HX ^ HXH HK HYHHH| HE a ƅ f D o L ) o )o( ) o8 )0VH9Y ff. H ƅb EHDžH aHrNHH1HHwE rDžt f(f= EcE1䈕[ @ t,DfEt fAt< fAHHDwD9 t<j tDfEtHxDž H Ht ;$ HE1HxX tHAE1H;A` fAGHAHx#FHHs L LX Hh DEt0D L:H5h HLk(HH fr(H l H E~ HH * HHHLhL)ueH t[E1Lu?f}u*HEHUH9HBHtLML9r LH9] IL;sLDLUHuL-=k L1H ) LH Au =oHAu 1LH ~ H L oHAXHAYH+HH HqAk JRu c DE1tBHM<k 18H@Ɖ-IH HY> LLHH>LHLH HHW1I}0HH %JtYf BfHHDdA +AxHPHL4H LH<HLD1LhHEILH) @ HLHEI9r HEI9 ILLIHuDdAfDA & sH=me +HCK<.>f D <HsHHc HH } HHHHLXPLaL8HH@PbPHRHP8H0 ' HHx9AHH LuH02f DdEHt-IHH HT^HIHEHf D H5R LY#HHH8k HH z H 0u1LkHEZHYH+E D LPbj HxDž H HHE1HxX f D Hwt Džt HEdH+%( T tHe[A\A]A^A_]LL5wDžtf HHUjHXHUH}ƅ H8HDž HSf HH=HE HDžH abƅVƅEQ H@*f f=& HL`pVL>1H4SHh HDžH 1Lmf. HLUHHA LHH- EШuHULpVRHH H5a H H H5` HHHt!HEHHt HTHH!H;U oEfofsffօH H1HmE1HXL HxI4$H8Q HID$H@H)IT$HACHDžH ƅbƅawH1H0HHHX H8.E1$HHl9+ H(tƅbƅa HDžH UHAWIAVIAUATISHH(B I dL,%( LmEň Ј f{( EtH H0jH tuE1ELHLL^AtnH DUt&A ELHLL.tADUDHUdH+%( u2H([A\A]A^A_] @ A$ u E1 ff. UHAWAVAUI1ATA SHhHxdL<%( L}MbH? HMtH#AHuHxADžuvH} tuE1ELe Jf D }u4Et.HuHEH9HGHtHxHUH}AՅ IL;usLDHHuAH{HEdH+%( HhD[A\A]A^A_]f D }u0Et*HuHEH9HGHtHxHUH}AՅu(IL;usLDHBHuAoAgAd f. U HATSHPdH%( HU1}H HH$Aăt,E1HzHEdH+%( uWHPD[A\]f D HX!t#HuHBHtf}>tA A E1V f D UHAWAVAUATSL$ H H $ L9uH fL H HXH H LLLdH%( HE1))о))fHnflH@L) fInflL)10 L1HXH\ L L 0 LLV H@L LH / L1HXH L / LL L HX1LG H AL_/LGH HHzLhH9t$HW(HPHLIE HW LhH9uHHHzHXI9t) D HWHPH@HHCHWHXL9uHEdH+%( HA D[A\A]A^A_] @ H@L HY L.HX 1HH_Y Hf.L11 ǃ 1Ҿ }zH(HH 5 H($HH HH0J?H(HHH L L@ 1H LL-H5 L LHGLL L1LHfX k-H5f L< HLL L5{l HA6~IIH HоL!HȾHH HH HHȾLHMt LRM9ICI!HLH| HtHtM f H(u L HX1Lj H LN,L6L!+ HH HT2HHtHtMt HuHHHxqADžWE1HHx H( DHPLh H(HHDL`{H L` LHI9IFHHh HLLH0J4#M9 I9 HȾH8 L8L)H`HL)H9ILC%H H0fInHPfInflL8J9HH @L)HHHHp H`HP(H LM9 I9 HH8 L8L)H`HL)H9HCI%H( H0fInHPfInflL8J9HH @L)HHHHp H`HP(H HLxH9h H8LMILZf D H0H`LhHPL)HPHHx HHHHp HP(H:HCHXH9ht\APHH#L9rL9sH8M8 H`I)HL9LB#HdHPLhaLf IL;x DHPLhH LHBMi H9 H HJHrH|1L9r I9 HJ HQH9uHHE1HN D Hr HyHVH9tHHz0 uLBLB Hff. f D HH0H3 HH+HQHPHP HBH9uD$H 1 Dt{p#1Ҿ sHxHHj D>HxHM H@LHDž fo0HDž H`fD1$fDž ) @ @ 8 HHff\OHx LUHxH HHxIAIDJH HHhH HHH9 HDP1LhL`IH(f. ADID$A~L$DnH ; HxLfHnID$HHDž flHHH(Hn ID$ L`H9uDPL`Hx YHxaH9h|XH LhH9u[ IE LhH9G I}0 uIu MEp HhIM$tHxTnpHH(1n vXHP HBH9LHI<0H1H9AI9AEt HqH9sHq HNH9u Hq HQ0HNH9ufHؾHlHH HDHȾRH9@4 4 A-HHMmtLH@1L H L#HX1H L H #1L1Ywh{H 11;w` AHHPkIHPIHH@RIHMtrHtmDHH@IHP3ty`HL HHcH9u+HLL?euAhL 4HHyHPLL `PhELHPDHL`h HxkpH(k L` xkpH|W U1HAWAVAUATSHH L-$l H?dH%( HE1Ee u 1Ҿ mH(HH H($g H02H< fo Ls H-XXXXXX D$LC IFDtpǃV 1Ҿ QmHxHH DV8HxH H@fo0HE $HE HE`HE E)E! @ @ 8 HuHMfUfEHHx HxHtyHCH fIn1HDž CH HAE HHHHxt /TI9~ Hx*ipoLH(i KHEdH+%( H [A\A]A^A_] @ 4 4 @ HsLCLዽ p\HxÅ\hpdH(ff. @ [h KAhpL$ @ UHHdH%( HE1HEdH+%( u H UHAWAVAUATSH( HH1dH%( HE1r 1Ҿ |jDžH HH H@H`/H L HLQ, LHE1HH H kHH LA 1L L4]HH(HH HHpHff. LLLLHh=IH< 4uL+H Hstapsdt I9L u< 8 H L( HHLH@H HHH LpHHPH HHHDžX HDž` HxHDž HDž q;HHI H@8HfHnHflAE8H9 H 1vRHH H@HH0 HPH1HH<H)HHH% HIEHc HHzHIE H3 HH1HHHHH)lHtGHH)H~7Pt/:t*Hx1IEHu Dž| f IE H H0fo IE01AE AEH HEHH+H HH E1HH E H'hHHt#HHtA} AE A+E$AE HH E1H ^E gHt6HHt*A} H AU( )AE( @ HHHFfHnHNfHnflAE8HO@HD 1HHk 01Kf DžLH bHEdH+%( H( [A\A]A^A_] @ HHIE FAE( Pf HH; uDžw D IU0HH)HIE0IE I+E(IE {Hk H Z HC 01JI}~DžLlI}cDžDžDžuDžDžf. UHAVAUATSHdH%( HEHHH9 IHXLrE1IHK@fHnH{AflHJHC8HH{HLIV8IF8HJL9uHEdH+%( uHD[A\A]A^] @ E1ff. UHHdH%( HEHH9t7HH1f HA8HHH9uHEdH+%( u ɉ D 1 ff. @ UHHdH%( HE1HEdH+%( u ɿ ef. f. fUHAWAVAUATSH H $ HhHxdL$%( LeIHt*HH<4 H5 Hu2] LH=O A LH d WAE L3 LE1DHLfIM M 1HLA Hf H1B 0iAŅ LHxD(HEdH+%( U HeD[A\A]A^A_]f D HLE1E1j DHL+AXZE/Hk Hٿ H 01NG @ Hk Hٿ HR 01)Ga @ LLLLGLH\MLE1AZf Hk IDH? 01Ff L) HLL11I^H&k Hٿ HU? A01`F6f D UHAWAVAUATSH H $ H8dL<%( L}I?La H5 ljIH; 1E1Lff. L L L`Ht{ L>Ht # M{ I$ LÃuHk Hֳ 101[Eff. ff. LHEdH+%( c H8 [A\A]A^A_]Ð z HHHtfHn11fl 2LH I$ ty%uAD$HHkI$ H ID$HHHÅ IGIOMgfHnfHnflA$L rfH LMk Gf. ID$HI$ HLEI$ f Ltff. UHAUATSH H $ HdH %( H]؉IL3M LHH# 1y%HUdH+%( uwH [A\A]] Hk DL H1< 01B1҄t Hk 8 t1L1/dy6F 닾 L1df. UHAWL=El AVAUATSH(D-l dH%( HE1HE HE Et2HEl HEdH+%( H(D[A\A]A^A_] 1H=o; DAƅxH5 IH6 LuLmL LL-0H =El =El = El tq=El tH=El t'= El uH5El H}:El f D H5Dl H}:Dl H5Dl H}:Dl H5Dl H}:Dl t D H5YDl H}:RDl K D I7H}d:&Dl "f Lrl aH}iDf UHAUAATASDH dL$%( LeAt;H=9 /CÅx;HEdH+%( ~ HĘ [A\A]]f D H=9 BÅyŃuAL H EtL H YG H k H 101? D AtzL%W9 L-^9 6u*u!Hj k H 101?2 S/MM1HH9 k H 01? @ tSHP Ak HI /ME1HH k H 01.?f L%`8 L-g8 2 D HP Au I UHAWAVAUATSH dH%( HE1H IH HH=7 AAAD6ADH=7 %AA;A1Dx&HUdH+%( HĘ [A\A]A^A_]Ðu D9 uuAK ufL%^7 L-e7 ku 25 -MM1HH k Hl 01=f @ Xf D AuL%7 L- 7 L@ߺ L|I4-L-% k M1HH 1Au c=D纀 LAI,Au M1HH 1/= L٫ H EtL H @D H k H 101<y L%b6 L- Hf k H߫ 101<? UHAVAUATSH H $ HdH%( HE1 11IH |WÅ H5* IH LF L L HHt3HHHÀ; u LLx9LtLEHEdH+%( uIH L[A\A]A^] HA k 12H*5 ;LLE1Hff. @ U HAWAVAUAATLSLH dH%( HE1H&H I11JI_IH3 E H{L=xPLH1 L@H LU L4 LLE1HEdH+%( H L[A\A]A^A_] D HLALA4AtExHs5HHtTH{L?<yvf D LLLA:4At EKH#5HHLO= D UHHdH%( HE1HEdH+%( u1 If UHAUATASH dH<%( H}HdBL-k Au H HHÿ 1H2 9H k 8 t3E1HHEdH+%( HĘ D[A\A]] @ HDHHB>HIHI9};HP 8AuAu 1AHHB2 1k8nHר 1AM8X# UHAWAVAUATSH(dH%( HE1H I IHEH HXAHtg L{: L_HtHpLuL{LLtHsLAătCE1H2HHuH}HEdH+%( uCH(D[A\A]A^A_]f D Hk H 10177AA UHAWAVAUATSH dL,%( LmLnM HB4L%k H@H8yf. H8: ?A4$H /HHR0 1 E16H4HH; L1IH IM1H/0 H߾ oAߺ H A4$H 0 1H16HEdH+%( HĨ D[A\A]A^A_] @ 39 HD8DEA4$1AHH/ 15E5f. E IM H Am5_ ;E1W6f D UHAUA1ATSHdH %( H]H1sHtHHHDIÅx LDL HEdH+%( uH[A\A]]ûf. UHAVAUATSHHk dH%( HEH Hc@9B HHIH<PHIHHtrH HXHtUE1E1 HIX/HHtI6H{LAa6yHEdH+%( u%HD[A\A]A^]E1AA @ UHAULoATSHdH %( H]H_L#HL9u X D IHSfHnflIT$L"H ! H{4H HLAI$LM9uHEdH+%( u H[A\A]]f D UHSHdH%( HE1Ht?H'";!HEdH+%( u7HH] D f HEdH+%( uH]f D UHAUATI SHdL,%( LmIH HH@LLfHnHflCqx-HxQHEdH+%( ubHH[A\A]] @ Hj 12H, 2H1f D Hj 12H+ 1ff. UHAWAVAUATIHSHdL,%( LmI HG I\$III9" A}D M} @HtLCt_ff. @ H L!t=HI9 MtIuH{ H9tHtHtuH{L9u LHEdH+%( HH[A\A]A^A_] IuHtH{ H9tHuAf HL9tHH{HtIu H9tHtltHL9u f D SkHL9u 1Yf 1Q @ UHAWAVAUATLgSH(dH %( H]H_L9 HIIAHE& Ht} u Lt0HL9tQH{ L9tHtEuLuH{L9uHEdH+%( u H(H[A\A]A^A_] 1G UHAWAVAUATSH(H}MdH%( HE1H IH HH gIHtEHH@fInflHBHI AE wI}>0I YL $HEIH fHn11fl I LmI " LI LmI I}L L}M0 AE1 H{ t7HA7IH5 I HAăj LAHXD9mHM E1HAHQLyfHnMH( fHnflAL8H>j 01-% H)j H' A01f-HEdH+%( H(D[A\A]A^A_]LmMt8I I}.I Lff. @ Hj H*' A01,sf Hqj H& 01,I HI.I *Lk f D H !j 1H 13g,3H& 1 R,H} ff. f UHAWAVAUATSH H HdH<%( H}HPfHnHfl)PEAŅ HPLpH9 L} MN1L*& L@ @ I IH Lb H HJ H` HH A~ EN IL1LHH5% A~ AV(Ht HH5% 1m I~H H<茸H(H| D<1E1H@EO LHLEfH(IcEl$H5 % H L<LVHt E9 HL1EH1 8 H@İHDžH IHz @ HpHG 1LHX! HH Hj L<HHH)HH LSHKH@?D<E9LLH(eH1HHI)2M H LH L(̾( IV8LrH9AH HEdH+%( [ H D[A\A]A^A_]ÐLL=5 H(LAHH LD1s;H(L AbHI$ .1I$ID$fInflHBHI$ A$ I|$Y)HxL蹽 @ HM1HH5}" ?HH%LL qHiH@]H(衸Hu0AI$ 4fIV0H MN HL -0 H`IH fHn11fl 6I$ H`H H t}H M1LH>! CL ML I>ELHC9H HC HBHJHZfHnfHnflHH`H`H H`4 @ L Hj Hv 101%ff. A Hj D H: 01%Hbj H L 01%LvHHjLL AUHj H L 01P%&f D U11HAWAVAUATSH dL%( LEI?L ADž L1A8ADž LMpIPI9 H0HMHff. @ A] HH L% A~ LDAHj 0Ez M L 1H4 E$I L L HDž H) LHH0 H HDž( *AQ9~xI LxMu D L IH IH LHH0 HHDž A9|EDH` T Hj H A01#HEdH+%( H D[A\A]A^A_] D DH 1Eǿ " D Hij 1ɿ H 01"M6HI9E1z D8Hj DH8 D01N"DEtE%f. Hj H A01 "ff. @ UHAWAVAULoATSH H8dH %( H]H_L;L9 I] HLK L@P L1L« ?H8XLZW u5IMM9 LIHCHuH H8" tHj H H 101!HCHfInflMHBHH H{L"H gH訶IM9hHEdH+%( uHe1[A\A]A^A_]w UHAWAVAUATSH dL4%( LuIL%j Hi HH1A4$? H mHi HXIH H@L0H8ff. @ H{1IH LhL;h H{9HK H5 IH1%L}M|$M9tZ IGH HMO H8P 1L v=H8XLZ5ulM?M9uLQHHH-L0L1HUdH+%( ugHe[A\A]A^A_]f D I LtI #M?M9-"A4$ H 1 q UHHdH%( HE1w t HUdH+%( u& D 1 @ HEdH+%( u1 ff. UHHdH%( HE1HEdH+%( u ɿ ;f D UHHdH%( HE1HEdH+%( u ɿ f D UHHdH%( HE1HEdH+%( u ɿ Ff D UHHdH%( HE1HEdH+%( u ɿ {f D UHHdH%( HE1HEdH+%( u ɿ ;f. f. f. U@ HAUATLeSH(dH %( H]HL* LkMtXLLLH HS H S { t H5 La L+MtKL) ~ H/ MlLHPHLE1LLH5 qu]H{ t61L蜷HL$HEdH+%( upH(H[A\A]] @ StH5 Ltf D 1 @ H5 L11f1 @ H5u L1 ff. fU1HAUE1ATSH dH%( HE1W< 1Ҿ lj4IHtsLmHLH LHPE1LH 6HHtc1t(HtWH8HtO} u H?LIT1蝷HEdH+%( u*HĘ L[A\A]] D LE1 1fff. @ UHAVAUATSHHHG L6dL$%( LeI H LIՃHHcu,C|. t,HUdH+%( uIH[A\A]A^] 1 @ S( K(9t BJvI\$ G UHAVAUIATL@SHLH dH<%( H}HiH11m:L, 1Ҿ A2IHtRLuHLHt{E1HPLLH a 4HtZH`H+hE1IE L}/ƵHEdH+%( u/HĠ D[A\A]A^] @ D0A A3 UHAWAVAUATISHH dL,%( LmAH] / H L0LL8H@7IHuAu2L+HEdH+%( HĨ L[A\A]A^A_]fL%Qj 11HH[ A4$H5j H A4$H؈ 11gA4$H 11E1Pi L@Iٹ L L@5Hl LH` JHH HX H f A4$H 11` H5al Lh M~ A @ HAj ALJ| HP0H 1LLD| I L0LL蓛H5IH]ASL%j H11H A4$fL8c LLyA| uUL@Ǻ L载HttEu#L%dj A4$HtFHH 11E1 L@ LL詶EuL%j A4$LH 11VH(unknownH@) fHjHj HH 01 / @ UHAUIATSHHl dL$%( LeIHh Ht8S( K(9t BJvL9#sSL9crMHHl Hl H9tfL;`rL;`rTH H9u1HUdH+%( uYH[A\A]]Hj 1LH[ 014H< D Hj LH 101ݹff. fUHAWAVAAUATISHH(MdH%( HEHgl Lh LxlLHt_L8LmMtSI7HxuDI} IGIWtEHDI$1HUdH+%( uhH([A\A]A^A_]f. Hl HUHH` Ht)HUH@z4 uHH+BEuH+B} tH+늸̸ff. UHAWAVIAUL-1 ATL%R SHH 4dH%( HE1H H LEHK HEE1H8f D L H H Hj H8MtPL1HL HHt HUdH+%( HĨ [A\A]A^A_] @ 4H8L1aLHLHqj H81G HJHuL89f LhoH@ 8hH 1HH j 01\1-ff. fUHAUATISHH?dH %( H]HH5N H( {D II<$tXsHCHV I}I<$YHH= 1Ҁ{D HEdH+%( ( H[A\A]]ÐH ^j u _ GHWtff. 1u0 v<_ BHuK 0H j 1u@_ubHP@t2ff. 1u0 v<_u0BHu1$ D HC I<$ HWH{NHXj I $1H 01aUHAWAVAUATISH(L7dL,%( LmIM0 M>ZM IZHtaH9ZHt LHMHM y HQP HH5P L1HA u A IW H5 L1E xcA~ IV HH5 L1H x-A|$ IT$tUHH5 L1H HHEdH+%( H([A\A]A^A_]fA|$ IT$uH5k L1f D @ H5J L1o[f. HH5 L1H EH5 L1/u D UHAWAVIAUIATSH(HLgdH%( HE1Hz H5 LÅ M~A?@3 M M<$MU IH H9HP LHMtHMx:y HQ H56 L1[ ff. HEdH+%( H([A\A]A^A_] @ LA荽LLHt f ) LÅuAsIVH HEdH+%( | H(LH5 1[A\A]A^A_] IFHM$$Ml @ L @ A|$ IT$tvHH5 L1H +M~A?@IFHHHLH5 1LA 1f H5 L1 D A IWt0HH5h L1HY 2>f D H5B L1gHH5% L1H J 膰f D UHSHH HXL`Lht#)p)M)U)])e)m)u)}dH%( H81HEIL H(H HH@Dž Dž$0 H09} H8dH+%( uH] 褯 @ UHAWAVIAUATIHSH(DEdH%( HE11>.HAH H5 HIfHtI9t H LLL H~ @ LD1ܮADžq LLH } uUHj LH{ 1A01L踞sf D LLH ) ALH L@ 1AADžyH+j DH 01kLCHEdH+%( H(D[A\A]A^A_]f D LA$H=j u_u=AD$IT$u BHt7u0 v<_tH}j LH{ 1A01R D HQj 1MDHy 01Li!H%j Hz 1A01eL=A( UHAWAVAUATSH H $ H8dH%( HE1蟢H HH 1H H薬Aą9 H5Ç HHH E1L-2 l D ( IH" H@INIVHH l L5 l H5 MM.IFL01 A H߾ H=* Ht0HxHH1HHH: u ÌIF IH Hj INAH MF 01H HWHH"HEdH+%( H8 D[A\A]A^A_]f. L=l AH l L9t HHCfHnH{ flHBHHI L9uj AA[تSD AF UHAUATSHL-pj dL$%( LeA1AE Å H=Bl uEt#1HEdH+%( H[A\A]]ÐIM0Ht Hj HH 01K&Hl HuL%j H" A4$ fL%j H 1A4$A4$H 11H贩 @ UHHdH<%( H}H=Xl KHHl HEdH+%( u;ff D UHAUATSH(dH %( H]HtsHIHHt8Lh Mt/LLLHD L ff. HEdH+%( H(H[A\A]] H]HE Ht'/ HZHt]HH HQl Hh HtS( K(9qBJv_ H l HUH56H` H]1 ff. UHAWAVAUATSH(H}dH %( H]HH{ @ H; 6 IHLAEIHO HsHUH蕓H HsHx- HEHMA LAE A*< MtfHj HKHu LE01RHuH}L蒳~ HC IF CAFCAF D ADžuf ALHEdH+%( uxH(D[A\A]A^A_]ÐA|$4 u M$M+D$M+D$J D A HQj HKHNt 1LE01 LE AyVf D UfHAWAVAUIATSH1HHX dL$%( LeA1) ))H LHIʅA Iw Ht1H DHHH DLD趌DAB E I] IU(IM HH螨AI9] tH߉GDDE K IMHj EMIU HH8DQ IE+MHn 1 諟DI} H5 DDHI{ A}A H fA f. H3H L H*HuLM] Hj H's 101\ALDDZDHEdH+%( HX D[A\A]A^A_] E9uFA IE0LxM IcDI;_s5 1A+uLAP`HI;_rAvDv A+uL ,LIHA AE=u;AFAE1f D1A+uL_A^AAEAA9~f D s H@ 8H; 1HHj 01AEAUfEAoM LLL)=HDEE1H))D))6DuSfoA}AEAE tDAELHHLLȁAHj H- 1D01DHEH* 1 DTDHIj H2p 101DCH$j Ho 101jA H 8H4IM H 1IHj 01$DA @ UHHdH%( HE1HEdH+%( u迠ff. @ UHAWAVIAUIATDSDH8dL<%( L}IIÅx1HMLHHMDLLH}G蒶HEdH+%( uH8[A\A]A^A_] ff. f UHAWAVAUAATISH EdH %( H]HA It$hI|$H1҉|AHXH ED|q IcLpH H)HIHP HpHE LpLH`H L=j H 1H LmA71HpHXLAx E L=j 1E1H`H D|I?yHc|IHHhDxff. fLeI?H[ 1 MIL$MD$)I|$I|$8HtkLoMx Dž| ff. I} ҶHHp&N LIHuI|$8|uI H= I@L9h0DxH}D|詍H`蝍HppHPHpD|H9Z D foEAfoEAFfoEAF A@A7 H`H=l 11HIH!AHXD|(D|D|ED|HEdH+%( U HĈ D[A\A]A^A_]f D IMI?H 1 fL|IH[I|$8A @ HpHXLeLLo@)EAoF)EAoF )Ef@AFAF L@hHHHDHEAHpHXLL牅|觾H}螾H}蕾D|ff D H 11D|H`蝋D|vAk聛 UHSHdH %( H]HHH H{ H{(HEdH+%( uH{0H]3 ff. UfHSHdH %( H]HHG0 GG 1EHC0Ht1HUdH+%( u H]ø詚f UHAWAVAUATSH(dL$%( LeIV{H HHS : HID$HH LpL}LuL1L IAD$Au ! HUI9 +uTLrLLuL1҈EYAD$AU A L;u }+AL$uDDED$ @ ED$L-\j H 1Au AD$A9D$= HM9 ` @ HHt^ Hx"zI$H I\$E1HEdH+%( t H(D[A\A]A^A_] HE f D / H蓱HtI $ . HsHuH5j u_uQCHSu-cff. ff. fBH;uȃ0 v<_tHj HHh 101\ f. Au Hg 11<AHf Au Hg 11 Hj H Hg 101Hj H Hf 101街AiAuff. UHAWAVAUATSHhHudH4%( HuHuAHEH M E L LeM A<$% H5U Lfu2: L襯Ht = L蓯H f. H5 LHHEDxDE HtK;@n LcL҈HEHa H L}H}IGHlIGHHU HuH}/Å HEH HHx1g 1HEH8 EL}AG@HH<H膸IGPIH HE@@ HE L=j @ H]A7 H' HHM,HxHELmLt1L= L&HEHt<L)LH/}IE HHE A7H 1YHELp@ LԭHEHt I9tHxH5 ~ : L衭HEHt: HEHxuHHEHHH A7H` 1H5V L迲H j HEA AĀ_ADe H L)LH.|LmHIEH@ A7HHߑ 1 IMff. f 誶IE IH HM<[' <. y> ELqAD$H5 LHEHH L)LH~{ID$HH A>[A7HB ED$HE1H} Mm JMe A7HFg 11mH}~HEdH+%( He؉[A\A]A^A_] HE@DA<$%5ILe( Hj Hb 101 D Ht ;= H5 L諵H H LH萵H D( LpA<$ HE HEE H@ LuA;tHL?H6 D Lx A:1 A% A+W 1HuLvHUHB0HE8 M6 MELuA;uLrHHEHH(H HEL=lj DH A7E HP0H H]C$Y LCHs E1E1LHEHE EuPHUHB80uKxxuE1HuH HUHB8HE8 t&Hٸj Hra 101 HUHBM? @ Lq1 D Lq1HuHML:HUID$Me AD$:] I9HM HBHEz HE ILLqID$HHQ A>[A7H ED$HE1WHEH8 f HEH j LpPHxIDu_uHEx$ H]HEHE9C@1 @ LpHHEHHH A7H 1qI pd HEH HEA7@ 1nKf A@ HEHx . LHUHBH* f EE1A:1HuLsHUB HE8 Hj HX_ 101cHqj AU H 1H` 018H5i L HE@$x @ HHH<D@ E/Hx( $Hx0 HH 1 RA7LHa 11 A7Hka 11A<$ XHE HEE= H@ HEHH(HHL=Rj DK AE$ LCHsM H& HS0HC$HA?QHP1 RHR` MH LHUHBHHmH]HHf HHH}H]ÅLeLeH5 L賯HL). LH臚HA ۅ[+ H@ H@ HS0HHX^ 11WfHj LHW\ 1014A7H]_ 1 Hj H] 101 Hj H\ 101pH~j LH\ 101HS0HuC$;f. HH^ 11H!j Hs 01_H] 11H A7H] 11+H\ 11H\ 11ff. UHAWAVAUATSHdH%( HEHcG@ LgPHL-{j IM4M<$AHAD _Љt#HEdH+%( u[H[A\A]A^A_] H5 LIt-H5 L6tI(M9u 1 @ ff. UHHdH%( HE1H t HEdH+%( u2ɸ G uH( uHEdH+%( u-舉 UHHC HAWAVIAUATSH HHL%j dH%( HE1A4$WHuHqH }I H8iHEHHz H]H5J Hz1HH5} IfHH5 1HEQHMMHH@@ H HHUE?kiH}IFHEZiIIH HMH A4$EϿ 1H7 cMeAr: AF@L٠IHt'HLL)oIF H 8/MgAFLHH5e Lx80 xxu 11H IF8A~L t#( LaHtHx11lIF0EAFHHcHHEIFPH AFH| E1 D Od= LLHt L`IFPK|HEHELHHgLHHEgHCH HMHs IE9~H1% IM A4$11H5[ H}vLrHEdH+%( X HH[A\A]A^A_]f D A4$HZ 11HE D x M}M H5D LEjIF8 L vIUH ff. IT HITHuHmID HfIFHt<1HH5< >Ht 1HjIF(IF( 뉻A4$ 1H| lBf U@ HAWAVAUATLeSH8H_dL,%( LmILf Mu IMMt!Ht LH5 L1舶 f D ILLLHL=+T L5 t(c { Hj LLIE14Hu=HthHK9[uHHM蓏HuLH褕Htff. f1LfHEdH+%( uKH8H[A\A]A^A_] D IUHt1H5 L覵x1LyH 1׃ U@ HAWAVLuAUATSH(dL,%( LmIL IM Ht+IUH H5 LHHD1 I}HHt}HuHLH臔xcHE1L=l !sAE@/ @ HL1L谴x,HIrE9e@~ZIUPKH<YHHuHr1LHEdH+%( u.H(H[A\A]A^A_] D 1 @ 1LvxH|ff. U HAVAULmATSH dH %( H]HL蜆 {@ Lp HK> 1H5* L轳 {L Lc M Ls8Mu!H{H H5 1LLLH5 ] H{0 CHE1~1LLHH{P AT$9SHI uӅxQ1LEwHDLCA80uvAxxuoHS LC8H H H5T L1Ʋt1L4HEdH+%( H H[A\A]A^]Ðr f D HS LK(H HtlH5 L1[f 1 @ s}HS01H5 L&1҅OTf. H H*H H?ff. @ UHAVAUATSHdL,%( LmI迢I}趢I}H譢I}褢I}蛢I}(蒢AE@~zE1I}PK HHsI}PHHcI}PHHSIEPH\Ht+ff. IHI|$'LhoHuIE9u@AE@ HEdH+%( uHI}P[A\A]A^]( UHAWAVAUATSH(H}H>dL,%( LmIHt_HH HEH8I}Ht_HH HEHxI}HHt_HH HMAEEHyHI}AEHt]_HH HEHxI}Ht;_HH HEHxI}(Ht_HHq H]AE C AE$H{(C$IE0HC0IcE@H<H葠HCPHH AE@HuE1F@ M}PKHIL4I?Ht^HH I>IHt s^HHt}I~IHt Y^HHtcMI~IMu=ff D IHt *^HHt4IGH{IHCAGM?CMt+ 譟IHHuH} f D IE9e@~ HEHPP1HUdH+%( uH([A\A]A^A_]|H]H{fH{]H{(Tff. UHAUATSHdL$%( LeI!I|$I|$ I|$I|$ AD$H~tE1f D I|$PLHHӞI|$PHHI|$PHH豞ID$PH\Htff. HHkHuIE9l$HI|$PrAD$H HEdH+%( u H[A\A]]{ UHAWAVAUIATSHHLc&HdL<%( L}AE H^j C<;P~]AIcHHBL4 HHXI9uLΝHEdH+%( HHD[A\A]A^A_]fIcH}HHUL4BKHuM$DJ HIHMJ<!HEqHUHIt\HuLH_HUK<&HE1_H}zjLMLEM1E8H H D>H 7IzAff. UHAWAVAUATSHHHHuHwhHHUdH%( HE1HE E :H1 LxL`IM9 HEHE M?M9 IHtIG HtHsHtHtIH3tHuL!Aƅ~HUH}HuAEtLvHEHcUH~)H HJL$ff. HHXL9uH}轛HUdH+%( uLHHD[A\A]A^A_] D LvDuE~H} tHE8/uCEHuE1xf D UHfHAWAVH}IHAU1ATISH8Hޡj dL,%( LmEI )EHUH\ 肿 HUL}1H5r LѩH}htbxHMEt5H L%HEdH+%( U H8[A\A]A^A_]ÐHj Hѱ 101 D I|$HEHH H辂HLHЈH}ug[MtLH5 L1Å8AD$@1) L蔟 D L}f D H5a LE1IÅt3f D H5' L1I胨H}fE9t$@tIT$PKH<#HEHHuv UA HAWAVAUATSHpHH H(@'dH%( HE1HH H8HD謻H L`IM6 HSl L0Hff. I|$H3AŅytL0H8IH1LiH=bSl \HHKSl =HEdH+%( Y H D[A\A]A^A_]f D L(HpLRuvL@LpHxHY LtxLLu:H8HnLfIHL0 f D H1j Hpf)PH`UHxHImUHMX HO L' HDž@ LHurM9 L5 j HH 1A6LLHDž@ LHHWH@HHR Lܐ HHt81H HH1 LHLLHLL5Vj LH, HH MA6LD1LH H= Ql MIEHHt HH@HM AcHSHHPl L1说HPl HH HL-] A61 HdG L' HDž@ LHfHH M H!Pl LH@LLHH` L@H A4 HHuII+OI)Hx-L RLHHtB f. 1HH uLHMIH@͕A6 HF 1HH RRHHH Ht3HcH<HœH HumL0AN H1H@軱L@LHDH苓H=Nl H E1E1E1HP H LAHLff. @ HHHH<H L )QMIH KA9HI(uLHE L8HA HHL LAdHLEf D L HLsAŅ' HHLH 1L LAUeH DMI$ J<> uuDf D L0HAH8F L5ɖj HC 1A6 LHDž@ LHTH~Ll E1H HL@H\S 1 L\nAŅLYO1HL0H<ALuL0H=Kl HU1HKl en D UHATSHdL$%( LeI Hj x uw1訙ÅxLHuH}1Åx7}yv}x$L1%Ë}~d}~dփHEdH+%( uTH[A\] @ HEdH+%( u6HL[A\]陛f L }É xt mff. UHHdH%( HE1HEdH+%( ulff. @ UHAWI1AVAUATSHcHxdH4%( Hu1HpHc ; L4 HEI)HxIML` AG`E1E1 ff. MwXMI~ ^ I?I_H AD H" HAN@HpA HxI HxLHIHhLHhIFHy Hp A LHH) HHu[AG`AIXD9 H`IpI91f. HpxxHUdH+%( Hx[A\A]A^A_]f D I>Ht8Ht AD I^HW HHDAE OIHt ?0u2xu,I~f D HxHpP H5 Hh荈HhHudH j H4 01` jff. f UHAWAVI1AUATSH <dH4%( Hu1G~HPH Dž@ E1MI_HtH5 H觭$ AE @ AG`1E1ۺ E1) DDLHXLXMoXI} I?MwH| AD q M LeAM@HPHA L_ LILIE HHIHHIEH H Z Me H0 HtLH觬o H5 LH5= 1rI] L` Ll2 MEA804 Axx) IU ME8H HY H5N L1) LA+ HP襚HEdH+%( HĨ D[A\A]A^A_] D I} H Mt AD {MuH MLDd @ AE 1A 1ɃDDHXX9} EDIA@Ip@9<~rE f IU MM(H Y HH H5/ L1藘AEHE1V ff. LLHI}P=AVA9UHI uӉA1L牍He\LIM틍Ht$LH55 1ILAVHAG`fA- H5 1 IHt ?0uRxuLI}8 HPLL @ H J Hf H 2 HH5! HH譃HHHu @ A 1H,j 1HH: 01oAE Hj H: 1A01E%AE1e A D UHAWAVAUATSH dH%( HE1 HcIH H)HHHHff. @ Hj A^EfEn`)pD`IFX{D,H H4_ HhADž- wHpH[ DhE Hc,H E1HIHPHH8 HpM>EMfH@M A~D M HEAM@H@LHHHADž HHPDLIE IADIEMH H? I~hLPLBhL LAE A H8IXI9 A]LL0hH I} A~E f M} M Mt A~D MeH MLD @ AuA~E AHphxYHxlx{YExHIpI9fHEdH+%( b H D[A\A]A^A_] hxtljHtHHHp h @ M~Mt A?0uAAxu:M}HHH@G* h @ H5~ LDHZDHHuAEHj x u E1IvhI~HCHHt ,H LHSL Hj H7 101ҺH] H0HH{0 I L0AL AGH M LH1L- L@$ LL赳 HA9_H IGPIܾ@ INt LxHtHj MH 6 1LL@01LHLO\H{`HH肱LHH0HMj 1HJ01LHA5 茹LHLHL@H0H5 1L@H@PJL Hj 01@LHDE1AHj H4 01H*VDŽhiHj Hd4 01θDAU^f D UHAUATSHdH%( HE1 HcIL, I)IIAD$`~(1 D HHCID$XHH<覲A9\$`I|$X̀I|$hAD$` ILIpID$ }M9uHEdH+%( u H[A\A]]]f UHAUATSHdL,%( LmIEE aH HuH}Ժ IÅx.}L-ÅyGtB}ԅxT}ЅxTL2MHEdH+%( u4H[A\A]]f D }LՋÅyu1뤻\f. UHAWIAVAUATISىH(dL4%( LuI{AŅxjLL觢HEH HrAŅtk MH H LDH j 10L1hH}orHEdH+%( H(D[A\A]A^A_] D HELx LCIH tE1IG@LJ H-HuIM;gHr~f D HIԺM;gHraf L_1H2 HHMj Hً01虵HqK$MH HŴ ALDHj 10L1\2[f UHATISHH~dH %( H]H;ID$HtUH{Ht;ID$Ht=H;Ht+;I$Ht'1HUdH+%( u H[A\] I$ ٸZf. UHAWAVAUATSH dH%( HE1J HcIH H)HHHHff. @ A{E - ICXI{ H ICH 80 xx~ LL8L8` X [|L8HICXH? IK8H{ H]> HH8AC$C@ACECL1L8 {L u#Hs8H{L8xL8 HK81H{ H L8gL8 I{HHt L89L8HHC _ H{ t$I{L89L8HHC4 I;Ht L89L8HH Ic{@L8{HH{L8HHCP SH~7E1HMH{PIEPKH4LIHHʹD9cHM HAK`IpI9H k L%k L9t8 @ HHCfHnH{ flHBHzHGI $L9uE1f HEdH+%( H D[A\A]A^A_] I{XL8 L8ICX A{D ISHH_ H LL8L8A{D Aʅ\AQA{D e A{E j H=mt L87L8ICH ICHf D IshI{HL8L8HI+ LHL8L8HH H Hnj Hc@;BQ IKHH H- L8HHDH}j 01DL\SL8A{D A? Hk H9 L8輨L8H}j H, 01ѯL8 D ICH(f D A{D LRL8A{D G LL81L8A{$ IshI{HL8HIZ H|j H, L801H H8LܬL8; 0 H|j H L0801輮L08A{E McHI[Xk M 11L牍(L8HDžH _L8(HH0 HH L(L8AWL8( LL8L HHLE1HHLAL]HCH4HCH2 M+gL)k(LcHc4HCH (AHXA9 LHLc(H0M)L2pIH HsHx-HH8+H8qH; FH3F L8HDžP DžH 4L8H HXHw LHH0LPML8f D HHHp H{LLHI2Aƅ~H8H LAL8BEtL(L0D8LքHcHL(8McX~1HMAHPI LIXTI9uMDH 0L8gtL80A{D 8AI{HL8`2HHC HlhIH L8t0H=3|j H u _ QHuLe1H n @ H LL8P L1L8ICH HL8@L8< Htxj H ( 01跪L8ASEIshL0I{H臖HHH L5e~j Ic~HH8H L0HHDžP Mk}L0 @ LL0hHL0HQ Lb8M E1HPH L(H0ff. @ I|$-vHHtt@ HAhHt!H)HHN7HPHH LHt AE;~}H8IcLd HP t H0qL袤IHfL(E E9~1 A{E u I{H Y HDž McL(KL0I<AHQqL(ICXH L01Dž E1DL(L0'ff. ff. IL9( H8N<AG*<uEMtPMGH81 HD9t4HL;BuHuj IO- H4) 01 A9uf D HcHHHPH0H@XLЋ9l H0IO HP0IGH)H9 H~4 uHH+FH4H0Ip8xE u HxH v HH H8Ht L .L HHH HI@8IxH+AIO-I@(HL -H H0L I@A$HyHA@@YEHt!< -H L I@ H0AXL@@A@Hm HH0LLI|L9(DL09 H(L0VpH8<L0(HL8H<PHnL8IICXH H LhM LL81E1M&AFELHXAGLIH IVXL<I}ALקyL8ML0L8H0L8H߉82;D8Hrj HǤ 1D801+D8?Hff. I|$-趯HHt@LVt"AE9~~H8IcLdf HP tHUmLIHuL0sL fL HH HL 4+L HII@ >:M] H0L XEyHcL HlL HI@PH Ic@H]H0L HIH LaPff. I<$Ht*H IE I|$Htv*HH I}I|$HtW*H IEI I(I9uL IO-LHH *HV LH I@H0H@0ML0L8L{HL8IO-L HHL aHI@ sLL80/L80H4pj H5! L0801j8L0x Hoj H) L801)L8mLL8.EL8tLEL8A{D hAH7AL8MD1HYtj x H HLD(H8D(M7H0qk(DHnj ѿ 1H D001-MfXD0LIXsD9|H MniH8-L*H 1HHnj Hً01ˠH6A AoCMkL0)PAoEHX)`AoE H8)pfACAEAE E{EIshI{HH HP | A IHg H8HHH1L0H H8Hx- L(H0eH0L( LAEu A|$4 u M$M+D$M+D$M H:mj H8H L(01L0hH0LLQL( HpIC0L狅`AC dL8AC$(iH H8LL0gL8I{{gL8I{(kgfoP0L8AE fo`AEfopAE L0L8+0L8wf EMAMfX1Eff. LIX葘D9|H D0fH hH83D0L0IH4 H|kj 018Ý8L0WA{$ tL0~L0H0!l L0Lh LBpL0x.LL0蘝HtH L0HH:Hjj H 101 H$gH82A D DL0ALL8ffoPH8AE fo`AEfopAE )H9jj HMG-1H DL001j AHjj 1H (01CL0(HDžH IShM& HHL牍0L8蝂L80 (H E1LHL0L8IމM)~Ls"IH? AAF,IXA9|(L8L0B L8AM HL8sL81A*< Hhj H8H 1L(01L0L0L(QL߉0L8+L80L0L8'L80YHImj x H8 l 0L8Lh LDmL80h L0L8芚L80H= L M1 HE11L80EI݉L(CH/HI It$IEIDt$IE(H)IEAIXA9s Iu(HtA}0 t 艧tIu(L9"I}H荄t!01I} I}pI} zI<$ HuL(A MIFHLǶ Hfj INH2H LE11HcH8.LL8 <L81H}fj H 10L801趘0L8PLHL L8c.H0b(H8Ή0m)L80|L80L(L߉(0L8()0(L89.L8AMIKHHm H HHDHsej 101HaH8-y1aAL`0(L8HDžH LWL8(HH0 1HHL牍(L8}L8({ L(HALHDž8 LKH,H HCH LI+D$L)k(HC88HXD9 Ls(H0M)L_YIHt;HKHx-HHH YH tH; dH dHhj x uH(LEH8H0D(`(DHcj H 1L80Mދ01ΕD0iL8LL8_H>cj 01LH< L8Mދ01qD0L0AH1+A!;IKHH bj MH? Hd Hɋ3HD11IH 3Hd t711H^H8*H^HT H^H8*H0HxHL(DH HLD(H8Haj 01LH L8Mދ010D0]H(LEH8fLL(D(L8\ff. @ UHAUATISHEdL,%( LmASeÅx!DLeÅt,DLYOHEdH+%( u H[A\A]]DLX,9f. fUHAWIHAVAAUIATSHHHLEdL$%( LeMh HuL:tLHU1H8HHEHEH LmHI\$(L)ID$qID$H Eu>1HUdH+%( HH[A\A]A^A_]f. L(+H I9u6AD$0 L+H 1HH_j 01,H_j HMH 10I1H_j HH 01C97UHAWE1AVLuAUI? ATISHxHxLHMDEdH %( H]LHE #H HtwL(*HpBDhMcLYHCH L)H{ LILL( 1H8 YH= H@ HCHEdH+%( HxD[A\A]A^A_] @ L L`"Ht , L L>"HL HEHMLLA HE1HhHpY H} HU<E1E1< H DpLbA H uDvHH HCHt0E QXHtL`HC HC A D Ht+HuLHM1H{H |xE1 HDp B< << Dr) HEH}HH`6ADžusHcj x L9mu\LuOH`H}Ht19 HhHpLLA QXYIL9msA @ HxHtpHELbA H C L`4VA^DrLbA +AEH[j DHm 01$A 3H[j H 01 UHAVAUATISHL.dH %( H]H貞tS4tHHLA Hp CcAHEdH+%( HD[A\A]A^]f { tHE E1LIMPH Hp vAŅuHcCLHHCL4%HSIFHcCHHHHHt*HZj H"d 01C- D C 82ff. @ UIHAWAVMMAUATLeSHHxH}L) HhL=-Zj HpHJH DMA7dH%( HE1LmTH}LZH LGLHx$A7 LxHHH 1LHKA9[ { M HsLLDMDMH+ A HE 1IEELAE@$Hg HE1HtHsDMHMMLAHEdH+%( 5 HxD[A\A]A^A_] @ { LLYH LA DMYSHEIH HpDMH H L(f D HuLdCAHEE HKA7H> 11}' AAy A7Hh11HC 6f D A D H}Dx"DxH/HKA7H* 11 Hp @ foELLDMAfoEAF^XDMHU LDx袟LHEF"A7LEHɉ H 1iDxAu, QHEIH HpH HtSL(LeHHCIEEAEDMHMMHHhL2Af. HpA7Hh11H 轈A7HhH/ 1蠈ADA7H3 11肈MH[L1!A7Hh1IIH 1Q HhA7H 14AA7H 11A- @ UHHodH%( HEHF oG@F HEdH+%( uɸ - @ UHAWAVAUATSHh HdL<%( L}IHc ~FHcI IW H<H yH f. HXH9tH;P8uDž fA9 FM IA HIW HFLAI IIIGPHHA$MNHDž tGLA H HEdH+%( He[A\A]A^A_] H, H$ IFH INMF( 1L-Sj H Au 1 NHHG IfE1L) DA@HDž$ E L1IL f ƅ Au HH- 1 蛅HHHH5D(3Au 1(H D)S, HD(HL0A9^@ IVPHH5à L<IGHHn8HH5 n$IcHAHAoHH AoG@IW HP A9^@yff. @ LLE IcHEfHLIFPH A~H HLLMHI01IH; _t\LLxf HHI(9XH9LxPHIL$M HH=Tj IM tI<$HH ^ HHI Au H 1tI IV HHHp貒H LLAu H H1 I Iv LM E H( F I HPHW LI HpDH MHOH LI x LxI @HMt_H5,L L@ltLH5ނ L-lt9AxuA t)suA t u A f H4 LLWL^ s DPL0L7 1RL 覟Y^U H@ MLK)Au H 1H1D HHHHOH HHHxAu LxHH 1ԀM H5J Lj] H5F LjF Au A ~ Džu H/]g@ H DL0PL L 1HXZLHHGH ML A MAu Hb I 1LHH1ILgIH : H >Ht _I L8I HH D I H1HHp討HA 1MAu HS 1I LHH1Dž:f MLÉf DžHDž f D LLAu H 11MLy~DžHHH;t ] HxHLxH u\HH@H ff. HH Hu HxHFHxHH @xHH5~ uHH5]~ ȞZHML*Au H_ 1H1S}ef Džr1H> Džs suA txuA uſ 8tDžx WDžMLHmAu A@ 1HH 1|@ + |8HJj HB 1 1U|DžMLNHHP=Au H| 1ML|Au H 1ML{HMLHHyAu I1HH> 1{GMLEDQ!HMLAu H 1H1D{ff. @ UHAUIATISHHvdH %( H]HHR \HtH{ދ.t!1HUdH+%( uhH[A\A]] D H3H{,atHSIu L[HtH{ t H{{HHtH{EuC K ff. UHATISHH~ dH %( H]Ht"{HHt!H{duH3HtL}`uI1f D HuL;CU9~)9C~ډCHCAo$ AoD$@1C !Ao$HC AoD$@ C HUdH+%( u H[A\]b fUHAWAVAUATSH8dH%( HE1HE H HI[LkP Ao$CPAoD$C`LuLL}@ LL Hs LLA L|B HEH H ff. fLHSH}AHǃ HEdH+%( o H8D[A\A]A^A_] Ls0Hs LLpH9Hs LL H LE1Hy 1HHEj 01 xx Hǃ @H 80H{xHtwLuHs LWtHs H LWuH}LL=HFEj HK 1H 01wH}_ A @ H {HDj H 1A01>wHDj H 101 w f UHAWAVAUATSHHL6dL$%( LeIM.I} twHHt I} AuIuH%]u)1HUdH+%( H[A\A]A^A_] D H@XtHdwIuHIF7INEE1L=Cj HKw A7?vEEA7 H<w DAMHANEEDH1EFvIFHIEu"LH5 HEAD$ "IFHLHDH5K H裋Ix!H@01ۋ@t AFX A\$Hx >Yf UHAVIAUIATASH HqdH %( H]H[@ugD9caD9c|[HMHULH{~D9eu=HuL^u-HH{ tCH{0D7yuff. 1HUdH+%( u'H [A\A]A^]fLhHC Hus UHAWAVAUATSHH8Lc dL$%( LeIE~TI$ IcIL$ HH H@H9t/H;H(u1HUdH+%( Q H8[A\A]A^A_] D E9$ AUI$II$ A$ IT$ I|$PM$ H$L@M|uHYAj IMHt ME01s11-IE8H AƄ$ L}LHL5 LLH:Gj 8 u%I}8G KIE8 @ I|$0LLLAƄ$ ̅I}8GH@j DH 101rf D UfHAWAVAUATSHH8HAj L dL<%( L}ILc )EHEbt]4tXA t>Iw HG¸ t'HUdH+%( H8[A\A]A^A_] D f Iw MwPE1HI E L t uA @ UEHEHHEx@HEj Ux tf} H5r Hr H}HE (t6H}}zH?j Hr 01Qq1f. HuHDuhHEj x t } H>j HM HFr 01pH}1I K|%HH}yg Hi>j HM Hq 01pf D H} H5q ' H} >HULHQHM Hq AH=j 01>pEX7 ff. UHFHHSH(HdH %( H]HHDH5~مH;x2HG0@u1HUdH+%( u'H]CX H E;8Ezf. UHcHAWAVIAUIATISHXHypdH %( H]HHtHs(Le:t)1HUdH+%( HX[A\A]A^A_] D D L}MH<j H Lu01nHDcLLk HyL~@DeLc0LEC(LuE )Epu } u Hs LHLp} t HL1҅O. D H <j H 101On UHAWAVAUATSHxdH%( HE19qt'1HUdH+%( Hx[A\A]A^A_] AHq(IIH8uDpLc0HtLHxLxPL=P;j Dt 1HxHn A7mHxLeWut9p HLk L}LuLHLL~@CLuEC(EE )Eou;} t HL1҅O Hs LHLn} uHu:j H 101lA7H 11lHH@HtkLk fHnCLuC(HMLLH EELuE Hh)EKnuY} Hht9HLHpRuFDtHxA7H 11lFHs HLm} uHpL,uLDtD+pDtHHu UHAWAVLPAUIATSHLH dL$%( LeI1HDžH HDžP HDžX Dž@ DžD <uHPL`I} HL[H HXHLHDLmLHL7cH LFgIH LL_rt{DžD HPH)I\$ LJID$H_ HXHt+I$H7 HUdH+%( Hĸ [A\A]A^A_] @ H@LHH07+dLLujL HXHHH(H9Puu f H(LqqLu H9H- hHH8tFH0L*u3foEH8)EfoEH )ELHL+HuL>jHHXHtH!S~DuHPy Dt +@AD$HX1Hy @ LIHDžD ŋ@DuPH +@L AD$f `LD HX AD$ H5j HH 1016hI|$0 U HAWAVAUIHhATISH dH%( HE1H`HHFH HxfHnI} H`HHH])0fHnfHn1flH0H5CDžP H Dž( )@:DPEL DEEe H HHE1E1H H`HxH HcI<$ Hht HI I|$ H1HH0H5Dž8 H0ND8MD !L^ HI} LE1j HE1H Gi^_ H I} HHL@GHt{I4$H I|$ HDžh 2ID$HHH5qHp{H`Aƅ HG0Hu@ME1, ML @ M E A HiHtHID$(H H2j IL$ Hٌ 01#eExDuHEdH+%( HeD[A\A]A^A_] D H HHHDMEE1WfH N-UAHM2j IL$ HA 01dlf D EuWH2j IL$ H 01Xd5IL$ H1j H A01,d HxHf UHAWAVAUATSHH(L56j dL$%( LeIMn@M LHII|GWI$HH% I@ @ F I~@ f$ I H{/ !HH I<$ 1IMH HUI<$ u1HUdH+%( H([A\A]A^A_] ?/t IH Hjt?!f LG+ f D LHE++HE vH?I$H_W L*=)f UfHAWAVAUATSH8 HHFpdL,%( LmI) ))@j I}0L-fHIEHp Ht L LLLkI}(HHL ÅN IE HH5k HDž H@(HHIEpHjIHY HA 1HL @ IHL LEOH~@HHD8 u HHI0tHL롐L?t dHLtsHg~HLH5]vHEdH+%( umH8 [A\A]A^A_] H-j H 101'` D H-j H H 01_HEcH@ 8HHH-] 1IH]-j 01_ UHAWAVAUATSHH(L.dL$%( LeIMu ,Au(1HUdH+%( 3 H([A\A]A^A_] @ IvHEtH`IHL I~Ht H+*uHuHHELE H_` HH,j 01^AV M}(tTIuH AF AELI}0H5btAD$I~H5! "Ht AD$y] Hu\HE2j x uLH5 HE.AD$uAD$ I~H5! ""HtAD$ IE HHHEeIM Ht:I~( t_LHAD$8Hq+j H 101]JHjH;_ HH<+j 01]KIU zE HUt;M}0L1IM u'Ht"HUHz tH H#B uHz( t"IN0LHIM AD$Hz0 uHz8 uI} LIM tH*j HV 101\HULHdIM ff. UHAWAVI1AUATSHxL.dH %( H]H0HCpHB M}M H5 Li HMHpH HEE1Dž| Hha LPXI} HC(tHtBI} HU1H5hLH]E CE|| L}HI>E1E1j HpLHh^ZYuoHuLc0I>LL<HtIuHOI} HC( _I}( tmHL"||pff. H{p'IHCp HEdH+%( |He[A\A]A^A_] AE HH5LCp| @ HEHps fInHC0LcPI>AEfInHU1)EfHnH5`flE HE H])E-}HpL|Dž| ff. @ UHAVIAUATSH H?dL,%( LmI:H LeHHL8H EE1LHHPH i[ A uHt Tt:I>B>LLI HUdH+%( u(HĐ [A\A]A^]ÐH1IExf$ @ U HAWAVIAUIATSHHH L%,j dH%( HE1H HHH5HHCHEIcD$H H<PHE+!IH AM@HEE Hx H Hu H} % AExH} Hxr]tcHEdH+%( H [A\A]A^A_] @ Hx4E~%E11 H}LIXMR9]LDt 37E.fMH} EE@E Hc1HHPL<Dž HGPHLLHHHIH1I ff. f D HX91 H:LH tH_9 LHLMI&ff. ff. IXM9 I~PLH uIL$H1 HmX Cx5HtIVPHLHJHHBHuf. HxLAw >f+A HHH9H@LHxE1) @ LH1LIUPHHe HHHz#j 0I1UHxAHA9눻KHxc U HATISH(HH dH%( HE1HLHHH ID$HEH)j Hcx}H HH H} HELHE uH} twAċUExKHEdH+%( uiH [A\]fHcHH}H3 HcEHHEHx8'-UЍBEЅuH D D CA뇺2f UHAUIATSHL&dH %( H]HI|$( t)HEdH+%( HH[A\A]] @ Hu[ HMHtJH!j IL$0 HU HK 01SHL.HUdH+%( u_H[A\A]]LLH HH !j 01mSL HG 1HH j 01BSf. UHATSHHdL$%( LeIc t$ HUdH+%( u&H[A\] I4$Ht(1t D UHATSHHdL$%( LeIc.t$ HUdH+%( u4H[A\] H(HHtLH<' UHATSHHdL$%( LeI c.t$1HUdH+%( u?H[A\]f. I4$H'tID$o oC@ ff. @ UHATSHHdL$%( LeIHE qb.t 1HUdH+%( uAH[A\]fHuH4 uHEI9$uID$o oC@ D UHATISHdH %( H]HH6&¸ uHUdH+%( uUH[A\] CH{pHcHHt3HcSAo$HHAoD$BHC Cb1ff. UHAUATSH(dH%( HE1Ht{IHUHuLugH} t`E1 II9s(H}11L/8LHH!HEЅuL9t"HEdH+%( uH(H[A\A]] D 1 U HSH(dH %( H]H]H5HtH+HUdH+%( uH]Nff. Un HSH(dH %( H]H]H[HtH+HUdH+%( uH]ff. UHSHdH %( H]HH1Ht H8HUdH+%( uH]ff. f UHAUATSHH(dL$%( LeIg_t:4t5It$H $ HUdH+%( upH([A\A]] I4$HlotLm? HLHt1 L HHuL HHm1 UHATSHHdL$%( LeIiHtHLFu5H JH1Ht#HEdH+%( u,HL[A\]F @ HUdH+%( u H[A\]# UY HSH8dH %( H]H]HHt$HuH4`EHUdH+%( u H]ø UHATSLeLH dH %( H]HI XHt+HL HtHEdH+%( uH H[A\]1W UHAUAATSHHdL$%( LeI @ H(]&w@Is:HL HHuHEdH+%( u'HH[A\A]]f. H\tff. UHAUATSHH dL$%( LeI\4t/t* HUdH+%( c He[A\A]] Lm HLHtHHELM1PHpLHhLxZYH~HEHMHP Hu/<w<jH Ht<v<QH HuLmHLH/ _>HH L`HUfHnpC<tlw&<ov:pCBC I$I $Hf D <t4<u!HBCB @ ЃP<OvS1C밐C B룋R1~ UHAUATSHH dL$%( LeIZ4t' HUdH+%( He[A\A]] @ Lm HLDHtHHELM1PHpLHhLxZYH~HE8uHMH Hu} D LmHLHY <HHteL._HUfHnH BHCI$CHI $fw H Htvt1f. UHAWAVAUATSH H8H@dH%( HE1fY4t1 HUdH+%( He[A\A]A^A_]f. H]H8 HHtHPE1LhHHL`LXLpf D HLMMATHHLH?IXZMPHh>uHpHV Hu)f<w<uH Ht<v<uH HuH@HNHPH9 H9H(H0ZLEH8L LLL H)HHxf L H(HxH0HH9)H@P1W1f. UHAWAVAUATSH H8dL4%( LuIlW4t/t* HUdH+%( He[A\A]A^A_] H]H8 HHtHhE1LXH@H`LPHHLp HLLLAWL@HLH;IXZMKIH;`sH;X2HhA~ t AN qP9 p9wHpHH Hu 7 @ w RH Htv7H HuIcNHPIH9( H9D H(H0LMH8LLLzLHHHx LH(HxH0HH9D A)EF1f ^AVH;PPHpHH Hu 8 D w *H HtvH HuIcNHPIH9AF 1efH9HHpH Hu 6 w H HtvH HuIcFL(H HHEH8HH0L(Ht\H0L(TL(y H0HxL(YL(xH H;x Hht HpH Hu 8 D w H HtvH HuIcFL(H HHEH8HH0L(H H0L(SL(C H0HxL(UL(9 H H;x% AF1THpHH Hu 8 D w H HtvH HuHPIcNH9H9щ H(H0WLMH8LLLLHt?HHxgLx!H(HxH0HH9dHhBH0HmL(HHhAN(H0H;L(HhQ U> HSH8dH %( H]H]H%LHt@HuHdSu0HUHBHH HUdH+%( u H] 1 UHATSH0dH%( HE1HtdIHbu 1HUdH+%( uKH0[A\] @ HUоU L/Ht1HULEHL,Hy뭸=ff. f UHATSH0dH %( H]HHE P.t 1HUdH+%( uWH0[A\] D Leо< HLHuL HwH¸ HuHuHnF f UHSH8dH %( H]H~O.t!1҃ tHEdH+%( u9H] HuH tHUоU HH D UHAVAUATSHHĀdL$%( LeIt7HHp1 HHtHu\IHt I$I9E t* HUdH+%( H[A\A]A^] D HN t#It$HAT$AD$1u LHdH5;duLu: LL IHtjHhLYPuWhLX H߉dHHt/HhL%Pu h9dL UHATSLeLH0dH %( H]H8 0HtkHLOu 1HUdH+%( u{H0[A\]fHUHuLx,LEMt#HEIu #uH@H H j ʿ HK 01;vff. UHAVAUATSHH@dL$%( LeIL t( HUdH+%( H@[A\A]A^] LmHL9xeHU1I9tLmHL HtHuLx HEL9sHEI9 @ HEHE L9rbfLuk HLFHtLL Nt1HUl D HUHf UX HAVAUATLeSLH`dH %( H]HlFHtwLuLLMudLmEx[L: H;FHtFj H}11j E1E1L<ZYHt%1HuL6uH}Ic113"1HUdH+%( u He[A\A]A^]ff. f U: HAVAUATLeSLH`dH %( H]HEHtwLuLLLudLmEx[L: H[EHtFj H}11j E1E1L\ZYHt%1HuL'5uH}Ic11S!1HUdH+%( u He[A\A]A^]ff. f UHAUATSHH(dL,%( LmIHE I tjH} u# HUdH+%( H([A\A]]H9IHtHuHuIMHULuAUAEt1fHQHI0EMt5~1HuH?u!IMHULuAUAEu A} 6=f D UHAWAVIAUIHATSH8dL$%( LeIuiL} t[LLPuLLLAՉÅt/tLLLLHtfoEA$foEAD$L f 1HUdH+%( uH8[A\A]A^A_] ff. UHAWAVAUATISHhL~LvdH %( H]HELuL}E 7HtHtLItMHMHULH5fIECHUdH+%( uKHh[A\A]A^A_]f. HxL>uHxtLLA։Etf U1HATSHH dL$%( LeE1HuH5QHUHU HIDHEdH+%( u H H[A\]ff. f U1HATSHH dL$%( LeE1HuH5QHUHUt HIDHEdH+%( u H H[A\]=ff. f UHAWAVAUIATSHHxH`HhdL$%( LeLeLn-HtHuL<5 HUHuH LeM I E1L}ff. @ LLH}L)HH)HHHtmL%BuaL;m LcM9rLLu D LAu4L;m H}IH[HwHHuff. @ Hh 2 H`H9 ! HUdH+%( ' Hx[A\A]A^A_] @ L9dI L9mL4H`HhLHpL@ LHAMLH2::L;m0 u'H}LIwHHu f. HhHQ-11H>H`HHHht 1Yff. @ UHAWAVLuAUATILSHHHudL,%( LmI*HtZH$f D HHULH5'EHHtLHAADžtHEdH+%( uHHD[A\A]A^A_]Aff. UHH HuH5dH %( HMHHUDHUdH+%( uf. UHAVAULuLmATL%cLSH@HuLdH %( H]HL,DHtLH @ oLLLoGCDHHuHEdH+%( uH@H[A\A]A^]1f UHATSLeLH0dH %( H]HHH5 CHt.HL{Ht HEdH+%( uH0H[A\] 1ff. @ U1HSH]HxdH%( HEHHuHHU1EHEHt/HMHUHH5 BEHUdH+%( u H]ø UHAWIAVAUATSH HH dH%( HE1Dž4 @P 11H`L H4LHL0HH H HH@HPWL-i Au HP1 E1H 1 L5 /HP b fH@LAHH H0H&) HHHo< H/HHG / HH]5 / HI9 HHL H`HHLHH Hh HGHHtH6 HH8 498 ff. IL;Pff. @ HI9P HLE E HEH HEg.HHtH<LG HMHULH5F@EHUdH+%( H [A\A]A^A_]f Au L 1I,L;P7H-H9ff. 11HD8H HHHNj0HЅNIL;Pkf D LHDž f Hf1L)EHUH5HEH )EHE EHXL3H <HHXHЉEwH#;0Hv 1+RH1i H* 01t+,L"HӴ HHi 01C+ ff. UHH dH%( HE1HuH5jHUHU=HUdH+%( u UHHdH%( HE1HEdH+%( uHHH5 c=~ff. UHAUATSHHXdL$%( LeIW; t2 ff. fHUdH+%( ubHX[A\A]]f D LHeKt 1 D HHuLmHLHtHULLȸHt1f. UHAVAUAATLeSHH0dL4%( LuI f D H:&w@Is:HLGHHuHUdH+%( u H0[A\A]A^]f D LL f D UHAUATISHdL,%( LmI9 Ãtw& LHZ A H* HH 6 HDHEdH+%( 6 HLH5 1[A\A]] D LL% H5x* yyHUdH+%( H[A\A]] LLy9uHEdH+%( HLH5-* 1[A\A]]f D H5V# HEdH+%( usHL[A\A]] HEdH+%( uO H5) Ht/H5 H) @ Hz) E D UHATISHdH %( H]Hx5LHHEdH+%( ugHHH5. 1[A\]fHi H" 01& H5 ) H yHUdH+%( u H[A\]ff. @ UHAWIAVAUIATSH HHpHdL4%( LuI.Åt*HEdH+%( He؉[A\A]A^A_]f D LH H Le LL蜷H HxL(A AH0LE1HhH8H`H@HXHHHEI- @ HH H1H5' Aą E1HHHL0LL8H@AVH(IXZMtdH`H HpLhH)I)H`LhEaLH54' H1uAąhDfIDEo H5' LTf D LHuH0IL3,Å'L1H8H HHuA HEA LeHHLmL@ADML0 HELHLLH@Hx IHtsHEHULEH)I)HULEt)HH8L1H5% >Aąx"1 LH5% L1 AąyDH}Y"MADEu H5% L̻Żff. UfHSHH8dH %( HMLEHuH5;UHUHE EDE5HtUԉHUdH+%( uH]ff. UfHSHEH8dH %( H]H)EHHHuH5)E 5HtUԉHUdH+%( uH]f UHH0dH%( HUHHMH594HEdH+%( uff. UHH0dH%( HUHHMH5t4HEdH+%( u~ff. UHAUIATSHH(dL$%( LeIHE HE Ht\HHUL@uIH}HuHU9ƅu2H}HMHW Hu)<w<uH Ht<v<t! @ <} w3<ovGpGA$HEdH+%( uaH([A\A]] <t4<u HGG D ЃP<Ov1 G D W6f D UHATSLeH0dH %( H]H1t[4tVLHt/LH9t`1HUdH+%( uYH0[A\]f D LtŸ D L H+Ht}u f D LHq UHAWIAVAUATSHHuHhHUdH%( HE1HE HE )t%HEdH+%( Hh[A\A]A^A_] HUHuHuH]M?LuHtE1Lm IL9tLL LHq,uL;}uHEL}LHEHELHxHuHHIHxMI9 HEHp&f D } upE9EuhM9ucIL9xtVLL}LHH+HpHXHuH4HEH9ErLmHL+HEHMH9s HMHIvLLHS+HE UfHSHMHXdH %( H]HHuHUH5LE#0HEHEHUdH+%( uH] ff. @ UHAWAVAUATSHHXudL,%( LmI- oHELcuLeHEL=)EoC)ELLLL{/HH LHTHtwL-t?foELAE foEAEHUdH+%( } HX[A\A]A^A_]f D HuHpM)MLcua D 1 @ HuHt1xUH;UsoLAE oCAEp UHAVAUAATSHH0dL$%( LeI,u-LuHLNHtLDL f 1HUdH+%( u H0[A\A]A^]=f. UHHdH%( HE1^L H+ HcH>f Hi HX 1 11HUdH+%( I @ _wHJi H @ wwȉHRi H뻃wHi H맃wH<i H듃wHvi H|HEdH+%( DAXHi HH=H'i H-A"Hi HHqi H t( Hi H Hi Hp UHHdH%( HE1HEdH+%( uɸ:f. UHATSHdL$%( LeAH| H5m HHHt Eu4H<AHѮHEdH+%( u6HD[A\]f D Hqi DH 1A01臾Af. D UHAUATSH(dL$%( LeI( HEHH 1L19AŅ H=i .HCHH QH{H5% DH[8HCHHtxHs HHtgH{HUHs mH{11ШH]Ht#Hhi L H! 01H]HEdH+%( uJH(H[A\A]]H{Ht)9HC fCf D H}D}&f D UHAVAUATSH H $ HPdL4%( LuIƅ H LI豷 H bi Lff. 3tUHA LL(x-LHHtLH#H @ sHuLl#LHUdH+%( u?HP [A\A]A^] D HLH~=HL - UHSHdH%( HE1Ht/HHHtHEdH+%( u$HH]颫fHEdH+%( uH]膻f D UHAWAVAUATSHH H`HwHdL,%( LmAaHhH[ H{Aą= E1HEEHXL|L- JHh|^HH HX薻H H@H`AHE9t'H{DL7LHtAE9u1HUdH+%( HĈ [A\A]A^A_] Hh|HHtVHXHtEHPH`HH+PHAE9tH{DLLHu YOǹ UHAVAUISHH(dL4%( LuEƁ t 9O@tEt[HLPH^ HuH LEDL9 1HUdH+%( H([A]A^] H?H50 MM̄ttHLH H$t H#uHHHYHi H 0Hi 8 11Hi @$@HQi DH 0Hvi tI11HXi @,Hi H" 0HCi tb11TH%i @(댿 1;Hi 0H i D Et4H 11F 1 5 1Ho 1谷UHAWAVAUATSHHhHi dL,%( LmAD Eu H>i 8~Le L HtiA ~ HE1L}HxHELuHpLmHMMLHpHxAU蘱HXZH~ H;]sH;]sRHEdH+%( h He[A\A]A^A_]HHEHM1PHULMLLE=Y^H~f D H ai H~ 113HE3 w3ow^O HHH 11hQ ubHHL@HE 11:# D L@pH 11 @ HHH 11 L@H 11 PH 11 HHH 11rfUHAUATSH8H\i H i dL$%( LeIHE u ; w+HJ! HcH>f D 3H 11 LmHuLnL ALL1L輪LI$3LE1ILH 1L蝤HEdH+%( ujH8[A\A]] 3H 11 @ 3H 11v @ 3H 11^ @ 3H 11F ff. @ UHAWAVAUATSHH dL,%( LmI t+ HUdH+%( s Hĸ [A\A]A^A_]Ð8 :I1MtL` LuLLHILH>H0L H@8 HH(<H(H H8Hm 1LHID$ HtH٥HѓID$(H0ILAD$4AE 8AD$0ID$ID$ID$IEMeM,$ID$L HMLH5xL` HDž8 K HDž0 Kff. UfHATSHH HGdL$%( LeAHt0H fH*Yӫ H fH*^E˴EHHi H8Hi x x t2HEdH+%( H DH) 1[A\]&f D HEdH+%( H H [A\] @ HHfHH H*XY H1HfHH H*X D HEdH+%( uH HHt 1[A\]x Ӱ UHAWAVAUIATISHH(ML5ti Hc dH%( HE1HGXA~ E H<tE S4 Hcs0Hc1HH1HHHHff. @ PHpHH9uA~ tM9$ E K4HC(S0 LsL ~ H5 HIDP1s DEXZL;stgH= L{M9tREEMLLLM?M9uL;st*]EH H51 Ë]T1iHEdH+%( HeH=~ [A\A]A^A_]\A$ EM4$M ff. HcK4M9$ M9 Ic IEXH<Ѕ~NHcS01HH1HHHHfPHpHH9ukM6MuA$ K4E11GM6Mkf A$ ET11'RfUHAWIAVAUATIHuSHHGHdL,%( LmILp 8 HH M LƎHCH Lc LeLLc( I~xHC0IFxHttHs ff. HHHH;p sHHHHufHHHCH HEdH+%( u&H[A\A]A^A_]H@ j H14HEdH+%( uHH[A\A]A^A_]ff. @ UIHAWAVL AUAATASH(H dL<%( L}II9u f D HL9 C0D9t{8 tD9}C4A9}ِHuLxhLAoCAoGAC HUDc0S4!Dk9C8HEdH+%( H([A\A]A^A_] HE f D @ LEHHtHuLfLEyHE LLEHUAofInLEDc0S4ACAoGDk9!C C8I fHnHXflI &bfUHAWAVAUATSH H_dH%( HEHHHxH9( L3HCfo IFL0LkHCHpI9 M} HXLPMIEfo%Ҷ ID$L I]IEHhAe H9@ L3LHL@MHCfo- ID$L LkHCH`+I9 M} H8MIEfo5P IFL0I]IEAu H9N L;L0L(L MIHCfo ID$L LkHCI9 HEMu IEfoٵ IUHUIFL0IEAU H9 HH]LeLuLmIL}IIUfo= MuIWL:I]A} L9 LmL#HKfo _ LCIL$L!Lk M9 Iu IEfo 3 LLHHFH0A] I} I}(LHLL9t<IH6H{ H{(HM9 LM$$ D H{ VH{(MH莘M9tLM$$ D LmI} "I}(LZHEI9tMM?f D H]LeLmLuL}I} I}(LHEI9)MM6L0L(L I} I}(L˗H`I9t MM6XH8H{ [H{(RH蓗HhI9t LM$$LHL@I} I}(LSHpI9t MM$$]HXLPH{ H{(HHxI9t LM6HEdH+%( uH [A\A]A^A_]֦f D UIHAWAVAUATSHH HHLLdH%( HEHFH@H@ L`xM L`xMtM;T$ X Md$MuHL`LH@LLLHt0D@E1LHH BL HCLuMLLH@L`s(H{LL>LHB HULh-H@z4 uHH+BA)HLLD ٗHCHHx HLLHHt;HE1LHH D gL 1[ @ M;T$(rMd$ HC8It$0LHH8LHtHE+T$ D HUdH+%( He[A\A]A^A_] HF8ML0IL0H(HH@HH8HH`Hf. L(HLE1E1j HLL(ZY~ H0LHHDž8 LHtHHbL8MtLML M?M AuIwHLHtHCLmMgLH@L`s(H{LLƐH HMHPy4 uHH+QLH HrH HA9[IwH{HP-HM?MC L8LLMfLMm 褒Mujf. L HCMH@H@ LĔ1L5HLIHc@LH{HLH)gHHc ff. UHATSHdH%( HEHHt<If L訕LHHZ H{hH詑I$HuHEdH+%( u H[A\]胡 UHAWAVAUATSHX HGdL4%( LuIH@H@ H H0IF8H HDžx Mn0DždAEEM AF@Džh A} AFHZ A H@L @ 1 @ HHwi H 0Hi DE 11IFH=i IN0H5<i HPDIFI6H+BEo HLJ-I1PH 1[_AXIFIvHxWMf8HHHHXI<$HHoH AEEe LH`Hi LDE LH蛒1IH HHmi 01A HXHHHxHx@ < <MEMPD9d(uAD$+h` Hcډ@L`HA (H HP LIDAHxLPLD HXL H EMMAD`HPDLLLH ai HxLD@Ar eHPHHE HHi D<H 0S1XZHi H i D` 1A A ( DH G 11ff. HXHPDL `HxAFHWH HH蠡HL5 H1HPLHH0D L`pff. @ MtE;l$L " Md$Mu` ZIH HX8H AD$LID$(fHnHai flx' AD$( H0HXpLhpHV E|$Lf D |(HCHSHt(HD;{LuHs8I|$8JyHCHSHufI $LLAD$L" H 1e HLJ-Iؿ PH 1Y^f LH萎Iؿ H HH_i 01A LIN IVL`HHML HXHHHxdž< @ E1H@H L@LPLHMIH@ H@I<$LLHtHXL L HI<$HE1j E1LLA[ZtHSi LP0H{i ) HXH 1wHHi @ HPH߅ Y HIM H HHi 01 HXHPD6L i`HxAFHÉE1I~8׀HEdH+%( t HeL[A\A]A^A_]fAEHH@LL @ @ HP1A\A_ H HPLIHHxHs LHPL薳H- ED(MIl APC ƅB H@fD@ HPH蔋HE1HHii D<HS~ 0S1Y^fHIPMHv~ 1HH"i 01qP @ H i D`H} IN 0H&i EFHDE 11- LHxH HPIt$8HxH @ Md$f D @@I LAA|$ E;4$ AD$A9 AfIHi H 0H6i 11Cgf D H5 HT L@LP D IN H N 11/ hH| 5 11 D H@Hx@ H5HH HMH H( <o4 <O D@EF@DdH߽i ANDH 0Hi 8: 11f. @@I I: H@IT$LH5u 1 1 1 1q @ HXHz 11Q @ 1< L1Dd<uIF8AFDHhHdHXH8藵yDždA 1WEXMA HI?H5k HDž fHnH Hxfl)E XM H MfHnHPHfHnHHcflHfl)H)LMH<8HHHHHHH@HLL1foHHL)H H\i LzD<81IHi HW 01AIGHIHxHIIGHLLHxj M9tMIGLMHx H@H@I)H)Hzi 0Hi D0Etf11LH 8 MH8 D<IHi Hv 01` 1OHH H9t.HHRHGH9 H;Gz H@pHhHGHHH9t'HHHH HXHHJHHHHHHtHx HPH HuIGHfoH5^h H@HHH i @H(H)1H S HI?) tMH ƅƅƅƅeƅƅƅ-ƅUƅ}H0LH I9/ LMIBIZLXH L HFi H 0Hni D E 11yLXH HChH9 LLLf H(L HpIFHxLHX' L II# AF@A~D Dž t HIH L M?M M;guIF8IwLH8HtEGA D;t AwEW EuIcfo@HH HHfoPƄƄHi 0Hi DEm 11 L^)f HChH HXH9LLMH I9MLH HPL'1H9tEXHWLIT$L"K~HPLM$$H9uًX R L HXI;F I>H5d HH9XLI. Aw H@L EG AHbi HH 0Hi DE 1H@Aw L + HD E+G IF8H LHtLH8LDDžt5AF@I>HHDžp L l܀H蜐" HC(HL`-H5p LHMi MDHW 0Hoi DE 11z tƅ tƅ tƅ = tƅ< e tƅd tƅ tƅ tƅ tƅ - tƅ, U tƅT } tƅ| tƅ tƅ tƅ tƅ H HHLHHX躝HILc0fo DH KMHfo0ƄƄHi 0Hոi DE 11KHX8H H$HaS xdI xd? LcAvI~H HWHB H HcK6HHHLL LtHX#t Ik(fo DDLXH fo0ƄƄHSi 0Hi 8 11Mk(H@B%J< ff D 1\LXm?xo5xv+A~D LcADDHXDDyHcHH Hk( < t< N 9@ 92 9l r uI~HXADHGH HHpHH HHLHXIHHL@H HX@H&H Ik(fo DDLHn fo0ƄƄHi 0HAi 8 F 11OMk(HXB% ! DAMcIk( l9DpH DA)HHPH9g B0A9tz8 tA9~B4A9}Ik(H@Hz8 HX DDH A)Hi 0H'i 8 115Ik(HX MIH=i LIw0IGD?LLc&H@DNH5~i +HKL63 REH/l 1P1Y^KHt A;_@ AD J Ik(< t<h < IGH@H@ tIG0x @ Hi H 0Hײi 8 11H CHAH+ Hfi H 0Hi 11Hli Hx@ dtREHj P1gXZHc Hk(6 DA IVHJHI t + DAQ IcHk(HHH逼 5 oMcEIk(H5i oD0HQi ƄH 8 11HMk(H@B%J< f 1d 1tMHH L'H9AHGLID$L rH LM$$H9uHHtHHorHuELHKi Hx@0CrH HP+ 1?ZH Hԩi L Hah 01IFH HPHxHrHpHlHIF8H8rDžl= HHHIFH@HPH@HHHX菶Av(I~HXHnHi HPHH-H@Hz4 uHH+BHX)tMsHH5 uIk( HBIFAHXHcH@H HP t:HcA9uHcw"Hk( tu HHHL LL@DLXTLXD IcHk(Ƅ IGIwHxHh IHi 0Hϭi 8 11IG8H@H LH8`y Dž H ; AWH@HHPAA)H9u; H HPH9p0A9tx8 tA9~DH4AE9}D@9A Ao@))o@ )AWHHPL'H9= XkHi H: 0Hi 8 11H HPAWHHH9u fH HPH9H09tx8 t9~H49}H90 o@+P0)o@ ). 13m 1"@Hk(H@H HHH H+HXppAHXH )H HPH9 p09tx8 t9~p49}Հx8 D Ik(o@o@ P9Ik(D)DADH ƄHӤi 0Hi 8 11Mk(H@B%J< cIk(H i Afo HXD1H i fo09 ƄƄt!WEDH P11vAXAY]RDEH P 1RY^; 1?*+P0L HxDLXuH Ik(fo X Dfo0u 1#HcHXH(O HBHXL L@HHH MLHPDsD @LLD蜬DH Mcfo DDIk(LXHa fo0ƄƄH~i 0Hi 8 ti11Ik(H@H<HHGHBHkjzH@H H<ϫHud 1SIcEH` DHk(ƄƄHΡi 0Hi 8 11 Ik(H i Afo HXD1H i fo09 ƄƄt2WEDHa P11AXAYu 1ylRDEH` P 1YY^BIG0H Lc`Hi 0Hi 8 \ 11!IW0z t2HcB9uHcw"Hk( tu IIWLLHHHL@It@AGH H HPL'H9MIIF0H]x D V@L H߹@ @ P1c_AXIF0ENHIH_ HH̟i 0Hi 8 ty11 L E1mHH L'H9HH9T 1ML1 1 1낹@ H1L2 @ * 1^$HXH@HD芩DHy E1L@HXHDIk(HDDo Bo B H@DJ0J4J9!ȈB8 HH AL'H9HHHi H 0H&i 8 tW118I?H5M tIG0@ @@( H HPL'H9 Xk 1H}i HG 0Hi 8 11Ik(HH@Ho)oIG0@)AGHΧTAGHH;@CH <ƄHXx#Mk(BƄ% 1 TIFHcH@HPH@HHHXI~Av(HXH bHXHH fHH5 Hx-|ZIk(DDH ƄHi 0H7i 8 te11IIk(H@DH HXD 1IcHk(Ƅ 1fIk(L@ILtItDIG0x y ;4`H=i H 0Hei 8 11s\Hi H 0H7i 8 11EHLHHIG0H@Hߋ@AGHp;4IWHHHcLHL@IH qi Hi 1 HB 11@H AGHHPL'H9~MI@LLDX赣H Ik(fo H i D1DXfo0ƄƄHӟi G D PHX 11QDAYAZ 1H< 1oIcHk(Ƅ e 1aIcDEDHk(HS ƄDƄHʘi 0Hi 8 te11 x I?H5G 轧unIG0P HW 1QD_AX 1j 1t}RDEHW P11Y^kH i H 0HDi 8 tf11VIG0IWHL@HHILHcH:AREDH^W P 1A[X 1ff. UHAWAVAUATSHdH%( HEHH Iff. @ LXcLIH I\$(M|$(L9tKL+HCfoL{ HIEL(H{ H{(ߑH _M9t LMm fAD$P1ۅ~ D ID$XH<H襑A9\$PI|$X蔑I|$8AD$P 聑L^IH6HEdH+%( uH[A\A]A^A_]n UHAWAVAUATSHHHuLEdH%( HE1HtkHX IA| # A9_L HEHuHcHHc IGXfHnH IcfHno flHD`fHp1HUdH+%( HH[A\A]A^A_]H LcwL Hc@IIHljELuHE聴IGXHtwUE1| @ IL9utnH}N,IE IGXJ< uAVEt/HcIcΉH)HL$IGXH<HI9uIX؏% EAGPlff. @ UHAWIAVAUATSHXH D dL4%( LuIHH Hwi x t M9 I H H5rT A HP81qH2i x t M9 Hi A H 9 x ux A H 8 H=?T :HDHAH PL 1L H5 M AYA Ic AZID$XH<Hi x tA AT$Ln Ict$HHc1HH1HHHHfPHpHH9u+H,i x t M9 A AL$LID$@AT$HH IH5 HHDE1I\$(P1At$8 _AXI;\$(O H= MT$(L95 H]DmD}f D ID$XIc A H<H{i x tA AR4 Icr0Hc1HH1HHHHff. PHpHH9uLUHi LUx t M9 A AJ4IB(AR0H H5 IA HHDP1Ar LULUY^MJM;JLM H= LULULMIZL9 LULMDmD} ID$XIc E H<HJi x tE S4 Hcs0Hc1HH1HHHHff. PHpHH9uHi x t M9 E K4HC(H= S0A IH5 LkHHDǿ P1s XZL;ktcH= L{M9t L LLͷM?M9uL{M9t)EDmH H5) D1AU cH=7 wHH9]LULMDmD}IZI9t,DH 1LUAH5 S LUH=?7 LULUML9UH]DmD}I;\$(t$DH P H5r 1A H=6 HEdH+%( Y Heظ> [A\A]A^A_]H U= >A E@M.M; D HcK4M9 M9 Ic ID$XH<Ѕ~NHcS01HH1HHHHfPHpHH9u蛴Mm MuA K4E11wMm Mj A E11XE A>I H8M IcM4I9 L9 Hc ID$XH<Ѕ~NIcU01HH1HHHHfPHpHH9u軳HHuME AJ411藳HHkf ME 11H1A LL- 6 D DI9 t+L9 u"H L1Db YHHuE E AI H IcL$LI9 L9 Hc ID$XH<Ѕ IcT$H1HH1HHHHff. PHpHH9ukHHuE AL$LLA HG0H0H9D H@0H0I9u11HH% E 11&df D UHHHdH<%( H}HH0H tgu"H01HUdH+%( AAptAu%H2Iu>AAAA t\ D HNH9rH6H2H @ tPwnt)uHNH9rLHL[ D E1 LNL9rLLH 5 LNL9wHcLLH f tZb UHHdH%( HE1HEdH+%( uɸbf. U1HK HHdH%( HEHOi 01螼HEdH+%( uɸcb U1H HHdH%( HEHi 01NHEdH+%( uɸb U1HJ HHdH%( HEHi 01HEdH+%( uɸa UHHdH%( HE1HEdH+%( u HWi HHJ 01陻ta @ UHAWAVAUATSH HPHGHHH@H dL4%( LuA藂HIcH HH H)HH9tH H$ H9u H)H HL|$wLPHhLHII4$HXH AŅ HhH A ID$HT H8蓤HH HPLLAŅuZI_A 2f D ~5LHھ tvL ZH+AHLDE9Etf. HPx u3A A AuHzi H5 101HEdH+%( HeD[A\A]A^A_] uA f D E9AtH ۆi DD)Q(tAD$HE1 I HtHPLhHHHXMHھ LHX膝oHH)pfI~MtAy4 u}IAHI+IHHG Iؿ HHH-H HDHQi 01蠸H@HpHHHXAPE I HL YHi HG 101<w ;k Hi H=A H HP;k H@dHi H- 101ַA] UHAWEAVIAUATISHHHH}H:dL,%( LmEHM蟁H LeHEDmt9E~4HuH}DLHUdH+%( uHH[A\A]A^A_] ] @ UHHdH%( HE1HHEdH+%( u}\ UHHdH%( HE1РHHEdH+%( u 114N\ff. @ UHAVAUATSHdL$%( LeA I ILH Dv HH}H AŅt*{ uMHi DH 101 /f D LEDHi H M01ҵE1HEdH+%( uFHD[A\A]A^]H HAi DH 101脵AU[ D UHAWAVAAUIATISHxI@dH %( H]LH |E L;I HH HxH XAƅu|HxI HHhI I9rzIT$H9spEI L A)IcLHEi HC ME 01艴 IE E1HEdH+%( > HxD[A\A]A^A_]LuLdH{LL @mL}M AW( D AO(9t BJvL7LI H HSA MLL2LH}HEH ^i A 3LhL1LxHB 芳IE D LKL 1H i H+ 3QAf LH}H ـi AXff. @ U1HATSHdL$%( LeIH=ȶj sHHL%xHt' Hӏ1HUdH+%( u)H[A\]HJi HB 101萲dX @ UHHdH%( HEHG H9tHEdH+%( u1 HH+GH;FsHFX UHAWAVAUATL SHH HLHHdL<%( L}MHL IjH0H S(fK(9t BJvLILk M H$i I HA 01`IP LHDžHHw IGHH5H8HEIwLIP LHA M+8 HEHLMH H8H LMHuLLHd MHLLF HL MHH DH)1HHH HDžH H!oL`IHHhLLp)0hAHyHEdH+%( i H D[A\A]A^A_] D IwLdAƅ 1Ҿ kHH HuHHXHHH E1H B LHHHt|H0IH H8IP D1Ҿ HDž HH% IDž8 L4 D LGA D D1Ҿ |HDž HH DžHHH HtIE1HLI LL#Ht tuHH;rHLHLI8 3uIP ff. A D Dž 6HLLHH#0HuIDž8 L03HwLSf. f UHAWAVAUATSHdH%( HEHi 8 u*1HUdH+%( H[A\A]A^A_]f D H~i Ln HIL0Ht2Hzi I H< 01ǬMtA$ HvIH H Hx LLwAŅJI sH5S) HIN H5P/ L7tH5r L$uAu Hczi L0Mu;/k Hyi LH; 101/k fLH7H WHMA$ AtHzi L0{vQf D UHSHdH %( H]HVHt!HUdH+%( u'H@HH] @ HEdH+%( uH]Qff. UHSHdH %( H]HNVHt!HUdH+%( u'H@HH] @ HEdH+%( uH]Pff. UHAWAVEAUIATISHH(H}H:dL<%( L}EUHt>HMdH+ %( uOH}H@H(EELHL[A\A]A^A_] HEdH+%( uH(1[A\A]A^A_]Of. UHAWL= AVL5 AUATL% SHHdL,%( LmIH" jAE t^<"( <H PZ IcL> Hٺ H=e g AEIuHEdH+%( HH" [A\A]A^A_]Օ D Hٺ H= D Hٺ H= D Hٺ H=1 ǷbfHٺ L諷Ff D Hٺ H= 臷"f<\uIHٺ Ld HY H1H< ~ Hމ֔Mff. UHAUIATMSHH LXt&)`)p)U)])e)m)u)}dH%( H(1@ H NH AH 4H 'LHlHٺ H=I SHELHH H0HDž( Dž0 H /H(dH+%( u'H [A\A]] H, 苓+LUHAUIATMSHH LXt&)`)p)U)])e)m)u)}dH%( H(1@ H H H LH9Hٺ H=VH HELHH H0HDž( Dž0 H H(dH+%( u$H [A\A]] @ H, [;KUHATISHH L`Lht#)p)M)U)])e)m)u)}dH4%( H8H, H ݑH БHELHH( H@H Dž Dž$0 H0H8dH+%( u H [A\]Jf UHAVIAUIATLcSH LPLXt&)`)p)U)])e)m)u)}dH4%( H(L Et!1f L HϐI9uHEL LHHH0Dž Dž0 H H(dH+%( uH [A\A]A^]Iff. @ UHAUIATISH LXt&)`)p)U)])e)m)u)}dH4%( H(L L ӏuLLL H=0E HE LHHH0H H Dž( Dž0 ҚH(dH+%( uH [A\A]]mHff. fUH -{ HAWAVAUI1ATIԺ SHH@ dH%( HE1H11MLA H u H{M ID$H fx( Ml$MtMm H, 莎Mt$H |A I-fH cAuH58r HL=C LHٺ 肰LHwMt"M MtA} uOff. @ HEdH+%( HHH `4 1[ A\1A]A^A_]g H, A 譍H 蠍H 蓍AuHH5 LHٺ 蹯LHYF @ UHAWAVAUIATSH H8H@ HH dL4%( LuMhIH@IHHX{LLL:^ H8HP H ƀH 11H x H7MM11L H HH@ HLf H DH1H@ HLxf H DH 1ZA H@DOE TCH, IH H ʋH 轋H 谋H5k HHٺ H=A حLH1 HL H I HV HHz Huƅ0E11H A H(H\H L D0E LYyLHDH@蔂H8HHHIELC6I AOIHH9 H\H wSH(, z EMXHߺ 1Ld H H@Ef D E1H H H Hki H Hٿ D01>I DHAOIH9H(11H | HMI HH0 ,zIH H8 Lu H0ML8Iff. L8IL}IVI L LIFHLe, LhH H H H ݈LH"Hٺ H=?> LHI> TL0L11H / 1H H41HUdH+%( H [A\A]A^A_]f. ƅ0X @ ƅ0H @ ƅ08 @ H, OLejIu HH8Hhi H5 101HD3;@ D UI+ HAWAVAUATLSLHh ~hi dH%( HE1li H)H~ni H thi )~li ji ) ~7hi 0ii )~ahi gi xHli z ~ mi f HHii 4li ƅH)fLDž L z ' <I L1A Ӻà H5R :#HH$ HL1tIH= ` Hx@ h H{ ÅH11H GH1H 8I x# D`HEM 11L: H W HH0Dn~ HHxLL%: Hx8H LHH, H لH ̄H 迄H5ϣ H LHٺ LHMML H1H MM 1L{ H HMM 1LU H d HH, M}@ H H H H5O H'Hٺ L LHH, M}H覃H 虃H 范H H5 HHٺ L 諥LHH, M}X?H 2H %H H5 HYHٺ L DLH9M}hMtcH, ӂH ƂH 蹂H 謂H5 H LHٺ ؤLHH, M}plH _H RH EH5* HHٺ L qLHfEM`1 Lc7 H V HpEMd1 L=7 H > HJA H, M}P諁H 螁H 葁H 脁H5 HHٺ L E1譣LH1 HL H Р A ] H H H H I HJ4I!E9 ~@MtH, 趀Hai H$ L%6 01 @ L%|s H11L H & H11Hٺ H 1H ן LWH11L H11H1H M 1H ci HH$ H;3HL O4fH;LH* `2 1H$ YYh3LH4FHEdH+%( Hh [A\A]A^A_]ú Hybi H= HhH1 E LX4 H $ mH1 M L H = D H1M L H HxA Hai H= H谠HG_i 82tPHʜ 11舑H _i H! 101eH_i He! 101JH! 118H'ai H=W H?.6 UHHdH%( HE1HEdH+%( u16ff. f UHAWAVAUATSH H $ HHH dH%( HE1HII H蚭H5D HH. IHA H=! 6L= H=! LI H=" LJ H=H" LI H=" ҞLE H=" 蹞LQ H=" 蠞L' H=$# 臞L H=ԛ nL H=ƛ UL1 H=# <L3 H= # #L" H=?# L H=o L H=l ؝L H=g 违L H=i 覝 L H=b 荝L 1L牅ArH1 E( HDž HH HH LH A L$1MD$IL$H.L H= L H=ݚ ֜L H=Κ 轜L H= 褜L H= 苜L H= rL H= YL H= @M|$(Dž M IL7M?MtTA]L H=d i=3333wL H=& ћDA D L H=td 觛DAEiA3333wL H=ޙ sL H=ə ZL H= AL_ H= (L H= M|$(M 1L-` 'f D Hv L1z,M?MtOw IOL L1Q,IG8 uH+ L1 (,M?MuH L1 ,Ml$(M L1E1 EiAǙA2333 L H= LEHH HHHL@1+IM 1H LIl+Mm M? EgAi=2333 IE8@H EiAǙA2333% L H= ; @ L H=b 7ië=UUUU_L H= A H, L1* D L H=2 ǘ&fL H=ta 觘fI}LE.4Mm ML H=8 gLO H= NL H=B 5L H= L1H3 )L& H=B LE H=Q ԗL< H= 軗LB H= 袗L H=u 艗 L1H )L H=P ZHH9HLO H= L/ H= LO H= L1H w( L1H^ a(L9;HWi HH H819(1HUdH+%( HH [A\A]A^A_]fL A H= Q @ L A H= )HWi Hپ H%c H81'e, UHHHdH<%( H}HHUdH+%( u HHf,UH=P HHdH4%( HuH5 x< UHAUATI SHdL,%( LmI֗HtuI|$H4A1HHw{I<$ A HH^{Au HEdH+%( u@HH[A\A]] I|$@ HH {H5 H=> ;+ @ UIHAWAVAUATSH8dH%( HUH E@ IHwIH- M$ ELE5 1fuHuHuHuHLMILuHLU E1E1D]ff. fDL4Hu[uIcMHLH 1D)Hc[RK?ts HHH#Utb H 0 fuH˄uHuHuHH AHEAHpPHEdH+%( u5H8[A\A]A^A_]fH 0 D 1p) UHHdH%( HE1&H5 H=f 9 UHAWAVIAUATSHHHUdH%( HEH HE HEH HEf H]H}]pK9r H}1E1z9H}A螀D9 D I HXL;c HEH;C HCHHIHD(HËuH}@ EmHEH LXH=k H H1KPH=k f _Hx: /AHuH= k H5k iIH; HSM+ Ic H}1HwHc} H} H{wH}Lm螙 LH^wH;Lm肙 LHBwH{Lme LH%wH{LmH LHwH} Zr HuLu&HH H x HH H}Hx HHtaH}At$I7H}A~D9 HEHNi H Rk Hq 01 1 ;f +qHEdH+%( u"HH[A\A]A^A_]H5 H= 6&H5 H= 6 UHAWAVAUATSH Hx HpdL %( L]L McuMc1LhLhHI M I; LXE1LH`n LHAL;A r HHLI)H-1Ho LQMLI!H5M HHHh0 HhHx HH HxIT$LHp HH3 y- ) LHAL;A r HHI)H-H 1 LLL H5M HHHh HhHx HH AD$H tH R uH < H: L1,LL$ H5 HIH IE xHIE H= AD$uH= H52L HIH IE xHIE k H=q AD$uH= H5L HIH IE xHIE 5 H`H.Hx HH LIIHXL;8 LX NHH HxI$LHp HHt y- JLH 1H LJ`H \ H L1 Jf D H 1 HV H LR L L L`HEdH+%( u;HĈ L[A\A]A^A_]H5 H=o J2H5؊ H=\ 72""f UHAVAUI ATASHdL4%( LuI荍H IcHy1HH,qLt HHqI H HHt\H x HHtEHx HHt%HEdH+%( u7H1[A\A]A^] Hf D \2!f UHAUI ATSHdL$%( LeI袌H I$ H1HH<pLtH| HH pI H HHt\H x HHtEHx HHt%HEdH+%( u7H1[A\A]]f Hf D d: f. UHAWIAVIAUATI SHdL,%( LmI蘋H LH1HH7oI~(n HH oI R HHoI$ H HHtaH x HHtJHx HHt*HEdH+%( u<H1[A\A]A^A_]f. H f D { D f. UHAUI ATSHdL$%( LeI肊H I$ Hi 1HH nIc|$R HHnI|$(H HHD: HHmI H[ HHtZH x HHtCHx HHt#HEdH+%( u5H1[A\A]] Hhf D [$o f. UHAWAVIAUI ATISHdL<%( L}IXH I$ H?1HHlI & HHlL HHlIc|$ HHlIc|$ HHlI H HHtZH x HHtCHx HHt#HEdH+%( u5H1[A\A]A^A_] Hf D f. UHAWE1AVAUIATSHHdL$%( LeIHtLxID$E1HtH Ii RH)L0 HH I|$1HH~kL HHfkL HHNkI|$ HH4kI HHHt\H x HHtEHx HHt%HEdH+%( u7H1[A\A]A^A_] D Hf D |Rf UHAWAVL}AUIH ATILSHHdL4%( LuI" 訆H I$ H1HHBjI v HH&jI$ i HH jI$ L HHiL4 HHiI HUHHt\H x HHtEHx HHt%HEdH+%( u7HH1[A\A]A^A_] D H`f D S gf UHAVAUI ATISHdL4%( LuI]H I|$(HG1HHhLMH: HHhI HHhI|$ HHhA|$ HHhI H HHtYH x HHtBHx HHt"HEdH+%( u4H1[A\A]A^] @ Hf D f. UHAWIAVAUI ATISHH>Ei dL4%( LuI@I)H I?H1HHgI HH}gI|$ HHcgI|$ HHIgA|$*@@v HH&gI|$-l HH gI HHHt\H x HHtEHx HHt%HEdH+%( u7H1[A\A]A^A_] D Hf D T*f. UHAUATSHdL$%( LeI@ 蕂HEH H=Yj L-Z LXHH H; LmL:1LHeH}о Oa HuHjHH H x HHt^H}Hx HHtBHEdH+%( uUH[A\A]]H=i L H~ 011p S뷐KH5,~ H={ %H5^~ H=^ %f UHAWAVIAUI ATISHHHEHuLEHEHELMHEdL<%( L}D} H^ H}H1HHdI HHdI|$ HHsdIc|$X HHYdH} HH@dH}w HH'dH}^ HHdH}E HHcIc- HHcI( H^HHt]H x HHtFHx HHt&HEdH+%( u8HH1[A\A]A^A_]f D Hhf D [$of. UHSHH=Tj dH4%( HuH5| THt9HH8t*H1HH H x HH H=j H=j HtHx HHtMH=j HtHx HHt!BHEdH+%( u7H]1 D kf [f Kq ff. UHAWIAVAUATSHHxHEHxHEHEHEdH%( HEHFH IHH MMH Hh(HxHHHpHpHhHx HHm HUH HHx3vHx LHHHxHxHx HH7 IGH8kLHIHzIx HI IGHx9LHIHHIE xHIE IHtsH- HuHIHI$xHI$ IWI(HBH;z sVH)辂HuHIHI$xHI$ HEdH+%( Hx[A\A]A^A_] @ IWH HHxHxx D H L L L+ L]^ff. UHy HAVAUATISH?H=j dL4%( LuIH5x HD9QH HI4 {HH I|$]1HH _I|$F HH_I|$, HH^Ic~X# HH^Ic~ HH^Ic~ HH^LH&HHtrH x HHtVHx HHt HEdH+%( u>H[A\A]A^]fHEdH+%( u HH[A\A]A^] D "fUHAUATSHdL$%( LeItn I!zHHE H=j 1HH]L HH]L HH]H5w Q yHH H=Cj 1HHQ]L HH9]H5v H=Cj NIHt3H2t'LH HH H x HHtSHx HHtHEdH+%( uOH[A\A]]ÐHEdH+%( u4HH[A\A]] 릐H5cu H=R{ - 3 UHAVE1AUIATSHHFdL$%( LeIHtLp( pxHH I|$PZ1HH \I$H = HH[L% HH[ID$Hx HH[I|$ HH[I|$ HH[I|$( HHi[I|$@ HHO[I|$H HH5[ID$H Hxd HH[Ic|$`J HHZI|$X0 HHZI|$0 HHZI|$8 HHZI H- HHt\H x HHtEHx HHt%HEdH+%( u7H1[A\A]A^] H8f D +? f. UHs HAWIAVIAUATL%s SH dL,%( LmILEvH LHVQH=j I1HHYL HHYL HHzYL HHbYH=sj L#KIHt3H.t'LHHH H x HHt`Hx HHt(HEdH+%( u[H[A\A]A^A_]f. HEdH+%( u3HH[A\A]A^A_] H5q H=w N9 T @ UHAVAUATSHdH%( HE1HtMHL-u {w:CIcD L> @ HKH5ej H HHu @ HEdH+%( H[A\A]A^]H{gH{^HHu @ H{GH5j 1ҿ L5j Lcf IL$IT$L yM$$MuHH$_ H{HS H5j JL5{j Lc ff. @ IL$IT$L M$$MuHH H=)j H{sHHj H H{ ?H{(6HHZ D H{HH;vf D H{H{H{ HH Dff. @ UHAWAVAUATSH(DnH=Gj dL$%( LeIL~(H5o AGH HI+z AD$ ID$0HE rHH A|$w1HHUA|$ w HHUIc|$ HHxUIc|$ HH^UIc|$ HHDUI|$ jw HH*ULRw HHUH}Y HHTA w HHTIc|$p HHTIc|$t HHTLH1HH H x HHtuHx HHt=HEdH+%( u]H([A\A]A^A_] ID$(E1HEf HEdH+%( u H(H[A\A]A^A_] f. UHAWAVAUATISHH(=j dL,%( LmIt<HEdH+%( H H(LHH[H=tj A\A]A^A_]wf D GH=j H5 f у`ME"EIH H( ;EAu C D{E PoHH I|$*u1HHRIc|$X# HHRIc|$ HHRIc|$ HHRIc HHRHc} HHnRIc} HHUR}I HH<R}sI HH#RIc$ V HHRIc$ 9 HHQLHnHHtzH x HHt^Hx HHt&HEdH+%( uFH([A\A]A^A_] HEdH+%( u H(H[A\A]A^A_][ Sbf UHAUI ATSHdL$%( LeIbmH I|$ HL1HHPID$H . HHPID$Hx%H HHPID$H H HHPI|$( HHvPI|$0 HH\PI|$8 HHBPI|$@x HH(PID$H8[ HH PID$Hx= HHOID$HcxX HHOI|$H HHOI|$P HHOI|$X HHOID$Hx HHcOID$Hx0 HHEOID$Hx8w HH'OID$Hx@Y HH OID$Hx`; HHNID$ HHNID$ @ HHNI|$` HHNID$HxH HHeNID$HxP HHGNID$Hc v HH&NID$Hx X HHNID$Hx(: HHMI HkHHN H x HH# Hx HHt3ID$x t;HEdH+%( H1[A\A]] D H`ID$x uI t iHH I|$ x1HH+MID$Hx] HH MID$p\H y HHLI HjHHtQH x HHt:HHH H D f D s<fUHAWAVAUATISH1HhdL,%( LmIcHI IH)i x H $HI} HIH'i LE1E1L P)ZY M IGIG IG IGI9 I_ H &IH H;CH57 LIHI$xHI$ H{ &IHI HCHxH5 k LHHxvHxHx HH HCHx H5 LHHx5HxHx HH HCx*@@H5d LHHxHxHx HH H{w(H-H5!u LHHxHxHx HH LH5 LzI$xHI$ LcM H{ H ?:A <H5c LIH'I$xHI$ HCHt_H@ H= Ht!H 'i y H H H5%} LHHHx HH IG LLH@PIGIG IE x\HIE `LIGI9XHEdH+%( HeL[A\A]A^A_] H V @ II9Gf LK 0 Hx+ H}HxP.A|$4 HHx HEAT$( AL$(9t BJvHsHELeHVHH)HxH;F Hx H5a LIH1I$xHI$uLH{ H D H H HxG Lh_ HXX I$H)HxF D ID$I+$f. H i HR 101QfLCH5 H=e H5.` H=e x UHAWAVAUATSH H $ HHHx$i fo0 H HLcIE|$IcdL,%( LmIHH8H)Džext DHk L1HA aHE~ f D K|1`JIE9}H5 !i Ht_*HDHH5 aYHH H11 AŅ H=_ `Hj HH tHj H tH=_ _HHtj[Ht`HH#i 11H8 HHIt7H5Y_ HHkH5G_ IE xHIE H=j HtHx HH H=j HtHxHHuHf i H H H81A H=j LIU x HIU uLAH=\j MH5|^ 6IHt6Ht*L1HHA H x HH L5j 1' LHLAŅ H=j H5,^ 5HHt4 =j tL k E~ INd @ I>IM9uHHEdH+%( z HH D[A\A]A^A_] H i H Hf H81dO#E~INdfI>IdM9u{f. H=j H5E] Hj 4HHt3 l H=j H5 ] Hj F4HHtf3 tTHj H H Hj Hu5H5 H=_ f. $A f D Hi i H=j H5\ j fP3H HHf| HH Hj HJj H=j H5R\ _3H4 HH HHHBj Hj H=dj H5!\ 3H HH HHHj Hj H=j H5[ 2Hv HHy_ HHsHj Huj H=j H5~[ r2H HH* HHHmj H.j H=wj H5A[ #2H HH HHuH&j Hj H=(j H5Z 1HY HHB HHHj Hj H=j H5Z 1H HH= HHHj HYj H=j H5}Z 61H HH HHHQj Hj H=;j H5;Z 0H< HH% HHH j Hj H=j H5Y 0H HHP HH*Hj Hj H=j H5Y I0H HHtnHH/Hj HIj H=Rj H5Y /Ht6HHHt Hj i L1Hj Hj FHj Hj Hj )Hoj HWj kH?j H'j Hj NHj Hj = LH=9HRj HuH5 H=Z f D AH5)W H=_Z ze7tff. UHAWAVAUIATSH HHHLdH%( HE1HH{ IHj H|HHH5W IHkI$xHI$ H HxhHH5 IH'I$xHI$ I} hH5w LIHI$xHI$u I}(4H5r LIHI$xHI$1 A}H5q LIHI$xHI$ A} \H57r LIHWI$xHI$ A}X(H5˝ LIH#I$xHI$e I} d H5& LIHI$xHI$! I}0 H5c LIHI$xHI$ I}0H5b LIHI$xHI$ I}hH5U LIHSI$xHI$U I}H51q LIH I$xHI$ HH@0H? E QIH HI8 蜽IWHLH5T LIx HI I}8H5 LIHaI$xHI$ I}@H5 LIH-I$xHI$ WIH I}`]H5cT LHHHHx HH IE`Ld I$ H`HHHL$HH5S LIHwI$xHI$9 HLH5u KIx HI Au\I dHH5S IHI$xHI$ HH8iHHH5 IHI$xHI$ HS LHL S PH LS PH S Hj LHH57T LHWH^_x HH HM A H M`HtM`1LINLHH Ms I8 i LE1LH 2 f D H H H58R HHHHHx HHO HIT$LA H0H= Ht8H@ Ht/HPi z H H ff. H5Q HHHHHx HH LH H Hx HH HIIL;8 HHB I<$H5 HIHeIx HIi I|$H5 HIH2Ix HIF A|$ ,H5P HIHIx HI A|$@+H5 HIHIx HI A|$@+H5 HIHIx HI A|$@P+H5 HIHKIx HI A|$H5;d HIHIx HI L LHI$LA dH0H=y H H@ H Hi z H I8 JIH E8 I@ EHL HHE1HHIff. HHLIWJIE98 L X D L L LpZ L` LP L@ L0J L L L ~ L: L H @ H L H$ H? L Lp L` LP L@) L0T LH HHH5M H]HHx HH HLH0 HH5L IHI$xHI$y A A H5L LIHI$xHI$B H tr 'H5wL LIHI$xHI$# HL HHL LPHL L @L PLIL H UL XZA I}HHt I}P K HH|HH{pIx.Dk Ic-IH HspEHLI wLHH5 L HHHHx HH HELLI Hp`L_HH5K IHFIE xHIE p LxHEdH+%( 3 HHe[A\A]A^A_] I0 LH5%J LHHHHHHWfI( H5I LHHHHHH{f. HHcI b ff. ff. HH~ Hu HH5I LIHI$xHI$ HA @ H=HH5I LIHI$eHI$WL Jf JH.Gf ;H5I LIH6I$xHI$5 A H5H LIHI$HI$L} Hh< LX HD^ H0I L z L L L L$ Hнb L L谽 L蠽 L落9L能Lv+H5 H LIHI$x HI$tYI}PH5G LIHI$_HI$QLD LLH5 H=H H5 H=@I {H5hF H=H hH5C H=H UH5 H=I B-H5C H=H *f. UHAWAVAUATSH H $ H H $ H GXL LL0 HH:HHPHHxdL4%( LuE1 HHpLHM LH5|F L辿L5j MMMEHH L1H XF }QIcM HHH HHH H1H H=uj L%HH H 1ۿ@ iEHH HSZ/D L1H HH Hi ʚ;H`1I)Hi LXH8fLIH1H(HL (HxHH HH ltHcLcH 藺H5DE HIHIx HID H`bH5E HIH]Ix HI HX-H5D HIH(Ix HI LH5kD HIHIx HI HpH5D HIH¿Ix HI@ LH5nD HL蕿Ix HI M}( MB LA} AW,A(֨ M,<t L LB:Ig8IHtu D IwLHIE xHIE M?MtnIG8wIcw(HAW,LBHAG8u H 蘸IHuHAFDLꉅ4&M?DMuDHI DvIAHH50C :ItOHtHH5C 9I1MtnLH5 C 9HHt5H HHx HH( ff. I$xHI$ D9 HHx HH HL HHHH H x HH+ HHx HHu迶ff. @ HEdH+%( HĈ [A\A]A^A_] H=j H5RA UHHtHtHH)H5-A H=>C f Ii Hi LH H8IG8AW,AW( D LصH L(IDnDvMHH#I}8>f۵H H#H`軵H Hg#HX蛵H HG#LH H+#HpoH H #H H"M}( MA A A f. 諴L牕蘴D9HLHPHxHHHLEoH[" H:HH$HLLqL3L߳LҳA A A \ HH j L H߹ LH1jJHH=p@ +H5: H=]@ #H56: H=E@ UMHAWIAVAUIATISHHHh dL4%( LuMIHHH8L{W = j t>HEdH+%( HMMHL[LA\H=j A]A^A_]LfH=j H5Bj Hprocess_H1j Hs_event H&j KIH H @ <HEH LHLLLHILvH}1H H} j HuLHH H x HHtyH}Hx HHtUHEdH+%( u`H[A\A]A^A_] HEdH+%( u;HLLHL[A\A]A^A_]f[f K}H5s8 H=< H5 8 H=< f D UHAWAVAUATSL$ H H $ L9uH8 dH%( HE1LHAL1HHJ H0lj H`E1A1 pIH p H; LJH`ADž HLȾHH1LDž @ Hؾ|n AL@H`L AHEdH+%( H8A D[A\A]A^A_] }H @ D+HcHHH92]f. Lx1s @ H @ D+Hc҉H"HH9DA U1HATSHdH%( HE1H1fE x"Hu I1ItHUdH+%( uH[A\]Ef99 f. UHAWAVAUATSL$ H H $ L9uH $L0HH59 LdH%( HE1HHf/H(H HLÅ L1HHDž0 HDž8 LHHDžP H> LF AHPH A E H8HuH(ȮuH L(HLH0LH8{ H(w EX $LH)IL9 LHHDžP EC1A LH(HEdH+%( H@ [A\A]A^A_] @ @ H9 HcH> 3(8 H7 HH^h 01$l AO HX9 HcH>H ff. Hh Aؿ Hb 01L$H 6 H H H U3 H 6 H { Hh H7 01#BH p H 3 H H d6 H v6 '8H6 HHHh 01#&8Hٿ IHh HR 01a#97 U1HATSH dH%( HE1{D1E7zXøZ E fE fUx"Hu I1It!HUdH+%( u8H [A\]f E9Et @ Ef9Eu1u D UfHHdH%( HE1wHEdH+%( u13 UHSHdH %( H]HHHt 5HC H;Ht pH HEdH+%( uH]1ff. f UHAWMAVAUIATISHH HEHXLpHEdH%( HE1H? HMLEHE ] L1HDžh HuHMH9p LPHMH`4 LHuHEIM,I)LhHEH9E 1LHEH;HuHE I)Mt IHpH`LuI9IFHE 1H;HuHxHxfHxLPc1LLIH)h H 01q HXLL?HEdH+%( HĈ H[A\A]A^A_] Hh [HHHt(s蘬HIu1H}HEt1Hh H 01 HiLH 1HHUh 01 }ff. f UHAWAVIAUATISHXHUH dH %( H]LHuHUHE HMLEHE H1HuLmHuH9r( HEHMIHUHH)HUH9MsVI~HUL3HItLHHMIHgh LE12PH 1 HEZYHUdH+%( He[A\A]A^A_]IFHHt' HI?u.HUHE HEHh H 011 1LH 1HHh 01 1`f. UHATSHdL$%( LeA<Ht71HMDHHstE Hu } 1HUdH+%( u H[A\]Q UHH0H}؉ЉʈUԈEdH%( HE1HUHEHѺ HHEHEHUdH+%( tf. U H5 HAWAVAUATSH(dL4%( LuI H5h AF LxHAHc3IHt{ H5Ch A "f D <$ CD/IED9}/IHcA<_uA|_uظ. CD/IED9|fMcMAE E1HEdH+%( H(L[A\A]A^A_] EDLBDlITDBDX@HU HUE: H5Zh E %fI^S UIHAWIAVAUATISHHMdL,%( LmEH M9j EE 1L50 E D@ D9t4A$B<3wIcL>fHcÃAf D IM9uHcL LHUdH+%( HH[A\A]A^A_]f HcI<A E? AM HcÃALA6 Em D HcLAa VM D At A AD$Hh A A @ At A uHcH 1LLU)DEHcDDELU D Av HcE A) AN HcA A(x AAEA[ AtA G u EA &f D M uAI<1HcH h LUH )H] DEHcRDELUËEHtcH DEHELULeA܋]DmAf. IcHU1D)LHcAAsDDELeLUDmEE [ CMf. 1Nf uHcH( 1LLUA )DEHcvDELUu1H* LUDE)HcIDELUËEHH DEHELULeA܋]DmAff. fIcHU1D)LHcAAsDDELeE LUDmOuHcH 1LLU)DEHcLUDEuH 1LUDE)HcnA$LUDEHcL蚼f. UHAWAVAUATSHdH%( HE1H A) IIH LoLt@L HH IA tAH1DE1LL)Ht\HEdH+%( uYHH[A\A]A^A_] 1A DHLrHt HHP Hf D H蘫1菻f. D UHAWAVAUIATISHHHdL<%( L}A~H;LHI蝳1uIE D8 L3IE HUdH+%( uH[A\A]A^A_]ff. UHATSH dH%( HE1HtHHw 1HUdH+%( H [A\]ÐLdA<$:uA|$:uA|$hufHIT$)EH9[ AT$JЀ ) JwWHcDIT$H9( AT$JЀ v J[WHcDIT$H9 AT$JЀ O J$WHcDIT$H9 AT$JЀ ( JWHcDIT$H9 AT$JЀ JWHcDIT$H9L AT$JЀ JWHcDIT$ H9 AT$ JЀ JHWHcDIT$ H9 AT$ JЀ JWHcDIT$ H9 AT$ JЀ e JWHcDIT$ H9p AT$ JЀ > JWHcDIT$ H99 AT$ JЀ JlWHcDIT$H9 AT$JЀ J5WHcDIT$H9 AT$JЀ JWHcDIT$H9 AT$JЀ JWHcDIT$H9saAT$JЀ JWHcDIT$H9s.AD$PЀ \ PaWHDf D UEUUUUUUUUUUUUUUߍD L9 <.tO <${Cug{$uaH <: A<9HCHH {.u{.ux 0HcD H5j# Hl4 H5S# HP H5<# H4 H5%# H H5# H H5" H H5" Hĭ H5" H設td H5" H萭tL H5" Hxt4 H5" H`t H5" HH!H0 H </g 0HcD0HcD0HcD0HcD0HcD-0HcDT0HcD{0HcD0HcD0HcD0HcD0HcD>0HcDe0HcD0HD 貳f UHAVAUATSH dH%( HE1HtyIH}H}詾MlM9sPL :t/} $ . {.HES HPHU -HH]L9rLeA$ f. HEdH+%( I H [A\A]A^]À_ ~]A<w]HEHH]HPHUL9S D {C {$ HEHH] ,HHE A<vHBh H 101 LeA$ Jf. I9 {:tyHEHH]HP _HU] D H5j HluXHEHH] @HHE$ @ HPH :HU@:H] @ {$}f H5 Hu HEHH] *HHE H5 Hȩu HEHH] &HHE H5 H蔩u HEHH] <HHEL H5r H`u HEHH] >HHELuH]ȹ( H; LHAtH]诰) H LHu H LHu' H LHu[ H LHu] H LHg~ H LHHHh Hg 101 Le UHAWAVAUATSH H $ H HEHIHHHDEHdH4%( HuDH H IG LIH h HDž 8 H/ IH H5 Hp AFI~0 H HHXH IH Et H5j Hih H01 HHHH8L0H@H LHH H@(H`HH HLH苍HH5, HHp LpM: ( HH L;Hp H߾( Aƃ KDk{ SLKLc =DTiJ =JiTD ƅxAIIH54h D6y B I y H8 HP ? DH(H(~6H苓HpIH 1HL HH E1IHH%LH襜Dff. HpH HXH H~ x D+CtHSAD+CHHSà A HXH9h HpHHs U HXA4 n E x CȉCCȉCHCHHCHC HHC HC(HHC(HC0HHC0HC8HHC8D;Ak Et H8HHDcH( HH FHH fnKHt f~ fn fnCHfoپX fbHH@f֝Dx IH s8HxH1LAT Lc HL0"HHHLHHAXAY H0H8HHHH % HH 0 ȋHL LAE fA}H{(IIE II}H{0Gd'HfEeEtHMcHLAE,LEL)I}HIH`Iu0I}AU(AM@AED IE8 tI<$G L1 LLLHHƅVH@HID$HHC(HHH%Aą`AUH0LH L@1LLHHHpH% D DHZh ~'Hh EHH H81%HDDHH Hǀ HHHHHHXHEdH+%( 8 HeD[A\A]A^A_]f L5h HH 1 I>|H01 HHHH8L0H@H LHH H@(H`HH H#h I>HHc 1 LH LHDDvHH3 H ^H H H5 A H$ H5 H H5l HE1Apf D Hh H H H81 LD9H o H HH9u @ xluH H9@;uHh HR 101HוHp軿Hp_A @ f. H' HpDHHaHpHDžp D AuXCDhLIHW Hs(LH ~CHCHC H)LE1Zf. H8HHDcH( HH ҌHHs fnKHt f~謌fn fnCHHC(foHs8Hfbп H`HK HHHcȋCHf֕HH)HHC0HH@@ HH fHIH H@HLL HHHǺ ATI1HHHHPHHHHxHHpHHXHHhA[XHh ~ HHh L H H81םHHHdH 1A \ Ad H LAV HDLhDHHPxPXpP H D牅辙 H tH H tH L0HHHLSC H0H8HIHIH A A HH E0 PA AE L`fEUD0HHIE fAEIuEtDHcHIM0HMHE}(I)AU,IuIHH`A}@IuAED IE8 tI4$V H1 LHLHHHƅVH@LHID$HHHO Aąu;AUH0L蜓H L@1HLLH赇L] HȆHHHXHh"f Hh DH 101$ DcI LH Hs LHЄHHCHf H Lc I9LBLMHHHXH Lh Ax HCHHCHCHHCHC HHC fAnf D fAnf D x :SʉSSʉSHSHHSHS HHS HS(HHS(HS0HHS03 x HCHHCHCHHHsHHC 1ff. HHHHHPPʉPPʉPH9r @ 1L1H1f. fy H{HDž H8) )twHH fF f HP HX Hv5o` )p q ! H{HI|$f D HHHH|H֔H. H tH V H t,H t"H譿fHDž )L،A= D 1L1H1ffy H{HDž H8) )twHH fF f HP HX Hv5o` )p q !z HHI|$f D x xdf D Hh H 101E1 HEP1W RH H . H+HDž @ H fHDž ) f HHfn} HHfn HHfnfn HHfnfnL HkHDž 151HWh EH ] H 019LH1H] IHh 01bH Hh LH 1H01/+Hh H\ 101 A|Hh H 101辙D9f UHAWAVAUATMcS HXEHuHULmEHE HMLMHEdL<%( L}L}(a 1Ҿ 3 HH H{H I H > fPH߃HHH@ fP>ʠ Hޕ HfHnH@ flH@fInH@0 fl@ HH HEH}H HML5t L`H@ H@ HLpH H< foD H@8 H@M HuI$ HHHEI) HH HEH' H@ H}H@ L(LxLp;H HÔ HMHH@ H@8 HHHHHt HEH HuKT= LpH@ H}H@ HHpH HM H@ H@8 HHULHPHIH HH2 H i LpLH@ H@ HH@r <H Hԓ H@ HH@8 HL%i Hi IHk HH H+ H Di H@ LH@ HH@0 HPH HM IH}H@ H@8 H҃P(2 H@LcHULHUHI HuHxHzHHHS HEH}H H@ H@ L(LxLpHT H H@ HH@8 HRHEHE HMH HEHEHE3IH) 21LHHu LT~HuLLE~1H5vj Lt ḼH HM_vj Yvj GNU H}HBvj H;vj HA HA HHA$ LqHN H foo H@ $ H@8 HHU@H M HuHA H= 1ʝAE1HLHEdH+%( HXD[A\A]A^A_] @ H=K 1z H=G 1bH= 1RH= DuH= 11Ad D H= 1 HE10H6H= 1 H= ԜfH= ĜfH=m 贜fH=" A螜ԒH= 1膜 UfHAWE1AVIAUIATISH H dH %( H]ȉHE HDžp HE )`)E)E~ @ M)4$I|$AnMdD9u1A A @ K6MIDILxHHEHt2HP H}LuL9sH~i H{i THEH HELuHPH}A L9r8 D MK6IDHIxHHEHt!HPH}LuL9sHEHHELuHPH}A L9r9f D MK6IDHIwHHEHt$HPH}LuL9s HEHHEHUL`A LhHpHcHIFL9 ff. @ MK?IDHI*wH`HHt@HpHCLhL9sHe H Ha HD H`HXH`LhHC HpA L9rJff. MK?IDHIvH`HHt>HpHC LhL9sHi H i D H`HX H`LhHCHpA L9r<MK?IDHIvH`HHSHt-HpLhL9s H`HXHPH`LhHpA L9r=MK?IDHIuH`HHSHt-HpLhL9s H`HXHPH`HpLhA D) BD7 fEL9rGff. MK?IDHIuH`HHSHt-HpLhL9s H`HXHPH`LhHpA L9r=MK?IDHItH`HHSHt-HpLhL9s H`HXHPH`LhHpA L9r=MK?IDHI:tH`HHt-HpHCLhL9s H`HXH`LhHCHpA L9r=MK?IDHIsH`HHt1HpHCLhL9sH H`HXH`H HuHSHpHDžH HDž@ HLhA Dž< HDž HDž0 HLXLIff. @ H0 HXH0H H(HHHPSH(H t7HPHH H( H(H LX<LApAA)LAA wM(L@MM)I D<D9 D)LcL9rGff. HHIDHHqH`HHQHt7HpHhH9sH`HHHPH`f. EDAIL E1@t ȀA AHhHpH9rBf D HHIDHHZqH`HHQHt-HpHhH9sD4H`HHHPH`EaHXLhLpp<H0H9@2 H@LH)HL9rJff. MK?IDHIpH`HHQHt7HpLhL9sH`HHHPH`f. LhAHpȀHDEL9rJff. fMKD- IDHIpH`HHQHt-HpLhL9sD4H`HHHPH`HpHXLhLpH H@LL9rIf MK?IDHIoH`HHQH6 HpLhL9sH`LhLpHHHPH`HPHHH HHH(迓HXH9H(H HDHXLLHHA L9rBf D MK?IDHInH`HHSHt-HpLhL9s H`HXHPH`LhHpA L9r>MKD- IDHI9nH`HHSHt-HpLhL9s H`HXHPH`LhHpA L9r=MKD- IDHImH`HHt-HpHCLhL9s H`HXH`LhHpL9rGA @ MKD- IDHIYmH`HHV HpLhL9sD)LeC B7HEH}HPL9rBff. @ MK$HDHIlHHEHPHt!H}LeL9sHUHBHHELeH} L9r: MK$HDHIlHHEHPHt!H}LeL9sHUHBHHELeH} L9r: MK$HDHI*lHHEHPHt!H}LeL9sHUHBHHELeH} L9r: MK$HDHIkHHEHPHt!H}LeL9sHUHBHHELeH} L9r: MK$HDHIjkHHEHPHt!H}LeL9sHUHBHHELeH} L9r: MK$HDHI kHHEHPHt!H}LeL9s HUHBHHELeH} L9r: MK$HDHIjHHEHPHt!H}LeL9s HUHBHHELeH} L9r: MK$HDHIJjHHt HEHELeHPL9s HEH IH HH HpH e~ LH@ H@ HH`HXHP賻H Hs L H@8 fHHLIH[ H H HUH@ LH@ HHUHXHP9Hl H H@8 fLHHIH HH HUH@ LH@ HHUHXHPƺH H H@8 fLH HH 1HpƤH}轤H}贤HEdH+%( ] H [A\A]A^A_]f D IE1@HXH@H6H99^ HXHHP@LL9rEf MK?IDHIgH`HHQHt-HpLhL9s H`HHHPH`HPH(H0 H0H(Lxff. DHhEHpȀIDEH9rHff. HHIDHH gH`HHQHt-HpHhH9sD,H`HHHPH`MqLhHpL9rJff. MK6IDHIfH`HHt-HpHALhL9sH`HHH`HPH0H0LhLxHpIL9rEf MK6IDHIeH`HHt:HpILhL9sHPHLBdH`LH`LhHAHpL9rFf. MK6IDHIzeH`HHQHt-HpLhL9s H`HHHPH`LhHpL9rC MK6IDHI eH`HHQHt-HpLhL9s H`HHHPH`LhHpL9rC MK6IDHIdH`HHQHt-HpLhL9s H`HHHPH`LhHHpL9rKff. @ MK6IDHIdH`HHQHt-HpLhL9sH`HHHPH`L DHhEHpȀIDEH9rHff. HHIDHHcH`HHQHt-HpHhH9sD,H`HHHPH`MqHPLhLpH0 Mi OL I A L9raL@Aff. fHHIDHHbH`HHQH HpHhH9sL@DD H`HHHPH`<LhL@Lp$LhHpHSqL9LhLpH= 1\wD{ H=x 12HpH= 1H= 1 @ UHH H}dH%( HE1HtHHGHt?H8 t9 H=]j HEu0H\j HxH@H\j HEdH+%( u5 HH~h HWr 101H\j H@H zff. UHHdH%( HE1H=U\j uHEdH+%( uþ H=>\j i|4z @ UHAVIAUATISHH @h dL,%( LmIH3uTHCH8 t Hh LH 101HCL01LkHUdH+%( uKH[A\A]A^] D H ih LH3螽tH h LH3舽¸ubyf UHATSHH zh dL$%( LeIH3Bu&HCH HUdH+%( uGH[A\] H ѥh LH3tH kh LH3Htxf. f UHAWAVAUIATI SLH( dL4%( LuI5HtHxH5 H}ADžt.E1HEdH+%( , H( D[A\A]A^A_] L)LHsIH H1HH5X t,1HH5Q LtLgofI] Hj C M}H1HLsLH{H SH= H fC1+AW 1fCfCHyAG LHfCI}IMLA4gA wff. @ UHAWIHAVAUE1ATS H8HUH H dH%( HUȉHEGhH}EHbpf_progI_ fAGDщUHL4LdMAIcEM H H)I| 1HL@ IAM9uA^ LuH}UMt{ HMLtLrL0XIHt- HcL| H)I< 1Hc/HEdH+%( u7H8[A\A]A^A_] D u}u@ LO@ufL 4Y uf UHAWAVAUATSH(dH%( HE1? OftYfu+1HUdH+%( H([A\A]A^A_] Hh Hbm 01<f. He{Aąx mIH> H= 2 D IHL L(HHb Eu"E1L]Dk'f. DHI=H HuLUfAnIfHnHz HUfbfEIHt~EHUHx Lf@YLHը^LcQLcLc4 Hh EH Hk 01 D Hih H Hfk 01qsLic @ UHAWAVAUATSHHHh dL,%( LmI8 AMftMfu'HEdH+%( H1[A\A]A^A_] Hh Hk 01fL MtEm LDŻHtL8AGxtE1fI H` J4ynHHtaH@ fAnfAnIfbƀ L fր 耖E;wxr. D Hh LH0.f IE;wxrr UHAWAVAUATS1H HHH`dH%( HE1yc E HMt(HEdH+%( HĨ [A\A]A^A_]Ðz IH =IH HELE1HPHEH0L8ff. HPTÅ }w\ HHH( H Hu H@H@\ hIH H= 8 I$ H@HpP A\$xA;$ = A;\$|2 A$ A$ A$ 9 HHEfAn$ H6 H}H0f~xiUfnxIfHnHz Hhfbfօx蚽HtU~xHhHx LHxf@THxH@kHx ff. 1HhIFIHxLMIff. I C LJ4I B1HIt$HxDAT$HpIH I$ HUfAD$AW 1fAD$HfAD$LeqH}LLfA\$H`L9hLH8LMÌ~c LEw^H}WE \e} HE Hh DEH Hf 011 HIh H@ IFHE HxfAD$5Ń fIF AAW HxAv1A HAF ID$IF4pfA^ EHH L H@Hg[ H`LLE1H}Hh H M Hd 01=\bdHΙh fInLuH6H0Hx8Hp HHDHH( H`)EHE~ L\f D H8xc L\1U Lp\Hh\ 1ۋ8Iă>H H HD衦H IHh IHqd 01(A$à ۃHh fA~H Hc 01L[H}T\b 8H Hd 1IHDh 01H/h H H,d 01kLC[\b!H+[Hh H 8 Hc 01(\MbjHZf&LZH}S UI H HH dH%( HE1H}HDžx HH2e HLE@HpHpHEE@E {HUdH+%( u5j D UHAWAVAUATSH8 dL,%( LmIEuhE9 uE9ult%HEdH+%( He[A\A]A^A_] HMexI]pIA HDž A AM1H L L=dEtrHLE1I @ DLIHHH/AD$DMHLKAHPHb 1cXZE9uHR D HLH!p Hx L聑LHf D HL1LLLvA$HL AMH MPHa 1cY^LMhf. U IHAWAVAUATASHHHH( dH%( HE1Dž HHH t/HEdH+%( H( L[A\A]A^A_] LDLAŅ; DD1L5Di Dž LA Mff. Hc0LHHI9J LcHIqI99 HcpII!݅7 A9 M DEx IB H5HHH sDH zIH HpHX1 HI H DK EDAE McExIJAHHHI HHHtMcFMcNExIFIEyQDE HH! D MtDEx IB f D IB EB< IB fLDLL=@i HA L- ÙHLA* LHELIIcFybAI A LDHHtIcxHH9 tHh LH^ 101IcFxHH9 tHph L1AHP I 01諾A kLA AB} @ 8ĞH HHh 01UIBf L8}H HHh 01HScIff. @ UHHHWdH%( HEHtHc Ti tHc Li h tHc Di 4 tHc <i tHc 4i tHc ,i @t Hc $i yht Hc i y@t Hc i yHEdH+%( HH H)Lf D HH H)THPfHH H)THP HH H)THPO HH H)THP HH H)THP HH H)THP HH H)THP HH H)THPKaf UHHHWdH%( HEHtHc di tHc \i h tHc Ti 4 tHc Li tHc Di tHc <i @t Hc 4i yht Hc 0i y@t Hc,i yHEdH+%( HH HLf D HH HTHPfHH HTHP HH HTHPO HH HTHP HH HTHP HH HTHP HH HTHP HH HTHPK_fUHAWAVAUATSH H $ H8dL$%( LeIH=ذ HDž ܗH Hk@HHH LL-· LL`HH HL=87 LL1`HHt[ H1MLƆ1HHuȻ HNHEdH+%( u$H8 [A\A]A^A_] @ 1 @ 1^ff. @ UHAVAUATSH H $ HdH %( HMHHtPI1LL5- HIL Ht*L1L L LYt͉HUdH+%( uH [A\A]A^]^ UHAUATSHdH%( HE1H t2HA1HE I/LHġu0HU1HHUdH+%( | H[A\A]]f H=K 贕HtNLmH1 LL H, 苤H}Ѕ ?/> QyLH5b: L" H5Y L H5 : L H5 : Lݠ H5 LƠ H59 L诠 A<$s A|$h A|$ L-ͅh L-h L HH}L IL H+ 1ksH}L1Ҹdf D L-1h 1E9 L-h s @ L-Ih cL-h WL-h KH5 L譟tiH58 L蚟tbH52 L臟t`H58 LtuYL-9h H5 H=6U L1HIH}L-h L-h [L-<h H=T L1H}ff. f UHHdH%( HE10|H57 HHUdH+%( uZf. f. f. f. f. @ U1ɉHSH(dH %( H]HHHHu܉}܉U MHFHuH{ FHuH{ FC HEdH+%( uH]Yf UHAUATLmSHLH8dL$%( LeIHu謑utM1ɸ HHAAAAAAA Av$ % Af D AAHLLHR1H ˀ$ HAqHXi YHt IcD 1HUdH+%( u2He[A\A]] A A% EAAzXff. UHATSH0dH<%( H}迀 :HHteLeHuLru̅ukAAHLᾀ HR1H $ HApZYHtIcD HEdH+%( u}HeH[A\]f1ɸ HHAAAAAAAt Al % A\f D A A% EAA7|Wff. UHAWAVIAUATS1HXdL,%( LmI @ Hx- oHuLE1 fAHx- oHuA E1tLe LL\ E1LHM LDLAeEuXDeD+eMc E - L:L)L9% @ H9~h LHP 101| HUdH+%( uUHX[A\A]A^A_]f H}h LH 1014fA D L(alUf. @ UH50 H=S HAWAVAUATSH8dH%( HE1HE HE HE uH HHELmHELeL5S fHٺ LL轝H~`L} LLMuI H5 `gHtHUHH5 1u N YMM D Mf(fTb f.OO w f.zf/GO s ff.zt5H}DHObEHEdH+%( u*H8[A\A]A^A_]HM|h HVO 101蓮lTH-|h HO 101sO f UHHdH%( HE11H H HEdH+%( uHT UHSH86j dH%( HE1=6j t#HEdH+%( H]f. H]Hu6j H詋H5T HeHt}}v_1ɸ HH @@u@t<ffH*H*YfH*^ 6j Sf D ;5j ;f D f,Rf. UH5( HATSHL'dH %( H]HLϖuHDzh C C HC(H5 L詖uC C ht4H;H5 腖tQHEdH+%( ubH[A\]f { tH5E6 Ht'Hp{h H H|h H HQ~h H Qf. UL*K HHFdH<%( H}HׅuLԙ HEdH+%( uHH ( 1IyQ @ UL HHFdH<%( H}HׅuLd HEdH+%( uHH= ( 1x4Q @ ULjJ HH~dH<%( H}HtL HEdH+%( uHH ( 1xP D UHHdH%( HE1HEdH+%( uPff. UHAVIH5 AUATISHdL,%( LmI2Äu%HEdH+%( uDH[A\A]A^] H LLΙHx LLIE 踙AEOff. f UHAVIH5 AUATISHdL,%( LmI[2Äu%HEdH+%( uDH[A\A]A^] H LL.H8 LLIE AE]Off. f UHAWAVAUIATISHdL4%( LuI`t, HEdH+%( utH[A\A]A^A_] H5 L1tL= LLLvHuH LL^LLLIMAFxNff. @ UHHdH%( HE1HEdH+%( u~KNff. UHAWAVAUIATISHdL4%( LuI`~t, HEdH+%( utH[A\A]A^A_] H5 Lo0tL= LLLfHuH LLNLLLI=AFxMff. @ UHATISHdH %( H]HH5 Ho_HtB~+h He fHnflA$ 1HUdH+%( ucH[A\] H5( H_Ht$~T+h H fHnflA$ 먐H5 H^HuȸL U11HAWAVAUATSHH {/j dL$%( LeIE fEfUE tt, HdHu$ HdH Hsh Hٿ HNG A 01'HEdH+%( / HeD[A\A]A^A_]f H5F H=.j QADž .j Zf D HME1 HH=.j ADžVLcuUD)CuEMhud`p9tHcE;E EHEHxJ3HcL5)h HXLPE1MHHHH= II<$IAHc LH0CuMcHB)h HXILPJt(LmL HxULIUhUHp+U)dD`)AAMcLlHI$Hhc L[UHxDeHpDUHHpHhHHcEIHPED)LxPHcEAUHHVLPE)H PIcDMH1SE)cqH@f. Haqh H 01褣x LmHHL LHXLPORf. 9htHEE+HxHEH[ HxH1pELcuUpED)hE`EdAH UHHdH%( HE1HEdH+%( u Hn*h H U HSH`HH dH%( HE1H!HDžp fEH HDžx HE=OPH 1ҿ* E1AH1a< ǃuEHEdH+%( uGH]H D 1H HtPH H hf>H Gf. UHHdH%( HE1HEdH+%( uɸ JGf. UHHdH%( HE1=*j w*j tHUdH+%( uG @ HtH5 H袃u7*j 1*j f D !*j Ff. UHSHdH %( H]H~Vt H{ HUdH+%( uH]eF D UHAVAUATISHHH dL,%( LmIu0Wt+H qh tH5)J L @ H5= Lt%1HUdH+%( H[A\A]A^] Hi SH{D0HcM9|%ui # S,HHtbHCHcHi LHL/HLwHG n`if D LkZ HcHi -E: D UHAWAVAUATSH H $ H8f E1dL$%( LeILH)L)\H5H LD:t0HEdH+%( H8 D[A\A]A^A_] HHLzVAŅu`HHtT~]E1E1" D AI D9~:HHLHLHBrtAH3BfH 3&C UHAWAVAUATISHLndH %( H]H迲1 LLpLNHS1LHR HL|(LEHCI}(LIT$AE H1fE}D@fAEI$H)fHnID$AMfHnʺ IE flAE ^HKHSLH;8HUdH+%( uH[A\A]A^A_]B UHSH8dH %( H]H` H}z HuH( HUeHEHt5HHUH5W}H}؉\2HEdH+%( u+H]Hjh H= 01D Bff. f UHHdH%( HEH@u HH f HH0f HG8HEdH+%( uA UHHdH%( HEHHW8H t! H H0H H HHEdH+%( uOAff. @ UH5j HSHdH %( H]H'Hq t H5j H H[ HEHUdH+%( uH]@ @ UH5xf HSHdH %( H]H跄¸ tH5Cf H蝄HUdH+%( uH]k@f. UHAWAVAUATSH8H}HudH%( HE1Hu'HUdH+%( H8[A\A]A^A_] D LeHIIfInE1fl)Eff. LIILj ݨL9uF: HHMHHL<E1A} up f 1L6kHH AFI~0H H C襩H H薩I>H ' H HEH]L#HCHL&IHuIň M9fH}Lro1 H}H L9t ff. 1HHL9uf D 1LfjHtHUIň HEL HPHM9|f. HuH}H <f>f D UHAWAVAUATSHHdL$%( LeI裴u7 A+$ HUdH+%( H[A\A]A^A_] Hq L L= LLQHtH5; LkQHtZM$ LLSQHtH5 L?QHtCL= LL(QLLIQMtH-1fH D L q@ =f. @ UHHdH%( HE1HEdH+%( u ɾ ke<f D UH HHdH%( HEH HHDt HEdH+%( u,1f HUdH+%( uH5 H8\<ff. UHATSHdL$%( LeI LÄt#M$ MtH5 LOHt%1HEdH+%( u?H[A\]f H5d LOHuH5 LmOH; UIL HHHGdH4%( HuHHH wHfh LH MLDHt:H H HHDHEdH+%( u:H, L1b @ HEdH+%( uLH L1b: UHAUATSHdH%( HE1. j t&HEdH+%( H[A\A]] HIPtH艃HHtH=*G %+H= I+Mt KA9MtHHtS9PuAD$ yH bh H 6 101F j Q AD$>9ff. f UHAUIATSHHdL$%( LeIDOt C8 uFH Ht :it% D HEdH+%( uUH1[A\A]] @ zbuڀzsu @ tHEdH+%( u HLL1[H5 A\A]]`79f. f. UHAUATS1H dH%( HE1HtSIL f Hù MP L5 L 11Lh"ZYtHEdH+%( u He[A\A]]8UHAWAVAUATSHX dH%( HE1H @E1DL @ HA5 L1E DE_HHL># H1HHH5q 蠊H' D|~H D8XHDpAf!A9=1HUdH+%( HX [A\A]A^A_]f D @ljIE1L@L 1EHH 4 AH^HHH=) H1HHH5G vH& DDQ}HH D I} DxDpCAEpCAuHcH H HcSAH IE D9f D H]h ED1H23 01l DESH]h HZ 101Ǐ D D1H%HD]h H; 101芏c5 UHAWAVAUIATSHdH %( H]H~2H\h H2 1018L5 IHT C H Lj {IH( sE1 @ ID9 H LH d2 JD@1APEAPիLL _ZYANjCEt~ E1f D HJ<IWD9kHVH:$L2$HEdH+%( HeD[A\A]A^A_] D IU I9tEH3ff. ff. f D ɍAIHHH HI9uC E1aAn3ff. UHAWAVAUATSH HGPdL,%( LmIHh8DE zIH 1ff. LuzD9uAHhL=aj @ M H5 Lv H^h HEdH+%( HĈ D[A\A]A^A_] EOA1E~ f. IH<H'UA9_LULZ" 1yf H]h yIH LHXHH LxH55m Lw3IHm HtHsDždHhH]D`Iff. H50 H7E111LH HhLH5A L) HYh 1LH0 01TH @Hj DstHn HcPH0_ HH#ff. ff. HH93 L8MtA;uE:GuIcGAT$I<$H BAD$HAWH4 H Džd IcWL<I$LH5k 11IHAD$D` L=j M AWQ 1fIH<HRA9_LRL d L%Mj HX @ HWh 1LH-/ 01ԉH>6 IcT$I$~;H4ff. fHH9t HHt; uD:BHH9uHWh Hj. 101_f. H>AM2AD$1ۅ~$ff. I$H<HQA9\$LQL LQL dAD$A떋dAHSVh HT- 1A01蓈AD$t7L=j MtDždAO LPL3 yHUh Hh- 1015L=vj M DždA LAPL HUh H 1LhD`01·Hh L=j MDždA YLA&PLg KAD$A@A ~$DždE1LXA`LAOL 1HX ,A uf UHAWAVAUATSHH dH%( HE1H9teIIL5 L I9t=I0Ht1Mt,HE $L AD$ED$AL$P1,'XZLHI9uHEdH+%( uHe[A\A]A^A_]<,ff. UHAUATSHH dH%( HE1H9t3I H NHL9tLL I9uHI9uHEdH+%( u H[A\A]]+f D UHHdH%( HEH H HtBIDHHVXD Ht@R L1AQAPRLIHLH U 薢H HEdH+%( u)ÐHH ; L1R H^XZ+ D UHH dH %( HMHO0u]G8t&HEdH+%( umɺ H=* ГHEdH+%( uGɺ H= 骓f. HEdH+%( uɺ H= zU* D UHH dH %( HMH )H5Xh HLH pH H@H;ps Hx tLLJD(LHMu*fHEdH+%( H2HBH 1LPMtH Ht;z u5HIH;qHy H1LHt1(HL 1H H)x>fH*MxpfI*MxBfI*^^Yy& F @ HfHH H*X D LAfHL H*X @ LAfHL H*Xz( @ UHAWIAVIAUATMSHH(HUH7HMdL,%( LmM HMLHL蝢Hs0L-M>M9trf I H HtBI9 t9LLɏHMHUHLFH{0HM1HU "LLHAM?M9uHEdH+%( u Hs0H( [A\A]A^A_]|n' U; HSHHH dH%( HE1H j t HUdH+%( uPH] H@MH@Ht H5 ~ H߉~ j ts j &f. f UHHdH%( HE1wHGh HH8HUdH+%( u&f UHATSH h HdL$%( LeIH= H{HHt+LkjuCHUdH+%( uH[A\] @ ,&ff. UHAVAUATSHdH%( HE1?%uhL-R h Lw1M IAt<I<$LiuHAD HUdH+%( u"H[A\A]A^] ָ% D UHHdH%( HE1w H HUdH+%( u$HMh H 101H %f. f. UHAUATSHH}HXdL$%( LeI @ f HGenuineIH9Et 1HUdH+%( y HX[A\A]]HneIntel,H9EuH= $H=Z IHH9tMtpH EEDH11 JHD9@ D9 H9u @ [LC]Pf D A$? Ht3p1ff. 9rH H9uff. HH9HH9u Auff. 9rH H9uL[ @uf D H Kh HB# 101O}A$r #f. UHAUATSH dH %( H]Hƅ_ H Hu HEdH+%( ueHĘ [A\A]]L HHA L_L~Aą~_H`LvxUD9f d" @ UHHdH%( HE1HEdH+%( upq+"ff. UHATISHdH %( H]HHtIHHu1軚HU: u6H CSI$ 1HUdH+%( uH[A\] D 1ʸ! UHHHGxdH%( HUHH8H9t@HRhRff. @ H?H9t 9WuHEdH+%( u"n f D HEdH+%( uɸ !ff. f UHHHGxdH%( HUHH8H9t@HRhRff. @ H?H9t 9WuHEdH+%( u"n f D HEdH+%( uɸ ff. f UHATSH dL$%( LeI~*1 D I$ H[HH<BA9$ I$ BHEdH+%( uHL[A\] ff. UHSHHHWhdH %( H]HH9tWR fH H9tH9PuH8 Ht7* Hu8H HEdH+%( u3H]Hf f HHH J f. UHAWMAVLAAUIATIH g SLH8 dH%( HE1kwt HDž 1LLDH _ L=w| HHLLHHH!Ht1HHHH?wY H1HHtIHEdH+%( 7 H8 [A\A]A^A_] v wHƅ 1E1 L DiH@x G H H IcHD1 HH)L^EAMA AA@ tHAHAA Hø tUAMHA@ Ic D1H)H LHDAMAA? AtfIc HGX 1H)LDA @ IcLHlf 1H)LHtDADi?t:u%D1 D 1AH9Dh ML1H L 01rvHp E1E1HLX# UH HATISHMHH5 HdH%( HE1tTE HCh I $IH 01uHEdH+%( HH[A\]f D EtH5U Lj H HH9} AL$ff. HH9t`9JuHr1ɺ@ ff. ff. fHyHHHHHHHHu߃ Hc D f UHAWLcAVI AUIH ATSLHPHMH`Bh H 01dL$%( LeMA0M EtA Y^ A D98 I KI HHHua IU1H H9j LUHc)HIIT HH9C H8 tG @ LM L_M}LJI9T A M9rrL)HI9rgHELLEHMJ4LML]HUrLMHMLEu3L]LHUHuL)HI<HALEHMLMAI9 HuI)HLLEh H L I $IMH M $H@h H Hx 0Q1H rX1ZHUdH+%( ~ He[A\A]A^A_]ÐI IMAƆ vWIvxI~hHMVHM HtH HBH= HCH9s I HH9rff. f1I A D9 Ҹ DA9| D A9}Hc UM^HHx HcEI H@HMI HA af MMI$M 1IuIM $H L L9IMH M $p I9M9 AHEHLLEHMJ4LM"LMHMLEA HuLLHMLELEHMK48HJ< L)IHuI)L @ I!2 HHUM}HM09Ht5I HUHMHHI I)L~I HLH#>h AH ~ 1H6 01\po-ff. fUHAWL=y AVLAUATSH dH %( H]HDž $H/ LA1v=LLDAH 1HntHDž 1LDHH (^ H m Dž u1LLDHl Hm Dž g L=0p 1DHLLHP LSmL H<h H HF M L0L 01n1 LHL1LLtU1LsAD HEdH+%( O H H[A\A]A^A_] # D E1 LLHDž8 HuH8| 1LHO DHIlMc H: 1L)K<.c;f D 1L DHH :\ H̑ k Dž _f D 1tJEʉt= Eʉt+ t u f Ic H 1H)L:A @ uF¹Eʉt@ Eʉt.tq ¹8f1u Ic H 1H)L:A= @ < @ f D t t u롐 @ UfHAWAVAUATSH( HH_hdH%( HE1HHDž0 )) H9 7 L@I ILL HL 1H5 Lu- HDž LJ>1 LHL 1H5Ǐ L4 HDž L >1 LHLt 1H5 L+ HDž L=HH5_ LH1HL 1H5͎ L HDž Lm=1 H1LH3 H5 Dt HDž@ H1LHs H5͎ t Dž HIOhH HH9 I H H9 9HuL8 M LHHIŋJ0% H H8H H\t B H=D 1H1H HzHIĘ \HADŽ$p HvIT$HIL$I$xIT$IcWpIt$HIT$A ID$HHIL$ID$HIt$ID$ЉID$؋IT$ID$HID$H@ID$Ml$Mt.M LLpHH LLIHc I$1HUdH+%( H( [A\A]A^A_] @ HE1LLHDžH {CHHH;HE1LLHDžH ;HHHHE1LLHDžH 'HHH HE1LLHDžH HHHH H f. E1E1 D 1lf Dž 1< HXHHHL>fL12CW UHAWAVIAUATSHH HFLghH dL,%( LmIH(L;I^xE1҈AESA L9 L5 ff. f M?L9 AD$A9GuM Ag9H@LIG 蔆1u @AƇ AG:AƇ AG:IAERH9n xA9|$8 MIM?L9jAESa E E HH9t21ff. ff. P;H H9u A}R A}U h M} LkAƅ L@L1H e HՈ bLMJ> L H ! DLH LLu6MJDLL H H LLt{DA5 D HEdH+%( t H D[A\A]A^A_] A}R A}U H[1h HD 101c @ MJDLH L H , L D LK A}S A}U j A}R AMptIQ Hi 0N 1Ҹ A}lAMpu 1AEl A}S u(A}U u!Hi HHH9HGABx1H@ LHL0HL1H5 LZL L35A}R L M H @p E1 f D H/h H 101aA @ AESM H/h H 101aHE1LL LHDžH )L/LLLHT4A}R L!M#b H(TLukA}Y tA}X t]LdLA I} LwL¸ H AEXEApAB8 u/L2LtcwLtAEe LHLH(SLr A}R 01I} tAr8@HLFIH HHELt AƄ$ H(LrSLg LLrL Hi ʋ HH I#UP H9r HPHH2-h HH 1 1s_of D L1H LL}(LqHLLI AMpIHi LHD L S @ 1AAEpII H LHLxHA}pL R,h LIH9E 1E1ff. @ HtINH9LCH9HBHH9uH,i H~uA}lu 1AElAA1H HI HtlHH HH ] HH8uHHH<uHHH>uHH IHAUp H(L PGI} L @ AB8*H= 1rAL *h Hm 11A3]LMJIMJL d+LuP m ; WHF H 1HIHtpHH D H HH0uHHH8uHHH<uHHH>uHH? HLAMpL )h AI9 H HH ƿ 1L[MLI I H9LH= 1LsALI9 I1LDH LLx[LLM-I L9 LLH=$ 1LfL HE111H` D LZLLME A}R AMpHi 0 @ 1AMpHII LW L( L(LsA}l 1AEl~1Ҹ AA}lAEpO 1AAEl<I} I} A}, I} f. HE111H D LYLLMdE1?H0 HH'h HL 101aY]/ ? E11H58 HLL* HLzMLH= I ƀ H @p HM?LHI LHǾ H;ƀ ' L& L& LdkH AEX L@p I} @I} 5A}, u I} # ; H 11X Hڗi H1E1 HL7Hx%h H 101WHH? D11WAHH 11~WzTL %h AA1LZ H Gn LA3H L5WILL A3H 1L WL L $h ff. UHSH=,i dH %( H]Ht*H i HCHEdH+%( u%H]f. Ki Hi Vf D UHATSHdL$%( LeIH=nv H H5 H={ Hq H HH xHXh~\g fHnH@HXXflfHnH @T fHnHv~&g fHnfl@~g fl@ ~g fl@0fHn'h @@HUdH+%( u6H[A\]f X A$1 A$1 UHHdH%( HE1HEdH+%( uɸ0 f. UHHdH%( HE1HEdH+%( uIff. UHATISHdH %( H]HHtIHHu1sHU: u6H CSI$ 1HUdH+%( uH[A\] D 1ʸ UHAWI AVMAUIHM ATSHcH0HMH!h H k 01dL$%( LeMA0M ASA Y^9 I H[H4ǀ~ u`IM1HH H9) H]Lc)LJHT ff. @ HH9 H8 tFIL` I$IEIM $H h HH H 7j 3P1RX1ZHUdH+%( He[A\A]A^A_]f Ҹ D9| 9}Hc UMW?MHcUHH~ I HRMHMMI HA @ IUI$II!Ht-M $IL* L9IEIM $f D 1HIH h AH "i Hu 01Q UHHHGpdH%( HUHH8H9t@HRhRff. @ H?H9t 9WuHEdH+%( u"~f D HEdH+%( uɸ-ff. f UHHHGpdH%( HUHH8H9t@HRhRff. @ H?H9t 9WuHEdH+%( u"~f D HEdH+%( uɸff. f UHATSH dL$%( LeI~*1 D I$ H[HH<A9$ I$ HEdH+%( uHL[A\] ff. UfHAUATSH8dL,%( LmLohHE )E)EH0 H H0 H IHH8H Hu|mt(t* HUdH+%( H8[A\A]]fEuYH=t 1uE1HMA}HC AD$xC H{HC81HsHK(HS0두1111f D uHM 볐f UHAWIAVAUATSHH(LwhLfdL,%( LmIsA}U ? AuSAHI_pAwxH9 ANE1 H H9tI;HuMR H`9H@ ƀ AERH9V ;J% IHH H9uAER@ LDMADM A}S , H=֍i I AMpDLH E, @ 1AAEpII Hƅ WHF H 1HIHtlHH / ? HH0uHHH8uHHH<uHHH>uHH? HLAMpHh I9 H H 1Hr DMLDMAuRAMp@ MtjHLL@ AuR@tEH5 H u4LcH߉ELAd$9EID$ @ '1HUdH+%( M H([A\A]A^A_] @ Hh Hj 101L I H=i uJDE 1Ҹ AA}lAMpu 1AAEluM H=si HA}S tn H9r HPHtbHh HX 101]KI EA}l 1AElf. MQlE1 @ 1AAMp5HII LH G L 1Ҹ AA}lAEp 1AAElHh H 101`JLH 11IJ5Hh H 101+JHH 11JHh Hv 101If UHATSHdL$%( LeIH=c EH H5 H=n H H HOH HXh~g fHnHHXXflfHnHl@P fHnH~g fHnfl@~g fl@ ~g fl@0fHnh @@HUdH+%( u6H[A\]f L A$1 A$1w UHE1ɹ H5 HAUATLmSMH(dH%( HE1H H}1Z E E H H@(HXH Lc MtyHp(H hHULHuHHt{LHx[LcEЋuILH= m H1OHIHEdH+%( u?H(L[A\A]]11E1 E1 E11E1f D LcEE1:f. UH H5l HSLMLEH(dH%( HE1G H}1 HHtxH@8HtgH Ht[8 t)H= 1NHUdH+%( u@H]f D H}V1HHC8H f D 먐1W UHE1ɹ H5 HHdH%( HE1LEFtAH}1F HHt.HEdH+%( u+H= 1Mf HEdH+%( u1 UHE1ɹ H5 HHdH%( HE1LE5FtAH}1 HHt.HEdH+%( u+H=X 1IMf HEdH+%( u1 UHE1ɹ H5C HHdH%( HE1LEEtAH}1 HHt.HEdH+%( u+H= 1Lf HEdH+%( u1x UHE1ɹ H5 HSLEHdH%( HE1D H}1aHH HxH? t7 fuWH@(H H8Ht(+H{HHC(H06H{ fu Hh HUdH+%( u6H] @ HEdH+%( u H]Hǟ e 1w UHE1ɹ H5 HATSLeMHdH%( HE1C H}1\E HtpH@(HxHtkH_ 1Ht Hp( cLHHUHH=Dh H1JHIHEdH+%( u HL[A\] @ E1 11ff. f UH=Ti HSHdH4%( Hu uHNh H5Q HHHEdH+%( u HH] f. D UHHcH5Y HHHdH%( HU1Ҁ8 HEHff. @ Hx u1Ҁ8 HEHQ f Hx u1Ҁ8 HEHQf Hx u1Ҁ8 HEHQf Hx u1Ҁ8 HEHQf HHx u80AAx0A@H1x HEHq8fHz u1: HDHQ(HEdH+%( u UHAWAVAUATSH(=i dL<%( L}ItL9=wi Hhi LIH =7i H h E1 D H{LH0 HMIHuH=i HEIHEL-i i Hi L=i Hi i HUdH+%( ukH([A\A]A^A_] D H=i H)PHji LHEHE KvHH)h S @ 1qff. UHAWIAVIAULmATSHxHxOHhdH%( HE1HDžp ff. LpHV IM&Ict$ HHhH HK3tfIcD$ H kV AT$HE HHEt^1ېI$L<H} tHxLLAׅu6HA;\$rHh u HpAFHpH9E1 HUdH+%( u,Hx[A\A]A^A_]fAD$HE Hud0 UHAWAVAUATSH HhHXHPLHdH%( HE1G2 IHm HOU E1H`a HXd$ HP HHHxLHP= AGII9 LL`HhHI Hcs L1tHDcHpHcC HE LE1HEHEHxAxC4HpHx HcË<H}HDsE9~AGII9V f Dcf. 1HUdH+%( HĘ [A\A]A^A_]HS 1LmH`IH`HhIM7Icv H0tIIcV H`AFM&HE HHUx#LAHA<H} tAFEuAGHH9r"HP 4HHHPLL=tff. f UHAWAVAUATSH(HudH%( HE1GtiIE1L5R E1LH}HI $Hcs L/tCIAD$II9rHEdH+%( uH(L[A\A]A^A_] @ E1ff. UHAWAVAUATSH HXHPHHdH%( HUȋWHDž@ % H R E1E1 HXL@ILIcA AyMHH` E1ff. ILJcH8 HEHh D Hx u8 LHEHp D Hx u8 LHEHx D Hx u8 LHEHu Hx u8 LHEHu Hx u8 LHEHu Hx u8 LHEHu Hx u8 LHEHu Hx u8 LHEHu Hx u8 LHEHu Hx ufAnf fn fdf`fffefafEHt&HHHXH`HPЅu7A~IA9OHXPH@H@H91HUdH+%( uHĘ [A\A]A^A_]C UHAVAUATSHdH %( H]H(HtsIHtF@E1L%~O uX AFII9sCLHHIVHcr L,tIFHUdH+%( uH[A\A]A^] D 1 UHAVAUATSHdH %( H]HxHtsIHtF@(E1L%N uX AF(II9sCLHHIV Hcr Li+tIF HUdH+%( uH[A\A]A^] D 1 UHAUATIH=t SHH 6h dL,%( LmI @ H{0H0Ht L uH{LuH{HEdH+%( uHH[A\A]]Yf UHAUATIH=Nt SHH h dL,%( LmI @ H{0H0Ht L uH{LuH{ HEdH+%( uHH[A\A]]f UHAUIATSHH h dL$%( LeIHX H0H{ t1LLH荼tHUdH+%( u H[A\A]]Jf. UHAUIATSHHh dL$%( LeIHX H0H{ tLLHtHUdH+%( u H[A\A]]ff. UHH=r HSHdH %( H]1 Htg HEHUdH+%( uH]nff. UHHdH%( HE1HEdH+%( uHH=g H1A ff. UHHdH%( HE1HEdH+%( uHHH=g sff. U HAWA AVAUL-,` ATE1SH K H(H}dH<%( H}ȿR $ E~E9|<C ' HIc| AHuHA AAJ t.yEfE9~1HUdH+%( u&H([A\A]A^A_] McH ,` JcDHf. D UHHdH%( HEHcG HUdH+%( uff. f UH Ji HSHHLEHH/[ HdH%( HE1HE t(H} HHCHUdH+%( u H]ø$ @ UHHHdH%( HE1l/HUdH+%( uH @ UHATISHHdH %( H]H%/HH9~6I|$HEdH+%( u3HH= 1[A\] HEdH+%( u H1[A\]Yf UHHdH%( HEHcG H9~fHWHH9t3HF'ff. ff. D HHH9tHuHEdH+%( u*HrH=$ 1 @ HEdH+%( u1 UHSHdH %( H]HH*HEdH+%( uHCHH]H@ a UH Gi HSHHHELMLEH0dH4%( HuHPHX 1EEEZYt0Uu}2HHCHUdH+%( uH] @ UHHHdH%( HE1HUdH+%( uH @ UHATISHHdH %( H]HuHH9~6I|$HEdH+%( u3HH=> 1[A\]K HEdH+%( u H1[A\]f UHSHdH %( H]HHHEdH+%( uHCHH]H@ UH HSHD dH%( HE1D HEAH1Ax1H}H}H4HEdH+%( uHH] @ CH f UHV HSH}HdH%( HE1x3H}rH}HHEdH+%( uHH]f D Hf UH4 HSHEHL dH %( HMH H1~x2H}H}H%HEdH+%( uHH] D 3Hf UH HSHEH dH %( HM苏 RH L D H1H x4H}3H}HwHEdH+%( uHH] HIf UHAWAVAUATSHHHGdL$%( LeIxt.HEdH+%( HLH[A\A]A^A_]rGfL>H <LsII0 H LQIHtH@L AU,A}(HIE8tcAר ItDL DL+4Ie8H?HUdH+%( H[A\A]A^A_] HcI4>HHIE8ut 襲 Bf A~HHH= I0 I4>HAIE8A AU,AU(f D L0%vf D UHHdH%( HE1HEdH+%( u 1H=y {&f D UH57 HH H dL%( LEL H tH5~ HEdH+%( uH=4 1 UH5% HH D dH%( HEH D tH5C HH= P1蜲HUdH+%( u6f D UHHdH%( HE1HEdH+%( u" H 1H= 4ff. @ U IHH HATSHH`L`LhMH dH%( HE1HDžX Dž Dž Dž Dž Dž HLHTHDžx Dž H |>i Dž Dž$ Dž( Dž, Dž0 Dž4 Dž8 Dž< Dž@ DžD DžH DžL DžP DžT PHEPHEPHEPHEPHPPHLPHHPHDPH@PH<PH8PH4PH0PH,PH(PH$PH PH PHPHPHPH PHPHEPHxPHXPHpP1_H HXHtHp ~ Hp H{LDžd Ѝ Ѝ Ћ Ћ Ћ @ Ћ$ Ћ( Ћ0 Ћ4 Ћ8 Ћ< Ћ@ ЋD @ ЋH ЋL ЋP Ћ, ЋU ЋTE(1HUdH+%( uHe[A\]f D ff. UH ;i HATSHHHELMLEH dH4%( HuHE HM HE HE E PHEP16ZYtHMLcHtHIHuHtHvUCHL HʈCH"x.HGg tHUdH+%( u"He[A\]f D Hg H81 UHSHdH %( H]HHHEdH+%( uHCHH]H@ UHSHHHMHUH5s H(dH%( HE1HE HE t6HEH{HPHEHp1HUdH+%( uH]f D $ @ UHATSHUHHH5 HdH%( HE1 tXHuLctHuC HL牆 s H= 1HUdH+%( uH[A\] D 1 UH T8i HSHHLEHH/K HdH%( HE1EtHuH{譹ƅx'H=8 1IHUdH+%( u H] @ Hg H81 UHSHdH %( H]HH:HEdH+%( uHCHH]H@ UH t7i HAWAVLMLEAUATIHHSH2J H(dH%( HE1E AD$@Uąy HcI$ HHH)HHff. H H9@ ;SuH# HIH Pv P fA~H H}g H<IH AVL LLqI|$LDBIHt}IEHp IULLa t;IE xHIE uLUnUHg H5M H81c3IHEdH+%( ugH(L[A\A]A^A_]IE y9 L-g AE tAE f. E1 IHIE uLܦ D UHAWAVAUATSHdL$%( LeI1D,IAL$P~1L=N D HA9\$P~dID$`LE1E1H5K <j j >IXZMtjLLIuIxHIuLH A9\$PHEdH+%( uSHeL[A\A]A^A_] x HIt"HEdH+%( u He[A\A]A^A_]L蹥bf UHHHdH%( HE1<x(H1g tHUdH+%( u Hg H81 UH 3i HSHHLMHLEHF HdH%( HE1E E BtNuH{x.Hg tHUdH+%( u#H]f Hg H8Q1G UHH 2i HHF HH dH%( HE1LMLEHE HE 1t HuH}? H= w HcxnHUdH+%( u D HL D UH=44i HAWAVAUATSHdH4%( HuȾ 荦HH L=jg L%sWi LL=Li L=>i L=SBi L=Ei L=%Ii L=~Pi L=WTi L=pXi H=Gi w H=Ri {c H=Ni gO H=Ki S; H=Ci ?' H=@i + H=<i L-3i L= 5i L L56i L=7i L H=\8i L=9i H=A:i L=r;i HZi T3i tI3i LH5M H6i t6i LH5K HUi tUi LH5H HKFi t@Fi H9Fi H5G HMi tyMi HrMi H5H Hs=Qi t2Qi L%G H$Qi HLISIi tHIi HAIi H5G H"Pi tPi HPi LH Bi tAi HAi H5G H>i tw>i Hp>i H5F H:i t:i H:i H5E Ht6i ti6i Hb6i H5"m HcM8i tB8i H;8i H5;E H<HdIHt\L-g L= @ M}IMt;Ic} rIHt*HLLlI$xHI$uL{7HtHg H5fA H80HEdH+%( uHH[A\A]A^A_]Zf. UHHdH%( HE1HEdH+%( u1 ff. f UHHdH%( HE1HEdH+%( u1ݽff. f UHHdH%( HE1HEdH+%( u1蝽ff. f UHHdH%( HE1HEdH+%( u1]ff. f UHHdH%( HE1HEdH+%( u ff. @ UHHdH%( HE1HEdH+%( uɸڼf. UHHdH%( HE1HEdH+%( u蟼ff. @ UHHdH%( HE1HEdH+%( u_ff. @ UHHdH%( HE1HEdH+%( uɸf. UHHdH%( HE1HEdH+%( u1ݻff. f UHHdH%( HE1HEdH+%( u1蝻ff. f UHHdH%( HE1HEdH+%( u_ff. @ UHHdH%( HE1HEdH+%( uɸf. UHHdH%( HE1HEdH+%( u1ݺff. f UHHdH%( HE1HEdH+%( u1蝺ff. f UHHdH%( HE1HEdH+%( u1]ff. f UHHdH%( HE1HEdH+%( uɸf. H7h 1 HH HH r~@8|5H H LLNLVL^Hv LLOLWL_H sԃ DHHH H LFLNLVL^HvLGLOLWL_Hs҃ H)H)׃r$LLNLTL\LLOLTL\ÐrLLLLLLf. rDDDDff. rtLFL DGD ÐI@HLÐI@HHAAupHHt9f HHHGHGHGHG HG(HG0HG8H@u у8tf D HHut ʈHuLHvHI M)LL)r HH %d [ , %s%d ] /sys /proc /sys/kernel/debug /debug /sys/kernel/tracing /sys/kernel/debug/tracing /tracing /trace /sys/fs/bpf sysfs procfs debugfs tracefs hugetlbfs bpf r /proc/mounts %*s %4096s %99s %*s %*d %*d fs/fs.c !fs->path fs->path PERF_%s_ENVIRONMENT %d %s/%s %s/sys/%s fs__init_once %s/%s tracing/ %s/events/%s events * sdt_ Error: File %s/events/%s not found. Hint: SDT event cannot be directly recorded on. Please first use 'perf probe %s:%s' before recording it. Error: File %s/events/%s not found. Hint: Perhaps this kernel misses some CONFIG_ setting to enable this feature?. Error: Unable to find debugfs/tracefs Hint: Was your kernel compiled with debugfs/tracefs support? Hint: Is the debugfs/tracefs filesystem mounted? Hint: Try 'sudo mount -t debugfs nodev /sys/kernel/debug' %s Error: No permissions to read %s/events/%s Hint: Try 'sudo mount -o remount,mode=755 %s' r /proc/mounts cgroup , devices/system/cpu/online devices/system/cpu/cpu%d/cpufreq/cpuinfo_max_freq INTERNAL ERROR: strerror_r(%d, [buf], %zd)=%d /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/include/linux/refcount.h !(new == (~0U)) !(!refcount_inc_not_zero(r)) !(new > val) cpu_map refcnt unbalanced libperf: Number of online CPUs (%d) differs from the number configured (%d) the CPU map will only cover the first %d CPUs. r /sys/devices/system/cpu/online cpumap.c j <= nr_cpus %u%c Perf can support %d CPUs. Consider raising MAX_NR_CPUS libperf: Unexpected characters at end of cpu list ('%s'), using online CPUs. k <= tmp_len refcount_inc refcount_inc_not_zero refcount_sub_and_test cpu_map__trim_new perf_cpu_map__merge /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/include/linux/refcount.h !(new == (~0U)) !(!refcount_inc_not_zero(r)) !(new > val) thread map refcnt unbalanced refcount_inc refcount_inc_not_zero refcount_sub_and_test Clibperf: idx %d: mmapping fd %d libperf: idx %d: set output fd %d -> %d libperf: %s: nr cpu values (may include -1) %d nr threads %d libperf: Miscounted nr_mmaps %d vs %d libperf: %s: nr cpu values %d nr threads %d mmap_per_thread mmap_per_cpu /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/include/linux/refcount.h !(new == (~0U)) !(!refcount_inc_not_zero(r)) !(new > val) mmap.c !(map->base && refcount_read(&map->refcnt) == 0) libperf: %s: buf=%p, start=%lx libperf: Finished reading overwrite ring buffer: rewind libperf: Finished reading overwrite ring buffer: get start libperf: move evt_head: %lx failed to keep up with mmap data. (warn only once) refcount_inc refcount_inc_not_zero perf_mmap__put refcount_sub_and_test overwrite_rb_find_range lib.c !((size_t)(buf - buf_start) != n) ion PIX Fatal: PWD Too long path: %.*s PREFIX %s%s/%s /usr/local/bin:/usr/bin:/bin LINES COLUMNS Out of memory, realloc failed perf- %s%s/ available %s in '%s' FRSX LESS /usr/bin/less /usr/bin/pager PAGER cat -c -%c --%s [=<n>] [<n>] <n> [=<%s>] [<%s>] <%s> [=...] [...] ... %*s%s %*s(not built-in because %s) Error: %s Usage: %s or: %s Error: switch `%c' %s Error: option `no-%s' %s Error: option `%s' %s is being ignored because %s is not available because %s takes no value isn't available is not usable cannot be used with %s requires a value Warning: switch `%c' %s Warning: option `no-%s' %s Warning: option `%s' %s expects a numerical value vasprintf failed no- %s%s %s [<options>] { help-all list-opts list-cmds --%s %sunknown option `%s' %sunknown switch `%c' exec %s: cd to %s failed (%s) Error: waitpid failed (%s) BUG: signal out of range: %d Usage: %14s: %s # Running %s/%s benchmark... default # Running '%s/%s' benchmark: --help Unknown collection: '%s' default|simple repeat sched Scheduler and IPC benchmarks System call benchmarks Memory access benchmarks numa futex Futex stressing benchmarks epoll Epoll stressing benchmarks internals Perf-internals benchmarks Breakpoint benchmarks uprobe uprobe benchmarks All benchmarks trace_printk empty_ret trace_printk_ret enable Run all breakpoint benchmarks kallsyms-parse Benchmark kallsyms parsing inject-build-id Benchmark build-id injection evlist-open-close pmu-scan Run all futex benchmarks hash wake-parallel lock-pi memcpy find_bit basic getpgid Benchmark for fork(2) calls execve Benchmark for execve(2) calls Run all syscall benchmarks messaging seccomp-notify Run all scheduler benchmarks Benchmark for NUMA workloads Run all NUMA benchmarks pipe() socketpair() CLIENT: ready write SERVER: read SENDER: write main:malloc() fork() pthread_attr_init: pthread_attr_setstacksize pthread_create failed Reading for readyfds Writing to start them # %d groups == %d %s run Total time %14s: %lu.%03lu [sec] %lu.%03lu Unknown format:%d Specify number of groups nr_loops cgroup.threads cgroup.procs tasks Cannot enter to cgroup: %s perf_event Hint: try to run as root memory allocation failure %14s: %lu.%03lu [sec] %14lf usecs/op %14d ops/sec Specify number of loops threaded SEND,RECV unexpected syscall: %d waitpid(%d) failed unexpected exit code: %d # Executed %lu system calls sync-mode getppid() # Executed %'d %s calls %'14d ops/sec getpgid() fork failed waitpid failed /bin/true execve /bin/true failed execve() perf bench syscall <options> # function '%s' (%s) # Copying %s bytes ... %14lf cycles/byte %14lf bytes/sec %14lfd KB/sec %14lf MB/sec %14lf GB/sec %lf Invalid size:%s Unknown function: %s Available functions: %s ... %s x86-64-unrolled x86-64-stosq x86-64-movsq 1MB shared private mlockall pthread_attr_setaffinity_np pthread_create pthread_join calloc Specify amount of threads Specify runtime (in seconds) silent nwakes Must be perfectly divisible nwakers futex_wait futex_wait_requeue_pi PI cpu_map__new nrequeue broadcast Requeue all threads at once multi Use multiple futexes epoll_create epoll_ctl epoll_wait lineal single (EPOLLONESHOT semantics) (nonblocking) CPU affinity Using %s queue model Nesting level(s): %d getrlimit setrlimit eventfd main thread: toggling done nfds noaffinity Disables CPU affinity randomize verbose Verbose mode multiq nonblocking nested oneshot Use EPOLLONESHOT semantics edge epoll_ct data Session creation failed. Thread map creation failed. Run single threaded benchmark mt Run multi-threaded benchmark min-threads max-threads single-iterations multi-iterations outer-iterations inner-iterations Adding DSO: %s Iteration #%d inject -b --buildid-all Build-id injection failed [%d] injecting: %s Child %d exited with %d Memory allocation failed /usr/lib/ Collected %d DSOs nr-mmaps nr-samples strbuf_init: %s strbuf_add: %s strbuf_addch: %s Number of cpus: %d Number of threads: %d Number of iterations: %d Started iteration %d evlist__mmap: %s Iteration %d took: %luus nr-events all-cpus user to profile per-thread use per-thread mmaps dummy %14lf usecs/op/cpu Unknown format: %d ioctl(PERF_EVENT_IOC_DISABLE) ioctl(PERF_EVENT_IOC_ENABLE) passive Specify amount of breakpoints Specify amount of parallelism Cannot find PMU %s core usleep(1000) usec %14s: %'lu %ss %s%'ld to baseline %s%'ld to previous %'.3f %ss/op %'.3f %ss/op to baseline %'.3f %ss/op to previous perf bench uprobe <options> got NODE list: {%s} got CPU list: {%s} thread %d/%d # %5.1f%% [%.1f mins] %2d/%-2d [%2d/%-2d] l:%3d-%-3d (%3d) [%4.1f%%] {%d-%d} (%6.1fs converged) (%6.1fs de-converged) main, g->p.nr_tasks: %d # binding tasks to CPUs: # token: {%s}, end: {%s} CPUs: %d_%d-%d#%dx%d %2d/%d # binding tasks to NODEs: NODEs: %d-%d #%d ,%2d ### # # process %2d: PID %d process %d NUMA-convergence-latency %-30s %15.3f, %-15s %s secs latency to NUMA-converge %14.3f %s runtime-max/thread runtime-min/thread runtime-avg/thread secs average thread-runtime spread-runtime/thread %, data/thread GB, GB data processed, per thread data-total GB data processed, total runtime/byte/thread nsecs, nsecs/byte/thread runtime thread-speed GB/sec, GB/sec/thread speed total-speed GB/sec total speed process%d:thread%d GB/sec thread-system-time system CPU time/thread thread-user-time user CPU time/thread RAM-bw-local, -p -t -P 1024 -C -M -s -zZq --thp --no-data_rand_walk RAM-bw-local-NOTHP, RAM-bw-remote, RAM-bw-local-2x, 0,2 RAM-bw-remote-2x, 1x2 RAM-bw-cross, 0,8 1,0 1x3-convergence, -zZ0qcm 1x4-convergence, 1x6-convergence, 1020 2x3-convergence, 3x3-convergence, 4x4-convergence, 4x4-convergence-NOTHP, 4x6-convergence, 4x8-convergence, 8x4-convergence, 8x4-convergence-NOTHP, 3x1-convergence, 4x1-convergence, 8x1-convergence, 16x1-convergence, 32x1-convergence, 128 2x1-bw-process, -zZ0q 3x1-bw-process, 4x1-bw-process, 8x1-bw-process, 512 8x1-bw-process-NOTHP, 16x1-bw-process, 1x4-bw-thread, -T 1x8-bw-thread, 1x16-bw-thread, 1x32-bw-thread, 2x3-bw-process, 4x4-bw-process, 4x6-bw-process, 4x8-bw-process, 4x8-bw-process-NOTHP, 3x3-bw-process, 5x5-bw-process, 2x16-bw-process, 1x32-bw-process, 2048 numa02-bw, numa02-bw-NOTHP, numa01-bw-thread, 192 numa01-bw-thread-NOTHP, perf bench numa <options> nr_proc number of processes nr_threads number of threads per process mb_global global memory (MBs) mb_proc process memory (MBs) mb_proc_locked mb_thread thread memory (MBs) nr_secs usleep data_reads data_writes data_backwards data_zero_memset init_zero bzero the initial allocations init_random init_cpu0 perturb_secs show_details Show details Run all tests in the suite show_convergence measure_convergence measure convergence latency quiet serialize-startup serialize thread startup cpu[,cpu2,...cpuN] memnodes node[,node2,...nodeN] annotate.objdump --- start --- test child forked, pid %d ---- end(%d) ---- %3d.%1d: %-*s: %3d: %-*s: Ok Skip (%s) [33m Skip FAILED! [31m %3d: %-*s: %3d.%1d: %s: %3d: %s: ---- end ---- tests to skip dont-fork Do not fork for testcase Run the tests in parallel sequential workload workload to run for testing dso to test %3d: %s %3d:%1d: %s No workload found: %s Skip (user override) ./tools/perf/tests/shell ./tests/shell %s/tests/shell -v /proc/%d/fd/%d .sh wrong type tests/parse-events.c FAILED %s:%d %s wrong config wrong number of entries wrong exclude_user wrong exclude_kernel wrong exclude_hv wrong precise_ip wrong period wrong callgraph wrong time wrong config1 wrong config2 wrong config3 wrong bp_type wrong bp_len wrong sample_type wrong sample_period wrong type term wrong type val wrong val r0xead wrong pinned wrong exclusive check_parse_fake %s failed %s/bus/event_source/devices/ ... SKIP Failed allocation can't access trace events %s/event=1/,%s/event=1/ unexpected PMU type PMU missing event wrong exclude guest wrong exclude host wrong group name wrong leader wrong sample_read branch-misses wrong number of groups group1 wrong core.nr_members wrong group_idx krava wrong name cpu/config=2/u breakpoint1 breakpoint2 intel_pt event not parsed as raw type PMU type expected once No PMU found for type Raw PMU not matched can't open pmu event dir: %s %s:u,%s/event=%s/u cachepmu wrong name setting wrong complex name parsing intel_pt//u numpmu rawpmu Can't open events dir header_event header_page Can't get sys path Can't open sys dir wrong events count running test %d '%s' cache-misses wrong exclude idle mem:0:w:up mem:0:r:hp mem:0:x:k mem:0:u l1d mem:0:rw:kp Test event parsing permissions pmu_events pmu_events2 alias no aliases in sysfs pmu_events_alias2 Parsing of aliased events terms2 software/r1a/ software/r0x1a/ cpu/L1-dcache-load-miss/ cpu/L1-dcache-load-miss/kp cpu/instructions/ cpu/instructions/h cpu/instructions/G cpu/instructions/H cpu/instructions/uDp cpu/instructions/I cpu/instructions/kIG cpu/cycles/u cpu/cycles/k cpu/instructions/uep cpu/cycles,name=name/ cpu/cycles,name=l1d/ syscalls:sys_enter_openat syscalls:* r1a 1:1 cycles/period=100000,config2/ L1-dcache-load-miss mem:0 mem:0:x mem:0:r mem:0:w syscalls:sys_enter_openat:k syscalls:*:u r1a:kp 1:1:hp instructions:h faults:u L1-dcache-load-miss:kp instructions:G instructions:H mem:0:rw {instructions:k,cycles:upp} {cycles:u,instructions:kp}:p *:* {cycles,cache-misses:G}:H {cycles,cache-misses:H}:G {cycles:G,cache-misses:H}:u {cycles:G,cache-misses:H}:uG instructions:uDp mem:0/1 mem:0/2:w mem:0/4:rw:u instructions:I instructions:kIG task-clock:P,cycles instructions/name=insn/ r1234/name=rawpmu/ 4:0x6530160/name=numpmu/ cycles//u cycles:k instructions:uep cycles/name=name/ cycles/name=l1d/ mem:0/name=breakpoint/ mem:0:x/name=breakpoint/ mem:0:r/name=breakpoint/ mem:0:w/name=breakpoint/ mem:0/name=breakpoint/u mem:0:x/name=breakpoint/k mem:0:r/name=breakpoint/hp mem:0:w/name=breakpoint/up mem:0:rw/name=breakpoint/ mem:0:rw/name=breakpoint/kp mem:0/1/name=breakpoint/ mem:0/2:w/name=breakpoint/ mem:0/4:rw/name=breakpoint/u 9p:9p_client_req %s/self/fd fd path: %s failed to open fd directory tests/dso-data.c mkstemp failed No test file Failed to add dso Failed to access to dso Wrong size Wrong data ENOMEM file limit %ld, new %d failed to set file limit failed to get dso file failed to get dso failed to add dso failed to create dsos failed to get fd failed to read dso dsos[0] is not open failed to close dsos[0] nr start %ld, nr stop %ld failed leaking files failed to open extra fd failed to close dso_0 failed to close dso_1 DSO data tests dso_data dso_data_cache dso_data_reopen %s/event-%d-%llu-%d w+ [event-%d-%llu-%d] group_fd=%d cpu=%d pid=%d flags=%lu size=%u config=%llu sample_period=%llu read_format=%llu disabled=%d inherit=%d pinned=%d exclusive=%d exclude_user=%d exclude_kernel=%d exclude_hv=%d exclude_idle=%d mmap=%d comm=%d freq=%d inherit_stat=%d enable_on_exec=%d task=%d watermark=%d precise_ip=%d mmap_data=%d sample_id_all=%d exclude_host=%d exclude_guest=%d exclude_callchain_kernel=%d exclude_callchain_user=%d mmap2=%d comm_exec=%d context_switch=%d write_backward=%d namespaces=%d use_clockid=%d wakeup_events=%u bp_type=%u config1=%llu config2=%llu branch_sample_type=%llu sample_regs_user=%llu sample_stack_user=%u Skip test on hybrid systems ./tests ./perf %s/tests /usr/bin %s/perf PERF_TEST_ATTR test attr FAILED Setup struct perf_event_attr : WARN: *%lx-%lx %lx kallsyms_offsets _from_arm .long_branch. machine__load_kallsyms failed __kernel_syscall_via_break __kernel_syscall_via_epc __kernel_sigtramp __gp WARN: Maps only in kallsyms: WARN: Maps only in vmlinux: .plt_branch. _from_thumb _veneer __crc_ __efistub_ __kvm_nvhe_$ __kvm_nvhe_.L __AArch64ADRPThunk_ __ARMV5PILongThunk_ __ARMV7PILongThunk_ __ThumbV7PILongThunk_ __LA25Thunk_ __microLA25Thunk_ kallsyms_relative_base kallsyms_num_syms kallsyms_names kallsyms_markers kallsyms_token_table kallsyms_token_index _SDA_BASE_ _SDA2_BASE_ vmlinux_matches_kallsyms thread_map__new syscalls /etc/passwd evsel__read_on_cpu Detect openat syscall event openat_syscall_event perf_cpu_map__new Ignoring CPU %d %s: evlist__new %s: evsel__newtp %s: evlist__create_maps perf_evlist__open: %s Can't parse sample, err = %d %s: no events! syscall_openat_tp_fields failed to create threads tests/mmap-basic.c failed to create evsel failed to open evsel: %s failed to mmap evsel: %s loop = %u, count = %llu getsid getppid sys_enter_%s evsel__new(%s) unexpected %s event mmap interface tests basic_mmap mmap_user_read_instr mmap_user_read_cycles Couldn't run the workload! sched_getaffinity sched_setaffinity: %s Couldn't parse sample %lu %d %s with unexpected pid/tid %s with different pid/tid! %s with unexpected comm! coreutils libc [vdso] No PERF_RECORD_EXIT event! PERF_RECORD Failed to alloc evlist Roundtrip evsel->name %s: "%s" field not found! evsel__newtp failed with %ld prev_comm prev_prio prev_state next_comm next_pid next_prio sched_wakeup target_cpu perf_evsel__tp_sched_test fdarray__new() failed! before %s: after before growing array after 3rd add after 4th add fdarray__add fdarray__filter pmuname Exact match tests/pmu.c FAILED %s:%d %s (%d != %d) longertoken Longer token Shorter token pmuname_10 pmuname_2 Diff suffix_ pmuname_1 Sub suffix_ Same suffix_ No suffix_ pmuname_ Underscore_ pmuna Substring_ pmuname_ab23 Diff suffix hex_ pmuname_ab Sub suffix hex_ Same suffix hex_ No suffix hex_ Underscore hex_ Substring hex_ pmuname10 pmuname2 Diff suffix pmuname1 Sub suffix Same suffix No suffix Underscore Substring pmunameab23 Diff suffix hex pmunameab Sub suffix hex Same suffix hex No suffix hex Underscore hex Substring hex pmuname_a3 Diff suffix 2 hex_ pmuname_a Sub suffix 2 hex_ Same suffix 2 hex_ No suffix 2 hex_ Underscore 2 hex_ Substring 2 hex_ pmuname_5 pmu* Glob 1 nomatch* Glob 2 pmuname_[12345] Seq 1 pmuname_[67890] Seq 2 pmuname_? ? 1 pmuname_1? ? 2 i915 cpum_cf cpum_ce cpum_d0 Strips uncore_cha suffix Strips mrvl_ddr_pmu suffix Sysfs not mounted Error opening "%s" krava01 config:0-1,62-63 krava02 config:10-17 krava03 config:5 krava11 config1:0,2,4,6,8,20-28 krava12 config1:63 krava13 config1:45-47 krava21 krava22 config2:8,18,48,58 krava23 config2:28-29,38 /tmp/perf-pmu-test-XXXXXX mkdtemp failed rm -fr %s perf-pmu-test perf-pmu-test/type 9999 perf-pmu-test/format perf-pmu-test/format/%s Failed to write to file "%s" perf-pmu-test/events Test PMU creation failed Failure to "%s" Term parsing failed perf_pmu__config_terms failed Unexpected config value %llx perf-pmu-test/test-event/ Sysfs PMU tests pmu_format Parsing with PMU event pmu_event_names PMU event names name_len PMU name combining name_cmp PMU name comparison pmu_match PMU cmdline match mrvl_ddr_pmu_87e1b0000000 mrvl_ddr_pmu_87e1b1000000 mrvl_ddr_pmu_87e1b2000000 mrvl_ddr_pmu_87e1b3000000 mrvl_ddr_pmu_87e1b4000000 mrvl_ddr_pmu_87e1b5000000 mrvl_ddr_pmu_87e1b6000000 mrvl_ddr_pmu_87e1b7000000 mrvl_ddr_pmu_87e1b8000000 mrvl_ddr_pmu_87e1b9000000 mrvl_ddr_pmu_87e1ba000000 mrvl_ddr_pmu_87e1bb000000 mrvl_ddr_pmu_87e1bc000000 mrvl_ddr_pmu_87e1bd000000 mrvl_ddr_pmu_87e1be000000 mrvl_ddr_pmu_87e1bf000000 uncore_cha_0 uncore_cha_1 uncore_cha_2 uncore_cha_3 uncore_cha_4 uncore_cha_5 uncore_cha_6 uncore_cha_7 uncore_cha_8 uncore_cha_9 uncore_cha_10 uncore_cha_11 uncore_cha_12 uncore_cha_13 uncore_cha_14 uncore_cha_15 uncore_cha_16 uncore_cha_17 uncore_cha_18 uncore_cha_19 uncore_cha_20 uncore_cha_21 uncore_cha_22 uncore_cha_23 uncore_cha_24 uncore_cha_25 uncore_cha_26 uncore_cha_27 uncore_cha_28 uncore_cha_29 uncore_cha_30 uncore_cha_31 Found metric '%s' duration_time Didn't find parsed metric %s Result %f Broken metric %s pmu_events__test_soc_sys testcpu testarch parsing '%s': '%s' expr__ctx_new failed expr__find_ids failed check_parse_fake failed expr__parse failed for %s tma_clears_resteers tma_mispredicts_resteers skipping testing core PMU %s bp_l1_btb_correct default_core testing event table %s: pass PMU JSON event tests pmu_event_table PMU event table sanity PMU event map aliases some metrics failed parsing_fake parsing_threshold hisi_sccl1_ddrc2 uncore_cbox_0 hisi_sccl3_l3c7 uncore_imc_free_running_0 uncore_imc_0 uncore_sys_ddr_pmu0 v8 uncore_sys_ccn_pmu4 0x01 uncore_sys_cmn_pmu0 43401 43602 43c03 43a01 sys_cmn_pmu.hnf_cache_miss (434|436|43c|43a).* eventid=1,type=5 uncore uncore_sys_cmn_pmu eventid=0x1,type=0x5 sys_ccn_pmu.read_cycles config=0x2c ccn read-cycles event uncore_sys_ccn_pmu sys_ddr_pmu.write_cycles event=0x2b ddr write-cycles event uncore_sys_ddr_pmu uncore_imc.cache_hits event=0x34 Total cache hits uncore_imc event=0x12 Total cache misses uncore_imc_free_running uncore_hisi_l3c.rd_hit_cpipe event=7 Total read hits hisi_sccl,l3c event=0x7 event-two-hyph event=0xc0 UNC_CBO_TWO_HYPH uncore_cbox event-hyphen event=0xe0 UNC_CBO_HYPHEN event=0x22,umask=0x81 uncore_hisi_ddrc.flux_wcmd event=2 DDRC write commands hisi_sccl,ddrc event=0x2 l3_cache_rd event=0x40 L3 cache access, read eist_trans event=0x3a,period=200000 other event=0x3a,period=0x30d40 dispatch_blocked.any segment_reg_loads.any bp_l2_btb_correct event=0x8b L2 BTB Correction event=0x8a L1 BTB Correction ----- %s -------- bash [kernel] schedule page_fault sys_perf_event_open realloc main xmalloc xfree run_command cmd_record Can't find the matched entry cpu-clock task-clock Match and link multiple hists hists_link No memory tests/hists_filter.c Normal histogram Invalid nr samples Invalid nr hist entries Invalid total period Unmatched nr samples Unmatched nr hist entries Unmatched total period Histogram for thread filter Histogram for dso filter Histogram for symbol filter Histogram for socket filters Histogram for all filters Filter hist entries hists_filter tests/hists_output.c cpu,pid,comm,dso,sym dso,pid [fields = %s, sort = %s] Invalid hist entry overhead,cpu dso,sym,comm,overhead,dso Sort output of hist entries hists_output tests/hists_cumulate.c callchains expected Invalid hist entry #%zd Cumulate child hist entries hists_cumulate 2> /dev/null '/usr/bin/python3' python usage test: "%s" 'import perf' in python python_use failed opening event %llx failed to read: %d bp_signal count %lld, overflow %d Breakpoint overflow sampling bp_signal_overflow wp %d created failed to create wp tests/bp_account.c failed to modify wp wp 0 modified to bp failed to create max wp wp max created Breakpoint accounting bp_accounting failed opening event %x WO watchpoint tests/wp.c RW watchpoint Modify watchpoint missing kernel support wp_ro Read Only Watchpoint missing hardware support wp_wo Write Only Watchpoint wp_rw Read / Write Watchpoint wp_modify Modify Watchpoint evlist__new_dummy Couldn't open the evlist: %s received %d EXIT records task_exit evsel__new Error during parse sample sw_clock_freq mmap failed tid = %d, map = %p failed to notify tests/mmap-thread-lookup.c failed to destroy threads failed to synthesize maps looking for map %p failed, couldn't find map map %p, addr %lx failed with sythesizing all Lookup mmap thread mmap_thread_lookup tests/thread-maps-share.c wrong refcnt maps don't match failed to find other leader Share thread maps thread_maps_share thread_map__new failed! perf_cpu_map__new failed! evlist__new failed! cpu-clock:u cycles:u Failed to parse event %s sched:sched_switch No sched_switch Failed to create event %s cycles event already at front dummy:u Tracking event not tracking Not supported evlist__mmap failed! spin_sleep failed! Test COMM 1 PR_SET_NAME failed! Test COMM 2 Test COMM 3 Test COMM 4 malloc failed evlist__parse_sample failed event with no time Missing sched_switch events cycles event Duplicate comm event comm event: %s nr: %d Unexpected comm event %u events recorded Missing comm events Missing cycles events Track with sched_switch switch_tracking threads failed! cpus failed! evlist failed! keep_tracking qsort failed map__load failed perf_cpu_map__new failed evlist__new failed Parsing event '%s' parse_events failed evlist__mmap failed pipe failed thread__find_map failed File is: %s On file address is: %#lx dso__data_read_offset failed kcore map tested already - skipping decompression failed Objdump command is: %s 2>/dev/null popen failed getline failed Reducing len to %zu objdump failed for kcore read_via_objdump failed buf1 (dso): 0x%02x buf2 (objdump): no vmlinux no kcore no access no kernel obj Object code reading code_reading Samples differ at 'id' Samples differ at 'ip' Samples differ at 'pid' Samples differ at 'tid' Samples differ at 'time' Samples differ at 'addr' Samples differ at 'cpu' Samples differ at 'period' Samples differ at 'raw_size' Samples differ at 'raw_data' Samples differ at 'weight' Samples differ at 'data_src' Samples differ at 'cgroup' perf_event__synthesize_sample evsel__parse_sample read_format %#lx parse_no_sample_id_all kmod_path__parse tests/kmod-path.c wrong kmod wrong comp [x_x] /xxxx/xxxx/x-x.ko is_kernel_module false [x] /xxxx/xxxx/x.ko.gz /xxxx/xxxx/x.gz [test_module] [test.module] [vdso32] [vdsox32] [vsyscall] [kernel.kallsyms] failed to set process name tests/thread-map.c failed to alloc map wrong nr wrong pid wrong comm failed to synthesize map %d,%d failed to allocate map string failed to allocate thread_map failed to remove thread thread_map count != 1 thread_map count != 0 failed to not remove thread Remove thread map thread_map_remove Synthesize thread map thread_map_synthesize Thread map can't get templ file tests/topology.c templ file: %s can't get session can't get evlist failed to write header failed to get system cpumap s390 aarch64 CPU %d, core %d, socket %d Cpu map - Node ID is set Cpu map - Thread IDX is set Core map - Node ID is set Core map - Thread IDX is set Die map - Node ID is set Die map - Core is set Die map - CPU is set Die map - Thread IDX is set Socket map - Node ID is set Socket map - Die ID is set Socket map - Core is set Socket map - CPU is set Node map - Socket is set Node map - Die ID is set Node map - Core is set Node map - CPU is set Node map - Thread IDX is set ppc64le Session topology session_topology tests/mem.c unexpected %s N/AL4 hit N/ARemote L4 hit N/APMEM miss N/ARemote PMEM miss FwdRemote RAM miss Test data source output 1-2 tests/cpumap.c not equal 4,5,7 4,2,1 6-8 6-9 1-8 6-8,15 6-9,15 1-8,12-20 failed to merge map: bad nr 1-2,4-5,7 0,2-20 1,256 1-256 wrong cpu wrong any_cpu wrong start_cpu wrong end_cpu wrong long_size failed to convert map 1,5 2-5 1,3-6,8-10,24,35-37 1-10,12-20,22-30,32-40 CPU map cpu_map_synthesize Synthesize cpu map cpu_map_print Print cpu map cpu_map_merge Merge cpu map cpu_map_intersect Intersect cpu map cpu_map_equal Equal cpu map tests/stat.c wrong thread wrong id wrong run wrong ena wrong aggr_mode wrong scale wrong interval Synthesize stat round synthesize_stat_round Synthesize stat synthesize_stat Synthesize stat config synthesize_stat_config tests/event_update.c failed to get evlist failed to allocate ids KRAVA 1,2,3 wrong cpus wrong unit Synthesize attr update event_update OK failed to create event list SKIP : not enough rights failed to attach tests/event-times.c %s: ena %lu, run %lu failed to detach Event times event_times ids__new tests/expr.c foo ids__insert bar baz EVENT1 get_cpuid Intel ids_union expr__ctx_new FOO 1+1 parse test failed unexpected value FOO+BAR (BAR/2)%2 1 - -4 (FOO-1)*2 + (BAR/2)%2 - -4 1-1 | 1 1-1 & 1 min(1,2) + 1 max(1,2) + 1 1+1 if 3*4 else 0 1.1 + 2.1 .1 + 2. d_ratio(1, 2) d_ratio(2.5, 0) 1.1 < 2.2 2.2 > 1.1 1.1 < 1.1 2.2 > 2.2 2.2 < 1.1 1.1 > 2.2 1.1e10 < 1.1e100 1.1e2 > 1.1e-2 FOO/0 division by zero BAR/ missing operand FOO + BAR + BAZ + BOZO find ids BAZ EVENT1,param=3@ EVENT2,param=3@ dash\-event1 - dash\-event2 dash-event1 dash-event2 EVENT1 if #smt_on else EVENT2 0 & EVENT1 > 0 EVENT1 > 0 & 0 1 & EVENT1 > 0 EVENT1 > 0 & 1 1 | EVENT1 > 0 EVENT1 > 0 | 1 0 | EVENT1 > 0 EVENT1 > 0 | 0 #num_cpus #num_cpus >= #num_cpus_online #num_cpus >= #num_cores #num_cores >= #num_dies #num_dies >= #num_packages #system_tsc_freq #system_tsc_freq > 0 #system_tsc_freq == 0 source_count(EVENT1) source count strcmp_cpuid_str(0x0) \- \, \= strcmp_cpuid_str(%s) has_event(cycles) Simple expression parser expr p:%d Unexpected record of type %d Read backward ring buffer backward_ring_buffer Probe SDT events sdt_event failed: test %u is_printable_array bitmap: %s tests/bitmap.c Print bitmap bitmap_print Setting failed: %d (%p) perf hooks perf_hooks 1B 10K 20M 30G 0B n %lu, str '%s', buf '%s' unit_number__scnprintf unit_number__scnprint failed: alloc bitmap tests/mem2node.c failed: mem2node__init failed: mem2node__node mem2node 5-7,9 Expected %d maps, got %d Expected: Got: bpf_prog_1 bpf_prog_2 bpf_prog_3 kcore1 kcore3 failed to create maps tests/maps.c failed to create map failed to insert map kcore2 failed to merge map merge check failed maps__merge_in parse_nsec_time("%s") failed to keep 0 failed to skip %lu failed to keep %lu 0.000000001 1.000000001 123456.123456 18446744073.709551615 perf_time__parse_str("%s") Error %d Failed. Expected %lu to %lu 1234567.123456789, 0,1234567.123456789 10%/1 10%/1,10%/2 10%/1,10%/3,10%/10 time utils time_utils Writing jit code to: %s Test jit_write_elf short write Failed to open '%s' Failed to allocate memory tests/api-io.c %s:%d: %d != %d %s:%d: %lld != %lld 12345678abcdef90 a b c d 1 2 3 12345678ABCDEF90;a;b 0x1x2x x1x 12345678;1;2 Test api io api_io Ljava/lang/Object;<init>()V void java.lang.Object<init>() FAILED: %s: %s != %s Demangle Java demangle_java (null) camlStdlib__array__map_154 Stdlib.array.map_154 Stdlib.bytes.++_2205 Demangle OCaml demangle_ocaml Test libpfm4 support pfm_events not compiled in pfm_group test groups of --pfm-events inst_retired.any cpu_clk_unhalted.thread IPC failed to compute metric tests/parse-metric.c idq_uops_not_delivered.core cpu_clk_unhalted.ref_xclk Frontend_Bound_SMT IPC failed l2_rqsts.demand_data_rd_hit l2_rqsts.pf_hit l2_rqsts.rfo_hit l2_rqsts.all_demand_data_rd l2_rqsts.pf_miss l2_rqsts.rfo_miss DCache_L2_Hits frontend failed DCache_L2_Misses DCache_L2 failed failed to find recursion l1d.replacement L1D_Cache_Fill_BW recursion fail failed l1d-loads-misses l1i-loads-misses cache_miss_cycles Memory bandwidth cache_miss_cycles failed group IPC failed, wrong ratio test metric group Parse and process metrics parse_metric PE file support pe_file_parsing evlist is empty tests/expand-cgroup.c event count doesn't match event name doesn't match: cgroup name doesn't match: failed to expand event group libpfm was not enabled failed to parse '%s' metric Event expansion for cgroups expand_cgroup_events evlist__open() failed Convert perf time to TSC tsc_is_supported TSC support perf_time_to_tsc Perf time to TSC >/dev/null 2>&1 Command: %s Failed with return value %d dlfilter-test-api-v%d.so dlfilter to test v%d C API /tmp/dlfilter-test-%u-prog.c /tmp/dlfilter-test-%u-prog %s/dlfilters/%s dlfilters not found Checking for gcc gcc --version gcc not found dlfilters path: %s Failed to write test C file cat %s ; echo gcc -g -o %s %s objdump -x -dS %s Failed to write sample %s script -i %s -D dlfilter C API dlfilter FAILED sigaction(): %s FAILED pthread_create(): %s misfired signal? tests/sigtrap.c enable failed pthread_join() failed disable failed unexpected sigtraps unexpected si_addr Sigtrap sigtrap Pass Fail amd_l3 amd_df hv_24x7 Event groups event_groups Overlapping symbols: Zero-length symbol: machine__new_host() failed! Testing %s Failed to create map! dso__load() failed! DSO has no symbols! Symbols symbols 123 empty string tests/util.c no match 124 replace 1 ef abcabc efbcefbc replace 2 longlong longlongbclonglongbc replace long util got: %s 0x%lx, expecting %s failed to get unwind sample unwind failed Could not get machine Failed to create kernel maps Could not init machine Could not get thread test__arch_unwind_sample test_dwarf_unwind__thread test_dwarf_unwind__compare bsearch test_dwarf_unwind__krava_3 test_dwarf_unwind__krava_2 test_dwarf_unwind__krava_1 test__dwarf_unwind Test dwarf unwind noploop thloop failed to get stack map x86 hybrid x86 hybrid event parsing not hybrid AMD IBS via core pmu amd_ibs_via_core_pmu x86 Sample parsing x86_sample_parsing x86 bp modify bp_modify Intel PT intel_pt_pkt_decoder Intel PT packet decoder intel_pt_hybrid_compat Samples differ at 'ins_lat' arch/x86/tests/hybrid.c wrong hybrid type missing pmu cpu_ unexpected pmu cpu_core/cycles/ {cpu-clock,cpu_core/cycles/} {cpu_core/cycles/,cpu-clock} cpu_core/r1a/ cpu_core/LLC-loads/ %02x intel_pt_pkt_desc failed! eax = 0x%08x ebx = 0x%08x ecx = 0x%08x edx = 0x%08x Decoding failed! Decoding: Packet context changed! Decoded ok: not CPU %d not found CPU %d OK failed to PTRACE_TRACEME tracee exited prematurely 1 failed to set dr7: %s failed to PTRACE_CONT: %s tracee exited prematurely 2 rip %lx, bp_1 %p failed to PTRACE_DETACH: %s modify test 1 failed arch/x86/tests/bp-modify.c failed to set breakpoint: %s modify test 2 failed ibs_op Fail Pass color.ui libperf-gtk.so Error: Warning: %*.1f %*.2f%% Self Overhead guest sys guest usr Children Samples Period Weight1 Weight2 Weight3 | Not enough memory! %s | Bad callchain mode / # %s%-.*s %*sno entry >= %.2f%% %.10s end UNKNOWN %16s events: %10d (%4.1f%%) %16s events: %10d colors. Press any key... Warning! medium green normal selected black yellow blue magenta white assertion failed at %s:%d %s %s [Percent: %s] String not found! Couldn't annotate %s: %s Press ESC to exit No source file location. Source file location: %s ENTER: OK, ESC: Cancel String: Search Invalid jump offset: %lx ui/browsers/annotate.c local hits global hits local period global period %10s %10s %*s}; %10lu %10d %10.2f %10d %10d %s%s %10d %10d %*s%s %s%s %*s %10s %10s %10s %s Field %*s%c %s lost: %lu/%lu drop: %lu/%lu [z] -c %s -S %s --time %s,%s # Samples: %lu of event '%s' %lu%c%s%s : %ld%c%schunks LOST! <...> no entry >= %.2f%% Run scripts for all samples%s the Kernel %.*lx Annotate %s ui/browsers/hists.c out of into Collapse Expand Collecting samples... perf.hist.%d Couldn't write to %s: %s %s written! Verbosity level set to %d Symbol to show Percent Limit Invalid percent: %.2f Do you really want to exit? Annotate type %s Zoom %s %s(%d) thread Zoom %s %s thread Browse map details Zoom %s Processor Socket %d with assembler with source Exit Available samples ? - help %*lx %*lx %c restart with -v to use Search by name/addr %s not found! scripts. Running %s Cannot run %s [c[H[J --inline -i perf script -s Show individual samples %s script %s -F +metric %s %s -F +disasm -F +srcline,+srccode perf script command %s script %s %s%s %s %s%s 2>&1 | less Press 'q' to exit Header information samples.context --tid --cpu %s: CPU %d tid %d --show-lost-events [m TUI initialization failed. ^(kB) Fatal Error -------- backtrace -------- Warning: Error: Help Enter: Yes, ESC: No %s [%s/%s] local ↓ ↑ ← → Sorted summary for file %s Nothing higher than %1.1f%% %7.2f annotate. annotate.offset_level annotate.hide_src_code annotate.jump_arrows annotate.show_linenr annotate.show_nr_jumps annotate.show_nr_samples annotate.show_total_period annotate.use_offset annotate.disassembler_style annotate.addr2line annotate.demangle annotate.demangle_kernel [35m [34m %7lu %11lu %*lx: # +%.2f%% -%.2f%% (p:%.2f%%) // %s %*s: %*s: %-*d %s %s: addr=%#lx Percent %6.2f %6lu %11lu %*.2f %*s %*lu %lu(%lu/%lu) Cycle(min/max) %-*s %lx: %*lx: account_cycles failed %d %s: unsupported arch %s util/annotate.h %-*.*s---- %*lx: %lu h->nr_samples %*s: %lu %#lx %s %.*s %s %s.annotation %s() %s Event: %s %s, [percent: %s] %s() %s x86 %gs: push (stack canary) (stack operation) [%s -> %s] [%7lx -> %7lx] %.1fM %.1fK %1d [unknown] Sampled Cycles% Sampled Cycles Avg Cycles% Avg Cycles [Program Block Range] (%d:%d):(%d:%d) %s/sys/kernel/notes %s/%s/%s/kallsyms %s/%s/%s %s/.build-id/%.2s/%s vdso %s/.build-id/ Error in lsdir(%s): %d %s%s%s%s%s /usr/lib/debug/.build-id/ %.2s/%s.debug Can't read link: %s Found %d SDTs in %s util/build-id.c yes core. core.proc-map-timeout core.addr2line-timeout hist. ui.show-headers call-graph. buildid. buildid.dir Invalid buildid directory! stat. stat.big-num stat.no-csv-summary stat.bpf-counter-events /etc/perfconfig %s: strdup failed PERF_CONFIG_NOSYSTEM PERF_CONFIG_NOGLOBAL HOME %s/.perfconfig %s.%s Missing value for '%s' PERF_BUILDID_DIR %s.XXXXXXx unknown no branch trace begin / %s %s / trace end unconditional jump software interrupt return from interrupt return from system call asynchronous branch hardware interrupt transaction abort trace begin vm entry vm exit %-*s %s %-*s %s,%s nop %-*s %.*s%lx (%r ^blr?$ sub dec %-*s *%lx brinc bper bnl bnl+ bnl- bnla bnla+ bnla- bez bnez bnezad bhsz bhz blsz blz jmpi bsr rts jsri jsr bras brasl basr lrl lgrl llgfrl strl stgrl %*[^,],%u,%u,%u AuthenticAMD (%rip) jirl bltu bgeu bgezal bltzal bgtzal blezal beqzal bnezal bgtzl bltzl bgezl blezl jialc beql bnel jal jr jmpl retl mov ^/[^:]+:([0-9]+) %-*s Invalid BPF file: %s. --prefix-strip= --prefix -S --no-show-raw-insn -l -M /bin/sh Executing: %s Failure starting to run %s Error running %s No output from %s nop nopl nopw arm64 csky mips bwlq powerpc riscv64 sparc loongarch adc andps bt btr cmovbe cmove cmovae cmpxch cmpxchg divsd divss imul ja jae jb jbe jc jcxz je jecxz jg jge jl jle jna jnae jnb jnbe jnc jne jng jnge jnl jnle jno jnp jns jnz jo jp jpe jpo jrcxz js jz lea movapd movaps movdqu movss movsb movsw movsl movupd movups movzb movzw movzl mulss paddq pcmpeqb por rcl sbb sete tzcnt ucomiss vaddsd vandpd vmovdqa vmovq vmovsd vmulsd vorpd vsubsd vucomisd xadd xbegin xor xorpd xorps to be implemented duplicated bpf prog info %u duplicated btf %u pmu mappings not available %u:%s x86_64 mips64 parisc64 s390x sparc64 parisc sun4u sa110 Old New %s bytes: INVALID exec %s: %s:%d/%d %u/%s: %lu/%#lx%s cgroup: %llu %s nr: pid: %u tid: %u hw_id: %#llx OUT preempt IN OUT next prev %s %s pid/tid: %5d/%-5d type %u, flags %u, id %u %llx old len %u new len %u lost %llu <not found> [hypervisor] ... thread: %s:%d ...... dso: %s TOTAL NAMESPACES KSYMBOL BPF_EVENT CGROUP TEXT_POKE AUX_OUTPUT_HW_ID EVENT_TYPE TRACING_DATA BUILD_ID FINISHED_ROUND ID_INDEX AUXTRACE_INFO AUXTRACE AUXTRACE_ERROR THREAD_MAP CPU_MAP STAT_CONFIG STAT STAT_ROUND EVENT_UPDATE TIME_CONV FEATURE COMPRESSED FINISHED_INIT kernel/perf_event_mlock_kb mmap size %zuB %s && common_pid != %d failed to create 'ready' pipe failed to create 'go' pipe failed to fork perf-exec unable to read pipe unable to write to pipe Hint: Shouldn't get there Weak group for %s/%d failed fifo: ack \0 \n disabled Message from ctl_fd: "%s%s" disable is snapshot Events disabled Events enabled failed: wrong command Event %s %s -g -F ctlfd: unsupported %d , %u - %u %n timerfd_create failed: %s timerfd_settime failed: %s cycles:P cycles:Pu %s... mem-loads-aux %-32s %s %s/%s/comm oprofiled ppp user_time system_time ftrace:function msec %s:%s unknown-hardware %s-%s-%s unknown-ext-hardware-cache-op invalid-cache unknown-software raw 0x%lx unknown tracepoint mem:0x%lx: unknown attr type: %d anon group %s { (%s) && (%s) %.60s perf_event_attr: switching off bpf_event switching off ksymbol switching off write_backward switching off clockid switching off use_clockid switching off cloexec flag switching off mmap2 switching off sample_id_all switching off group read %s%su fs/selinux/enforce wrong clockid (%d). offcpu-time Opening: %s /proc/%d/stat /proc/stat broken group leader for %s user stack dump failure Reference prefetch prefetches speculative-read speculative-load L1-dcache l1-d L1-data L1-icache l1-i l1i L1-instruction LLC L2 dTLB d-tlb Data-TLB iTLB i-tlb Instruction-TLB bpu btb bpc page-faults context-switches cpu-migrations minor-faults major-faults alignment-faults emulation-faults cache-references bus-cycles stalled-cycles-frontend stalled-cycles-backend ref-cycles sample_freq %s{ %s=%lu (not a tracepoint) (no trace field) trace_fields: %s <- %c%16lx (inlined) PERF_TYPE_HARDWARE PERF_TYPE_BREAKPOINT PERF_TYPE_RAW PERF_TYPE_HW_CACHE PERF_TYPE_TRACEPOINT PERF_TYPE_SOFTWARE PERF_COUNT_HW_INSTRUCTIONS PERF_COUNT_HW_CPU_CYCLES PERF_COUNT_HW_REF_CPU_CYCLES PERF_COUNT_HW_BUS_CYCLES PERF_COUNT_HW_BRANCH_MISSES PERF_COUNT_HW_CACHE_MISSES PERF_COUNT_SW_CPU_CLOCK PERF_COUNT_SW_CGROUP_SWITCHES PERF_COUNT_SW_BPF_OUTPUT PERF_COUNT_SW_DUMMY PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_CPU_MIGRATIONS PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_TASK_CLOCK PERF_COUNT_HW_CACHE_L1D PERF_COUNT_HW_CACHE_L1I PERF_COUNT_HW_CACHE_LL PERF_COUNT_HW_CACHE_DTLB PERF_COUNT_HW_CACHE_ITLB PERF_COUNT_HW_CACHE_BPU PERF_COUNT_HW_CACHE_NODE PERF_COUNT_HW_CACHE_OP_READ PERF_COUNT_HW_CACHE_OP_WRITE %lu (%s) %#lx (%s) %#lx (%s | %s | %s) BRANCH_STACK REGS_USER STACK_USER IDENTIFIER REGS_INTR DATA_SRC WEIGHT PHYS_ADDR DATA_PAGE_SIZE CODE_PAGE_SIZE WEIGHT_STRUCT read_format exclude_idle inherit_stat enable_on_exec mmap_data exclude_host exclude_guest exclude_callchain_kernel exclude_callchain_user mmap2 comm_exec use_clockid context_switch write_backward namespaces ksymbol bpf_event aux_output cgroup text_poke build_id inherit_thread remove_on_exec { bp_addr, config1 } { bp_len, config2 } KERNEL HV ANY ANY_CALL ANY_RETURN IND_CALL ABORT_TX IN_TX NO_TX CALL_STACK IND_JUMP NO_FLAGS NO_CYCLES TYPE_SAVE HW_INDEX PRIV_SAVE COUNTERS branch_sample_type sample_regs_user sample_stack_user sample_regs_intr aux_watermark sample_max_stack aux_sample_size sig_data %p: %s mask[%zd]: %s %s'%s' event syntax error: %*s\___ %s %s hardware-cache No PMU found for '%s' <no help> failed to add tracepoint *? nr_addr_filters unknown term %s=%#lx valid terms: %s,%s valid terms: %s expected numeric value expected string value invalid branch sample type expected 0 or 1 too big Invalid term_type %s// Attempt to add: %s %s -> %s/%s/ fake_pmu Bad event or PMU <sysfs term> branch_type call-graph stack-size no-inherit max-stack no-overwrite driver-config percore aux-output aux-sample-size metric-id legacy-cache bpf-output cgroup-switches cpu-cycles branch-instructions idle-cycles-frontend idle-cycles-backend tracepoint/config=0x%llx/ Tracepoint event Failed to get buildids: %d %s:%s@%s %s@%s(%.12s) SDT event %s/%s/ Hardware cache event tool Tool event %s OR %s OR rNNN Raw event descriptor mem:<addr>[/len][:access] Hardware breakpoint Hardware event Software event %s/%s/id riscv vg regs0 regs1 regs2 regs3 regs4 regs5 regs6 regs7 regs8 regs9 %r1 %r2 %r3 %r4 %r5 %r6 %r7 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 $1 $2 $3 $4 $5 $6 $7 $8 $9 $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $20 $21 $22 $23 $24 $25 $28 $29 $30 $31 nip orig_r3 ccr softe sier mmcra mmcr0 mmcr1 mmcr2 mmcr3 sier2 sier3 pmc1 pmc2 pmc3 pmc4 pmc5 pmc6 sdar siar tp t0 s10 s11 t5 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 MASK AX BX CX DX SI DI SP DS FS XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 /bad-path/ devices/system/cpu/smt/active == || != && %s %s %d file:// %lu%s ], (target_pid: %s (target_tid: %s (uid: %s (all , CPU%s: %s) , %d CPU%s) /usr/lib/debug .debug%s [guest.kernel.kallsyms [%.*s] dso open failed: %s failed to get fd limit dso cache fstat failed: %s NOT dso: %s ( %sloaded, /tmp/perf-%d.map Invalid ELF file Can not read build id Mismatching build id Decompression failure %.0s%s %s/.debug/%s /usr/lib/debug%s/%s [JIT] tid %d %-40s %s /boot/vmlinux compat_SyS %s sym:%s end:%#lx %s: %s %#lx-%#lx acpi_idle_do_entry arch_cpu_idle cpu_startup_entry idle_cpu intel_idle intel_idle_ibrs default_idle native_safe_halt enter_idle exit_idle mwait_idle mwait_idle_with_hints poll_idle ppc64_runlatch_off pseries_dedicated_idle_sleep psw_idle psw_idle_exit __entry_SYSCALL_64_trampoline [guest.kernel].%d [kernel].%d @@ _stext Using %s for kernel data Using %s for symbols [kernel.kcore] /proc/kcore (deleted) problems parsing %s list Invalid file: %s /boot/vmlinux-%s /lib/modules/%s/build/vmlinux %lx-%lx %c %s +0x%lx [%#lx] [32m never always auto TERM dumb TopdownL No_group found event %s ,metric-id= /metric-id= ,-=@ }:W Parsing metric events '%s' Default Matched metric-id %s to %s metric expr %s for %s __threshold__ %s/level %s/coherency_line_size %s/number_of_sets %s/ways_of_associativity %s/type %s/size %s/shared_cpu_list # hybrid cpu system: # %s cpu list : %s Zstd Unknown # clockid frequency: %lu MHz # CPU cache info: L%d %-15s %8s [%s] # contains stat data # sibling sockets : %s # sibling dies : %s # sibling threads : %s , %s = %s # total memory : %llu kB # cpuid : %s # cpudesc : %s # nrcpus online : %u # nrcpus avail : %u # arch : %s # perf version : %s # os release : %s # hostname : %s # btf info of id %u # %3lu [%s]: %s # time of first sample : %s # time of last sample : %s # group: %s{%s # pmu mappings: %s%s = %u # node%u cpu list : # cmdline : %s\' unknown feature %d broken or missing trace data # %s pmu capabilities: # reference time disabled %F %T %s.%06d # clockid: %s (%u) legacy perf.data format %s/devices/system/node/ node%u memory%u util/header.c branch_counter_nr branch_counter_width group desc not available {anon_group} invalid group desc # event : name = %s, , id = { /proc/meminfo MemTotal: %*s %lu failed to write perf header failed to write feature %s /proc/cpuinfo model name /sys/devices/system/cpu/cpu%d # captured on : %s # header version : %u # data offset : %lu # data size : %lu # feat offset : %lu # missing features: magic/endian check failed endian/magic failed incompatible file format ... id: %llu ... scale: %f ... unit: %s ... name: %s ... failed to get cpus ... unknown type %s: reading input file HOSTNAME OSRELEASE VERSION ARCH NRCPUS CPUDESC TOTAL_MEM CMDLINE EVENT_DESC CPU_TOPOLOGY NUMA_TOPOLOGY PMU_MAPPINGS GROUP_DESC SAMPLE_TIME MEM_TOPOLOGY CLOCKID DIR_FORMAT BPF_PROG_INFO BPF_BTF CPU_PMU_CAPS CLOCK_DATA HYBRID_TOPOLOGY flat fractal folded Chain comparison error dwarf record-mode dump-size print-type Invalid callchain mode: %s order caller callee Invalid callchain order: %s sort-key print-limit none percent %s %s%s (calltrace) %s%s:%.1f%% %s%s:%ld iter avg_cycles %s: not enough memory # %*s %*s %*s %*s %*s Count Raw Name %*d %*d %*s %*lx %*lu # %*s %*s %*d %*d %04x: debug_file not set %F %H:%M:%S [%s.%06lu] [%13lu.%06lu] Obtained %zd stack frames. ordered-events stderr data-convert perf-event-open kmaps type-profile %s: cannot open %s dir build %s/proc/modules %s/proc/version Linux version %s/lib/modules/%s Thread init failed thread %d [guest.kernel.kallsyms.%d] [guest.kernel.kallsyms] [guest/%d] %s/%d Can't access file %s swapper : id:%llu: lost:%llu : id:%lu: lost samples :%llu bpf_trampoline_ bpf_dispatcher_ [0] %s [%d] %s _edata _etext [guest.kernel] %s/%s/proc/kallsyms Threads: %zu _entry_trampoline __entry_trampoline_start [kernel.vmlinux] __sched_text_start __sched_text_end __lock_text_start __lock_text_end __traceiter_contention_begin trace_contention_begin _text /data/app-lib/ /system/lib/ //anon /dev/zero /anon_hugepage [stack /SYSV [heap] APP_ABI APK_PATH %s/libs/%s/%s NDK_ROOT APP_PLATFORM bpf_prog_ %s with build id %s not found Failed to open %s , continuing without symbols %lx-%lx %lx %s Map: Map missing from maps overlapping maps: %s: %p not on the pstack! %s: top=%d, overflow! %s: underflow! : unhandled! Couldn't decompress data decomp (B): %zd to %zd failed to mmap file %#lx@%s [%#x]: event: %d -1 -1 %u %lu %#lx [%#x]: PERF_RECORD_%s .... %-5s 0x%016lx non matching sample_type non matching sample_id_all non matching read_format Cannot read kernel map ... LBR call chain: nr:%lu ..... %2d: %016lx ... FP chain: nr:%lu ... branch stack %s: nr:%lu ... branch callstack ..... %2lu: %016lx ... weight: %lu ,0x%x . data_src: 0x%lx .. phys_addr: 0x%lx .. data page size: %s .. code page size: %s ... transaction: %lx ... sample_read: ...... time enabled %016lx ...... time running %016lx .... group nr %lu ..... id %016lx, value %016lx , lost %lu : %d %d %s %llu ... time enabled : %llu ... time running : %llu ... id : %llu ... lost : %llu Processing events... failed to read event header bad event header size failed to read event data Aggregated stats:%s Kernel and module maps: Invalid cpu_list # ======== # ======== # Too big: nr %zu max_nr %zu Too big2: nr %zu max_nr %zu nr: %zu ... id: %llu idx: %llu cpu: %lld tid: %lld machine_pid: %lld vcpu: %llu 32-bit 64-bit event= event=%x <unknown> NNPA_ALL CRYPTO_ALL L2Miss 1 L2Miss 0 uOps OpBrnMisp 1 OpBrnMisp 0 OpBrnTaken 1 OpBrnTaken 0 OpReturn 1 OpReturn 0 CacheHitSt 1=O-State CacheHitSt 0=M-state L1TlbPgSz 4KB L1TlbPgSz 1GB L1TlbPgSz 2MB IcMiss 0 IcMiss 1 L1TlbPgSz RESERVED L1TlbPgSz 16KB IbsFetchLinAd: %016llx IbsFetchPhysAd: %016llx L3MissOnly %d IbsOpRip: %016llx L2Miss %d OpDcMissOpenMemReqs %2d OpMemWidth %2d bytes IbsDCLinAd: %016llx IbsDCPhysAd: %016llx IbsBrTarget: %016llx %u:%9s ibs_fetch zen4_ibs_extensions %*[^,],%u,%u problem parsing cpuid DataSrc 1=(reserved) DataSrc 2=Local node cache DataSrc 3=DRAM DataSrc 4=Remote node cache DataSrc 5=(reserved) DataSrc 6=(reserved) DataSrc 7=Other DataSrc 4=(reserved) DataSrc 6=Long-latency DIMM DataSrc 8=Extension Memory DataSrc 9=(reserved) DataSrc 10=(reserved) DataSrc 11=(reserved) fstat lstat lseek munmap brk rt_sigaction rt_sigprocmask rt_sigreturn ioctl pread64 pwrite64 select sched_yield mremap msync mincore shmget shmat shmctl dup dup2 pause getitimer alarm setitimer getpid sendfile connect accept sendto recvfrom sendmsg recvmsg shutdown listen getsockname getpeername socketpair setsockopt getsockopt clone vfork wait4 semget semop semctl shmdt msgget msgsnd msgrcv msgctl fcntl flock fsync fdatasync ftruncate getdents getcwd fchdir rename mkdir rmdir creat symlink readlink fchmod fchown lchown gettimeofday getrusage sysinfo ptrace getuid syslog getgid setuid setgid geteuid getegid setpgid getpgrp setsid setreuid setregid getgroups setgroups setresuid getresuid setresgid getresgid setfsuid setfsgid capget capset rt_sigpending rt_sigtimedwait rt_sigqueueinfo rt_sigsuspend sigaltstack utime mknod uselib personality ustat fstatfs getpriority setpriority sched_setparam sched_getparam sched_setscheduler sched_getscheduler sched_get_priority_max sched_get_priority_min sched_rr_get_interval mlock munlock munlockall vhangup modify_ldt pivot_root _sysctl arch_prctl adjtimex chroot acct settimeofday umount2 swapon swapoff reboot sethostname setdomainname iopl ioperm create_module delete_module get_kernel_syms query_module quotactl nfsservctl getpmsg putpmsg afs_syscall tuxcall security gettid readahead lsetxattr fsetxattr lgetxattr fgetxattr llistxattr flistxattr lremovexattr fremovexattr tkill sched_setaffinity set_thread_area io_setup io_destroy io_getevents io_submit io_cancel get_thread_area lookup_dcookie epoll_ctl_old epoll_wait_old remap_file_pages getdents64 set_tid_address restart_syscall semtimedop fadvise64 timer_create timer_settime timer_gettime timer_getoverrun timer_delete clock_settime clock_gettime clock_getres clock_nanosleep exit_group tgkill utimes vserver mbind set_mempolicy get_mempolicy mq_open mq_unlink mq_timedsend mq_timedreceive mq_notify mq_getsetattr kexec_load waitid add_key request_key keyctl ioprio_set ioprio_get inotify_init inotify_add_watch inotify_rm_watch migrate_pages mkdirat mknodat fchownat futimesat newfstatat unlinkat renameat symlinkat readlinkat fchmodat faccessat pselect6 ppoll unshare set_robust_list get_robust_list tee sync_file_range vmsplice move_pages utimensat epoll_pwait signalfd timerfd_create fallocate timerfd_settime timerfd_gettime accept4 signalfd4 eventfd2 epoll_create1 dup3 pipe2 inotify_init1 preadv pwritev rt_tgsigqueueinfo recvmmsg fanotify_init fanotify_mark prlimit64 name_to_handle_at open_by_handle_at clock_adjtime syncfs sendmmsg setns getcpu process_vm_readv process_vm_writev kcmp finit_module sched_setattr sched_getattr renameat2 seccomp getrandom memfd_create kexec_file_load bpf execveat userfaultfd membarrier mlock2 copy_file_range preadv2 pwritev2 pkey_mprotect pkey_alloc pkey_free statx io_pgetevents rseq uretprobe pidfd_send_signal io_uring_setup io_uring_enter io_uring_register open_tree move_mount fsopen fsconfig fsmount fspick pidfd_open clone3 close_range openat2 pidfd_getfd faccessat2 process_madvise epoll_pwait2 mount_setattr quotactl_fd landlock_create_ruleset landlock_add_rule landlock_restrict_self memfd_secret process_mrelease futex_waitv set_mempolicy_home_node cachestat fchmodat2 map_shadow_stack futex_wake futex_requeue statmount listmount lsm_get_self_attr lsm_set_self_attr lsm_list_modules mseal queue_event nr_events %u empty queue max_timestamp last_flush out of order event NONE FINAL HALF TOP TIME Tgid: NStgid: nsinfo refcnt unbalanced /proc/%d/ns/mnt /proc/%d/status util/namespaces.c /proc/self/status net uts ipc %d/task/%d/comm Thread %d %s :%d /proc/%s %d thread%s: %s/%d/comm Duplicate modifier '%c' (%s) Bad base %d number "%s" bad buffer in yy_scan_bytes() hypervisor non_idle Maximum precise value is 3 precise_max weak input in flex scanner failed Unrecognized input Bad event name syntax error memory exhausted PERF_CPUID Using CPUID %s kprobe uncore_ *?[ %s/events/%s.snapshot %s/events/%s.per-pkg %s/events/%s.unit %s/events/%s.scale long_desc topic identifier %s (%s) no value assigned for term Invalid sysfs entry %s=%s value too big for format events/%s %s/events Cannot parse alias %s: %d Cannot open %s Cannot set up %s %.*s/%s ,%s=%s %G%s %.*s/%s/ Failure to duplicate terms caps cpumask caps/max_precise config=0..0xffffffffffffffff config1=0..0xffffffffffffffff config2=0..0xffffffffffffffff config3=0..0xffffffffffffffff name=string period=number freq=number branch_type=(u|k|hv|any|...) call-graph=(fp|dwarf|lbr) stack-size=number max-stack=number nr=number aux-sample-size=number Unexpected event %s/%s/ %s=0..0x%llx %s=0..%llu Kernel PMU event %.*s/ ,.../modifier Cannot open %s for output ]]> </style> </defs> <g> </g> %.1f us %.1f ms <desc>Blocked on: %s</desc> blocked sample_hi waiting WAITING <desc>Waiting on: %s</desc> CPU %i c%i %9lli %6lli Mhz %6.2f Ghz <desc>%s</desc> disk Disk Network Sync Poll Running Deeper Idle Deepest Idle process2 Sleeping Waiting for cpu Blocked on IO </svg> topology: no memory Can't read '%s' writing file size failed can't read directory '%s' can't write count %s/%s/format Can't make temp file 0.6 can't read '%s' can't write header_page can't write header_event ftrace can't get tracing/events printk_formats saved_cmdlines Python Perl perl common_lock_depth common_flags common_preempt_count %d %16s HI_SOFTIRQ NET_TX_SOFTIRQ NET_RX_SOFTIRQ BLOCK_SOFTIRQ IRQ_POLL_SOFTIRQ TASKLET_SOFTIRQ SCHED_SOFTIRQ HRTIMER_SOFTIRQ RCU_SOFTIRQ HRTIMER_NORESTART HRTIMER_RESTART repiping input file no data repiping input file string no trace data in the file tracing trace_event__init failed did not read header page did not read header event error reading ftrace file. error parsing ftrace file. error parsing event file. error reading saved cmdlines %7d:%-*.*s [other] %*.*d %lu/0x%lx %-*llu %-*u [%c] %-#*llx %-5.2f [%5.1f%%] %-5s %2s %*.*s SVE n/a [e] %s [p] %s [.] %s %-*hd :%lx [%c] %-#.*llx [%c] %s+0x%llx %-#*llx %c Memory allocation failed %s %+d (%s) local_p_stage_cyc local_ins_lat Invalid regex: %s %s unsupported field option %s trace_fields Cannot find event: %s %s is not a tracepoint event # %s: %s sym_from sym_to dso_from dso_to addr_from addr_to Invalid --sort key: `+' overhead overhead_children {}, dcacheline Invalid --sort key: `%s' Unknown --sort key: `%s' parent Invalid --fields key: `+' Invalid --fields key: `%s' Unknown --fields key: `%s' overhead_sys overhead_us overhead_guest_sys overhead_guest_us weight1 weight2 weight3 symbol_daddr dso_daddr snoop symbol_iaddr phys_daddr data_page_size symbol_from symbol_to mispredict in_tx srcline_from srcline_to ipc_lbr srcfile local_weight symbol_size dso_size cgroup_id ipc_null code_page_size local_retire_lat simd typeoff Data Type Offset Data Type (unknown) DSO size Symbol size Transaction Branch in transaction Transaction abort Code Page Size Data Page Size Data Physical Address Blocked Data Cacheline Snoop Memory access TLB access Locked Data Object Code Symbol Data Symbol Local Pipeline Stage Cycle Local INSTR Latency Local Weight Branch Mispredicted Basic Block Cycles Target Address Source Address Target Symbol Source Symbol Target Shared Object Source Shared Object Trace output Time Socket Cgroup cgroup id (dev/inode) Parent symbol Source File IPC [IPC Coverage] To Source:Line From Source:Line Symbol Offset Simd Pid:Command comm,dso,symbol %s stats: call-graph=no , UID: %s , Thread: %s(%d) , Thread: %s , DSO: %s , Processor Socket: %d %d Hz, relative absolute Invalid percentage: %s hist.percentage kcore_dir__[1-9]* kernel/perf_event_max_stack kernel/nmi_watchdog data.* kernel/perf_event_paranoid /proc/version_signature %d.%d.%d tips.txt Tip: %s /proc/self/exe DEBUGINFOD_URLS system DEBUGINFOD_URLS=%s /proc/%d/root %s/devices/system/cpu/present physical_package_id die_id cluster_id core_id cpu_map not initialized %s: calloc failed %s/devices/system/node cpu%u %s%d-%d cpumask list: %s Error creating CPU topology %s/devices/system/node/online %*s %*d %31s %lu MemFree: no access to cgroup %s memory allocation failed {}[]()|*+?^$ no cgroup matched: %s PID/TID switch overriding CPU PID/TID switch overriding UID UID switch overriding CPU UID switch overriding SYSTEM BPF switch overriding CPU BPF switch overriding PID/TID BPF switch overriding UID BPF switch overriding THREAD Invalid User: %s /proc/self/maps cannot open maps %p-%p r-xp %*x %*x:%*x %*u %n perf-read-vdso32 perf-read-vdsox32 %s: %lu %lu %lu Invalid CPU %d for event %s. INTERVAL ... time %llu, type %s ... aggr_mode %d ... scale %d ... interval %u CPUs utilized %8.3f Invalid tool event 'max' Unknown tool event '%s' backend cycles idle %7.2f%% insn per cycle %7.2f stalled cycles per insn frontend cycles idle of all iTLB cache accesses of all dTLB cache accesses of all LL-cache accesses of all L1-icache accesses of all L1-dcache accesses of all cache refs of all branches %s (%s) %s %s_%d %s %s %8.1f %8.2f %c/sec "metric-value" : "%f", "metric-unit" : "%s" "variance" : %.2f, %s%.2f%% ( +-%6.2f%% ) of all time%s "core" : "S%d-D%d-C%d" "cpu" : "%d", "thread" : "%s-%d", S%d-D%d-C%d%s%d%s S%d-D%d-L%d-ID%d%s%d%s S%d-D%d-CLS%d%s%d%s S%d-D%d%s%d%s N%d%s%d%s S%d-D%d-C%d%s CPU%d%s %s-%d%s S%d-D%d-C%d S%d-D%d-L%d-ID%d S%d-D%d-CLS%d S%d-D%d N%d S%d-D%d-C%d CPU%-*d %*s-%-*d %-*s %*d { %s%lu%s%.2f (%.2f%%) # %s"%s" : "%s" "cgroup" : "%s", "metricgroup" : "%s"} <not counted> <not supported> %.2f%s %.0f%s %'*.2f %'*.0f %*.0f "counter-value" : "%f", "counter-value" : "%s", "unit" : "%s", "event" : "%s", %s [%s] "interval" : %lu.%09lu, %lu.%09lu%s %6lu.%09lu [H[2J #%*s %-*s cpus #%*s %-*s #%*s %*s-%-*s #%*s counts %*s %*s events 'BPF program(s) %s 'system wide 'CPU(s) %s process id '%s thread id '%s (%d runs) : "metric-value" : "none" %17.9f seconds time elapsed %17.9f seconds user %17.9f seconds sys %17.*f %*s# Final result: %17.*f (%+.*f) die cluster comm-pid cpu, socket,cpus, die,cpus, cluster,cpus, cache,cpus, core,cpus, comm-pid, node, instructions:u ?? %s:%u ??:0 .debug_line -e -a -f %c%s %016lx , %s[%lx] cannot open source file %s cannot mmap source file %s /proc/%u/ns/%s /proc/%d/task/%d/status couldn't open %s Name: PPid: VmPeak: Threads: process synth event failed failed to open directory: %s %s/proc/%d/task/%d/maps %s/proc/%d/task %s/proc Synthesizing id index Couldn't synthesize attrs. Couldn't synthesize config. Error writing feature Unknown file found %s.old failed to open %s: %s perf.data (try 'perf record' first) failed to open %s : %s util/data.c %s/data.%d data. %s/data Failed to rename %s to %s Failed to lseek to %zu: %s %s/kcore_dir %s/kcore_dir/kallsyms %s/kcore_dir__%d/kallsyms ... Time Shift %llu ... Time Muliplier %llu ... Time Zero %llu ... Time Cycles %llu ... Time Mask %#llx ... Cap Time Zero %d ... Cap Time Short %d Error flushing thread stack! __x86_indirect_thunk_ ▁ ▂ ▃ ▄ ▅ ▆ ▇ █ hot chain %d: cycles: %ld, hits: %.2f%% %35s %35s %35s %35s hot chain pair %d: --------------------------- [ Matched hot streams ] %s 0x%lx/0x%lx%s%s %s 0x%lx%s%s #%d 0x%lx %c %s which is near %s Symbol '%s' not found. Kernel symbol lookup: Uninitialized auxtrace_mmap failed to mmap AUX area AUX area mmap length %zu No AUX area event to sample itrace.debug-log-buffer-size unknown AUX %s error type %u time %lu.%09llu time 0 machine_pid %d vcpu %d %u %s errors instruction trace tracestop , Address filter: %s type: %u %s no ip %s 0x%llx %s CTC 0x%x FC 0x%x %s IF:%d %lld %s TXAbort:%u InTX:%u %s 0x%llx (NR=%d) %s 0x%llx IP:0 %s 0x%llx IP:1 %s IP:0 %s IP:1 %s SZ %s-byte Type 0x%llx %s ID 0x%02x Value 0x%llx %s Type 0x%02x Payload 0x%llx %s 0x%llx (%d) Bad Packet! PAD TNT TIP.PGD MODE.Exec MODE.TSX MTC TIP CYC PSB CBR TraceSTOP PIP OVF MNT PTWRITE EXSTOP PWRE PWRX BBP BIP EVD <bad> %s %s%d Call Jcc Jmp Loop IRet Int Syscall Sysret VMentry Erets Eretu .log Dumping debug log buffer End of debug log buffer dump %08lx: Bad instruction! Getting more data No more data Reference timestamp 0x%lx ERROR: Bad packet Scanning for PSB Setting timestamp %s to 0x%lx %s at 0x%lx ERROR: Never-ending loop ERROR: Internal error Wraparound timestamp Suppressing bad timestamp Timestamp out of range ERROR: Unexpected packet ERROR: Buffer overflow ERROR: Missing TIP after FUP Omitting PGE ip 0x%lx Setting IP Emulated ptwrite detected Skipping zero TIP.PGE Skipping zero FUP ERROR: Missing FUP after BEP ERROR: Missing FUP after CFE ERROR: Too many EVD packets timestamp: mtc_shift %u timestamp: tsc_ctc_mult %u timestamp: tsc_slip %#x Unknown error! Scanning for full IP ERROR: PSB without PSBEND Surprising PGE change in OVF! ERROR: TSC without TMA %s: last_mtc_ctc %#lx %s: last_ctc %#x %s: ctc_delta %#lx %s: delta %#lx %s: ctc %#x %s: new_ctc_delta %#lx %s: last_ctc_timestamp %#lx %s: fc %#x %s: expected_tsc %#lx ERROR: Missing VMCS VMCS: %#lx TSC Offset %#lx ERROR: Unknown VMCS Internal error Bad packet No more data Failed to get instruction Overflow packet Lost trace data Broken emulated ptwrite GenuineIntel,6,92, intel-pt.mispred-all intel-pt.max-loops intel-pt.cache-divisor %08x: Bad packet! ERROR: no guest machine ERROR: no guest thread ERROR: no thread perf,ptwrite switch: cpu %d tid %d perf_trace_sched_switch __perf_event_task_sched_out __switch_to switch_ip: %lx ptss_ip: %lx TSC %lx est. TSC %lx queue %u getting timestamp queue %u has no timestamp queue %u timestamp 0x%lx Bad AUX output hardware ID transactions cbr psb mwait pwre exstop pwrx evt iflag Max non-turbo ratio %lu Filter string len. %lu %s: bad filter string length Filter string %-20s%s Cap Event Trace %d TSC frequency %lu Maximum non-turbo ratio %u %s: %u range(s) PMU Type %ld Time Shift %lu Time Muliplier %lu Time Zero %lu Cap Time Zero %ld TSC bit %#lx NoRETComp bit %#lx Have sched_switch %ld Snapshot mode %ld Per-cpu maps %ld MTC bit %#lx MTC freq bits %#lx TSC:CTC numerator %lu TSC:CTC denominator %lu CYC bit %#lx %lx -> %lx %s Bad record! PMU Type %ld Time Shift %lu Time Muliplier %lu Time Zero %lu Cap Time Zero %ld Snapshot mode %ld l1d-miss l1d-access llc-miss llc-access tlb-miss tlb-access branch-miss remote-access COND-SELECT INSN-OTHER EV EXCEPTION-GEN RETIRED L1D-ACCESS L1D-REFILL TLB-ACCESS TLB-REFILL NOT-TAKEN MISPRED LLC-ACCESS LLC-REFILL REMOTE-ACCESS ALIGNMENT SVE-PARTIAL-PRED SVE-EMPTY-PRED SVE-OTHER EVLEN %d FP PRED AT EXCL AR SIMD-FP GP-REG UNSPEC-REG NV-SYSREG MTE-TAG MEMCPY MEMSET SG COND IND %s %lld %s 0x%llx el%d ns=%d VA 0x%llx PA 0x%llx ns=%d ch=%d pat=%x %s 0x%lx el%d %s %d TOT ISSUE XLAT TGT PA PBT CONTEXT OP-TYPE EVENTS DATA-SOURCE Get packet error! Prefix Header DW0 Header DW1 Header DW2 Header DW3 Format Length SO T8 T9 auxtrace.dumpdir %s/aux.ctr.%02x %s/aux.smp.%02x %*[^,],%u , version supported <= %x Magic number %llx CPU %lld NR_TRC_PARAMS %llx TRCCONFIGR %llx TRCTRACEIDR %llx TRCIDR0 %llx TRCIDR1 %llx TRCIDR2 %llx TRCIDR8 %llx TRCAUTHSTATUS %llx TS_SOURCE %lld ETMCR %llx ETMTRACEIDR %llx ETMCCER %llx ETMIDR %llx Header version %llx Snapshot %llx any_call any_ret ind_call abort_tx no_tx cond ind_jmp no_flags no_cycles save_type hw_index priv counter -I --user-regs= available registers: Unknown option name '%s' help.autocorrect one of these Did you mean %s? this ./%s :-1 dlopen failed for: '%s' filter_event filter_event_early perf_dlfilter_fns filter_description %-36s %s %39s%s List of available dlfilters: %s/dlfilters : available %-*s%-*s%s Unknown level %d Fwd Peer Yes N/A Data Addr |OP LOAD STORE PFETCH EXEC |LVL |SNP |TLB |LCK |BLK None Hit Miss HitM core, same node node, same socket socket, same board L1 L3 L4 L2 MHB Memory-side Cache Uncached CXL I/O Any cache LFB/MAB PMEM HIT Local RAM Remote RAM (1 hop) Remote RAM (2 hops) Remote Cache (1 hop) Remote Cache (2 hops) Walker Fault ldlat-loads %s/mem-loads,ldlat=%u/P mem-loads ldlat-stores %s/mem-stores/P mem-stores %lu%c start time %lu, end time %lu start time %d: %lu, end time %d: %lu Invalid time string %lu.%06lu %lu.%09lu %Y%m%d%H%M%S %s%02u Error creating IDs for '%s' division by zero %s/firmware/acpi/tables/NFIT adding ref metric %s: %s parsing metric: %s %s not found lookup(%s): val %f processing metric: %s ENTRY %s failed to count #smt_on #core_wide #slots #has_pmem Unrecognized literal '%s' literal: %s = %f FAULT_ALGN FAULT_DATA FAULT_INST ARCH_1 ARCH_2 ARCH_3 ARCH_4 ARCH_5 UNCOND SYSCALL SYSRET COND_CALL COND_RET ERET SERROR # # Branch Statistics: COND_FWD %8s: %5.1f%% COND_BWD CROSS_4K CROSS_2M SPEC_WRONG_PATH NON_SPEC_CORRECT_PATH monotonic CLOCK_ (not found) monotonic_raw realtime boottime tai mono real %s error: '%s' [%d] = %d, [%d] = ERROR, .text %s: cannot get elf header. .note.gnu.build-id .notes .note .plt.got .rela.dyn %s@plt offset_%#lx@plt .plt.sec .rela.plt .rel.plt %s: cannot read %s ELF file. .gnu_debuglink .symtab .dynsym .opd .init .exit adtx %s/kcore %s/modules .note.stapsdt gelf_xlatetom : %s %s : cannot get elf header. .stapsdt.base .probes Failed to get cache from %s %s/probes Failed to open cache(%d): %s Opening %s write=%d README kprobe_events CONFIG_KPROBE_EVENTS=y uprobe_events CONFIG_UPROBE_EVENTS=y {k,u}probe_events strlist__add failed (%d) Writing event: %s Failed to write event: %s -:%s Failed to delete event: %s Cache open error: %d Cache read error: %d Failed to add probe caches Added probe cache: %d Failed to get sdt note: %d sdt_%s %s:%s=%s p:%s/%s %s:0x%llx (0x%llx) [sp, Allocation error arg%d=%s%s Cache committed: %d Writing cache: %s%s Removed cached event: %s list cache with filter: %s %s (%s): *type: * x8/16/32/64,* *place (kretprobe): * *ref_ctr_offset* *u]<offset>* *Create/append/* *\imm-value,* :s64 :s32 :s16 :s8 :u8 :u16 :u32 :u64 %return .gnu.linkonce.this_module Failed to find module %s. Rebuild with -g, %s is out of .text, skip it. %7d File read error: %s +u %s%ld( %+ld( %s= %s%+ld __return .@ snprintf() failed: %d %s/kprobes/blacklist 0x%lx-0x%lx Blacklist: 0x%lx-0x%lx, %s Failed to init symbol map. Use vmlinux: %s machine__new_host() failed. Failed to init vmlinux path. Debuginfo analysis failed. <%s@%s:%d> <%s:%d> Failed to open %s: %s Searching variables at %s Available variables at %s @<%s+%lu> (No matched variables) start line end line Line range is %d to %d Failed to split arguments. sdt_ ;=@+% %%%s ;: ;:+@% util/probe-event.c %s_L%d parsing arg: %s into name:%s user_access type:%s -.[ %s(%d), %s(%d) $params $vars Parsing probe_events: %s Group:%s Event:%s probe:%c -> %s:%s= %c:%s/%s 0x0 %s:0x%lx (0x%lx) %s%s0x%lx %s%s%s+%lu %-20s (on in %s with [$+-]* Failed to get a map for %s Failed to load symbols in %s %s_%s Failed to make a group name. abs_%lx Found %d probe_trace_events. Probe point '%s' not found. Trying to use symbols. \%ld DW_OP %x is not supported. converting %s in %s Var real type: %s (%x) Array real type: %s (%x) Probe point found: %s+%lu Expanding %s into: ustring b%d@%d/%d %s type is %s. Out of memory error unsigned char %c%d Ignoring tail call from %s fname: %s, lineno:%d New line range: %d to %d [INV] [VAL] [EXT] Add new var: %s Error in strbuf Reversed line: %s:%d Matched function: %s [%lx] %s has no entry PC. Skipped .eh_frame \%lx found inline addr: 0x%jx Get %zd lines from this CU union struct enum [] (function_type) void* (unknown_type) @<%s+[%lu-%lu ,%lu-%lu ]> ,) %r0 $0 $26 $27 %29 $hi $lo %g0 %g1 %g2 %g3 %g4 %g5 %g6 %g7 %o0 %o1 %o2 %o3 %o4 %o5 %sp %o7 %l0 %l1 %l2 %l3 %l4 %l5 %l6 %l7 %i0 %i1 %i2 %i3 %i4 %i5 %fp %i7 %f0 %f1 %f2 %f3 %f4 %f5 %f6 %f7 %f8 %f9 %f10 %f11 %f12 %f13 %f14 %f15 %f16 %f17 %f18 %f19 %f20 %f21 %f22 %f23 %f24 %f25 %f26 %f27 %f28 %f29 %f30 %f31 %f32 %f33 %f34 %f35 %f36 %f37 %f38 %f39 %f40 %f41 %f42 %f43 %f44 %f45 %f46 %f47 %f48 %f49 %f50 %f51 %f52 %f53 %f54 %f55 %f56 %f57 %f58 %f59 %f60 %f61 %f62 %f63 %c0 %c1 %c2 %c3 %c4 %c5 %c6 %c7 %c8 %c9 %c10 %c11 %c12 %c13 %c14 %c15 %a0 %a1 %a2 %a3 %a4 %a5 %a6 %a7 %a8 %a9 %a10 %a11 %a12 %a13 %a14 %a15 %pswm %pswa %gpr0 %gpr1 %gpr2 %gpr3 %gpr4 %gpr5 %gpr6 %gpr7 %gpr8 %gpr9 %gpr10 %gpr11 %gpr12 %gpr13 %gpr14 %gpr15 %gpr16 %gpr17 %gpr18 %gpr19 %gpr20 %gpr21 %gpr22 %gpr23 %gpr24 %gpr25 %gpr26 %gpr27 %gpr28 %gpr29 %gpr30 %gpr31 %msr %xer %link %ctr %dsisr %dar %x0 %x1 %x2 %x3 %x4 %x5 %x6 %x7 %x8 %x9 %x10 %x11 %x12 %x13 %x14 %x15 %x16 %x17 %x18 %x19 %x20 %x21 %x22 %x23 %x24 %x25 %x26 %x27 %x28 %x29 %lr %ip %pc %ax %dx %cx %bx %si %di %bp $stack Open Debuginfo file: %s variable has no type no pointer or no type type size is unknown variable location: base=reg%d, offset=%#lx reg%ld base=reg%ld, offset=%#lx use frame base, offset=%#lx address=%#lx percpu base constant pointer stack canary %7d %10d %10d %*s%s %s %*s} cannot get the debug info reg%d, reg%d CU for %s (die:%#lx) frame base: cfa=%d fbreg=%d addr=%#lx type_offset=%#x scope: [%d/%d] (die:%lx) bb: [%lx - %lx] var [%lx] -%#x(stack) var [%lx] reg%d fbreg cfa percpu var percpu ptr this-cpu var global var negative offset __fentry__ call [%x] %s call [%x] return -> reg%d this_cpu_off add [%x] percpu %#lx -> reg%d mov [%x] imm=%#x -> reg%d mov [%x] reg%d -> reg%d mov [%x] -%#x(stack) -> reg%d mov [%x] %#x(reg%d) -> reg%d __per_cpu_offset mov [%x] percpu base reg%d mov [%x] reg%d -> -%#x(stack) no variable found (unknown type) event[%d] = %s %*s %10s %10s %s unwind: resume unsupported '' WARNING: ui->thread is NULL unwind: Only supports local. unwind: Unspecified error. unwind: access_reg w %d unwind: can't read reg %d unwind: reg %d, val %lx unwind: no map for %lx .eh_frame_hdr \" \\ \b \f \r \t \u%04x "0x%lx" Sample resolution failed! %li Error opening output file! Error creating perf session! Symbol init error! "linux-perf-json-version": 1 "headers": { header-version %FT%TZ captured-on data-offset data-size feat-offset os-release cpu-desc nrcpus-online nrcpus-avail clock-time real-time perf-version cmdline "samples": [ %s.py import os import sys from Core import * def trace_begin(): print("in trace_begin") def trace_end(): print("in trace_end") def %s__%s( event_name, context, common_cpu, common_secs, common_nsecs, common_pid, common_comm, common_callchain, perf_sample_dict print(" " \ " %%d %%u " %% \ ( flag_str(" %s__%s", "%s", %s) symbol_str(" )) if 'sym' in node: else: print() generated Python script: %s couldn't create Python tuple %5s:0x%lx stat__%s can't find python handler %s error resizing Python tuple couldn't create Python list %s+0x%x trace_end unthrottle define_symbolic_field define_flag_field define_flag_value define_symbolic_value auxtrace_error binding sym_off sym_srcline Can't open python script "%s" __main__ perf_trace_context perf_script_context trace_begin failed to initialize export perf_db_export_mode perf_db_export_calls perf_db_export_callchains evsel_table machine_table comm_table comm_thread_table dso_table symbol_table branch_type_table sample_table call_path_table call_return_table context_switch_table synth_data bcrosyiABExghDt ev_name phys_addr time_enabled time_running values couldn't create mem-info datasrc datasrc_decode raw_buf mispred from_dsoname to_dsoname brstack brstacksym machine_pid vcpu cpumode addr_correlates_sym addr_dso_map_end addr_dso_map_start addr_dso_bid addr_dso addr_symoff addr_symbol flags_disp insn_cnt cyc_cnt iregs uregs common_pid %s__%s trace_unhandled couldn't create Python dict common_cpu common_s common_ns common_comm common_callchain func_code __code__ co_argcount 1.3.1 Compressed file is corrupt Unknown error, possibly a bug rb lzma: read error: %s lzma: write error: %s lzma: failed %s void byte double float short boolean $SP$ $BP$ $RF$ $LT$ $GT$ $LP$ $RP$ $u20$ $u27$ $u5b$ $u5d$ $u7e$ jit marker trying : %s /jit- .dump jit marker found: %s [anon: /memfd: %s/jitted-%d-%lu.so write ELF image %s cannot create jit ELF %s: %s injected: %s (%d) ELF initialization failed elf_begin failed cannot get ehdr cannot create section cannot get new data cannot get section header cannot allocate strsym failed to create EVP_MD_CTX elf_update 4 failed elf_update debug failed Overwrite existing hook: %s record_end record_start [bpf] bpf_trampoline_%lu bpf_dispatcher_%s -- kernel too old? # bpf_prog_info %u: can't get prog info: %s %s: mismatch in rec size CROSS_COMPILE riscv32 mips-unknown-linux-gnu- mipsel-linux-android- mips-linux-gnu- mips64-linux-gnu- mips64el-linux-gnuabi64- mips64-linux-gnuabi64- mipsel-linux-gnu- x86_64-pc-linux-gnu- x86_64-unknown-linux-gnu- i686-pc-linux-gnu- i586-pc-linux-gnu- i486-pc-linux-gnu- i386-pc-linux-gnu- i686-linux-android- i686-android-linux- x86_64-linux-gnu- i586-linux-gnu- sparc-unknown-linux-gnu- sparc64-unknown-linux-gnu- sparc64-linux-gnu- sh-unknown-linux-gnu- sh-linux-gnu- s390-ibm-linux- s390x-linux-gnu- riscv64-unknown-linux-gnu- riscv64-linux-android- riscv64-linux-gnu- riscv32-unknown-linux-gnu- riscv32-linux-android- riscv32-linux-gnu- powerpc-unknown-linux-gnu- powerpc-linux-gnu- powerpc64-unknown-linux-gnu- powerpc64-linux-gnu- powerpc64le-linux-gnu- aarch64-linux-android- aarch64-linux-gnu- arm-eabi- arm-linux-androideabi- arm-unknown-linux- arm-unknown-linux-gnu- arm-unknown-linux-gnueabi- arm-linux-gnu- arm-linux-gnueabihf- arm-none-eabi- arc-linux- arc-snps-linux-uclibc- arc-snps-linux-gnu- %s,%u,%u,%u$ %s-%u-%X-%X$ @ @ %lfGHz intel_bts %#llx:%s POUT PIN %#lx:%s kvm:kvm_msr kvm:kvm_pio kvm:kvm_mmio gpa VMX Hygon SVM HLT vmexit ioport kvm:kvm_entry kvm:kvm_exit MSR Access IO Port Access MMIO Access exit_reason vcpu_id VM-EXIT read_cr0 read_cr2 read_cr3 read_cr4 read_cr8 write_cr0 write_cr2 write_cr3 write_cr4 write_cr8 read_dr0 read_dr1 read_dr2 read_dr3 read_dr4 read_dr5 read_dr6 read_dr7 write_dr0 write_dr1 write_dr2 write_dr3 write_dr4 write_dr5 write_dr6 write_dr7 DE excp DB excp BP excp OF excp BR excp UD excp NM excp DF excp TS excp NP excp SS excp GP excp PF excp MF excp AC excp MC excp XF excp nmi smi vintr cr0_sel_write read_idtr read_gdtr read_ldtr read_rt write_idtr write_gdtr write_ldtr write_rt rdtsc rdpmc pushf popf rsm iret swint hlt invlpg invlpga task_switch ferr_freeze vmrun hypercall vmload vmsave stgi clgi skinit rdtscp icebp wbinvd monitor xsetbv write_efer_trap write_cr0_trap write_cr4_trap write_cr8_trap invpcid npf avic_incomplete_ipi avic_unaccelerated_access vmgexit vmgexit_mmio_read vmgexit_mmio_write vmgexit_nmi_complete vmgexit_ap_hlt_loop vmgexit_ap_jump_table vmgexit_page_state_change vmgexit_guest_request vmgexit_ext_guest_request vmgexit_ap_creation vmgexit_hypervisor_feature invalid_guest_state EXCEPTION_NMI EXTERNAL_INTERRUPT TRIPLE_FAULT INIT_SIGNAL SIPI_SIGNAL INTERRUPT_WINDOW NMI_WINDOW TASK_SWITCH INVLPG RDPMC RDTSC VMCALL VMCLEAR VMLAUNCH VMPTRLD VMPTRST VMREAD VMRESUME VMWRITE VMOFF VMON CR_ACCESS DR_ACCESS IO_INSTRUCTION MSR_READ MSR_WRITE INVALID_STATE MSR_LOAD_FAIL MWAIT_INSTRUCTION MONITOR_TRAP_FLAG MONITOR_INSTRUCTION PAUSE_INSTRUCTION MCE_DURING_VMENTRY TPR_BELOW_THRESHOLD APIC_ACCESS EOI_INDUCED GDTR_IDTR LDTR_TR EPT_VIOLATION EPT_MISCONFIG INVEPT RDTSCP PREEMPTION_TIMER INVVPID WBINVD XSETBV APIC_WRITE RDRAND INVPCID VMFUNC ENCLS RDSEED PML_FULL XSAVES XRSTORS UMWAIT TPAUSE BUS_LOCK NOTIFY %eax Regex compilation error. +0 %.*s%.*s%.*s%.*s%.*s %rax %al %ah %ebx %rbx %bl %bh %ecx %rcx %cl %ch %edx %rdx %dl %dh %esi %rsi %sil %edi %rdi %dil %ebp %rbp %bpl %rsp %esp %spl %r8b %r8w %r8d %r9b %r9w %r9d %r10b %r10w %r10d %r11b %r11w %r11d %r12b %r12w %r12d %r13b %r13w %r13d %r14b %r14w %r14d %r15b %r15w %r15d Local Retire Latency uops_retired.slots topdown mem-ldst %04x:%02hhx Mode iostat is not supported Failed to realloc memory %08x:%02hhx S%d-uncore_iio_%d<%04x:%02x> %6lu.%09lu%s%04x:%02x%s port, port %8.0f Inbound Read(MB) Inbound Write(MB) Outbound Read(MB) Outbound Write(MB) rip unwind: invalid reg id %d GenuineIntel, -%u caps/topa_multiple_entries psb_period %s psb_period %zu %s: failed, error %d caps/mtc caps/mtc_periods ,mtc,mtc_period=%d caps/psb_cyc caps/psb_periods ,psb_period=%d format/pt format/branch ,pt,branch %s default config: %s noretcomp mtc_period max_nonturbo_ratio caps/event_trace cyc_thresh caps/cycle_thresholds Intel PT snapshot size: %zu JITDUMP_USE_ARCH_TIMESTAMP Intel BTS: TSC not available Intel BTS snapshot size: %zu (sIs#) (sI) common_pc perf_sample_insn perf_set_itrace_options Set --itrace options. perf_sample_srcline perf_sample_srccode GenuineIntel-6-BE GenuineIntel-6-(3D|47) GenuineIntel-6-56 GenuineIntel-6-4F GenuineIntel-6-9[6C] GenuineIntel-6-CF GenuineIntel-6-5[CF] GenuineIntel-6-7A GenuineIntel-6-B6 GenuineIntel-6-A[DE] GenuineIntel-6-(3C|45|46) GenuineIntel-6-3F GenuineIntel-6-7[DE] GenuineIntel-6-6[AC] GenuineIntel-6-3A GenuineIntel-6-3E GenuineIntel-6-2D GenuineIntel-6-(57|85) GenuineIntel-6-BD GenuineIntel-6-A[AC] GenuineIntel-6-1[AEF] GenuineIntel-6-2E GenuineIntel-6-A7 GenuineIntel-6-2A GenuineIntel-6-8F GenuineIntel-6-AF GenuineIntel-6-55-[01234] GenuineIntel-6-86 GenuineIntel-6-8[CD] GenuineIntel-6-2C GenuineIntel-6-25 GenuineIntel-6-2F AuthenticAMD-23-[[:xdigit:]]+ AuthenticAMD-25-[[:xdigit:]]+ AuthenticAMD-26-[[:xdigit:]]+ |s |iii { type: sample } |OOii i|i |ii |ss perf: Init failed! wakeup_events bp_addr cpustr Get tracepoint config. COUNT_HW_CACHE_REFERENCES COUNT_HW_BRANCH_INSTRUCTIONS COUNT_HW_CACHE_OP_PREFETCH COUNT_HW_CACHE_RESULT_ACCESS COUNT_HW_CACHE_RESULT_MISS COUNT_SW_CONTEXT_SWITCHES COUNT_SW_ALIGNMENT_FAULTS COUNT_SW_EMULATION_FAULTS SAMPLE_IP SAMPLE_TID SAMPLE_ADDR SAMPLE_READ SAMPLE_CALLCHAIN SAMPLE_ID SAMPLE_CPU SAMPLE_PERIOD SAMPLE_STREAM_ID SAMPLE_RAW FORMAT_TOTAL_TIME_ENABLED FORMAT_TOTAL_TIME_RUNNING FORMAT_ID FORMAT_GROUP RECORD_MMAP RECORD_LOST RECORD_COMM RECORD_EXIT RECORD_THROTTLE RECORD_UNTHROTTLE RECORD_FORK RECORD_READ RECORD_SAMPLE RECORD_MMAP2 RECORD_AUX RECORD_ITRACE_START RECORD_LOST_SAMPLES RECORD_SWITCH RECORD_SWITCH_CPU_WIDE RECORD_MISC_SWITCH_OUT perf.evlist open the file descriptors. get_pollfd read_on_cpu reads an event. perf.evsel perf.thread_map perf.cpu_map perf.context_switch_event sample_ip event ip sample_pid event pid sample_tid event tid sample_time event timestamp sample_addr event addr sample_id event id sample_stream_id event stream id event period sample_cpu event cpu event type next_prev_pid next/prev pid next_prev_tid next/prev tid perf.sample_event perf.read_event perf.lost_event lost number of lost events perf.throttle_event perf.comm_event perf.task_event event ppid event ptid perf.mmap_event event misc start of the map map length pgoff page offset filename backing store Cannot determine the current working directory Error: too many args to run %s %s available from elsewhere on your $PATH cannot be used with switch `%c' expects an unsigned numerical value should not happen, someone must be hit on the forehead STOP_AT_NON_OPTION and KEEP_UNKNOWN don't go together Error: did you mean `--%s` (with two dashes ?) Error: Ambiguous option: %s (could be --%s%s or --%s%s) SUBCMD_HAS_NOT_BEEN_INITIALIZED perf bench [<common options>] <collection> <benchmark> [<options>] # List of all available benchmark collections: Unknown format descriptor: '%s' Invalid repeat option: Must specify a positive value # List of available benchmarks for collection '%s': Unknown benchmark: '%s' for collection '%s' Specify the output formatting style Specify number of times to repeat the run NUMA scheduling and MM benchmarks Baseline libc usleep(1000) call Attach empty BPF prog to uprobe on usleep, system wide Attach trace_printk BPF prog to uprobe on usleep syswide Attach empty BPF prog to uretprobe on usleep, system wide Attach trace_printk BPF prog to uretprobe on usleep syswide Benchmark thread start/finish with breakpoints Benchmark breakpoint enable/disable Benchmark perf event synthesis Benchmark evlist open and close Benchmark sysfs PMU info scanning Benchmark epoll concurrent epoll_waits Benchmark epoll concurrent epoll_ctls Benchmark for futex hash table Benchmark for futex wake calls Benchmark for parallel futex wake calls Benchmark for futex requeue calls Benchmark for futex lock_pi calls Benchmark for memcpy() functions Benchmark for memset() functions Benchmark for find_bit() functions Run all memory access benchmarks Benchmark for basic getppid(2) calls Benchmark for getpgid(2) calls Benchmark for scheduling and IPC Benchmark for pipe() between two processes Benchmark for seccomp user notify # %d sender and receiver %s per group perf bench sched messaging <options> Use pipe() instead of socketpair() Be multi thread instead of multi process Specify the number of loops to run (default: 100) Failed to open cgroup file in %s Hint: create the cgroup first, like 'mkdir %s/%s' it should have two cgroup names: %s # Executed %d pipe operations between two %s perf bench sched pipe <options> Specify threads/process based task setup Put sender and receivers in given cgroups can't create a notification descriptor can't set the parent death signal can't set SECCOMP_USER_NOTIF_FD_SYNC_WAKE_UP SECCOMP_IOCTL_NOTIF_RECV failed SECCOMP_IOCTL_NOTIF_SEND failed perf bench sched secccomp-notify <options> Enable the synchronous mode for seccomp notifications # Memory allocation failed - maybe size (%s) is too large? No CONFIG_PERF_EVENTS=y kernel support configured? Failed to open cycles counter Default memset() provided by glibc unrolled memset() in arch/x86/lib/memset_64.S movsq-based memset() in arch/x86/lib/memset_64.S perf bench mem memset <options> perf bench mem memcpy <options> Default memcpy() provided by glibc unrolled memcpy() in arch/x86/lib/memcpy_64.S movsq-based memcpy() in arch/x86/lib/memcpy_64.S Specify the size of the memory buffers. Available units: B, KB, MB, GB and TB (case insensitive) Specify the function to run, "all" runs all available functions, "help" lists them Specify the number of loops to run. (default: 1) Use a cycles event instead of gettimeofday() to measure performance Non-expected futex return call Run summary [PID %d]: %d threads, each operating on %d [%s] futexes for %d secs. [thread %2d] futex: %p [ %ld ops/sec ] [thread %2d] futexes: %p ... %p [ %ld ops/sec ] %sAveraged %ld operations/sec (+- %.2f%%), total secs = %d perf bench futex hash <options> Specify amount of futexes per threads Silent mode: do not display data/details Use shared futexes instead of private ones Lock all current and future memory Run summary [PID %d]: blocking on %d threads (at [%s] futex %p), waking up %d at a time. Wokeup %d of %d threads in %.4f ms (+-%.2f%%) [Run %d]: Wokeup %d of %d threads in %.4f ms perf bench futex wake <options> Specify amount of threads to wake at once couldn't wakeup all tasks (%d/%d) Run summary [PID %d]: blocking on %d threads (at [%s] futex %p), %d threads waking up %d at a time. Avg per-thread latency (waking %d/%d threads) in %.4f ms (+-%.2f%%) [Run %d]: Avg per-thread latency (waking %d/%d threads) in %.4f ms (+-%.2f%%) perf bench futex wake-parallel <options> Specify amount of waking threads Run summary [PID %d]: Requeuing %d threads (from [%s] %p to %s%p), %d at a time. Requeued %d of %d threads in %.4f ms (+-%.2f%%) couldn't requeue from %p to %p [Run %d]: Requeued %d of %d threads in %.4f ms [Run %d]: Awoke and Requeued (%d+%d) of %d threads in %.4f ms perf bench futex requeue <options> Specify amount of threads to requeue at once Use PI-aware variants of FUTEX_CMP_REQUEUE thread %d: Could not lock pi-lock for %p (%d) thread %d: Could not unlock pi-lock for %p (%d) Run summary [PID %d]: %d threads doing pi lock/unlock pairing for %d secs. [thread %3d] futex: %p [ %ld ops/sec ] perf bench futex lock-pi <options> starting writer-thread: doing %s writes ... exiting writer-thread (total full-loops: %zd) Setting RLIMIT_NOFILE rlimit from %lu to: %lu Run summary [PID %d]: %d threads monitoring%s on %d file-descriptors for %d secs. starting worker/consumer %sthreads%s [thread %2d] fdmap: %p [ %04ld ops/sec ] [thread %2d] fdmap: %p ... %p [ %04ld ops/sec ] Averaged %ld operations/sec (+- %.2f%%), total secs = %d perf bench epoll wait <options> Specify amount of file descriptors to monitor for each thread Enable random write behaviour (default is lineal) Use multiple epoll instances (one per thread) Nonblocking epoll_wait(2) behaviour Nesting level epoll hierarchy (default is 0, no nesting) Use Edge-triggered interface (default is LT) Run summary [PID %d]: %d threads doing epoll_ctl ops %d file-descriptors for %d secs. [thread %2d] fdmap: %p [ add: %04ld; mod: %04ld; del: %04lds ops ] [thread %2d] fdmap: %p ... %p [ add: %04ld ops; mod: %04ld ops; del: %04ld ops ] Averaged %ld ADD operations (+- %.2f%%) Averaged %ld MOD operations (+- %.2f%%) Averaged %ld DEL operations (+- %.2f%%) perf bench epoll ctl <options> Perform random operations on random fds Average %ssynthesis took: %.3f usec (+- %.3f usec) Average num. events: %.3f (+- %.3f) Average time per event %.3f usec Computing performance of single threaded perf event synthesis by synthesizing events on the perf process itself: Computing performance of multi threaded perf event synthesis by synthesizing events on CPU 0: Number of synthesis threads: %u Average synthesis took: %.3f usec (+- %.3f usec) Average num. events: %.3f (+- %.3f) Average time per event %.3f usec perf bench internals synthesize <options> Minimum number of threads in multithreaded bench Maximum number of threads in multithreaded bench Number of iterations used to compute single-threaded average Number of iterations used to compute multi-threaded average Average kallsyms__parse took: %.3f ms (+- %.3f ms) perf bench internals kallsyms-parse <options> Number of iterations used to compute average %d operations %d bits set of %d bits Average for_each_set_bit took: %.3f usec (+- %.3f usec) Average test_bit loop took: %.3f usec (+- %.3f usec) perf bench mem find_bit <options> Number of outer iterations used Number of inner iterations used Build-id%s injection benchmark Build-id injection setup failed Average build-id%s injection took: %.3f msec (+- %.3f msec) Average time per event: %.3f usec (+- %.3f usec) Average memory usage: %.0f KB (+- %.0f KB) Cannot collect DSOs for injection perf bench internals inject-build-id <options> Number of iterations used to compute average (default: 100) Number of mmap events for each iteration (default: 100) Number of sample events per mmap event (default: 100) be more verbose (show iteration count, DSO name, etc) Not enough memory to create evlist Run 'perf list' for a list of valid events Not enough memory to create thread/cpu maps Number of events: %d (%d fds) Average open-close took: %.3f usec (+- %.3f usec) perf bench internals evlist-open-close <options> event selector. use 'perf list' to list available events number of dummy events to create (default 1). If used with -e, it clones those events n times (1 = no change) Number of iterations used to compute average (default=100) system-wide collection from all CPUs list of cpus where to open events record events on existing process id record events on existing thread id Skipping perf bench breakpoint thread: No hardware support # Created/joined %d threads with %d breakpoints and %d parallelism Skipping perf bench breakpoint enable: No hardware support # Enabled/disabled breakpoint %d time with %d passive and %d active threads perf bench breakpoint enable <options> Specify amount of passive threads Specify amount of active threads perf bench breakpoint thread <options> Computing performance of sysfs PMU event scan for %u times pmu[%d] name=%s, nr_caps=%d, nr_aliases=%d, nr_formats=%d Failed to initialize PMU scan result Unmatched number of event caps in %s: expect %d vs got %d Unmatched number of event aliases in %s: expect %d vs got %d Unmatched number of event formats in %s: expect %d vs got %d Average%s PMU scanning took: %.3f usec (+- %.3f usec) perf bench internals pmu-scan <options> binding to node %d, mask: %016lx => %d WARNING: Could not enable THP - do: 'echo madvise > /sys/kernel/mm/transparent_hugepage/enabled' WARNING: Could not disable THP: run a CONFIG_TRANSPARENT_HUGEPAGE kernel? # thread %2d / %2d global mem: %p, process mem: %p, thread mem: %p (injecting perturbalance, moved to CPU#%d) #%2d / %2d: %14.2lf nsecs/op [val: %016lx] Test not applicable, system has only %d CPUs. Test not applicable, bind_cpu_0 or bind_cpu_1 is offline # NOTE: ignoring bind CPUs starting at CPU#%d # # NOTE: %d tasks bound, %d tasks unbound Test not applicable, system has only %d nodes. # NOTE: ignoring bind NODEs starting at NODE#%d # NOTE: %d tasks mem-bound, %d tasks unbound # %d %s will execute (on %d nodes, %d CPUs): # %5dx %5ldMB global shared mem operations # %5dx %5ldMB process shared mem operations # %5dx %5ldMB thread local mem operations # Startup synchronization: ... # process %2d global mem: %p, process mem: %p threads initialized in %.6f seconds. secs slowest (max) thread-runtime secs fastest (min) thread-runtime % difference between max/avg runtime # Running %s "perf bench numa echo ' #'; echo ' # Running test on: '$(uname -a); echo ' #' perf bench numa mem [<options>] process serialized/locked memory access (MBs), <= process_memory max number of loops to run (default: unlimited) max number of seconds to run (default: 5 secs) usecs to sleep per loop iteration access the data via reads (can be mixed with -W) access the data via writes (can be mixed with -R) access the data backwards as well access the data via glibc bzero only access the data with random (32bit LFSR) walk randomize the contents of the initial allocations do the initial allocations on CPU#0 perturb thread 0/0 every X secs, to test convergence stability MADV_NOHUGEPAGE < 0 < MADV_HUGEPAGE show convergence details, convergence is reached when each process (all its threads) is running on a single NUMA node. quiet mode (do not show any warnings or messages) bind the first N tasks to these specific cpus (the rest is unbound) bind the first N tasks to these specific memory nodes (the rest is unbound) perf test [<options>] [{list <test-name-fragment>|[<test-name-fragments>|<test-numbers>]}] be more verbose (show symbol address, etc) Run the tests one after another rather than in parallel objdump binary to use for disassembly and annotations Out of memory while building script test suite list Out of memory while duplicating test script string failed to parse event '%s', err %d %s/bus/event_source/devices/%s/alias %s/bus/event_source/devices/%s/events/ skipping PMU %s events tests: %s pmu event name crossed PATH_MAX(%d) size can't open pmu event file for '%s' pmu event: %s is a null event skipping parameterized PMU event: %s which contains ? Test PMU event failed for '%s' COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks config=10,config1,config2=3,config3=4,umask=1,read,r0xead failed to parse terms '%s', err %d Event test failure: test %d '%s' Parse event definition strings Parsing of all PMU events from sysfs Parsing of given PMU events from sysfs Parsing of aliased events from sysfs Parsing of terms (event modifiers) cpu/config=10,config1=1,config2=3,period=1000/u cpu/config=1,name=krava/u,cpu/config=2/u cpu/config=1,call-graph=fp,time,period=100000/,cpu/config=2,call-graph=no,time=0,period=2000/ cpu/name='COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks',period=0x1,event=0x2/ukp cpu/L1-dcache-misses,name=cachepmu/ cpu/cycles,period=100000,config2/ {cpu/instructions/k,cpu/cycles/upp} {cpu/cycles/u,cpu/instructions/kp}:p {cpu/cycles/,cpu/cache-misses/G}:H {cpu/cycles/,cpu/cache-misses/H}:G {cpu/cycles/G,cpu/cache-misses/H}:u {cpu/cycles/G,cpu/cache-misses/H}:uG {cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:S {cpu/instructions/,cpu/branch-misses/}:Su {cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:D {cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:e r1,syscalls:sys_enter_openat:k,1:1:hp {faults:k,branches}:u,cycles:k group1{syscalls:sys_enter_openat:H,cycles:kppp},group2{cycles,1:3}:G,instructions:u {cycles,instructions}:G,{cycles:G,instructions:G},cycles {cycles,cache-misses,branch-misses}:S {instructions,branch-misses}:Su {cycles,cache-misses,branch-misses}:D L1-dcache-misses/name=cachepmu/ cycles/name='COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks'/Duk {cycles,cache-misses,branch-misses}:e mem:0/1/name=breakpoint1/,mem:0/4:rw/name=breakpoint2/ test attr - failed to open event file test attr - failed to write event file '/usr/bin/python3' %s/attr.py -d %s/attr/ -p %s %.*s WARN: Maps in vmlinux with a different name in kallsyms: WARN: %lx-%lx %lx %s in kallsyms as machine__create_kernel_maps failed Couldn't find a vmlinux that matches the kernel running on this machine, skipping test WARN: %#lx: diff end addr for %s v: %#lx k: %#lx WARN: %#lx: diff name v: %s k: %s ERR : %#lx: %s not on kallsyms vmlinux symtab matches kallsyms failed to open counter: %s, tweak /proc/sys/kernel/perf_event_paranoid? evsel__read_on_cpu: expected to intercept %d calls, got %lu sched_setaffinity() failed on CPU %d: %s evsel__read_on_cpu: expected to intercept %d calls on cpu %d, got %lu Detect openat syscall event on all cpus openat_syscall_event_on_all_cpus %s: Expected flags=%#x, got %#x syscalls:sys_enter_openat event fields failed to get mmapped address userspace counter access not %s userspace counter width not set (%d) failed to read value for evsel failed to mmap events: %d (%s) event with id %lu doesn't map to an evsel expected %d %s events, got %d Read samples using the mmap interface User space counter reading of instructions User space counter reading of cycles sched__get_first_possible_cpu: %s %s going backwards in time, prev=%lu, curr=%lu %s with unexpected cpu, expected %d, got %d %s with unexpected pid, expected %d, got %d %s with unexpected tid, expected %d, got %d Unexpected perf_event->header.type %d! Excessive number of PERF_RECORD_COMM events! Missing PERF_RECORD_COMM for %s! PERF_RECORD_MMAP for %s missing! PERF_RECORD_* events & perf_sample fields Failure to parse cache event '%s' possibly as PMUs don't support it perf_evsel__roundtrip_name_test %s: "%s" signedness(%d) is wrong, should be %d %s: "%s" size (%d) should be %d! Parse sched tracepoints fields fdarray__filter()=%d != %d shouldn't have filtered anything fdarray__filter()=%d != %d, should have filtered all fds filtering all but fda->entries[2]: fdarray__filter()=%d != 1, should have left just one event filtering all but (fda->entries[0], fda->entries[3]): fdarray__filter()=%d != 2, should have left just two events %d: fdarray__add(fda, %d, %d) failed! %d: fdarray__add(fda, %d, %d)=%d != %d %d: fda->entries[%d](%d) != %d! %d: fda->entries[%d].revents(%d) != %d! Add fd to a fdarray, making it autogrow Filter fds with revents mask in a fdarray uncore_cha suffixes ordered lt uncore_cha suffixes ordered gt mrvl_ddr_pmu suffixes ordered lt mrvl_ddr_pmu suffixes ordered gt %s/bus/event_source/devices/%s/type %s/bus/event_source/devices/%s/events Skipping as no event directory "%s" sysfs event '%s' should be all lower/upper case, it will be matched using legacy encoding. Invalid sysfs event name: %s/%s config2:0-3,10-13,20-23,30-33,40-43,50-53,60-63 Failed to open test directory "%s" Failed to mkdir PMU directory Failed to open for writing file "type" Failed to write to 'type' file Failed to mkdir PMU format directory ) Failure to set up path for "%s" Failed to open for writing file "%s" Failed to mkdir PMU events directory perf-pmu-test/events/test-event krava01=15,krava02=170,krava03=1,krava11=27,krava12=1,krava13=2,krava21=119,krava22=11,krava23=2 Failed to write to 'test-event' file Failure to set up buffer for "%s" krava01=15,krava02=170,krava03=1,krava11=27,krava12=1,krava13=2,krava21=119,krava22=11,krava23=2 Unexpected config1 value %llx Unexpected config2 value %llx Parsing with PMU format directory Expected broken metric %s skipping testing event table: found %d, but expected %d Missing test event in test architecture testing core PMU %s aliases: failed testing core PMU %s aliases: no events to match testing core PMU %s aliases: pass testing aliases uncore PMU %s: mismatch expected aliases (%d) vs found (%d) testing aliases uncore PMU %s: mismatched matching_pmu, %s vs %s testing aliases uncore PMU %s: could not match alias %s testing aliases uncore PMU %s: mismatch found aliases (%d) vs matched (%d) testing aliases PMU %s: mismatched name, %s vs %s testing aliases PMU %s: mismatched desc, %s vs %s testing aliases PMU %s: mismatched long_desc, %s vs %s testing aliases PMU %s: mismatched topic, %s vs %s testing aliases PMU %s: mismatched str, %s vs %s testing aliases PMU %s: mismatched pmu_name, %s vs %s testing aliases core PMU %s: matched event %s testing event e1 %s: mismatched name string, %s vs %s testing event e1 %s: mismatched compat string, %s vs %s testing event e1 %s: mismatched event, %s vs %s testing event e1 %s: mismatched desc, %s vs %s testing event e1 %s: mismatched topic, %s vs %s testing event e1 %s: mismatched long_desc, %s vs %s testing event e1 %s: mismatched pmu string, %s vs %s testing event e1 %s: mismatched unit, %s vs %s testing event e1 %s: mismatched perpkg, %d vs %d testing event e1 %s: mismatched deprecated, %d vs %d testing sys event table %s: pass testing sys event table: could not find event %s testing event table: could not find event %s Parsing of PMU event table metrics Parsing of PMU event table metrics with fake PMUs Parsing of metric thresholds with fake PMUs (unc_p_power_state_occupancy.cores_c0 / unc_p_clockticks) * 100. imx8_ddr0@read\-cycles@ * 4 * 4 imx8_ddr0@axid\-read\,axi_mask\=0xffff\,axi_id\=0x0000@ * 4 (cstate_pkg@c2\-residency@ / msr@tsc@) * 100 (imx8_ddr0@read\-cycles@ + imx8_ddr0@write\-cycles@) Counts total cache misses in first lookup result (high priority) uncore_imc_free_running.cache_miss unc_cbo_xsnp_response.miss_eviction A cross-core snoop resulted from L3 Eviction which misses in some processor core Attributable Level 3 cache access, read Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions event=9,period=200000,umask=0x20 Memory cluster signals to block micro-op dispatch for any reason event=0x9,period=0x30d40,umask=0x20 event=6,period=200000,umask=0x80 Number of segment register loads event=0x6,period=0x30d40,umask=0x80 Not enough memory for machine setup %2d: entry: %-8s [%-8s] %20s: period = %lu %2d: entry: %8s:%5d [%-8s] %20s: period = %lu/%lu Invalid count for matched entries: %zd of %zd A entry from the other hists should have pair Invalid count of dummy entries: %zd of %zd Invalid count of total leader entries: %zd of %zd Other hists should not have dummy entries: %zd Not enough memory for adding a hist entry Unmatched nr samples for thread filter Unmatched nr hist entries for thread filter Unmatched total period for thread filter Unmatched nr samples for dso filter Unmatched nr hist entries for dso filter Unmatched total period for dso filter Unmatched nr samples for symbol filter Unmatched nr hist entries for symbol filter Unmatched total period for symbol filter Unmatched nr samples for socket filter Unmatched nr hist entries for socket filter Unmatched total period for socket filter Unmatched nr samples for all filter Unmatched nr hist entries for all filter Unmatched total period for all filter use callchain: %d, cumulate callchain: %d Incorrect number of hist entry Invalid callchain entry #%zd/%zd Incorrect number of callchain entry echo "import sys ; sys.path.insert(0, '%s'); import perf" | %s %s failed setting up signal handler failed setting up signal handler 2 count1 %lld, count2 %lld, count3 %lld, overflow %d, overflows_2 %d failed: RF EFLAG recursion issue detected failed: wrong count for bp1: %lld, expected 1 failed: wrong overflow (%d) hit, expected 3 failed: wrong overflow_2 (%d) hit, expected 3 failed: wrong count for bp2 (%lld), expected 3 failed: wrong count for bp3 (%lld), expected 2 Breakpoint overflow signal handler Wrong number of executions %lld != %d Wrong number of overflows %d != %d way too many debug registers, fix the test watchpoints count %d, breakpoints count %d, has_ioctl %d, share %d ioctl(PERF_EVENT_IOC_MODIFY_ATTRIBUTES) failed Failed after retrying 1000 times Number of exit events of a simple workload /proc/sys/kernel/perf_event_max_sample_rate Couldn't open evlist: %s Hint: check %s, using %lu in this test. failed to mmap event: %d (%s) All (%d) samples have period value of 1! Software clock events period values failed with sythesizing process Failed to parse event dummy:u Failed to move cycles event to front Front event no longer at front Non-tracking event is tracking perf_evlist__disable_event failed! sched_switch: cpu: %d prev_tid %d next_tid %d cycles events even though event was disabled parse_event(evlist, "dummy:u") failed! parse_event(evlist, "cycles:u") failed! Unable to open dummy and cycles event evlist__mmap(evlist, UINT_MAX) failed! prctl(PR_SET_NAME, (unsigned long)comm, 0, 0, 0) failed! First time, failed to find tracking event. evsel__disable(evsel) failed! Second time, failed to find tracking event. Use a dummy software event to keep tracking machine__create_kernel_maps failed thread_map__new_by_tid failed perf_event__synthesize_thread_map failed machine__findnew_thread failed perf_evlist__open() failed! %s temp-perf-code-reading-test-file-- Reading object code for memory address: %#lx Hypervisor address can not be resolved - skipping Unexpected kernel address - skipping skipping the module address %#lx after text end Too many kcore maps - skipping %s -z -d --start-address=0x%lx --stop-address=0x%lx %s addr going backwards, read beyond section? objdump read too few bytes: %zd Bytes read differ from those read by objdump Bytes read match those read by objdump machine__process_event failed, event type %u Samples differ at 'stream_id' Samples differ at 'read.group.nr' Samples differ at 'read.one.value' Samples differ at 'read.time_enabled' Samples differ at 'read.time_running' Samples differ at 'read.group.values[i]' Samples differ at 'read.one.id' Samples differ at 'read.one.lost' Samples differ at 'callchain->nr' Samples differ at 'callchain->ips[i]' Samples differ at 'branch_stack->nr' Samples differ at 'branch_stack->hw_idx' Samples differ at 'branch_stack->entries[i]' Samples differ at 'user_regs.mask' Samples differ at 'user_regs.abi' Samples differ at 'user_regs' Samples differ at 'user_stack.size' Samples differ at 'user_stack' Samples differ at 'transaction' Samples differ at 'intr_regs.mask' Samples differ at 'intr_regs.abi' Samples differ at 'intr_regs' Samples differ at 'phys_addr' Samples differ at 'data_page_size' Samples differ at 'code_page_size' Samples differ at 'aux_sample.size' Samples differ at 'aux_sample' %s failed for sample_type %#lx, error %d Event size mismatch: actual %zu vs expected %zu parsing failed for sample_type %#lx perf_event__process_attr failed Parse with no sample_id_all bit set %s - alloc name %d, kmod %d, comp %d, name '%s' %s (cpumode: %d) - is_kernel_module: %s Session header CPU map not set Cpu map - CPU ID doesn't match Cpu map - Core ID doesn't match Cpu map - Socket ID doesn't match Cpu map - Die ID doesn't match Core map - Core ID doesn't match Core map - Socket ID doesn't match Core map - Die ID doesn't match Die map - Socket ID doesn't match Die map - Die ID doesn't match Socket map - Socket ID doesn't match Socket map - Thread IDX is set Node map - Node ID doesn't match failed to intersect map: bad nr failed to intersect map: bad result failed to merge map: bad result 1,3,5,7,9,11,13,15,17,19,21-40 failed to synthesize stat_config failed to synthesize attr update unit failed to synthesize attr update scale failed to synthesize attr update name failed to synthesize attr update cpus failed to parse event cpu-clock:u attaching to spawned child, enable on exec attaching to current thread as enabled failed to call thread_map__new attaching to current thread as disabled Failed to open event cpu-clock:u attaching to CPU 0 as enabled failed to call perf_cpu_map__new 100 if 1 else 200 if 1 else 300 100 if 0 else 200 if 1 else 300 100 if 1 else 200 if 0 else 300 100 if 0 else 200 if 0 else 300 EVENT1\,param\=?@ + EVENT2\,param\=?@ EVENT1 if #core_wide else EVENT2 1.0 if EVENT1 > 100.0 else 1.0 syscalls:sys_enter_prctl/overwrite/ Failed to parse tracepoint event, try use root Unexpected counter: sample_count=%d, comm_count=%d Skip SDT event test because SDT support is not compiled SIGSEGV is observed as expected, try to recover. start: %lu end: %lu name: '%s' refcnt: %d start: %lu end: %lu name: '%s' refcnt: 1 Failed. ptime %lu expected %lu perf_time__parse_for_ranges("%s") first_sample_time %lu last_sample_time %lu bad size: range_size %d range_num %d expected num %d bad range %d expected %lu to %lu 1234567.123456789,1234567.123456789 1234567.123456789,1234567.123456790 1234567.123456789,1234567.123456790 7654321.987654321,7654321.987654444 8000000,8000000.000000005 10000000000000000000000000000abcdefgh99i 10000000000000000000000000000000000000000000000000000000000123456789ab99c Ljava/lang/StringLatin1;equals([B[B)Z boolean java.lang.StringLatin1.equals(byte[], byte[]) Ljava/util/zip/ZipUtils;CENSIZ([BI)J long java.util.zip.ZipUtils.CENSIZ(byte[], int) Ljava/util/regex/Pattern$BmpCharProperty;match(Ljava/util/regex/Matcher;ILjava/lang/CharSequence;)Z boolean java.util.regex.Pattern$BmpCharProperty.match(java.util.regex.Matcher, int, java.lang.CharSequence) Ljava/lang/AbstractStringBuilder;appendChars(Ljava/lang/String;II)V void java.lang.AbstractStringBuilder.appendChars(java.lang.String, int, int) camlStdlib__anon_fn$5bstdlib$2eml$3a334$2c0$2d$2d54$5d_1453 Stdlib.anon_fn[stdlib.ml:334,0--54]_1453 camlStdlib__bytes__$2b$2b_2205 test of individual --pfm-events cpu_clk_unhalted.one_thread_active Frontend_Bound_SMT failed, wrong ratio DCache_L2_Hits failed, wrong ratio DCache_L2_Misses failed, wrong ratio L1D_Cache_Fill_BW, wrong ratio cache_miss_cycles failed, wrong ratio group cache_miss_cycles failed, wrong ratio failed to expand events for cgroups evsel[%d]: %s expected: %s event group doesn't match: got %s, expect %s event group member doesn't match: %d vs %d failed to expand default events failed to expand metric events perf_read_tsc_conversion is not supported in current kernel prctl(PR_SET_NAME, (unsigned long)comm1, 0, 0, 0) failed! prctl(PR_SET_NAME, (unsigned long)comm2, 0, 0, 0) failed! evsel = evlist__event2evsel(evlist, event) failed! evsel__parse_sample(evsel, event, &sample) failed! 1st event perf time %lu tsc %lu rdtsc time %lu tsc %lu 2nd event perf time %lu tsc %lu This architecture does not support perf_read_tsc_conversion is not supported -- Testing version %d API -- /tmp/dlfilter-test-%u-perf-data Filter used by the 'dlfilter C API' perf test Failed to get expected filter description int bar(){};int foo(){bar();};int main(){foo();return 0;} Creating new host machine structure Failed to find program symbols Failed to create test perf.data file perf_header__write_pipe() failed perf_event__synthesize_attr() failed perf_event__synthesize_sample() failed %s script -i %s --dlfilter %s/%s --dlarg first --dlarg %d --dlarg %lu --dlarg %lu --dlarg %d --dlarg last perf_event_attr doesn't have sigtrap FAILED sys_perf_event_open(): %s missing signals or incorrectly delivered Using %s for uncore pmu event 0x%x 0x%lx, 0x%x 0x%lx, 0x%x 0x%lx: %s machine__findnew_thread() failed! Failed to find map for current kernel module %s failed: crossed the max stack value %d failed: got unresolved address 0x%lx got wrong number of stack entries %lu != %d failed to allocate sample uregs data Intel PT hybrid CPU compatibility Samples differ at 'retire_lat' {cpu_core/cycles/,cpu_core/branches/} {cpu_core/cycles/k,cpu_core/branches/u} cpu_core/config=10,config1,config2=3,period=1000/u {cpu_core/cycles/,cpu_core/cpu-cycles/} sched_setaffinity() failed for CPU %d CPU %d CPUID leaf 20 subleaf %d intel_pt_get_packet returned %d Expected length: %d Decoded length %d Expected type: %d Decoded type %d Expected count: %d Decoded count %d Expected payload: 0x%llx Decoded payload 0x%llx Expected packet context: %d Decoded packet context %d Is %shybrid : CPUID leaf 7 subleaf 0 edx %#x (bit-15 indicates hybrid) CPU %d same caps as previous CPU CPU %d subleaf %d reg %d FAIL %#x vs %#x CPU %d subleaf 1 reg 0 FAIL address filter count %#x vs %#x failed to set breakpoint, 1st time: %s failed to set breakpoint, 2nd time: %s failed to PTRACE_PEEKUSER: %s failed, breakpoint set to bogus address type: 0x%x, config: 0x%lx, fd: %d - GTK browser requested but could not find %s Not enough memory to display remaining hits WARN: jump target inconsistency, press 'o', notes->offsets[%#x] = NULL Press 'h' for help on key bindings ui/browsers/../../util/annotate.h UP/DOWN/PGUP PGDN/SPACE Navigate </> Move to prev/next symbol q/ESC/CTRL+C Exit ENTER Go to target H Go to hottest instruction TAB/shift+TAB Cycle thru hottest instructions j Toggle showing jump to target arrows J Toggle showing number of jump sources on targets n Search next string o Toggle disassembler output/simplified view O Bump offset level (jump targets -> +call -> all -> cycle thru) s Toggle source code view t Circulate percent, total period, samples view c Show min/max cycle / Search string k Toggle line numbers l Show full source file location P Print to [symbol_name].annotation file. r Run available scripts p Toggle percent type [local/global] b Toggle percent base [period/hits] ? Search string backwards f Toggle showing offsets to full address Only available for source code lines. %d: nr_ent=%d, height=%d, idx=%d, top_idx=%d, nr_asm_entries=%d Huh? No selection. Report to linux-kernel@vger.kernel.org Actions are only available for assembly lines. Actions are only available for function call/return & jump/branch instructions. The called function was not found. Not enough memory for annotating '%s' symbol! Annotate type: '%s' (%d samples) UP/DOWN/PGUP PGDN/SPACE Navigate </> Move to prev/next symbol q/ESC/CTRL+C Exit Can't search all data files due to memory shortage. Too many perf data files in PWD! Only the first 32 files will be listed. Data switch failed due to memory shortage! Won't switch the data files due to no valid data file get selected! Run scripts for samples of thread [%s]%s Run scripts for samples of symbol [%s]%s To zoom out press ESC or ENTER + "Zoom out of %s(%d) thread" To zoom out press ESC or ENTER + "Zoom out of %s thread" To zoom out press ESC or ENTER + "Zoom out of %s DSO" Events are being lost, check IO/CPU overload! You may want to run 'perf' using a RT scheduler policy: perf top -r 80 Or reduce the sampling frequency. %d: nr_ent=(%d,%d), etl: %d, rows=%d, idx=%d, fve: idx=%d, row_off=%d, nrows=%d Press '?' for help on key bindings Press 'f' again to re-enable the events Press 'f' to disable the events or 'h' to see other hotkeys Max event group index to sort is %d (index from 0 to %d) Annotation is only available for symbolic views, include "sym*" in --sort to use it. No samples for the "%s" symbol. Probably appeared just in a callchain Too many perf.hist.N files, nothing written! Please enter the name of symbol you want to see. To remove the filter later, press / + ENTER. Please enter the value you want to hide entries under that percent. Zoom %s %s DSO (use the 'k' hotkey to zoom directly into the kernel) %s [%s] callchain (one level, same as '+' hotkey, use 'e'/'c' for the whole main level entry) Show context for individual samples %s Switch to another data file in PWD ESC: exit, ENTER|->: Browse histograms Press ESC to exit, %s / to search Prefix with 0x to search by address Show individual samples with assembler Show individual samples with source Show samples with custom perf script arguments Enter perf script command line (without perf script prefix) --show-switch-events --show-task-events %s script %s%s --time %s %s%s %s%s --ns %s %s %s %s %s | less +/%s ESC: exit, ENTER|->: Select option maximum size of symbol name reached! ---------------------------------------------- Not enough memory for annotate.disassembler_style Not enough memory for annotate.objdump Not enough memory for annotate.addr2line %s variable unknown, ignoring... %s(%d): ERANGE! sym->name=%s, start=%#lx, addr=%#lx, end=%#lx %s(%d): ENOMEM! sym->name=%s, start=%#lx, addr=%#lx, end=%#lx, func: %d %#lx %s: period++ [addr: %#lx, %#lx, evidx=%d] => nr_samples: %lu, period: %lu (Average IPC: %.2f, IPC Coverage: %.1f%%) BB with bad start: addr %lx start %lx sym %lx saddr %lx %s: failed to initialize %s arch priv area %-*.*s| Source code & Disassembly of %s for %s (%lu samples, percent: %s) --prefix-strip requires --prefix problem processing %d event, skipping it. build <%s> already linked to %s Failed to update/scan SDT cache for %s bad config value for '%s' in %s, ignoring... bad config value for '%s', ignoring... bad config file line %d in %s Not enough memory to process %s/.perfconfig, ignoring it. File %s not owned by current user or root, ignoring it. Error in the given config file: wrong config key-value pair %s=%s ^[ct]?br?\.?(cc|cs|eq|ge|gt|hi|hs|le|lo|ls|lt|mi|ne|pl|vc|vs)?n?z?$ ^blx?(cc|cs|eq|ge|gt|hi|le|ls|lt|mi|ne|pl|vc|vs)?$ ^bx?(cc|cs|eq|ge|gt|hi|le|ls|lt|mi|ne|pl|vc|vs)?$ %*[^,],%u,%[^,],%[^,],%[^,],%s No vmlinux file%s was found in the path. Note that annotation using /proc/kcore requires CAP_SYS_RAWIO capability. Please use: perf buildid-cache -vu vmlinux or: --vmlinux vmlinux Please link with binutils's libopcode to enable BPF annotation Problems with arch specific instruction name regular expressions. Problems while parsing the CPUID in the arch specific initialization. The %s BPF file has no BTF section, compile with -g or use pahole -J. Internal error: Invalid %d error code %s: filename=%s, sym=%s, start=%#lx, end=%#lx annotating [%p] %30s : [%p] %30s %s %s%s --start-address=0x%016lx --stop-address=0x%016lx %s -d %s %s %s %c%s%c %s%s -C "$1" Failure allocating memory for the command to run Failure creating FILE stream for %s Failure allocating memory for tab expansion no arch specific strerrno function unknown stat config term %llu %d/%d - nr_namespaces: %u [ %d/%d: [%#llx(%#llx) @ %#llx]: %c %s %d/%d: [%#llx(%#llx) @ %#llx <%s>]: %c%c%c%c %s %d/%d: [%#llx(%#llx) @ %#llx %02x:%02x %llu %llu]: %c%c%c%c %s failed to get threads from event failed to get cpumap from event offset: %#llx size: %#llx flags: %#llx [%s%s%s] addr %llx len %u type %u flags 0x%x name %s rounding mmap pages size to %s (%lu pages) Invalid argument for --mmap_pages/-m Read format differs %#lx vs %#lx FATAL: evlist->threads need to be set at this point (%s:%d). Error: %s. Hint: Check /proc/sys/kernel/perf_event_paranoid setting. For your workloads it needs to be <= 1 Hint: For system wide tracing it needs to be set to -1. Hint: Try: 'sudo sh -c "echo -1 > /proc/sys/kernel/perf_event_paranoid"' Hint: The current value is %d. kernel/perf_event_max_sample_rate Error: %s. Hint: Check /proc/sys/kernel/perf_event_max_sample_rate. Hint: The current value is %d and %lu is being requested. Error: %s. Hint: Check /proc/sys/kernel/perf_event_mlock_kb (%d kB) setting. Hint: Tried using %zd kB. Hint: Try 'sudo sh -c "echo %d > /proc/sys/kernel/perf_event_mlock_kb"', or Hint: Try using a smaller -m/--mmap-pages value. Control descriptor is not initialized Failed to add ctl fd entry: %m failed to write to ctl_ack_fd %d: %m Failed to read from ctlfd %d: %m failed: can't find '%s' event WARNING: A requested CPU in '%s' is not supported by PMU '%s' (CPUs %s) for event '%s' cannot locate proper evsel for the side band event enabling sample_id_all for all side band events unknown-ext-hardware-cache-type unknown-ext-hardware-cache-result decreasing precise_ip by one (%d) switching off branch counters support switching off PERF_FORMAT_LOST support switching off weight struct support Kernel has no PERF_SAMPLE_CODE_PAGE_SIZE support, bailing out Kernel has no PERF_SAMPLE_DATA_PAGE_SIZE support, bailing out Kernel has no cgroup sampling support, bailing out switching off branch HW index support Kernel has no attr.aux_output support, bailing out PMU has no exclude_host/guest support, bailing out switching off exclude_guest, exclude_host switching off branch sample type no (cycles/flags) The cycles event is not supported, trying to fall back to %s kernel.perf_event_paranoid=%d, trying to fall back to excluding kernel and hypervisor samples Access to performance monitoring and observability operations is limited. Enforced MAC policy settings (SELinux) can limit access to performance monitoring and observability operations. Inspect system audit records for more perf_event access control information and adjusting the policy. No permission to enable %s event. Consider adjusting /proc/sys/kernel/perf_event_paranoid setting to open access to performance monitoring and observability operations for processes without CAP_PERFMON, CAP_SYS_PTRACE or CAP_SYS_ADMIN Linux capability. More information can be found at 'Perf events and tool security' document: https://www.kernel.org/doc/html/latest/admin-guide/perf-security.html perf_event_paranoid setting is %d: -1: Allow use of (almost) all events by all users Ignore mlock limit after perf_event_mlock_kb without CAP_IPC_LOCK >= 0: Disallow raw and ftrace function tracepoint access >= 1: Disallow CPU event access >= 2: Disallow kernel profiling To make the adjusted perf_event_paranoid setting permanent preserve it in /etc/sysctl.conf (e.g. kernel.perf_event_paranoid = <setting>) The %s event is not supported. Too many events are opened. Probably the maximum number of open file descriptors has been reached. Hint: Try again after reducing the number of events. Hint: Try increasing the limit with 'ulimit -n <limit>' /proc/sys/kernel/perf_event_max_stack Not enough memory to setup event with callchain. Hint: Try tweaking /proc/sys/kernel/perf_event_max_stack Hint: Current value: %d No such device - did you specify an out-of-range profile CPU? %s: PMU Hardware or event type doesn't support branch stack sampling. %s: PMU Hardware doesn't support 'aux_output' feature %s: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat' 'precise' request may not be supported. Try removing 'p' modifier. No hardware sampling interrupt available. The PMU counters are busy/taken by another profiler. We found oprofile daemon running, please stop it and try again. Asking for the code page size isn't supported by this kernel. Asking for the data page size isn't supported by this kernel. Reading from overwrite event is not supported by this kernel. clockid feature not supported. The 'aux_output' feature is not supported, update the kernel. Invalid event (%s) in per-thread mode, enable system wide with '-a'. Cannot collect data source with the load latency event alone. Please add an auxiliary event in front of the load latency event. The sys_perf_event_open() syscall returned with %d (%s) for event (%s). /bin/dmesg | grep -i perf may provide additional information. LBR callstack option is only available to get user callchain information. Falling back to framepointers. Cannot use LBR callstack with branch stack. Falling back to framepointers. WARNING: The use of --call-graph=dwarf may require all the user registers, specifying a subset with --user-regs may render DWARF unwinding unreliable, so the minimal registers set (IP, SP) is explicitly forced. Cannot use DWARF unwind for function trace event, falling back to framepointers. Disabling user space callchains for function trace event. per-event callgraph setting for %s failed. Apply callgraph global setting for it sys_perf_event_open: pid %d cpu %d group_fd %d flags %#lx sys_perf_event_open failed, error %d failed to attach bpf fd %d: %s WARNING: Ignored open failure for pid %d <not enough memory for the callchain cursor>%s PERF_COUNT_HW_STALLED_CYCLES_BACKEND PERF_COUNT_HW_STALLED_CYCLES_FRONTEND PERF_COUNT_HW_BRANCH_INSTRUCTIONS PERF_COUNT_HW_CACHE_REFERENCES PERF_COUNT_SW_EMULATION_FAULTS PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_CONTEXT_SWITCHES PERF_COUNT_HW_CACHE_OP_PREFETCH PERF_COUNT_HW_CACHE_RESULT_ACCESS PERF_COUNT_HW_CACHE_RESULT_MISS { sample_period, sample_freq } { wakeup_events, wakeup_watermark } ERROR: switch-%s event not found (%s) HINT: use 'perf evlist' to see the available event names failed to mmap perf event ring buffer, error %d failed to alloc mmap affinity mask, error %d failed to init mmap compressor, error %d failed to mmap data buffer, error %d failed to allocate aiocb for data buffer, error %m failed to allocate cblocks for data buffer, error %m failed to allocate data buffer, error %m failed to allocate data buffer area, error %m Failed to allocate node mask for mbind: error %m Failed to bind [%p-%p] AIO buffer to node %lu: error %m invalid or unsupported event: WARNING: failed to set leader: empty list WARNING: event parser found nothing WARNING: events were regrouped to match PMUs WARNING: failed to provide error string or struct Failed to allocate memory for event parsing error: %s (%s) Weak modifier is for use with groups Maximum combined precise value is 3, adding precision to "%s" --filter option should follow a -e tracepoint or HW tracer option not enough memory to hold filter string --exclude-perf option should follow a -e tracepoint option '%s' is not usable in 'perf stat' Failed to find PMU for type %d ..after resolving event: %s/%s/ Unable to find PMU or event on a PMU of '%s' valid terms: call-graph,stack-size Error: failed to open tracing events directory Failed to allocate new strlist for SDT Failed to allocate new strlist for symbol events Fail to find IP register for arch %s, returns 0 Fail to find SP register for arch %s, returns 0 Couldn't bump rlimit(MEMLOCK), failures may take place when creating BPF maps, etc this should not happen, your vsnprintf is broken ............................................................................................................................................................................................................... --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PerfTop:%8.0f irqs/sec kernel:%4.1f%% exact: %4.1f%% lost: %lu/%lu drop: %lu/%lu [ PerfTop:%8.0f irqs/sec kernel:%4.1f%% us:%4.1f%% guest kernel:%4.1f%% guest us:%4.1f%% exact: %4.1f%% [ Internal error: passing unmasked cpumode (%x) to is_kernel_module Failed to check whether %s is a kernel module or not. Assume it is. DSO data fd counter out of bounds. DSO %s is still in rbtree when being deleted! %s/sys/module/%.*s/notes/.note.gnu.build-id Internal tools/perf/ library error acpi_processor_ffh_cstate_enter mwait_idle_with_hints.constprop.0 %s/proc/{kallsyms,modules} inconsistency while looking for "%s" module! Failed to open %s. Note /proc/kcore requires CAP_SYS_RAWIO capability to access. Using %s for kernel object code Looking at the vmlinux_path (%d entries long) No kallsyms or vmlinux with build-id %s was found Annotation needs to be init before symbol__init() '.' is the only non valid --field-separator argument /proc/sys/kernel/kptr_restrict /usr/lib/debug/boot/vmlinux-%s /usr/lib/debug/lib/modules/%s/vmlinux /usr/lib/debug/boot/vmlinux-%s.debug Bad metric-id encoding in: '%s' Cannot find metric or group `%s' Try disabling the NMI watchdog to comply NO_NMI_WATCHDOG metric constraint: echo 0 > /proc/sys/kernel/nmi_watchdog perf stat ... echo 1 > /proc/sys/kernel/nmi_watchdog Events in '%s' fully contained within '%s' Cannot resolve IDs for %s: %s failed: recursion detected for %s Not grouping metric %s's events. Use hardware aware grouping instead of traditional metric grouping method copying metric event for cgroup '%s': %s (idx=%d) devices/system/cpu/cpu%d/cache/index%d/ # compressed : %s, level = %d, ratio = %d # directory data version : %lu # contains AUX area data (e.g. instruction trace) # contains samples with branch stack # CPU %d: Core ID %d, Die ID %d, Socket ID %d # Core ID, Die ID and Socket ID information is not available # CPU %d: Core ID %d, Socket ID %d # Core ID and Socket ID information is not available # memory nodes (nr %d, block size 0x%llx): # sample duration : %10.3f ms # pmu mappings: not available # pmu mappings: unable to read # node%u meminfo : total = %lu kB, free = %lu kB Failed to lseek to %lu offset for feature %d, continuing... # %s info available, use -I to display unknown feature %d, continuing... Error: calling %s in pipe-mode. failed to write buildid table cannot find event format for %d # %s pmu capabilities: not available # reference time: %s = %ld.%06d (TOD) = %ld.%09ld (%s) Failed to process auxtrace index Failed to write auxtrace index Pipe ABI%d perf.data file detected ABI%d perf.data file detected, need_swap=%d build id event received for %s: %s [%zu] Failed to read buildids, continuing... %s: couldn't read %s, does this arch have topology information? Failed to write MEM_TOPOLOGY, size %zd nodes %s/devices/system/node/node%lu failed: can't open memory sysfs data # AMD systems uses ibs_op// PMU for some precise events, e.g.: cycles:p, see the 'perf list' man page for further details. cpu pmu capabilities not available pmu capabilities not available %s pmu capabilities not available interpreting btf from systems with endianness is not yet supported interpreting bpf_prog_info from systems with endianness is not yet supported detected invalid bpf_prog_info Reserved bits are set unexpectedly. Please update perf tool. Unknown sample type (0x%llx) is detected. Please update perf tool. Unknown read format (0x%llx) is detected. Please update perf tool. Unknown branch sample type (0x%llx) is detected. Please update perf tool. # event desc: not available or unable to read socket_id number is too big.You may need to upgrade the perf tool. devices/system/memory/block_size_bytes failed to write perf header attribute failed to write feature section Invalid regular expression %s /sys/devices/system/cpu/cpu%d/online devices/system/cpu/cpu%d/online failed to write perf pipe header In-place update not supported when byte-swapping is required WARNING: The %s file's data size field is 0 which is unexpected. Was the 'perf record' command properly terminated? ERROR: The %s file's attr size field is 0 which is unexpected. Was the 'perf record' command properly terminated? cannot read %d bytes of header attr file uses a more recent and unsupported ABI (%zu bytes extra) invalid record type %d in pipe-mode failed to get event_update cpus %s: repiping tracing data padding %s: tracing data size mismatch not enough memory to create child for code path tree Warning: empty node in callchain tree not enough memory for the code path tree not enough memory for the code path branch statistics callchain cursor creation failed callchain: Incorrect stack dump size (max %ld): %s callchain: No more arguments needed for --call-graph lbr callchain: Unknown --call-graph option value: %s Invalid callchain sort key: %s Invalid callchain threshold: %s Invalid callchain print limit: %s Can't register callchain params failed to allocate read_values threads arrays failed to allocate read_values counters arrays failed to enlarge read_values threads arrays failed to allocate read_values counters array failed to enlarge read_values rawid array failed to enlarge read_values ->values array INTERNAL ERROR: Failed to allocate counterwidth array . ... raw event: size %d bytes invalid callchain context: %ld Problems setting modules path maps, continuing anyway... Discarding thread maps for %d:%d Failed to join map groups for %d:%d problem inserting idle task for machine pid %d problem processing PERF_RECORD_COMM, skipping event. WARNING: kernel seems to support more namespaces than perf tool. Try updating the perf tool.. WARNING: perf tool seems to support more namespaces than the kernel. Try updating the kernel.. problem processing PERF_RECORD_NAMESPACES, skipping event. %s: unsupported cpumode - ignoring Failed to write kernel text poke at %#llx Failed to find kernel text poke address map for %#llx Added extra kernel map %s %lx-%lx Problems creating module maps, continuing anyway... Problems creating module maps for guest %d, continuing anyway... Problems creating extra kernel maps, continuing anyway... invalid directory (%s). Skipping. removing erroneous parent thread %d/%d problem processing PERF_RECORD_FORK, skipping event. Failed to allocate space for stitched LBRs. Disable LBR stitch corrupted branch chain. skipping... problem processing PERF_RECORD_MMAP2, skipping event. problem processing PERF_RECORD_MMAP, skipping event. %.*s/platforms/%.*s/arch-%s/usr/lib/%s %.*s was updated (is prelink enabled?). Restart the long running apps that use it! no symbols found in %s, maybe install a debug package? Internal error: map__kmap with a non-kernel map Internal error: map__kmaps with a non-kernel map Internal error: kernel dso with non kernel map overlapping maps in %s (disable tui for more info) Couldn't allocate memory for decompression Reloading kvm_intel module with vmm_exclusive=0 will reduce the gaps to only guest's timeslices. Processed %d events and lost %d chunks! Check IO/CPU overload! Processed %lu samples and lost %3.2f%%! AUX data lost %lu times out of %u! module/kvm_intel/parameters/vmm_exclusive AUX data had gaps in it %lu times out of %u! Are you running a KVM guest in the background?%s AUX data detected collision %lu times out of %u! Found %u unknown events! Is this an older tool processing a perf.data file generated by a more recent tool? If that is not the case, consider reporting to linux-kernel@vger.kernel.org. %u samples with id not present in the header Found invalid callchains! %u out of %u events were discarded for this reason. Consider reporting to linux-kernel@vger.kernel.org. %u unprocessable samples recorded. Do you have a KVM guest running and not using 'perf kvm'? %u out of order events recorded. %d map information files for pre-existing threads were not processed, if there are samples for addresses they will not be resolved, you may find out which are these threads by running with -v and redirecting the output to a file. The time limit to process proc map is too short? Increase it by --proc-map-timeout cpu_map swap: unsupported long size ... %s regs: mask 0x%lx ABI %s incompatible file format (rerun with -v to learn more) WARNING: No sample_id_all support, falling back to unordered processing (IP, 0x%x): %d/%d: %#lx period: %lu addr: %#lx ..... %2lu: %016lx ..... %2lu: %016lx ..... %2lu: %016lx -> %016lx %hu cycles %s%s%s%s %x %s %s ... branch stack counters: nr:%lu (counter width: %u max counter nr:%u) ... ustack: size %lu, offset 0x%x %s: head=%#lx event->header.size=%#x, mmap_size=%#zx: fuzzed or compressed perf.data? %#lx [%#x]: failed to process type: %d %#lx [%#x]: failed to process type: %d [%s] failed to allocate memory to read event unexpected end of event stream No trace sample to read. Did you call 'perf %s'? (excludes AUX area (e.g. instruction trace) decoded / synthesized events) File does not contain CPU events. Remove -C option to proceed. Requested CPU %d too large. Consider raising MAX_NR_CPUS Invalid counter set entry at %zd Invalid counter set data encountered [%#08zx] Trailer:%c%c%c%c%c Cfvn:%d Csvn:%d Speed:%d TOD:%#llx 1:%lx 2:%lx 3:%lx TOD-Base:%#llx Type:%x [%#08zx] Counterset:%d Counters:%d Counter:%03d %s Value:%#018lx Invalid %s raw data encountered Invalid raw IBS Fetch MSR data encountered L3MissOnly %d FetchOcMiss %d FetchL3Miss %d ibs_fetch_ctl: %016llx MaxCnt %7d Cnt %7d Lat %5d En %d Val %d Comp %d%s PhyAddrValid %d%s L1TlbMiss %d L2TlbMiss %d RandEn %d%s%s ic_ibs_ext_ctl: %016llx IbsItlbRefillLat %3d ibs_op_ctl: %016llx MaxCnt %9d%s En %d Val %d CntCtl %d=%s CurCnt %9d ibs_op_data: %016llx CompToRetCtr %5d TagToRetCtr %5d%s%s%s BrnRet %d RipInvalid %d BrnFuse %d Microcode %d ibs_op_data2: %016llx %sRmtNode %d%s ibs_op_data3: %016llx LdOp %d StOp %d DcL1TlbMiss %d DcL2TlbMiss %d DcL1TlbHit2M %d DcL1TlbHit1G %d DcL2TlbHit2M %d DcMiss %d DcMisAcc %d DcWcMemAcc %d DcUcMemAcc %d DcLockedOp %d DcMissNoMabAlloc %d DcLinAddrValid %d DcPhyAddrValid %d DcL2TlbHit1G %d%s SwPf %d%s%s DcMissLat %5d TlbRefillLat %5d Invalid raw IBS Op MSR data encountered DataSrc 1=Local L3 or other L1/L2 in CCX DataSrc 2=Another CCX cache in the same NUMA node DataSrc 5=Another CCX cache in a different NUMA node DataSrc 7=MMIO/Config/PCI/APIC DataSrc 12=Coherent Memory of a different processor type next_flush - ordered_events__flush PRE %s, nr_events %u Processing time ordered events... next_flush - ordered_events__flush POST %s, nr_events %u last flush, last_flush_type %d alloc size %luB (+%zu), max %luB allocation limit reached %luB broken map groups on thread %d/%d parent %d/%d scandir for %d returned empty, skipping Couldn't resolve comm name for pid %d yyset_lineno called with no buffer yyset_column called with no buffer out of dynamic memory in yy_create_buffer() out of dynamic memory in yyensure_buffer_stack() out of dynamic memory in yy_scan_buffer() out of dynamic memory in yy_scan_bytes() out of dynamic memory in yylex() flex scanner push-back overflow fatal flex scanner internal error--end of buffer missed input buffer overflow, can't enlarge buffer because scanner uses REJECT out of dynamic memory in yy_get_next_buffer() fatal flex scanner internal error--no action found Unable to find event on a PMU of '%s' WARNING: event '%s' not valid (bits %s of %s '%llx' not supported by kernel)! alias %s differs in field '%s' ('%s' != '%s') WARNING: '%s' format '%s' requires 'perf_event_attr::config%d'which is not supported by this version of perf! unknown term '%s' for pmu '%s' Required parameter '%s' not specified value too big for format (%s), maximum is %llu Attempt to set event's unit twice Attempt to set event's scale twice Attempt to set event snapshot twice Failure to set up any core PMUs FATAL: not enough memory to print PMU events (see 'man perf-list' or 'man perf-record' on how to encode it) fatal error - scanner input buffer overflow <?xml version="1.0" standalone="no"?> <!DOCTYPE svg SYSTEM "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd"> <svg width="%i" height="%lu" version="1.1" xmlns="http://www.w3.org/2000/svg"> <defs> <style type="text/css"> <![CDATA[ rect { stroke-width: 1; } rect.process { fill:rgb(180,180,180); fill-opacity:0.9; stroke-width:1; stroke:rgb( 0, 0, 0); } rect.process2 { fill:rgb(180,180,180); fill-opacity:0.9; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.process3 { fill:rgb(180,180,180); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.sample { fill:rgb( 0, 0,255); fill-opacity:0.8; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.sample_hi{ fill:rgb(255,128, 0); fill-opacity:0.8; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.error { fill:rgb(255, 0, 0); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.net { fill:rgb( 0,128, 0); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.disk { fill:rgb( 0, 0,255); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.sync { fill:rgb(128,128, 0); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.poll { fill:rgb( 0,128,128); fill-opacity:0.2; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.blocked { fill:rgb(255, 0, 0); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.waiting { fill:rgb(224,214, 0); fill-opacity:0.8; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.WAITING { fill:rgb(255,214, 48); fill-opacity:0.6; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.cpu { fill:rgb(192,192,192); fill-opacity:0.2; stroke-width:0.5; stroke:rgb(128,128,128); } rect.pstate { fill:rgb(128,128,128); fill-opacity:0.8; stroke-width:0; } rect.c1 { fill:rgb(255,214,214); fill-opacity:0.5; stroke-width:0; } rect.c2 { fill:rgb(255,172,172); fill-opacity:0.5; stroke-width:0; } rect.c3 { fill:rgb(255,130,130); fill-opacity:0.5; stroke-width:0; } rect.c4 { fill:rgb(255, 88, 88); fill-opacity:0.5; stroke-width:0; } rect.c5 { fill:rgb(255, 44, 44); fill-opacity:0.5; stroke-width:0; } rect.c6 { fill:rgb(255, 0, 0); fill-opacity:0.5; stroke-width:0; } line.pstate { stroke:rgb(255,255, 0); stroke-opacity:0.8; stroke-width:2; } <title>fd=%d error=%d merges=%d</title> <rect x="%.8f" width="%.8f" y="%.1f" height="%.1f" class="%s"/> <title>#%d blocked %s</title> <title>#%d running %s</title> <desc>Switched because: %s</desc> <text x="%.8f" y="%.8f" font-size="%.8fpt">%i</text> <g transform="translate(%.8f,%.8f)"> <title>#%d waiting %s</title> <rect x="0" width="%.8f" y="0" height="%.1f" class="%s"/> <text transform="rotate(90)" font-size="%.8fpt"> %s</text> <rect x="%.8f" width="%.8f" y="%.1f" height="%.1f" class="cpu"/> <text x="%.8f" y="%.8f">%s</text> /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies <text transform="translate(%.8f,%.8f)" font-size="1.25pt">%s</text> <title>%d %s running %s</title> <text transform="rotate(90)" font-size="%.8fpt">%s</text> <rect class="%s" x="%.8f" width="%.8f" y="%.1f" height="%.1f"/> <text x="%.8f" y="%.8f" font-size="%.8fpt">C%i</text> <line x1="%.8f" x2="%.8f" y1="%.1f" y2="%.1f" class="pstate"/> <text x="%.8f" y="%.8f" font-size="0.25pt">%s</text> <title>%s wakes up %s</title> <line x1="%.8f" y1="%.2f" x2="%.8f" y2="%.2f" style="stroke:rgb(32,255,32);stroke-width:0.009"/> <g transform="translate(%.8f,%.8f)"><text transform="rotate(90)" font-size="0.02pt">%s ></text></g> <g transform="translate(%.8f,%.8f)"><text transform="rotate(90)" font-size="0.02pt">%s <</text></g> <circle cx="%.8f" cy="%.2f" r = "0.01" style="fill:rgb(32,255,32)"/> <title>Wakeup from interrupt</title> <circle cx="%.8f" cy="%.2f" r = "0.01" style="fill:rgb(255,128,128)"/> <rect x="%i" width="%.8f" y="0" height="%.1f" class="%s"/> <text transform="translate(%.8f, %.8f)" font-size="%.8fpt">%s</text> <line x1="%.8f" y1="%.2f" x2="%.8f" y2="%lu" style="stroke:rgb(%i,%i,%i);stroke-width:%.3f"/> topology: can't parse siblings map No memory to alloc tracepoints list can't get tracing/events/header_page can't record header_page file can't get tracing/events/header_event can't record header_event file can't get tracing/events/ftrace can't get tracing/printk_formats can't get tracing/saved_cmdline Python scripting not supported. Install libpython and rebuild perf to enable it. For example: # apt-get install python-dev (ubuntu) # yum install python-devel (Fedora) etc. Perl scripting not supported. Install libperl and rebuild perf to enable it. For example: # apt-get install libperl-dev (ubuntu) # yum install 'perl(ExtUtils::Embed)' (Fedora) etc. Error registering Python script extension: disabling it Error registering Perl script extension: disabling it printk format with empty entry reading input file (size expected=%d received=%d) not a trace file (missing 'tracing' tag) '%s' event is ambiguous: it can be %s or %s Cannot find event field for %s.%s --fields weight shows the average value unlike in the --sort key. Not enough memory to set up --sort Not enough memory to setup sort keys Not enough memory to setup overhead keys The "dcacheline" --sort key needs to know the cacheline size and it couldn't be determined on this system Not enough memory to setup output fields Samples: %lu%c of event%s '%s',%s%sEvent count (approx.): %lu FATAL ERROR: Couldn't setup hists class kernel/perf_event_max_contexts_per_stack Open /proc/version_signature failed: %s Reading from /proc/version_signature failed: %s Parsing /proc/version_signature failed: %s Unable to get kernel version from /proc/version_signature '%s' Unable to get kernel version from uname '%s' WARNING: debuginfod support requested, but perf is not built with it devices/system/cpu/cpu%d/topology/%s %s/devices/system/cpu/possible sysfs path crossed PATH_MAX(%d) size Failed to read max cpus, using default of %d %s/devices/system/node/possible Failed to read max nodes, using default of %d cpu_map__new_data unknown type %d %s/devices/system/cpu/cpu%d/topology/die_cpus_list %s/devices/system/cpu/cpu%d/topology/package_cpus_list %s/devices/system/cpu/cpu%d/topology/core_siblings_list %s/devices/system/cpu/cpu%d/topology/core_cpus_list %s/devices/system/cpu/cpu%d/topology/thread_siblings_list %s/devices/system/node/node%d/meminfo %s/devices/system/node/node%d/cpulist must define events before cgroups PID/TID switch overriding SYSTEM SYSTEM/CPU switch overriding PER-THREAD Problems obtaining information for user %s failed to read per-pkg counter Unmatched aggregation mode between aliases Failed to resolve counter for stat event. Failed to find perf count for CPU %d thread %d on event %s. ... id %llu, cpu %d, thread %d ... value %llu, enabled %llu, running %llu "core" : "S%d-D%d-C%d", "aggregate-number" : %d, "cache" : "S%d-D%d-L%d-ID%d", "aggregate-number" : %d, "cluster" : "S%d-D%d-CLS%d", "aggregate-number" : %d, "die" : "S%d-D%d", "aggregate-number" : %d, "socket" : "S%d", "aggregate-number" : %d, "node" : "N%d", "aggregate-number" : %d, "event-runtime" : %lu, "pcnt-running" : %.2f, Performance counter stats for Cannot allocate per-core aggr map for display %*s# Table of individual measurements: %17.*f +- %.*f seconds time elapsed Some events weren't counted. Try disabling the NMI watchdog: echo 0 > /proc/sys/kernel/nmi_watchdog perf stat ... echo 1 > /proc/sys/kernel/nmi_watchdog The events in group usually have to be from the same PMU. Try reorganizing the group. cannot set frequency and period at the same time frequency and count are zero, aborting error: Maximum frequency rate (%'u Hz) exceeded. Please use -F freq option with a lower value or consider tweaking /proc/sys/kernel/perf_event_max_sample_rate. warning: Maximum frequency rate (%'u Hz) exceeded, throttling from %'u Hz to %'u Hz. The limit can be raised via /proc/sys/kernel/perf_event_max_sample_rate. The kernel will lower it when perf's interrupts take too long. Use --strict-freq to disable this throttling, refusing to record. Lowering default frequency rate from %u to %u. Please consider tweaking /proc/sys/kernel/perf_event_max_sample_rate. couldn't read /proc/sys/kernel/perf_event_max_sample_rate info: Using a maximum frequency rate of %'d Hz %s %s: addr2line read address for sentinel: %s %s %s: addr2line read line: %s %s %s: addr2line filename:number : %s addr2line missing ':' in filename split Failed to allocate memory for addr2line could not start addr2line (%s) for %s: start_command return code %d %s %s: addr2line_subprocess_init failed Detected LLVM addr2line style Detected binutils addr2line style %s %s: addr2line configuration failed Unknown/broken addr2line style %s %s: could not send request %s %s: could not read first record %s %s: could not read sentinel record %s %s: unexpected record instead of sentinel not enough memory for the srcline node not enough memory for the inline node Failed to read build ID for %s Couldn't get COMM, tigd and ppid for pid %d Name: string not found for pid %d Tgid: string not found for pid %d PPid: string not found for pid %d Reading %s/proc/%d/task/%d/maps time out. You may want to increase the time limit by --proc-map-timeout cannot find cgroup mount point Not enough memory synthesizing mmap event for kernel modules Perf runs in non-root PID namespace but it tries to gather process info from its parent PID namespace. Please mount the proc file system properly, e.g. add the option '--mount-proc' for unshare command. Couldn't synthesize evsel unit. Couldn't synthesize evsel evsel. Couldn't synthesize evsel cpus. Couldn't synthesize evsel name. failed to create perf header attribute Couldn't synthesize thread map. No record header feature for header :%d Couldn't synthesize features. Couldn't record tracing data. Can't remove old data: %s (%s) Can't move data: %s (%s to %s) File %s not owned by current user or root (use -f to override) zero-sized data (%s), nothing to do! failed to get perf_event_mmap_page lock Synthesizing TSC conversion information perf_event_open(..., PERF_FLAG_FD_CLOEXEC) failed with unexpected error %d (%s) perf_event_open(..., 0) failed unexpectedly with error %d (%s) Out of memory: no thread stack Out of memory: discarding thread stack iostat mode is not supported on current platform [ Hot streams in old perf data only ] [ Hot streams in new perf data only ] Multiple symbols with name '%s' Disambiguate symbol name by inserting #n after the name e.g. %s #2 Or select a global symbol by inserting #0 or #g or #G N'th occurrence (N=%d) of symbol '%s' not found. Global symbol '%s' not found. Note that symbols must be functions. Failed to parse /proc/kallsyms Multiple kernel symbols with name '%s' AUX area tracing is not supported on this architecture auxtrace idx %d old %#lx head %#lx diff %#lx No AUX area tracing to snapshot Bad AUX area sampling option: '%s' Cannot add AUX area sampling to an AUX area event Cannot add AUX area sampling to a group leader AUX area sample size %u too big, max. %d Cannot add AUX area sampling because group leader is not an AUX area event AUX area sampling requires an AUX area event group leader plus other events to which to add samples AUX area sampling is not supported by kernel Synthesizing auxtrace information size: %#llx offset: %#llx ref: %#llx idx: %u tid: %d cpu: %d Bad Instruction Tracing options '%s' cpu %d pid %d tid %d ip %#llx code %u: %s Error: number of address filters (%d) exceeds maximum (%d) Kernel addresses are restricted. Unable to resolve kernel symbols. Symbol '%s' (0x%lx) comes before '%s' (0x%lx) Symbol '%s' (0x%lx) comes before address 0x%lx) Cannot determine size of symbol '%s' Failed to load symbols from: %s File '%s' not found or has no symbols. Failed to determine filter for %s Cannot determine file size. Failed to parse address filter: '%s' Filter format is: filter|start|stop|tracestop <start symbol or address> [/ <end symbol or size>] [@<file name>] Where multiple filters are separated by space or comma. %s 0x%llx Hints 0x%x Extensions 0x%x %s 0x%llx HW:%u CState:%u Sub-CState:%u %s 0x%llx Last CState:%u Deepest CState:%u Wake Reason 0x%x %s IP:%d Type 0x%02x Vector 0x%llx Suppressing CYC timestamp 0x%lx less than current timestamp 0x%lx CTC timestamp 0x%lx last MTC %#x CTC rem %#x Timestamp: calculated %g TSC ticks per cycle too big (c.f. CBR-based value %g), pos 0x%lx Timestamp: calculated %g TSC ticks per cycle c.f. CBR-based value %g, pos 0x%lx Timestamp: calculated %g TSC ticks per cycle c.f. unknown CBR-based value, pos 0x%lx ERROR: Failed to get instruction ERROR: Conditional branch when expecting indirect branch ERROR: Unexpected branch at FUP instruction ERROR: Unexpected indirect branch ERROR: Unexpected conditional branch Buffer 1st timestamp 0x%lx ref timestamp 0x%lx Suppressing MTC timestamp 0x%lx less than current timestamp 0x%lx Suppressing backwards timestamp ERROR: RET when expecting conditional branch ERROR: Bad RET compression (stack empty) ERROR: Bad RET compression (TNT=N) ERROR: Missing deferred TIP for indirect branch ERROR: Missing FUP after MODE.TSX ERROR: Missing FUP after PTWRITE ERROR: Missing FUP after EXSTOP WARNING: Unknown block type %u WARNING: Duplicate block type %u WARNING: Unknown block item %u type %d WARNING: Duplicate block item %u type %d timestamp: tsc_ctc_ratio_n %u timestamp: tsc_ctc_ratio_d %u Hop mode: decoding FUP and TIPs, but not TNT ERROR: First TSC is not in PSB+ Translated VM TSC %#lx -> %#lx VMCS %#lx TSC Offset %#lx ERROR: First TSC, unknown TSC Offset ERROR: First TSC, no PIP, unknown TSC Offset %s: intel_pt_ctc_to_tsc(decoder, new_ctc_delta) %#lx ERROR: Unknown TSC Offset for VMCS %#lx Fast forward towards timestamp 0x%lx Fast forward to next PSB timestamp 0x%lx Trace doesn't match instruction Never-ending loop (refer perf config intel-pt.max-loops) TIP.PGD ip %#lx offset %#lx in %s hit filter: %s offset %#lx size %#lx TIP.PGD ip %#lx offset %#lx in %s is not in a filter region Intel Processor Trace: failed to deliver error event, error %d Intel PT: failed to deliver event, error %d . ... Intel Processor Trace data: size %zu bytes ERROR: cpu %d expecting switch ip ERROR: guest sideband but no guest machine ERROR: thread has no dso for %#lx ERROR: thread has no map for %#lx ERROR: failed to read at offset %#lx Emulated ptwrite signature found Emulated ptwrite signature not found queue %u decoding cpu %d pid %d tid %d PEBS-via-PT record with no applicable_counters PEBS-via-PT record with no matching event, hw_id %d queue %u processing 0x%lx to 0x%lx Intel Processor Trace requires ordered events queue %u cpu %d pid %d tid %d sched_switch: cpu %d tid %d time %lu tsc %#lx itrace_start: cpu %d pid %d tid %d time %lu tsc %#lx Expecting CPU-wide context switch event context_switch event has no tid Invalidated instruction cache for %s at %#lx event %u: cpu %d time %lu tsc %#lx There are no selected events with Intel Processor Trace data Synthesizing '%s' event with id %lu sample type %#lx %s: failed to synthesize '%s' event type %s: filter string not null terminated Intel PT has no time information for VM Time Correlation Time ranges cannot be specified with VM Time Correlation MTC packets must have been enabled for VM Time Correlation Failed to parse VM Time Correlation options %s: missing sched_switch event %s: missing context_switch attribute flag range %d: perf time interval: %lu to %lu range %d: TSC time interval: %#lx to %#lx WARNING: Intel PT with pipe mode is not recommended. The output cannot relied upon. In particular, timestamps and the order of events may be incorrect. Intel PT decoding without timestamps Intel BTS: failed to deliver error event, error %d Intel BTS: failed to deliver branch event, error %d There are no selected events with Intel BTS data Synthesizing 'branches' event with id %lu sample type %#lx %s: failed to synthesize 'branches' event type Intel BTS requires ordered events . ... Intel BTS data: size %zu bytes ARM SPE: failed to deliver event, error %d . ... ARM SPE data: size %#zx bytes No data or all data has been processed. SPE trace requires ordered events Arm SPE CONTEXT packets not found in the traces. Matching of TIDs to SPE events could be inaccurate. No selected events with SPE trace data Only instruction-based sampling period is currently supported by Arm SPE. Arm SPE has a hardware-based sample period. Additional instruction events will be discarded by --itrace ignoring unsupported address packet index: 0x%x . ... HISI PTT data: size %zu bytes %s %x %s %x %s %x %s %x %s %x %s %x %s %x %s %x %s pos:%#zx ip:%#lx P:%d CL:%d pid:%d.%d cpumode:%d cpu:%d s390 Auxiliary Trace: failed to deliver event Failed to find auxtrace log directory %s, continue with current directory... Missing auxtrace log directory %s, continue with current directory... s390 Auxiliary Trace: failed to deliver error event,error %d . ... s390 AUX data: size %zu bytes Invalid AUX trace data block size:%zu (type:%d bsdes:%hd dsdes:%hd) Invalid AUX trace basic entry [%#08zx] [%#08zx] Basic Def:%04x Inst:%#04x %c%c%c%c AS:%d ASN:%#04x IA:%#018llx CL:%d HPP:%#018llx GPP:%#018llx Invalid AUX trace diagnostic entry [%#08zx] [%#08zx] Diag Def:%04x %c Invalid AUX trace trailer entry [%#08zx] [%#08zx] Trailer %c%c%c bsdes:%d dsdes:%d Overflow:%lld Time:%#llx C:%d TOD:%#lx s390 Auxiliary Trace requires ordered events Failed to open counter set log file %s, continue... Failed to write counter set data Failed to open auxiliary log file %s,continue... Failed to write auxiliary data %s queue_nr:%d buffer:%ld offset:%#lx size:%#zx rest:%#zx [%#08lx] Invalid AUX trailer entry TOD clock base Unsupported --itrace options specified CS ETM Trace: Unknown Header Version = %#lx Magic number Unknown %lx Unknown parameter [%d] %lx CS ETM Trace: OpenCSD is not linked in, please recompile with CORESIGHT=1 TRCDEVARCH %llx TS_SOURCE %lld PMU type/num cpus %llx unknown branch filter %s, check man page Error: Can't use --branch-any (-b) with --branch-filter (-j). Unknown register "%s", check man page or run "perf record %s?" ERROR: Failed to allocate command list for unknown command. WARNING: You called a perf program named '%s', which does not exist. Continuing under the assumption that you meant '%s' in %0.1f seconds automatically... perf: '%s' is not a perf-command. See 'perf --help'. %s/bus/event_source/devices/%s/events/%s failed: event '%s' not found, use '-e list' to get list of available events failed: event '%s' not supported Memory events are enabled on a subset of CPUs: %s HINT: no first/last sample time found in perf data. Please use latest perf binary to execute 'perf record' (if '--buildid-all' is enabled, please set '--timestamp-boundary'). lookup(%s): ref metric name %s processing metric: %s EXIT: %f lookup(%s): ref val %f metric name %s No memory nodes, is CONFIG_MEMORY_HOTPLUG enabled? mem2node %03lu [0x%016lx-0x%016lx] WARNING: Failed to determine specified clock resolution. unknown clockid %s, check man page Missing PLT entry size for %s %s: problems reading %s PLT info. Failed to decompress (error %d) %s %s: truncating reading of build id in sysfs file %s: n_namesz=%u, n_descsz=%u. unrecognized DSO data encoding %d %s: build id mismatch for %s. %s: failed to find program header for symbol: %s st_value: %#lx %s: adjusting symbol: st_value: %#lx sh_addr: %#lx sh_offset: %#lx %s: adjusting symbol: st_value: %#lx p_vaddr: %#lx p_offset: %#lx Failed to get build-id from %s. Failed to add build-id cache: %s strlist__add failed with -ENOMEM run this command again with sudo. try 'sudo mount -o remount,mode=755 /sys/kernel/tracing/' No permission to %s tracefs. Please %s Debugfs or tracefs is not mounted Please try 'sudo mount -t tracefs nodev /sys/kernel/tracing/' %s/%s does not exist. Please rebuild kernel with %s. Failed to open %s/%cprobe_events: %s CONFIG_KPROBE_EVENTS=y and CONFIG_UPROBE_EVENTS=y Failed to open %s/kprobe_events: %s. Failed to open %s/uprobe_events: %s. Failed to synthesize probe trace event. Internal error: %s should have ':' but not. Failed to get a valid sdt type Module %s is not loaded, please specify its full path name. Failed to find the path for the kernel: %s Rebuild with CONFIG_DEBUG_INFO=y, or install an appropriate debuginfo package. The %s file has no debug information. %s is blacklisted function, skip it. Semantic error :%s is bad for event name -it must follow C symbol-naming rule. snprintf() failed: %d; the event name nbase='%s' is too long Error: event "%s" already exists. Hint: Remove existing event by 'perf probe -d' or force duplicates by 'perf probe -f' or set 'force=yes' in BPF source. Internal error: "%s" is an invalid event name. Too many events are on the same function. Warning: The probe function (%s) is a GNU indirect function. Consider identifying the final function used at run time and set the probe directly on that. Symbol %s address found : %lx Specified source line is not found. Failed to find source file path. Source file is shorter than expected. Failed to find the address of %s Semantic error :'%s' is not a valid number. Semantic error :Start line must be smaller than end line. Semantic error :Tailing with invalid str '%s'. Semantic error :'%s' is not a valid function name. Semantic error :Too many probe arguments (%d). Semantic error :%s must be an SDT name. Semantic error :Invalid absolute address. Semantic error :There is non-digit char in line number. Semantic error :There is non-digit character in offset. Semantic error :SRC@SRC is not allowed. Semantic error :%%%s is not supported. This program has a bug at %s:%d. Semantic error :Lazy pattern can't be used with line number. Semantic error :Lazy pattern can't be used with offset. Semantic error :Offset can't be used with line number. Semantic error :File always requires line number or lazy pattern. Semantic error :Offset requires an entry function. Semantic error :Offset/Line/Lazy pattern can't be used with return probe. symbol:%s file:%s line:%d offset:%lu return:%d lazy:%s Semantic error :ftrace does not support user access Semantic error :Array index must be a number. Semantic error :Argument parse error: %s Semantic error :You can't specify local variable for kretprobe. Semantic error :Too few probe arguments. Semantic error :Failed to parse event name: %s try to find information at %lx in %s Failed to find corresponding probes from debuginfo. Failed to find probe point from both of dwarf and map. WARN: Group name %s is ignored ERROR: Bootconfig doesn't support uprobes %sftrace.event.kprobes.%s.probe = Failed to get current event list. A semaphore is associated with %s:%s and seems your kernel doesn't support it. %s accesses a variable by symbol name, but that is not supported for user application probe. Please upgrade your kernel to at least 3.14 to have access to feature %s Failed to add event to probe cache Failed to find symbols matched to "%s" No kprobe blacklist support, ignored Too many entries matched in the cache of %s Could not open debuginfo. Try to use symbols. Try to find probe point from debuginfo. Failed to get ELF symbols for %s Relocated base symbol is not found! Check /proc/sys/kernel/kptr_restrict and /proc/sys/kernel/perf_event_paranoid. Or run as privileged perf user. Post processing failed or all events are skipped. (%d) An error occurred in debuginfo analysis (%d). Warning: No dwarf info found in the vmlinux - please rebuild kernel with CONFIG_DEBUG_INFO=y. Failed to load symbols from %s Please ensure the file is not stripped. Please ensure you can read the /proc/kallsyms symbol addresses. If /proc/sys/kernel/kptr_restrict is '2', you can not read kernel symbol addresses even if you are a superuser. Please change it to '1'. If kptr_restrict is '1', the superuser can read the symbol addresses. In that case, please run this command again with sudo. Failed to find symbol %s in %s Too many functions matched in %s Found duplicated symbol %s @ %lx Too many symbols are listed. Skip it. Offset %ld is bigger than the size of %s Specified offset is out of %s Failed to find symbol at 0x%lx Failed to find "%s%%return", because %s is an inlined function and has no return point. Mapping for the register number %u missing on this architecture. Failed to get the type of %s. Semantic error: %s must be referred by '->' %s is not a data structure nor a union. Semantic error: %s is not a pointer nor array. Semantic error: %s must be referred by '.' Structure on a register is not supported yet. %s(type:%s) has no member %s. Failed to get the offset of %s. Too many( > %d) probe point found. Searching '%s' variable in context. Failed to find '%s' in this function. Converting variable %s into trace event. Failed to find the location of the '%s' variable at this address. Perhaps it has been optimized out. Use -V with the --range option to show '%s' location range. Sorry, we don't support this variable location yet. Failed to get a type information of %s. Failed to cast into string: %s(%s) is not a pointer nor array. Failed to get a type information. Failed to cast into string: %s is not (unsigned) char *. %s exceeds max-bitwidth. Cut down to %d bits. Failed to convert variable type: %s Caller must pass a scope DIE. Program error. Failed to find probe point in any functions. Failed to get call frame on 0x%jx Probe line found: line:%d addr:0x%llx Failed to find scope of probe point. This line is sharing the address with other lines. Please try to probe at %s:%d instead. Failed to find debug information for address %#lx No matched lines found in %s. A function DIE doesn't have decl_line. Maybe broken DWARF? Target program is compiled without optimization. Skipping prologue. Probe on address 0x%lx to force probing at the function entry. Failed to get entry address of %s. %s has no valid entry address. skipped. Unable to get offset:Unexpected OP %x (%zd) Failed to get the declared file name of %s Failed to get CU from given DIE. Failed to get source lines on this CU. Failed to get line info. Possible error in debuginfo. Failed to get type, make it unknown. ELF MACHINE %x is not supported. offset: %d is bigger than size: %lu unknown: code=%#x, number=%#lx type='%s' size=%#lx (die:%#lx) ----------------------------------------------------------- find data type for %#x(%s) at %s+%#lx cannot find CU for address %lx found by addr=%#lx type_offset=%#x found "%s" in scope=%d/%d (die: %#lx) stack_offset=%#x type_offset=%#x check variable "%s" failed (die: %#lx) cannot find a basic block from %lx to %lx prepend basic blocks: mismatched disasm line %lx -> %lx chk [%x] reg%d offset=%#x ok=%d kind=%d mov [%x] stack canary -> reg%d mov [%x] this-cpu addr=%#lx -> reg%d mov [%x] global addr=%lx -> reg%d mov [%x] percpu %#x(reg%d,reg%d) -> reg%d mov [%x] percpu %#x(reg%d) -> reg%d mov [%x] pointer %#x(reg%d) -> reg%d found by insn track: %#x(%s) type-offset=%#x Annotate type: '%s' in %s (%d samples): ============================================================================ unwind: get_proc_name unsupported unwind: access_fpreg unsupported unwind: put_unwind_info called unwind: Register unavailable. unwind: %s:ip = 0x%lx (0x%lx) unwind: access_mem %p not inside range 0x%lx-0x%lx unwind: access_mem addr %p val %lx, offset %d unwind: Can't create unwind address space. unwind: find_proc_info dso %s unwind: thread map already set, dso=%s unwind: target platform=%s is not supported --all is currently unsupported for JSON output. --tod is currently unsupported for JSON output. Output file exists. Use --force to overwrite it. Failed to get mtime of source file, not writing captured-on [ perf data convert: Converted '%s' into JSON data '%s' ] [ perf data convert: Converted and wrote %.3f MB (%lu samples) ] # perf script event handlers, generated by perf script -g python # Licensed under the terms of the GNU GPL License version 2 # The common_* event handler fields are the most useful fields common to # all events. They don't necessarily correspond to the 'common_*' fields # in the format files. Those fields not available as handler params can # be retrieved using Python functions of the form common_*(context). # See the perf-script-python Documentation for the list of available functions. from __future__ import print_function sys.path.append(os.environ['PERF_EXEC_PATH'] + \ '/scripts/python/Perf-Trace-Util/lib/Perf/Trace') from perf_trace_context import * print_header(event_name, common_cpu, common_secs, common_nsecs, common_pid, common_comm) print('Sample: {'+get_dict_as_string(perf_sample_dict['sample'], ', ')+'}') for node in common_callchain: print(" [%%x] %%s%%s%%s%%s" %% ( node['ip'], node['sym']['name'], "+0x{:x}".format(node['sym_off']) if 'sym_off' in node else "", " ({})".format(node['dso']) if 'dso' in node else "", " " + node['sym_srcline'] if 'sym_srcline' in node else "")) print(" [%%x]" %% (node['ip'])) def trace_unhandled(event_name, context, event_fields_dict, perf_sample_dict): print(get_dict_as_string(event_fields_dict)) def print_header(event_name, cpu, secs, nsecs, pid, comm): print("%%-20s %%5u %%05u.%%09u %%8u %%-20s " %% \ (event_name, cpu, secs, nsecs, pid, comm), end="") def get_dict_as_string(a_dict, delimiter=' '): return delimiter.join(['%%s=%%s'%%(k,str(v))for k,v in sorted(a_dict.items())]) problem in Python trace event handler couldn't create Python dictionary Failed to resolve callchain. Skipping Error running python script %s Error starting python script %s failed to create calls processor failed to create call path root Failed to setting regs in dict ug! no event found for type %lu Unsupported decompressor flags The input is not in the .xz format Compressed file is truncated or otherwise corrupt lzma: fopen failed on %s: '%s' lzma: lzma_stream_decoder failed %s (%d) Couldn't create compression stream. Failed to initialize compression stream: %s failed to compress %ld bytes: %s Couldn't create decompression stream. Failed to initialize decompression stream: %s failed to decompress (B): %zd -> %zd, dst_size %zd : %s demangle-rust: unexpected escape sequence demangle-rust: unexpected character '%c' in symbol problem processing JIT mmap event, skipping it. version=%u hdr.size=%u ts=0x%llx pid=%d elf_mach=%d use_arch_timestamp=%d wrong jitdump version %u, expected 1 jitdump file contains invalid or unsupported flags 0x%llx jitdump file uses arch timestamps but there is no timestamp conversion next_entry: unknown record type %d, skipping %s: thread %d not found or created error, jitted code must be sampled with perf record -k 1 Fatal error (SEGFAULT) in perf hook '%s' %s: failed to get BPF program info. aborting %s: failed to get BTF of id %u, aborting unexpected bpf event type of %d %s: can't get next program: %s%s %s: failed to get fd for prog_id %u %s: the kernel is too old, aborting %s: mismatch in BPF sub program count and BTF function info count, aborting %s: failed to synthesize bpf images: %s # bpf_prog_info %u: %s addr 0x%llx size %u # sub_prog %u: %s addr 0x%llx size %u %s: mismatch in element count binutils for %s not supported. Please install %s for %s. You can add it to PATH, set CROSS_COMPILE or override the default using --%s. Invalid CPUID %s. Full CPUID is required, vendor-family-model-stepping Failed to read /proc/cpuinfo for TSC frequency Failed to find TSC frequency in /proc/cpuinfo ^([+\-]?)([0-9]*)(\(?)(%[a-z][a-z0-9]+)(\)?)$ Skipping unsupported SDT argument: %s Not enough memory synthesizing mmap event for extra kernel maps {%s/mem-loads-aux/,%s/mem-loads,ldlat=%u/}:P WARNING: Hw internally resets sampling period when L3 Miss Filtering is enabled and tagged operation does not cause L3 Miss. This causes sampling period skew. AMD IBS doesn't support privilege filtering. Try again without the privilege modifiers (like 'k') at the end. %s/bus/event_source/devices/uncore_iio_%d bus/event_source/devices/uncore_iio_%d/die%d Invalid mapping data: iio_%d; die%d The -e and -M options are not supported.All chosen events/metrics will be dropped {uncore_iio_%x/event=0x83,umask=0x04,ch_mask=0xF,fc_mask=0x07/, uncore_iio_%x/event=0x83,umask=0x01,ch_mask=0xF,fc_mask=0x07/, uncore_iio_%x/event=0xc0,umask=0x04,ch_mask=0xF,fc_mask=0x07/, uncore_iio_%x/event=0xc0,umask=0x01,ch_mask=0xF,fc_mask=0x07/} Unsupported uncore pmu configuration ^([a-f0-9A-F]{1,}):([a-f0-9A-F]{1,2}) Root port %04x:%02x were not found Requested root ports were not found Unrecognized root port format: %s Please use the following format: [domain]:[bus] for example: 0000:3d # time port intel_pt and intel_bts may not be used together Invalid %s for %s. Valid values are: %s %s: mmap index %d old head %zu new head %zu %s: wrap-around %sdetected, adjusted old head %zu adjusted new head %zu Intel Processor Trace: TSC not available There may be only one intel_pt event module/kvm_intel/parameters/pt_mode Snapshot mode (-S option) requires intel_pt PMU event (-e intel_pt) Snapshot mode (intel_pt PMU) and sample trace cannot be used together Cannot use clockid (-k option) with intel_pt intel_pt supports at most one event with aux-output pt=0 doesn't make sense, forcing pt=1 Snapshot size %zu must not be greater than AUX area tracing mmap size %zu Failed to calculate default snapshot size and/or AUX area tracing mmap pages Intel PT snapshot size (%zu) may be too small for PSB period (%zu) Intel PT min. sample size: %zu max. sample size: %zu Sample size %zu must not be greater than AUX area tracing mmap size %zu Intel PT sample size (%zu) may be too small for PSB period (%zu) Invalid mmap size for Intel Processor Trace: must be at least %zuKiB and a power of 2 %s: failed to create %s, error = %d Unable to select sched:sched_switch Intel Processor Trace decoding will not be possible except for kernel tracing! Intel BTS does not support AUX area sampling There may be only one intel_bts event Snapshot mode (-S option) requires intel_bts PMU event (-e intel_bts) intel_bts does not support per-cpu recording Invalid mmap size for Intel BTS: must be at least %zuKiB and a power of 2 Get the common preempt count event field value. Get the common flags event field value. Get the common lock depth event field value. Get the machine code instruction. Get source file name and line number. Get source file name, line number and line. GenuineIntel-6-(97|9A|B7|BA|BF) GenuineIntel-6-(1C|26|27|35|36) GenuineIntel-6-55-[56789ABCDEF] GenuineIntel-6-(37|4A|4C|4D|5A) GenuineIntel-6-(4E|5E|8E|9E|A5|A6) AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]) AuthenticAMD-25-([245][[:xdigit:]]|[[:xdigit:]]) { type: context_switch, next_prev_pid: %u, next_prev_tid: %u, switch_out: %u } { type: lost, id: %#llx, lost: %#llx } { type: mmap, pid: %u, tid: %u, start: %#llx, length: %#llx, offset: %#llx, filename: %s } { type: read, pid: %u, tid: %u } { type: %sthrottle, time: %llu, id: %llu, stream_id: %llu } { type: %s, pid: %u, ppid: %u, tid: %u, ptid: %u, time: %llu} { type: comm, pid: %u, tid: %u, comm: %s } |iKiKKiiiiiiiiiiiiiiiiiiiiiiKK perf: can't parse sample, err=%d COUNT_HW_STALLED_CYCLES_FRONTEND COUNT_HW_STALLED_CYCLES_BACKEND mmap the file descriptor table. poll the file descriptor table. get the poll file descriptor table. adds an event selector to the list. open the event selector file descriptor table. is not availableis being ignored@B /tmp/perf-test-X d xV4 wUf3D" Z h i j k l m o q s t ާdY Sj xc d , X , X L d & : p L Sb Sb Sb Sb 1 ,1 4&k 4&k 1 -1 3&k 4&k 3|1 d3|1 3|1 3|1 3|1 3|1 3|1 3|1 3|1 3|1 Oh' dOh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' ZOh' dOh' Oh' Oh' Oh' Oh' YOh' eOh' {cycles,instruct @ test-prog Sort by index only available with group events! -F +brstackinsn with build id /tmp/perf-kmod-XPERFILE2h PERFILE2 /proc/self/ns/mn/tmp/perf-XXXXXX show reference e callgraph, Lost Auxiliary Trace Buffer /tmp/perf-kcore-perf_trace_conte libbpf: %s size (%zu) is too small libbpf: %s has non-zero extra bytes libbpf: failed to dup FD %d to FD > 2: %d cgroup_inet_ingress cgroup_inet_egress cgroup_inet_sock_create cgroup_sock_ops sk_skb_stream_parser sk_skb_stream_verdict cgroup_device sk_msg_verdict cgroup_inet4_bind cgroup_inet6_bind cgroup_inet4_connect cgroup_inet6_connect cgroup_inet4_post_bind cgroup_inet6_post_bind cgroup_udp4_sendmsg cgroup_udp6_sendmsg lirc_mode2 flow_dissector cgroup_sysctl cgroup_udp4_recvmsg cgroup_udp6_recvmsg cgroup_getsockopt cgroup_setsockopt trace_raw_tp trace_fentry trace_fexit modify_return lsm_mac trace_iter cgroup_inet4_getpeername cgroup_inet6_getpeername cgroup_inet4_getsockname cgroup_inet6_getsockname xdp_devmap cgroup_inet_sock_release xdp_cpumap sk_lookup xdp sk_skb_verdict sk_reuseport_select sk_reuseport_select_or_migrate perf_event trace_kprobe_multi lsm_cgroup struct_ops netfilter tcx_ingress tcx_egress trace_uprobe_multi cgroup_unix_connect cgroup_unix_sendmsg cgroup_unix_recvmsg cgroup_unix_getpeername cgroup_unix_getsockname netkit_primary netkit_peer trace_kprobe_session unspec raw_tracepoint tracing cgroup iter netns kprobe_multi tcx uprobe_multi netkit sockmap hash array prog_array perf_event_array percpu_hash percpu_array stack_trace cgroup_array lru_hash lru_percpu_hash lpm_trie array_of_maps hash_of_maps devmap cpumap xskmap sockhash cgroup_storage reuseport_sockarray percpu_cgroup_storage queue stack sk_storage devmap_hash ringbuf inode_storage task_storage bloom_filter user_ringbuf cgrp_storage arena socket_filter kprobe sched_cls sched_act tracepoint cgroup_skb cgroup_sock lwt_in lwt_out lwt_xmit sock_ops sk_skb sk_msg cgroup_sock_addr lwt_seg6local sk_reuseport raw_tracepoint_writable cgroup_sockopt ext lsm syscall LIBBPF_LOG_LEVEL warn debug info libbpf: unrecognized '%s' envvar value: '%s', should be one of 'warn', 'debug', or 'info'. %zu bytes %.1f KiB %.1f MiB libbpf: permission error while running as root; try raising 'ulimit -l'? current value: %s v1.5 libbpf: sec '%s': corrupted program '%s', offset %zu, size %zu libbpf: sec '%s': failed to allocate memory for prog '%s' libbpf: sec '%s': failed to get symbol name for offset %zu libbpf: sec '%s': program at offset %zu crosses section boundary libbpf: sec '%s': program '%s' is static and not supported libbpf: sec '%s': found program '%s' at insn offset %zu (%zu bytes), code size %zu insns (%zu bytes) libbpf: sec '%s': failed to alloc memory for new program '%s' %.*s libbpf: struct_ops init_kern: struct %s is not found in kernel BTF bpf_struct_ops_ libbpf: struct_ops init_kern: struct %s%s is not found in kernel BTF libbpf: struct_ops init_kern: struct %s data is not found in struct %s%s libbpf: struct_ops init_kern %s: type_id:%u kern_type_id:%u kern_vtype_id:%u libbpf: struct_ops init_kern %s: failed to resolve the size of member %s libbpf: struct_ops init_kern %s: Cannot find member %s in kernel BTF libbpf: struct_ops %s: member %s not found in kernel, skipping it as it's set to zero libbpf: struct_ops init_kern %s: bitfield %s is not supported libbpf: struct_ops init_kern %s: Unmatched member type %s %u != %u(kernel) libbpf: struct_ops init_kern %s: member %s is not a struct_ops program libbpf: struct_ops init_kern %s: kernel member %s is not a func ptr libbpf: struct_ops init_kern %s func ptr %s: invalid reuse of prog %s in sec %s with type %u: attach_btf_id %u != kern_type_id %u libbpf: struct_ops init_kern %s func ptr %s: invalid reuse of prog %s in sec %s with type %u: expected_attach_type %u != kern_member_idx %u libbpf: struct_ops init_kern %s: func ptr %s is set to prog %s from data(+%u) to kern_data(+%u) libbpf: struct_ops init_kern %s: Error in size of member %s: %zd != %zd(kernel) libbpf: struct_ops init_kern %s: copy %s %u bytes from data(+%u) to kern_data(+%u) libbpf: struct_ops init: DATASEC %s not found libbpf: struct_ops init: Cannot resolve var type_id %u in DATASEC %s libbpf: struct_ops init: anonymous type is not supported libbpf: struct_ops init: %s is not a struct .struct_ops.link libbpf: struct_ops init: var %s is beyond the end of DATASEC %s libbpf: struct_ops init: struct %s(type_id=%u) %s found at offset %u libbpf: alloc memory failed for %s libbpf: elf: init internal error libbpf: elf: failed to open %s: %s libbpf: elf: failed to open %s as ELF file: %s libbpf: elf: '%s' is not a proper ELF object libbpf: elf: '%s' is not a 64-bit ELF object libbpf: elf: failed to get ELF header from %s: %s libbpf: elf: failed to get section names section index for %s: %s libbpf: elf: failed to get section names strings from %s: %s libbpf: elf: %s is not a valid eBPF object file libbpf: elf: endianness mismatch in %s. libbpf: invalid license section in %s libbpf: license of %s is %s libbpf: invalid kver section in %s libbpf: kernel version of %s is %x libbpf: failed to get sym name string for var %s libbpf-placeholder-fd %.*s%.*s libbpf: map '%s' (global data): at sec_idx %d, offset %zu, flags %x. libbpf: failed to alloc map '%s' content buffer: %d libbpf: map %td is "%s" libbpf: extern (kcfg) '%s': value '%c' implies tristate or char type libbpf: extern (kcfg) '%s': value '%c' implies bool, tristate, or char type libbpf: extern (kcfg) '%s': value '%s' implies char array type libbpf: extern (kcfg) '%s': invalid string config '%s' libbpf: extern (kcfg) '%s': long string '%s' of (%zu bytes) truncated to %d bytes libbpf: failed to parse '%s' as integer: %d libbpf: failed to parse '%s' as integer completely libbpf: extern (kcfg) '%s': value '%llu' implies integer, char, or boolean type libbpf: extern (kcfg) '%s': value '%llu' isn't boolean compatible libbpf: extern (kcfg) '%s': value '%llu' doesn't fit in %d bytes CONFIG_ libbpf: failed to parse '%s': no separator libbpf: failed to parse '%s': no value libbpf: extern (kcfg) '%s': value '%s' isn't a valid integer libbpf: extern (kcfg) '%s': value '%s' implies integer type libbpf: extern (kcfg) '%s': set to %s /boot/config-%s re /proc/config.gz libbpf: failed to open system Kconfig libbpf: error parsing system Kconfig line '%s': %d r libbpf: failed to open in-memory Kconfig: %d libbpf: error parsing in-memory Kconfig line '%s': %d .kconfig void int ptr struct union enum fwd typedef volatile const restrict func func_proto var datasec float decl_tag type_tag enum64 unknown 0<HT`lxɥҥۥlibbpf: map '%s': attr '%s': expected PTR, got %s. libbpf: map '%s': attr '%s': type [%u] not found. libbpf: map '%s': attr '%s': expected ARRAY, got %s. libbpf: map '%s': attr '%s': expected ENUM or ENUM64, got %s. libbpf: map '%s': attr '%s': invalid __ulong %s/%s /sys/fs/bpf libbpf: map '%s': invalid field #%d. type max_entries map_flags numa_node key_size libbpf: map '%s': conflicting key size %u != %u. key libbpf: map '%s': key type [%d] not found. libbpf: map '%s': key spec is not PTR: %s. libbpf: map '%s': can't determine key size for type [%u]: %zd. libbpf: map '%s': conflicting key size %u != %zd. value_size libbpf: map '%s': conflicting value size %u != %u. value libbpf: map '%s': value type [%d] not found. libbpf: map '%s': value spec is not PTR: %s. libbpf: map '%s': can't determine value size for type [%u]: %zd. libbpf: map '%s': conflicting value size %u != %zd. values map-in-map inner prog-array value libbpf: map '%s': multi-level inner maps not supported. libbpf: map '%s': '%s' member should be last. libbpf: map '%s': should be map-in-map or prog-array. libbpf: map '%s': conflicting value size %u != 4. libbpf: map '%s': %s type [%d] not found. libbpf: map '%s': %s spec is not a zero-sized array. libbpf: map '%s': %s def is of unexpected kind %s. libbpf: map '%s': prog-array value def is of unexpected kind %s. libbpf: map '%s': map-in-map inner def is of unexpected kind %s. %s.inner pinning libbpf: map '%s': inner def can't be pinned. libbpf: map '%s': invalid pinning value %u. map_extra libbpf: map '%s': unknown field '%s'. libbpf: map '%s': ignoring unknown field '%s'. libbpf: map '%s': map type isn't specified. libbpf: map '%s': found type = %u. libbpf: map '%s': found key [%u], sz = %u. libbpf: map '%s': found key_size = %u. libbpf: map '%s': found value [%u], sz = %u. libbpf: map '%s': found value_size = %u. libbpf: map '%s': found max_entries = %u. libbpf: map '%s': found map_flags = 0x%x. libbpf: map '%s': found map_extra = 0x%llx. libbpf: map '%s': found pinning = %u. libbpf: map '%s': found numa_node = %u. libbpf: map '%s': found inner map definition. static global extern libbpf: map #%d: empty name. libbpf: map '%s' BTF data is corrupted. libbpf: map '%s': unexpected var kind %s. libbpf: map '%s': unsupported map linkage %s. libbpf: map '%s': unexpected def kind %s. libbpf: map '%s': invalid def size. libbpf: map '%s': failed to alloc map name. libbpf: map '%s': at sec_idx %d, offset %zu. libbpf: map '%s': couldn't build pin path. libbpf: elf: sec '%s': declared ARENA map size (%zu) is too small to hold global __arena variables of size %zu .maps libbpf: elf: failed to get %s map definitions for %s libbpf: DATASEC '%s' not found. libbpf: map '%s': only single ARENA map is supported (map '%s' is also ARENA) .addr_space.1 libbpf: elf: sec '%s': to use global __arena variables the ARENA map should be explicitly declared in SEC(".maps") enum64_placeholder .BTF libbpf: Error loading ELF section %s: %d. .BTF.ext libbpf: Ignore ELF section %s because its depending ELF section %s is not found. libbpf: Error loading ELF section %s: %d. Ignored and continue. libbpf: BTF is required, but is missing or corrupted. libbpf: No name found in string section for DATASEC kind. .ksyms libbpf: sec '%s': failed to determine size from ELF: size %u, err %d libbpf: sec '%s': unexpected non-VAR type found libbpf: sec '%s': failed to find name of DATASEC's member #%d libbpf: sec '%s': failed to find ELF symbol for VAR '%s' libbpf: Error loading vmlinux BTF: %d libbpf: Kernel doesn't support BTF, skipping uploading it. BTF is mandatory, can't proceed. BTF is optional, ignoring. libbpf: Error loading .BTF into kernel: %d. %s libbpf: elf: failed to get section name string at offset %zu from %s: %s libbpf: elf: failed to get section(%zu) from %s: %s libbpf: elf: failed to get section(%zu) header from %s: %s libbpf: elf: failed to get section(%zu) name from %s: %s <?> libbpf: elf: failed to get section(%zu) %s data from %s: %s .debug_ .text .rel libbpf: elf: failed to get the number of sections for %s: %s libbpf: elf: multiple symbol tables in %s libbpf: elf: couldn't find symbol table in %s, stripped object file? libbpf: elf: section(%d) %s, size %ld, link %d, flags %lx, type=%d license version maps libbpf: elf: legacy map definitions in 'maps' section are not supported by libbpf v1.0+ .data .data. .rodata .rodata. .struct_ops ?.struct_ops ?.struct_ops.link libbpf: elf: skipping unrecognized data section(%d) %s .rel.struct_ops .rel.struct_ops.link .rel?.struct_ops .rel?.struct_ops.link .rel.maps libbpf: elf: skipping relo section(%d) %s for section(%d) %s .bss .bss. libbpf: elf: skipping section(%d) %s (size %zu) libbpf: elf: symbol strings section missing or invalid in %s libbpf_tristate dummy_ksym libbpf: cannot create a dummy_ksym var libbpf: looking for externs among %d symbols... libbpf: failed to find BTF for extern '%s': %d libbpf: failed to find BTF for extern '%s' [%d] section: %d libbpf: extern function %s is unsupported under %s section libbpf: failed to resolve size of extern (kcfg) '%s': %d libbpf: failed to determine alignment of extern (kcfg) '%s': %d libbpf: extern (kcfg) '%s': type is unsupported libbpf: unrecognized extern section '%s' libbpf: collected %d externs total libbpf: extern (ksym) #%d: symbol %d, name %s libbpf: failed to find extern definition for BTF %s '%s' libbpf: extern (kcfg) #%d: symbol %d, off %u, name %s libbpf: failed to find extern definition for BTF var '%s' libbpf: prog '%s': invalid relo against '%s' for insns[%d].code 0x%x libbpf: prog '%s': extern relo failed to find extern for '%s' (%d) libbpf: prog '%s': found extern #%d '%s' (sym %d) for insn #%u libbpf: prog '%s': incorrect bpf_call opcode libbpf: prog '%s': bad call relo against '%s' in section '%s' libbpf: prog '%s': bad call relo against '%s' at offset %zu libbpf: prog '%s': invalid relo against '%s' in special section 0x%x; forgot to initialize global var?.. libbpf: prog '%s': bad subprog addr relo against '%s' at offset %zu+%d libbpf: prog '%s': bad map relo against '%s' in section '%s' libbpf: prog '%s': found map %zd (%s, sec %d, off %zu) for insn #%u libbpf: prog '%s': map relo failed to find map for section '%s', off %zu libbpf: prog '%s': bad data relo against section '%s' libbpf: prog '%s': found data map %zd (%s, sec %d, off %zu) for insn %u libbpf: prog '%s': data relo failed to find map for section '%s' libbpf: sec '%s': collecting relocation for section(%zu) '%s' libbpf: sec '%s': failed to get relo #%d libbpf: sec '%s': symbol #%zu not found for relo #%d libbpf: sec '%s': corrupted symbol #%zu pointing to invalid section #%zu for relo #%d libbpf: sec '%s': invalid offset 0x%zx for relo #%d <? libbpf: sec '%s': relo #%d: insn #%u against '%s' libbpf: sec '%s': relo #%d: couldn't find program in section '%s' for insn #%u, probably overridden weak function, skipping... /proc/%d/fdinfo/%d libbpf: failed to open %s: %d. No procfs support? map_type: %u key_size: %u value_size: %u max_entries: %u map_flags: %i libbpf: object '%s': token is prevented, skipping... , skipping optional step... libbpf: object '%s': failed (%d) to open BPF FS mount at '%s'%s libbpf: object '%s': BPF FS at '%s' doesn't have BPF token delegation set up, skipping... libbpf: object '%s': failed (%d) to create BPF token from '%s'%s libbpf: Failed to bump RLIMIT_MEMLOCK (err = %d), you might need to do it explicitly! GPL libbpf: Error in %s():%s(%d). Couldn't load trivial BPF program. Make sure your kernel supports BPF (CONFIG_BPF_SYSCALL=y) and/or that RLIMIT_MEMLOCK is set to big enough value. libbpf: failed to get map info for map FD %d: %s libbpf: found no pinned map to reuse at '%s' libbpf: couldn't retrieve pinned map '%s': %s libbpf: couldn't reuse pinned map at '%s': parameter mismatch libbpf: reused pinned map at '%s' libbpf: map '%s': failed to set initial contents: %s libbpf: map '%s': failed to freeze as read-only: %s libbpf: map '%s': failed to re-mmap() contents: %d libbpf: map '%s': failed to create inner map: %d libbpf: Error in bpf_create_map_xattr(%s):%s(%d). Retrying without BTF. libbpf: map '%s': failed to initialize slot [%d] to map '%s' fd=%d: %d libbpf: map '%s': slot [%d] set to map '%s' fd=%d libbpf: map '%s': failed to initialize slot [%d] to prog '%s' fd=%d: %d libbpf: map '%s': slot [%d] set to prog '%s' fd=%d libbpf: map '%s': failed to determine number of system CPUs: %d libbpf: map '%s': setting size to %d libbpf: map '%s': skipped auto-creating... libbpf: map '%s': error reusing pinned map libbpf: map '%s': cannot find pinned map libbpf: map '%s': skipping creation (preset fd=%d) libbpf: map '%s': created successfully, fd=%d libbpf: map '%s': failed to mmap arena: %d libbpf: map '%s': failed to auto-pin at '%s': %d libbpf: map '%s': failed to create: %s(%d) libbpf: CO-RE relocating [%d] %s %s: found target candidate [%d] %s %s in [%s] libbpf: skipping module BTFs loading, missing privileges libbpf: failed to iterate BTF objects: %d libbpf: failed to get BTF object #%d FD: %d libbpf: failed to get BTF object #%d info: %d vmlinux libbpf: failed to load module [%s]'s BTF object #%d: %d libbpf: prog '%s': relo #%d: target candidate search failed for [%d] %s %s: %ld libbpf: failed to parse target BTF: %d libbpf: sec '%s': found %d CO-RE relocations libbpf: sec '%s': skipping CO-RE relocation #%d for insn #%d belonging to eliminated weak subprogram libbpf: prog '%s': relo #%d: failed to record relocation: %d libbpf: prog '%s': relo #%d: failed to relocate: %d libbpf: prog '%s': relo #%d: failed to patch insn #%u: %d libbpf: prog '%s': relo #%d: poisoning insn #%d that loads map #%d '%s' libbpf: prog '%s': relo #%d: poisoning insn #%d that calls kfunc '%s' libbpf: prog '%s': relo #%d: bad insn libbpf: prog '%s': relo #%d: bad relo type %d >&*&' ))* libbpf: prog '%s': error relocating .BTF.ext function info: %d libbpf: prog '%s': missing .BTF.ext function info. libbpf: prog '%s': missing .BTF.ext function info for the main program, skipping all of .BTF.ext func info. libbpf: prog '%s': error relocating .BTF.ext line info: %d libbpf: prog '%s': missing .BTF.ext line info. libbpf: prog '%s': missing .BTF.ext line info for the main program, skipping all of .BTF.ext line info. libbpf: prog '%s': failed to realloc prog code libbpf: prog '%s': added %zu insns from sub-prog '%s' libbpf: prog '%s': unexpected relo for insn #%zu, type %d libbpf: prog '%s': missing subprog addr relo for insn #%zu libbpf: prog '%s': no .text section found yet sub-program call exists libbpf: prog '%s': insn #%zu relocated, imm %d points to subprog '%s' (now at %zu offset) exception_callback: libbpf: prog '%s': exception_callback:<value> decl tag not applied to the main program libbpf: prog '%s': exception_callback:<value> decl tag contains empty value libbpf: prog '%s': exception callback %s must be a global non-hidden function libbpf: prog '%s': multiple subprogs with same name as exception callback '%s' libbpf: prog '%s': cannot find exception callback '%s' bpf_cgroup_dev_ctx __sk_buff bpf_sock bpf_sock_addr bpf_sockopt bpf_sysctl bpf_user_pt_regs_t bpf_nf_ctx bpf_perf_event_data bpf_raw_tracepoint_args bpf_sk_lookup sk_msg_md sk_reuseport_md bpf_sock_ops xdp_md <anon> pt_regs libbpf: prog '%s': subprog '%s' arg#%d is expected to be of `struct %s *` type arg:ctx libbpf: failed to perform CO-RE relocations: %d libbpf: prog '%s': failed to relocate calls: %d libbpf: prog '%s': failed to relocate data references: %d libbpf: prog '%s': failed to perform .BTF.ext fix ups: %d libbpf: .maps relo #%d: failed to get ELF relo libbpf: .maps relo #%d: symbol %zx not found libbpf: .maps relo #%d: for %zd value %zd rel->r_offset %zu name %d ('%s') libbpf: .maps relo #%d: cannot find map '%s' at rel->r_offset %zu map prog libbpf: .maps relo #%d: '%s' isn't a BTF-defined map libbpf: .maps relo #%d: hash-of-maps '%s' should have key size %zu. libbpf: .maps relo #%d: '%s' isn't a valid map reference libbpf: .maps relo #%d: '%s' isn't a valid program reference libbpf: .maps relo #%d: '%s' isn't an entry-point program libbpf: .maps relo #%d: map '%s' slot [%d] points to %s '%s' libbpf: internal error at %d libbpf: prog '%s': no BTF-based attach target is specified, use bpf_program__set_attach_target() libbpf: prog '%s': missing BPF prog type, check ELF section name '%s' libbpf: prog '%s': SEC("struct_ops") program isn't referenced anywhere, did you forget to use it? libbpf: prog '%s': failed to prepare load attributes: %d libbpf: prog '%s': -- BEGIN PROG LOAD LOG -- %s-- END PROG LOAD LOG -- libbpf: prog '%s': failed to bind map '%s': %s libbpf: prog '%s': BPF program load failed: %s %d: (%*d) call unknown#195896080 ... %d: <invalid CO-RE relocation> failed to resolve CO-RE relocation %s%s %d: (%*d) call unknown#%d %d: <invalid BPF map reference> BPF map '%s' is referenced but wasn't created %d: <invalid kfunc call> kfunc '%s' is referenced but wasn't resolved invalid func unknown#195896080 invalid func unknown#200100 invalid func unknown#2002 libbpf: prog '%s': skipped loading libbpf: prog '%s': failed to load: %d libbpf: prog '%s': unrecognized ELF section name '%s' libbpf: prog '%s': failed to initialize: %d (mem buf) libbpf: failed to init libelf for %s bpf_object_open_opts libbpf: loading object '%s' from buffer libbpf: loading object from %s LIBBPF_BPF_TOKEN_PATH %lx-%zx /proc/kallsyms libbpf: failed to open /proc/kallsyms: %d %llx %c %499s%*[^ ] libbpf: failed to read kallsyms entry: %d .llvm. libbpf: extern (ksym) '%s': resolution is ambiguous: 0x%llx or 0x%llx libbpf: extern (ksym) '%s': set to 0x%llx libbpf: extern (var ksym) '%s': not found in kernel BTF libbpf: extern (var ksym) '%s': incompatible types, expected [%d] %s %s, but kernel has [%d] %s %s libbpf: extern (var ksym) '%s': resolved to [%d] %s %s libbpf: extern (func ksym) '%s': not found in kernel or module BTFs libbpf: extern (func ksym) '%s': func_proto [%d] incompatible with %s [%d] libbpf: extern (func ksym) '%s': module BTF fd index %d too big to fit in bpf_insn offset libbpf: extern (func ksym) '%s': resolved to %s [%d] LINUX_KERNEL_VERSION libbpf: extern (kcfg) '%s': failed to get kernel version LINUX_HAS_BPF_COOKIE LINUX_HAS_SYSCALL_WRAPPER LINUX_ libbpf: extern (kcfg) '%s': unrecognized virtual extern libbpf: extern (kcfg) '%s': set to 0x%llx libbpf: extern '%s': unrecognized extern kind libbpf: extern '%s' (strong): not resolved libbpf: extern '%s' (weak): not resolved, defaulting to zero libbpf: object '%s': load can't be attempted twice libbpf: failed to load object '%s' libbpf: failed to mkdir %s: %s libbpf: failed to statfs %s: %s libbpf: specified path %s is not on BPF FS libbpf: prog '%s': can't pin program that wasn't loaded libbpf: prog '%s': failed to pin at '%s': %s libbpf: prog '%s': pinned at '%s' libbpf: prog '%s': can't unpin program that wasn't loaded libbpf: prog '%s': unpinned from '%s' libbpf: invalid map pointer libbpf: map '%s': can't pin BPF map without FD (was it created?) libbpf: map '%s' already has pin path '%s' different from '%s' libbpf: map '%s' already pinned at '%s'; not re-pinning libbpf: missing a path to pin map '%s' at libbpf: map '%s' already pinned libbpf: pinned map '%s' libbpf: failed to pin map: %s libbpf: no path to unpin map '%s' from libbpf: unpinned map '%s' from '%s' libbpf: object not yet loaded; load it first gen_loader_opts libbpf: error: program handler doesn't match object socket sk_reuseport/migrate kprobe+ uprobe+ uprobe.s+ kretprobe+ uretprobe+ uretprobe.s+ kprobe.multi+ kretprobe.multi+ kprobe.session+ uprobe.multi+ uretprobe.multi+ uprobe.multi.s+ uretprobe.multi.s+ ksyscall+ kretsyscall+ usdt+ usdt.s+ tc/ingress tc/egress tcx/ingress tcx/egress tc classifier action netkit/primary netkit/peer tracepoint+ tp+ raw_tracepoint+ raw_tp+ raw_tracepoint.w+ raw_tp.w+ tp_btf+ fentry+ fmod_ret+ fexit+ fentry.s+ fmod_ret.s+ fexit.s+ freplace+ lsm+ lsm.s+ lsm_cgroup+ iter+ iter.s+ xdp.frags/devmap xdp/devmap xdp.frags/cpumap xdp/cpumap xdp.frags sockops sk_skb/stream_parser sk_skb/stream_verdict sk_skb/verdict cgroup_skb/ingress cgroup_skb/egress cgroup/skb cgroup/sock_create cgroup/sock_release cgroup/sock cgroup/post_bind4 cgroup/post_bind6 cgroup/bind4 cgroup/bind6 cgroup/connect4 cgroup/connect6 cgroup/connect_unix cgroup/sendmsg4 cgroup/sendmsg6 cgroup/sendmsg_unix cgroup/recvmsg4 cgroup/recvmsg6 cgroup/recvmsg_unix cgroup/getpeername4 cgroup/getpeername6 cgroup/getpeername_unix cgroup/getsockname4 cgroup/getsockname6 cgroup/getsockname_unix cgroup/sysctl cgroup/getsockopt cgroup/setsockopt cgroup/dev struct_ops+ struct_ops.s+ libbpf_prog_handler_opts libbpf: failed to guess program type from ELF section '%s' libbpf: supported section(type) names are:%s libbpf: struct_ops reloc: failed to get %d reloc libbpf: struct_ops reloc: symbol %zx not found libbpf: struct_ops reloc: cannot find map at rel->r_offset %zu libbpf: struct_ops reloc %s: for %lld value %lld shdr_idx %u rel->r_offset %zu map->sec_offset %zu name %d ('%s') libbpf: struct_ops reloc %s: rel->r_offset %zu shdr_idx %u unsupported non-static function libbpf: struct_ops reloc %s: invalid target program offset %llu libbpf: struct_ops reloc %s: cannot find member at moff %u libbpf: struct_ops reloc %s: cannot relocate non func ptr %s libbpf: struct_ops reloc %s: cannot find prog at shdr_idx %u to relocate func ptr %s libbpf: struct_ops reloc %s: prog %s is not struct_ops BPF program btf_trace_ bpf_lsm_ bpf_iter_ %s%s libbpf: vmlinux BTF is not found libbpf: %s is not found in vmlinux BTF libbpf: failed bpf_prog_get_info_by_fd for FD %d: %d libbpf: The target program doesn't have BTF libbpf: Failed to get BTF %d of the program: %d libbpf: %s is not found in prog's BTF libbpf: prog '%s': attach program FD is not set libbpf: prog '%s': failed to find BPF program (FD %d) BTF ID for '%s': %d libbpf: prog '%s': failed to find kernel BTF type ID of '%s': %d libbpf: failed to guess attach type based on ELF section name '%s' libbpf: attachable section(type) names are:%s libbpf: map '%s': cannot be resized, map value type is not a datasec libbpf: map '%s': cannot be resized, map value datasec is empty libbpf: map '%s': cannot be resized, last var must be an array libbpf: map '%s': cannot be resized, element size (%d) doesn't align with new total size (%u) libbpf: map '%s': failed to resize memory-mapped region: %d libbpf: map '%s': failed to adjust resized BTF, clearing BTF key/value info: %d libbpf: error: unsupported map type libbpf: error: inner_map_fd already specified libbpf: error in %s: map handler doesn't belong to object libbpf: map '%s': unexpected key size %zu provided, expected %u libbpf: map '%s': can't use BPF map without FD (was it created?) libbpf: map '%s': unexpected value size %zu provided for per-CPU map, expected %d * %zu = %zd libbpf: map '%s': unexpected value size %zu provided, expected %u libbpf: prog '%s': can't use BPF program without FD (was it loaded?) libbpf: failed to open link at %s: %d libbpf: link fd=%d: pinned at %s libbpf: link fd=%d: unpinned from %s bpf_perf_event_opts libbpf: prog '%s': invalid perf event FD %d libbpf: prog '%s': can't attach BPF program without FD (was it loaded?) libbpf: prog '%s': failed to create BPF link for perf_event FD %d: %d (%s) libbpf: prog '%s': user context value is not supported libbpf: prog '%s': failed to attach to perf_event FD %d: %s libbpf: prog '%s': try add PERF_SAMPLE_CALLCHAIN to or remove exclude_callchain_[kernel|user] from pfd %d libbpf: prog '%s': failed to enable perf_event FD %d: %s libbpf: failed to open '%s': %s libbpf: failed to parse '%s': %s /sys/bus/event_source/devices/kprobe/type %d /sys/bus/event_source/devices/uprobe/type /sys/bus/event_source/devices/kprobe/format/retprobe config:%d /sys/bus/event_source/devices/uprobe/format/retprobe uprobe libbpf: failed to determine %s perf type: %s libbpf: failed to determine %s retprobe bit: %s /sys/kernel/debug/tracing /sys/kernel/tracing /sys/kernel/debug/tracing/kprobe_events /sys/kernel/tracing/kprobe_events /sys/kernel/debug/tracing/uprobe_events /sys/kernel/tracing/uprobe_events /sys/kernel/debug/tracing/available_filter_functions /sys/kernel/tracing/available_filter_functions /sys/kernel/debug/tracing/available_filter_functions_addrs /sys/kernel/tracing/available_filter_functions_addrs libbpf_%u_%s_0x%zx_%d kretprobes kprobes %c:%s/%s %s+0x%zx -:%s/%s %s/events/%s/%s/id libbpf: failed to add legacy kprobe event for '%s+0x%zx': %s libbpf: failed to determine legacy kprobe event id for '%s+0x%zx': %s libbpf: legacy kprobe perf_event_open() failed: %s x64 __%s_sys_bpf bpf_kprobe_opts kretprobe libbpf: prog '%s': failed to create %s '%s+0x%zx' perf event: %s libbpf: prog '%s': failed to attach to %s '%s+0x%zx': %s bpf_ksyscall_opts __%s_sys_%s __se_sys_%s libbpf: failed to open %s: %d %499s%*[^ ] libbpf: failed to parse available_filter_functions entry: %d %llx %499s%*[^ ] libbpf: failed to parse available_filter_functions_addrs entry: %d bpf_kprobe_multi_opts libbpf: prog '%s': failed to attach: %s kretprobe/ %m[a-zA-Z0-9_.]+%li libbpf: kprobe name is invalid: %s libbpf: kretprobes do not support offset specification ksyscall kretsyscall kretsyscall/ kprobe.multi kretprobe.multi kretprobe.multi/ %m[a-zA-Z0-9_.*?] libbpf: kprobe multi pattern is invalid: %s kprobe.session libbpf: kprobe session pattern is invalid: %s %m[^/]/%m[^:]:%m[^ ] uretprobe.multi libbpf: prog '%s': invalid format of section definition '%s' libbpf_%u_%s_0x%zx uretprobes uprobes %c:%s/%s %s:0x%zx libbpf: failed to add legacy uprobe event for %s:0x%zx: %d libbpf: failed to determine legacy uprobe event id for %s:0x%zx: %d libbpf: legacy uprobe perf_event_open() failed: %d libbpf: zip: failed to open %s: %ld libbpf: zip: could not find archive member %s in %s: %ld libbpf: zip: found entry for %s in %s at 0x%lx libbpf: zip: entry %s of %s is compressed and cannot be handled libbpf: elf: could not read elf file %s from %s: %s libbpf: elf: symbol address match for %s of %s in %s: 0x%x + 0x%lx = 0x%lx /lib/x86_64-linux-gnu .so .so. LD_LIBRARY_PATH /usr/lib64:/usr/lib PATH /usr/bin:/usr/sbin %.*s/%s libbpf: resolved '%s' to '%s' bpf_uprobe_multi_opts libbpf: prog '%s': failed to resolve full path for '%s': %d libbpf: prog '%s': failed to attach multi-uprobe: %s bpf_uprobe_opts !/ uretprobe libbpf: prog '%s': failed to create %s '%s:0x%zx' perf event: %s libbpf: prog '%s': failed to attach to %s '%s:0x%zx': %s libbpf: prog '%s': section '%s' missing ':function[+offset]' specification +%li%n uretprobe.s libbpf: prog '%s': uretprobes do not support offset specification usdt usdt/%m[^:]:%m[^:]:%m[^:] libbpf: invalid section '%s', expected SEC("usdt/<path>:<provider>:<name>") libbpf: tracepoint %s/%s path is too long libbpf: failed to determine tracepoint '%s/%s' perf event ID: %s libbpf: tracepoint '%s/%s' perf_event_open() failed: %s bpf_tracepoint_opts libbpf: prog '%s': failed to create tracepoint '%s/%s' perf event: %s libbpf: prog '%s': failed to attach to tracepoint '%s/%s': %s tp tp/ bpf_raw_tracepoint_opts libbpf: prog '%s': can't attach before loaded libbpf: prog '%s': failed to attach to raw tracepoint '%s': %s libbpf: prog '%s': invalid section name '%s' bpf_trace_opts libbpf: prog '%s': failed to attach to %s: %s bpf_tcx_opts libbpf: prog '%s': target netdevice ifindex cannot be zero libbpf: prog '%s': relative_fd and relative_id cannot be set at the same time bpf_netkit_opts libbpf: prog '%s': supply none or both of target_fd and attach_func_name libbpf: prog '%s': only BPF_PROG_TYPE_EXT can attach as freplace freplace bpf_iter_attach_opts libbpf: prog '%s': failed to attach to iterator: %s bpf_netfilter_opts libbpf: prog '%s': failed to attach to netfilter: %s libbpf: map '%s': can't attach non-struct_ops map libbpf: map '%s': can't attach BPF map without FD (was it created?) libbpf: failed to munmap cpu_buf #%d libbpf: failed to open perf buffer event on cpu #%d: %s libbpf: failed to mmap perf buffer on cpu #%d: %s libbpf: failed to enable perf buffer event on cpu #%d: %s perf_buffer_opts perf_buffer_raw_opts /sys/devices/system/cpu/online libbpf: page count should be power of two, but is %zu libbpf: failed to get map info for FD %d; API not supported? Ignoring... libbpf: map '%s' should be BPF_MAP_TYPE_PERF_EVENT_ARRAY libbpf: failed to create epoll instance: %s libbpf: failed to allocate events: out of memory libbpf: failed to allocate buffers: out of memory libbpf: failed to get online CPU mask: %d libbpf: failed to set cpu #%d, key %d -> perf FD %d: %s libbpf: failed to epoll_ctl cpu #%d perf FD %d: %s libbpf: unknown perf sample type %d libbpf: error while processing records: %d libbpf: perf_buffer: failed to process records in buffer #%d: %d %d%n-%d%n libbpf: Failed to get CPU range %s: %d libbpf: Invalid CPU range [%d,%d] in %s libbpf: Empty CPU range libbpf: Failed to open cpu mask file %s: %d libbpf: Failed to read cpu mask from %s: %d libbpf: CPU mask is too big in file %s libbpf: failed to find skeleton map '%s' libbpf: failed to find skeleton program '%s' libbpf: failed to initialize skeleton BPF object '%s': %d libbpf: failed to populate skeleton maps for '%s': %d libbpf: failed to populate skeleton progs for '%s': %d libbpf: subskeletons require BTF at runtime (object %s) libbpf: failed to populate subskeleton maps: %d libbpf: type for map '%1$s' is not a datasec: %2$s libbpf: failed to load BPF skeleton '%s': %d libbpf: prog '%s': failed to auto-attach: %d libbpf: map '%s': BPF skeleton version is old, skipping map auto-attachment... libbpf: map '%s': failed to auto-attach: %d bpf_object__probe_loading __bpf_map__iter raw_tp raw_tp.w raw_tracepoint.w /sys/devices/system/cpu/possible @ 0Alibbpf: %s size (%zu) is too small libbpf: %s has non-zero extra bytes libbpf: failed to dup FD %d to FD > 2: %d GPL bpf_map_create_opts bpf_prog_load_opts bpf_map_batch_opts bpf_obj_pin_opts bpf_obj_get_opts bpf_prog_attach_opts bpf_prog_detach_opts bpf_link_create_opts aaaaa|]HfHfHfHfHfHfHfHfHfHfHfHf]j^HfHfgbcc_HfHfHfHfHfddj^bpf_link_update_opts bpf_prog_query_opts bpf_test_run_opts bpf_get_fd_by_id_opts bpf_raw_tp_opts bpf_btf_load_opts bpf_prog_bind_opts bpf_token_create_opts libbpf: Attribute of type %#x found multiple times in message, previous attribute is being ignored. libbpf: Failed to parse extended error attributes libbpf: Kernel error message: %s libbpf: %s size (%zu) is too small libbpf: %s has non-zero extra bytes libbpf: BTF header not found libbpf: Can't load BTF with non-native endianness due to unsupported header length %u libbpf: Invalid BTF magic: %x libbpf: BTF header len %u larger than data size %u libbpf: Invalid BTF total size: %u libbpf: Invalid BTF data sections layout: type data at %u + %u, strings data at %u + %u libbpf: BTF type section is not aligned to 4 bytes libbpf: Invalid BTF string section libbpf: Unsupported BTF_KIND:%u !˒ӒӒߓy֕w> libbpf: BTF type [%d] is malformed libbpf: BTF types data is malformed libbpf: btf: type [%u]: invalid %s (string offset %u) libbpf: btf: type [%u]: invalid referenced type ID %u type name field name enum name libbpf: btf: type [%u]: referenced type [%u] is not FUNC_PROTO param name libbpf: btf: type [%u]: unrecognized kind %u zz u|libbpf: unsupported BTF_KIND:%u void libbpf: failed to get EHDR from %s libbpf: failed to get section names section index for %s libbpf: failed to get e_shstrndx from %s libbpf: failed to get section(%d) header from %s libbpf: failed to get section(%d) name from %s .BTF .BTF.ext .BTF.base libbpf: failed to get section(%d, %s) data from %s libbpf: failed to init libelf for %s libbpf: failed to open %s: %s libbpf: failed to open %s as ELF file libbpf: failed to find '%s' ELF section in %s libbpf: failed to get ELF class (bitness) for %s rbe libbpf: BTF loading error: %d libbpf: -- BEGIN BTF LOAD LOG --- %s -- END BTF LOAD LOG -- libbpf: .BTF.ext %s section is not aligned to 4 bytes libbpf: %s section (off:%u len:%u) is beyond the end of the ELF section .BTF.ext libbpf: .BTF.ext %s record size not found libbpf: %s section in .BTF.ext has invalid record size %u libbpf: %s section in .BTF.ext has no records libbpf: %s section header is not found in .BTF.ext libbpf: %s section has incorrect num_records in .BTF.ext func_info line_info core_relo libbpf: BTF.ext header not found libbpf: BTF.ext in non-native endianness is not supported libbpf: Invalid BTF.ext magic:%x libbpf: Unsupported BTF.ext version:%u libbpf: Unsupported BTF.ext flags:%x libbpf: BTF.ext has no data btf_dedup_opts libbpf: btf_dedup_new failed: %ld libbpf: btf_dedup_prep failed:%d libbpf: btf_dedup_strings failed:%d libbpf: btf_dedup_prim_types failed:%d libbpf: btf_dedup_struct_types failed:%d libbpf: btf_dedup_resolve_fwds failed:%d libbpf: btf_dedup_ref_types failed:%d libbpf: btf_dedup_compact_types failed:%d libbpf: btf_dedup_remap_types failed:%d libbpf: unknown kind %d for type [%d] #zzRERRR M /sys/kernel/btf/vmlinux /boot/vmlinux-%1$s /lib/modules/%1$s/vmlinux-%1$s /lib/modules/%1$s/build/vmlinux /usr/lib/modules/%1$s/kernel/vmlinux /usr/lib/debug/boot/vmlinux-%1$s /usr/lib/debug/boot/vmlinux-%1$s.debug /usr/lib/debug/lib/modules/%1$s/vmlinux libbpf: kernel BTF is missing at '%s', was CONFIG_DEBUG_INFO_BTF enabled? libbpf: failed to read kernel BTF from '%s': %d libbpf: loaded kernel BTF from '%s' libbpf: loading kernel BTF '%s': %d libbpf: failed to find valid kernel BTF /sys/kernel/btf/%s libbpf: unexpected reference to base type[%u] of kind [%u] when creating distilled base BTF. libbpf: unexpected kind when adding base type '%s'[%u] of kind [%u] to distilled base BTF. long long int int long unsigned long long unsigned unsigned long int unsigned int long long unsigned int long int unsigned int unsigned long int long unsigned Something wrong in libelf BPF object format invalid 'version' section incorrect or lost Endian mismatch Internal error in libbpf Relocation failed Kernel verifier blocks program loading Program too big Incorrect kernel version Kernel doesn't support this program type Wrong pid in netlink message Invalid netlink sequence Incorrect netlink message parsing %s Unknown libbpf error %d unknown error (%d) ERROR: strerror_r(%d)=%d libbpf: %s size (%zu) is too small libbpf: %s has non-zero extra bytes libbpf: Netlink error reporting not supported bpf_xdp_attach_opts bpf_xdp_query_opts netdev clsact bpf_tc_hook %s:[%u] bpf_tc_opts bpf /proc/version_signature re %*s %*s %u.%u.%u Debian Debian %u.%u.%u %u.%u.%u attach_btf_id 1 is not a function Cannot replace kernel functions GPL )^)^1])^)^)^)^)^)^)^)^)^)^)^)^)^)^)^])^A])^)^)^)^]P]^]P]"]]^ddddddd{cdddcdddddddcdccccdTd.dccnd.dcdinvalid func unknown func program of this type cannot use helper libbpf: %s size (%zu) is too small libbpf: %s has non-zero extra bytes btf_dump_opts ~~1}V}}}~~1}1}1}1}1}}1}G~~1}1}~libbpf: unsatisfiable type cycle, id:[%u] ) 7keeAAA_ Ae__builtin_va_list libbpf: anonymous struct/union loop, id:[%u] ; /LHHp///~/long int short char %s%s: %d; struct union %s%s%s %s%s%s { %s : %d ; %s} } __attribute__((packed)) __Poly8_t unsigned char __Poly16_t unsigned short __Poly64_t unsigned long long __Poly128_t unsigned __int128 typedef %s %s; enum %s %s%s___%zd = %d, %s%s___%zd = %u, %s%s = %d, %s%s = %u, %s%s___%zd = %lldLL, %s%s___%zd = %lluULL, %s%s = %lldLL, %s%s = %lluULL, enum%s%s { %s} __attribute__((mode(byte))) __attribute__((mode(word))) union %s struct %s __gnuc_va_list typedef __builtin_va_list __gnuc_va_list typedef btf_dump_emit_type_decl_opts libbpf: not enough memory for decl stack:%d libbpf: unexpected type in decl chain, kind:%u, id:[%u] volatile const restrict %s%s void %s * * volatile const restrict __attribute__((btf_type_tag("%s"))) [%u] ( ) ( void) , ... VۛÜg4T1Vt%s___%zu , <unsupported kind:%u> libbpf: unexpected bitfield size %d 0x%llx%s%s libbpf: unexpected size %d for id [%u] 0x%llx%016llx%s%s %lld%s%s %llu%s%s %d%s%s %u%s%s '\0'%s%s '%c'%s%s libbpf: unexpected sz %d for id [%u] ެa˪ެ=ެެެެެެެެެެ%Lf%s%s %lf%s%s %f%s%s static extern %s = libbpf: unexpected elem size %zd for array type [%u] [%s ]%s%s {%s }%s%s %p%s%s 0x%x%s%s libbpf: unexpected size %d for enum, id:[%u] %d %lldLL %lluULL%s%s SEC("%s") %s%s libbpf: unexpected size [%zu] for id [%u] libbpf: unexpected error skipping mods/typedefs for id [%u] ϻϻ.%s = libbpf: unexpected kind [%u] for id [%u] 1¿ | btf_dump_type_data_opts libbpf: %s size (%zu) is too small libbpf: %s has non-zero extra bytes libbpf: ringbuf: failed to get map info for fd=%d: %d libbpf: ringbuf: map fd=%d is not BPF_MAP_TYPE_RINGBUF libbpf: ringbuf: failed to mmap consumer page for map fd=%d: %d libbpf: ringbuf: failed to mmap data pages for map fd=%d: %d libbpf: ringbuf: failed to epoll add map fd=%d: %d ring_buffer_opts libbpf: ringbuf: failed to create epoll instance: %d libbpf: user ringbuf: failed to get map info for fd=%d: %d libbpf: user ringbuf: map fd=%d is not BPF_MAP_TYPE_USER_RINGBUF libbpf: user ringbuf: failed to mmap consumer page for map fd=%d: %d libbpf: user ringbuf: failed to mmap data pages for map fd=%d: %d libbpf: user ringbuf: failed to epoll add map fd=%d: %d user_ring_buffer_opts libbpf: user ringbuf: failed to create epoll instance: %d libbpf: %s size (%zu) is too small libbpf: %s has non-zero extra bytes bpf_linker_opts libbpf: libelf initialization failed: %s libbpf: failed to create '%s': %d libbpf: failed to create ELF object: %s libbpf: failed to create ELF header: %s .strtab libbpf: failed to create STRTAB section: %s libbpf: failed to create STRTAB data: %s .symtab libbpf: failed to create SYMTAB section: %s libbpf: failed to create SYMTAB data: %s bpf_linker_file_opts .debug_ .text .rel .BTF .BTF.ext libbpf: linker: adding object file '%s'... libbpf: failed to open file '%s': %d libbpf: failed to parse ELF file '%s': %s libbpf: failed to get ELF header for %s: %s libbpf: unsupported byte order of ELF file %s: %s libbpf: unsupported kind of ELF file %s: %s libbpf: failed to get SHSTRTAB section index for %s: %s libbpf: failed to get section #%zu header for %s: %s libbpf: failed to get section #%zu name for %s: %s libbpf: failed to get section #%zu (%s) data from %s: %s libbpf: multiple SYMTAB sections found, not supported libbpf: failed to parse .BTF from %s: %d libbpf: failed to parse .BTF.ext from '%s': %d libbpf: unrecognized section #%zu (%s) in %s VVVlibbpf: ELF is missing SYMTAB section in %s libbpf: ELF is missing section headers STRTAB section in %s libbpf: ELF section #%zu has empty name in %s libbpf: ELF section #%zu alignment %llu is non pow-of-2 alignment in %s libbpf: ELF section #%zu has inconsistent alignment addr=%llu != d=%llu in %s libbpf: ELF section #%zu has inconsistent section size sh=%llu != d=%llu in %s libbpf: ELF section #%zu has unexpected size alignment %llu in %s libbpf: ELF section #%zu (%s) has unrecognized type %zu in %s xPbblibbpf: ELF SYMTAB section #%zu points to missing STRTAB section #%zu in %s libbpf: ELF SYMTAB section #%zu points to invalid STRTAB section #%zu in %s libbpf: ELF sym #0 is invalid in %s libbpf: ELF sym #%d in section #%zu has unsupported symbol binding %d libbpf: ELF sym #%d in section #%zu has unsupported symbol visibility %d libbpf: ELF sym #%d is invalid extern symbol in %s libbpf: ELF sym #%d in section #%zu points to missing section #%zu in %s libbpf: ELF relo section #%zu points to invalid SYMTAB section #%zu in %s libbpf: ELF relo section #%zu points to missing section #%zu in %s libbpf: ELF relo section #%zu name has invalid name in %s libbpf: ELF relo section #%zu points to invalid section #%zu in %s libbpf: ELF relo #%d in section #%zu has unexpected type %zu in %s libbpf: ELF relo #%d in section #%zu points to invalid symbol #%zu in %s libbpf: ELF relo #%d in section #%zu points to missing symbol #%zu in %s libbpf: sec %s types mismatch libbpf: sec %s flags mismatch libbpf: sec %s entsize mismatch libbpf: failed to init section '%s' libbpf: ELF sections %s are incompatible license version libbpf: non-identical contents of section '%s' are not supported libbpf: can't fetch symbol name for symbol #%d in '%s' libbpf: global '%s': incompatible forward declaration names '%s' and '%s' union struct libbpf: global '%s': incompatible %s forward declaration and concrete kind %s libbpf: global '%s': incompatible BTF kinds %s and %s libbpf: global '%s': incompatible %s names '%s' and '%s' libbpf: global '%s': incompatible %s '%s' size %u and %u libbpf: global '%s': incompatible func '%s' linkage libbpf: global '%s': incompatible var '%s' linkage libbpf: global '%s': incompatible number of %s fields %u and %u libbpf: global '%s': incompatible field #%d names '%s' and '%s' libbpf: global '%s': incompatible field #%d ('%s') offsets libbpf: global '%s': incompatible number of %s params %u and %u libbpf: global '%s': unsupported BTF kind %s ( 2 2 ( t 2 2 type key_size key type value_size value type max_entries map_flags numa_node pinning inner map %s.inner libbpf: global '%s': map %s mismatch libbpf: global '%s': invalid map definition type [%d] libbpf: global '%s': invalid map definition libbpf: global '%s': invalid dst map definition libbpf: BTF info is missing for global symbol '%s' libbpf: only extern variables and functions are supported, but got '%s' for '%s' .maps libbpf: failed to find BTF info for object '%s' libbpf: global/extern '%s' BTF is ambiguous: both types #%d and #%u match libbpf: failed to find BTF info for global/extern symbol '%s' libbpf: externs without BTF info are not supported .extern libbpf: failed to find matching ELF sec '%s' libbpf: conflicting non-weak symbol #%d (%s) definition in '%s' libbpf: sections %s are not compatible libbpf: relocation against STT_SECTION in non-exec section is not supported! libbpf: failed to find symbol for variable '%s' in section '%s' libbpf: failed to append BTF type #%d from file '%s' libbpf: failed to find new ID mapping for original BTF type ID %u libbpf: global '%s': section mismatch %d vs %d libbpf: global '%s': failed to resolve size of underlying type: %d libbpf: can't find section '%s' referenced from .BTF.ext libbpf: incompatible .BTF.ext record sizes for section '%s' libbpf: failed to finalize ELF layout: %s libbpf: failed to write ELF contents: %s libbpf: failed to add consolidated BTF type for datasec '%s': %d libbpf: .BTF.ext generation failed: %d libbpf: BTF dedup failed: %d libbpf: failed to write out .BTF ELF section: %d libbpf: failed to write out .BTF.ext ELF section: %d libbpf: mismatch in func_info record size %zu != %u libbpf: mismatch in line_info record size %zu != %u libbpf: mismatch in core_relo_info record size %zu != %u libbpf: failed to parse final .BTF.ext data: %d libbpf: Total maps exceeds %d close(%%d) = %%d libbpf: nr_progs %d/%d nr_maps %d/%d mismatch libbpf: gen: finish %d libbpf: gen: load_btf: size %d btf_load size %d libbpf: gen: map_create: %s idx %d type %d value_type_id %d map_create %s idx %d type %d value_size %d value_btf_id %d %s%s libbpf: gen: find_attach_tgt %s %d find_by_name_kind(%s,%d) kallsyms_lookup_name(%s,%d) libbpf: BTF fd off %d for kfunc %s exceeds INT16_MAX, cannot process relocation func (%s:count=%d): imm: %%d, off: %%d func (%s:count=%d): btf_fd var t=%d w=%d (%s:count=%d): imm[0]: %%d, imm[1]: %%d var t=%d w=%d (%s:count=%d): insn.reg ld64 call libbpf: gen: emit_relo (%d): %s at %d %s libbpf: gen: prog_load: type %d insns_cnt %zd progi_idx %d prog_load %s insn_cnt %d libbpf: gen: map_update_elem: idx %d update_elem idx %d value_size %d libbpf: gen: populate_outer_map: outer %d key %d inner %d populate_outer_map outer %d key %d inner %d libbpf: gen: map_freeze: idx %d map_freeze byte_off byte_sz field_exists signed lshift_u64 rshift_u64 local_type_id target_type_id type_exists type_matches type_size enumval_exists enumval_value unknown pyʏӏ libbpf: unexpected kind %s relocated, local [%d], target [%d] &Zs 0 %d%n libbpf: prog '%s': relo for [%u] %s (at idx %d) captures type [%d] of unexpected kind %s Zəəə libbpf: prog '%s': relo %d at insn #%d can't be applied to array access libbpf: prog '%s': relo %d at insn #%d can't be satisfied for bitfield @p7libbpf: prog '%s': relo #%d: unrecognized CO-RE relocation %s (%d) at insn #%d libbpf: prog '%s': relo #%d: substituting insn #%d w/ invalid insn libbpf: prog '%s': relo #%d: unexpected insn #%d (ALU/ALU64) value: got %u, exp %llu -> %llu libbpf: prog '%s': relo #%d: patched insn #%d (ALU/ALU64) imm %llu -> %llu libbpf: prog '%s': relo #%d: unexpected insn #%d (LDX/ST/STX) value: got %u, exp %llu -> %llu libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) value too big: %llu libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) accesses field incorrectly. Make sure you are accessing pointers, unsigned integers, or fields of matching type and size. libbpf: prog '%s': relo #%d: patched insn #%d (LDX/ST/STX) off %llu -> %llu libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) unexpected mem size: got %d, exp %u libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) invalid new mem size: %u libbpf: prog '%s': relo #%d: patched insn #%d (LDX/ST/STX) mem_sz %u -> %u libbpf: prog '%s': relo #%d: insn #%d (LDIMM64) has unexpected form libbpf: prog '%s': relo #%d: unexpected insn #%d (LDIMM64) value: got %llu, exp %llu -> %llu libbpf: prog '%s': relo #%d: patched insn #%d (LDIMM64) imm64 %llu -> %llu libbpf: prog '%s': relo #%d: trying to relocate unrecognized insn #%d, code:0x%x, src:0x%x, dst:0x%x, off:0x%x, imm:0x%x <anon> <%s> [%u] %s %s ::%s = %d ::%s = %u ::%s = %lld ::%s = %llu .%s [%u] ( : %s%d @ offset %u.%u) @ offset %u) <?> libbpf: prog '%s': relo #%d: parsing [%d] %s %s + %s failed: %d libbpf: prog '%s': relo #%d: %s libbpf: prog '%s': relo #%d: <%s> (%d) relocation doesn't support anonymous types libbpf: prog '%s': relo #%d: error matching candidate #%d %s: %d non-matching matching libbpf: prog '%s': relo #%d: %s candidate #%d %s libbpf: prog '%s': relo #%d: field offset ambiguity: %u != %u failure success libbpf: prog '%s': relo #%d: relocation decision ambiguity: %s %llu != %s %llu libbpf: prog '%s': relo #%d: no matching targets found _HyJJr__bpf_usdt_specs __bpf_usdt_ip_to_spec_id libbpf: usdt: failed to find USDT support BPF maps, did you forget to include bpf/usdt.bpf.h? libbpf: usdt: unrecognized ELF kind %d for '%s' libbpf: usdt: attaching to 32-bit ELF binary '%s' is not supported libbpf: usdt: unsupported ELF class for '%s' libbpf: usdt: unsupported type of ELF binary '%s' (%d), only ET_EXEC and ET_DYN are supported libbpf: usdt: ELF endianness mismatch for '%s' libbpf: usdt: discovered PHDR #%d in '%s': vaddr 0x%lx memsz 0x%lx offset 0x%lx type 0x%lx flags 0x%lx libbpf: usdt: failed to find PT_LOAD program headers in '%s' /proc/%d/root%s libbpf: usdt: failed to get absolute path of '%s' (err %d), using path as is... /proc/%d/maps re libbpf: usdt: failed to open '%s' to get base addr of '%s': %d libbpf: usdt: discovered segment for lib '%s': addrs %zx-%zx mode %s offset %zx %zx-%zx %s %zx %*s %*d%[^ ] libbpf: usdt: failed to find '%s' (resolved to '%s') within PID %d memory mappings .note.stapsdt libbpf: usdt: no USDT notes section (%s) found in '%s' libbpf: usdt: invalid USDT notes section (%s) in '%s' libbpf: usdt: failed to process ELF program segments for '%s': %d .stapsdt.base libbpf: usdt: failed to find ELF program segment for '%s:%s' in '%s' at IP 0x%lx libbpf: usdt: matched ELF binary '%s' segment [0x%lx, 0x%lx) for '%s:%s' at IP 0x%lx is not executable libbpf: usdt: attaching to shared libraries without specific PID is not supported on current kernel libbpf: usdt: failed to get memory segments in PID %d for shared library '%s': %d libbpf: usdt: failed to find shared lib memory segment for '%s:%s' in '%s' at relative IP 0x%lx exec lib libbpf: usdt: probe for '%s:%s' in %s '%s': addr 0x%lx base 0x%lx (resolved abs_ip 0x%lx rel_ip 0x%lx) args '%s' in segment [0x%lx, 0x%lx) at offset 0x%lx libbpf: usdt: kernel doesn't support USDT semaphore refcounting for '%s:%s' in '%s' libbpf: usdt: failed to find ELF loadable segment with semaphore of '%s:%s' in '%s' at 0x%lx libbpf: usdt: matched ELF binary '%s' segment [0x%lx, 0x%lx] for semaphore of '%s:%s' at 0x%lx is executable libbpf: usdt: sema for '%s:%s' in %s '%s': addr 0x%lx base 0x%lx (resolved 0x%lx) in segment [0x%lx, 0x%lx] at offset 0x%lx libbpf: usdt: failed to set USDT spec #%d for '%s:%s' in '%s': %d libbpf: usdt: IP collision detected for spec #%d for '%s:%s' in '%s' libbpf: usdt: failed to map IP 0x%lx to spec #%d for '%s:%s' in '%s': %d libbpf: usdt: failed to attach uprobe #%d for '%s:%s' in '%s': %d libbpf: usdt: failed to attach uprobe multi for '%s:%s' in '%s': %d stapsdt libbpf: usdt: too many USDT arguments (> %d) for '%s:%s' with args spec '%s' libbpf: usdt: unsupported arg #%d (spec '%s') size: %d libbpf: usdt: unrecognized register '%s' %d @ %ld ( %%%15[^)] ) %n %d @ ( %%%15[^)] ) %n %d @ %%%15s %n %d @ $%ld %n libbpf: usdt: unrecognized arg #%d spec '%s' /sys/bus/event_source/devices/uprobe/format/ref_ctr_offset rip eip rax eax ax al rbx ebx bx bl rcx ecx cx cl rdx edx dx dl rsi esi si sil rdi edi di dil rbp ebp bp bpl rsp esp sp spl r8 r8d r8w r8b r9 r9d r9w r9b r10 r10d r10w r10b r11 r11d r11w r11b r12 r12d r12w r12b r13 r13d r13w r13b r14 r14d r14w r14b r15 r15d r15w r15b libbpf: elf: failed to init libelf for %s libbpf: elf: failed to open %s: %s libbpf: elf: could not read elf from %s: %s libbpf: elf: failed to get ehdr from %s: %s libbpf: elf: failed to find symbol table ELF sections in '%s' libbpf: elf: failed to get symbols for symtab section in '%s': %s libbpf: elf: failed to get verdef ELF section in '%s' libbpf: elf: ambiguous match for '%s', '%s' in '%s' libbpf: elf: symbol address match for '%s' in '%s': 0x%lx should not be 0 in a shared library try using shared library path instead libbpf: elf: '%s' is 0 in symtab for '%s': %s libbpf: elf: failed to find symbol '%s' in '%s' libbpf: elf: ambiguous match found '%s@%lu' in '%s' previous offset %lu GPL libbpf_nametest libbpf_global libbpf: Error in %s():%s(%d). Couldn't create simple array map. libbpf_mmap libbpf_det_bind / det_arg_ctx BPF program name global variables minimal BTF BTF functions BTF data section and variable BTF global function ARRAY map mmap() BPF_PROG_LOAD expected_attach_type attribute bpf_probe_read_kernel() helper BPF_PROG_BIND_MAP support module BTF support BTF_KIND_FLOAT support BPF perf link support BTF_KIND_DECL_TAG support BTF_KIND_TYPE_TAG support memcg-based memory accounting BPF cookie support BTF_KIND_ENUM64 support Kernel using syscall wrapper BPF multi-uprobe link support kernel-side __arg_ctx tag BTF DATASEC names starting from '?' libbpf: Detection of kernel %s support failed: %d probe_kern_global_data int int x a int x a x .data x ?.data float tag tag probe_prog_bind_map int enum64 a b arg:ctx L L a L a a a a a a a ; L a a L ] r r r r r r r r r * r r r r r libbpf: base BTF id [%d] maps to invalid distilled base BTF id [%d] libbpf: distilled base BTF type '%s' [%u], size %u has multiple candidates of the same size (ids [%u, %u]) in base BTF libbpf: distilled base BTF type '%s' [%d] is not mapped to base BTF id :+):+:+ * *)3):+:+:+:+:+:+:+:+) libbpf: type [%d], kind [%d] is invalid for distilled base BTF; it is anonymous libbpf: type [%d] in distilled based BTF has unexpected kind [%d] libbpf: string '%s' [offset %u] is not mapped to base BTF .A @ P? 0A A C @@ eA N@ Y@ ? ? f g n rh|? @ @ @ i@ r@ @ @ ??333333?ffffff?{Gz? ?90 :0 {Gz? ?? j@ư> 0C ?33333333UUUUUUUU >@ ? )@ 9@ $@ K@ @ @ @? ?? ? ? 1@ `]@ 0k@ s@ z@ v@ @ ܄@ @333333? .@333333? & .> R@ I@ 4@00000000 @ h Z ! 4 @ L >.. event-hyphen event-two-hyph test__syscall_openat_tp_fields p78p7h88p7p7p7p777 print_hists_out print_hists_in D`DDDD write_mmap write_comm leafloop sqrtloop brstack datasym Q / F / F - M m 1 Q q ! A a = ] } C C @ @ ! " Y s s s s ? @ # È 2 b " " "4 4 " V V c c c c 3 3 ! ! S " S? " ? bp_2 bp_1 v = 88((d,4,,+d+,, P`F`F`F G`F`F`F`F`FM`F`F`FF`F`F`F`F`F`F`F`F`F`F`F`F`F G`F`F`F`F`F`F`F`F`F`F`F`F`F`F`F`F`F`F`FH`F`F`F`F`F`F`F`F`F`F`F`F G`F GJ`F`F`F`F[J`F`F`FH`F K`F`F`F`FTK9K`F`F`F`F`F`F`F`F`F`F`F`F`F`F`F`F`FGK`F`FK`FrK`F LKK`FHBJG G"JwIUIPDDD5EDDDDD"LDDDDDDDDDDDDDDDDD5EDDDDDDDDDDDDDDDDDDD GDDDDDDDDDDDD5ED5EHDDDDHDDD8FDHIDDDD|IaIDDDDDDDDDDDDDDDDDE/IDDIDID3J&JIDGjHE5EJHG}GNJJJ]CJJJJJ`DJJJNJJJJJJJJJJJJJ]CJJJJJJJJJJJJJJJJJJJNJJJJJJJJJJJJ]CJ]CGJJJJFJJJ`DJmGJJJJGGJJJJJJJJJJJJJJJJJCTGJJGJGJXHKHGJ+EFC]CoFEE @(PPPPPPPPPPPPPPPPPPPPPPPPPPPPPJ83HHHHHHHHHHHHHHHHHHHHHxHHHHHHHHHHHHHHHHHHH``````````HHHHHHHHHHHhHHHHHHHHHHdHH-HHHHHHHHHHHHuHHHHHHHhMHHHHH- q Quit h/?/F1 Show this window UP/DOWN/PGUP PGDN/SPACE Navigate q/ESC/CTRL+C Exit browser or go back to previous screen For multiple event sessions: TAB/UNTAB Switch events For symbolic views (--sort has sym): ENTER Zoom into DSO/Threads & Annotate current symbol ESC Zoom out + Expand/Collapse one callchain level a Annotate current symbol C Collapse all callchains d Zoom into current DSO e Expand/Collapse main entry callchains E Expand all callchains F Toggle percentage of filtered entries H Display column headers k Zoom into the kernel map L Change percent limit m Display context menu S Zoom into current Processor Socket P Print histograms to perf.hist.N t Zoom into current Thread V Verbose (DSO names in callchains, etc) z Toggle zeroing of samples f Enable/Disable events / Filter symbol by name h/?/F1 Show this window UP/DOWN/PGUP PGDN/SPACE Navigate q/ESC/CTRL+C Exit browser or go back to previous screen For multiple event sessions: TAB/UNTAB Switch events For symbolic views (--sort has sym): ENTER Zoom into DSO/Threads & Annotate current symbol ESC Zoom out + Expand/Collapse one callchain level a Annotate current symbol C Collapse all callchains d Zoom into current DSO e Expand/Collapse main entry callchains E Expand all callchains F Toggle percentage of filtered entries H Display column headers k Zoom into the kernel map L Change percent limit m Display context menu S Zoom into current Processor Socket i Show header information P Print histograms to perf.hist.N r Run available scripts s Switch to another data file in PWD t Zoom into current Thread V Verbose (DSO names in callchains, etc) / Filter symbol by name 0-9 Sort by event n in group h/?/F1 Show this window UP/DOWN/PGUP PGDN/SPACE LEFT/RIGHT Navigate q/ESC/CTRL+C Exit browser evsel__get_arch __symbol__inc_addr_samples 4$tTd<$llt\ԕϕ{hUޙ˙ܖ add_config_item add_section collect_config (((((AAAAAABBBBBB hAAAA(AHA symbol__disassemble d dddd4LdĀ܀d| evlist__prepare_workload 0 ( !! "! " ! ! !787 7666p6P6 64545 |V}J}>}2}&}}}}|||hzzzzzxz{>{||{{{|||J|>|2|&|b|V|f`Ԙ\< |< ,|\< , | XHH8(xhXxhX(8(((((((((((((Ht ,<L\l| ,4D,T,$ dt | l \ L < , L < , | l \ | l \ L < , | l \ L < d |l\L<, |l\L<, L<, l\|0 p`P@p`P@0 hp`P@0 P@0 p`hXH8(xhXH8(xxhhXXHH88((`LPLPLPLPLLPLPLPLpLPLLPLPLPLPLPLPLLPLPLPLPLPLPLPLPLPLPLPLPLPL`LPLPLPLPLLPLPLPLpLPLLPLPLPLPLPLPLL See 'perf help COMMAND' for more information on a specific command. perf [--version] [--help] [OPTIONS] COMMAND [ARGS] ~~}}~H~~~ X} ~ ~}}(~(~kgvVjlBDfuxbdGMKm o @@((@@@@@0000 symbol__new symbols__fixup_end perf_event__process_tracing_data do_write_feat write_tracing_data write_build_id write_auxtrace build_mem_topology 6.11.11 get_tls_callchain_cursor lXXX$YDYdYYYW4X 0H`pp0Pp maps__set_modules_path_dir machine__process_text_poke pstack__pop pstack__push pstack__remove JHJ(KK@KJ`J8J JJIIIIPI8ITKJi|hTh4hhhhhlg4ffeete|d|dTeeddd4e prefetch_event xXHh _1HHu$$%K% V ((`((()!*"b""" #B#z###=$z sgu$$$ 2!!@))%z$]6 o 5 n R A)bJ I% DD&$+/ / +z+f+/ / / / / / +/ / +/ / / R+/ / / / / / / / / / >+/ / ,/ / +/ / ,/ / / / / / / / + H N M$ & . $ L. . H & + + + + + / KG / / 6 - - - - - l C G 6 C Jl 0 < b b ? 0 )< I? i ? )0 , , , , , ? H # # # # # 7 i # # # # i 7 7 7 G8 # # # # # # F7 9 7 8 S, 4 M M M M M ED9 8 9 4 9 9 y C4 4 4 y y 8 = 4 B4 4 ; 4 8 ; 4 = 4 B S> ; 4 Y > AY 4 : = B = > ; ; >@ :Y : Y E B > > +T= @ > A z : E : ; z z F > : @ A @ { B E @ : : F @ : T A { A : *F F E { A E F A D w w w w w )D D D D D D $ D D D D #"D D D D D D D N N N N N N N N N ! N N N N N N O O O $O O $ O O O O V V V . V V .V V V V V V o o o o o o o o o o o o o o o ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ g e dca ` _ ^]\[ZYX W VU3 - , + * )(&%$# " ! ~ } |B A@?=< ; BB:9 8B765 4 21B 0/.-, + *CDF ) CDF( '& %#"!CDFD D F GCHGHJGHGJHJ88888IEK8888JIEK888888AAALIEKEAMAILANAEOMAKPQLANOLRMPQNSORPQMTSMRONVRWTPQSUPXSUVWTYZUsXT[rVqWpYZoU\X[mW^lX]YZk\YV[Z^[_]j`Ya\ihcg^_^]`faebdccbd_ef`hab\ac]dbefah`_b^_]id[efchjZkYmiXlWhnVjdkemfilipnRojqkomwtlpQnoPqONxwtjxplMoLqmxwt ntwp xqrrrrruvrrrr uvrrrrrrsssssuvssssyzuvssssssyzyzz|||||||||||||||}}}}}}}}}~=<;:97653210/.-,+*('&%$#"! $ $ $ $ !" # %!} "t s #r q %p !(" '&n #"&)%,(m k '&j h g !)f ,e (d #'&&%'*)&,*+(-c ./(*+++0+a -)./` ,*_ 10] +\ -3./[ 2.1Z 04/53X W -2U 6174T 5S 38R Q 26P 7K 415982J 9:6;75 6% 9" 878:! ;5<=4>9? @:A;<= > ?;:@ A <= > ?<?@ A >@E =BBBBB E BBBB EBBBBBBCCCCCDFGCCCC EHIDFGCCCCCCHI DFGGDvF HI v IvHJJJJJwxvJJJJ wx JJJJJJKKKywxz | K{ KxyK zK| {Kw yKUz |U}{y } UU}UUzUU|{U\ }\ \ \\ \\\\} \nnnnnnnnn nnnnnnuuu~ ~ u u ~uu u ~u ~ F GF G FHG GF H H>>>>>IJK>>>> H IJK>>>>>>EEELIJK KJEI EMLE NEOQ EPM LEN OQ P M RSN OQOLNP ORS PTVMUWQXUYRSZTVSUW XRY Z TVTUW[X\Y]WZ^a_ [ \ ]V ^a_XY [Z\`] ^a_ b ^c` [_d e\b]fc `fgdae hbf`c ig djeh f ki glj chgmnkdiel jopqmnhkwitluopq mn w t u opq mlvw tou n uv w qrrrrrtxvrrrr x rrrrrrsssssxyvssss xy ssssss yzzzzz zzzz zzzzzz{{{ { { { { { { 6 <6 <66 < 8 <8 8 8 77 9 79: 9 7 A : A 9 :22222;A=2222 A;:=222222555>;?= @B5D 5 >5? 5@B D5;=C>5? F@BEDHGC F E>HG C? @BFIJELHG FGKMIJCL ENHOkKM IJ LvNIOk KM K vKN Ok JPPPPPvnRPPPPk v nRPPPPPPQQQQQnRnQQQQR jQQQQQQSSSSSj lSSSS j jlSSSSSSTTTs ls To T sT T l oT sTfffffmo ffffo m pffffffiiiqmp mrit iuqi pi r tiwu qi px rytwrutz{ xuy ~wz{qx y~ z{z w y~ {||||| ~|||| ||||||}}}}} }}}} }}}}}} % & % '(& , -. % %'( &,&-. '( ,'-. , -. (000000000000011111111111112 2 223 3 33 3 3344444444444445 5 55 55556 6 67777 7777777888888888888899999 9999; ;; ;;;<<<<<<<<<<<<<==== == ====? ? ???@@@@ @@ @@@@////////////////////////////////////////////////////////// ! " # $ % & ' ( * L I R S * + , - - - - . Q L I T * M M M M M M M M M M V L W j X Y ` k q L l y c r / y y / / * J * a t + , - - - - . J * N Z v v v v v [ z { b z z \ ] { ^ w w w w w _ / / / 0 1 2 3 0 0 0 4 5 6 0 7 0 0 0 8 9 : ; < = 0 5 > 0 5 ? @ A B C 0 D E F G 0 0 0 0 0 ' ( O O O L e { P O O L | O O h O f | L O \g w w w w w { L 4h o o o o o L S o o o o S ] | L o o o o p o { L | Ux L M M M M M D L | U t~ ~ ~ L L ~ L ~ ~ | ~ L L | ~ L L ~ L L | | L >L | L L L U | L L | L L | L L | S L | S L UL U L w w w w w | +L _" &*`L | L L L )$%# | &| L L L L | " | L L !L L | | d S e ? L L ?? L L | | L L L { L L | L L L | L | L | | | L | L L L L L L L L L L | | | | L | L L L L L L | L | | L L L L L L L | | | | L L ^ L L L L L | | L L | L L | | L L L L L | | L L L S L | L L | L L | | L U| L L S gcL L bBa| `_^]\[ZL L L | L L YXPC| L | | DL WEL L VL L O| UQT310/ | L .L L ! S-L ,+L L R| | Y*)L g| ('L L L %$| L L #U| ! L 88888L L 8888 V | Z888888AAAL L L L L AWAL | A| A| | L AX| L AL L L L | ]L L L [| \L | | ^FL G_L L L L L HIJKLM| | | N ` dL L L L AAAL | L aAeAL | AL | AL L bAf| L AL L | | cL L L L L | L L | | | | L L hL L L L iL kL | L jl| L m| L | nL o| pL L qrrrrrL L rrrrwx| rrrrrrsssssL L L ssssyL L L | | ssssss| | | L L uL L L v~}z|||||L L |||||CBA@| ?| ||||||}}}L L =L <;}:9}8| }76}543}210L }L L L /. -| | | L L L L ,+L *| )L L (| L L L | '$| L L #| | "! L L L | L L L | S L L L | L L L | S | L L L | | L L L | | L L L | L L L L | L | L | L L L L L | L | | L | L L L L L L L | L | | | | L L L L L L L L L | L L | | | L | L | L L L L L L L L | L | | L | | L L S L | sL L rqpomL lL L kjihgf| | L L edcL L ba| | ^[ZYXWL L VL L | | UTSRQPL L ONS ML L L L | | | L L L L L L L | L | | | L | L L L L L L L L L | L | | | L | L | L L L | L L L L L L L L | !| | | | L "L L L $(L L L | L | L &L L L L #L | L | %| | )| | 'L L L L L L L L L | +L | | L */-L L L | S L L | 0,.| | 1L L L L L 7L 4L L 2L | | | ;L | 53L L | S L L L | L 6| | 9L L L L L L L 8:| <=L | | L L L L E| >L L ?| | | AL L ~L L L @BBBBB| L BBBBGt=vDIL | BBBBBBCCCCCL L L CCCCF<;:9| 7| CCCCCCS 654L 3L 2HJJJJJL L L JJJJ1S 0/| | | JJJJJJKKKL L L L w.K-,KS | K+*K)('&K%$zL KnnnnnL L L nnnn#"| | | nnnnnnuuuL L L L xyuL {uL | u L uL L | uL | L u| | | |L L | { L }L L L L L | L L L | | ~L | | L L L L L L L L L | | | | | L L L L L L L L L L | L | | | | L L | L L L L L L | L L L | S | L L L | S | L L L | | L L L | L L L L { s | n L | m | L L L L L i d L L L L | | U | L | | /| //L L /L /L L /L //L /////| ////////L L L L /L L L | | | | | | /L L L L //L L L ////| // L L L /////| | /L L L L /L /L /| /| | //| //L L /L L L ///L //| | //L ///L /L //// | //!L L /////L | L | /L L ///| L L | /////L | //L /L /L //L //L L | | L | | L L L L L | /L /L L /L | | /| L | /L | /L L L L L L | L L | /L | //L L L L | /L | /L | /| /| /L /L L L L L L L L /L /| | | | /| //L L L L L L L L L L | /| // L L | /| | L L L L | | /L /L L L | /| /L L /L /L | L L ///| | /L L /L / ////L | /L //L L L L L | | | | | //L /////L L L L // FL L //G//| | L /L L ///H//| ////////L >>>>>L L L >>>>//K//| | | >>>>>>EEEL L L L /JL EI/EL | E/L E/| /MEL | /L E| /L /L /L | LL L /L L | OL | /L L | N| /L L L | PL /| QL /L | R| /L /T/L /SL L L /L L L U WL | | /VL | | YL L L | XL L /| /L L | | | ZL \L L /L /L /L L L ^/| | [L /| ]L /L L L _L L | daL | `| | | cbL L L eL L L /L L L L | | /L | | h//fg| /L L | /L L kiL /L L jL /L L L /l| n| //| /m| | /L /L oL //L p/L L | t/v/qrrrrr//L rrrr/////w/urrrrrrsssssL L /ssss/////| | /ssssss////L L L /x//yzzzzzL | /zzzz/////| /L zzzzzz{{{L L ///{//{/| {//{////{///L {L L L ////| | | L L L L //L | /L L L //L | /L | /| | ///| /L /L L L /L L L /| | /L L L L L L L L L | | | | /| | //| /L L L L L L L L L L L L L //| /| /| /| | | /L L L L //L L L /L /L | /L /L | L | /L L | | /L L | L /L | /L L L | //L /L | /L L | /0L L L | L | /L L L L | | L L L L L | | | /L L /| /| /| /L L L /L L /L L ////| ///L L //////| /L L /////| /L ////L L | //////| /L L L ////L //| /////| //L L L L ////| | L L L L /L L L | | /L | /| L | /L L /| L L L | /L L L L L L | /L L | /| | /| /L L /| /L L L L L L | L L | /L //| /L L | /L | /L //L L | /L L /L L | L | /L | /L | L L | /L L /L | /L L L | /L /| / L L | | L L L L L | /L L /| /| /L | //L /L L /L | /L L L | //////L L L | | L /////| | /L L //3L L L //7///| L L ///L /| /6/| /L L ///L | ///////L L L | /////L 8/| L ////| ///L 22222L L 92222:////| /222222555L L L L /L /5/5/| 5| | 5| //L 5/</L 5L L L L ;| =L >L L L L | //L L | /| | | | /L ?@/| /L L L L L L L L /CL L L | /L /E| | AB| /| DL | /L FL L KL L /L L JL | /L L L | /HI| /GL L | | | /L L//L L | //L L L ///O/| jL M//RNPPPPPL /L PPPP//////n| PPPPPPQQQQQ/L /QQQQl//////L QQQQQQSSSSS| /L SSSS//////L | SSSSSSTTTL //L /k/TL /T/| T//T///| T//L TfffffL L L ffff////q| | ffffffiiiL L L L /L L iL /i/| i| /i| | /| imL L iL /L L L L L L L | ////| //| | | /L o/prL L L L L L L //uvL L | | s| /tL wL L | | /L L /L L | x| | /L L /z//| {L /L L /y|||||L L L |||| ////| | ||||||}}}}}L L }}}}~//////L }}}}}}| /L /////L | L //L //L //| ////| ///L L L /////| /L L L | //L L /L | /L /| /| L | /L /L /L L L | L L L /| L | /L L L L | | L | /L | | | /L L /L /L /L L ////////L //////| /L /////////L L L /////| | | L L L L ///L /| /////| /L /L //////L L | /L /L /L //| L | | //| /L /L L /L L L | ///////| //L /L L //////| /L L L /////| | L L L //////| L L L /L L L | /| | | | /L /L L /L L //L L L L L | /| | //| /| /L L L /L ///L /L ///| L //L | ////////L /////////L | ////////L L | /L //L L L L | | /| | /L L L L L /L /L L | /| /| | ///L L /L /L /L L | | //////////L L /L /////| /L L //////| /L L //L L /L | /| | /| /L ///////L L L L //L | //L L L | L | | | /L L L / L /L L L L L | | L | /| /L /| /L L /| /L L | //L ////L ///L L L L L L | /| | | | /L L L /L //L L L L L | / | ///| /L /| /L %L L / &L | //L L L | /L (L L /L ',| | /L | -| | /////L L //L L L // ///.) ) ) ) ) ) ) ) ) ) ) ) ) H H H H H H H H H H H H H K ////K /K K L /L /L L /L /L L u u u u u u u u u u u u u { /{ /{ { /{ { { { } /} /} / / | /| | /| | | //@//@/@@@{{{{/{{/{{{{ ///////////////////////////////////////////////////////// / 00/ 11///23//33//3 33 33 33333 333 ////4////5//654 4 554 554 5555554 5554 7/893333333333333V 3333333333333333333333o 3333///://5;64 5555555~ 55~ 5555555555555555555555555~ D 555557<88=/93333333333333333333333333333333333 3333>//?~ 5555555~ 555555555555555555555555555555555D D 55555<@=333333333333333333333333333333333/333333333A/?~ 5555555555555555555555555555555555555;55555555555555555@33333333333333333333333333333333333333333333B~ 555555555555555555555555555555555555555555555555555555333333333333333333333333333333333333333333333C~ 5555555555555555555555555555555555555555555555555555555333333333333333333333333333333333333333333D~ 555555555 55555555 55555555555555555555555555555555555333333333333333333333333333333333333333333333333E~ 55555555555555555555555555555555555555555555555555555553333333333333333333333333333333333333333333F~ 5555555555555555555555555555555555555555555555555533333333333333333333333333333333333333333G~ 55555555555555555555555555555555555555555555533333333333333333333333333333333H~ 555555555555555555555555555555553333333333333333333333333333I~ 555555555555555555555555555333333333333333333333J~ 555555555555555555533333333333333333K~ 5555555555555553333333333333333L55555555555555533333333333333M5555555555553333333333N555555555333333333/555555553333335555555333335555533335555333555 /////////////////////////////// 8 l 7 D I D 3 + a W ; = 0 D v 5 W $q TA <L ]kJ{ bsj 3 2one t`s PA@VC; C=t E:46# , @y <,47;>?BUVYZ]hml{~ + $)We}e %*E;X(Ylbta "$%'7<YsBLg zQS \]OTLBJ 9<8;74#0 *( E #,6F?AHPQV`hesvx| +:ovwqfnGuNE S; D88F3]2Z=c'908& r+,opq ,-1.7<@AQVW|`ghf=5632"!!5 | $&'+5<>CGZYV_w|a~ ! ( ) H W cp { uz{~nlaY[T^LZBK4 8W+., = T U l o t q f * ! + 4 1 < ? E C G W Y Z [ ] o q w y z +- /+ : 8 7 O 9 U Z ^ e l p v t { * D P Q j y sr~rvzqDBA@?G:+ -)&N0"$ k v ! # 6 " > A F H L Q V \ ` g k q r z { | % " $:<@EBKPZ_abeyjt &=LvxjgfoeTc_Z\ICPK978BS! u% 0>Vai "<Ve0 V0dz-!GV GU sk $3\ k012HPu a xxf dbhR !#$*Lf,JEHH ; D08% M? 01- +34MYN bcdstz6 x~ }mH *5AMS^juX~UK8/%$ ~ _ W B !"#$%&'()*+,-./0123456789 # ' + . 1 5 8 ; ? B E H K N R U X [ _ b e g h j m p r u y } "&(*,/1368:<>ACEGIKMOQSUWY[]_acfhjmquy{} ""#$&()*+,-./0123456789:;<=>?@ABCDEFGHIJKMNOPQRSTUXZ\^`bdfhjlnprtvxz|~ !#%')+-/13579;=?ADFHJLNPRTVXZ\^`bdfjmoqsuwy{}~ #%')+-/13456789:<>?@ABCDEFGHIJKLMNOPQRSTUVWYZ[\]^_bdfhjlnptxz|~ "$&(*,.02468:<@BDFHJLNTVXZ\^`bdfhjlnprtvxz|~ !#'*,.02479;<=>?@ABDEFGHIJKLMOPQSTUVWXYZ[\]_`acefgijmoqsuwy{ !%')+-1468:<>@BDFHJLPSUXZ\]^_`abcefghijlmnopqrsuwy{|} !"#$%&'(*+,/13579;=?ACEGIKORTVXY[\]^_`bcdefhijmosuwy|~ ! $ & ( ) * , - . 0 2 6 8 : ; < = > @ B D F G H I K M O O ` ^ _ ] _ ^ _ U ^ _ X ^ _ W ^ _ R U ^ _ R U ^ _ Y ^ _ \ ^ _ T U ^ _ T U ^ _ T U ^ _ U ^ _ U ^ _ T U ^ _ U ^ _ U ^ _ T U ^ _ U ^ _ U ^ _ U ^ _ U ^ _ U ^ _ T U ^ _ U ^ _ U ^ _ U ^ _ T U ^ _ Z ^ _ [ ^ _ 3 _ _ 3 _ 1 3 _ 1 3 _ 3 _ - 3 _ + U ^ _ & X ^ _ ' W ^ _ ^ _ + T U ^ _ + T U ^ _ + T U ^ _ + U ^ _ + U ^ _ + T U ^ _ + U ^ _ + U ^ _ + T U ^ _ + U ^ _ + U ^ _ + U ^ _ + U ^ _ + U ^ _ + U ^ _ + T U ^ _ + U ^ _ + U ^ _ + U ^ _ + T U ^ _ _ _ _ U R U U T U U U U M U U U T U U U T U U U U U C U U U U U U U U U U U U U U U U U Q U Q U U U U U 0 / 1 . - + U + , + T U + U + U + U ( + M U + U + U + U + T U + U + U + T U + U + U + U + U + C U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + T U $ + Q U $ + Q U $ + Q U + U + U + U + U + U V S U T U U U U U U U M T U U U U U U U U U U U U U U U U U U U U U U U U U Q U Q U U U U U 2 . - + T U + U + U + U + U + U + U + U ( + M T U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U $ + Q U + U $ + Q U + U + U + U + U + U S U T U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U P U U U Q U U U U U U 2 . , + T U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + P + U + U + U + U + U + U + U + U + U + U $ + Q U % + U + U + U + U + U + U + U + U S U T U U U U U U U U U U U U U U U U U U U U U U U U U U U G U U U U U U U U U U Q U U U U U U 2 + T U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + G U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U $ + Q U % + U + U + U + U + U + U + U S U T U U U U U U U U U U U N U U U U U U U U U M U U U U U U U U 4 U U U @ U U U U U U U Q U U U U U U 2 + T U + U + U + U + U + U + U + U + U + U + U ) + N U + U + U + U + U + U + U + U + U + U + U ( + M U + U + U + U + U + U + U + U + U + U + 4 U + U + U + @ U + U + U + U + U + U + U + U + U + U + U + U + U + U + U $ + Q U % + U + U + U + U + U + U + U S U T U U U U U U U U N U N U U U U U U U U U U U U U U U U U U U U U U U U U U Q U U U U U U 2 + T U + U + U + U + U + U + U + U ) + N U ) + N U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U $ + Q U % + U + U + U + U + U + U + U S U T U U U U U U U U U U U U U U U U U U U N U U U U U : M U U U U U U U U U U U U U U U U U Q U U U U U U 2 + T U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U ) + N U + U + U + U + U + U + U + U ( + : M U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U $ + Q U % + U + U + U + U + U + U + U S U T U U U U U U U U U U U U U U U U U U U U U U U U U > U U U U U U U U U U U Q U U U U U I U 2 + T U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + > U + U + U + U + U + U + U + U + U + U + U + U + U + U + U + U $ + Q U % + U + U + U + U + U + U + I U S U T U U U U U U U U O U U U U U U U U U U K U U U < U U U U U U U U U U U D U U U Q U = U U U ? U 2 + T U + U + U + U + U + U + U + U * + O U + U + U + U + U + U + U + U + U + U + U + U + K U + U + U + U " + < U + U + U + U + U + U + U + U + U + U + U + U + D U + U + U + U + U $ + Q U % + U # + = U + U + U + U + ? U S U T U U U U U U O U O U U U U U N U U U U N U U U U U U U U U U U U Q U U J U 2 + T U + U + U + U + U + U * + O U * + O U + U + U + U + U ) + N U + U + U + U + U ) + N U + U + U + U + U + U + U + U + U + U + U + U + U + U $ + Q U % + U + U + J U S U T U U U U U U U U O U U U U U U 9 U U U U U U U U 7 U B U A U Q U U 2 + T U + U + U + U + U + U + U + U * + O U + U + U + U + U + U + U + 9 U + U + U + U + U + U + U + U + 7 U + B U + A U + U $ + Q U % + U + U S U T U U U U U U U U U ; N U U U U U H U U U U Q U U 2 + T U + U + U + U + U + U + U + U + U + U ! ) + ; N U + U + U + U + U + H U + U + U + U $ + Q U % + U + U S U T U U U U U U U U U U U U U U Q U U 2 + T U + U + U + U + U + U + U + U + U + U + U + U + U + U + U $ + Q U % + U + U S U T U U O U U U U U U L U U U U U Q U U 2 + T U + U * + O U + U + U + U + U + U + U + L U + U + U + U + U $ + Q U % + U + U S U U U U U E U U 8 U F U U U Q U U U 2 + U + U + U + U + E U + U + 8 U + F U + U + U $ + Q U % + U + U + U S U U U U U U U Q U U U 2 + U + U + U + U + U + U $ + Q U % + U + U + U S U U U U U U U U U 2 + U + U + U + U + U + U % + U + U + U U : U 6 U U U U + U + : U + 6 U + U % + U + U + U U U 5 U U U + U + U + 5 U + U + U U U U U + U + U + U + U U U U + U + U + U 8`HPXة@@@( xcqA,X\SLLSLzӾʾ`- *8Dгггггггггггггг8ȷXxг(xHг !!""#$$%%&&&&&&&''(()))*++++,-./0001123344445555555555566777 !#$%&'()*+,-./ 2345 7 &0160"# 76660663 "30 # 3 4540#000 04 8>GI; J U ijp 3;H 7) *RSn D0 ! 0 0" !#$8;"ML#$QG HP !fTHZ"Hh#$la[dK\X<]^e@+c_,`]^23=4_ABC`EFk .mo+ >q . !H "I2#$4UUJVgNKYjipOW/b? 9: 15%&'(6- KR @6r F -C- FCCC-CC@7;:A<0 2 E !C *B "- B' -D, ( / & ?>3456=198)+ .-- % $-# Bc*a3Q %?J))))) >ENU[Zwf_sQdt 2c=eu}Qv "HCHHJ#JHGGHHG T0V`VxVV V ddffdddddddddddddddddddddddddddddeePeaaaaaaaaaaaaaaaaaaaaaaaaaaedtrace dso,symbol dso,symbol local_weight,mem,sym,dso,symbol_daddr,dso_daddr,snoop,tlb,locked,blocked,local_ins_lat,local_p_stage_cyc comm,dso_from,symbol_from,symbol_to,cycles ^sys_|^do_page_fault init_cpunode_map Z h 0ZȐ2(ȏ(h2H HЕ HdҺҺ read_addr2line_record addr2line_configure addr2line //anon MM4<D$ T4<$ lT 3E s:8 (xh@((bidd;05< gb V f 1 T T T" <" "d! T T T !T #!! !!l#D##! $!$!,# 1H211 22p1p26666666666666666555555555555555555555555556555555755555555555555555555555555555555775555557707070775555555555555555P7P7P7655557j76j755555555555555555557 E C E E P P P P P P P P 0 0 0 P P ` P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P X P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P X P P X X X X X X X X X X X X X P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P X P X P X P X P X P X P X P X P X P X X P X P X X P X P X P X P X X X X X X X X X X X X X X X X X X X X X X P P P P X X P X X X P P P PP P X X X X P P P P P 0 P 0 0 0 P 0 0 0 0 0 P P 0 P P P P P P 0 0 0 0 0 0 P P P P P 0 0 0 P P P P P P P P P P P P X X X X X X X 0 0 P P P P P P P P 0 0 0 0 0 0 0 0 P P P P P P P P P P P P P P P P P P P P P P P P P P 0 0 0 P 0 0 0 0 0 0 0 0 0 0 0 P P 0 0 0 0 0 P P P P 0 0 0 0 0 P P P 0 0 0 P P P P P P 0 0 0 P P P P P P P P P P P P P 0 0 P P P P P P P P P P P 0 P 0 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P 0 0 0 8 8 8 8 8 0 8 8 P P P P P P P P P P P P P P @ ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` P ` p p p p p p p p ` ` P ````` v@-l%% : q 5 V i {W>k/xM~H [ $ $ anP \ S | \\>%?\4DtDn\ ) q$""""$C"$""}!"$"#" #"K!# $t$[$7$ $$ $$$u$#$! $###h#$"d(%%%g%d($)))c)N))E)/b/v/U/D/D/\.\.333w281q7//7P6i:\:99A:9v:7/8/K8)886 1 1n4Bn4=B 1 1Bn4`4B|B@@@@)@@C< 1 1 1 1 1 1 1 10<:55`MMMMqM`MLDMMMqMUMDML^A4ChAhAhAAhAhA CABhAABAhADDDDDDDDEDDDDDDDLMM LML"5L\M@MKL$ML=6QNT4NNNNNNNNNQNNNNNNNNNNNNNNNjPNNNNNNNNND intel_pt_calc_expected_tsc intel_pt_synth_event intel_pt_setup_time_ranges intel_pt_process_auxtrace_info intel_bts_synth_events 5111111155a55a55p5 A A A 8O8O8OO`QOxPPQOVUUUVUUUUUUUUUUUqVUUU^VUUUUUUUUUUUVUUUUVUUUUUUUUUUUYl[ZZ[Zc[Z%ZZ s390_cpumsf_make_event s390_cpumsf_run_decoder Xt_LB8.$tj`V~ ! ) \ ! " " ! # $ " $ ( % ) # % * $ & & # , % $ - . ( / 2 W 4 0 * 4 5 2 - 6 0 6 5 , / . 0 9 : < > ? : @ A ? > B D C E F 9 A @ C < F G H G H D E J K B L M K N L O Q R S J U X T X Y Z N V M O S T V [ Q R P U I = Y ; Z 8 7 3 1 + [ ^ ^ _ _ ' ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ! # " $ " & ( " ' ' " " " " " ' % * ! + " ) " , " " . ' ' - / % 0 # ' $ " 1 5 " 2 " " 3 " % " " % " " 4 " 2 " " 0 6 < " " 8 " " > = 7 : 9 % " " " " " @ " " C B " " " " " ? E D G A J " " K L H I " " F " " N " O " " " " M " " " Y " " Q " P R U V X " S T " W " " Z ; [ " " " ; " \ " " " ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ^ ] ] ] ] ] ] ] ] _ ] _ _ ] ] _ ] ] _ _ _ _ _ _ ] ^ _ _ ] _ _ _ _ _ _ _ _ _ _ _ _ _ _ ] _ _ _ _ _ _ _ _ _ ] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ] ] ) ! $ " * # / < = @ E B : , ? D G H J U R M Q T \ ] ^ _ ` b c f h g i j q r w x z { } L . !"#$%&'()* @@8@ &iJPZI'dH !!!!!!!!!!!!!!!!!!!!! !! !!! !!!!!!!!!!! !!! !" 567; !"#$% !"*+,-./01234 &') <=>?( 89: !"; !" !" 5 !" 6 !" 7 !" @ !" A !" B !" !" !" ' ( % & . C R a 9 p ~ cond_broadcast cond_signal cond_wait cond_destroy __cond_init mutex_trylock mutex_unlock mutex_lock mutex_destroy __mutex_init populate_sdt_note dso__load_sym_internal symsrc__init filename__read_debuglink sysfs__read_build_id elf_read_build_id read_build_id dso__synthesize_plt_symbols d;ddddVddddddddddd ddddddddddddddddddddddddddddddddddddqdddddddddddddddddddddddddddddddpX@E E EEDDEEEEEEEEEEEEEEEEEEEE`D h8Њ ؋set_table_handlers python_process_general_event python_process_brstacksym python_process_brstack set_sample_datasrc_in_dict get_sample_value_as_tuple set_sample_read_in_dict get_perf_sample_dict get_field_numeric_entry python_process_callchain define_field define_value python_process_tracepoint process_stat stat__interval python_process_stat_interval handler_call_die tuple_new )NiE`W|,,,,,4,,,,,,,,,,,,,,,,,|||,|,,||,,,,,,,|,,,,,| jit_add_pid perf_env__add_bpf_info perf_event__synthesize_one_bpf_prog perf_event__synthesize_bpf_events get_bpf_prog_info_linear intel_pt_track_switches intel_pt_find_snapshot intel_bts_find_snapshot default_core bp_l1_btb_correct branch L1 BTB Correction event=0x8a 00 bp_l2_btb_correct branch L2 BTB Correction event=0x8b 00 l3_cache_rd cache L3 cache access, read event=0x40 00 Attributable Level 3 cache access, read segment_reg_loads.any other Number of segment register loads event=6,period=200000,umask=0x80 00 dispatch_blocked.any other Memory cluster signals to block micro-op dispatch for any reason event=9,period=200000,umask=0x20 00 eist_trans other Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions event=0x3a,period=200000 00 hisi_sccl,ddrc uncore_hisi_ddrc.flux_wcmd uncore DDRC write commands event=2 00 DDRC write commands uncore_cbox unc_cbo_xsnp_response.miss_eviction uncore A cross-core snoop resulted from L3 Eviction which misses in some processor core event=0x22,umask=0x81 00 A cross-core snoop resulted from L3 Eviction which misses in some processor core event-hyphen uncore UNC_CBO_HYPHEN event=0xe0 00 UNC_CBO_HYPHEN event-two-hyph uncore UNC_CBO_TWO_HYPH event=0xc0 00 UNC_CBO_TWO_HYPH hisi_sccl,l3c uncore_hisi_l3c.rd_hit_cpipe uncore Total read hits event=7 00 Total read hits uncore_imc_free_running uncore_imc_free_running.cache_miss uncore Total cache misses event=0x12 00 Total cache misses uncore_imc uncore_imc.cache_hits uncore Total cache hits event=0x34 00 Total cache hits uncore_sys_ddr_pmu sys_ddr_pmu.write_cycles uncore ddr write-cycles event event=0x2b v8 00 uncore_sys_ccn_pmu sys_ccn_pmu.read_cycles uncore ccn read-cycles event config=0x2c 0x01 00 uncore_sys_cmn_pmu sys_cmn_pmu.hnf_cache_miss uncore Counts total cache misses in first lookup result (high priority) eventid=1,type=5 (434|436|43c|43a).* 00 l1d.hwpf_miss cache L1D.HWPF_MISS event=0x51,period=1000003,umask=0x20 00 l1d.replacement cache Counts the number of cache lines replaced in L1 data cache event=0x51,period=100003,umask=1 00 Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace l1d_pend_miss.fb_full cache Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability event=0x48,period=1000003,umask=2 00 Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.fb_full_periods cache Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability event=0x48,cmask=1,edge=1,period=1000003,umask=2 00 Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.l2_stall cache This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS event=0x48,period=1000003,umask=4 10 l1d_pend_miss.l2_stalls cache Number of cycles a demand request has waited due to L1D due to lack of L2 resources event=0x48,period=1000003,umask=4 00 Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.pending cache Number of L1D misses that are outstanding event=0x48,period=1000003,umask=1 00 Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=1000003,umask=1 00 Counts duration of L1D miss outstanding in cycles l2_lines_in.all cache L2 cache lines filling L2 event=0x25,period=100003,umask=0x1f 00 Counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_out.useless_hwpf cache Cache lines that have been L2 hardware prefetched but not used by demand accesses event=0x26,period=200003,umask=4 00 Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache l2_request.all cache All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES] event=0x24,period=200003,umask=0xff 00 Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES] l2_request.miss cache Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS] event=0x24,period=200003,umask=0x3f 00 Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS] l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0xe4 00 Counts the total number of L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read access L2 cache event=0x24,period=200003,umask=0xe1 00 Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache event=0x24,period=200003,umask=0x27 00 Counts demand requests that miss L2 cache l2_rqsts.all_hwpf cache L2_RQSTS.ALL_HWPF event=0x24,period=200003,umask=0xf0 00 l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xe2 00 Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0xc4 00 Counts L2 cache hits when fetching instructions, code reads l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x24 00 Counts L2 cache misses when fetching instructions l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=0xc1 00 Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2 cache event=0x24,period=200003,umask=0x21 00 Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once l2_rqsts.hwpf_miss cache L2_RQSTS.HWPF_MISS event=0x24,period=200003,umask=0x30 00 l2_rqsts.miss cache Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS] event=0x24,period=200003,umask=0x3f 00 Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS] l2_rqsts.references cache All accesses to L2 cache [This event is alias to L2_REQUEST.ALL] event=0x24,period=200003,umask=0xff 00 Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL] l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0xc2 00 Counts the RFO (Read-for-Ownership) requests that hit L2 cache l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x22 00 Counts the RFO (Read-for-Ownership) requests that miss L2 cache l2_rqsts.swpf_hit cache SW prefetch requests that hit L2 cache event=0x24,period=200003,umask=0xc8 00 Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full l2_rqsts.swpf_miss cache SW prefetch requests that miss L2 cache event=0x24,period=200003,umask=0x28 00 Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0x23,period=200003,umask=0x40 00 Counts L2 writebacks that access L2 cache longest_lat_cache.miss cache Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis event=0x2e,period=200003,umask=0x41 00 Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis longest_lat_cache.miss cache Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3) event=0x2e,period=100003,umask=0x41 00 Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3 longest_lat_cache.reference cache Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis event=0x2e,period=200003,umask=0x4f 00 Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis longest_lat_cache.reference cache Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3) event=0x2e,period=100003,umask=0x4f 00 Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3 mem_bound_stalls.ifetch cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=0x38 00 Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) mem_bound_stalls.ifetch_dram_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=0x20 00 Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM) mem_bound_stalls.ifetch_l2_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache event=0x34,period=200003,umask=8 00 Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache mem_bound_stalls.ifetch_llc_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M event=0x34,period=200003,umask=0x10 00 Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M mem_bound_stalls.load cache Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=7 00 mem_bound_stalls.load_dram_hit cache Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=4 00 mem_bound_stalls.load_l2_hit cache Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache event=0x34,period=200003,umask=1 00 mem_bound_stalls.load_llc_hit cache Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M event=0x34,period=200003,umask=2 00 Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M mem_inst_retired.all_loads cache Retired load instructions Supports address when precise (Precise event) event=0xd0,period=1000003,umask=0x81 00 Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW Supports address when precise (Precise event) mem_inst_retired.all_stores cache Retired store instructions Supports address when precise (Precise event) event=0xd0,period=1000003,umask=0x82 00 Counts all retired store instructions Supports address when precise (Precise event) mem_inst_retired.any cache All retired memory instructions Supports address when precise (Precise event) event=0xd0,period=1000003,umask=0x83 00 Counts all retired memory instructions - loads and stores Supports address when precise (Precise event) mem_inst_retired.lock_loads cache Retired load instructions with locked access Supports address when precise (Precise event) event=0xd0,period=100007,umask=0x21 00 Counts retired load instructions with locked access Supports address when precise (Precise event) mem_inst_retired.split_loads cache Retired load instructions that split across a cacheline boundary Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x41 00 Counts retired load instructions that split across a cacheline boundary Supports address when precise (Precise event) mem_inst_retired.split_stores cache Retired store instructions that split across a cacheline boundary Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x42 00 Counts retired store instructions that split across a cacheline boundary Supports address when precise (Precise event) mem_inst_retired.stlb_miss_loads cache Retired load instructions that miss the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x11 00 Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB) Supports address when precise (Precise event) mem_inst_retired.stlb_miss_stores cache Retired store instructions that miss the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x12 00 Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB) Supports address when precise (Precise event) mem_load_completed.l1_miss_any cache Completed demand load uops that miss the L1 d-cache event=0x43,period=1000003,umask=0xfd 00 Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss) mem_load_l3_hit_retired.xsnp_fwd cache Retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) event=0xd2,period=20011,umask=4 00 Counts retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hit cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) event=0xd2,period=20011,umask=2 00 Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hitm cache Retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) event=0xd2,period=20011,umask=4 00 Counts retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_miss cache Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) event=0xd2,period=20011,umask=1 00 Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_none cache Retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event) event=0xd2,period=100003,umask=8 00 Counts retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_no_fwd cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) event=0xd2,period=20011,umask=2 00 Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) mem_load_l3_miss_retired.local_dram cache Retired load instructions which data sources missed L3 but serviced from local dram Supports address when precise (Precise event) event=0xd3,period=100007,umask=1 00 Retired load instructions which data sources missed L3 but serviced from local DRAM Supports address when precise (Precise event) mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or lock Supports address when precise (Precise event) event=0xd4,period=100007,umask=4 00 Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock) Supports address when precise (Precise event) mem_load_retired.fb_hit cache Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1 Supports address when precise (Precise event) event=0xd1,period=100007,umask=0x40 00 Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) mem_load_retired.l1_hit cache Retired load instructions with L1 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=1000003,umask=1 00 Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source Supports address when precise (Precise event) mem_load_retired.l1_miss cache Retired load instructions missed L1 cache as data sources Supports address when precise (Precise event) event=0xd1,period=200003,umask=8 00 Counts retired load instructions with at least one uop that missed in the L1 cache Supports address when precise (Precise event) mem_load_retired.l2_hit cache Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=200003,umask=2 00 Counts retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) mem_load_retired.l2_miss cache Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) event=0xd1,period=100021,umask=0x10 00 Counts retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) mem_load_retired.l3_hit cache Retired load instructions with L3 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=100021,umask=4 00 Counts retired load instructions with at least one uop that hit in the L3 cache Supports address when precise (Precise event) mem_load_retired.l3_miss cache Retired load instructions missed L3 cache as data sources Supports address when precise (Precise event) event=0xd1,period=50021,umask=0x20 00 Counts retired load instructions with at least one uop that missed in the L3 cache Supports address when precise (Precise event) mem_load_uops_retired.dram_hit cache Counts the number of load uops retired that hit in DRAM Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x80 00 mem_load_uops_retired.l2_hit cache Counts the number of load uops retired that hit in the L2 cache Supports address when precise (Precise event) event=0xd1,period=200003,umask=2 00 mem_load_uops_retired.l3_hit cache Counts the number of load uops retired that hit in the L3 cache Supports address when precise (Precise event) event=0xd1,period=200003,umask=4 00 mem_scheduler_block.all cache Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full event=4,period=20003,umask=7 00 mem_scheduler_block.ld_buf cache Counts the number of cycles that uops are blocked due to a load buffer full condition event=4,period=20003,umask=2 00 mem_scheduler_block.rsv cache Counts the number of cycles that uops are blocked due to an RSV full condition event=4,period=20003,umask=4 00 mem_scheduler_block.st_buf cache Counts the number of cycles that uops are blocked due to a store buffer full condition event=4,period=20003,umask=1 00 mem_store_retired.l2_hit cache MEM_STORE_RETIRED.L2_HIT event=0x44,period=200003,umask=1 00 mem_uops_retired.all_loads cache Counts the number of load uops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x81 00 Counts the total number of load uops retired Supports address when precise (Precise event) mem_uops_retired.all_stores cache Counts the number of store uops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x82 00 Counts the total number of store uops retired Supports address when precise (Precise event) mem_uops_retired.load_latency_gt_128 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=5,ldlat=0x80 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_16 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=5,ldlat=0x10 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_256 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=5,ldlat=0x100 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_32 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=5,ldlat=0x20 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_4 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=5,ldlat=0x4 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_512 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=5,ldlat=0x200 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_64 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=5,ldlat=0x40 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_8 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=5,ldlat=0x8 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.lock_loads cache Counts the number of load uops retired that performed one or more locks Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x21 00 mem_uops_retired.split_loads cache Counts the number of retired split load uops Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x41 00 mem_uops_retired.store_latency cache Counts the number of stores uops retired. Counts with or without PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=6 00 Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uop_retired.any cache Retired memory uops for any access event=0xe5,period=1000003,umask=3 00 Number of retired micro-operations (uops) for load or store memory accesses ocr.demand_data_rd.l3_hit cache Counts demand data reads that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001 00 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x8003C0001 00 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002 00 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002 00 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C0002 00 offcore_requests.all_requests cache OFFCORE_REQUESTS.ALL_REQUESTS event=0x21,period=100003,umask=0x80 00 offcore_requests.data_rd cache Demand and prefetch data reads event=0x21,period=100003,umask=8 00 Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests.demand_code_rd cache Cacheable and noncacheable code read requests event=0x21,period=100003,umask=2 00 Counts both cacheable and non-cacheable code read requests offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0x21,period=100003,umask=1 00 Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0x21,period=100003,umask=4 00 Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_requests_outstanding.all_data_rd cache This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD Spec update: ADL038 event=0x20,period=1000003,umask=8 10 offcore_requests_outstanding.cycles_with_data_rd cache OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Spec update: ADL038 event=0x20,cmask=1,period=1000003,umask=8 00 offcore_requests_outstanding.cycles_with_demand_code_rd cache Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore event=0x20,cmask=1,period=1000003,umask=2 00 Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles where at least 1 outstanding demand data read request is pending event=0x20,cmask=1,period=2000003,umask=1 00 offcore_requests_outstanding.cycles_with_demand_rfo cache For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1 event=0x20,cmask=1,period=1000003,umask=4 00 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO offcore_requests_outstanding.data_rd cache OFFCORE_REQUESTS_OUTSTANDING.DATA_RD Spec update: ADL038 event=0x20,period=1000003,umask=8 00 offcore_requests_outstanding.demand_code_rd cache Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle event=0x20,period=1000003,umask=2 00 Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_data_rd cache For every cycle, increments by the number of outstanding demand data read requests pending event=0x20,period=1000003,umask=1 00 For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor sq_misc.bus_lock cache Counts bus locks, accounts for cache line split locks and UC locks event=0x2c,period=100003,umask=0x10 00 Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory sw_prefetch_access.any cache Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed event=0x40,period=100003,umask=0xf 00 sw_prefetch_access.nta cache Number of PREFETCHNTA instructions executed event=0x40,period=100003,umask=1 00 Counts the number of PREFETCHNTA instructions executed sw_prefetch_access.prefetchw cache Number of PREFETCHW instructions executed event=0x40,period=100003,umask=8 00 Counts the number of PREFETCHW instructions executed sw_prefetch_access.t0 cache Number of PREFETCHT0 instructions executed event=0x40,period=100003,umask=2 00 Counts the number of PREFETCHT0 instructions executed sw_prefetch_access.t1_t2 cache Number of PREFETCHT1 or PREFETCHT2 instructions executed event=0x40,period=100003,umask=4 00 Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed topdown_fe_bound.icache cache Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses event=0x71,period=1000003,umask=0x20 00 arith.fpdiv_active floating point ARITH.FPDIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=1 00 assists.fp floating point Counts all microcode FP assists event=0xc1,period=100003,umask=2 00 Counts all microcode Floating Point assists assists.sse_avx_mix floating point ASSISTS.SSE_AVX_MIX event=0xc1,period=1000003,umask=0x10 00 fp_arith_dispatched.port_0 floating point FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0] event=0xb3,period=2000003,umask=1 00 fp_arith_dispatched.port_1 floating point FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1] event=0xb3,period=2000003,umask=2 00 fp_arith_dispatched.port_5 floating point FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2] event=0xb3,period=2000003,umask=4 00 fp_arith_dispatched.v0 floating point FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0] event=0xb3,period=2000003,umask=1 00 fp_arith_dispatched.v1 floating point FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1] event=0xb3,period=2000003,umask=2 00 fp_arith_dispatched.v2 floating point FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5] event=0xb3,period=2000003,umask=4 00 fp_arith_inst_retired.128b_packed_double floating point Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=4 00 Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.128b_packed_single floating point Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=8 00 Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_double floating point Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x10 00 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_single floating point Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x20 00 Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.4_flops floating point Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x18 00 Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar floating point Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=1000003,umask=3 00 Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_double floating point Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=1 00 Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_single floating point Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=2 00 Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.vector floating point Number of any Vector retired FP arithmetic instructions event=0xc7,period=1000003,umask=0xfc 00 Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events machine_clears.fp_assist floating point Counts the number of floating point operations retired that required microcode assist event=0xc3,period=20003,umask=4 00 Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops uops_retired.fpdiv floating point Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt) (Precise event) event=0xc2,period=2000003,umask=8 00 baclears.any frontend Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches event=0xe6,period=100003,umask=1 00 Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches baclears.any frontend Clears due to Unknown Branches event=0x60,period=100003,umask=1 00 Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore decode.lcp frontend Stalls caused by changing prefix length of the instruction event=0x87,period=500009,umask=1 00 Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk decode.ms_busy frontend Cycles the Microcode Sequencer is busy event=0x87,period=500009,umask=2 00 dsb2mite_switches.penalty_cycles frontend DSB-to-MITE switch true penalty cycles event=0x61,period=100003,umask=2 00 Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE frontend_retired.any_dsb_miss frontend Retired Instructions who experienced DSB miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x1 00 Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event) frontend_retired.dsb_miss frontend Retired Instructions who experienced a critical DSB miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x11 00 Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss (Precise event) frontend_retired.itlb_miss frontend Retired Instructions who experienced iTLB true miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x14 00 Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event) frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x12 00 Counts retired Instructions who experienced Instruction L1 Cache true miss (Precise event) frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x13 00 Counts retired Instructions who experienced Instruction L2 Cache true miss (Precise event) frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle (Precise event) event=0xc6,period=100007,umask=1,frontend=0x600106 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x608006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x601006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_2 frontend Retired instructions after front-end starvation of at least 2 cycles (Precise event) event=0xc6,period=100007,umask=1,frontend=0x600206 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x610006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_2_bubbles_ge_1 frontend Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x100206 00 Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event) frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x602006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x600406 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x620006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x604006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x600806 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.ms_flows frontend FRONTEND_RETIRED.MS_FLOWS (Precise event) event=0xc6,period=100007,umask=1,frontend=0x8 00 frontend_retired.stlb_miss frontend Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x15 00 Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event) frontend_retired.unknown_branch frontend FRONTEND_RETIRED.UNKNOWN_BRANCH (Precise event) event=0xc6,period=100007,umask=1,frontend=0x17 00 icache.accesses frontend Counts the number of requests to the instruction cache for one or more bytes of a cache line event=0x80,period=200003,umask=3 00 Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line icache.misses frontend Counts the number of instruction cache misses event=0x80,period=200003,umask=2 00 Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line icache_data.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache miss event=0x80,period=500009,umask=4 00 Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity icache_data.stall_periods frontend ICACHE_DATA.STALL_PERIODS event=0x80,cmask=1,edge=1,period=500009,umask=4 00 icache_tag.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss event=0x83,period=200003,umask=4 00 Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss idq.dsb_cycles_any frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=8 00 Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path idq.dsb_cycles_ok frontend Cycles DSB is delivering optimal number of Uops event=0x79,cmask=6,period=2000003,umask=8 00 Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=8 00 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path idq.mite_cycles_any frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=4 00 Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_cycles_ok frontend Cycles MITE is delivering optimal number of Uops event=0x79,cmask=6,period=2000003,umask=4 00 Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=4 00 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles_any frontend Cycles when uops are being delivered to IDQ while MS is busy event=0x79,cmask=1,period=2000003,umask=0x20 00 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_switches frontend Number of switches from DSB or MITE to the MS event=0x79,cmask=1,edge=1,period=100003,umask=0x20 00 Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer idq.ms_uops frontend Uops delivered to IDQ while MS is busy event=0x79,period=1000003,umask=0x20 00 Counts the total number of uops delivered by the Microcode Sequencer (MS) idq_bubbles.core frontend Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE] event=0x9c,period=1000003,umask=1 00 Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE] idq_bubbles.cycles_0_uops_deliv.core frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] event=0x9c,cmask=6,period=1000003,umask=1 00 Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] idq_bubbles.cycles_fe_was_ok frontend Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK] event=0x9c,cmask=1,inv=1,period=1000003,umask=1 00 Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK] idq_uops_not_delivered.core frontend Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE] event=0x9c,period=1000003,umask=1 00 Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CORE] idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] event=0x9c,cmask=6,period=1000003,umask=1 00 Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] idq_uops_not_delivered.cycles_fe_was_ok frontend Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK] event=0x9c,cmask=1,inv=1,period=1000003,umask=1 00 Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK] cycle_activity.stalls_l3_miss memory Execution stalls while L3 cache miss demand load is outstanding event=0xa3,cmask=6,period=1000003,umask=6 00 ld_head.any_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires event=5,period=1000003,umask=0xff 00 ld_head.l1_bound_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring event=5,period=1000003,umask=0xf4 00 ld_head.l1_miss_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss event=5,period=1000003,umask=0x81 00 ld_head.other_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases event=5,period=1000003,umask=0xc0 00 Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc ld_head.pgwalk_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk event=5,period=1000003,umask=0xa0 00 ld_head.st_addr_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match event=5,period=1000003,umask=0x84 00 machine_clears.memory_ordering memory Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation event=0xc3,period=20003,umask=2 00 machine_clears.memory_ordering memory Number of machine clears due to memory ordering conflicts event=0xc3,period=100003,umask=2 00 Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture memory_activity.cycles_l1d_miss memory Cycles while L1 cache miss demand load is outstanding event=0x47,cmask=2,period=1000003,umask=2 00 memory_activity.stalls_l1d_miss memory Execution stalls while L1 cache miss demand load is outstanding event=0x47,cmask=3,period=1000003,umask=3 00 memory_activity.stalls_l2_miss memory Execution stalls while L2 cache miss demand cacheable load request is outstanding event=0x47,cmask=5,period=1000003,umask=5 00 Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock) memory_activity.stalls_l3_miss memory Execution stalls while L3 cache miss demand cacheable load request is outstanding event=0x47,cmask=9,period=1000003,umask=9 00 Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock) mem_trans_retired.load_latency_gt_1024 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles Supports address when precise (Must be precise) event=0xcd,period=53,umask=1,ldlat=0x400 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_128 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles Supports address when precise (Must be precise) event=0xcd,period=1009,umask=1,ldlat=0x80 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_16 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles Supports address when precise (Must be precise) event=0xcd,period=20011,umask=1,ldlat=0x10 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_256 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles Supports address when precise (Must be precise) event=0xcd,period=503,umask=1,ldlat=0x100 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_32 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles Supports address when precise (Must be precise) event=0xcd,period=100007,umask=1,ldlat=0x20 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_4 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles Supports address when precise (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x4 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_512 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles Supports address when precise (Must be precise) event=0xcd,period=101,umask=1,ldlat=0x200 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_64 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles Supports address when precise (Must be precise) event=0xcd,period=2003,umask=1,ldlat=0x40 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_8 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles Supports address when precise (Must be precise) event=0xcd,period=50021,umask=1,ldlat=0x8 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.store_sample memory Retired memory store access operations. A PDist event for PEBS Store Latency Facility Supports address when precise (Must be precise) event=0xcd,period=1000003,umask=2 00 Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 Supports address when precise (Must be precise) ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400001 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0x3FBFC00001 00 ocr.demand_data_rd.l3_miss_local memory Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400002 00 ocr.demand_rfo.l3_miss memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0x3FBFC00002 00 ocr.demand_rfo.l3_miss_local memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400002 00 offcore_requests.l3_miss_demand_data_rd memory Counts demand data read requests that miss the L3 cache event=0x21,period=100003,umask=0x10 00 offcore_requests_outstanding.l3_miss_demand_data_rd memory For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache event=0x20,period=2000003,umask=0x10 00 For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache assists.hardware other ASSISTS.HARDWARE event=0xc1,period=100003,umask=4 00 assists.page_fault other ASSISTS.PAGE_FAULT event=0xc1,period=1000003,umask=8 00 core_power.license_1 other CORE_POWER.LICENSE_1 event=0x28,period=200003,umask=2 00 core_power.license_2 other CORE_POWER.LICENSE_2 event=0x28,period=200003,umask=4 00 core_power.license_3 other CORE_POWER.LICENSE_3 event=0x28,period=200003,umask=8 00 lbr_inserts.any other This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS] (Precise event) event=0xe4,period=1000003,umask=1 10 ocr.corewb_m.any_response other Counts modified writebacks from L1 cache and L2 cache that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10008 00 ocr.demand_data_rd.any_response other Counts demand data reads that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10001 00 ocr.demand_data_rd.any_response other Counts demand data reads that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10001 00 ocr.demand_data_rd.dram other Counts demand data reads that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x184000001 00 ocr.demand_rfo.any_response other Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10002 00 ocr.demand_rfo.any_response other Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10002 00 ocr.streaming_wr.any_response other Counts streaming stores that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10800 00 ocr.streaming_wr.any_response other Counts streaming stores that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10800 00 rs.empty other Cycles when Reservation Station (RS) is empty for the thread event=0xa5,period=1000003,umask=7 00 Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses) rs.empty_count other Counts end of periods where the Reservation Station (RS) was empty event=0xa5,cmask=1,edge=1,inv=1,period=100003,umask=7 00 Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) rs.empty_resource other Cycles when Reservation Station (RS) is empty due to a resource in the back-end event=0xa5,period=1000003,umask=1 00 rs_empty.count other This event is deprecated. Refer to new event RS.EMPTY_COUNT event=0xa5,cmask=1,edge=1,inv=1,period=100003,umask=7 10 rs_empty.cycles other This event is deprecated. Refer to new event RS.EMPTY event=0xa5,period=1000003,umask=7 10 serialization.c01_ms_scb other Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state) event=0x75,period=200003,umask=4 00 xq.full_cycles other Cycles the uncore cannot take further requests event=0x2d,cmask=1,period=1000003,umask=1 00 number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache) arith.divider_active pipeline This event is deprecated. Refer to new event ARITH.DIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=9 10 arith.div_active pipeline Cycles when divide unit is busy executing divide or square root operations event=0xb0,cmask=1,period=1000003,umask=9 00 Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations arith.fp_divider_active pipeline This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=1 10 arith.idiv_active pipeline This event counts the cycles the integer divider is busy event=0xb0,cmask=1,period=1000003,umask=8 00 arith.int_divider_active pipeline This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=8 10 assists.any pipeline Number of occurrences where a microcode assist is invoked by hardware event=0xc1,period=100003,umask=0x1b 00 Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists br_inst_retired.all_branches pipeline Counts the total number of branch instructions retired for all branch types (Precise event) event=0xc4,period=200003 00 Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for (Precise event) br_inst_retired.all_branches pipeline All branch instructions retired (Precise event) event=0xc4,period=400009 00 Counts all branch instructions retired (Precise event) br_inst_retired.call pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL (Precise event) event=0xc4,period=200003,umask=0xf9 10 br_inst_retired.cond pipeline Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches (Precise event) event=0xc4,period=200003,umask=0x7e 00 br_inst_retired.cond pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x11 00 Counts conditional branch instructions retired (Precise event) br_inst_retired.cond_ntaken pipeline Not taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x10 00 Counts not taken branch instructions retired (Precise event) br_inst_retired.cond_taken pipeline Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfe 00 br_inst_retired.cond_taken pipeline Taken conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=1 00 Counts taken conditional branch instructions retired (Precise event) br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return (Precise event) event=0xc4,period=200003,umask=0xbf 00 br_inst_retired.far_branch pipeline Far branch instructions retired (Precise event) event=0xc4,period=100007,umask=0x40 00 Counts far branch instructions retired (Precise event) br_inst_retired.indirect pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xeb 00 br_inst_retired.indirect pipeline Indirect near branch instructions retired (excluding returns) (Precise event) event=0xc4,period=100003,umask=0x80 00 Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch (Precise event) br_inst_retired.indirect_call pipeline Counts the number of near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfb 00 br_inst_retired.ind_call pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL (Precise event) event=0xc4,period=200003,umask=0xfb 10 br_inst_retired.jcc pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.COND (Precise event) event=0xc4,period=200003,umask=0x7e 10 br_inst_retired.near_call pipeline Counts the number of near CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf9 00 br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100007,umask=2 00 Counts both direct and indirect near call instructions retired (Precise event) br_inst_retired.near_return pipeline Counts the number of near RET branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf7 00 br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100007,umask=8 00 Counts return instructions retired (Precise event) br_inst_retired.near_taken pipeline Counts the number of near taken branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xc0 00 br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20 00 Counts taken branch instructions retired (Precise event) br_inst_retired.non_return_ind pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT (Precise event) event=0xc4,period=200003,umask=0xeb 10 br_inst_retired.rel_call pipeline Counts the number of near relative CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfd 00 br_inst_retired.return pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN (Precise event) event=0xc4,period=200003,umask=0xf7 10 br_inst_retired.taken_jcc pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN (Precise event) event=0xc4,period=200003,umask=0xfe 10 br_misp_retired.all_branches pipeline Counts the total number of mispredicted branch instructions retired for all branch types (Precise event) event=0xc5,period=200003 00 Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path (Precise event) br_misp_retired.all_branches pipeline All mispredicted branch instructions retired (Precise event) event=0xc5,period=400009 00 Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.cond pipeline Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc5,period=200003,umask=0x7e 00 br_misp_retired.cond pipeline Mispredicted conditional branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x11 00 Counts mispredicted conditional branch instructions retired (Precise event) br_misp_retired.cond_ntaken pipeline Mispredicted non-taken conditional branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x10 00 Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken (Precise event) br_misp_retired.cond_taken pipeline Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfe 00 br_misp_retired.cond_taken pipeline number of branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=1 00 Counts taken conditional mispredicted branch instructions retired (Precise event) br_misp_retired.indirect pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xeb 00 br_misp_retired.indirect pipeline Miss-predicted near indirect branch instructions retired (excluding returns) (Precise event) event=0xc5,period=100003,umask=0x80 00 Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch (Precise event) br_misp_retired.indirect_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfb 00 br_misp_retired.indirect_call pipeline Mispredicted indirect CALL retired (Precise event) event=0xc5,period=400009,umask=2 00 Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect (Precise event) br_misp_retired.ind_call pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL (Precise event) event=0xc5,period=200003,umask=0xfb 10 br_misp_retired.jcc pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.COND (Precise event) event=0xc5,period=200003,umask=0x7e 10 br_misp_retired.near_taken pipeline Counts the number of mispredicted near taken branch instructions retired (Precise event) event=0xc5,period=200003,umask=0x80 00 br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20 00 Counts number of near branch instructions retired that were mispredicted and taken (Precise event) br_misp_retired.non_return_ind pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT (Precise event) event=0xc5,period=200003,umask=0xeb 10 br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) event=0xc5,period=100007,umask=8 00 This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired (Precise event) br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xf7 00 br_misp_retired.taken_jcc pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN (Precise event) event=0xc5,period=200003,umask=0xfe 10 cpu_clk_unhalted.c01 pipeline Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state event=0xec,period=2000003,umask=0x10 00 Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions cpu_clk_unhalted.c02 pipeline Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state event=0xec,period=2000003,umask=0x20 00 Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions cpu_clk_unhalted.c0_wait pipeline Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state event=0xec,period=2000003,umask=0x70 00 Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction cpu_clk_unhalted.core pipeline Counts the number of unhalted core clock cycles. (Fixed event) event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1 cpu_clk_unhalted.core_p pipeline Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter cpu_clk_unhalted.distributed pipeline Cycle counts are evenly distributed between active threads in the Core event=0xec,period=2000003,umask=2 00 This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread cpu_clk_unhalted.one_thread_active pipeline Core crystal clock cycles when this thread is unhalted and the other thread is halted event=0x3c,period=25003,umask=2 00 Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted cpu_clk_unhalted.pause pipeline CPU_CLK_UNHALTED.PAUSE event=0xec,period=2000003,umask=0x40 00 cpu_clk_unhalted.pause_inst pipeline CPU_CLK_UNHALTED.PAUSE_INST event=0xec,cmask=1,edge=1,period=2000003,umask=0x40 00 cpu_clk_unhalted.ref_distributed pipeline Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core event=0x3c,period=2000003,umask=8 00 This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread cpu_clk_unhalted.ref_tsc pipeline Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event) event=0,period=2000003,umask=3 00 Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_tsc_p pipeline Counts the number of unhalted reference clock cycles at TSC frequency event=0x3c,period=2000003,umask=1 00 Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter cpu_clk_unhalted.ref_tsc_p pipeline Reference cycles when the core is not in halt state event=0x3c,period=2000003,umask=1 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.thread pipeline Counts the number of unhalted core clock cycles. (Fixed event) event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1 cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003 00 Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state event=0x3c,period=2000003 00 This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time cycle_activity.cycles_l1d_miss pipeline Cycles while L1 cache miss demand load is outstanding event=0xa3,cmask=8,period=1000003,umask=8 00 cycle_activity.cycles_l2_miss pipeline Cycles while L2 cache miss demand load is outstanding event=0xa3,cmask=1,period=1000003,umask=1 00 cycle_activity.cycles_mem_any pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=16,period=1000003,umask=0x10 00 cycle_activity.stalls_l1d_miss pipeline Execution stalls while L1 cache miss demand load is outstanding event=0xa3,cmask=12,period=1000003,umask=0xc 00 cycle_activity.stalls_l2_miss pipeline Execution stalls while L2 cache miss demand load is outstanding event=0xa3,cmask=5,period=1000003,umask=5 00 cycle_activity.stalls_total pipeline Total execution stalls event=0xa3,cmask=4,period=1000003,umask=4 00 exe_activity.1_ports_util pipeline Cycles total of 1 uop is executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=2 00 Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty exe_activity.2_3_ports_util pipeline Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty event=0xa6,period=2000003,umask=0xc 00 exe_activity.2_ports_util pipeline Cycles total of 2 uops are executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=4 00 Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty exe_activity.3_ports_util pipeline Cycles total of 3 uops are executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=8 00 Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty exe_activity.4_ports_util pipeline Cycles total of 4 uops are executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=0x10 00 Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty exe_activity.bound_on_loads pipeline Execution stalls while memory subsystem has an outstanding load event=0xa6,cmask=5,period=2000003,umask=0x21 00 exe_activity.bound_on_stores pipeline Cycles where the Store Buffer was full and no loads caused an execution stall event=0xa6,cmask=2,period=1000003,umask=0x40 00 Counts cycles where the Store Buffer was full and no loads caused an execution stall exe_activity.exe_bound_0_ports pipeline Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load event=0xa6,period=1000003,umask=0x80 00 Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load inst_decoded.decoders pipeline Instruction decoders utilized in a cycle event=0x75,period=2000003,umask=1 00 Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions inst_retired.any pipeline Counts the total number of instructions retired. (Fixed event) (Precise event) event=0xc0,period=2000003 00 Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0 (Precise event) inst_retired.any pipeline Number of instructions retired. Fixed Counter - architectural event (Precise event) event=0xc0,period=2000003 00 Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event) inst_retired.any_p pipeline Counts the total number of instructions retired (Precise event) event=0xc0,period=2000003 00 Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter (Precise event) inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event (Precise event) event=0xc0,period=2000003 00 Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event) inst_retired.macro_fused pipeline INST_RETIRED.MACRO_FUSED (Precise event) event=0xc0,period=2000003,umask=0x10 00 inst_retired.nop pipeline Retired NOP instructions (Precise event) event=0xc0,period=2000003,umask=2 00 Counts all retired NOP or ENDBR32/64 instructions (Precise event) inst_retired.prec_dist pipeline Precise instruction retired with PEBS precise-distribution (Precise event) event=0,period=2000003,umask=1 00 A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0 (Precise event) inst_retired.rep_iteration pipeline Iterations of Repeat string retired instructions (Precise event) event=0xc0,period=2000003,umask=8 00 Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent (Precise event) int_misc.clears_count pipeline Clears speculative count event=0xad,cmask=1,edge=1,period=500009,umask=1 00 Counts the number of speculative clears due to any type of branch misprediction or machine clears int_misc.clear_resteer_cycles pipeline Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path event=0xad,period=500009,umask=0x80 00 Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread event=0xad,period=500009,umask=1 00 Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event int_misc.unknown_branch_cycles pipeline Bubble cycles of BAClear (Unknown Branch) event=0xad,period=1000003,umask=0x40,frontend=0x7 00 int_misc.uop_dropping pipeline TMA slots where uops got dropped event=0xad,period=1000003,umask=0x10 00 Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons int_vec_retired.128bit pipeline INT_VEC_RETIRED.128BIT event=0xe7,period=1000003,umask=0x13 00 int_vec_retired.256bit pipeline INT_VEC_RETIRED.256BIT event=0xe7,period=1000003,umask=0xac 00 int_vec_retired.add_128 pipeline integer ADD, SUB, SAD 128-bit vector instructions event=0xe7,period=1000003,umask=3 00 Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions int_vec_retired.add_256 pipeline integer ADD, SUB, SAD 256-bit vector instructions event=0xe7,period=1000003,umask=0xc 00 Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions int_vec_retired.mul_256 pipeline INT_VEC_RETIRED.MUL_256 event=0xe7,period=1000003,umask=0x80 00 int_vec_retired.shuffles pipeline INT_VEC_RETIRED.SHUFFLES event=0xe7,period=1000003,umask=0x40 00 int_vec_retired.vnni_128 pipeline INT_VEC_RETIRED.VNNI_128 event=0xe7,period=1000003,umask=0x10 00 int_vec_retired.vnni_256 pipeline INT_VEC_RETIRED.VNNI_256 event=0xe7,period=1000003,umask=0x20 00 ld_blocks.4k_alias pipeline This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS (Precise event) event=3,period=1000003,umask=4 10 ld_blocks.address_alias pipeline Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check (Precise event) event=3,period=1000003,umask=4 00 ld_blocks.address_alias pipeline False dependencies in MOB due to partial compare on address event=3,period=100003,umask=4 00 Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address ld_blocks.data_unknown pipeline Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready (Precise event) event=3,period=1000003,umask=1 00 ld_blocks.no_sr pipeline The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=3,period=100003,umask=0x88 00 Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks.store_forward pipeline Loads blocked due to overlapping with a preceding store that cannot be forwarded event=3,period=100003,umask=0x82 00 Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide load_hit_prefetch.swpf pipeline Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch event=0x4c,period=100003,umask=1 00 Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions lsd.cycles_active pipeline Cycles Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=1,period=2000003,umask=1 00 Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector) lsd.cycles_ok pipeline Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder event=0xa8,cmask=6,period=2000003,umask=1 00 Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector) lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=1 00 Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector) machine_clears.count pipeline Number of machine clears (nukes) of any type event=0xc3,cmask=1,edge=1,period=100003,umask=1 00 Counts the number of machine clears (nukes) of any type machine_clears.disambiguation pipeline Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU event=0xc3,period=20003,umask=8 00 machine_clears.mrn_nuke pipeline Counts the number of machines clears due to memory renaming event=0xc3,period=1000003,umask=0x80 00 machine_clears.page_fault pipeline Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs event=0xc3,period=20003,umask=0x20 00 machine_clears.slow pipeline Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP event=0xc3,period=20003,umask=0x6f 00 machine_clears.smc pipeline Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page event=0xc3,period=20003,umask=1 00 machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=4 00 Counts self-modifying code (SMC) detected, which causes a machine clear misc2_retired.lfence pipeline LFENCE instructions retired event=0xe0,period=400009,umask=0x20 00 number of LFENCE retired instructions misc_retired.lbr_inserts pipeline Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY] (Precise event) event=0xe4,period=1000003,umask=1 00 Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. This event is PDIR on GP0 and NPEBS on all other GPs [This event is alias to LBR_INSERTS.ANY] (Precise event) misc_retired.lbr_inserts pipeline Increments whenever there is an update to the LBR array event=0xcc,period=100003,umask=0x20 00 Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=100003,umask=8 00 Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end resource_stalls.scoreboard pipeline Counts cycles where the pipeline is stalled due to serializing operations event=0xa2,period=100003,umask=2 00 serialization.non_c01_ms_scb pipeline Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires event=0x75,period=200003,umask=2 00 Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE topdown.backend_bound_slots pipeline TMA slots where no uops were being issued due to lack of back-end resources event=0xa4,period=10000003,umask=2 00 Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources topdown.bad_spec_slots pipeline TMA slots wasted due to incorrect speculations event=0xa4,period=10000003,umask=4 00 Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations topdown.br_mispredict_slots pipeline TMA slots wasted due to incorrect speculation by branch mispredictions event=0xa4,period=10000003,umask=8 00 Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction topdown.memory_bound_slots pipeline TOPDOWN.MEMORY_BOUND_SLOTS event=0xa4,period=10000003,umask=0x10 00 topdown.slots pipeline TMA slots available for an unhalted logical processor. Fixed counter - architectural event event=0,period=10000003,umask=4 00 Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3) topdown.slots_p pipeline TMA slots available for an unhalted logical processor. General counter - architectural event event=0xa4,period=10000003,umask=1 00 Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core topdown_bad_speculation.all pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0x73,period=1000003 00 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear topdown_bad_speculation.fastnuke pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears event=0x73,period=1000003,umask=2 00 topdown_bad_speculation.machine_clears pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation event=0x73,period=1000003,umask=3 00 topdown_bad_speculation.mispredict pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts event=0x73,period=1000003,umask=4 00 topdown_bad_speculation.nuke pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke) event=0x73,period=1000003,umask=1 00 topdown_be_bound.all pipeline Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls event=0x74,period=1000003 00 topdown_be_bound.alloc_restrictions pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions event=0x74,period=1000003,umask=1 00 topdown_be_bound.mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops event=0x74,period=1000003,umask=2 00 topdown_be_bound.non_mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops event=0x74,period=1000003,umask=8 00 topdown_be_bound.register pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls) event=0x74,period=1000003,umask=0x20 00 topdown_be_bound.reorder_buffer pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls) event=0x74,period=1000003,umask=0x40 00 topdown_be_bound.serialization pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS) event=0x74,period=1000003,umask=0x10 00 topdown_fe_bound.all pipeline Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls event=0x71,period=1000003 00 topdown_fe_bound.branch_detect pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS event=0x71,period=1000003,umask=2 00 Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches topdown_fe_bound.branch_resteer pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS event=0x71,period=1000003,umask=0x40 00 Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch topdown_fe_bound.cisc pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS) event=0x71,period=1000003,umask=1 00 topdown_fe_bound.decode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls event=0x71,period=1000003,umask=8 00 topdown_fe_bound.frontend_bandwidth pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations event=0x71,period=1000003,umask=0x8d 00 topdown_fe_bound.frontend_latency pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses event=0x71,period=1000003,umask=0x72 00 topdown_fe_bound.itlb pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses event=0x71,period=1000003,umask=0x10 00 Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses topdown_fe_bound.other pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized event=0x71,period=1000003,umask=0x80 00 topdown_fe_bound.predecode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes event=0x71,period=1000003,umask=4 00 topdown_retiring.all pipeline Counts the total number of consumed retirement slots (Precise event) event=0xc2,period=1000003 00 uops_decoded.dec0_uops pipeline UOPS_DECODED.DEC0_UOPS event=0x76,period=1000003,umask=1 00 uops_dispatched.port_0 pipeline Uops executed on port 0 event=0xb2,period=2000003,umask=1 00 Number of uops dispatch to execution port 0 uops_dispatched.port_1 pipeline Uops executed on port 1 event=0xb2,period=2000003,umask=2 00 Number of uops dispatch to execution port 1 uops_dispatched.port_2_3_10 pipeline Uops executed on ports 2, 3 and 10 event=0xb2,period=2000003,umask=4 00 Number of uops dispatch to execution ports 2, 3 and 10 uops_dispatched.port_4_9 pipeline Uops executed on ports 4 and 9 event=0xb2,period=2000003,umask=0x10 00 Number of uops dispatch to execution ports 4 and 9 uops_dispatched.port_5_11 pipeline Uops executed on ports 5 and 11 event=0xb2,period=2000003,umask=0x20 00 Number of uops dispatch to execution ports 5 and 11 uops_dispatched.port_6 pipeline Uops executed on port 6 event=0xb2,period=2000003,umask=0x40 00 Number of uops dispatch to execution port 6 uops_dispatched.port_7_8 pipeline Uops executed on ports 7 and 8 event=0xb2,period=2000003,umask=0x80 00 Number of uops dispatch to execution ports 7 and 8 uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core event=0xb1,cmask=1,period=2000003,umask=2 00 Counts cycles when at least 1 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core event=0xb1,cmask=2,period=2000003,umask=2 00 Counts cycles when at least 2 micro-ops are executed from any thread on physical core uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core event=0xb1,cmask=3,period=2000003,umask=2 00 Counts cycles when at least 3 micro-ops are executed from any thread on physical core uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core event=0xb1,cmask=4,period=2000003,umask=2 00 Counts cycles when at least 4 micro-ops are executed from any thread on physical core uops_executed.cycles_ge_1 pipeline Cycles where at least 1 uop was executed per-thread event=0xb1,cmask=1,period=2000003,umask=1 00 Cycles where at least 1 uop was executed per-thread uops_executed.cycles_ge_2 pipeline Cycles where at least 2 uops were executed per-thread event=0xb1,cmask=2,period=2000003,umask=1 00 Cycles where at least 2 uops were executed per-thread uops_executed.cycles_ge_3 pipeline Cycles where at least 3 uops were executed per-thread event=0xb1,cmask=3,period=2000003,umask=1 00 Cycles where at least 3 uops were executed per-thread uops_executed.cycles_ge_4 pipeline Cycles where at least 4 uops were executed per-thread event=0xb1,cmask=4,period=2000003,umask=1 00 Cycles where at least 4 uops were executed per-thread uops_executed.stalls pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=1 00 Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_executed.stall_cycles pipeline This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS event=0xb1,cmask=1,inv=1,period=2000003,umask=1 10 uops_executed.thread pipeline Counts the number of uops to be executed per-thread each cycle event=0xb1,period=2000003,umask=1 00 uops_executed.x87 pipeline Counts the number of x87 uops dispatched event=0xb1,period=2000003,umask=0x10 00 Counts the number of x87 uops executed uops_issued.any pipeline Counts the number of uops issued by the front end every cycle event=0xe,period=200003 00 Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued uops_issued.any pipeline Uops that RAT issues to RS event=0xae,period=2000003,umask=1 00 Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) uops_issued.cycles pipeline UOPS_ISSUED.CYCLES event=0xae,cmask=1,period=2000003,umask=1 00 uops_retired.all pipeline Counts the total number of uops retired (Precise event) event=0xc2,period=2000003 00 uops_retired.cycles pipeline Cycles with retired uop(s) event=0xc2,cmask=1,period=1000003,umask=2 00 Counts cycles where at least one uop has retired uops_retired.heavy pipeline Retired uops except the last uop of each instruction event=0xc2,period=2000003,umask=1 00 Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count uops_retired.idiv pipeline Counts the number of integer divide uops retired (Precise event) event=0xc2,period=2000003,umask=0x10 00 uops_retired.ms pipeline Counts the number of uops that are from complex flows issued by the micro-sequencer (MS) (Precise event) event=0xc2,period=2000003,umask=1 00 Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows (Precise event) uops_retired.ms pipeline UOPS_RETIRED.MS event=0xc2,period=2000003,umask=4,frontend=0x8 00 uops_retired.slots pipeline Retirement slots used event=0xc2,period=2000003,umask=2 00 Counts the retirement slots used each cycle uops_retired.stalls pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=1000003,umask=2 00 This event counts cycles without actually retired uops uops_retired.stall_cycles pipeline This event is deprecated. Refer to new event UOPS_RETIRED.STALLS event=0xc2,cmask=1,inv=1,period=1000003,umask=2 10 uops_retired.x87 pipeline Counts the number of x87 uops retired, includes those in MS flows (Precise event) event=0xc2,period=2000003,umask=2 00 uncore_arb unc_arb_coh_trk_requests.all uncore interconnect Number of requests allocated in Coherency Tracker event=0x84,umask=1 01 unc_arb_dat_occupancy.all uncore interconnect Each cycle counts number of any coherent request at memory controller that were issued by any core event=0x85,umask=1 01 unc_arb_dat_occupancy.rd uncore interconnect Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core event=0x85,umask=2 01 unc_arb_dat_requests.rd uncore interconnect This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD event=0x81,umask=2 11 unc_arb_ifa_occupancy.all uncore interconnect This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL event=0x85,umask=1 11 unc_arb_req_trk_occupancy.drd uncore interconnect Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD] event=0x80,umask=2 01 unc_arb_req_trk_request.drd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD] event=0x81,umask=2 01 unc_arb_trk_occupancy.all uncore interconnect Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic event=0x80,umask=1 01 unc_arb_trk_occupancy.rd uncore interconnect Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD] event=0x80,umask=2 01 unc_arb_trk_requests.all uncore interconnect Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC event=0x81,umask=1 01 unc_arb_trk_requests.rd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD] event=0x81,umask=2 01 uncore_imc_free_running_0 unc_mc0_rdcas_count_freerun uncore memory Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels) event=0xff,umask=0x20 01 Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels) unc_mc0_wrcas_count_freerun uncore memory Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x30 01 uncore_imc_free_running_1 unc_mc1_rdcas_count_freerun uncore memory Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels) event=0xff,umask=0x20 01 Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels) unc_mc1_wrcas_count_freerun uncore memory Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x30 01 unc_m_act_count_rd uncore memory ACT command for a read request sent to DRAM event=0x24 01 unc_m_act_count_total uncore memory ACT command sent to DRAM event=0x26 01 unc_m_act_count_wr uncore memory ACT command for a write request sent to DRAM event=0x25 01 unc_m_cas_count_rd uncore memory Read CAS command sent to DRAM event=0x22 01 unc_m_cas_count_wr uncore memory Write CAS command sent to DRAM event=0x23 01 unc_m_clockticks uncore memory Number of clocks event=1 01 unc_m_dram_page_empty_rd uncore memory incoming read request page status is Page Empty event=0x1d 01 unc_m_dram_page_empty_wr uncore memory incoming write request page status is Page Empty event=0x20 01 unc_m_dram_page_hit_rd uncore memory incoming read request page status is Page Hit event=0x1c 01 unc_m_dram_page_hit_wr uncore memory incoming write request page status is Page Hit event=0x1f 01 unc_m_dram_page_miss_rd uncore memory incoming read request page status is Page Miss event=0x1e 01 unc_m_dram_page_miss_wr uncore memory incoming write request page status is Page Miss event=0x21 01 unc_m_dram_thermal_hot uncore memory Any Rank at Hot state event=0x19 01 unc_m_dram_thermal_warm uncore memory Any Rank at Warm state event=0x1a 01 unc_m_prefetch_rd uncore memory Incoming read prefetch request from IA event=0xa 01 unc_m_pre_count_idle uncore memory PRE command sent to DRAM due to page table idle timer expiration event=0x28 01 unc_m_pre_count_page_miss uncore memory PRE command sent to DRAM for a read/write request event=0x27 01 unc_m_vc0_requests_rd uncore memory Incoming VC0 read request event=2 01 unc_m_vc0_requests_wr uncore memory Incoming VC0 write request event=3 01 unc_m_vc1_requests_rd uncore memory Incoming VC1 read request event=4 01 unc_m_vc1_requests_wr uncore memory Incoming VC1 write request event=5 01 uncore_clock unc_clock.socket uncore other This 48-bit fixed counter counts the UCLK cycles event=0xff 01 dtlb_load_misses.stlb_hit virtual memory Loads that miss the DTLB and hit the STLB event=0x12,period=100003,umask=0x20 00 Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) dtlb_load_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a demand load event=0x12,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load dtlb_load_misses.walk_completed virtual memory Counts the number of page walks completed due to load DTLB misses to any page size event=8,period=200003,umask=0xe 00 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault dtlb_load_misses.walk_completed virtual memory Load miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x12,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_1g virtual memory Page walks completed due to a demand data load to a 1G page event=0x12,period=100003,umask=8 00 Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data load to a 2M/4M page event=0x12,period=100003,umask=4 00 Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_4k virtual memory Page walks completed due to a demand data load to a 4K page event=0x12,period=100003,umask=2 00 Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_pending virtual memory Number of page walks outstanding for a demand load in the PMH each cycle event=0x12,period=100003,umask=0x10 00 Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle dtlb_store_misses.stlb_hit virtual memory Stores that miss the DTLB and hit the STLB event=0x13,period=100003,umask=0x20 00 Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) dtlb_store_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a store event=0x13,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to any page size event=0x49,period=2000003,umask=0xe 00 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault dtlb_store_misses.walk_completed virtual memory Store misses in all TLB levels causes a page walk that completes. (All page sizes) event=0x13,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_1g virtual memory Page walks completed due to a demand data store to a 1G page event=0x13,period=100003,umask=8 00 Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data store to a 2M/4M page event=0x13,period=100003,umask=4 00 Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_4k virtual memory Page walks completed due to a demand data store to a 4K page event=0x13,period=100003,umask=2 00 Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_pending virtual memory Number of page walks outstanding for a store in the PMH each cycle event=0x13,period=100003,umask=0x10 00 Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle itlb_misses.miss_caused_walk virtual memory Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs event=0x85,period=1000003,umask=1 00 itlb_misses.pde_cache_miss virtual memory Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache event=0x85,period=2000003,umask=0x80 00 itlb_misses.stlb_hit virtual memory Instruction fetch requests that miss the ITLB and hit the STLB event=0x11,period=100003,umask=0x20 00 Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB) itlb_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request event=0x11,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request itlb_misses.walk_completed virtual memory Counts the number of page walks completed due to instruction fetch misses to any page size event=0x85,period=200003,umask=0xe 00 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault itlb_misses.walk_completed virtual memory Code miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x11,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) event=0x11,period=100003,umask=4 00 Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) event=0x11,period=100003,umask=2 00 Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_pending virtual memory Number of page walks outstanding for an outstanding code request in the PMH each cycle event=0x11,period=100003,umask=0x10 00 Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle ld_head.dtlb_miss_at_ret virtual memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss event=5,period=1000003,umask=0x90 00 bp_dyn_ind_pred branch Dynamic Indirect Predictions event=0x8e 00 Indirect Branch Prediction for potential multi-target branch (speculative) bp_de_redirect branch Decoder Overrides Existing Branch Prediction (speculative) event=0x91 00 bp_l1_tlb_fetch_hit branch The number of instruction fetches that hit in the L1 ITLB event=0x94 00 ic_fw32 cache The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses) event=0x80 00 ic_fw32_miss cache The number of 32B fetch windows tried to read the L1 IC and missed in the full tag event=0x81 00 ic_cache_fill_l2 cache The number of 64 byte instruction cache line was fulfilled from the L2 cache event=0x82 00 ic_cache_fill_sys cache The number of 64 byte instruction cache line fulfilled from system memory or another cache event=0x83 00 bp_l1_tlb_miss_l2_hit cache The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84 00 bp_l1_tlb_miss_l2_miss cache The number of instruction fetches that miss in both the L1 and L2 TLBs event=0x85 00 bp_snp_re_sync cache The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event event=0x86 00 ic_fetch_stall.ic_stall_any cache Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1) event=0x87,umask=4 00 ic_fetch_stall.ic_stall_dq_empty cache Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty event=0x87,umask=2 00 ic_fetch_stall.ic_stall_back_pressure cache Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure event=0x87,umask=1 00 ic_cache_inval.l2_invalidating_probe cache IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core event=0x8c,umask=2 00 ic_cache_inval.fill_invalidated cache IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core event=0x8c,umask=1 00 bp_tlb_rel cache The number of ITLB reload requests event=0x99 00 l2_request_g1.rd_blk_l cache All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch) event=0x60,umask=0x80 00 l2_request_g1.rd_blk_x cache All L2 Cache Requests (Breakdown 1 - Common). Data cache stores event=0x60,umask=0x40 00 l2_request_g1.ls_rd_blk_c_s cache All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads event=0x60,umask=0x20 00 l2_request_g1.cacheable_ic_read cache All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads event=0x60,umask=0x10 00 l2_request_g1.change_to_x cache All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state event=0x60,umask=8 00 l2_request_g1.prefetch_l2_cmd cache All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd event=0x60,umask=4 00 l2_request_g1.l2_hw_pf cache All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event event=0x60,umask=2 00 l2_request_g1.group2 cache Miscellaneous events covered in more detail by l2_request_g2 (PMCx061) event=0x60,umask=1 00 l2_request_g1.all_no_prefetch cache event=0x60,umask=0xf9 00 l2_request_g2.group1 cache Miscellaneous events covered in more detail by l2_request_g1 (PMCx060) event=0x61,umask=0x80 00 l2_request_g2.ls_rd_sized cache All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized event=0x61,umask=0x40 00 l2_request_g2.ls_rd_sized_nc cache All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable event=0x61,umask=0x20 00 l2_request_g2.ic_rd_sized cache All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized event=0x61,umask=0x10 00 l2_request_g2.ic_rd_sized_nc cache All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable event=0x61,umask=8 00 l2_request_g2.smc_inval cache All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates event=0x61,umask=4 00 l2_request_g2.bus_locks_originator cache All L2 Cache Requests (Breakdown 2 - Rare). Bus locks event=0x61,umask=2 00 l2_request_g2.bus_locks_responses cache All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response event=0x61,umask=1 00 l2_latency.l2_cycles_waiting_on_fills cache Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used event=0x62,umask=1 00 l2_wcb_req.wcb_write cache LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requests event=0x63,umask=0x40 00 l2_wcb_req.wcb_close cache LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requests event=0x63,umask=0x20 00 l2_wcb_req.zero_byte_store cache LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests event=0x63,umask=4 00 l2_wcb_req.cl_zero cache LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests event=0x63,umask=1 00 l2_cache_req_stat.ls_rd_blk_cs cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2 event=0x64,umask=0x80 00 l2_cache_req_stat.ls_rd_blk_l_hit_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2 event=0x64,umask=0x40 00 l2_cache_req_stat.ls_rd_blk_l_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L2 event=0x64,umask=0x20 00 l2_cache_req_stat.ls_rd_blk_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2 event=0x64,umask=0x10 00 l2_cache_req_stat.ls_rd_blk_c cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types) event=0x64,umask=8 00 l2_cache_req_stat.ic_fill_hit_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2 event=0x64,umask=4 00 l2_cache_req_stat.ic_fill_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2 event=0x64,umask=2 00 l2_cache_req_stat.ic_fill_miss cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 event=0x64,umask=1 00 l2_cache_req_stat.ic_access_in_l2 cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2 event=0x64,umask=7 00 l2_cache_req_stat.ic_dc_miss_in_l2 cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types) event=0x64,umask=9 00 l2_cache_req_stat.ic_dc_hit_in_l2 cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types) event=0x64,umask=0xf6 00 l2_fill_pending.l2_fill_busy cache Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2 event=0x6d,umask=1 00 l2_pf_hit_l2 cache L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead event=0x70,umask=0xff 00 l2_pf_miss_l2_hit_l3 cache L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3 event=0x71,umask=0xff 00 l2_pf_miss_l2_l3 cache L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches event=0x72,umask=0xff 00 amd_l3 l3_request_g1.caching_l3_cache_accesses cache Caching: L3 cache accesses event=1,umask=0x80 00 l3_lookup_state.all_l3_req_typs cache All L3 Request Types event=4,umask=0xff 00 l3_comb_clstr_state.other_l3_miss_typs cache Other L3 Miss Request Types event=6,umask=0xfe 00 l3_comb_clstr_state.request_miss cache L3 cache misses event=6,umask=1 00 xi_sys_fill_latency cache L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask event=0x90 00 xi_ccx_sdp_req1.all_l3_miss_req_typs cache All L3 Miss Request Types. Ignores SliceMask and ThreadMask event=0x9a,umask=0x3f 00 ex_ret_instr core Retired Instructions event=0xc0 00 ex_ret_cops core Retired Uops event=0xc1 00 The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4 ex_ret_brn core Retired Branch Instructions event=0xc2 00 The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts ex_ret_brn_misp core Retired Branch Instructions Mispredicted event=0xc3 00 The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts) ex_ret_brn_tkn core Retired Taken Branch Instructions event=0xc4 00 The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts ex_ret_brn_tkn_misp core Retired Taken Branch Instructions Mispredicted event=0xc5 00 The number of retired taken branch instructions that were mispredicted ex_ret_brn_far core Retired Far Control Transfers event=0xc6 00 The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction ex_ret_brn_resync core Retired Branch Resyncs event=0xc7 00 The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare ex_ret_near_ret core Retired Near Returns event=0xc8 00 The number of near return instructions (RET or RET Iw) retired ex_ret_near_ret_mispred core Retired Near Returns Mispredicted event=0xc9 00 The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction ex_ret_brn_ind_misp core Retired Indirect Branch Instructions Mispredicted event=0xca 00 ex_ret_mmx_fp_instr.sse_instr core SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) event=0xcb,umask=4 00 The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) ex_ret_mmx_fp_instr.mmx_instr core MMX instructions event=0xcb,umask=2 00 The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions ex_ret_mmx_fp_instr.x87_instr core x87 instructions event=0xcb,umask=1 00 The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions ex_ret_cond core Retired Conditional Branch Instructions event=0xd1 00 ex_div_busy core Div Cycles Busy count event=0xd3 00 ex_div_count core Div Op Count event=0xd4 00 ex_tagged_ibs_ops.ibs_count_rollover core Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired event=0x1cf,umask=4 00 ex_tagged_ibs_ops.ibs_tagged_ops_ret core Tagged IBS Ops. Number of Ops tagged by IBS that retired event=0x1cf,umask=2 00 ex_tagged_ibs_ops.ibs_tagged_ops core Tagged IBS Ops. Number of Ops tagged by IBS event=0x1cf,umask=1 00 ex_ret_fus_brnch_inst core The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3 event=0x1d0 00 amd_df remote_outbound_data_controller_0 data fabric event=0x7c7,umask=2 01 Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0 remote_outbound_data_controller_1 data fabric event=0x807,umask=2 01 Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1 remote_outbound_data_controller_2 data fabric event=0x847,umask=2 01 Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2 remote_outbound_data_controller_3 data fabric event=0x887,umask=2 01 Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3 dram_channel_data_controller_0 data fabric event=7,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_1 data fabric event=0x47,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_2 data fabric event=0x87,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_3 data fabric event=0xc7,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_4 data fabric event=0x107,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_5 data fabric event=0x147,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_6 data fabric event=0x187,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_7 data fabric event=0x1c7,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 fpu_pipe_assignment.dual floating point Total number multi-pipe uOps assigned to all pipes event=0,umask=0xf0 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipes fpu_pipe_assignment.dual3 floating point Total number multi-pipe uOps assigned to pipe 3 event=0,umask=0x80 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3 fpu_pipe_assignment.dual2 floating point Total number multi-pipe uOps assigned to pipe 2 event=0,umask=0x40 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2 fpu_pipe_assignment.dual1 floating point Total number multi-pipe uOps assigned to pipe 1 event=0,umask=0x20 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1 fpu_pipe_assignment.dual0 floating point Total number multi-pipe uOps assigned to pipe 0 event=0,umask=0x10 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 0 fpu_pipe_assignment.total floating point Total number uOps assigned to all fpu pipes event=0,umask=0xf 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to all pipes fpu_pipe_assignment.total3 floating point Total number of fp uOps on pipe 3 event=0,umask=8 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3 fpu_pipe_assignment.total2 floating point Total number of fp uOps on pipe 2 event=0,umask=4 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2 fpu_pipe_assignment.total1 floating point Total number of fp uOps on pipe 1 event=0,umask=2 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1 fpu_pipe_assignment.total0 floating point Total number of fp uOps on pipe 0 event=0,umask=1 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0 fp_sched_empty floating point This is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the scheduler event=1 00 fp_retx87_fp_ops.all floating point All Ops event=2,umask=7 00 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8 fp_retx87_fp_ops.div_sqr_r_ops floating point Divide and square root Ops event=2,umask=4 00 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Divide and square root Ops fp_retx87_fp_ops.mul_ops floating point Multiply Ops event=2,umask=2 00 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Multiply Ops fp_retx87_fp_ops.add_sub_ops floating point Add/subtract Ops event=2,umask=1 00 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Add/subtract Ops fp_ret_sse_avx_ops.all floating point All FLOPS event=3,umask=0xff 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 fp_ret_sse_avx_ops.dp_mult_add_flops floating point Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS event=3,umask=0x80 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS fp_ret_sse_avx_ops.dp_div_flops floating point Double precision divide/square root FLOPS event=3,umask=0x40 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision divide/square root FLOPS fp_ret_sse_avx_ops.dp_mult_flops floating point Double precision multiply FLOPS event=3,umask=0x20 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply FLOPS fp_ret_sse_avx_ops.dp_add_sub_flops floating point Double precision add/subtract FLOPS event=3,umask=0x10 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision add/subtract FLOPS fp_ret_sse_avx_ops.sp_mult_add_flops floating point Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS event=3,umask=8 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS fp_ret_sse_avx_ops.sp_div_flops floating point Single-precision divide/square root FLOPS event=3,umask=4 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision divide/square root FLOPS fp_ret_sse_avx_ops.sp_mult_flops floating point Single-precision multiply FLOPS event=3,umask=2 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision multiply FLOPS fp_ret_sse_avx_ops.sp_add_sub_flops floating point Single-precision add/subtract FLOPS event=3,umask=1 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision add/subtract FLOPS fp_num_mov_elim_scal_op.optimized floating point Number of Scalar Ops optimized event=4,umask=8 00 This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Scalar Ops optimized fp_num_mov_elim_scal_op.opt_potential floating point Number of Ops that are candidates for optimization (have Z-bit either set or pass) event=4,umask=4 00 This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Ops that are candidates for optimization (have Z-bit either set or pass) fp_num_mov_elim_scal_op.sse_mov_ops_elim floating point Number of SSE Move Ops eliminated event=4,umask=2 00 This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops eliminated fp_num_mov_elim_scal_op.sse_mov_ops floating point Number of SSE Move Ops event=4,umask=1 00 This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops fp_retired_ser_ops.x87_ctrl_ret floating point x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits event=5,umask=8 00 The number of serializing Ops retired. x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits fp_retired_ser_ops.x87_bot_ret floating point x87 bottom-executing uOps retired event=5,umask=4 00 The number of serializing Ops retired. x87 bottom-executing uOps retired fp_retired_ser_ops.sse_ctrl_ret floating point SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits event=5,umask=2 00 The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits fp_retired_ser_ops.sse_bot_ret floating point SSE bottom-executing uOps retired event=5,umask=1 00 The number of serializing Ops retired. SSE bottom-executing uOps retired ls_locks.bus_lock memory Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type event=0x25,umask=1 00 ls_dispatch.ld_st_dispatch memory Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores event=0x29,umask=4 00 ls_dispatch.store_dispatch memory Counts the number of stores dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=2 00 ls_dispatch.ld_dispatch memory Counts the number of loads dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=1 00 ls_stlf memory Number of STLF hits event=0x35 00 ls_dc_accesses memory The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event event=0x40 00 ls_mab_alloc.dc_prefetcher memory LS MAB allocates by type - DC prefetcher event=0x41,umask=8 00 ls_mab_alloc.stores memory LS MAB allocates by type - stores event=0x41,umask=2 00 ls_mab_alloc.loads memory LS MAB allocates by type - loads event=0x41,umask=1 00 ls_l1_d_tlb_miss.all memory L1 DTLB Miss or Reload off all sizes event=0x45,umask=0xff 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB Miss of a page of 1G size event=0x45,umask=0x80 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB Miss of a page of 2M size event=0x45,umask=0x40 00 ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss memory L1 DTLB Miss of a page of 32K size event=0x45,umask=0x20 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB Miss of a page of 4K size event=0x45,umask=0x10 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit memory L1 DTLB Reload of a page of 1G size event=0x45,umask=8 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit memory L1 DTLB Reload of a page of 2M size event=0x45,umask=4 00 ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit memory L1 DTLB Reload of a page of 32K size event=0x45,umask=2 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit memory L1 DTLB Reload of a page of 4K size event=0x45,umask=1 00 ls_tablewalker.iside memory Total Page Table Walks on I-side event=0x46,umask=0xc 00 ls_tablewalker.ic_type1 memory Total Page Table Walks IC Type 1 event=0x46,umask=8 00 ls_tablewalker.ic_type0 memory Total Page Table Walks IC Type 0 event=0x46,umask=4 00 ls_tablewalker.dside memory Total Page Table Walks on D-side event=0x46,umask=3 00 ls_tablewalker.dc_type1 memory Total Page Table Walks DC Type 1 event=0x46,umask=2 00 ls_tablewalker.dc_type0 memory Total Page Table Walks DC Type 0 event=0x46,umask=1 00 ls_misal_accesses memory Misaligned loads event=0x47 00 ls_pref_instr_disp.prefetch_nta memory Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched event=0x4b,umask=4 00 ls_pref_instr_disp.store_prefetch_w memory Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched event=0x4b,umask=2 00 ls_pref_instr_disp.load_prefetch_w memory Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2 event=0x4b,umask=1 00 ls_inef_sw_pref.mab_mch_cnt memory The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer event=0x52,umask=2 00 ls_inef_sw_pref.data_pipe_sw_pf_dc_hit memory The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit event=0x52,umask=1 00 ls_not_halted_cyc memory Cycles not in Halt event=0x76 00 ic_oc_mode_switch.oc_ic_mode_switch other OC Mode Switch. OC to IC mode switch event=0x28a,umask=2 00 ic_oc_mode_switch.ic_oc_mode_switch other OC Mode Switch. IC to OC mode switch event=0x28a,umask=1 00 de_dis_dispatch_token_stalls0.retire_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable event=0xaf,umask=0x40 00 de_dis_dispatch_token_stalls0.agsq_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable event=0xaf,umask=0x20 00 de_dis_dispatch_token_stalls0.alu_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable event=0xaf,umask=0x10 00 de_dis_dispatch_token_stalls0.alsq3_0_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailable event=0xaf,umask=8 00 de_dis_dispatch_token_stalls0.alsq3_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable event=0xaf,umask=4 00 de_dis_dispatch_token_stalls0.alsq2_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable event=0xaf,umask=2 00 de_dis_dispatch_token_stalls0.alsq1_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable event=0xaf,umask=1 00 all_dc_accesses recommended All L1 Data Cache Accesses event=0x29,umask=7 00 l2_cache_accesses_from_ic_misses recommended L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch) event=0x60,umask=0x10 00 l2_cache_accesses_from_dc_misses recommended L2 Cache Accesses from L1 Data Cache Misses (including prefetch) event=0x60,umask=0xc8 00 l2_cache_misses_from_ic_miss recommended L2 Cache Misses from L1 Instruction Cache Misses event=0x64,umask=1 00 l2_cache_misses_from_dc_misses recommended L2 Cache Misses from L1 Data Cache Misses event=0x64,umask=8 00 l2_cache_hits_from_ic_misses recommended L2 Cache Hits from L1 Instruction Cache Misses event=0x64,umask=6 00 l2_cache_hits_from_dc_misses recommended L2 Cache Hits from L1 Data Cache Misses event=0x64,umask=0x70 00 l2_cache_hits_from_l2_hwpf recommended L2 Cache Hits from L2 HWPF event=0x70,umask=0xff 00 l3_accesses recommended L3 Accesses event=4,umask=0xff 00 l3_misses recommended L3 Misses (includes Chg2X) event=4,umask=1 00 l2_itlb_misses recommended L2 ITLB Misses & Instruction page walks event=0x85,umask=7 00 l1_dtlb_misses recommended L1 DTLB Misses event=0x45,umask=0xff 00 l2_dtlb_misses recommended L2 DTLB Misses & Data page walks event=0x45,umask=0xf0 00 all_tlbs_flushed recommended All TLBs Flushed event=0x78,umask=0xdf 00 uops_dispatched recommended Micro-ops Dispatched event=0xaa,umask=3 00 sse_avx_stalls recommended Mixed SSE/AVX Stalls event=0xe,umask=0xe 00 uops_retired recommended Micro-ops Retired event=0xc1 00 bp_l1_btb_correct branch L1 Branch Prediction Overrides Existing Prediction (speculative) event=0x8a 00 bp_l2_btb_correct branch L2 Branch Prediction Overrides Existing Prediction (speculative) event=0x8b 00 bp_l1_tlb_fetch_hit branch The number of instruction fetches that hit in the L1 ITLB event=0x94,umask=0xff 00 bp_l1_tlb_fetch_hit.if1g branch The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 1GB page event=0x94,umask=4 00 bp_l1_tlb_fetch_hit.if2m branch The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 2MB page event=0x94,umask=2 00 bp_l1_tlb_fetch_hit.if4k branch The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 4KB page event=0x94,umask=1 00 bp_tlb_rel branch The number of ITLB reload requests event=0x99 00 bp_l1_tlb_miss_l2_tlb_miss cache The number of instruction fetches that miss in both the L1 and L2 TLBs event=0x85,umask=0xff 00 bp_l1_tlb_miss_l2_tlb_miss.if1g cache The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 1GB page event=0x85,umask=4 00 bp_l1_tlb_miss_l2_tlb_miss.if2m cache The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 2MB page event=0x85,umask=2 00 bp_l1_tlb_miss_l2_tlb_miss.if4k cache The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 4KB page event=0x85,umask=1 00 ic_oc_mode_switch.oc_ic_mode_switch cache OC Mode Switch. OC to IC mode switch event=0x28a,umask=2 00 ic_oc_mode_switch.ic_oc_mode_switch cache OC Mode Switch. IC to OC mode switch event=0x28a,umask=1 00 ex_ret_cops core Retired Uops event=0xc1 00 The number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8 ex_ret_cond_misp core Retired Conditional Branch Instructions Mispredicted event=0xd2 00 ex_ret_fus_brnch_inst core Retired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8 event=0x1d0 00 fpu_pipe_assignment.total floating point Total number of fp uOps event=0,umask=0xf 00 Total number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS fpu_pipe_assignment.total3 floating point Total number uOps assigned to pipe 3 event=0,umask=8 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3 fpu_pipe_assignment.total2 floating point Total number uOps assigned to pipe 2 event=0,umask=4 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2 fpu_pipe_assignment.total1 floating point Total number uOps assigned to pipe 1 event=0,umask=2 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1 fp_ret_sse_avx_ops.all floating point All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=3,umask=0xff 00 fp_ret_sse_avx_ops.mac_flops floating point Multiply-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=3,umask=8 00 fp_ret_sse_avx_ops.div_flops floating point Divide/square root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=3,umask=4 00 fp_ret_sse_avx_ops.mult_flops floating point Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=3,umask=2 00 fp_ret_sse_avx_ops.add_sub_flops floating point Add/subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=3,umask=1 00 fp_num_mov_elim_scal_op.optimized floating point Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=4,umask=8 00 fp_num_mov_elim_scal_op.opt_potential floating point Number of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=4,umask=4 00 fp_num_mov_elim_scal_op.sse_mov_ops_elim floating point Number of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=4,umask=2 00 fp_num_mov_elim_scal_op.sse_mov_ops floating point Number of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=4,umask=1 00 fp_retired_ser_ops.sse_bot_ret floating point SSE bottom-executing uOps retired. The number of serializing Ops retired event=5,umask=8 00 fp_retired_ser_ops.sse_ctrl_ret floating point The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits event=5,umask=4 00 fp_retired_ser_ops.x87_bot_ret floating point x87 bottom-executing uOps retired. The number of serializing Ops retired event=5,umask=2 00 fp_retired_ser_ops.x87_ctrl_ret floating point x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retired event=5,umask=1 00 fp_disp_faults.ymm_spill_fault floating point Floating Point Dispatch Faults. YMM spill fault event=0xe,umask=8 00 fp_disp_faults.ymm_fill_fault floating point Floating Point Dispatch Faults. YMM fill fault event=0xe,umask=4 00 fp_disp_faults.xmm_fill_fault floating point Floating Point Dispatch Faults. XMM fill fault event=0xe,umask=2 00 fp_disp_faults.x87_fill_fault floating point Floating Point Dispatch Faults. x87 fill fault event=0xe,umask=1 00 ls_bad_status2.stli_other memory Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason event=0x24,umask=2 00 Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores ls_locks.spec_lock_hi_spec memory Retired lock instructions. High speculative cacheable lock speculation succeeded event=0x25,umask=8 00 ls_locks.spec_lock_lo_spec memory Retired lock instructions. Low speculative cacheable lock speculation succeeded event=0x25,umask=4 00 ls_locks.non_spec_lock memory Retired lock instructions. Non-speculative lock succeeded event=0x25,umask=2 00 ls_locks.bus_lock memory Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock event=0x25,umask=1 00 ls_ret_cl_flush memory Number of retired CLFLUSH instructions event=0x26 00 ls_ret_cpuid memory Number of retired CPUID instructions event=0x27 00 ls_dispatch.ld_st_dispatch memory Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address event=0x29,umask=4 00 ls_dispatch.store_dispatch memory Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=2 00 ls_dispatch.ld_dispatch memory Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=1 00 ls_smi_rx memory Number of SMIs received event=0x2b 00 ls_int_taken memory Number of interrupts taken event=0x2c 00 ls_rdtsc memory Number of reads of the TSC (RDTSC instructions). The count is speculative event=0x2d 00 ls_st_commit_cancel2.st_commit_cancel_wcb_full memory A non-cacheable store and the non-cacheable commit buffer is full event=0x37 00 ls_dc_accesses memory Number of accesses to the dcache for load/store references event=0x40 00 The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event ls_mab_alloc.dc_prefetcher memory LS MAB Allocates by Type. DC prefetcher event=0x41,umask=8 00 ls_mab_alloc.stores memory LS MAB Allocates by Type. Stores event=0x41,umask=2 00 ls_mab_alloc.loads memory LS MAB Allocates by Type. Loads event=0x41,umask=1 00 ls_refills_from_sys.ls_mabresp_rmt_dram memory Demand Data Cache Fills by Data Source. DRAM or IO from different die event=0x43,umask=0x40 00 ls_refills_from_sys.ls_mabresp_rmt_cache memory Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die event=0x43,umask=0x10 00 ls_refills_from_sys.ls_mabresp_lcl_dram memory Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die event=0x43,umask=8 00 ls_refills_from_sys.ls_mabresp_lcl_cache memory Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die event=0x43,umask=2 00 ls_refills_from_sys.ls_mabresp_lcl_l2 memory Demand Data Cache Fills by Data Source. Local L2 hit event=0x43,umask=1 00 ls_l1_d_tlb_miss.all memory All L1 DTLB Misses or Reloads event=0x45,umask=0xff 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB event=0x45,umask=0x80 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB event=0x45,umask=0x40 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss memory L1 DTLB Miss. DTLB reload coalesced page miss event=0x45,umask=0x20 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB event=0x45,umask=0x10 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit memory L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB event=0x45,umask=8 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit memory L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB event=0x45,umask=4 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit memory L1 DTLB Miss. DTLB reload hit a coalesced page event=0x45,umask=2 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit memory L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB event=0x45,umask=1 00 ls_pref_instr_disp memory Software Prefetch Instructions Dispatched (Speculative) event=0x4b,umask=0xff 00 ls_pref_instr_disp.prefetch_nta memory Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel event=0x4b,umask=4 00 ls_pref_instr_disp.prefetch_w memory Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW event=0x4b,umask=2 00 ls_pref_instr_disp.prefetch memory Software Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel event=0x4b,umask=1 00 ls_sw_pf_dc_fill.ls_mabresp_rmt_dram memory Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) event=0x59,umask=0x40 00 ls_sw_pf_dc_fill.ls_mabresp_rmt_cache memory Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote) event=0x59,umask=0x10 00 ls_sw_pf_dc_fill.ls_mabresp_lcl_dram memory Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die. From DRAM (home node local) event=0x59,umask=8 00 ls_sw_pf_dc_fill.ls_mabresp_lcl_cache memory Software Prefetch Data Cache Fills by Data Source. From another cache (home node local) event=0x59,umask=2 00 ls_sw_pf_dc_fill.ls_mabresp_lcl_l2 memory Software Prefetch Data Cache Fills by Data Source. Local L2 hit event=0x59,umask=1 00 ls_hw_pf_dc_fill.ls_mabresp_rmt_dram memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) event=0x5a,umask=0x40 00 ls_hw_pf_dc_fill.ls_mabresp_rmt_cache memory Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote) event=0x5a,umask=0x10 00 ls_hw_pf_dc_fill.ls_mabresp_lcl_dram memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local) event=0x5a,umask=8 00 ls_hw_pf_dc_fill.ls_mabresp_lcl_cache memory Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local) event=0x5a,umask=2 00 ls_hw_pf_dc_fill.ls_mabresp_lcl_l2 memory Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit event=0x5a,umask=1 00 ls_tlb_flush memory All TLB Flushes event=0x78 00 de_dis_uop_queue_empty_di0 other Cycles where the Micro-Op Queue is empty event=0xa9 00 de_dis_uops_from_decoder other Ops dispatched from either the decoders, OpCache or both event=0xaa,umask=0xff 00 de_dis_uops_from_decoder.opcache_dispatched other Count of dispatched Ops from OpCache event=0xaa,umask=2 00 de_dis_uops_from_decoder.decoder_dispatched other Count of dispatched Ops from Decoder event=0xaa,umask=1 00 de_dis_dispatch_token_stalls1.fp_misc_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP ops event=0xae,umask=0x80 00 de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP scheduler resource stall. Applies to ops that use the FP scheduler event=0xae,umask=0x40 00 de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Floating point register file resource stall. Applies to all FP ops that have a destination register event=0xae,umask=0x20 00 de_dis_dispatch_token_stalls1.taken_branch_buffer_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Taken branch buffer resource stall event=0xae,umask=0x10 00 de_dis_dispatch_token_stalls1.int_sched_misc_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stall event=0xae,umask=8 00 de_dis_dispatch_token_stalls1.store_queue_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Store queue resource stall. Applies to all ops with store semantics event=0xae,umask=4 00 de_dis_dispatch_token_stalls1.load_queue_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Load queue resource stall. Applies to all ops with load semantics event=0xae,umask=2 00 de_dis_dispatch_token_stalls1.int_phy_reg_file_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Physical Register File resource stall. Applies to all ops that have an integer destination register event=0xae,umask=1 00 de_dis_dispatch_token_stalls0.sc_agu_dispatch_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. SC AGU dispatch stall event=0xaf,umask=0x40 00 de_dis_dispatch_token_stalls0.retire_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable event=0xaf,umask=0x20 00 de_dis_dispatch_token_stalls0.agsq_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable event=0xaf,umask=0x10 00 de_dis_dispatch_token_stalls0.alu_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable event=0xaf,umask=8 00 de_dis_dispatch_token_stalls0.alsq3_0_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ3_0_TokenStall event=0xaf,umask=4 00 bp_dyn_ind_pred branch Dynamic Indirect Predictions event=0x8e 00 The number of times a branch used the indirect predictor to make a prediction bp_de_redirect branch Decode Redirects event=0x91 00 The number of times the instruction decoder overrides the predicted target bp_l1_tlb_fetch_hit.if1g branch The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (1G page size) event=0x94,umask=4 00 bp_l1_tlb_fetch_hit.if2m branch The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (2M page size) event=0x94,umask=2 00 bp_l1_tlb_fetch_hit.if4k branch The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit (4K or 16K page size) event=0x94,umask=1 00 l2_cache_req_stat.ls_rd_blk_l_hit_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable event=0x64,umask=0x40 00 l2_cache_req_stat.ls_rd_blk_l_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line in L2 event=0x64,umask=0x20 00 l2_cache_req_stat.ls_rd_blk_c cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types). Use l2_cache_misses_from_dc_misses instead event=0x64,umask=8 00 l2_cache_req_stat.ic_fill_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line in L2 event=0x64,umask=2 00 l2_cache_req_stat.ic_fill_miss cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2. Use l2_cache_misses_from_ic_miss instead event=0x64,umask=1 00 l2_pf_miss_l2_l3 cache L2 prefetcher misses in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches event=0x72,umask=0xff 00 ic_cache_fill_l2 cache Instruction Cache Refills from L2. The number of 64 byte instruction cache line was fulfilled from the L2 cache event=0x82 00 ic_cache_fill_sys cache Instruction Cache Refills from System. The number of 64 byte instruction cache line fulfilled from system memory or another cache event=0x83 00 bp_l1_tlb_miss_l2_tlb_hit cache L1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84 00 bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for >4K Coalesced page event=0x85,umask=8 00 bp_l1_tlb_miss_l2_tlb_miss.if1g cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 1G page event=0x85,umask=4 00 bp_l1_tlb_miss_l2_tlb_miss.if2m cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 2M page event=0x85,umask=2 00 bp_l1_tlb_miss_l2_tlb_miss.if4k cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk to 4K page event=0x85,umask=1 00 ic_tag_hit_miss.all_instruction_cache_accesses cache All Instruction Cache Accesses. Counts various IC tag related hit and miss events event=0x18e,umask=0x1f 00 ic_tag_hit_miss.instruction_cache_miss cache Instruction Cache Miss. Counts various IC tag related hit and miss events event=0x18e,umask=0x18 00 ic_tag_hit_miss.instruction_cache_hit cache Instruction Cache Hit. Counts various IC tag related hit and miss events event=0x18e,umask=7 00 op_cache_hit_miss.all_op_cache_accesses cache All Op Cache accesses. Counts Op Cache micro-tag hit/miss events event=0x28f,umask=7 00 op_cache_hit_miss.op_cache_miss cache Op Cache Miss. Counts Op Cache micro-tag hit/miss events event=0x28f,umask=4 00 op_cache_hit_miss.op_cache_hit cache Op Cache Hit. Counts Op Cache micro-tag hit/miss events event=0x28f,umask=3 00 l3_lookup_state.all_l3_req_typs cache All L3 Request Types. All L3 cache Requests event=4,umask=0xff 00 xi_ccx_sdp_req1 cache L3 Misses by Request Type. Ignores SliceID, EnAllSlices, CoreID, EnAllCores and ThreadMask. Requires unit mask 0xFF to engage event for counting event=0x9a,umask=0xff 00 ex_ret_ops core Retired Ops. Use macro_ops_retired instead event=0xc1 00 The number of macro-ops retired ex_ret_brn_misp core Retired Branch Instructions Mispredicted event=0xc3 00 The number of retired branch instructions, that were mispredicted ex_ret_brn_ind_misp core Retired Indirect Branch Instructions Mispredicted event=0xca 00 The number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are counted ex_ret_mmx_fp_instr.sse_instr core SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) event=0xcb,umask=4 00 The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS ex_ret_ind_brch_instr core Retired Indirect Branch Instructions. The number of indirect branches retired event=0xcc 00 ex_ret_msprd_brnch_instr_dir_msmtch core Retired Mispredicted Branch Instructions due to Direction Mismatch event=0x1c7 00 The number of retired conditional branch instructions that were not correctly predicted because of a branch direction mismatch ex_ret_fused_instr core Counts retired Fused Instructions event=0x1d0 00 fp_ret_sse_avx_ops.mac_flops floating point Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=3,umask=8 00 fp_ret_sse_avx_ops.div_flops floating point Divide/square root FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=3,umask=4 00 fp_ret_sse_avx_ops.mult_flops floating point Multiply FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=3,umask=2 00 fp_ret_sse_avx_ops.add_sub_flops floating point Add/subtract FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=3,umask=1 00 fp_retired_ser_ops.sse_bot_ret floating point SSE/AVX bottom-executing ops retired. The number of serializing Ops retired event=5,umask=8 00 fp_retired_ser_ops.sse_ctrl_ret floating point SSE/AVX control word mispredict traps. The number of serializing Ops retired event=5,umask=4 00 fp_retired_ser_ops.x87_bot_ret floating point x87 bottom-executing ops retired. The number of serializing Ops retired event=5,umask=2 00 ls_locks.bus_lock memory Retired lock instructions. Comparable to legacy bus lock event=0x25,umask=1 00 ls_ret_cl_flush memory The number of retired CLFLUSH instructions. This is a non-speculative event event=0x26 00 ls_ret_cpuid memory The number of CPUID instructions retired event=0x27 00 ls_dispatch.ld_st_dispatch memory Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=4 00 ls_dispatch.store_dispatch memory Dispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=2 00 ls_dispatch.ld_dispatch memory Dispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=1 00 ls_smi_rx memory Counts the number of SMIs received event=0x2b 00 ls_int_taken memory Counts the number of interrupts taken event=0x2c 00 ls_st_commit_cancel2.st_commit_cancel_wcb_full memory A non-cacheable store and the non-cacheable commit buffer is full event=0x37,umask=1 00 ls_mab_alloc.all_allocations memory All Allocations. Counts when a LS pipe allocates a MAB entry event=0x41,umask=0x7f 00 ls_mab_alloc.hardware_prefetcher_allocations memory Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entry event=0x41,umask=0x40 00 ls_mab_alloc.load_store_allocations memory Load Store Allocations. Counts when a LS pipe allocates a MAB entry event=0x41,umask=0x3f 00 ls_dmnd_fills_from_sys.mem_io_remote memory Demand Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x43,umask=0x40 00 ls_dmnd_fills_from_sys.ext_cache_remote memory Demand Data Cache Fills by Data Source. From CCX Cache in different Node event=0x43,umask=0x10 00 ls_dmnd_fills_from_sys.mem_io_local memory Demand Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x43,umask=8 00 ls_dmnd_fills_from_sys.ext_cache_local memory Demand Data Cache Fills by Data Source. From cache of different CCX in same node event=0x43,umask=4 00 ls_dmnd_fills_from_sys.int_cache memory Demand Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x43,umask=2 00 ls_dmnd_fills_from_sys.lcl_l2 memory Demand Data Cache Fills by Data Source. From Local L2 to the core event=0x43,umask=1 00 ls_any_fills_from_sys.mem_io_remote memory Any Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x44,umask=0x40 00 ls_any_fills_from_sys.ext_cache_remote memory Any Data Cache Fills by Data Source. From CCX Cache in different Node event=0x44,umask=0x10 00 ls_any_fills_from_sys.mem_io_local memory Any Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x44,umask=8 00 ls_any_fills_from_sys.ext_cache_local memory Any Data Cache Fills by Data Source. From cache of different CCX in same node event=0x44,umask=4 00 ls_any_fills_from_sys.int_cache memory Any Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x44,umask=2 00 ls_any_fills_from_sys.lcl_l2 memory Any Data Cache Fills by Data Source. From Local L2 to the core event=0x44,umask=1 00 ls_l1_d_tlb_miss.all memory All L1 DTLB Misses or Reloads. Use l1_dtlb_misses instead event=0x45,umask=0xff 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB event=0x45,umask=0x80 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB event=0x45,umask=0x40 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss memory L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLB event=0x45,umask=0x20 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLB event=0x45,umask=0x10 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit memory L1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLB event=0x45,umask=2 00 ls_misal_loads.ma4k memory The number of 4KB misaligned (i.e., page crossing) loads event=0x47,umask=2 00 ls_misal_loads.ma64 memory The number of 64B misaligned (i.e., cacheline crossing) loads event=0x47,umask=1 00 ls_pref_instr_disp.prefetch_w memory Software Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHW event=0x4b,umask=2 00 ls_pref_instr_disp.prefetch memory Software Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel event=0x4b,umask=1 00 ls_sw_pf_dc_fills.mem_io_remote memory Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x59,umask=0x40 00 ls_sw_pf_dc_fills.ext_cache_remote memory Software Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node event=0x59,umask=0x10 00 ls_sw_pf_dc_fills.mem_io_local memory Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x59,umask=8 00 ls_sw_pf_dc_fills.ext_cache_local memory Software Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node event=0x59,umask=4 00 ls_sw_pf_dc_fills.int_cache memory Software Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x59,umask=2 00 ls_sw_pf_dc_fills.lcl_l2 memory Software Prefetch Data Cache Fills by Data Source. From Local L2 to the core event=0x59,umask=1 00 ls_hw_pf_dc_fills.mem_io_remote memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x5a,umask=0x40 00 ls_hw_pf_dc_fills.ext_cache_remote memory Hardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node event=0x5a,umask=0x10 00 ls_hw_pf_dc_fills.mem_io_local memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x5a,umask=8 00 ls_hw_pf_dc_fills.ext_cache_local memory Hardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node event=0x5a,umask=4 00 ls_hw_pf_dc_fills.int_cache memory Hardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x5a,umask=2 00 ls_hw_pf_dc_fills.lcl_l2 memory Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to the core event=0x5a,umask=1 00 ls_alloc_mab_count memory Count of Allocated Mabs event=0x5f 00 This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events] ls_tlb_flush.all_tlb_flushes memory All TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed instead event=0x78,umask=0xff 00 de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch other Any Integer dispatch. Types of Oops Dispatched from Decoder event=0xab,umask=8 00 de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch other Any FP dispatch. Types of Oops Dispatched from Decoder event=0xab,umask=4 00 de_dis_dispatch_token_stalls1.fp_flush_recovery_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP Flush recovery stall event=0xae,umask=0x80 00 de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP scheduler resource stall. Applies to ops that use the FP scheduler event=0xae,umask=0x40 00 de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Floating point register file resource stall. Applies to all FP ops that have a destination register event=0xae,umask=0x20 00 de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Taken branch buffer resource stall event=0xae,umask=0x10 00 de_dis_dispatch_token_stalls1.store_queue_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Store Queue resource stall. Applies to all ops with store semantics event=0xae,umask=4 00 de_dis_dispatch_token_stalls1.load_queue_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Load Queue resource stall. Applies to all ops with load semantics event=0xae,umask=2 00 de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Integer Physical Register File resource stall. Integer Physical Register File, applies to all ops that have an integer destination register event=0xae,umask=1 00 de_dis_dispatch_token_stalls2.retire_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Insufficient Retire Queue tokens available event=0xaf,umask=0x20 00 de_dis_dispatch_token_stalls2.agsq_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable event=0xaf,umask=0x10 00 de_dis_dispatch_token_stalls2.int_sch3_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 3 available event=0xaf,umask=8 00 de_dis_dispatch_token_stalls2.int_sch2_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 2 available event=0xaf,umask=4 00 de_dis_dispatch_token_stalls2.int_sch1_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 1 available event=0xaf,umask=2 00 de_dis_dispatch_token_stalls2.int_sch0_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 0 available event=0xaf,umask=1 00 all_data_cache_accesses recommended All L1 Data Cache Accesses event=0x29,umask=7 00 l2_cache_accesses_from_dc_misses recommended L2 Cache Accesses from L1 Data Cache Misses (including prefetch) event=0x60,umask=0xe8 00 l2_cache_hits_from_dc_misses recommended L2 Cache Hits from L1 Data Cache Misses event=0x64,umask=0xf0 00 l2_cache_hits_from_l2_hwpf recommended L2 Cache Hits from L2 Cache HWPF event=0x70,umask=0xff 00 l3_cache_accesses recommended L3 Cache Accesses event=4,umask=0xff 00 l3_misses recommended L3 Misses (includes cacheline state change requests) event=4,umask=1 00 l1_data_cache_fills_from_memory recommended L1 Data Cache Fills: From Memory event=0x44,umask=0x48 00 l1_data_cache_fills_from_remote_node recommended L1 Data Cache Fills: From Remote Node event=0x44,umask=0x50 00 l1_data_cache_fills_from_within_same_ccx recommended L1 Data Cache Fills: From within same CCX event=0x44,umask=3 00 l1_data_cache_fills_from_external_ccx_cache recommended L1 Data Cache Fills: From External CCX Cache event=0x44,umask=0x14 00 l1_data_cache_fills_all recommended L1 Data Cache Fills: All event=0x44,umask=0xff 00 all_tlbs_flushed recommended All TLBs Flushed event=0x78,umask=0xff 00 macro_ops_retired recommended Macro-ops Retired event=0xc1 00 bp_l2_btb_correct branch L2 branch prediction overrides existing prediction (speculative) event=0x8b 00 bp_dyn_ind_pred branch Dynamic indirect predictions (branch used the indirect predictor to make a prediction) event=0x8e 00 bp_de_redirect branch Instruction decoder corrects the predicted target and resteers the branch predictor event=0x91 00 ex_ret_brn branch Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts) event=0xc2 00 ex_ret_brn_misp branch Retired branch instructions mispredicted event=0xc3 00 ex_ret_brn_tkn branch Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts) event=0xc4 00 ex_ret_brn_tkn_misp branch Retired taken branch instructions mispredicted event=0xc5 00 ex_ret_brn_far branch Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction event=0xc6 00 ex_ret_near_ret branch Retired near returns (RET or RET Iw) event=0xc8 00 ex_ret_near_ret_mispred branch Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction event=0xc9 00 ex_ret_brn_ind_misp branch Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction event=0xca 00 ex_ret_ind_brch_instr branch Retired indirect branch instructions event=0xcc 00 ex_ret_cond branch Retired conditional branch instructions event=0xd1 00 ex_ret_msprd_brnch_instr_dir_msmtch branch Retired branch instructions mispredicted due to direction mismatch event=0x1c7 00 ex_ret_uncond_brnch_instr_mispred branch Retired unconditional indirect branch instructions mispredicted event=0x1c8 00 ex_ret_uncond_brnch_instr branch Retired unconditional branch instructions event=0x1c9 00 ls_mab_alloc.load_store_allocations cache Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations event=0x41,umask=0x3f 00 ls_mab_alloc.hardware_prefetcher_allocations cache Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations event=0x41,umask=0x40 00 ls_mab_alloc.all_allocations cache Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations event=0x41,umask=0x7f 00 ls_dmnd_fills_from_sys.local_l2 cache Demand data cache fills from local L2 cache event=0x43,umask=1 00 ls_dmnd_fills_from_sys.local_ccx cache Demand data cache fills from L3 cache or different L2 cache in the same CCX event=0x43,umask=2 00 ls_dmnd_fills_from_sys.near_cache cache Demand data cache fills from cache of another CCX when the address was in the same NUMA node event=0x43,umask=4 00 ls_dmnd_fills_from_sys.dram_io_near cache Demand data cache fills from either DRAM or MMIO in the same NUMA node event=0x43,umask=8 00 ls_dmnd_fills_from_sys.far_cache cache Demand data cache fills from cache of another CCX when the address was in a different NUMA node event=0x43,umask=0x10 00 ls_dmnd_fills_from_sys.dram_io_far cache Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x43,umask=0x40 00 ls_dmnd_fills_from_sys.alternate_memories cache Demand data cache fills from extension memory event=0x43,umask=0x80 00 ls_dmnd_fills_from_sys.all cache Demand data cache fills from all types of data sources event=0x43,umask=0xff 00 ls_any_fills_from_sys.local_l2 cache Any data cache fills from local L2 cache event=0x44,umask=1 00 ls_any_fills_from_sys.local_ccx cache Any data cache fills from L3 cache or different L2 cache in the same CCX event=0x44,umask=2 00 ls_any_fills_from_sys.local_all cache Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX event=0x44,umask=3 00 ls_any_fills_from_sys.near_cache cache Any data cache fills from cache of another CCX when the address was in the same NUMA node event=0x44,umask=4 00 ls_any_fills_from_sys.dram_io_near cache Any data cache fills from either DRAM or MMIO in the same NUMA node event=0x44,umask=8 00 ls_any_fills_from_sys.far_cache cache Any data cache fills from cache of another CCX when the address was in a different NUMA node event=0x44,umask=0x10 00 ls_any_fills_from_sys.remote_cache cache Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node event=0x44,umask=0x14 00 ls_any_fills_from_sys.dram_io_far cache Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x44,umask=0x40 00 ls_any_fills_from_sys.dram_io_all cache Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket) event=0x44,umask=0x48 00 ls_any_fills_from_sys.far_all cache Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket) event=0x44,umask=0x50 00 ls_any_fills_from_sys.all_dram_io cache Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket) event=0x44,umask=0x48 00 ls_any_fills_from_sys.alternate_memories cache Any data cache fills from extension memory event=0x44,umask=0x80 00 ls_any_fills_from_sys.all cache Any data cache fills from all types of data sources event=0x44,umask=0xff 00 ls_pref_instr_disp.prefetch cache Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2) event=0x4b,umask=1 00 ls_pref_instr_disp.prefetch_w cache Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable) event=0x4b,umask=2 00 ls_pref_instr_disp.prefetch_nta cache Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access) event=0x4b,umask=4 00 ls_pref_instr_disp.all cache Software prefetch instructions dispatched (speculative) of all types event=0x4b,umask=7 00 ls_inef_sw_pref.data_pipe_sw_pf_dc_hit cache Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit event=0x52,umask=1 00 ls_inef_sw_pref.mab_mch_cnt cache Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB) event=0x52,umask=2 00 ls_inef_sw_pref.all cache event=0x52,umask=3 00 ls_sw_pf_dc_fills.local_l2 cache Software prefetch data cache fills from local L2 cache event=0x59,umask=1 00 ls_sw_pf_dc_fills.local_ccx cache Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX event=0x59,umask=2 00 ls_sw_pf_dc_fills.near_cache cache Software prefetch data cache fills from cache of another CCX in the same NUMA node event=0x59,umask=4 00 ls_sw_pf_dc_fills.dram_io_near cache Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node event=0x59,umask=8 00 ls_sw_pf_dc_fills.far_cache cache Software prefetch data cache fills from cache of another CCX in a different NUMA node event=0x59,umask=0x10 00 ls_sw_pf_dc_fills.dram_io_far cache Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x59,umask=0x40 00 ls_sw_pf_dc_fills.alternate_memories cache Software prefetch data cache fills from extension memory event=0x59,umask=0x80 00 ls_sw_pf_dc_fills.all cache Software prefetch data cache fills from all types of data sources event=0x59,umask=0xdf 00 ls_hw_pf_dc_fills.local_l2 cache Hardware prefetch data cache fills from local L2 cache event=0x5a,umask=1 00 ls_hw_pf_dc_fills.local_ccx cache Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX event=0x5a,umask=2 00 ls_hw_pf_dc_fills.near_cache cache Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node event=0x5a,umask=4 00 ls_hw_pf_dc_fills.dram_io_near cache Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node event=0x5a,umask=8 00 ls_hw_pf_dc_fills.far_cache cache Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node event=0x5a,umask=0x10 00 ls_hw_pf_dc_fills.dram_io_far cache Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x5a,umask=0x40 00 ls_hw_pf_dc_fills.alternate_memories cache Hardware prefetch data cache fills from extension memory event=0x5a,umask=0x80 00 ls_hw_pf_dc_fills.all cache Hardware prefetch data cache fills from all types of data sources event=0x5a,umask=0xdf 00 ls_alloc_mab_count cache In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle event=0x5f 00 l2_request_g1.group2 cache L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks) event=0x60,umask=1 00 l2_request_g1.l2_hw_pf cache L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss) event=0x60,umask=2 00 l2_request_g1.prefetch_l2_cmd cache L2 cache requests: prefetch directly into L2 event=0x60,umask=4 00 l2_request_g1.change_to_x cache L2 cache requests: data cache state change to writable, check L2 for current state event=0x60,umask=8 00 l2_request_g1.cacheable_ic_read cache L2 cache requests: instruction cache reads event=0x60,umask=0x10 00 l2_request_g1.ls_rd_blk_c_s cache L2 cache requests: data cache shared reads event=0x60,umask=0x20 00 l2_request_g1.rd_blk_x cache L2 cache requests: data cache stores event=0x60,umask=0x40 00 l2_request_g1.rd_blk_l cache L2 cache requests: data cache reads including hardware and software prefetch event=0x60,umask=0x80 00 l2_request_g1.all_dc cache L2 cache requests of common types from L1 data cache (including prefetches) event=0x60,umask=0xe8 00 l2_request_g1.all_no_prefetch cache L2 cache requests of common types not including prefetches event=0x60,umask=0xf9 00 l2_request_g1.all cache L2 cache requests of all types event=0x60,umask=0xff 00 l2_cache_req_stat.ic_fill_miss cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2 event=0x64,umask=1 00 l2_cache_req_stat.ic_fill_hit_s cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2 event=0x64,umask=2 00 l2_cache_req_stat.ic_fill_hit_x cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2 event=0x64,umask=4 00 l2_cache_req_stat.ic_hit_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for instruction cache hits event=0x64,umask=6 00 l2_cache_req_stat.ic_access_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for instruction cache access event=0x64,umask=7 00 l2_cache_req_stat.ls_rd_blk_c cache Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2 event=0x64,umask=8 00 l2_cache_req_stat.ic_dc_miss_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses event=0x64,umask=9 00 l2_cache_req_stat.ls_rd_blk_x cache Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2 event=0x64,umask=0x10 00 l2_cache_req_stat.ls_rd_blk_l_hit_s cache Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2 event=0x64,umask=0x20 00 l2_cache_req_stat.ls_rd_blk_l_hit_x cache Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2 event=0x64,umask=0x40 00 l2_cache_req_stat.ls_rd_blk_cs cache Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2 event=0x64,umask=0x80 00 l2_cache_req_stat.dc_hit_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data cache hits event=0x64,umask=0xf0 00 l2_cache_req_stat.ic_dc_hit_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits event=0x64,umask=0xf6 00 l2_cache_req_stat.dc_access_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data cache access event=0x64,umask=0xf8 00 l2_cache_req_stat.all cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access event=0x64,umask=0xff 00 l2_pf_hit_l2.l2_stream cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stream (fetch additional sequential lines into L2 cache) event=0x70,umask=1 00 l2_pf_hit_l2.l2_next_line cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2NextLine (fetch the next line into L2 cache) event=0x70,umask=2 00 l2_pf_hit_l2.l2_up_down cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) event=0x70,umask=4 00 l2_pf_hit_l2.l2_burst cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache) event=0x70,umask=8 00 l2_pf_hit_l2.l2_stride cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stride (fetch additional lines into L2 cache when each access is at a constant distance from the previous) event=0x70,umask=0x10 00 l2_pf_hit_l2.l1_stream cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stream (fetch additional sequential lines into L1 cache) event=0x70,umask=0x20 00 l2_pf_hit_l2.l1_stride cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) event=0x70,umask=0x40 00 l2_pf_hit_l2.l1_region cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) event=0x70,umask=0x80 00 l2_pf_hit_l2.all cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all types event=0x70,umask=0xff 00 l2_pf_miss_l2_hit_l3.l2_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stream (fetch additional sequential lines into L2 cache) event=0x71,umask=1 00 l2_pf_miss_l2_hit_l3.l2_next_line cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2NextLine (fetch the next line into L2 cache) event=0x71,umask=2 00 l2_pf_miss_l2_hit_l3.l2_up_down cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) event=0x71,umask=4 00 l2_pf_miss_l2_hit_l3.l2_burst cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache) event=0x71,umask=8 00 l2_pf_miss_l2_hit_l3.l2_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous) event=0x71,umask=0x10 00 l2_pf_miss_l2_hit_l3.l1_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stream (fetch additional sequential lines into L1 cache) event=0x71,umask=0x20 00 l2_pf_miss_l2_hit_l3.l1_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) event=0x71,umask=0x40 00 l2_pf_miss_l2_hit_l3.l1_region cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) event=0x71,umask=0x80 00 l2_pf_miss_l2_hit_l3.all cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache cache of all types event=0x71,umask=0xff 00 l2_pf_miss_l2_l3.l2_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stream (fetch additional sequential lines into L2 cache) event=0x72,umask=1 00 l2_pf_miss_l2_l3.l2_next_line cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2NextLine (fetch the next line into L2 cache) event=0x72,umask=2 00 l2_pf_miss_l2_l3.l2_up_down cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) event=0x72,umask=4 00 l2_pf_miss_l2_l3.l2_burst cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Burst (aggressively fetch additional sequential lines into L2 cache) event=0x72,umask=8 00 l2_pf_miss_l2_l3.l2_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous) event=0x72,umask=0x10 00 l2_pf_miss_l2_l3.l1_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stream (fetch additional sequential lines into L1 cache) event=0x72,umask=0x20 00 l2_pf_miss_l2_l3.l1_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) event=0x72,umask=0x40 00 l2_pf_miss_l2_l3.l1_region cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) event=0x72,umask=0x80 00 l2_pf_miss_l2_l3.all cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of all types event=0x72,umask=0xff 00 ic_cache_fill_l2 cache Instruction cache lines (64 bytes) fulfilled from the L2 cache event=0x82 00 ic_cache_fill_sys cache Instruction cache lines (64 bytes) fulfilled from system memory or another cache event=0x83 00 ic_tag_hit_miss.instruction_cache_hit cache Instruction cache hits event=0x18e,umask=7 00 ic_tag_hit_miss.instruction_cache_miss cache Instruction cache misses event=0x18e,umask=0x18 00 ic_tag_hit_miss.all_instruction_cache_accesses cache Instruction cache accesses of all types event=0x18e,umask=0x1f 00 op_cache_hit_miss.op_cache_hit cache Op cache hits event=0x28f,umask=3 00 op_cache_hit_miss.op_cache_miss cache Op cache misses event=0x28f,umask=4 00 op_cache_hit_miss.all_op_cache_accesses cache Op cache accesses of all types event=0x28f,umask=7 00 l3_lookup_state.l3_miss cache L3 cache misses event=4,umask=1 00 l3_lookup_state.l3_hit cache L3 cache hits event=4,umask=0xfe 00 l3_lookup_state.all_coherent_accesses_to_l3 cache L3 cache requests for all coherent accesses event=4,umask=0xff 00 l3_xi_sampled_latency.dram_near cache Average sampled latency when data is sourced from DRAM in the same NUMA node event=0xac,umask=1,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.dram_far cache Average sampled latency when data is sourced from DRAM in a different NUMA node event=0xac,umask=2,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.near_cache cache Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node event=0xac,umask=4,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.far_cache cache Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node event=0xac,umask=8,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.ext_near cache Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node event=0xac,umask=0x10,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.ext_far cache Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node event=0xac,umask=0x20,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.all cache Average sampled latency from all data sources event=0xac,umask=0x3f,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.dram_near cache L3 cache fill requests sourced from DRAM in the same NUMA node event=0xad,umask=1,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.dram_far cache L3 cache fill requests sourced from DRAM in a different NUMA node event=0xad,umask=2,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.near_cache cache L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node event=0xad,umask=4,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.far_cache cache L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node event=0xad,umask=8,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.ext_near cache L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node event=0xad,umask=0x10,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.ext_far cache L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node event=0xad,umask=0x20,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.all cache L3 cache fill requests sourced from all data sources event=0xad,umask=0x3f,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 ls_locks.bus_lock core Retired Lock instructions which caused a bus lock event=0x25,umask=1 00 ls_ret_cl_flush core Retired CLFLUSH instructions event=0x26 00 ls_ret_cpuid core Retired CPUID instructions event=0x27 00 ls_smi_rx core SMIs received event=0x2b 00 ls_int_taken core Interrupts taken event=0x2c 00 ls_not_halted_cyc core Core cycles not in halt event=0x76 00 ex_ret_instr core Retired instructions event=0xc0 00 ex_ret_ops core Retired macro-ops event=0xc1 00 ex_div_busy core Number of cycles the divider is busy event=0xd3 00 ex_div_count core Divide ops executed event=0xd4 00 ex_no_retire.empty core Cycles with no retire due to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects) event=0xd6,umask=1 00 ex_no_retire.not_complete core Cycles with no retire while the oldest op is waiting to be executed event=0xd6,umask=2 00 ex_no_retire.other core Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.) event=0xd6,umask=8 00 ex_no_retire.thread_not_selected core Cycles with no retire because thread arbitration did not select the thread event=0xd6,umask=0x10 00 ex_no_retire.load_not_complete core Cycles with no retire while the oldest op is waiting for load data event=0xd6,umask=0xa2 00 ex_no_retire.all core Cycles with no retire for any reason event=0xd6,umask=0x1b 00 ls_not_halted_p0_cyc.p0_freq_cyc core Reference cycles (P0 frequency) not in halt event=0x120,umask=1 00 ex_ret_ucode_instr core Retired microcoded instructions event=0x1c1 00 ex_ret_ucode_ops core Retired microcode ops event=0x1c2 00 ex_tagged_ibs_ops.ibs_tagged_ops core Ops tagged by IBS event=0x1cf,umask=1 00 ex_tagged_ibs_ops.ibs_tagged_ops_ret core Ops tagged by IBS that retired event=0x1cf,umask=2 00 ex_ret_fused_instr core Retired fused instructions event=0x1d0 00 local_processor_read_data_beats_cs0 data fabric event=0x1f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 0 local_processor_read_data_beats_cs1 data fabric event=0x5f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 1 local_processor_read_data_beats_cs2 data fabric event=0x9f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 2 local_processor_read_data_beats_cs3 data fabric event=0xdf,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 3 local_processor_read_data_beats_cs4 data fabric event=0x11f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 4 local_processor_read_data_beats_cs5 data fabric event=0x15f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 5 local_processor_read_data_beats_cs6 data fabric event=0x19f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 6 local_processor_read_data_beats_cs7 data fabric event=0x1df,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 7 local_processor_read_data_beats_cs8 data fabric event=0x21f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 8 local_processor_read_data_beats_cs9 data fabric event=0x25f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 9 local_processor_read_data_beats_cs10 data fabric event=0x29f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 10 local_processor_read_data_beats_cs11 data fabric event=0x2df,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 11 local_processor_write_data_beats_cs0 data fabric event=0x1f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 0 local_processor_write_data_beats_cs1 data fabric event=0x5f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 1 local_processor_write_data_beats_cs2 data fabric event=0x9f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 2 local_processor_write_data_beats_cs3 data fabric event=0xdf,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 3 local_processor_write_data_beats_cs4 data fabric event=0x11f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 4 local_processor_write_data_beats_cs5 data fabric event=0x15f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 5 local_processor_write_data_beats_cs6 data fabric event=0x19f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 6 local_processor_write_data_beats_cs7 data fabric event=0x1df,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 7 local_processor_write_data_beats_cs8 data fabric event=0x21f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 8 local_processor_write_data_beats_cs9 data fabric event=0x25f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 9 local_processor_write_data_beats_cs10 data fabric event=0x29f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 10 local_processor_write_data_beats_cs11 data fabric event=0x2df,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 11 remote_processor_read_data_beats_cs0 data fabric event=0x1f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 0 remote_processor_read_data_beats_cs1 data fabric event=0x5f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 1 remote_processor_read_data_beats_cs2 data fabric event=0x9f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 2 remote_processor_read_data_beats_cs3 data fabric event=0xdf,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 3 remote_processor_read_data_beats_cs4 data fabric event=0x11f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 4 remote_processor_read_data_beats_cs5 data fabric event=0x15f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 5 remote_processor_read_data_beats_cs6 data fabric event=0x19f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 6 remote_processor_read_data_beats_cs7 data fabric event=0x1df,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 7 remote_processor_read_data_beats_cs8 data fabric event=0x21f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 8 remote_processor_read_data_beats_cs9 data fabric event=0x25f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 9 remote_processor_read_data_beats_cs10 data fabric event=0x29f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 10 remote_processor_read_data_beats_cs11 data fabric event=0x2df,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 11 remote_processor_write_data_beats_cs0 data fabric event=0x1f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 0 remote_processor_write_data_beats_cs1 data fabric event=0x5f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 1 remote_processor_write_data_beats_cs2 data fabric event=0x9f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 2 remote_processor_write_data_beats_cs3 data fabric event=0xdf,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 3 remote_processor_write_data_beats_cs4 data fabric event=0x11f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 4 remote_processor_write_data_beats_cs5 data fabric event=0x15f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 5 remote_processor_write_data_beats_cs6 data fabric event=0x19f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 6 remote_processor_write_data_beats_cs7 data fabric event=0x1df,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 7 remote_processor_write_data_beats_cs8 data fabric event=0x21f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 8 remote_processor_write_data_beats_cs9 data fabric event=0x25f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 9 remote_processor_write_data_beats_cs10 data fabric event=0x29f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 10 remote_processor_write_data_beats_cs11 data fabric event=0x2df,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 11 local_socket_upstream_read_beats_iom0 data fabric event=0x81f,umask=0x7fe 01 Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0 local_socket_upstream_read_beats_iom1 data fabric event=0x85f,umask=0x7fe 01 Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1 local_socket_upstream_read_beats_iom2 data fabric event=0x89f,umask=0x7fe 01 Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2 local_socket_upstream_read_beats_iom3 data fabric event=0x8df,umask=0x7fe 01 Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3 local_socket_upstream_write_beats_iom0 data fabric event=0x81f,umask=0x7ff 01 Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0 local_socket_upstream_write_beats_iom1 data fabric event=0x85f,umask=0x7ff 01 Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1 local_socket_upstream_write_beats_iom2 data fabric event=0x89f,umask=0x7ff 01 Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2 local_socket_upstream_write_beats_iom3 data fabric event=0x8df,umask=0x7ff 01 Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3 remote_socket_upstream_read_beats_iom0 data fabric event=0x81f,umask=0xbfe 01 Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0 remote_socket_upstream_read_beats_iom1 data fabric event=0x85f,umask=0xbfe 01 Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1 remote_socket_upstream_read_beats_iom2 data fabric event=0x89f,umask=0xbfe 01 Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2 remote_socket_upstream_read_beats_iom3 data fabric event=0x8df,umask=0xbfe 01 Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3 remote_socket_upstream_write_beats_iom0 data fabric event=0x81f,umask=0xbff 01 Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0 remote_socket_upstream_write_beats_iom1 data fabric event=0x85f,umask=0xbff 01 Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1 remote_socket_upstream_write_beats_iom2 data fabric event=0x89f,umask=0xbff 01 Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2 remote_socket_upstream_write_beats_iom3 data fabric event=0x8df,umask=0xbff 01 Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3 local_socket_inf0_inbound_data_beats_ccm0 data fabric event=0x41e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 0 local_socket_inf0_inbound_data_beats_ccm1 data fabric event=0x45e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 1 local_socket_inf0_inbound_data_beats_ccm2 data fabric event=0x49e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 2 local_socket_inf0_inbound_data_beats_ccm3 data fabric event=0x4de,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 3 local_socket_inf0_inbound_data_beats_ccm4 data fabric event=0x51e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 4 local_socket_inf0_inbound_data_beats_ccm5 data fabric event=0x55e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 5 local_socket_inf0_inbound_data_beats_ccm6 data fabric event=0x59e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 6 local_socket_inf0_inbound_data_beats_ccm7 data fabric event=0x5de,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 7 local_socket_inf1_inbound_data_beats_ccm0 data fabric event=0x41f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 0 local_socket_inf1_inbound_data_beats_ccm1 data fabric event=0x45f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 1 local_socket_inf1_inbound_data_beats_ccm2 data fabric event=0x49f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 2 local_socket_inf1_inbound_data_beats_ccm3 data fabric event=0x4df,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 3 local_socket_inf1_inbound_data_beats_ccm4 data fabric event=0x51f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 4 local_socket_inf1_inbound_data_beats_ccm5 data fabric event=0x55f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 5 local_socket_inf1_inbound_data_beats_ccm6 data fabric event=0x59f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 6 local_socket_inf1_inbound_data_beats_ccm7 data fabric event=0x5df,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 7 local_socket_inf0_outbound_data_beats_ccm0 data fabric event=0x41e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 0 local_socket_inf0_outbound_data_beats_ccm1 data fabric event=0x45e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 1 local_socket_inf0_outbound_data_beats_ccm2 data fabric event=0x49e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 2 local_socket_inf0_outbound_data_beats_ccm3 data fabric event=0x4de,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 3 local_socket_inf0_outbound_data_beats_ccm4 data fabric event=0x51e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 4 local_socket_inf0_outbound_data_beats_ccm5 data fabric event=0x55e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 5 local_socket_inf0_outbound_data_beats_ccm6 data fabric event=0x59e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 6 local_socket_inf0_outbound_data_beats_ccm7 data fabric event=0x5de,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 7 local_socket_inf1_outbound_data_beats_ccm0 data fabric event=0x41f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 0 local_socket_inf1_outbound_data_beats_ccm1 data fabric event=0x45f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 1 local_socket_inf1_outbound_data_beats_ccm2 data fabric event=0x49f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 2 local_socket_inf1_outbound_data_beats_ccm3 data fabric event=0x4df,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 3 local_socket_inf1_outbound_data_beats_ccm4 data fabric event=0x51f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 4 local_socket_inf1_outbound_data_beats_ccm5 data fabric event=0x55f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 5 local_socket_inf1_outbound_data_beats_ccm6 data fabric event=0x59f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 6 local_socket_inf1_outbound_data_beats_ccm7 data fabric event=0x5df,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 7 remote_socket_inf0_inbound_data_beats_ccm0 data fabric event=0x41e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 0 remote_socket_inf0_inbound_data_beats_ccm1 data fabric event=0x45e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 1 remote_socket_inf0_inbound_data_beats_ccm2 data fabric event=0x49e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 2 remote_socket_inf0_inbound_data_beats_ccm3 data fabric event=0x4de,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 3 remote_socket_inf0_inbound_data_beats_ccm4 data fabric event=0x51e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 4 remote_socket_inf0_inbound_data_beats_ccm5 data fabric event=0x55e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 5 remote_socket_inf0_inbound_data_beats_ccm6 data fabric event=0x59e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 6 remote_socket_inf0_inbound_data_beats_ccm7 data fabric event=0x5de,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 7 remote_socket_inf1_inbound_data_beats_ccm0 data fabric event=0x41f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 0 remote_socket_inf1_inbound_data_beats_ccm1 data fabric event=0x45f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 1 remote_socket_inf1_inbound_data_beats_ccm2 data fabric event=0x49f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 2 remote_socket_inf1_inbound_data_beats_ccm3 data fabric event=0x4df,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 3 remote_socket_inf1_inbound_data_beats_ccm4 data fabric event=0x51f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 4 remote_socket_inf1_inbound_data_beats_ccm5 data fabric event=0x55f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 5 remote_socket_inf1_inbound_data_beats_ccm6 data fabric event=0x59f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 6 remote_socket_inf1_inbound_data_beats_ccm7 data fabric event=0x5df,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 7 remote_socket_inf0_outbound_data_beats_ccm0 data fabric event=0x41e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 0 remote_socket_inf0_outbound_data_beats_ccm1 data fabric event=0x45e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 1 remote_socket_inf0_outbound_data_beats_ccm2 data fabric event=0x49e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 2 remote_socket_inf0_outbound_data_beats_ccm3 data fabric event=0x4de,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 3 remote_socket_inf0_outbound_data_beats_ccm4 data fabric event=0x51e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 4 remote_socket_inf0_outbound_data_beats_ccm5 data fabric event=0x55e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 5 remote_socket_inf0_outbound_data_beats_ccm6 data fabric event=0x59e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 6 remote_socket_inf0_outbound_data_beats_ccm7 data fabric event=0x5de,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 7 remote_socket_inf1_outbound_data_beats_ccm0 data fabric event=0x41f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 0 remote_socket_inf1_outbound_data_beats_ccm1 data fabric event=0x45f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 1 remote_socket_inf1_outbound_data_beats_ccm2 data fabric event=0x49f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 2 remote_socket_inf1_outbound_data_beats_ccm3 data fabric event=0x4df,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 3 remote_socket_inf1_outbound_data_beats_ccm4 data fabric event=0x51f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 4 remote_socket_inf1_outbound_data_beats_ccm5 data fabric event=0x55f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 5 remote_socket_inf1_outbound_data_beats_ccm6 data fabric event=0x59f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 6 remote_socket_inf1_outbound_data_beats_ccm7 data fabric event=0x5df,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 7 local_socket_outbound_data_beats_link0 data fabric event=0xb5f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 0 local_socket_outbound_data_beats_link1 data fabric event=0xb9f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 1 local_socket_outbound_data_beats_link2 data fabric event=0xbdf,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 2 local_socket_outbound_data_beats_link3 data fabric event=0xc1f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 3 local_socket_outbound_data_beats_link4 data fabric event=0xc5f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 4 local_socket_outbound_data_beats_link5 data fabric event=0xc9f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 5 local_socket_outbound_data_beats_link6 data fabric event=0xcdf,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 6 local_socket_outbound_data_beats_link7 data fabric event=0xd1f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 7 fp_ret_x87_fp_ops.add_sub_ops floating point Retired x87 floating-point add and subtract ops event=2,umask=1 00 fp_ret_x87_fp_ops.mul_ops floating point Retired x87 floating-point multiply ops event=2,umask=2 00 fp_ret_x87_fp_ops.div_sqrt_ops floating point Retired x87 floating-point divide and square root ops event=2,umask=4 00 fp_ret_x87_fp_ops.all floating point Retired x87 floating-point ops of all types event=2,umask=7 00 fp_ret_sse_avx_ops.add_sub_flops floating point Retired SSE and AVX floating-point add and subtract ops event=3,umask=1 00 fp_ret_sse_avx_ops.mult_flops floating point Retired SSE and AVX floating-point multiply ops event=3,umask=2 00 fp_ret_sse_avx_ops.div_flops floating point Retired SSE and AVX floating-point divide and square root ops event=3,umask=4 00 fp_ret_sse_avx_ops.mac_flops floating point Retired SSE and AVX floating-point multiply-accumulate ops (each operation is counted as 2 ops) event=3,umask=8 00 fp_ret_sse_avx_ops.bfloat_mac_flops floating point Retired SSE and AVX floating-point bfloat multiply-accumulate ops (each operation is counted as 2 ops) event=3,umask=0x10 00 fp_ret_sse_avx_ops.all floating point Retired SSE and AVX floating-point ops of all types event=3,umask=0x1f 00 fp_retired_ser_ops.x87_ctrl_ret floating point Retired x87 control word mispredict traps due to mispredictions in RC or PC, or changes in exception mask bits event=5,umask=1 00 fp_retired_ser_ops.x87_bot_ret floating point Retired x87 bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing event=5,umask=2 00 fp_retired_ser_ops.sse_ctrl_ret floating point Retired SSE and AVX control word mispredict traps event=5,umask=4 00 fp_retired_ser_ops.sse_bot_ret floating point Retired SSE and AVX bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing event=5,umask=8 00 fp_retired_ser_ops.all floating point Retired SSE and AVX serializing ops of all types event=5,umask=0xf 00 fp_ops_retired_by_width.x87_uops_retired floating point Retired x87 floating-point ops event=8,umask=1 00 fp_ops_retired_by_width.mmx_uops_retired floating point Retired MMX floating-point ops event=8,umask=2 00 fp_ops_retired_by_width.scalar_uops_retired floating point Retired scalar floating-point ops event=8,umask=4 00 fp_ops_retired_by_width.pack_128_uops_retired floating point Retired packed 128-bit floating-point ops event=8,umask=8 00 fp_ops_retired_by_width.pack_256_uops_retired floating point Retired packed 256-bit floating-point ops event=8,umask=0x10 00 fp_ops_retired_by_width.pack_512_uops_retired floating point Retired packed 512-bit floating-point ops event=8,umask=0x20 00 fp_ops_retired_by_width.all floating point Retired floating-point ops of all widths event=8,umask=0x3f 00 fp_ops_retired_by_type.scalar_add floating point Retired scalar floating-point add ops event=0xa,umask=1 00 fp_ops_retired_by_type.scalar_sub floating point Retired scalar floating-point subtract ops event=0xa,umask=2 00 fp_ops_retired_by_type.scalar_mul floating point Retired scalar floating-point multiply ops event=0xa,umask=3 00 fp_ops_retired_by_type.scalar_mac floating point Retired scalar floating-point multiply-accumulate ops event=0xa,umask=4 00 fp_ops_retired_by_type.scalar_div floating point Retired scalar floating-point divide ops event=0xa,umask=5 00 fp_ops_retired_by_type.scalar_sqrt floating point Retired scalar floating-point square root ops event=0xa,umask=6 00 fp_ops_retired_by_type.scalar_cmp floating point Retired scalar floating-point compare ops event=0xa,umask=7 00 fp_ops_retired_by_type.scalar_cvt floating point Retired scalar floating-point convert ops event=0xa,umask=8 00 fp_ops_retired_by_type.scalar_blend floating point Retired scalar floating-point blend ops event=0xa,umask=9 00 fp_ops_retired_by_type.scalar_other floating point Retired scalar floating-point ops of other types event=0xa,umask=0xe 00 fp_ops_retired_by_type.scalar_all floating point Retired scalar floating-point ops of all types event=0xa,umask=0xf 00 fp_ops_retired_by_type.vector_add floating point Retired vector floating-point add ops event=0xa,umask=0x10 00 fp_ops_retired_by_type.vector_sub floating point Retired vector floating-point subtract ops event=0xa,umask=0x20 00 fp_ops_retired_by_type.vector_mul floating point Retired vector floating-point multiply ops event=0xa,umask=0x30 00 fp_ops_retired_by_type.vector_mac floating point Retired vector floating-point multiply-accumulate ops event=0xa,umask=0x40 00 fp_ops_retired_by_type.vector_div floating point Retired vector floating-point divide ops event=0xa,umask=0x50 00 fp_ops_retired_by_type.vector_sqrt floating point Retired vector floating-point square root ops event=0xa,umask=0x60 00 fp_ops_retired_by_type.vector_cmp floating point Retired vector floating-point compare ops event=0xa,umask=0x70 00 fp_ops_retired_by_type.vector_cvt floating point Retired vector floating-point convert ops event=0xa,umask=0x80 00 fp_ops_retired_by_type.vector_blend floating point Retired vector floating-point blend ops event=0xa,umask=0x90 00 fp_ops_retired_by_type.vector_shuffle floating point Retired vector floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xa,umask=0xb0 00 fp_ops_retired_by_type.vector_logical floating point Retired vector floating-point logical ops event=0xa,umask=0xd0 00 fp_ops_retired_by_type.vector_other floating point Retired vector floating-point ops of other types event=0xa,umask=0xe0 00 fp_ops_retired_by_type.vector_all floating point Retired vector floating-point ops of all types event=0xa,umask=0xf0 00 fp_ops_retired_by_type.all floating point Retired floating-point ops of all types event=0xa,umask=0xff 00 sse_avx_ops_retired.mmx_add floating point Retired MMX integer add event=0xb,umask=1 00 sse_avx_ops_retired.mmx_sub floating point Retired MMX integer subtract ops event=0xb,umask=2 00 sse_avx_ops_retired.mmx_mul floating point Retired MMX integer multiply ops event=0xb,umask=3 00 sse_avx_ops_retired.mmx_mac floating point Retired MMX integer multiply-accumulate ops event=0xb,umask=4 00 sse_avx_ops_retired.mmx_cmp floating point Retired MMX integer compare ops event=0xb,umask=7 00 sse_avx_ops_retired.mmx_shift floating point Retired MMX integer shift ops event=0xb,umask=9 00 sse_avx_ops_retired.mmx_mov floating point Retired MMX integer MOV ops event=0xb,umask=0xa 00 sse_avx_ops_retired.mmx_shuffle floating point Retired MMX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xb,umask=0xb 00 sse_avx_ops_retired.mmx_pack floating point Retired MMX integer pack ops event=0xb,umask=0xc 00 sse_avx_ops_retired.mmx_logical floating point Retired MMX integer logical ops event=0xb,umask=0xd 00 sse_avx_ops_retired.mmx_other floating point Retired MMX integer multiply ops of other types event=0xb,umask=0xe 00 sse_avx_ops_retired.mmx_all floating point Retired MMX integer ops of all types event=0xb,umask=0xf 00 sse_avx_ops_retired.sse_avx_add floating point Retired SSE and AVX integer add ops event=0xb,umask=0x10 00 sse_avx_ops_retired.sse_avx_sub floating point Retired SSE and AVX integer subtract ops event=0xb,umask=0x20 00 sse_avx_ops_retired.sse_avx_mul floating point Retired SSE and AVX integer multiply ops event=0xb,umask=0x30 00 sse_avx_ops_retired.sse_avx_mac floating point Retired SSE and AVX integer multiply-accumulate ops event=0xb,umask=0x40 00 sse_avx_ops_retired.sse_avx_aes floating point Retired SSE and AVX integer AES ops event=0xb,umask=0x50 00 sse_avx_ops_retired.sse_avx_sha floating point Retired SSE and AVX integer SHA ops event=0xb,umask=0x60 00 sse_avx_ops_retired.sse_avx_cmp floating point Retired SSE and AVX integer compare ops event=0xb,umask=0x70 00 sse_avx_ops_retired.sse_avx_clm floating point Retired SSE and AVX integer CLM ops event=0xb,umask=0x80 00 sse_avx_ops_retired.sse_avx_shift floating point Retired SSE and AVX integer shift ops event=0xb,umask=0x90 00 sse_avx_ops_retired.sse_avx_mov floating point Retired SSE and AVX integer MOV ops event=0xb,umask=0xa0 00 sse_avx_ops_retired.sse_avx_shuffle floating point Retired SSE and AVX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xb,umask=0xb0 00 sse_avx_ops_retired.sse_avx_pack floating point Retired SSE and AVX integer pack ops event=0xb,umask=0xc0 00 sse_avx_ops_retired.sse_avx_logical floating point Retired SSE and AVX integer logical ops event=0xb,umask=0xd0 00 sse_avx_ops_retired.sse_avx_other floating point Retired SSE and AVX integer ops of other types event=0xb,umask=0xe0 00 sse_avx_ops_retired.sse_avx_all floating point Retired SSE and AVX integer ops of all types event=0xb,umask=0xf0 00 sse_avx_ops_retired.all floating point Retired SSE, AVX and MMX integer ops of all types event=0xb,umask=0xff 00 fp_pack_ops_retired.fp128_add floating point Retired 128-bit packed floating-point add ops event=0xc,umask=1 00 fp_pack_ops_retired.fp128_sub floating point Retired 128-bit packed floating-point subtract ops event=0xc,umask=2 00 fp_pack_ops_retired.fp128_mul floating point Retired 128-bit packed floating-point multiply ops event=0xc,umask=3 00 fp_pack_ops_retired.fp128_mac floating point Retired 128-bit packed floating-point multiply-accumulate ops event=0xc,umask=4 00 fp_pack_ops_retired.fp128_div floating point Retired 128-bit packed floating-point divide ops event=0xc,umask=5 00 fp_pack_ops_retired.fp128_sqrt floating point Retired 128-bit packed floating-point square root ops event=0xc,umask=6 00 fp_pack_ops_retired.fp128_cmp floating point Retired 128-bit packed floating-point compare ops event=0xc,umask=7 00 fp_pack_ops_retired.fp128_cvt floating point Retired 128-bit packed floating-point convert ops event=0xc,umask=8 00 fp_pack_ops_retired.fp128_blend floating point Retired 128-bit packed floating-point blend ops event=0xc,umask=9 00 fp_pack_ops_retired.fp128_shuffle floating point Retired 128-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xc,umask=0xb 00 fp_pack_ops_retired.fp128_logical floating point Retired 128-bit packed floating-point logical ops event=0xc,umask=0xd 00 fp_pack_ops_retired.fp128_other floating point Retired 128-bit packed floating-point ops of other types event=0xc,umask=0xe 00 fp_pack_ops_retired.fp128_all floating point Retired 128-bit packed floating-point ops of all types event=0xc,umask=0xf 00 fp_pack_ops_retired.fp256_add floating point Retired 256-bit packed floating-point add ops event=0xc,umask=0x10 00 fp_pack_ops_retired.fp256_sub floating point Retired 256-bit packed floating-point subtract ops event=0xc,umask=0x20 00 fp_pack_ops_retired.fp256_mul floating point Retired 256-bit packed floating-point multiply ops event=0xc,umask=0x30 00 fp_pack_ops_retired.fp256_mac floating point Retired 256-bit packed floating-point multiply-accumulate ops event=0xc,umask=0x40 00 fp_pack_ops_retired.fp256_div floating point Retired 256-bit packed floating-point divide ops event=0xc,umask=0x50 00 fp_pack_ops_retired.fp256_sqrt floating point Retired 256-bit packed floating-point square root ops event=0xc,umask=0x60 00 fp_pack_ops_retired.fp256_cmp floating point Retired 256-bit packed floating-point compare ops event=0xc,umask=0x70 00 fp_pack_ops_retired.fp256_cvt floating point Retired 256-bit packed floating-point convert ops event=0xc,umask=0x80 00 fp_pack_ops_retired.fp256_blend floating point Retired 256-bit packed floating-point blend ops event=0xc,umask=0x90 00 fp_pack_ops_retired.fp256_shuffle floating point Retired 256-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xc,umask=0xb0 00 fp_pack_ops_retired.fp256_logical floating point Retired 256-bit packed floating-point logical ops event=0xc,umask=0xd0 00 fp_pack_ops_retired.fp256_other floating point Retired 256-bit packed floating-point ops of other types event=0xc,umask=0xe0 00 fp_pack_ops_retired.fp256_all floating point Retired 256-bit packed floating-point ops of all types event=0xc,umask=0xf0 00 fp_pack_ops_retired.all floating point Retired packed floating-point ops of all types event=0xc,umask=0xff 00 packed_int_op_type.int128_add floating point Retired 128-bit packed integer add ops event=0xd,umask=1 00 packed_int_op_type.int128_sub floating point Retired 128-bit packed integer subtract ops event=0xd,umask=2 00 packed_int_op_type.int128_mul floating point Retired 128-bit packed integer multiply ops event=0xd,umask=3 00 packed_int_op_type.int128_mac floating point Retired 128-bit packed integer multiply-accumulate ops event=0xd,umask=4 00 packed_int_op_type.int128_aes floating point Retired 128-bit packed integer AES ops event=0xd,umask=5 00 packed_int_op_type.int128_sha floating point Retired 128-bit packed integer SHA ops event=0xd,umask=6 00 packed_int_op_type.int128_cmp floating point Retired 128-bit packed integer compare ops event=0xd,umask=7 00 packed_int_op_type.int128_clm floating point Retired 128-bit packed integer CLM ops event=0xd,umask=8 00 packed_int_op_type.int128_shift floating point Retired 128-bit packed integer shift ops event=0xd,umask=9 00 packed_int_op_type.int128_mov floating point Retired 128-bit packed integer MOV ops event=0xd,umask=0xa 00 packed_int_op_type.int128_shuffle floating point Retired 128-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xd,umask=0xb 00 packed_int_op_type.int128_pack floating point Retired 128-bit packed integer pack ops event=0xd,umask=0xc 00 packed_int_op_type.int128_logical floating point Retired 128-bit packed integer logical ops event=0xd,umask=0xd 00 packed_int_op_type.int128_other floating point Retired 128-bit packed integer ops of other types event=0xd,umask=0xe 00 packed_int_op_type.int128_all floating point Retired 128-bit packed integer ops of all types event=0xd,umask=0xf 00 packed_int_op_type.int256_add floating point Retired 256-bit packed integer add ops event=0xd,umask=0x10 00 packed_int_op_type.int256_sub floating point Retired 256-bit packed integer subtract ops event=0xd,umask=0x20 00 packed_int_op_type.int256_mul floating point Retired 256-bit packed integer multiply ops event=0xd,umask=0x30 00 packed_int_op_type.int256_mac floating point Retired 256-bit packed integer multiply-accumulate ops event=0xd,umask=0x40 00 packed_int_op_type.int256_cmp floating point Retired 256-bit packed integer compare ops event=0xd,umask=0x70 00 packed_int_op_type.int256_shift floating point Retired 256-bit packed integer shift ops event=0xd,umask=0x90 00 packed_int_op_type.int256_mov floating point Retired 256-bit packed integer MOV ops event=0xd,umask=0xa0 00 packed_int_op_type.int256_shuffle floating point Retired 256-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xd,umask=0xb0 00 packed_int_op_type.int256_pack floating point Retired 256-bit packed integer pack ops event=0xd,umask=0xc0 00 packed_int_op_type.int256_logical floating point Retired 256-bit packed integer logical ops event=0xd,umask=0xd0 00 packed_int_op_type.int256_other floating point Retired 256-bit packed integer ops of other types event=0xd,umask=0xe0 00 packed_int_op_type.int256_all floating point Retired 256-bit packed integer ops of all types event=0xd,umask=0xf0 00 packed_int_op_type.all floating point Retired packed integer ops of all types event=0xd,umask=0xff 00 fp_disp_faults.x87_fill_fault floating point Floating-point dispatch faults for x87 fills event=0xe,umask=1 00 fp_disp_faults.xmm_fill_fault floating point Floating-point dispatch faults for XMM fills event=0xe,umask=2 00 fp_disp_faults.ymm_fill_fault floating point Floating-point dispatch faults for YMM fills event=0xe,umask=4 00 fp_disp_faults.ymm_spill_fault floating point Floating-point dispatch faults for YMM spills event=0xe,umask=8 00 fp_disp_faults.sse_avx_all floating point Floating-point dispatch faults of all types for SSE and AVX ops event=0xe,umask=0xe 00 fp_disp_faults.all floating point Floating-point dispatch faults of all types event=0xe,umask=0xf 00 amd_umc umc_mem_clk memory controller event=0 01 Number of memory clock cycles umc_act_cmd.all memory controller event=5 01 Number of ACTIVATE commands sent umc_act_cmd.rd memory controller event=5,rdwrmask=1 01 Number of ACTIVATE commands sent for reads umc_act_cmd.wr memory controller event=5,rdwrmask=2 01 Number of ACTIVATE commands sent for writes umc_pchg_cmd.all memory controller event=6 01 Number of PRECHARGE commands sent umc_pchg_cmd.rd memory controller event=6,rdwrmask=1 01 Number of PRECHARGE commands sent for reads umc_pchg_cmd.wr memory controller event=6,rdwrmask=2 01 Number of PRECHARGE commands sent for writes umc_cas_cmd.all memory controller event=0xa 01 Number of CAS commands sent umc_cas_cmd.rd memory controller event=0xa,rdwrmask=1 01 Number of CAS commands sent for reads umc_cas_cmd.wr memory controller event=0xa,rdwrmask=2 01 Number of CAS commands sent for writes umc_data_slot_clks.all memory controller event=0x14 01 Number of clocks used by the data bus umc_data_slot_clks.rd memory controller event=0x14,rdwrmask=1 01 Number of clocks used by the data bus for reads umc_data_slot_clks.wr memory controller event=0x14,rdwrmask=2 01 Number of clocks used by the data bus for writes ls_bad_status2.stli_other memory Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store) event=0x24,umask=2 00 ls_dispatch.ld_dispatch memory Number of memory load operations dispatched to the load-store unit event=0x29,umask=1 00 ls_dispatch.store_dispatch memory Number of memory store operations dispatched to the load-store unit event=0x29,umask=2 00 ls_dispatch.ld_st_dispatch memory Number of memory load-store operations dispatched to the load-store unit event=0x29,umask=4 00 ls_stlf memory Store-to-load-forward (STLF) hits event=0x35 00 ls_st_commit_cancel2.st_commit_cancel_wcb_full memory Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full event=0x37,umask=1 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit memory L1 DTLB misses with L2 DTLB hits for 4k pages event=0x45,umask=1 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit memory L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x45,umask=2 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit memory L1 DTLB misses with L2 DTLB hits for 2M pages event=0x45,umask=4 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit memory L1 DTLB misses with L2 DTLB hits for 1G pages event=0x45,umask=8 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages event=0x45,umask=0x10 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x45,umask=0x20 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages event=0x45,umask=0x40 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages event=0x45,umask=0x80 00 ls_l1_d_tlb_miss.all_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes event=0x45,umask=0xf0 00 ls_l1_d_tlb_miss.all memory L1 DTLB misses for all page sizes event=0x45,umask=0xff 00 ls_misal_loads.ma64 memory 64B misaligned (cacheline crossing) loads event=0x47,umask=1 00 ls_misal_loads.ma4k memory 4kB misaligned (page crossing) loads event=0x47,umask=2 00 ls_tlb_flush.all memory All TLB Flushes event=0x78,umask=0xff 00 bp_l1_tlb_miss_l2_tlb_hit memory Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84 00 bp_l1_tlb_miss_l2_tlb_miss.if4k memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages event=0x85,umask=1 00 bp_l1_tlb_miss_l2_tlb_miss.if2m memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages event=0x85,umask=2 00 bp_l1_tlb_miss_l2_tlb_miss.if1g memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages event=0x85,umask=4 00 bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x85,umask=8 00 bp_l1_tlb_miss_l2_tlb_miss.all memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes event=0x85,umask=0xf 00 bp_l1_tlb_fetch_hit.if4k memory Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x94,umask=1 00 bp_l1_tlb_fetch_hit.if2m memory Instruction fetches that hit in the L1 ITLB for 2M pages event=0x94,umask=2 00 bp_l1_tlb_fetch_hit.if1g memory Instruction fetches that hit in the L1 ITLB for 1G pages event=0x94,umask=4 00 bp_l1_tlb_fetch_hit.all memory Instruction fetches that hit in the L1 ITLB for all page sizes event=0x94,umask=7 00 resyncs_or_nc_redirects other Pipeline restarts not caused by branch mispredicts event=0x96 00 de_op_queue_empty other Cycles when the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough event=0xa9 00 de_src_op_disp.decoder other Ops fetched from instruction cache and dispatched event=0xaa,umask=1 00 de_src_op_disp.op_cache other Ops fetched from op cache and dispatched event=0xaa,umask=2 00 de_src_op_disp.loop_buffer other Ops dispatched from loop buffer event=0xaa,umask=4 00 de_src_op_disp.all other Ops dispatched from any source event=0xaa,umask=7 00 de_dis_ops_from_decoder.any_fp_dispatch other Number of ops dispatched to the floating-point unit event=0xab,umask=4 00 de_dis_ops_from_decoder.disp_op_type.any_integer_dispatch other Number of ops dispatched to the integer execution unit event=0xab,umask=8 00 de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall other Number of cycles dispatch is stalled for integer physical register file tokens event=0xae,umask=1 00 de_dis_dispatch_token_stalls1.load_queue_rsrc_stall other Number of cycles dispatch is stalled for Load queue token event=0xae,umask=2 00 de_dis_dispatch_token_stalls1.store_queue_rsrc_stall other Number of cycles dispatch is stalled for store queue tokens event=0xae,umask=4 00 de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc other Number of cycles dispatch is stalled for taken branch buffer tokens event=0xae,umask=0x10 00 de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall other Number of cycles dispatch is stalled for floating-point register file tokens event=0xae,umask=0x20 00 de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall other Number of cycles dispatch is stalled for floating-point scheduler tokens event=0xae,umask=0x40 00 de_dis_dispatch_token_stalls1.fp_flush_recovery_stall other Number of cycles dispatch is stalled for floating-point flush recovery event=0xae,umask=0x80 00 de_dis_dispatch_token_stalls2.int_sch0_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 0 tokens event=0xaf,umask=1 00 de_dis_dispatch_token_stalls2.int_sch1_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 1 tokens event=0xaf,umask=2 00 de_dis_dispatch_token_stalls2.int_sch2_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 2 tokens event=0xaf,umask=4 00 de_dis_dispatch_token_stalls2.int_sch3_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 3 tokens event=0xaf,umask=8 00 de_dis_dispatch_token_stalls2.retire_token_stall other Number of cycles dispatch is stalled for retire queue tokens event=0xaf,umask=0x20 00 de_no_dispatch_per_slot.no_ops_from_frontend other In each cycle counts dispatch slots left empty because the front-end did not supply ops event=0x1a0,umask=1 00 de_no_dispatch_per_slot.backend_stalls other In each cycle counts ops unable to dispatch because of back-end stalls event=0x1a0,umask=0x1e 00 de_no_dispatch_per_slot.smt_contention other In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread event=0x1a0,umask=0x60 00 all_data_cache_accesses recommended All data cache accesses event=0x29,umask=7 00 bp_l1_tlb_miss_l2_tlb_hit branch prediction Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84 00 bp_l1_tlb_miss_l2_tlb_miss.if4k branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages event=0x85,umask=1 00 bp_l1_tlb_miss_l2_tlb_miss.if2m branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages event=0x85,umask=2 00 bp_l1_tlb_miss_l2_tlb_miss.if1g branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages event=0x85,umask=4 00 bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x85,umask=8 00 bp_l1_tlb_miss_l2_tlb_miss.all branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes event=0x85,umask=0xf 00 bp_l2_btb_correct branch prediction L2 branch prediction overrides existing prediction (speculative) event=0x8b 00 bp_dyn_ind_pred branch prediction Dynamic indirect predictions (branch used the indirect predictor to make a prediction) event=0x8e 00 bp_de_redirect branch prediction Number of times an early redirect is sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected event=0x91 00 bp_l1_tlb_fetch_hit.if4k branch prediction Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x94,umask=1 00 bp_l1_tlb_fetch_hit.if2m branch prediction Instruction fetches that hit in the L1 ITLB for 2M pages event=0x94,umask=2 00 bp_l1_tlb_fetch_hit.if1g branch prediction Instruction fetches that hit in the L1 ITLB for 1G pages event=0x94,umask=4 00 bp_l1_tlb_fetch_hit.all branch prediction Instruction fetches that hit in the L1 ITLB for all page sizes event=0x94,umask=7 00 bp_redirects.resync branch prediction Redirects of the branch predictor caused by resyncs event=0x9f,umask=1 00 bp_redirects.ex_redir branch prediction Redirects of the branch predictor caused by mispredicts event=0x9f,umask=2 00 bp_redirects.all branch prediction Redirects of the branch predictor event=0x9f 00 de_op_queue_empty decode Cycles where the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough event=0xa9 00 de_src_op_disp.x86_decoder decode Ops dispatched from x86 decoder event=0xaa,umask=1 00 de_src_op_disp.op_cache decode Ops dispatched from op cache event=0xaa,umask=2 00 de_src_op_disp.all decode Ops dispatched from any source event=0xaa,umask=7 00 de_dis_ops_from_decoder.any_fp_dispatch decode Number of ops dispatched to the floating-point unit event=0xab,umask=4 00 de_dis_ops_from_decoder.any_integer_dispatch decode Number of ops dispatched to the integer execution unit event=0xab,umask=8 00 de_dispatch_stall_cycle_dynamic_tokens_part1.int_phy_reg_file_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to an integer physical register file resource stall event=0xae,umask=1 00 de_dispatch_stall_cycle_dynamic_tokens_part1.load_queue_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to a lack of load queue tokens event=0xae,umask=2 00 de_dispatch_stall_cycle_dynamic_tokens_part1.store_queue_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to a lack of store queue tokens event=0xae,umask=4 00 de_dispatch_stall_cycle_dynamic_tokens_part1.taken_brnch_buffer_rsrc decode Cycles where a dispatch group is valid but does not get dispatched due to a taken branch buffer resource stall event=0xae,umask=0x10 00 de_dispatch_stall_cycle_dynamic_tokens_part1.fp_sch_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to a floating-point non-schedulable queue token stall event=0xae,umask=0x40 00 de_dispatch_stall_cycle_dynamic_tokens_part2.al_tokens decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of ALU tokens event=0xaf,umask=1 00 de_dispatch_stall_cycle_dynamic_tokens_part2.ag_tokens decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of agen tokens event=0xaf,umask=2 00 de_dispatch_stall_cycle_dynamic_tokens_part2.ex_flush_recovery decode Cycles where a dispatch group is valid but does not get dispatched due to a pending integer execution flush recovery event=0xaf,umask=4 00 de_dispatch_stall_cycle_dynamic_tokens_part2.retq decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of retire queue tokens event=0xaf,umask=0x20 00 de_no_dispatch_per_slot.no_ops_from_frontend decode In each cycle counts dispatch slots left empty because the front-end did not supply ops event=0x1a0,umask=1 00 de_no_dispatch_per_slot.backend_stalls decode In each cycle counts ops unable to dispatch because of back-end stalls event=0x1a0,umask=0x1e 00 de_no_dispatch_per_slot.smt_contention decode In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread event=0x1a0,umask=0x60 00 de_additional_resource_stalls.dispatch_stalls decode Counts additional cycles where dispatch is stalled due to a lack of dispatch resources event=0x1a2,umask=0x30 00 ex_ret_instr execution Retired instructions event=0xc0 00 ex_ret_ops execution Retired macro-ops event=0xc1 00 ex_ret_brn execution Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts) event=0xc2 00 ex_ret_brn_misp execution Retired branch instructions mispredicted event=0xc3 00 ex_ret_brn_tkn execution Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts) event=0xc4 00 ex_ret_brn_tkn_misp execution Retired taken branch instructions mispredicted event=0xc5 00 ex_ret_brn_far execution Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction event=0xc6 00 ex_ret_near_ret execution Retired near returns (RET or RET Iw) event=0xc8 00 ex_ret_near_ret_mispred execution Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction event=0xc9 00 ex_ret_brn_ind_misp execution Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction event=0xca 00 ex_ret_mmx_fp_instr.x87 execution Retired x87 instructions event=0xcb,umask=1 00 ex_ret_mmx_fp_instr.mmx execution Retired MMX instructions event=0xcb,umask=2 00 ex_ret_mmx_fp_instr.sse execution Retired SSE instructions (includes SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42 and AVX) event=0xcb,umask=4 00 ex_ret_ind_brch_instr execution Retired indirect branch instructions event=0xcc 00 ex_ret_cond execution Retired conditional branch instructions event=0xd1 00 ex_div_busy execution Number of cycles the divider is busy event=0xd3 00 ex_div_count execution Divide ops executed event=0xd4 00 ex_no_retire.empty execution Cycles with no retire due to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects) event=0xd6,umask=1 00 ex_no_retire.not_complete execution Cycles with no retire while the oldest op is waiting to be executed event=0xd6,umask=2 00 ex_no_retire.other execution Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.) event=0xd6,umask=8 00 ex_no_retire.thread_not_selected execution Cycles with no retire because thread arbitration did not select the thread event=0xd6,umask=0x10 00 ex_no_retire.load_not_complete execution Cycles with no retire while the oldest op is waiting for load data event=0xd6,umask=0xa2 00 ex_no_retire.all execution Cycles with no retire for any reason event=0xd6,umask=0x1b 00 ex_ret_ucode_instr execution Retired microcoded instructions event=0x1c1 00 ex_ret_ucode_ops execution Retired microcode ops event=0x1c2 00 ex_ret_msprd_brnch_instr_dir_msmtch execution Retired branch instructions mispredicted due to direction mismatch event=0x1c7 00 ex_ret_uncond_brnch_instr_mispred execution Retired unconditional indirect branch instructions mispredicted event=0x1c8 00 ex_ret_uncond_brnch_instr execution Retired unconditional branch instructions event=0x1c9 00 ex_tagged_ibs_ops.ibs_tagged_ops execution Ops tagged by IBS event=0x1cf,umask=1 00 ex_tagged_ibs_ops.ibs_tagged_ops_ret execution Ops tagged by IBS that retired event=0x1cf,umask=2 00 ex_tagged_ibs_ops.ibs_count_rollover execution Ops not tagged by IBS due to a previous tagged op that has not yet signaled interrupt event=0x1cf,umask=4 00 ex_ret_fused_instr execution Retired fused instructions event=0x1d0 00 fp_ret_sse_avx_ops.bfloat16_flops floating point Retired SSE and AVX floating-point bfloat16 ops event=3,umask=0x20 00 fp_ret_sse_avx_ops.scalar_single_flops floating point Retired SSE and AVX floating-point scalar single-precision ops event=3,umask=0x40 00 fp_ret_sse_avx_ops.packed_single_flops floating point Retired SSE and AVX floating-point packed single-precision ops event=3,umask=0x60 00 fp_ret_sse_avx_ops.scalar_double_flops floating point Retired SSE and AVX floating-point scalar double-precision ops event=3,umask=0x80 00 fp_ret_sse_avx_ops.packed_double_flops floating point Retired SSE and AVX floating-point packed double-precision ops event=3,umask=0xa0 00 fp_ret_sse_avx_ops.all floating point Retired SSE and AVX floating-point ops of all types event=3,umask=0xf 00 ic_cache_fill_l2 inst cache Instruction cache lines (64 bytes) fulfilled from the L2 cache event=0x82 00 ic_cache_fill_sys inst cache Instruction cache lines (64 bytes) fulfilled from system memory or another cache event=0x83 00 ic_fetch_ibs_events.fetch_tagged inst cache Fetches tagged by Fetch IBS. Not all tagged fetches result in a valid sample and an IBS interrupt event=0x188,umask=2 00 ic_fetch_ibs_events.sample_discarded inst cache Fetches discarded after being tagged by Fetch IBS due to reasons other than IBS filtering event=0x188,umask=4 00 ic_fetch_ibs_events.sample_filtered inst cache Fetches discarded after being tagged by Fetch IBS due to IBS filtering event=0x188,umask=8 00 ic_fetch_ibs_events.sample_valid inst cache Fetches tagged by Fetch IBS that result in a valid sample and an IBS interrupt event=0x188,umask=0x10 00 ic_tag_hit_miss.instruction_cache_hit inst cache Instruction cache hits event=0x18e,umask=7 00 ic_tag_hit_miss.instruction_cache_miss inst cache Instruction cache misses event=0x18e,umask=0x18 00 ic_tag_hit_miss.all_instruction_cache_accesses inst cache Instruction cache accesses of all types event=0x18e,umask=0x1f 00 op_cache_hit_miss.op_cache_hit inst cache Op cache hits event=0x28f,umask=3 00 op_cache_hit_miss.op_cache_miss inst cache Op cache misses event=0x28f,umask=4 00 op_cache_hit_miss.all_op_cache_accesses inst cache Op cache accesses of all types event=0x28f,umask=7 00 l2_request_g1.group2 l2 cache L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks) event=0x60,umask=1 00 l2_request_g1.l2_hw_pf l2 cache L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss) event=0x60,umask=2 00 l2_request_g1.prefetch_l2_cmd l2 cache L2 cache requests: prefetch directly into L2 event=0x60,umask=4 00 l2_request_g1.cacheable_ic_read l2 cache L2 cache requests: instruction cache reads event=0x60,umask=0x10 00 l2_request_g1.ls_rd_blk_c_s l2 cache L2 cache requests: data cache shared reads event=0x60,umask=0x20 00 l2_request_g1.rd_blk_x l2 cache L2 cache requests: data cache stores event=0x60,umask=0x40 00 l2_request_g1.rd_blk_l l2 cache L2 cache requests: data cache reads including hardware and software prefetch event=0x60,umask=0x80 00 l2_request_g1.all_dc l2 cache L2 cache requests of common types from L1 data cache (including prefetches) event=0x60,umask=0xe0 00 l2_request_g1.all_no_prefetch l2 cache L2 cache requests of common types not including prefetches event=0x60,umask=0xf1 00 l2_request_g1.all l2 cache L2 cache requests of all types event=0x60,umask=0xf7 00 l2_request_g2.ls_rd_sized_nc l2 cache L2 cache requests: non-coherent, non-cacheable LS sized reads event=0x61,umask=0x20 00 l2_request_g2.ls_rd_sized l2 cache L2 cache requests: coherent, non-cacheable LS sized reads event=0x61,umask=0x40 00 l2_wcb_req.wcb_close l2 cache Write Combining Buffer (WCB) closures event=0x63,umask=0x20 00 l2_cache_req_stat.ic_fill_miss l2 cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2 event=0x64,umask=1 00 l2_cache_req_stat.ic_fill_hit_s l2 cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2 event=0x64,umask=2 00 l2_cache_req_stat.ic_fill_hit_x l2 cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2 event=0x64,umask=4 00 l2_cache_req_stat.ic_hit_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for instruction cache hits event=0x64,umask=6 00 l2_cache_req_stat.ic_access_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for instruction cache access event=0x64,umask=7 00 l2_cache_req_stat.ls_rd_blk_c l2 cache Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2 event=0x64,umask=8 00 l2_cache_req_stat.ic_dc_miss_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses event=0x64,umask=9 00 l2_cache_req_stat.ls_rd_blk_x l2 cache Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2 event=0x64,umask=0x10 00 l2_cache_req_stat.ls_rd_blk_l_hit_s l2 cache Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2 event=0x64,umask=0x20 00 l2_cache_req_stat.ls_rd_blk_l_hit_x l2 cache Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2 event=0x64,umask=0x40 00 l2_cache_req_stat.ls_rd_blk_cs l2 cache Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2 event=0x64,umask=0x80 00 l2_cache_req_stat.dc_hit_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for data cache hits event=0x64,umask=0xf0 00 l2_cache_req_stat.ic_dc_hit_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits event=0x64,umask=0xf6 00 l2_cache_req_stat.dc_access_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for data cache access event=0x64,umask=0xf8 00 l2_cache_req_stat.all l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access event=0x64,umask=0xff 00 l2_pf_hit_l2.l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L2 hardware prefetchers event=0x70,umask=0x1f 00 l2_pf_hit_l2.l1_dc_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data hardware prefetchers event=0x70,umask=0xe0 00 l2_pf_hit_l2.l1_dc_l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data and L2 hardware prefetchers event=0x70,umask=0xff 00 l2_pf_miss_l2_hit_l3.l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L2 hardware prefetchers event=0x71,umask=0x1f 00 l2_pf_miss_l2_hit_l3.l1_dc_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data hardware prefetchers event=0x71,umask=0xe0 00 l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data and L2 hardware prefetchers event=0x71,umask=0xff 00 l2_pf_miss_l2_l3.l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L2 hardware prefetchers event=0x72,umask=0x1f 00 l2_pf_miss_l2_l3.l1_dc_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data hardware prefetchers event=0x72,umask=0xe0 00 l2_pf_miss_l2_l3.l1_dc_l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data and L2 hardware prefetchers event=0x72,umask=0xff 00 l2_fill_rsp_src.local_ccx l2 cache L2 cache fills from L3 cache or different L2 cache in the same CCX event=0x165,umask=2 00 l2_fill_rsp_src.near_cache l2 cache L2 cache fills from cache of another CCX when the address was in the same NUMA node event=0x165,umask=4 00 l2_fill_rsp_src.dram_io_near l2 cache L2 cache fills from either DRAM or MMIO in the same NUMA node event=0x165,umask=8 00 l2_fill_rsp_src.far_cache l2 cache L2 cache fills from cache of another CCX when the address was in a different NUMA node event=0x165,umask=0x10 00 l2_fill_rsp_src.dram_io_far l2 cache L2 cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x165,umask=0x40 00 l2_fill_rsp_src.alternate_memories l2 cache L2 cache fills from extension memory event=0x165,umask=0x80 00 l2_fill_rsp_src.all l2 cache L2 cache fills from all types of data sources event=0x165,umask=0xde 00 l3_lookup_state.l3_miss l3 cache L3 cache misses event=4,umask=1 00 l3_lookup_state.l3_hit l3 cache L3 cache hits event=4,umask=0xfe 00 l3_lookup_state.all_coherent_accesses_to_l3 l3 cache L3 cache requests for all coherent accesses event=4,umask=0xff 00 l3_xi_sampled_latency.dram_near l3 cache Average sampled latency when data is sourced from DRAM in the same NUMA node event=0xac,umask=1,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.dram_far l3 cache Average sampled latency when data is sourced from DRAM in a different NUMA node event=0xac,umask=2,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.near_cache l3 cache Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node event=0xac,umask=4,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.far_cache l3 cache Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node event=0xac,umask=8,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.ext_near l3 cache Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node event=0xac,umask=0x10,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.ext_far l3 cache Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node event=0xac,umask=0x20,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency.all l3 cache Average sampled latency from all data sources event=0xac,umask=0x3f,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.dram_near l3 cache L3 cache fill requests sourced from DRAM in the same NUMA node event=0xad,umask=1,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.dram_far l3 cache L3 cache fill requests sourced from DRAM in a different NUMA node event=0xad,umask=2,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.near_cache l3 cache L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node event=0xad,umask=4,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.far_cache l3 cache L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node event=0xad,umask=8,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.ext_near l3 cache L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node event=0xad,umask=0x10,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.ext_far l3 cache L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node event=0xad,umask=0x20,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 l3_xi_sampled_latency_requests.all l3 cache L3 cache fill requests sourced from all data sources event=0xad,umask=0x3f,enallcores=1,enallslices=1,sliceid=3,threadmask=3 00 ls_bad_status2.stli_other load store Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store) event=0x24,umask=2 00 ls_locks.bus_lock load store Retired Lock instructions which caused a bus lock event=0x25,umask=1 00 ls_ret_cl_flush load store Retired CLFLUSH instructions event=0x26 00 ls_ret_cpuid load store Retired CPUID instructions event=0x27 00 ls_dispatch.ld_dispatch load store Number of memory load operations dispatched to the load-store unit event=0x29,umask=1 00 ls_dispatch.store_dispatch load store Number of memory store operations dispatched to the load-store unit event=0x29,umask=2 00 ls_dispatch.ld_st_dispatch load store Number of memory load-store operations dispatched to the load-store unit event=0x29,umask=4 00 ls_dispatch.all load store Number of memory operations dispatched to the load-store unit event=0x29,umask=7 00 ls_smi_rx load store SMIs received event=0x2b 00 ls_int_taken load store Interrupts taken event=0x2c 00 ls_stlf load store Store-to-load-forward (STLF) hits event=0x35 00 ls_st_commit_cancel2.st_commit_cancel_wcb_full load store Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full event=0x37,umask=1 00 ls_mab_alloc.load_store_allocations load store Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations event=0x41,umask=0x3f 00 ls_mab_alloc.hardware_prefetcher_allocations load store Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations event=0x41,umask=0x40 00 ls_mab_alloc.all_allocations load store Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations event=0x41,umask=0x7f 00 ls_dmnd_fills_from_sys.local_l2 load store Demand data cache fills from local L2 cache event=0x43,umask=1 00 ls_dmnd_fills_from_sys.local_ccx load store Demand data cache fills from L3 cache or different L2 cache in the same CCX event=0x43,umask=2 00 ls_dmnd_fills_from_sys.near_cache load store Demand data cache fills from cache of another CCX when the address was in the same NUMA node event=0x43,umask=4 00 ls_dmnd_fills_from_sys.dram_io_near load store Demand data cache fills from either DRAM or MMIO in the same NUMA node event=0x43,umask=8 00 ls_dmnd_fills_from_sys.far_cache load store Demand data cache fills from cache of another CCX when the address was in a different NUMA node event=0x43,umask=0x10 00 ls_dmnd_fills_from_sys.dram_io_far load store Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x43,umask=0x40 00 ls_dmnd_fills_from_sys.alternate_memories load store Demand data cache fills from extension memory event=0x43,umask=0x80 00 ls_dmnd_fills_from_sys.all load store Demand data cache fills from all types of data sources event=0x43,umask=0xff 00 ls_any_fills_from_sys.local_l2 load store Any data cache fills from local L2 cache event=0x44,umask=1 00 ls_any_fills_from_sys.local_ccx load store Any data cache fills from L3 cache or different L2 cache in the same CCX event=0x44,umask=2 00 ls_any_fills_from_sys.local_all load store Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX event=0x44,umask=3 00 ls_any_fills_from_sys.near_cache load store Any data cache fills from cache of another CCX when the address was in the same NUMA node event=0x44,umask=4 00 ls_any_fills_from_sys.dram_io_near load store Any data cache fills from either DRAM or MMIO in the same NUMA node event=0x44,umask=8 00 ls_any_fills_from_sys.far_cache load store Any data cache fills from cache of another CCX when the address was in a different NUMA node event=0x44,umask=0x10 00 ls_any_fills_from_sys.remote_cache load store Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node event=0x44,umask=0x14 00 ls_any_fills_from_sys.dram_io_far load store Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x44,umask=0x40 00 ls_any_fills_from_sys.dram_io_all load store Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket) event=0x44,umask=0x48 00 ls_any_fills_from_sys.far_all load store Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket) event=0x44,umask=0x50 00 ls_any_fills_from_sys.all_dram_io load store Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket) event=0x44,umask=0x48 00 ls_any_fills_from_sys.alternate_memories load store Any data cache fills from extension memory event=0x44,umask=0x80 00 ls_any_fills_from_sys.all load store Any data cache fills from all types of data sources event=0x44,umask=0xff 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit load store L1 DTLB misses with L2 DTLB hits for 4k pages event=0x45,umask=1 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit load store L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x45,umask=2 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit load store L1 DTLB misses with L2 DTLB hits for 2M pages event=0x45,umask=4 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit load store L1 DTLB misses with L2 DTLB hits for 1G pages event=0x45,umask=8 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages event=0x45,umask=0x10 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x45,umask=0x20 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages event=0x45,umask=0x40 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages event=0x45,umask=0x80 00 ls_l1_d_tlb_miss.all_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes event=0x45,umask=0xf0 00 ls_l1_d_tlb_miss.all load store L1 DTLB misses for all page sizes event=0x45,umask=0xff 00 ls_misal_loads.ma64 load store 64B misaligned (cacheline crossing) loads event=0x47,umask=1 00 ls_misal_loads.ma4k load store 4kB misaligned (page crossing) loads event=0x47,umask=2 00 ls_pref_instr_disp.prefetch load store Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2) event=0x4b,umask=1 00 ls_pref_instr_disp.prefetch_w load store Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable) event=0x4b,umask=2 00 ls_pref_instr_disp.prefetch_nta load store Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access) event=0x4b,umask=4 00 ls_pref_instr_disp.all load store Software prefetch instructions dispatched (speculative) of all types event=0x4b,umask=7 00 wcb_close.full_line_64b load store Number of events that caused a Write Combining Buffer (WCB) entry to close because all 64 bytes of the entry have been written to event=0x50,umask=1 00 ls_inef_sw_pref.data_pipe_sw_pf_dc_hit load store Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit event=0x52,umask=1 00 ls_inef_sw_pref.mab_mch_cnt load store Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB) event=0x52,umask=2 00 ls_inef_sw_pref.all load store event=0x52,umask=3 00 ls_sw_pf_dc_fills.local_l2 load store Software prefetch data cache fills from local L2 cache event=0x59,umask=1 00 ls_sw_pf_dc_fills.local_ccx load store Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX event=0x59,umask=2 00 ls_sw_pf_dc_fills.near_cache load store Software prefetch data cache fills from cache of another CCX in the same NUMA node event=0x59,umask=4 00 ls_sw_pf_dc_fills.dram_io_near load store Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node event=0x59,umask=8 00 ls_sw_pf_dc_fills.far_cache load store Software prefetch data cache fills from cache of another CCX in a different NUMA node event=0x59,umask=0x10 00 ls_sw_pf_dc_fills.dram_io_far load store Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x59,umask=0x40 00 ls_sw_pf_dc_fills.alternate_memories load store Software prefetch data cache fills from extension memory event=0x59,umask=0x80 00 ls_sw_pf_dc_fills.all load store Software prefetch data cache fills from all types of data sources event=0x59,umask=0xdf 00 ls_hw_pf_dc_fills.local_l2 load store Hardware prefetch data cache fills from local L2 cache event=0x5a,umask=1 00 ls_hw_pf_dc_fills.local_ccx load store Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX event=0x5a,umask=2 00 ls_hw_pf_dc_fills.near_cache load store Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node event=0x5a,umask=4 00 ls_hw_pf_dc_fills.dram_io_near load store Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node event=0x5a,umask=8 00 ls_hw_pf_dc_fills.far_cache load store Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node event=0x5a,umask=0x10 00 ls_hw_pf_dc_fills.dram_io_far load store Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x5a,umask=0x40 00 ls_hw_pf_dc_fills.alternate_memories load store Hardware prefetch data cache fills from extension memory event=0x5a,umask=0x80 00 ls_hw_pf_dc_fills.all load store Hardware prefetch data cache fills from all types of data sources event=0x5a,umask=0xdf 00 ls_alloc_mab_count load store In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle event=0x5f 00 ls_not_halted_cyc load store Core cycles not in halt event=0x76 00 ls_tlb_flush.all load store All TLB Flushes event=0x78,umask=0xff 00 ls_not_halted_p0_cyc.p0_freq_cyc load store Reference cycles (P0 frequency) not in halt event=0x120,umask=1 00 umc_mem_clk memory controller event=0 01 Number of memory clock (MEMCLK) cycles umc_data_slot_clks.all memory controller event=0x14 01 Number of clock cycles used by the data bus umc_data_slot_clks.rd memory controller event=0x14,rdwrmask=1 01 Number of clock cycles used by the data bus for reads umc_data_slot_clks.wr memory controller event=0x14,rdwrmask=2 01 Number of clock cycles used by the data bus for writes l1d_cache.all_cache_ref cache L1 Data Cacheable reads and writes event=0x40,period=2000000,umask=0xa3 00 l1d_cache.all_ref cache L1 Data reads and writes event=0x40,period=2000000,umask=0x83 00 l1d_cache.evict cache Modified cache lines evicted from the L1 data cache event=0x40,period=200000,umask=0x10 00 l1d_cache.ld cache L1 Cacheable Data Reads event=0x40,period=2000000,umask=0xa1 00 l1d_cache.repl cache L1 Data line replacements event=0x40,period=200000,umask=8 00 l1d_cache.replm cache Modified cache lines allocated in the L1 data cache event=0x40,period=200000,umask=0x48 00 l1d_cache.st cache L1 Cacheable Data Writes event=0x40,period=2000000,umask=0xa2 00 l2_ads.self cache Cycles L2 address bus is in use event=0x21,period=200000,umask=0x40 00 l2_data_rqsts.self.e_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x44 00 l2_data_rqsts.self.i_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x41 00 l2_data_rqsts.self.mesi cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x4f 00 l2_data_rqsts.self.m_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x48 00 l2_data_rqsts.self.s_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x42 00 l2_dbus_busy.self cache Cycles the L2 cache data bus is busy event=0x22,period=200000,umask=0x40 00 l2_dbus_busy_rd.self cache Cycles the L2 transfers data to the core event=0x23,period=200000,umask=0x40 00 l2_ifetch.self.e_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x44 00 l2_ifetch.self.i_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x41 00 l2_ifetch.self.mesi cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x4f 00 l2_ifetch.self.m_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x48 00 l2_ifetch.self.s_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x42 00 l2_ld.self.any.e_state cache L2 cache reads event=0x29,period=200000,umask=0x74 00 l2_ld.self.any.i_state cache L2 cache reads event=0x29,period=200000,umask=0x71 00 l2_ld.self.any.mesi cache L2 cache reads event=0x29,period=200000,umask=0x7f 00 l2_ld.self.any.m_state cache L2 cache reads event=0x29,period=200000,umask=0x78 00 l2_ld.self.any.s_state cache L2 cache reads event=0x29,period=200000,umask=0x72 00 l2_ld.self.demand.e_state cache L2 cache reads event=0x29,period=200000,umask=0x44 00 l2_ld.self.demand.i_state cache L2 cache reads event=0x29,period=200000,umask=0x41 00 l2_ld.self.demand.mesi cache L2 cache reads event=0x29,period=200000,umask=0x4f 00 l2_ld.self.demand.m_state cache L2 cache reads event=0x29,period=200000,umask=0x48 00 l2_ld.self.demand.s_state cache L2 cache reads event=0x29,period=200000,umask=0x42 00 l2_ld.self.prefetch.e_state cache L2 cache reads event=0x29,period=200000,umask=0x54 00 l2_ld.self.prefetch.i_state cache L2 cache reads event=0x29,period=200000,umask=0x51 00 l2_ld.self.prefetch.mesi cache L2 cache reads event=0x29,period=200000,umask=0x5f 00 l2_ld.self.prefetch.m_state cache L2 cache reads event=0x29,period=200000,umask=0x58 00 l2_ld.self.prefetch.s_state cache L2 cache reads event=0x29,period=200000,umask=0x52 00 l2_ld_ifetch.self.e_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x44 00 l2_ld_ifetch.self.i_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x41 00 l2_ld_ifetch.self.mesi cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x4f 00 l2_ld_ifetch.self.m_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x48 00 l2_ld_ifetch.self.s_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x42 00 l2_lines_in.self.any cache L2 cache misses event=0x24,period=200000,umask=0x70 00 l2_lines_in.self.demand cache L2 cache misses event=0x24,period=200000,umask=0x40 00 l2_lines_in.self.prefetch cache L2 cache misses event=0x24,period=200000,umask=0x50 00 l2_lines_out.self.any cache L2 cache lines evicted event=0x26,period=200000,umask=0x70 00 l2_lines_out.self.demand cache L2 cache lines evicted event=0x26,period=200000,umask=0x40 00 l2_lines_out.self.prefetch cache L2 cache lines evicted event=0x26,period=200000,umask=0x50 00 l2_lock.self.e_state cache L2 locked accesses event=0x2b,period=200000,umask=0x44 00 l2_lock.self.i_state cache L2 locked accesses event=0x2b,period=200000,umask=0x41 00 l2_lock.self.mesi cache L2 locked accesses event=0x2b,period=200000,umask=0x4f 00 l2_lock.self.m_state cache L2 locked accesses event=0x2b,period=200000,umask=0x48 00 l2_lock.self.s_state cache L2 locked accesses event=0x2b,period=200000,umask=0x42 00 l2_m_lines_in.self cache L2 cache line modifications event=0x25,period=200000,umask=0x40 00 l2_m_lines_out.self.any cache Modified lines evicted from the L2 cache event=0x27,period=200000,umask=0x70 00 l2_m_lines_out.self.demand cache Modified lines evicted from the L2 cache event=0x27,period=200000,umask=0x40 00 l2_m_lines_out.self.prefetch cache Modified lines evicted from the L2 cache event=0x27,period=200000,umask=0x50 00 l2_no_req.self cache Cycles no L2 cache requests are pending event=0x32,period=200000,umask=0x40 00 l2_reject_busq.self.any.e_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x74 00 l2_reject_busq.self.any.i_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x71 00 l2_reject_busq.self.any.mesi cache Rejected L2 cache requests event=0x30,period=200000,umask=0x7f 00 l2_reject_busq.self.any.m_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x78 00 l2_reject_busq.self.any.s_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x72 00 l2_reject_busq.self.demand.e_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x44 00 l2_reject_busq.self.demand.i_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x41 00 l2_reject_busq.self.demand.mesi cache Rejected L2 cache requests event=0x30,period=200000,umask=0x4f 00 l2_reject_busq.self.demand.m_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x48 00 l2_reject_busq.self.demand.s_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x42 00 l2_reject_busq.self.prefetch.e_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x54 00 l2_reject_busq.self.prefetch.i_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x51 00 l2_reject_busq.self.prefetch.mesi cache Rejected L2 cache requests event=0x30,period=200000,umask=0x5f 00 l2_reject_busq.self.prefetch.m_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x58 00 l2_reject_busq.self.prefetch.s_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x52 00 l2_rqsts.self.any.e_state cache L2 cache requests event=0x2e,period=200000,umask=0x74 00 l2_rqsts.self.any.i_state cache L2 cache requests event=0x2e,period=200000,umask=0x71 00 l2_rqsts.self.any.mesi cache L2 cache requests event=0x2e,period=200000,umask=0x7f 00 l2_rqsts.self.any.m_state cache L2 cache requests event=0x2e,period=200000,umask=0x78 00 l2_rqsts.self.any.s_state cache L2 cache requests event=0x2e,period=200000,umask=0x72 00 l2_rqsts.self.demand.e_state cache L2 cache requests event=0x2e,period=200000,umask=0x44 00 l2_rqsts.self.demand.i_state cache L2 cache demand requests from this core that missed the L2 event=0x2e,period=200000,umask=0x41 00 l2_rqsts.self.demand.mesi cache L2 cache demand requests from this core event=0x2e,period=200000,umask=0x4f 00 l2_rqsts.self.demand.m_state cache L2 cache requests event=0x2e,period=200000,umask=0x48 00 l2_rqsts.self.demand.s_state cache L2 cache requests event=0x2e,period=200000,umask=0x42 00 l2_rqsts.self.prefetch.e_state cache L2 cache requests event=0x2e,period=200000,umask=0x54 00 l2_rqsts.self.prefetch.i_state cache L2 cache requests event=0x2e,period=200000,umask=0x51 00 l2_rqsts.self.prefetch.mesi cache L2 cache requests event=0x2e,period=200000,umask=0x5f 00 l2_rqsts.self.prefetch.m_state cache L2 cache requests event=0x2e,period=200000,umask=0x58 00 l2_rqsts.self.prefetch.s_state cache L2 cache requests event=0x2e,period=200000,umask=0x52 00 l2_st.self.e_state cache L2 store requests event=0x2a,period=200000,umask=0x44 00 l2_st.self.i_state cache L2 store requests event=0x2a,period=200000,umask=0x41 00 l2_st.self.mesi cache L2 store requests event=0x2a,period=200000,umask=0x4f 00 l2_st.self.m_state cache L2 store requests event=0x2a,period=200000,umask=0x48 00 l2_st.self.s_state cache L2 store requests event=0x2a,period=200000,umask=0x42 00 mem_load_retired.l2_hit cache Retired loads that hit the L2 cache (precise event) event=0xcb,period=200000,umask=1 00 mem_load_retired.l2_miss cache Retired loads that miss the L2 cache event=0xcb,period=10000,umask=2 00 fp_assist.ar floating point Floating point assists for retired operations event=0x11,period=10000,umask=0x81 00 fp_assist.s floating point Floating point assists event=0x11,period=10000,umask=1 00 simd_assist floating point SIMD assists invoked event=0xcd,period=100000 00 simd_comp_inst_retired.packed_single floating point Retired computational Streaming SIMD Extensions (SSE) packed-single instructions event=0xca,period=2000000,umask=1 00 simd_comp_inst_retired.scalar_double floating point Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions event=0xca,period=2000000,umask=8 00 simd_comp_inst_retired.scalar_single floating point Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions event=0xca,period=2000000,umask=2 00 simd_instr_retired floating point SIMD Instructions retired event=0xce,period=2000000 00 simd_inst_retired.packed_single floating point Retired Streaming SIMD Extensions (SSE) packed-single instructions event=0xc7,period=2000000,umask=1 00 simd_inst_retired.scalar_double floating point Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions event=0xc7,period=2000000,umask=8 00 simd_inst_retired.scalar_single floating point Retired Streaming SIMD Extensions (SSE) scalar-single instructions event=0xc7,period=2000000,umask=2 00 simd_inst_retired.vector floating point Retired Streaming SIMD Extensions 2 (SSE2) vector instructions event=0xc7,period=2000000,umask=0x10 00 simd_sat_instr_retired floating point Saturated arithmetic instructions retired event=0xcf,period=2000000 00 simd_sat_uop_exec.ar floating point SIMD saturated arithmetic micro-ops retired event=0xb1,period=2000000,umask=0x80 00 simd_sat_uop_exec.s floating point SIMD saturated arithmetic micro-ops executed event=0xb1,period=2000000 00 simd_uops_exec.ar floating point SIMD micro-ops retired (excluding stores) (Must be precise) event=0xb0,period=2000000,umask=0x80 00 simd_uops_exec.s floating point SIMD micro-ops executed (excluding stores) event=0xb0,period=2000000 00 simd_uop_type_exec.arithmetic.ar floating point SIMD packed arithmetic micro-ops retired event=0xb3,period=2000000,umask=0xa0 00 simd_uop_type_exec.arithmetic.s floating point SIMD packed arithmetic micro-ops executed event=0xb3,period=2000000,umask=0x20 00 simd_uop_type_exec.logical.ar floating point SIMD packed logical micro-ops retired event=0xb3,period=2000000,umask=0x90 00 simd_uop_type_exec.logical.s floating point SIMD packed logical micro-ops executed event=0xb3,period=2000000,umask=0x10 00 simd_uop_type_exec.mul.ar floating point SIMD packed multiply micro-ops retired event=0xb3,period=2000000,umask=0x81 00 simd_uop_type_exec.mul.s floating point SIMD packed multiply micro-ops executed event=0xb3,period=2000000,umask=1 00 simd_uop_type_exec.pack.ar floating point SIMD packed micro-ops retired event=0xb3,period=2000000,umask=0x84 00 simd_uop_type_exec.pack.s floating point SIMD packed micro-ops executed event=0xb3,period=2000000,umask=4 00 simd_uop_type_exec.shift.ar floating point SIMD packed shift micro-ops retired event=0xb3,period=2000000,umask=0x82 00 simd_uop_type_exec.shift.s floating point SIMD packed shift micro-ops executed event=0xb3,period=2000000,umask=2 00 simd_uop_type_exec.unpack.ar floating point SIMD unpacked micro-ops retired event=0xb3,period=2000000,umask=0x88 00 simd_uop_type_exec.unpack.s floating point SIMD unpacked micro-ops executed event=0xb3,period=2000000,umask=8 00 x87_comp_ops_exe.any.ar floating point Floating point computational micro-ops retired (Must be precise) event=0x10,period=2000000,umask=0x81 00 x87_comp_ops_exe.any.s floating point Floating point computational micro-ops executed event=0x10,period=2000000,umask=1 00 x87_comp_ops_exe.fxch.ar floating point FXCH uops retired (Must be precise) event=0x10,period=2000000,umask=0x82 00 x87_comp_ops_exe.fxch.s floating point FXCH uops executed event=0x10,period=2000000,umask=2 00 baclears.any frontend BACLEARS asserted event=0xe6,period=2000000,umask=1 00 cycles_icache_mem_stalled.icache_mem_stalled frontend Cycles during which instruction fetches are stalled event=0x86,period=2000000,umask=1 00 decode_stall.iq_full frontend Decode stall due to IQ full event=0x87,period=2000000,umask=2 00 decode_stall.pfb_empty frontend Decode stall due to PFB empty event=0x87,period=2000000,umask=1 00 icache.accesses frontend Instruction fetches event=0x80,period=200000,umask=3 00 icache.hit frontend Icache hit event=0x80,period=200000,umask=1 00 icache.misses frontend Icache miss event=0x80,period=200000,umask=2 00 macro_insts.all_decoded frontend All Instructions decoded event=0xaa,period=2000000,umask=3 00 macro_insts.cisc_decoded frontend CISC macro instructions decoded event=0xaa,period=2000000,umask=2 00 macro_insts.non_cisc_decoded frontend Non-CISC macro instructions decoded event=0xaa,period=2000000,umask=1 00 uops.ms_cycles frontend This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ event=0xa9,cmask=1,period=2000000,umask=1 00 misalign_mem_ref.bubble memory Nonzero segbase 1 bubble event=5,period=200000,umask=0x97 00 misalign_mem_ref.ld_bubble memory Nonzero segbase load 1 bubble event=5,period=200000,umask=0x91 00 misalign_mem_ref.ld_split memory Load splits event=5,period=200000,umask=9 00 misalign_mem_ref.ld_split.ar memory Load splits (At Retirement) event=5,period=200000,umask=0x89 00 misalign_mem_ref.rmw_bubble memory Nonzero segbase ld-op-st 1 bubble event=5,period=200000,umask=0x94 00 misalign_mem_ref.rmw_split memory ld-op-st splits event=5,period=200000,umask=0x8c 00 misalign_mem_ref.split memory Memory references that cross an 8-byte boundary event=5,period=200000,umask=0xf 00 misalign_mem_ref.split.ar memory Memory references that cross an 8-byte boundary (At Retirement) event=5,period=200000,umask=0x8f 00 misalign_mem_ref.st_bubble memory Nonzero segbase store 1 bubble event=5,period=200000,umask=0x92 00 misalign_mem_ref.st_split memory Store splits event=5,period=200000,umask=0xa 00 misalign_mem_ref.st_split.ar memory Store splits (Ar Retirement) event=5,period=200000,umask=0x8a 00 prefetch.hw_prefetch memory L1 hardware prefetch request event=7,period=2000000,umask=0x10 00 prefetch.prefetchnta memory Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed event=7,period=200000,umask=0x88 00 prefetch.prefetcht0 memory Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed event=7,period=200000,umask=0x81 00 prefetch.prefetcht1 memory Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed event=7,period=200000,umask=0x82 00 prefetch.prefetcht2 memory Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed event=7,period=200000,umask=0x84 00 prefetch.software_prefetch memory Any Software prefetch event=7,period=200000,umask=0xf 00 prefetch.software_prefetch.ar memory Any Software prefetch event=7,period=200000,umask=0x8f 00 prefetch.sw_l2 memory Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed event=7,period=200000,umask=0x86 00 busq_empty.self other Bus queue is empty event=0x7d,period=200000,umask=0x40 00 bus_bnr_drv.all_agents other Number of Bus Not Ready signals asserted event=0x61,period=200000,umask=0x20 00 bus_bnr_drv.this_agent other Number of Bus Not Ready signals asserted event=0x61,period=200000 00 bus_data_rcv.self other Bus cycles while processor receives data event=0x64,period=200000,umask=0x40 00 bus_drdy_clocks.all_agents other Bus cycles when data is sent on the bus event=0x62,period=200000,umask=0x20 00 bus_drdy_clocks.this_agent other Bus cycles when data is sent on the bus event=0x62,period=200000 00 bus_hitm_drv.all_agents other HITM signal asserted event=0x7b,period=200000,umask=0x20 00 bus_hitm_drv.this_agent other HITM signal asserted event=0x7b,period=200000 00 bus_hit_drv.all_agents other HIT signal asserted event=0x7a,period=200000,umask=0x20 00 bus_hit_drv.this_agent other HIT signal asserted event=0x7a,period=200000 00 bus_io_wait.self other IO requests waiting in the bus queue event=0x7f,period=200000,umask=0x40 00 bus_lock_clocks.all_agents other Bus cycles when a LOCK signal is asserted event=0x63,period=200000,umask=0xe0 00 bus_lock_clocks.self other Bus cycles when a LOCK signal is asserted event=0x63,period=200000,umask=0x40 00 bus_request_outstanding.all_agents other Outstanding cacheable data read bus requests duration event=0x60,period=200000,umask=0xe0 00 bus_request_outstanding.self other Outstanding cacheable data read bus requests duration event=0x60,period=200000,umask=0x40 00 bus_trans_any.all_agents other All bus transactions event=0x70,period=200000,umask=0xe0 00 bus_trans_any.self other All bus transactions event=0x70,period=200000,umask=0x40 00 bus_trans_brd.all_agents other Burst read bus transactions event=0x65,period=200000,umask=0xe0 00 bus_trans_brd.self other Burst read bus transactions event=0x65,period=200000,umask=0x40 00 bus_trans_burst.all_agents other Burst (full cache-line) bus transactions event=0x6e,period=200000,umask=0xe0 00 bus_trans_burst.self other Burst (full cache-line) bus transactions event=0x6e,period=200000,umask=0x40 00 bus_trans_def.all_agents other Deferred bus transactions event=0x6d,period=200000,umask=0xe0 00 bus_trans_def.self other Deferred bus transactions event=0x6d,period=200000,umask=0x40 00 bus_trans_ifetch.all_agents other Instruction-fetch bus transactions event=0x68,period=200000,umask=0xe0 00 bus_trans_ifetch.self other Instruction-fetch bus transactions event=0x68,period=200000,umask=0x40 00 bus_trans_inval.all_agents other Invalidate bus transactions event=0x69,period=200000,umask=0xe0 00 bus_trans_inval.self other Invalidate bus transactions event=0x69,period=200000,umask=0x40 00 bus_trans_io.all_agents other IO bus transactions event=0x6c,period=200000,umask=0xe0 00 bus_trans_io.self other IO bus transactions event=0x6c,period=200000,umask=0x40 00 bus_trans_mem.all_agents other Memory bus transactions event=0x6f,period=200000,umask=0xe0 00 bus_trans_mem.self other Memory bus transactions event=0x6f,period=200000,umask=0x40 00 bus_trans_p.all_agents other Partial bus transactions event=0x6b,period=200000,umask=0xe0 00 bus_trans_p.self other Partial bus transactions event=0x6b,period=200000,umask=0x40 00 bus_trans_pwr.all_agents other Partial write bus transaction event=0x6a,period=200000,umask=0xe0 00 bus_trans_pwr.self other Partial write bus transaction event=0x6a,period=200000,umask=0x40 00 bus_trans_rfo.all_agents other RFO bus transactions event=0x66,period=200000,umask=0xe0 00 bus_trans_rfo.self other RFO bus transactions event=0x66,period=200000,umask=0x40 00 bus_trans_wb.all_agents other Explicit writeback bus transactions event=0x67,period=200000,umask=0xe0 00 bus_trans_wb.self other Explicit writeback bus transactions event=0x67,period=200000,umask=0x40 00 cycles_int_masked.cycles_int_masked other Cycles during which interrupts are disabled event=0xc6,period=2000000,umask=1 00 cycles_int_masked.cycles_int_pending_and_masked other Cycles during which interrupts are pending and disabled event=0xc6,period=2000000,umask=2 00 ext_snoop.all_agents.any other External snoops event=0x77,period=200000,umask=0x2b 00 ext_snoop.all_agents.clean other External snoops event=0x77,period=200000,umask=0x21 00 ext_snoop.all_agents.hit other External snoops event=0x77,period=200000,umask=0x22 00 ext_snoop.all_agents.hitm other External snoops event=0x77,period=200000,umask=0x28 00 ext_snoop.this_agent.any other External snoops event=0x77,period=200000,umask=0xb 00 ext_snoop.this_agent.clean other External snoops event=0x77,period=200000,umask=1 00 ext_snoop.this_agent.hit other External snoops event=0x77,period=200000,umask=2 00 ext_snoop.this_agent.hitm other External snoops event=0x77,period=200000,umask=8 00 hw_int_rcv other Hardware interrupts received event=0xc8,period=200000 00 snoop_stall_drv.all_agents other Bus stalled for snoops event=0x7e,period=200000,umask=0xe0 00 snoop_stall_drv.self other Bus stalled for snoops event=0x7e,period=200000,umask=0x40 00 thermal_trip other Number of thermal trips event=0x3b,period=200000,umask=0xc0 00 bogus_br pipeline Bogus branches event=0xe4,period=2000000,umask=1 00 br_inst_decoded pipeline Branch instructions decoded event=0xe0,period=2000000,umask=1 00 br_inst_retired.any pipeline Retired branch instructions event=0xc4,period=2000000 00 br_inst_retired.any1 pipeline Retired branch instructions event=0xc4,period=2000000,umask=0xf 00 br_inst_retired.mispred pipeline Retired mispredicted branch instructions (precise event) (Precise event) event=0xc5,period=200000 00 br_inst_retired.mispred_not_taken pipeline Retired branch instructions that were mispredicted not-taken event=0xc4,period=200000,umask=2 00 br_inst_retired.mispred_taken pipeline Retired branch instructions that were mispredicted taken event=0xc4,period=200000,umask=8 00 br_inst_retired.pred_not_taken pipeline Retired branch instructions that were predicted not-taken event=0xc4,period=2000000,umask=1 00 br_inst_retired.pred_taken pipeline Retired branch instructions that were predicted taken event=0xc4,period=2000000,umask=4 00 br_inst_retired.taken pipeline Retired taken branch instructions event=0xc4,period=2000000,umask=0xc 00 br_inst_type_retired.cond pipeline All macro conditional branch instructions event=0x88,period=2000000,umask=1 00 br_inst_type_retired.cond_taken pipeline Only taken macro conditional branch instructions event=0x88,period=2000000,umask=0x41 00 br_inst_type_retired.dir_call pipeline All non-indirect calls event=0x88,period=2000000,umask=0x10 00 br_inst_type_retired.ind pipeline All indirect branches that are not calls event=0x88,period=2000000,umask=4 00 br_inst_type_retired.ind_call pipeline All indirect calls, including both register and memory indirect event=0x88,period=2000000,umask=0x20 00 br_inst_type_retired.ret pipeline All indirect branches that have a return mnemonic event=0x88,period=2000000,umask=8 00 br_inst_type_retired.uncond pipeline All macro unconditional branch instructions, excluding calls and indirects event=0x88,period=2000000,umask=2 00 br_missp_type_retired.cond pipeline Mispredicted cond branch instructions retired event=0x89,period=200000,umask=1 00 br_missp_type_retired.cond_taken pipeline Mispredicted and taken cond branch instructions retired event=0x89,period=200000,umask=0x11 00 br_missp_type_retired.ind pipeline Mispredicted ind branches that are not calls event=0x89,period=200000,umask=2 00 br_missp_type_retired.ind_call pipeline Mispredicted indirect calls, including both register and memory indirect event=0x89,period=200000,umask=8 00 br_missp_type_retired.return pipeline Mispredicted return branches event=0x89,period=200000,umask=4 00 cpu_clk_unhalted.bus pipeline Bus cycles when core is not halted event=0x3c,period=200000,umask=1 00 cpu_clk_unhalted.core pipeline Core cycles when core is not halted event=0x3c,period=2000003 00 cpu_clk_unhalted.core_p pipeline Core cycles when core is not halted event=0x3c,period=2000000 00 cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003 00 div.ar pipeline Divide operations retired event=0x13,period=2000000,umask=0x81 00 div.s pipeline Divide operations executed event=0x13,period=2000000,umask=1 00 inst_retired.any pipeline Instructions retired event=0xc0,period=2000003 00 inst_retired.any_p pipeline Instructions retired (precise event) (Must be precise) event=0xc0,period=2000003 00 machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=200000,umask=1 00 mul.ar pipeline Multiply operations retired event=0x12,period=2000000,umask=0x81 00 mul.s pipeline Multiply operations executed event=0x12,period=2000000,umask=1 00 reissue.any pipeline Micro-op reissues for any cause event=3,period=200000,umask=0x7f 00 reissue.any.ar pipeline Micro-op reissues for any cause (At Retirement) event=3,period=200000,umask=0xff 00 reissue.overlap_store pipeline Micro-op reissues on a store-load collision event=3,period=200000,umask=1 00 reissue.overlap_store.ar pipeline Micro-op reissues on a store-load collision (At Retirement) event=3,period=200000,umask=0x81 00 resource_stalls.div_busy pipeline Cycles issue is stalled due to div busy event=0xdc,period=2000000,umask=2 00 store_forwards.any pipeline All store forwards event=2,period=200000,umask=0x83 00 store_forwards.good pipeline Good store forwards event=2,period=200000,umask=0x81 00 uops_retired.any pipeline Micro-ops retired event=0xc2,period=2000000,umask=0x10 00 uops_retired.stalled_cycles pipeline Cycles no micro-ops retired event=0xc2,period=2000000,umask=0x10 00 uops_retired.stalls pipeline Periods no micro-ops retired event=0xc2,period=2000000,umask=0x10 00 data_tlb_misses.dtlb_miss virtual memory Memory accesses that missed the DTLB event=8,period=200000,umask=7 00 data_tlb_misses.dtlb_miss_ld virtual memory DTLB misses due to load operations event=8,period=200000,umask=5 00 data_tlb_misses.dtlb_miss_st virtual memory DTLB misses due to store operations event=8,period=200000,umask=6 00 data_tlb_misses.l0_dtlb_miss_ld virtual memory L0 DTLB misses due to load operations event=8,period=200000,umask=9 00 data_tlb_misses.l0_dtlb_miss_st virtual memory L0 DTLB misses due to store operations event=8,period=200000,umask=0xa 00 itlb.flush virtual memory ITLB flushes event=0x82,period=200000,umask=4 00 itlb.hit virtual memory ITLB hits event=0x82,period=200000,umask=1 00 itlb.misses virtual memory ITLB misses (Must be precise) event=0x82,period=200000,umask=2 00 mem_load_retired.dtlb_miss virtual memory Retired loads that miss the DTLB (precise event) (Precise event) event=0xcb,period=200000,umask=4 00 page_walks.cycles virtual memory Duration of page-walks in core cycles event=0xc,period=2000000,umask=3 00 page_walks.d_side_cycles virtual memory Duration of D-side only page walks event=0xc,period=2000000,umask=1 00 page_walks.d_side_walks virtual memory Number of D-side only page walks event=0xc,period=200000,umask=1 00 page_walks.i_side_cycles virtual memory Duration of I-Side page walks event=0xc,period=2000000,umask=2 00 page_walks.i_side_walks virtual memory Number of I-Side page walks event=0xc,period=200000,umask=2 00 page_walks.walks virtual memory Number of page-walks executed event=0xc,period=200000,umask=3 00 l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=1 00 This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace l1d_pend_miss.fb_full cache Cycles a demand request was blocked due to Fill Buffers unavailability event=0x48,cmask=1,period=2000003,umask=2 00 l1d_pend_miss.pending cache L1D miss outstandings duration in cycles event=0x48,period=2000003,umask=1 00 This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=2000003,umask=1 00 This event counts duration of L1D miss outstanding in cycles l1d_pend_miss.pending_cycles_any cache Cycles with L1D load Misses outstanding from any thread on physical core event=0x48,any=1,cmask=1,period=2000003,umask=1 00 l2_demand_rqsts.wb_hit cache Not rejected writebacks that hit L2 cache event=0x27,period=200003,umask=0x50 00 This event counts the number of WB requests that hit L2 cache l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=7 00 This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_in.e cache L2 cache lines in E state filling L2 event=0xf1,period=100003,umask=4 00 This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects l2_lines_in.i cache L2 cache lines in I state filling L2 event=0xf1,period=100003,umask=1 00 This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects l2_lines_in.s cache L2 cache lines in S state filling L2 event=0xf1,period=100003,umask=2 00 This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects l2_lines_out.demand_clean cache Clean L2 cache lines evicted by demand event=0xf2,period=100003,umask=5 00 l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0xe4 00 This event counts the total number of L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=0xe1 00 This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache event=0x24,period=200003,umask=0x27 00 l2_rqsts.all_demand_references cache Demand requests to L2 cache event=0x24,period=200003,umask=0xe7 00 l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xf8 00 This event counts the total number of requests from the L2 hardware prefetchers l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xe2 00 This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0xc4 00 l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x24 00 l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=0xc1 00 Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2, no rejects event=0x24,period=200003,umask=0x21 00 This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted l2_rqsts.l2_pf_hit cache L2 prefetch requests that hit L2 cache event=0x24,period=200003,umask=0xd0 00 This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types l2_rqsts.l2_pf_miss cache L2 prefetch requests that miss L2 cache event=0x24,period=200003,umask=0x30 00 This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache l2_rqsts.miss cache All requests that miss L2 cache event=0x24,period=200003,umask=0x3f 00 l2_rqsts.references cache All L2 requests event=0x24,period=200003,umask=0xff 00 l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0xc2 00 l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x22 00 l2_trans.all_pf cache L2 or L3 HW prefetches that access L2 cache event=0xf0,period=200003,umask=8 00 This event counts L2 or L3 HW prefetches that access L2 cache including rejects l2_trans.all_requests cache Transactions accessing L2 pipe event=0xf0,period=200003,umask=0x80 00 This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on l2_trans.code_rd cache L2 cache accesses when fetching instructions event=0xf0,period=200003,umask=4 00 This event counts the number of L2 cache accesses when fetching instructions l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=1 00 This event counts Demand Data Read requests that access L2 cache, including rejects l2_trans.l1d_wb cache L1D writebacks that access L2 cache event=0xf0,period=200003,umask=0x10 00 This event counts L1D writebacks that access L2 cache l2_trans.l2_fill cache L2 fill requests that access L2 cache event=0xf0,period=200003,umask=0x20 00 This event counts L2 fill requests that access L2 cache l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40 00 This event counts L2 writebacks that access L2 cache l2_trans.rfo cache RFO requests that access L2 cache event=0xf0,period=200003,umask=2 00 This event counts Read for Ownership (RFO) requests that access L2 cache lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x63,period=2000003,umask=2 00 This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION) longest_lat_cache.miss cache Core-originated cacheable demand requests missed L3 event=0x2e,period=100003,umask=0x41 00 This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to L3 event=0x2e,period=100003,umask=0x4f 00 This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU mem_load_uops_l3_hit_retired.xsnp_hit cache Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) event=0xd2,period=20011,umask=2 00 This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared L3 Supports address when precise. Spec update: BDM100 (Precise event) event=0xd2,period=20011,umask=4 00 This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3) Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_miss cache Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) event=0xd2,period=20011,umask=1 00 This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_none cache Retired load uops which data sources were hits in L3 without snoops required Supports address when precise. Spec update: BDM100 (Precise event) event=0xd2,period=100003,umask=8 00 This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_miss_retired.local_dram cache Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70, BDM100 (Precise event) event=0xd3,period=100007,umask=1 00 Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70, BDM100 (Precise event) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x40 00 This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load Supports address when precise (Precise event) mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=2000003,umask=1 00 This event counts retired load uops which data sources were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source Supports address when precise (Precise event) mem_load_uops_retired.l1_miss cache Retired load uops misses in L1 cache as data sources Supports address when precise (Precise event) event=0xd1,period=100003,umask=8 00 This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources Supports address when precise. Spec update: BDM35 (Precise event) event=0xd1,period=100003,umask=2 00 This event counts retired load uops which data sources were hits in the mid-level (L2) cache Supports address when precise. Spec update: BDM35 (Precise event) mem_load_uops_retired.l2_miss cache Miss in mid-level (L2) cache. Excludes Unknown data-source Supports address when precise (Precise event) event=0xd1,period=50021,umask=0x10 00 This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) mem_load_uops_retired.l3_hit cache Retired load uops which data sources were data hits in L3 without snoops required Supports address when precise. Spec update: BDM100 (Precise event) event=0xd1,period=50021,umask=4 00 This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_retired.l3_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source Supports address when precise. Spec update: BDM100, BDE70 (Precise event) event=0xd1,period=100007,umask=0x20 00 mem_uops_retired.all_loads cache Retired load uops Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x81 00 Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW Supports address when precise (Precise event) mem_uops_retired.all_stores cache Retired store uops Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x82 00 Counts all retired store uops Supports address when precise (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access Supports address when precise. Spec update: BDM35 (Precise event) event=0xd0,period=100007,umask=0x21 00 This event counts load uops with locked access retired to the architected path Supports address when precise. Spec update: BDM35 (Precise event) mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x41 00 This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x42 00 This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x11 00 This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x12 00 This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=8 00 This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests.all_requests cache Any memory transaction that reached the SQ event=0xb0,period=100003,umask=0x80 00 This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on offcore_requests.demand_code_rd cache Cacheable and non-cacheable code read requests event=0xb0,period=100003,umask=2 00 This event counts both cacheable and non-cacheable code read requests offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=1 00 This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=4 00 This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_requests_buffer.sq_full cache Offcore requests buffer cannot take more entries for this thread core event=0xb2,period=2000003,umask=1 00 This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full. Note: Writeback pending FIFO has six entries offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Spec update: BDM76 event=0x60,period=2000003,umask=8 00 This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: BDM76 event=0x60,cmask=1,period=2000003,umask=8 00 This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: BDM76 event=0x60,cmask=1,period=2000003,umask=1 00 This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) Spec update: BDM76 offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: BDM76 event=0x60,cmask=1,period=2000003,umask=4 00 This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: BDM76 event=0x60,period=2000003,umask=2 00 This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue Spec update: BDM76 event=0x60,period=2000003,umask=1 00 This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS. Note: A prefetch promoted to Demand is counted from the promotion point Spec update: BDM76 offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Spec update: BDM76 event=0x60,cmask=6,period=2000003,umask=1 00 offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Spec update: BDM76 event=0x60,period=2000003,umask=4 00 This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_response cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction event=0xb7,period=100003,umask=1 00 offcore_response.all_data_rd.any_response cache Counts all demand & prefetch data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10091 00 offcore_response.all_data_rd.l3_hit.any_snoop cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0091 00 offcore_response.all_data_rd.l3_hit.snoop_hitm cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0091 00 offcore_response.all_data_rd.l3_hit.snoop_hit_no_fwd cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0091 00 offcore_response.all_data_rd.l3_hit.snoop_miss cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0091 00 offcore_response.all_data_rd.l3_hit.snoop_none cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0091 00 offcore_response.all_data_rd.l3_hit.snoop_not_needed cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0091 00 offcore_response.all_data_rd.supplier_none.any_snoop cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020091 00 offcore_response.all_data_rd.supplier_none.snoop_hitm cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020091 00 offcore_response.all_data_rd.supplier_none.snoop_hit_no_fwd cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020091 00 offcore_response.all_data_rd.supplier_none.snoop_miss cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020091 00 offcore_response.all_data_rd.supplier_none.snoop_none cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020091 00 offcore_response.all_data_rd.supplier_none.snoop_not_needed cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020091 00 offcore_response.all_pf_code_rd.any_response cache Counts all prefetch code reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10240 00 offcore_response.all_pf_code_rd.l3_hit.any_snoop cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0240 00 offcore_response.all_pf_code_rd.l3_hit.snoop_hitm cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0240 00 offcore_response.all_pf_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0240 00 offcore_response.all_pf_code_rd.l3_hit.snoop_miss cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0240 00 offcore_response.all_pf_code_rd.l3_hit.snoop_none cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0240 00 offcore_response.all_pf_code_rd.l3_hit.snoop_not_needed cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0240 00 offcore_response.all_pf_code_rd.supplier_none.any_snoop cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_hitm cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_miss cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_none cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_not_needed cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020240 00 offcore_response.all_pf_data_rd.any_response cache Counts all prefetch data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10090 00 offcore_response.all_pf_data_rd.l3_hit.any_snoop cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0090 00 offcore_response.all_pf_data_rd.l3_hit.snoop_hitm cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0090 00 offcore_response.all_pf_data_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0090 00 offcore_response.all_pf_data_rd.l3_hit.snoop_miss cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0090 00 offcore_response.all_pf_data_rd.l3_hit.snoop_none cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0090 00 offcore_response.all_pf_data_rd.l3_hit.snoop_not_needed cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0090 00 offcore_response.all_pf_data_rd.supplier_none.any_snoop cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_hitm cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_miss cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_none cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_not_needed cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020090 00 offcore_response.all_pf_rfo.any_response cache Counts prefetch RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10120 00 offcore_response.all_pf_rfo.l3_hit.any_snoop cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_hitm cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_hit_no_fwd cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_miss cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_none cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_not_needed cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0120 00 offcore_response.all_pf_rfo.supplier_none.any_snoop cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020120 00 offcore_response.all_pf_rfo.supplier_none.snoop_hitm cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020120 00 offcore_response.all_pf_rfo.supplier_none.snoop_hit_no_fwd cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x400020120 00 offcore_response.all_pf_rfo.supplier_none.snoop_miss cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020120 00 offcore_response.all_pf_rfo.supplier_none.snoop_none cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020120 00 offcore_response.all_pf_rfo.supplier_none.snoop_not_needed cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x100020120 00 offcore_response.all_rfo.any_response cache Counts all demand & prefetch RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10122 00 offcore_response.all_rfo.l3_hit.any_snoop cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0122 00 offcore_response.all_rfo.l3_hit.snoop_hitm cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122 00 offcore_response.all_rfo.l3_hit.snoop_hit_no_fwd cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122 00 offcore_response.all_rfo.l3_hit.snoop_miss cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0122 00 offcore_response.all_rfo.l3_hit.snoop_none cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0122 00 offcore_response.all_rfo.l3_hit.snoop_not_needed cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0122 00 offcore_response.all_rfo.supplier_none.any_snoop cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020122 00 offcore_response.all_rfo.supplier_none.snoop_hitm cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020122 00 offcore_response.all_rfo.supplier_none.snoop_hit_no_fwd cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x400020122 00 offcore_response.all_rfo.supplier_none.snoop_miss cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020122 00 offcore_response.all_rfo.supplier_none.snoop_none cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020122 00 offcore_response.all_rfo.supplier_none.snoop_not_needed cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x100020122 00 offcore_response.corewb.any_response cache Counts writebacks (modified to exclusive) have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10008 00 offcore_response.corewb.l3_hit.any_snoop cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0008 00 offcore_response.corewb.l3_hit.snoop_hitm cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0008 00 offcore_response.corewb.l3_hit.snoop_hit_no_fwd cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0008 00 offcore_response.corewb.l3_hit.snoop_miss cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0008 00 offcore_response.corewb.l3_hit.snoop_none cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0008 00 offcore_response.corewb.l3_hit.snoop_not_needed cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0008 00 offcore_response.corewb.supplier_none.any_snoop cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020008 00 offcore_response.corewb.supplier_none.snoop_hitm cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020008 00 offcore_response.corewb.supplier_none.snoop_hit_no_fwd cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x400020008 00 offcore_response.corewb.supplier_none.snoop_miss cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x200020008 00 offcore_response.corewb.supplier_none.snoop_none cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x80020008 00 offcore_response.corewb.supplier_none.snoop_not_needed cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x100020008 00 offcore_response.demand_code_rd.any_response cache Counts all demand code reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10004 00 offcore_response.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004 00 offcore_response.demand_code_rd.supplier_none.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020004 00 offcore_response.demand_code_rd.supplier_none.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020004 00 offcore_response.demand_code_rd.supplier_none.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020004 00 offcore_response.demand_code_rd.supplier_none.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020004 00 offcore_response.demand_code_rd.supplier_none.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020004 00 offcore_response.demand_code_rd.supplier_none.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020004 00 offcore_response.demand_data_rd.any_response cache Counts demand data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10001 00 offcore_response.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001 00 offcore_response.demand_data_rd.supplier_none.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020001 00 offcore_response.demand_data_rd.supplier_none.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020001 00 offcore_response.demand_data_rd.supplier_none.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020001 00 offcore_response.demand_data_rd.supplier_none.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020001 00 offcore_response.demand_data_rd.supplier_none.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020001 00 offcore_response.demand_data_rd.supplier_none.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020001 00 offcore_response.demand_rfo.any_response cache Counts all demand data writes (RFOs) have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10002 00 offcore_response.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002 00 offcore_response.demand_rfo.l3_hit.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002 00 offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002 00 offcore_response.demand_rfo.l3_hit.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0002 00 offcore_response.demand_rfo.l3_hit.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0002 00 offcore_response.demand_rfo.l3_hit.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002 00 offcore_response.other.any_response cache Counts any other requests have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x18000 00 offcore_response.other.l3_hit.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C8000 00 offcore_response.other.l3_hit.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C8000 00 offcore_response.other.l3_hit.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C8000 00 offcore_response.other.l3_hit.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C8000 00 offcore_response.other.l3_hit.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x803C8000 00 offcore_response.other.l3_hit.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C8000 00 offcore_response.other.supplier_none.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80028000 00 offcore_response.other.supplier_none.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1000028000 00 offcore_response.other.supplier_none.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x400028000 00 offcore_response.other.supplier_none.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200028000 00 offcore_response.other.supplier_none.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80028000 00 offcore_response.other.supplier_none.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x100028000 00 offcore_response.pf_l2_code_rd.any_response cache Counts all prefetch (that bring data to LLC only) code reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10040 00 offcore_response.pf_l2_code_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0040 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0040 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0040 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0040 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0040 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0040 00 offcore_response.pf_l2_code_rd.supplier_none.any_snoop cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_miss cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_none cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020040 00 offcore_response.pf_l2_data_rd.any_response cache Counts prefetch (that bring data to L2) data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10010 00 offcore_response.pf_l2_data_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_hitm cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_no_fwd cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_not_needed cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010 00 offcore_response.pf_l2_data_rd.supplier_none.any_snoop cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_hitm cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_hit_no_fwd cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_not_needed cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020010 00 offcore_response.pf_l2_rfo.any_response cache Counts all prefetch (that bring data to L2) RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10020 00 offcore_response.pf_l2_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020 00 offcore_response.pf_l2_rfo.supplier_none.any_snoop cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x400020020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x100020020 00 offcore_response.pf_l3_code_rd.any_response cache Counts prefetch (that bring data to LLC only) code reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10200 00 offcore_response.pf_l3_code_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0200 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_hitm cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0200 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_hit_no_fwd cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0200 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0200 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_none cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0200 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_not_needed cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0200 00 offcore_response.pf_l3_code_rd.supplier_none.any_snoop cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_hitm cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_hit_no_fwd cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_miss cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_none cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_not_needed cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020200 00 offcore_response.pf_l3_data_rd.any_response cache Counts all prefetch (that bring data to LLC only) data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10080 00 offcore_response.pf_l3_data_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0080 00 offcore_response.pf_l3_data_rd.supplier_none.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020080 00 offcore_response.pf_l3_rfo.any_response cache Counts all prefetch (that bring data to LLC only) RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10100 00 offcore_response.pf_l3_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0100 00 offcore_response.pf_l3_rfo.supplier_none.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x400020100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x100020100 00 sq_misc.split_lock cache Split locks in SQ event=0xf4,period=100003,umask=0x10 00 This event counts the number of split locks in the super queue fp_arith_inst_retired.128b_packed_double floating point Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=4 00 Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.128b_packed_single floating point Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element event=0xc7,period=2000003,umask=8 00 Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_double floating point Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element event=0xc7,period=2000003,umask=0x10 00 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_single floating point Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element event=0xc7,period=2000003,umask=0x20 00 Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.4_flops floating point Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x18 00 Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.double floating point Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000006,umask=0x15 00 fp_arith_inst_retired.packed floating point Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000004,umask=0x3c 00 fp_arith_inst_retired.scalar floating point Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000003,umask=3 00 Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_double floating point Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000003,umask=1 00 Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_single floating point Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000003,umask=2 00 Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.single floating point Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000005,umask=0x2a 00 fp_arith_inst_retired.vector floating point Number of any Vector retired FP arithmetic instructions event=0xc7,period=2000003,umask=0xfc 00 fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e 00 This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 fp_assist.simd_input floating point Number of SIMD FP assists due to input values event=0xca,period=100003,umask=0x10 00 This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention fp_assist.simd_output floating point Number of SIMD FP assists due to Output values event=0xca,period=100003,umask=8 00 This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention fp_assist.x87_input floating point Number of X87 assists due to input value event=0xca,period=100003,umask=4 00 This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid fp_assist.x87_output floating point Number of X87 assists due to output value event=0xca,period=100003,umask=2 00 This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid move_elimination.simd_eliminated floating point Number of SIMD Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=2 00 move_elimination.simd_not_eliminated floating point Number of SIMD Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=8 00 other_assists.avx_to_sse floating point Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: BDM30 event=0xc1,period=100003,umask=8 00 This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable Spec update: BDM30 other_assists.sse_to_avx floating point Number of transitions from SSE to AVX-256 when penalty applicable Spec update: BDM30 event=0xc1,period=100003,umask=0x10 00 This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable Spec update: BDM30 uop_dispatches_cancelled.simd_prf floating point Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports event=0xa0,period=2000003,umask=3 00 This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information baclears.any frontend Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end event=0xe6,period=100003,umask=0x1f 00 dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=2 00 This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles icache.hit frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches event=0x80,period=2000003,umask=1 00 This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches icache.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction-cache miss event=0x80,period=2000003,umask=4 00 This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit) icache.misses frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses event=0x80,period=200003,umask=2 00 This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x18 00 This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x18 00 This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24 00 This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24 00 This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=8 00 This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=8 00 This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.empty frontend Instruction Decode Queue (IDQ) empty cycles event=0x79,period=2000003,umask=2 00 This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty idq.mite_all_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x3c 00 This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=4 00 This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=4 00 This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10 00 This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_dsb_occur frontend Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,edge=1,period=2000003,umask=0x10 00 This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_dsb_uops frontend Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x10 00 This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20 00 This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_switches frontend Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer event=0x79,cmask=1,edge=1,period=2000003,umask=0x30 00 idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30 00 This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=1 00 This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread; b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); c. Instruction Decode Queue (IDQ) delivers four uops idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=4,period=2000003,umask=1 00 This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 idq_uops_not_delivered.cycles_fe_was_ok frontend Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE event=0x9c,cmask=1,inv=1,period=2000003,umask=1 00 idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=3,period=2000003,umask=1 00 This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3 idq_uops_not_delivered.cycles_le_2_uop_deliv.core frontend Cycles with less than 2 uops delivered by the front end event=0x9c,cmask=2,period=2000003,umask=1 00 idq_uops_not_delivered.cycles_le_3_uop_deliv.core frontend Cycles with less than 3 uops delivered by the front end event=0x9c,cmask=1,period=2000003,umask=1 00 hle_retired.aborted memory Number of times HLE abort was triggered (Precise event) event=0xc8,period=2000003,umask=4 00 Number of times HLE abort was triggered (Precise event) hle_retired.aborted_misc1 memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=2000003,umask=8 00 Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details) hle_retired.aborted_misc2 memory Number of times an HLE execution aborted due to uncommon conditions event=0xc8,period=2000003,umask=0x10 00 Number of times the TSX watchdog signaled an HLE abort hle_retired.aborted_misc3 memory Number of times an HLE execution aborted due to HLE-unfriendly instructions event=0xc8,period=2000003,umask=0x20 00 Number of times a disallowed operation caused an HLE abort hle_retired.aborted_misc4 memory Number of times an HLE execution aborted due to incompatible memory type event=0xc8,period=2000003,umask=0x40 00 Number of times HLE caused a fault hle_retired.aborted_misc5 memory Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) event=0xc8,period=2000003,umask=0x80 00 Number of times HLE aborted and was not due to the abort conditions in subevents 3-6 hle_retired.commit memory Number of times HLE commit succeeded event=0xc8,period=2000003,umask=2 00 Number of times HLE commit succeeded hle_retired.start memory Number of times we entered an HLE region; does not count nested transactions event=0xc8,period=2000003,umask=1 00 Number of times we entered an HLE region does not count nested transactions machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=2 00 This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following: 1. memory disambiguation, 2. external snoop, or 3. cross SMT-HW-thread snoop (stores) hitting load buffer mem_trans_retired.load_latency_gt_128 memory Randomly selected loads with latency value being above 128 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=1009,umask=1,ldlat=0x80 00 Counts randomly selected loads with latency value being above 128 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_16 memory Randomly selected loads with latency value being above 16 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=20011,umask=1,ldlat=0x10 00 Counts randomly selected loads with latency value being above 16 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_256 memory Randomly selected loads with latency value being above 256 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=503,umask=1,ldlat=0x100 00 Counts randomly selected loads with latency value being above 256 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_32 memory Randomly selected loads with latency value being above 32 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=100007,umask=1,ldlat=0x20 00 Counts randomly selected loads with latency value being above 32 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_4 memory Randomly selected loads with latency value being above 4 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x4 00 Counts randomly selected loads with latency value being above four Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_512 memory Randomly selected loads with latency value being above 512 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=101,umask=1,ldlat=0x200 00 Counts randomly selected loads with latency value being above 512 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_64 memory Randomly selected loads with latency value being above 64 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=2003,umask=1,ldlat=0x40 00 Counts randomly selected loads with latency value being above 64 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_8 memory Randomly selected loads with latency value being above 8 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=50021,umask=1,ldlat=0x8 00 Counts randomly selected loads with latency value being above eight Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) misalign_mem_ref.loads memory Speculative cache line split load uops dispatched to L1 cache event=5,period=2000003,umask=1 00 This event counts speculative cache-line split load uops dispatched to the L1 cache misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=5,period=2000003,umask=2 00 This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache offcore_response.all_data_rd.l3_hit.snoop_non_dram memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0091 00 offcore_response.all_data_rd.l3_miss.snoop_hit_no_fwd memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000091 00 offcore_response.all_data_rd.l3_miss.snoop_miss memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000091 00 offcore_response.all_data_rd.l3_miss.snoop_none memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000091 00 offcore_response.all_data_rd.l3_miss.snoop_not_needed memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000091 00 offcore_response.all_data_rd.l3_miss_local_dram.any_snoop memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_hitm memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_none memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000091 00 offcore_response.all_data_rd.supplier_none.snoop_non_dram memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020091 00 offcore_response.all_pf_code_rd.l3_hit.snoop_non_dram memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0240 00 offcore_response.all_pf_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000240 00 offcore_response.all_pf_code_rd.l3_miss.snoop_miss memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000240 00 offcore_response.all_pf_code_rd.l3_miss.snoop_none memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000240 00 offcore_response.all_pf_code_rd.l3_miss.snoop_not_needed memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_non_dram memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020240 00 offcore_response.all_pf_data_rd.l3_hit.snoop_non_dram memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0090 00 offcore_response.all_pf_data_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000090 00 offcore_response.all_pf_data_rd.l3_miss.snoop_miss memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000090 00 offcore_response.all_pf_data_rd.l3_miss.snoop_none memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000090 00 offcore_response.all_pf_data_rd.l3_miss.snoop_not_needed memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_non_dram memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020090 00 offcore_response.all_pf_rfo.l3_hit.snoop_non_dram memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0120 00 offcore_response.all_pf_rfo.l3_miss.snoop_hit_no_fwd memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000120 00 offcore_response.all_pf_rfo.l3_miss.snoop_miss memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000120 00 offcore_response.all_pf_rfo.l3_miss.snoop_none memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000120 00 offcore_response.all_pf_rfo.l3_miss.snoop_not_needed memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoop memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hitm memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x404000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_none memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_non_dram memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_not_needed memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x104000120 00 offcore_response.all_pf_rfo.supplier_none.snoop_non_dram memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020120 00 offcore_response.all_rfo.l3_hit.snoop_non_dram memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0122 00 offcore_response.all_rfo.l3_miss.snoop_hit_no_fwd memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000122 00 offcore_response.all_rfo.l3_miss.snoop_miss memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000122 00 offcore_response.all_rfo.l3_miss.snoop_none memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000122 00 offcore_response.all_rfo.l3_miss.snoop_not_needed memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000122 00 offcore_response.all_rfo.l3_miss_local_dram.any_snoop memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_hitm memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x404000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_none memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x104000122 00 offcore_response.all_rfo.supplier_none.snoop_non_dram memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020122 00 offcore_response.corewb.l3_hit.snoop_non_dram memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0008 00 offcore_response.corewb.l3_miss.snoop_hit_no_fwd memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000008 00 offcore_response.corewb.l3_miss.snoop_miss memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000008 00 offcore_response.corewb.l3_miss.snoop_none memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000008 00 offcore_response.corewb.l3_miss.snoop_not_needed memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000008 00 offcore_response.corewb.l3_miss_local_dram.any_snoop memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_hitm memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_hit_no_fwd memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x404000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_miss memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x204000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_none memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x84000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_non_dram memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_not_needed memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x104000008 00 offcore_response.corewb.supplier_none.snoop_non_dram memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020008 00 offcore_response.demand_code_rd.l3_hit.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0004 00 offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000004 00 offcore_response.demand_code_rd.l3_miss.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000004 00 offcore_response.demand_code_rd.l3_miss.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000004 00 offcore_response.demand_code_rd.l3_miss.snoop_not_needed memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hitm memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000004 00 offcore_response.demand_code_rd.supplier_none.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020004 00 offcore_response.demand_data_rd.l3_hit.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0001 00 offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwd memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000001 00 offcore_response.demand_data_rd.l3_miss.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000001 00 offcore_response.demand_data_rd.l3_miss.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000001 00 offcore_response.demand_data_rd.l3_miss.snoop_not_needed memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hitm memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000001 00 offcore_response.demand_data_rd.supplier_none.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020001 00 offcore_response.demand_rfo.l3_hit.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0002 00 offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwd memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000002 00 offcore_response.demand_rfo.l3_miss.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000002 00 offcore_response.demand_rfo.l3_miss.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000002 00 offcore_response.demand_rfo.l3_miss.snoop_not_needed memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000002 00 offcore_response.demand_rfo.l3_miss_local_dram.any_snoop memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000002 00 offcore_response.other.l3_hit.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C8000 00 offcore_response.other.l3_miss.snoop_hit_no_fwd memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x43C008000 00 offcore_response.other.l3_miss.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x23C008000 00 offcore_response.other.l3_miss.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0xBC008000 00 offcore_response.other.l3_miss.snoop_not_needed memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x13C008000 00 offcore_response.other.l3_miss_local_dram.any_snoop memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84008000 00 offcore_response.other.l3_miss_local_dram.snoop_hitm memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1004008000 00 offcore_response.other.l3_miss_local_dram.snoop_hit_no_fwd memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x404008000 00 offcore_response.other.l3_miss_local_dram.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x204008000 00 offcore_response.other.l3_miss_local_dram.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x84008000 00 offcore_response.other.l3_miss_local_dram.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2004008000 00 offcore_response.other.l3_miss_local_dram.snoop_not_needed memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x104008000 00 offcore_response.other.supplier_none.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2000028000 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0040 00 offcore_response.pf_l2_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000040 00 offcore_response.pf_l2_code_rd.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000040 00 offcore_response.pf_l2_code_rd.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000040 00 offcore_response.pf_l2_code_rd.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020040 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_non_dram memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0010 00 offcore_response.pf_l2_data_rd.l3_miss.snoop_hit_no_fwd memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000010 00 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000010 00 offcore_response.pf_l2_data_rd.l3_miss.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000010 00 offcore_response.pf_l2_data_rd.l3_miss.snoop_not_needed memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoop memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hitm memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_non_dram memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020010 00 offcore_response.pf_l2_rfo.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0020 00 offcore_response.pf_l2_rfo.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000020 00 offcore_response.pf_l2_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000020 00 offcore_response.pf_l2_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000020 00 offcore_response.pf_l2_rfo.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x404000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x104000020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020020 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_non_dram memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0200 00 offcore_response.pf_l3_code_rd.l3_miss.snoop_hit_no_fwd memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000200 00 offcore_response.pf_l3_code_rd.l3_miss.snoop_miss memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000200 00 offcore_response.pf_l3_code_rd.l3_miss.snoop_none memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000200 00 offcore_response.pf_l3_code_rd.l3_miss.snoop_not_needed memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.any_snoop memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hitm memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_miss memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_none memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_non_dram memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020200 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0080 00 offcore_response.pf_l3_data_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000080 00 offcore_response.pf_l3_data_rd.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000080 00 offcore_response.pf_l3_data_rd.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000080 00 offcore_response.pf_l3_data_rd.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020080 00 offcore_response.pf_l3_rfo.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0100 00 offcore_response.pf_l3_rfo.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000100 00 offcore_response.pf_l3_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000100 00 offcore_response.pf_l3_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000100 00 offcore_response.pf_l3_rfo.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x404000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x104000100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020100 00 rtm_retired.aborted memory Number of times RTM abort was triggered (Must be precise) event=0xc9,period=2000003,umask=4 00 Number of times RTM abort was triggered (Must be precise) rtm_retired.aborted_misc1 memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=2000003,umask=8 00 Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details) rtm_retired.aborted_misc2 memory Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc9,period=2000003,umask=0x10 00 Number of times the TSX watchdog signaled an RTM abort rtm_retired.aborted_misc3 memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=2000003,umask=0x20 00 Number of times a disallowed operation caused an RTM abort rtm_retired.aborted_misc4 memory Number of times an RTM execution aborted due to incompatible memory type event=0xc9,period=2000003,umask=0x40 00 Number of times a RTM caused a fault rtm_retired.aborted_misc5 memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=2000003,umask=0x80 00 Number of times RTM aborted and was not due to the abort conditions in subevents 3-6 rtm_retired.commit memory Number of times RTM commit succeeded event=0xc9,period=2000003,umask=2 00 Number of times RTM commit succeeded rtm_retired.start memory Number of times we entered an RTM region; does not count nested transactions event=0xc9,period=2000003,umask=1 00 Number of times we entered an RTM region does not count nested transactions tx_exec.misc1 memory Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort event=0x5d,period=2000003,umask=1 00 tx_exec.misc2 memory Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region event=0x5d,period=2000003,umask=2 00 Unfriendly TSX abort triggered by a vzeroupper instruction tx_exec.misc3 memory Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded event=0x5d,period=2000003,umask=4 00 Unfriendly TSX abort triggered by a nest count that is too deep tx_exec.misc4 memory Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region event=0x5d,period=2000003,umask=8 00 RTM region detected inside HLE tx_exec.misc5 memory Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region event=0x5d,period=2000003,umask=0x10 00 tx_mem.abort_capacity_write memory Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow event=0x54,period=2000003,umask=2 00 Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow tx_mem.abort_conflict memory Number of times a TSX line had a cache conflict event=0x54,period=2000003,umask=1 00 Number of times a TSX line had a cache conflict tx_mem.abort_hle_elision_buffer_mismatch memory Number of times a TSX Abort was triggered due to release/commit but data and address mismatch event=0x54,period=2000003,umask=0x10 00 Number of times a TSX Abort was triggered due to release/commit but data and address mismatch tx_mem.abort_hle_elision_buffer_not_empty memory Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty event=0x54,period=2000003,umask=8 00 Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer event=0x54,period=2000003,umask=0x20 00 Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer tx_mem.abort_hle_store_to_elided_lock memory Number of times a TSX Abort was triggered due to a non-release/commit store to lock event=0x54,period=2000003,umask=4 00 Number of times a TSX Abort was triggered due to a non-release/commit store to lock tx_mem.hle_elision_buffer_full memory Number of times we could not allocate Lock Buffer event=0x54,period=2000003,umask=0x40 00 Number of times we could not allocate Lock Buffer cpl_cycles.ring0 other Unhalted core cycles when the thread is in ring 0 event=0x5c,period=2000003,umask=1 00 This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100007,umask=1 00 This event counts when there is a transition from ring 1,2 or 3 to ring0 cpl_cycles.ring123 other Unhalted core cycles when thread is in rings 1, 2, or 3 event=0x5c,period=2000003,umask=2 00 This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3 lock_cycles.split_lock_uc_lock_duration other Cycles when L1 and L2 are locked due to UC or split lock event=0x63,period=2000003,umask=1 00 This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access arith.fpu_div_active pipeline Cycles when divider is busy executing divide operations event=0x14,period=2000003,umask=1 00 This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed br_inst_exec.all_branches pipeline Speculative and retired branches event=0x88,period=200003,umask=0xff 00 This event counts both taken and not taken speculative and retired branch instructions br_inst_exec.all_conditional pipeline Speculative and retired macro-conditional branches event=0x88,period=200003,umask=0xc1 00 This event counts both taken and not taken speculative and retired macro-conditional branch instructions br_inst_exec.all_direct_jmp pipeline Speculative and retired macro-unconditional branches excluding calls and indirects event=0x88,period=200003,umask=0xc2 00 This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects br_inst_exec.all_direct_near_call pipeline Speculative and retired direct near calls event=0x88,period=200003,umask=0xd0 00 This event counts both taken and not taken speculative and retired direct near calls br_inst_exec.all_indirect_jump_non_call_ret pipeline Speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0xc4 00 This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches br_inst_exec.all_indirect_near_return pipeline Speculative and retired indirect return branches event=0x88,period=200003,umask=0xc8 00 This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic br_inst_exec.nontaken_conditional pipeline Not taken macro-conditional branches event=0x88,period=200003,umask=0x41 00 This event counts not taken macro-conditional branch instructions br_inst_exec.taken_conditional pipeline Taken speculative and retired macro-conditional branches event=0x88,period=200003,umask=0x81 00 This event counts taken speculative and retired macro-conditional branch instructions br_inst_exec.taken_direct_jump pipeline Taken speculative and retired macro-conditional branch instructions excluding calls and indirects event=0x88,period=200003,umask=0x82 00 This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches br_inst_exec.taken_direct_near_call pipeline Taken speculative and retired direct near calls event=0x88,period=200003,umask=0x90 00 This event counts taken speculative and retired direct near calls br_inst_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0x84 00 This event counts taken speculative and retired indirect branches excluding calls and return branches br_inst_exec.taken_indirect_near_call pipeline Taken speculative and retired indirect calls event=0x88,period=200003,umask=0xa0 00 This event counts taken speculative and retired indirect calls including both register and memory indirect br_inst_exec.taken_indirect_near_return pipeline Taken speculative and retired indirect branches with return mnemonic event=0x88,period=200003,umask=0x88 00 This event counts taken speculative and retired indirect branches that have a return mnemonic br_inst_retired.all_branches pipeline All (macro) branch instructions retired event=0xc4,period=400009 00 This event counts all (macro) branch instructions retired br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired. (Precise Event - PEBS) Spec update: BDW98 (Must be precise) event=0xc4,period=400009,umask=4 00 This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired Spec update: BDW98 (Must be precise) br_inst_retired.conditional pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=1 00 This event counts conditional branch instructions retired (Precise event) br_inst_retired.far_branch pipeline Far branch instructions retired Spec update: BDW98 event=0xc4,period=100007,umask=0x40 00 This event counts far branch instructions retired Spec update: BDW98 br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100007,umask=2 00 This event counts both direct and indirect near call instructions retired (Precise event) br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) event=0xc4,period=100007,umask=2 00 This event counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100007,umask=8 00 This event counts return instructions retired (Precise event) br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20 00 This event counts taken branch instructions retired (Precise event) br_inst_retired.not_taken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10 00 This event counts not taken branch instructions retired br_misp_exec.all_branches pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xff 00 This event counts both taken and not taken speculative and retired mispredicted branch instructions br_misp_exec.all_conditional pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xc1 00 This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.all_indirect_jump_non_call_ret pipeline Mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0xc4 00 This event counts both taken and not taken mispredicted indirect branches excluding calls and returns br_misp_exec.indirect pipeline Speculative mispredicted indirect branches event=0x89,period=200003,umask=0xe4 00 Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded) br_misp_exec.nontaken_conditional pipeline Not taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x41 00 This event counts not taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.taken_conditional pipeline Taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x81 00 This event counts taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0x84 00 This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns br_misp_exec.taken_indirect_near_call pipeline Taken speculative and retired mispredicted indirect calls event=0x89,period=200003,umask=0xa0 00 br_misp_exec.taken_return_near pipeline Taken speculative and retired mispredicted indirect branches with return mnemonic event=0x89,period=200003,umask=0x88 00 This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009 00 This event counts all mispredicted macro branch instructions retired br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc5,period=400009,umask=4 00 This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise) br_misp_retired.conditional pipeline Mispredicted conditional branch instructions retired (Precise event) event=0xc5,period=400009,umask=1 00 This event counts mispredicted conditional branch instructions retired (Precise event) br_misp_retired.near_taken pipeline number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20 00 Number of near branch instructions retired that were mispredicted and taken (Precise event) br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) event=0xc5,period=100007,umask=8 00 This event counts mispredicted return instructions retired (Precise event) cpu_clk_thread_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other thread is halted event=0x3c,period=100003,umask=2 00 cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=1 00 This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=100003,umask=1 00 cpu_clk_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other thread is halted event=0x3c,period=100003,umask=2 00 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3 00 This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=1 00 Reference cycles when the thread is unhalted (counts at 100 MHz rate) cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=100003,umask=1 00 cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003 00 This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cpu_clk_unhalted.thread_any pipeline Core cycles when at least one thread on the physical core is not in halt state event=0x3c,any=1,period=2000003 00 cpu_clk_unhalted.thread_p_any pipeline Core cycles when at least one thread on the physical core is not in halt state event=0x3c,any=1,period=2000003 00 cycle_activity.cycles_l1d_miss pipeline Cycles while L1 cache miss demand load is outstanding event=0xa3,cmask=8,period=2000003,umask=8 00 cycle_activity.cycles_l1d_pending pipeline Cycles while L1 cache miss demand load is outstanding event=0xa3,cmask=8,period=2000003,umask=8 00 Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache cycle_activity.cycles_l2_miss pipeline Cycles while L2 cache miss demand load is outstanding event=0xa3,cmask=1,period=2000003,umask=1 00 cycle_activity.cycles_l2_pending pipeline Cycles while L2 cache miss demand load is outstanding event=0xa3,cmask=1,period=2000003,umask=1 00 Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache cycle_activity.cycles_ldm_pending pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=2,period=2000003,umask=2 00 Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem) cycle_activity.cycles_mem_any pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=2,period=2000003,umask=2 00 cycle_activity.cycles_no_execute pipeline This event increments by 1 for every cycle where there was no execute for this thread event=0xa3,cmask=4,period=2000003,umask=4 00 Counts number of cycles nothing is executed on any execution port cycle_activity.stalls_l1d_miss pipeline Execution stalls while L1 cache miss demand load is outstanding event=0xa3,cmask=12,period=2000003,umask=0xc 00 cycle_activity.stalls_l1d_pending pipeline Execution stalls while L1 cache miss demand load is outstanding event=0xa3,cmask=12,period=2000003,umask=0xc 00 Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache cycle_activity.stalls_l2_miss pipeline Execution stalls while L2 cache miss demand load is outstanding event=0xa3,cmask=5,period=2000003,umask=5 00 cycle_activity.stalls_l2_pending pipeline Execution stalls while L2 cache miss demand load is outstanding event=0xa3,cmask=5,period=2000003,umask=5 00 Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands cycle_activity.stalls_ldm_pending pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=6,period=2000003,umask=6 00 Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request cycle_activity.stalls_mem_any pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=6,period=2000003,umask=6 00 cycle_activity.stalls_total pipeline Total execution stalls event=0xa3,cmask=4,period=2000003,umask=4 00 ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction event=0x87,period=2000003,umask=1 00 This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003 00 This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event Spec update: BDM61 event=0xc0,period=2000003 00 This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two) Spec update: BDM61 inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: BDM11, BDM55 (Must be precise) event=0xc0,period=2000003,umask=1 00 This is a precise version (that is, uses PEBS) of the event that counts instructions retired Spec update: BDM11, BDM55 (Must be precise) inst_retired.x87 pipeline FP operations retired. X87 FP operations that have no exceptions: event=0xc0,period=2000003,umask=2 00 This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling int_misc.rat_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread event=0xd,period=2000003,umask=8 00 This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) event=0xd,cmask=1,period=2000003,umask=3 00 Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear int_misc.recovery_cycles_any pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) event=0xd,any=1,cmask=1,period=2000003,umask=3 00 ld_blocks.no_sr pipeline This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=3,period=100003,umask=8 00 ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=3,period=100003,umask=2 00 This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: - preceding store conflicts with the load (incomplete overlap); - store forwarding is impossible due to u-arch limitations; - preceding lock RMW operations are not forwarded; - store has the no-forward bit set (uncacheable/page-split/masked stores); - all-blocking stores are used (mostly, fences and port I/O); and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare event=7,period=100003,umask=1 00 This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased load_hit_pre.hw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for hardware prefetch event=0x4c,period=100003,umask=2 00 This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch load_hit_pre.sw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for software prefetch event=0x4c,period=100003,umask=1 00 This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions lsd.cycles_4_uops pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=4,period=2000003,umask=1 00 lsd.cycles_active pipeline Cycles Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=1,period=2000003,umask=1 00 lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=1 00 machine_clears.count pipeline Number of machine clears (nukes) of any type event=0xc3,cmask=1,edge=1,period=100003,umask=1 00 machine_clears.cycles pipeline Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes event=0xc3,period=2000003,umask=1 00 This event counts both thread-specific (TS) and all-thread (AT) nukes machine_clears.maskmov pipeline This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 event=0xc3,period=100003,umask=0x20 00 Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=4 00 This event counts self-modifying code (SMC) detected, which causes a machine clear move_elimination.int_eliminated pipeline Number of integer Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=1 00 move_elimination.int_not_eliminated pipeline Number of integer Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=4 00 other_assists.any_wb_assist pipeline Number of times any microcode assist is invoked by HW upon uop writeback event=0xc1,period=100003,umask=0x40 00 resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=1 00 This event counts resource-related stall cycles resource_stalls.rob pipeline Cycles stalled due to re-order buffer full event=0xa2,period=2000003,umask=0x10 00 This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end resource_stalls.rs pipeline Cycles stalled due to no eligible RS entry available event=0xa2,period=2000003,umask=4 00 This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=8 00 This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end rob_misc_events.lbr_inserts pipeline Count cases of saving new LBR event=0xcc,period=2000003,umask=0x20 00 This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=1 00 This event counts cycles during which the reservation station (RS) is empty for the thread. Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues event=0x5e,cmask=1,edge=1,inv=1,period=200003,umask=1 00 uops_dispatched_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=1 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=2 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1 uops_dispatched_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=4 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2 uops_dispatched_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=8 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5 uops_dispatched_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6 uops_dispatched_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7 uops_executed.core pipeline Number of uops executed on the core event=0xb1,period=2000003,umask=2 00 Number of uops executed from any thread uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core event=0xb1,cmask=1,period=2000003,umask=2 00 uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core event=0xb1,cmask=2,period=2000003,umask=2 00 uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core event=0xb1,cmask=3,period=2000003,umask=2 00 uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core event=0xb1,cmask=4,period=2000003,umask=2 00 uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core event=0xb1,inv=1,period=2000003,umask=2 00 uops_executed.cycles_ge_1_uop_exec pipeline Cycles where at least 1 uop was executed per-thread event=0xb1,cmask=1,period=2000003,umask=1 00 uops_executed.cycles_ge_2_uops_exec pipeline Cycles where at least 2 uops were executed per-thread event=0xb1,cmask=2,period=2000003,umask=1 00 uops_executed.cycles_ge_3_uops_exec pipeline Cycles where at least 3 uops were executed per-thread event=0xb1,cmask=3,period=2000003,umask=1 00 uops_executed.cycles_ge_4_uops_exec pipeline Cycles where at least 4 uops were executed per-thread event=0xb1,cmask=4,period=2000003,umask=1 00 uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=1 00 This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_executed.thread pipeline Counts the number of uops to be executed per-thread each cycle event=0xb1,period=2000003,umask=1 00 Number of uops to be executed per-thread each cycle uops_executed_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=1 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0 uops_executed_port.port_0_core pipeline Cycles per core when uops are executed in port 0 event=0xa1,any=1,period=2000003,umask=1 00 uops_executed_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=2 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1 uops_executed_port.port_1_core pipeline Cycles per core when uops are executed in port 1 event=0xa1,any=1,period=2000003,umask=2 00 uops_executed_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=4 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2 uops_executed_port.port_2_core pipeline Cycles per core when uops are dispatched to port 2 event=0xa1,any=1,period=2000003,umask=4 00 uops_executed_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=8 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3 uops_executed_port.port_3_core pipeline Cycles per core when uops are dispatched to port 3 event=0xa1,any=1,period=2000003,umask=8 00 uops_executed_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4 uops_executed_port.port_4_core pipeline Cycles per core when uops are executed in port 4 event=0xa1,any=1,period=2000003,umask=0x10 00 uops_executed_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5 uops_executed_port.port_5_core pipeline Cycles per core when uops are executed in port 5 event=0xa1,any=1,period=2000003,umask=0x20 00 uops_executed_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6 uops_executed_port.port_6_core pipeline Cycles per core when uops are executed in port 6 event=0xa1,any=1,period=2000003,umask=0x40 00 uops_executed_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7 uops_executed_port.port_7_core pipeline Cycles per core when uops are dispatched to port 7 event=0xa1,any=1,period=2000003,umask=0x80 00 uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=1 00 This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) uops_issued.flags_merge pipeline Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch event=0xe,period=2000003,umask=0x10 00 Number of flags-merge uops being allocated. Such uops considered perf sensitive added by GSR u-arch uops_issued.single_mul pipeline Number of Multiply packed/scalar single precision uops allocated event=0xe,period=2000003,umask=0x40 00 uops_issued.slow_lea pipeline Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not event=0xe,period=2000003,umask=0x20 00 uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=1 00 This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_retired.all pipeline Actually retired uops (Precise event) event=0xc2,period=2000003,umask=1 00 This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight (Precise event) uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=2 00 This event counts the number of retirement slots used (Precise event) uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=1 00 This event counts cycles without actually retired uops uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=16,inv=1,period=2000003,umask=1 00 Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event unc_cbo_cache_lookup.any_es uncore cache L3 Lookup any request that access cache and found line in E or S-state event=0x34,umask=0x86 01 L3 Lookup any request that access cache and found line in E or S-state unc_cbo_cache_lookup.any_i uncore cache L3 Lookup any request that access cache and found line in I-state event=0x34,umask=0x88 01 L3 Lookup any request that access cache and found line in I-state unc_cbo_cache_lookup.any_m uncore cache L3 Lookup any request that access cache and found line in M-state event=0x34,umask=0x81 01 L3 Lookup any request that access cache and found line in M-state unc_cbo_cache_lookup.any_mesi uncore cache L3 Lookup any request that access cache and found line in MESI-state event=0x34,umask=0x8f 01 L3 Lookup any request that access cache and found line in MESI-state unc_cbo_cache_lookup.read_es uncore cache L3 Lookup read request that access cache and found line in E or S-state event=0x34,umask=0x16 01 L3 Lookup read request that access cache and found line in E or S-state unc_cbo_cache_lookup.read_i uncore cache L3 Lookup read request that access cache and found line in I-state event=0x34,umask=0x18 01 L3 Lookup read request that access cache and found line in I-state unc_cbo_cache_lookup.read_m uncore cache L3 Lookup read request that access cache and found line in M-state event=0x34,umask=0x11 01 L3 Lookup read request that access cache and found line in M-state unc_cbo_cache_lookup.read_mesi uncore cache L3 Lookup read request that access cache and found line in any MESI-state event=0x34,umask=0x1f 01 L3 Lookup read request that access cache and found line in any MESI-state unc_cbo_cache_lookup.write_es uncore cache L3 Lookup write request that access cache and found line in E or S-state event=0x34,umask=0x26 01 L3 Lookup write request that access cache and found line in E or S-state unc_cbo_cache_lookup.write_m uncore cache L3 Lookup write request that access cache and found line in M-state event=0x34,umask=0x21 01 L3 Lookup write request that access cache and found line in M-state unc_cbo_cache_lookup.write_mesi uncore cache L3 Lookup write request that access cache and found line in MESI-state event=0x34,umask=0x2f 01 L3 Lookup write request that access cache and found line in MESI-state unc_cbo_xsnp_response.hitm_xcore uncore cache A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core event=0x22,umask=0x48 01 unc_cbo_xsnp_response.hit_xcore uncore cache A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core event=0x22,umask=0x44 01 unc_cbo_xsnp_response.miss_eviction uncore cache A cross-core snoop resulted from L3 Eviction which misses in some processor core event=0x22,umask=0x81 01 unc_cbo_xsnp_response.miss_xcore uncore cache A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core event=0x22,umask=0x41 01 uncore_cbox_0 unc_clock.socket uncore cache This 48-bit fixed counter counts the UCLK cycles event=0xff 01 This 48-bit fixed counter counts the UCLK cycles unc_arb_coh_trk_requests.all uncore interconnect Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc event=0x84,umask=1 01 unc_arb_trk_occupancy.all uncore interconnect Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic event=0x80,umask=1 01 unc_arb_trk_occupancy.cycles_with_any_request uncore interconnect Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.; event=0x80,cmask=1,umask=1 01 unc_arb_trk_occupancy.drd_direct uncore interconnect Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case event=0x80,umask=2 01 Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case unc_arb_trk_requests.all uncore interconnect Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic event=0x81,umask=1 01 unc_arb_trk_requests.drd_direct uncore interconnect Number of Core coherent Data Read entries allocated in DirectData mode event=0x81,umask=2 01 Number of Core coherent Data Read entries allocated in DirectData mode unc_arb_trk_requests.writes uncore interconnect Number of Writes allocated - any write transactions: full/partials writes and evictions event=0x81,umask=0x20 01 dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks Spec update: BDM69 event=8,period=100003,umask=1 00 This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=8,period=2000003,umask=0x60 00 dtlb_load_misses.stlb_hit_2m virtual memory Load misses that miss the DTLB and hit the STLB (2M) event=8,period=2000003,umask=0x40 00 dtlb_load_misses.stlb_hit_4k virtual memory Load misses that miss the DTLB and hit the STLB (4K) event=8,period=2000003,umask=0x20 00 dtlb_load_misses.walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size Spec update: BDM69 event=8,period=100003,umask=0xe 00 dtlb_load_misses.walk_completed_1g virtual memory Load miss in all TLB levels causes a page walk that completes. (1G) Spec update: BDM69 event=8,period=2000003,umask=8 00 This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_load_misses.walk_completed_2m_4m virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) Spec update: BDM69 event=8,period=2000003,umask=4 00 This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 dtlb_load_misses.walk_completed_4k virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) Spec update: BDM69 event=8,period=2000003,umask=2 00 This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_load_misses.walk_duration virtual memory Cycles when PMH is busy with page walks Spec update: BDM69 event=8,period=2000003,umask=0x10 00 This event counts the number of cycles while PMH is busy with the page walk Spec update: BDM69 dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks Spec update: BDM69 event=0x49,period=100003,umask=1 00 This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 dtlb_store_misses.stlb_hit virtual memory Store operations that miss the first TLB level but hit the second and do not cause page walks event=0x49,period=100003,umask=0x60 00 dtlb_store_misses.stlb_hit_2m virtual memory Store misses that miss the DTLB and hit the STLB (2M) event=0x49,period=100003,umask=0x40 00 dtlb_store_misses.stlb_hit_4k virtual memory Store misses that miss the DTLB and hit the STLB (4K) event=0x49,period=100003,umask=0x20 00 dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks Spec update: BDM69 event=0x49,period=100003,umask=0xe 00 dtlb_store_misses.walk_completed_1g virtual memory Store misses in all DTLB levels that cause completed page walks (1G) Spec update: BDM69 event=0x49,period=100003,umask=8 00 This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.walk_completed_2m_4m virtual memory Store misses in all DTLB levels that cause completed page walks (2M/4M) Spec update: BDM69 event=0x49,period=100003,umask=4 00 This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.walk_completed_4k virtual memory Store miss in all TLB levels causes a page walk that completes. (4K) Spec update: BDM69 event=0x49,period=100003,umask=2 00 This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks Spec update: BDM69 event=0x49,period=100003,umask=0x10 00 This event counts the number of cycles while PMH is busy with the page walk Spec update: BDM69 ept.walk_cycles virtual memory Cycle count for an Extended Page table walk event=0x4f,period=2000003,umask=0x10 00 This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=1 00 This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks Spec update: BDM69 event=0x85,period=100003,umask=1 00 This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x60 00 itlb_misses.stlb_hit_2m virtual memory Code misses that miss the DTLB and hit the STLB (2M) event=0x85,period=100003,umask=0x40 00 itlb_misses.stlb_hit_4k virtual memory Core misses that miss the DTLB and hit the STLB (4K) event=0x85,period=100003,umask=0x20 00 itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks Spec update: BDM69 event=0x85,period=100003,umask=0xe 00 itlb_misses.walk_completed_1g virtual memory Store miss in all TLB levels causes a page walk that completes. (1G) Spec update: BDM69 event=0x85,period=100003,umask=8 00 This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) Spec update: BDM69 event=0x85,period=100003,umask=4 00 This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) Spec update: BDM69 event=0x85,period=100003,umask=2 00 This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks Spec update: BDM69 event=0x85,period=100003,umask=0x10 00 This event counts the number of cycles while PMH is busy with the page walk Spec update: BDM69 page_walker_loads.dtlb_l1 virtual memory Number of DTLB page walker hits in the L1+FB Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x11 00 page_walker_loads.dtlb_l2 virtual memory Number of DTLB page walker hits in the L2 Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x12 00 page_walker_loads.dtlb_l3 virtual memory Number of DTLB page walker hits in the L3 + XSNP Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x14 00 page_walker_loads.dtlb_memory virtual memory Number of DTLB page walker hits in Memory Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x18 00 page_walker_loads.itlb_l1 virtual memory Number of ITLB page walker hits in the L1+FB Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x21 00 page_walker_loads.itlb_l2 virtual memory Number of ITLB page walker hits in the L2 Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x22 00 page_walker_loads.itlb_l3 virtual memory Number of ITLB page walker hits in the L3 + XSNP Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x24 00 tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=1 00 This event counts the number of DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20 00 This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on) mem_load_uops_l3_miss_retired.remote_dram cache Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70 (Precise event) event=0xd3,period=100007,umask=4 00 mem_load_uops_l3_miss_retired.remote_fwd cache Retired load uop whose Data Source was: forwarded from remote cache Supports address when precise. Spec update: BDE70 (Precise event) event=0xd3,period=100007,umask=0x20 00 mem_load_uops_l3_miss_retired.remote_hitm cache Retired load uop whose Data Source was: Remote cache HITM Supports address when precise. Spec update: BDE70 (Precise event) event=0xd3,period=100007,umask=0x10 00 rtm_retired.aborted memory Number of times RTM abort was triggered (Precise event) event=0xc9,period=2000003,umask=4 00 Number of times RTM abort was triggered (Precise event) unc_c_bounce_control uncore cache Bounce Control event=0xa 01 unc_c_clockticks uncore cache Uncore Clocks event=0 01 unc_c_counter0_occupancy uncore cache Counter 0 Occupancy event=0x1f 01 Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry unc_c_fast_asserted uncore cache FaST wire asserted event=9 01 Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn unc_c_llc_lookup.any uncore cache Cache Lookups; Any Request event=0x34,umask=0x11 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_c_llc_lookup.data_read uncore cache Cache Lookups; Data Read Request event=0x34,umask=3 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions unc_c_llc_lookup.nid uncore cache Cache Lookups; Lookups that Match NID event=0x34,umask=0x41 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_llc_lookup.read uncore cache Cache Lookups; Any Read Request event=0x34,umask=0x21 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions unc_c_llc_lookup.remote_snoop uncore cache Cache Lookups; External Snoop Request event=0x34,umask=9 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ unc_c_llc_lookup.write uncore cache Cache Lookups; Write Requests event=0x34,umask=5 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_c_llc_victims.e_state uncore cache Lines Victimized; Lines in E state event=0x37,umask=2 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.f_state uncore cache Lines Victimized event=0x37,umask=8 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.i_state uncore cache Lines Victimized; Lines in S State event=0x37,umask=4 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.miss uncore cache Lines Victimized event=0x37,umask=0x10 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.m_state uncore cache Lines Victimized; Lines in M state event=0x37,umask=1 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.nid uncore cache Lines Victimized; Victimized Lines that Match NID event=0x37,umask=0x40 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_misc.cvzero_prefetch_miss uncore cache Cbo Misc; DRd hitting non-M with raw CV=0 event=0x39,umask=0x20 01 Miscellaneous events in the Cbo unc_c_misc.cvzero_prefetch_victim uncore cache Cbo Misc; Clean Victim with raw CV=0 event=0x39,umask=0x10 01 Miscellaneous events in the Cbo unc_c_misc.rfo_hit_s uncore cache Cbo Misc; RFO HitS event=0x39,umask=8 01 Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB unc_c_misc.rspi_was_fse uncore cache Cbo Misc; Silent Snoop Eviction event=0x39,umask=1 01 Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings unc_c_misc.started uncore cache Cbo Misc event=0x39,umask=4 01 Miscellaneous events in the Cbo unc_c_misc.wc_aliasing uncore cache Cbo Misc; Write Combining Aliasing event=0x39,umask=2 01 Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing unc_c_qlru.age0 uncore cache LRU Queue; LRU Age 0 event=0x3c,umask=1 01 How often age was set to 0 unc_c_qlru.age1 uncore cache LRU Queue; LRU Age 1 event=0x3c,umask=2 01 How often age was set to 1 unc_c_qlru.age2 uncore cache LRU Queue; LRU Age 2 event=0x3c,umask=4 01 How often age was set to 2 unc_c_qlru.age3 uncore cache LRU Queue; LRU Age 3 event=0x3c,umask=8 01 How often age was set to 3 unc_c_qlru.lru_decrement uncore cache LRU Queue; LRU Bits Decremented event=0x3c,umask=0x10 01 How often all LRU bits were decremented by 1 unc_c_qlru.victim_non_zero uncore cache LRU Queue; Non-0 Aged Victim event=0x3c,umask=0x20 01 How often we picked a victim that had a non-zero age unc_c_ring_ad_used.all uncore cache AD Ring In Use; All event=0x1b,umask=0xf 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.ccw uncore cache AD Ring In Use; Down event=0x1b,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.cw uncore cache AD Ring In Use; Up event=0x1b,umask=3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_even uncore cache AD Ring In Use; Down and Even event=0x1b,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ad_used.down_odd uncore cache AD Ring In Use; Down and Odd event=0x1b,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ad_used.up_even uncore cache AD Ring In Use; Up and Even event=0x1b,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ad_used.up_odd uncore cache AD Ring In Use; Up and Odd event=0x1b,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_ak_used.all uncore cache AK Ring In Use; All event=0x1c,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.ccw uncore cache AK Ring In Use; Down event=0x1c,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.cw uncore cache AK Ring In Use; Up event=0x1c,umask=3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_even uncore cache AK Ring In Use; Down and Even event=0x1c,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ak_used.down_odd uncore cache AK Ring In Use; Down and Odd event=0x1c,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ak_used.up_even uncore cache AK Ring In Use; Up and Even event=0x1c,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ak_used.up_odd uncore cache AK Ring In Use; Up and Odd event=0x1c,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_bl_used.all uncore cache BL Ring in Use; Down event=0x1d,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.ccw uncore cache BL Ring in Use; Down event=0x1d,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.cw uncore cache BL Ring in Use; Up event=0x1d,umask=3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_even uncore cache BL Ring in Use; Down and Even event=0x1d,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_bl_used.down_odd uncore cache BL Ring in Use; Down and Odd event=0x1d,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_bl_used.up_even uncore cache BL Ring in Use; Up and Even event=0x1d,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_bl_used.up_odd uncore cache BL Ring in Use; Up and Odd event=0x1d,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_bounces.ad uncore cache Number of LLC responses that bounced on the Ring.; AD event=5,umask=1 01 unc_c_ring_bounces.ak uncore cache Number of LLC responses that bounced on the Ring.; AK event=5,umask=2 01 unc_c_ring_bounces.bl uncore cache Number of LLC responses that bounced on the Ring.; BL event=5,umask=4 01 unc_c_ring_bounces.iv uncore cache Number of LLC responses that bounced on the Ring.; Snoops of processor's cache event=5,umask=0x10 01 unc_c_ring_iv_used.any uncore cache BL Ring in Use; Any event=0x1e,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.dn uncore cache BL Ring in Use; Any event=0x1e,umask=0xc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.down uncore cache BL Ring in Use; Down event=0x1e,umask=0xcc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity unc_c_ring_iv_used.up uncore cache BL Ring in Use; Any event=0x1e,umask=3 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_sink_starved.ad uncore cache AD event=6,umask=1 01 unc_c_ring_sink_starved.ak uncore cache AK event=6,umask=2 01 unc_c_ring_sink_starved.bl uncore cache BL event=6,umask=4 01 unc_c_ring_sink_starved.iv uncore cache IV event=6,umask=8 01 unc_c_ring_src_thrtl uncore cache Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic event=7 01 unc_c_rxr_ext_starved.ipq uncore cache Ingress Arbiter Blocking Cycles; IRQ event=0x12,umask=2 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ unc_c_rxr_ext_starved.irq uncore cache Ingress Arbiter Blocking Cycles; IPQ event=0x12,umask=1 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ unc_c_rxr_ext_starved.ismq_bids uncore cache Ingress Arbiter Blocking Cycles; ISMQ_BID event=0x12,umask=8 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid unc_c_rxr_ext_starved.prq uncore cache Ingress Arbiter Blocking Cycles; PRQ event=0x12,umask=4 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_inserts.ipq uncore cache Ingress Allocations; IPQ event=0x13,umask=4 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.irq uncore cache Ingress Allocations; IRQ event=0x13,umask=1 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.irq_rej uncore cache Ingress Allocations; IRQ Rejected event=0x13,umask=2 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.prq uncore cache Ingress Allocations; PRQ event=0x13,umask=0x10 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.prq_rej uncore cache Ingress Allocations; PRQ event=0x13,umask=0x20 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_int_starved.ipq uncore cache Ingress Internal Starvation Cycles; IPQ event=0x14,umask=4 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation unc_c_rxr_int_starved.irq uncore cache Ingress Internal Starvation Cycles; IRQ event=0x14,umask=1 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation unc_c_rxr_int_starved.ismq uncore cache Ingress Internal Starvation Cycles; ISMQ event=0x14,umask=8 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation unc_c_rxr_int_starved.prq uncore cache Ingress Internal Starvation Cycles; PRQ event=0x14,umask=0x10 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_ipq_retry.addr_conflict uncore cache Probe Queue Retries; Address Conflict event=0x31,umask=4 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics unc_c_rxr_ipq_retry.any uncore cache Probe Queue Retries; Any Reject event=0x31,umask=1 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts unc_c_rxr_ipq_retry.full uncore cache Probe Queue Retries; No Egress Credits event=0x31,umask=2 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits unc_c_rxr_ipq_retry.qpi_credits uncore cache Probe Queue Retries; No QPI Credits event=0x31,umask=0x10 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries unc_c_rxr_ipq_retry2.ad_sbo uncore cache Probe Queue Retries; No AD Sbo Credits event=0x28,umask=1 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo unc_c_rxr_ipq_retry2.target uncore cache Probe Queue Retries; Target Node Filter event=0x28,umask=0x40 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register unc_c_rxr_irq_retry.addr_conflict uncore cache Ingress Request Queue Rejects; Address Conflict event=0x32,umask=4 01 Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled unc_c_rxr_irq_retry.any uncore cache Ingress Request Queue Rejects; Any Reject event=0x32,umask=1 01 Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request unc_c_rxr_irq_retry.full uncore cache Ingress Request Queue Rejects; No Egress Credits event=0x32,umask=2 01 Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried unc_c_rxr_irq_retry.iio_credits uncore cache Ingress Request Queue Rejects; No IIO Credits event=0x32,umask=0x20 01 Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO unc_c_rxr_irq_retry.nid uncore cache Ingress Request Queue Rejects event=0x32,umask=0x40 01 Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid unc_c_rxr_irq_retry.qpi_credits uncore cache Ingress Request Queue Rejects; No QPI Credits event=0x32,umask=0x10 01 Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information unc_c_rxr_irq_retry.rtid uncore cache Ingress Request Queue Rejects; No RTIDs event=0x32,umask=8 01 Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case unc_c_rxr_irq_retry2.ad_sbo uncore cache Ingress Request Queue Rejects; No AD Sbo Credits event=0x29,umask=1 01 Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo unc_c_rxr_irq_retry2.bl_sbo uncore cache Ingress Request Queue Rejects; No BL Sbo Credits event=0x29,umask=2 01 Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo unc_c_rxr_irq_retry2.target uncore cache Ingress Request Queue Rejects; Target Node Filter event=0x29,umask=0x40 01 Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register unc_c_rxr_ismq_retry.any uncore cache ISMQ Retries; Any Reject event=0x33,umask=1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here unc_c_rxr_ismq_retry.full uncore cache ISMQ Retries; No Egress Credits event=0x33,umask=2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried unc_c_rxr_ismq_retry.iio_credits uncore cache ISMQ Retries; No IIO Credits event=0x33,umask=0x20 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO unc_c_rxr_ismq_retry.nid uncore cache ISMQ Retries event=0x33,umask=0x40 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid unc_c_rxr_ismq_retry.qpi_credits uncore cache ISMQ Retries; No QPI Credits event=0x33,umask=0x10 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.rtid uncore cache ISMQ Retries; No RTIDs event=0x33,umask=8 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried unc_c_rxr_ismq_retry.wb_credits uncore cache ISMQ Retries event=0x33,umask=0x80 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid unc_c_rxr_ismq_retry2.ad_sbo uncore cache ISMQ Request Queue Rejects; No AD Sbo Credits event=0x2a,umask=1 01 Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo unc_c_rxr_ismq_retry2.bl_sbo uncore cache ISMQ Request Queue Rejects; No BL Sbo Credits event=0x2a,umask=2 01 Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo unc_c_rxr_ismq_retry2.target uncore cache ISMQ Request Queue Rejects; Target Node Filter event=0x2a,umask=0x40 01 Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register unc_c_rxr_occupancy.ipq uncore cache Ingress Occupancy; IPQ event=0x11,umask=4 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.irq uncore cache Ingress Occupancy; IRQ event=0x11,umask=1 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.irq_rej uncore cache Ingress Occupancy; IRQ Rejected event=0x11,umask=2 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.prq_rej uncore cache Ingress Occupancy; PRQ Rejects event=0x11,umask=0x20 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_sbo_credits_acquired.ad uncore cache SBo Credits Acquired; For AD Ring event=0x3d,umask=1 01 Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with unc_c_sbo_credits_acquired.bl uncore cache SBo Credits Acquired; For BL Ring event=0x3d,umask=2 01 Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with unc_c_sbo_credit_occupancy.ad uncore cache SBo Credits Occupancy; For AD Ring event=0x3e,umask=1 01 Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with unc_c_sbo_credit_occupancy.bl uncore cache SBo Credits Occupancy; For BL Ring event=0x3e,umask=2 01 Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with unc_c_tor_inserts.all uncore cache TOR Inserts; All event=0x35,umask=8 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots unc_c_tor_inserts.eviction uncore cache TOR Inserts; Evictions event=0x35,umask=4 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory) unc_c_tor_inserts.local uncore cache TOR Inserts; Local Memory event=0x35,umask=0x28 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.local_opcode uncore cache TOR Inserts; Local Memory - Opcode Matched event=0x35,umask=0x21 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.miss_local uncore cache TOR Inserts; Misses to Local Memory event=0x35,umask=0x2a 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.miss_local_opcode uncore cache TOR Inserts; Misses to Local Memory - Opcode Matched event=0x35,umask=0x23 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.miss_opcode uncore cache TOR Inserts; Miss Opcode Match event=0x35,umask=3 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode unc_c_tor_inserts.miss_remote uncore cache TOR Inserts; Misses to Remote Memory event=0x35,umask=0x8a 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.miss_remote_opcode uncore cache TOR Inserts; Misses to Remote Memory - Opcode Matched event=0x35,umask=0x83 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.nid_all uncore cache TOR Inserts; NID Matched event=0x35,umask=0x48 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_tor_inserts.nid_eviction uncore cache TOR Inserts; NID Matched Evictions event=0x35,umask=0x44 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR unc_c_tor_inserts.nid_miss_all uncore cache TOR Inserts; NID Matched Miss All event=0x35,umask=0x4a 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR unc_c_tor_inserts.nid_miss_opcode uncore cache TOR Inserts; NID and Opcode Matched Miss event=0x35,umask=0x43 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode unc_c_tor_inserts.nid_opcode uncore cache TOR Inserts; NID and Opcode Matched event=0x35,umask=0x41 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode unc_c_tor_inserts.nid_wb uncore cache TOR Inserts; NID Matched Writebacks event=0x35,umask=0x50 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR unc_c_tor_inserts.opcode uncore cache TOR Inserts; Opcode Match event=0x35,umask=1 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) unc_c_tor_inserts.remote uncore cache TOR Inserts; Remote Memory event=0x35,umask=0x88 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.remote_opcode uncore cache TOR Inserts; Remote Memory - Opcode Matched event=0x35,umask=0x81 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.wb uncore cache TOR Inserts; Writebacks event=0x35,umask=0x10 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core unc_c_tor_occupancy.all uncore cache TOR Occupancy; Any event=0x36,umask=8 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots unc_c_tor_occupancy.eviction uncore cache TOR Occupancy; Evictions event=0x36,umask=4 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory) unc_c_tor_occupancy.local uncore cache TOR Occupancy event=0x36,umask=0x28 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.local_opcode uncore cache TOR Occupancy; Local Memory - Opcode Matched event=0x36,umask=0x21 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory unc_c_tor_occupancy.miss_all uncore cache TOR Occupancy; Miss All event=0x36,umask=0xa 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO unc_c_tor_occupancy.miss_local uncore cache TOR Occupancy event=0x36,umask=0x2a 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_local_opcode uncore cache TOR Occupancy; Misses to Local Memory - Opcode Matched event=0x36,umask=0x23 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory unc_c_tor_occupancy.miss_opcode uncore cache TOR Occupancy; Miss Opcode Match event=0x36,umask=3 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO unc_c_tor_occupancy.miss_remote uncore cache TOR Occupancy event=0x36,umask=0x8a 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_remote_opcode uncore cache TOR Occupancy; Misses to Remote Memory - Opcode Matched event=0x36,umask=0x83 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory unc_c_tor_occupancy.nid_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x48 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_tor_occupancy.nid_eviction uncore cache TOR Occupancy; NID Matched Evictions event=0x36,umask=0x44 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR unc_c_tor_occupancy.nid_miss_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x4a 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID unc_c_tor_occupancy.nid_miss_opcode uncore cache TOR Occupancy; NID and Opcode Matched Miss event=0x36,umask=0x43 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode unc_c_tor_occupancy.nid_opcode uncore cache TOR Occupancy; NID and Opcode Matched event=0x36,umask=0x41 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode unc_c_tor_occupancy.nid_wb uncore cache TOR Occupancy; NID Matched Writebacks event=0x36,umask=0x50 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR unc_c_tor_occupancy.opcode uncore cache TOR Occupancy; Opcode Match event=0x36,umask=1 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) unc_c_tor_occupancy.remote uncore cache TOR Occupancy event=0x36,umask=0x88 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.remote_opcode uncore cache TOR Occupancy; Remote Memory - Opcode Matched event=0x36,umask=0x81 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory unc_c_tor_occupancy.wb uncore cache TOR Occupancy; Writebacks event=0x36,umask=0x10 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include RFO, but actual operations that contain data being sent from the core unc_c_txr_ads_used.ad uncore cache Onto AD Ring event=4,umask=1 01 unc_c_txr_ads_used.ak uncore cache Onto AK Ring event=4,umask=2 01 unc_c_txr_ads_used.bl uncore cache Onto BL Ring event=4,umask=4 01 unc_c_txr_inserts.ad_cache uncore cache Egress Allocations; AD - Cachebo event=2,umask=1 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_c_txr_inserts.ad_core uncore cache Egress Allocations; AD - Corebo event=2,umask=0x10 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests unc_c_txr_inserts.ak_cache uncore cache Egress Allocations; AK - Cachebo event=2,umask=2 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses unc_c_txr_inserts.ak_core uncore cache Egress Allocations; AK - Corebo event=2,umask=0x20 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo unc_c_txr_inserts.bl_cache uncore cache Egress Allocations; BL - Cacheno event=2,umask=4 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_c_txr_inserts.bl_core uncore cache Egress Allocations; BL - Corebo event=2,umask=0x40 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_c_txr_inserts.iv_cache uncore cache Egress Allocations; IV - Cachebo event=2,umask=8 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores unc_c_txr_starved.ad_core uncore cache Injection Starvation; Onto AD Ring (to core) event=3,umask=0x10 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation unc_c_txr_starved.ak_both uncore cache Injection Starvation; Onto AK Ring event=3,umask=2 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation unc_c_txr_starved.bl_both uncore cache Injection Starvation; Onto BL Ring event=3,umask=4 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation unc_c_txr_starved.iv uncore cache Injection Starvation; Onto IV Ring event=3,umask=8 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation uncore_ha unc_h_bt_cycles_ne uncore cache BT Cycles Not Empty event=0x42 01 Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT unc_h_bt_to_ht_not_issued.incoming_bl_hazard uncore cache BT to HT Not Issued; Incoming Data Hazard event=0x51,umask=4 01 Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard unc_h_bt_to_ht_not_issued.incoming_snp_hazard uncore cache BT to HT Not Issued; Incoming Snoop Hazard event=0x51,umask=2 01 Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard unc_h_bt_to_ht_not_issued.rspackcflt_hazard uncore cache BT to HT Not Issued; Incoming Data Hazard event=0x51,umask=8 01 Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard unc_h_bt_to_ht_not_issued.wbmdata_hazard uncore cache BT to HT Not Issued; Incoming Data Hazard event=0x51,umask=0x10 01 Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard unc_h_bypass_imc.not_taken uncore cache HA to iMC Bypass; Not Taken event=0x14,umask=2 01 Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass unc_h_bypass_imc.taken uncore cache HA to iMC Bypass; Taken event=0x14,umask=1 01 Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass unc_h_clockticks uncore cache uclks event=0 01 Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent unc_h_direct2core_count uncore cache Direct2Core Messages Sent event=0x11 01 Number of Direct2Core messages sent unc_h_direct2core_cycles_disabled uncore cache Cycles when Direct2Core was Disabled event=0x12 01 Number of cycles in which Direct2Core was disabled unc_h_direct2core_txn_override uncore cache Number of Reads that had Direct2Core Overridden event=0x13 01 Number of Reads where Direct2Core overridden unc_h_directory_lat_opt uncore cache Directory Lat Opt Return event=0x41 01 Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc) unc_h_directory_lookup.no_snp uncore cache Directory Lookups; Snoop Not Needed event=0xc,umask=2 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear unc_h_directory_lookup.snp uncore cache Directory Lookups; Snoop Needed event=0xc,umask=1 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set unc_h_directory_update.any uncore cache Directory Updates; Any Directory Update event=0xd,umask=3 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.clear uncore cache Directory Updates; Directory Clear event=0xd,umask=2 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory clears. This occurs when snoops were sent and all returned with RspI unc_h_directory_update.set uncore cache Directory Updates; Directory Set event=0xd,umask=1 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory sets. This occurs when a remote read transaction requests memory, bringing it to a remote cache unc_h_hitme_hit.ackcnfltwbi uncore cache Counts Number of Hits in HitMe Cache; op is AckCnfltWbI event=0x71,umask=4 01 unc_h_hitme_hit.all uncore cache Counts Number of Hits in HitMe Cache; All Requests event=0x71,umask=0xff 01 unc_h_hitme_hit.allocs uncore cache Counts Number of Hits in HitMe Cache; Allocations event=0x71,umask=0x70 01 unc_h_hitme_hit.evicts uncore cache Counts Number of Hits in HitMe Cache; Allocations event=0x71,umask=0x42 01 unc_h_hitme_hit.hom uncore cache Counts Number of Hits in HitMe Cache; HOM Requests event=0x71,umask=0xf 01 unc_h_hitme_hit.invals uncore cache Counts Number of Hits in HitMe Cache; Invalidations event=0x71,umask=0x26 01 unc_h_hitme_hit.read_or_invitoe uncore cache Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE event=0x71,umask=1 01 unc_h_hitme_hit.rsp uncore cache Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI event=0x71,umask=0x80 01 unc_h_hitme_hit.rspfwdi_local uncore cache Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request event=0x71,umask=0x20 01 unc_h_hitme_hit.rspfwdi_remote uncore cache Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request event=0x71,umask=0x10 01 unc_h_hitme_hit.rspfwds uncore cache Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb event=0x71,umask=0x40 01 unc_h_hitme_hit.wbmtoe_or_s uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS event=0x71,umask=8 01 unc_h_hitme_hit.wbmtoi uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoI event=0x71,umask=2 01 unc_h_hitme_hit_pv_bits_set.ackcnfltwbi uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI event=0x72,umask=4 01 unc_h_hitme_hit_pv_bits_set.all uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; All Requests event=0x72,umask=0xff 01 unc_h_hitme_hit_pv_bits_set.hom uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests event=0x72,umask=0xf 01 unc_h_hitme_hit_pv_bits_set.read_or_invitoe uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE event=0x72,umask=1 01 unc_h_hitme_hit_pv_bits_set.rsp uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI event=0x72,umask=0x80 01 unc_h_hitme_hit_pv_bits_set.rspfwdi_local uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request event=0x72,umask=0x20 01 unc_h_hitme_hit_pv_bits_set.rspfwdi_remote uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request event=0x72,umask=0x10 01 unc_h_hitme_hit_pv_bits_set.rspfwds uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb event=0x72,umask=0x40 01 unc_h_hitme_hit_pv_bits_set.wbmtoe_or_s uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS event=0x72,umask=8 01 unc_h_hitme_hit_pv_bits_set.wbmtoi uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI event=0x72,umask=2 01 unc_h_hitme_lookup.ackcnfltwbi uncore cache Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI event=0x70,umask=4 01 unc_h_hitme_lookup.all uncore cache Counts Number of times HitMe Cache is accessed; All Requests event=0x70,umask=0xff 01 unc_h_hitme_lookup.allocs uncore cache Counts Number of times HitMe Cache is accessed; Allocations event=0x70,umask=0x70 01 unc_h_hitme_lookup.hom uncore cache Counts Number of times HitMe Cache is accessed; HOM Requests event=0x70,umask=0xf 01 unc_h_hitme_lookup.invals uncore cache Counts Number of times HitMe Cache is accessed; Invalidations event=0x70,umask=0x26 01 unc_h_hitme_lookup.read_or_invitoe uncore cache Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE event=0x70,umask=1 01 unc_h_hitme_lookup.rsp uncore cache Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI event=0x70,umask=0x80 01 unc_h_hitme_lookup.rspfwdi_local uncore cache Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request event=0x70,umask=0x20 01 unc_h_hitme_lookup.rspfwdi_remote uncore cache Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request event=0x70,umask=0x10 01 unc_h_hitme_lookup.rspfwds uncore cache Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb event=0x70,umask=0x40 01 unc_h_hitme_lookup.wbmtoe_or_s uncore cache Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS event=0x70,umask=8 01 unc_h_hitme_lookup.wbmtoi uncore cache Counts Number of times HitMe Cache is accessed; op is WbMtoI event=0x70,umask=2 01 unc_h_igr_no_credit_cycles.ad_qpi0 uncore cache Cycles without QPI Ingress Credits; AD to QPI Link 0 event=0x22,umask=1 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.ad_qpi1 uncore cache Cycles without QPI Ingress Credits; AD to QPI Link 1 event=0x22,umask=2 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.ad_qpi2 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 0 event=0x22,umask=0x10 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.bl_qpi0 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 0 event=0x22,umask=4 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.bl_qpi1 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 1 event=0x22,umask=8 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.bl_qpi2 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 1 event=0x22,umask=0x20 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_imc_reads.normal uncore cache HA to iMC Normal Priority Reads Issued; Normal Priority event=0x17,umask=1 01 Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads unc_h_imc_retry uncore cache Retry Events event=0x1e 01 unc_h_imc_writes.all uncore cache HA to iMC Full Line Writes Issued; All Writes event=0x1a,umask=0xf 01 Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.full uncore cache HA to iMC Full Line Writes Issued; Full Line Non-ISOCH event=0x1a,umask=1 01 Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.full_isoch uncore cache HA to iMC Full Line Writes Issued; ISOCH Full Line event=0x1a,umask=4 01 Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.partial uncore cache HA to iMC Full Line Writes Issued; Partial Non-ISOCH event=0x1a,umask=2 01 Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.partial_isoch uncore cache HA to iMC Full Line Writes Issued; ISOCH Partial event=0x1a,umask=8 01 Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_iot_backpressure.hub uncore cache IOT Backpressure event=0x61,umask=2 01 unc_h_iot_backpressure.sat uncore cache IOT Backpressure event=0x61,umask=1 01 unc_h_iot_cts_east_lo.cts0 uncore cache IOT Common Trigger Sequencer - Lo event=0x64,umask=1 01 Debug Mask/Match Tie-Ins unc_h_iot_cts_east_lo.cts1 uncore cache IOT Common Trigger Sequencer - Lo event=0x64,umask=2 01 Debug Mask/Match Tie-Ins unc_h_iot_cts_hi.cts2 uncore cache IOT Common Trigger Sequencer - Hi event=0x65,umask=1 01 Debug Mask/Match Tie-Ins unc_h_iot_cts_hi.cts3 uncore cache IOT Common Trigger Sequencer - Hi event=0x65,umask=2 01 Debug Mask/Match Tie-Ins unc_h_iot_cts_west_lo.cts0 uncore cache IOT Common Trigger Sequencer - Lo event=0x62,umask=1 01 Debug Mask/Match Tie-Ins unc_h_iot_cts_west_lo.cts1 uncore cache IOT Common Trigger Sequencer - Lo event=0x62,umask=2 01 Debug Mask/Match Tie-Ins unc_h_osb.cancelled uncore cache OSB Snoop Broadcast; Cancelled event=0x53,umask=0x10 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring unc_h_osb.invitoe_local uncore cache OSB Snoop Broadcast; Local InvItoE event=0x53,umask=4 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.reads_local uncore cache OSB Snoop Broadcast; Local Reads event=0x53,umask=2 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.reads_local_useful uncore cache OSB Snoop Broadcast; Reads Local - Useful event=0x53,umask=0x20 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.remote uncore cache OSB Snoop Broadcast; Remote event=0x53,umask=8 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.remote_useful uncore cache OSB Snoop Broadcast; Remote - Useful event=0x53,umask=0x40 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb_edr.all uncore cache OSB Early Data Return; All event=0x54,umask=1 01 Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_local_i uncore cache OSB Early Data Return; Reads to Local I event=0x54,umask=2 01 Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_local_s uncore cache OSB Early Data Return; Reads to Local S event=0x54,umask=8 01 Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_remote_i uncore cache OSB Early Data Return; Reads to Remote I event=0x54,umask=4 01 Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_remote_s uncore cache OSB Early Data Return; Reads to Remote S event=0x54,umask=0x10 01 Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_requests.invitoe_local uncore cache Read and Write Requests; Local InvItoEs event=1,umask=0x10 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket unc_h_requests.invitoe_remote uncore cache Read and Write Requests; Remote InvItoEs event=1,umask=0x20 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets unc_h_requests.reads uncore cache Read and Write Requests; Reads event=1,umask=3 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests. This is a good proxy for LLC Read Misses (including RFOs) unc_h_requests.reads_local uncore cache Read and Write Requests; Local Reads event=1,umask=1 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket. This is a good proxy for LLC Read Misses (including RFOs) from the local socket unc_h_requests.reads_remote uncore cache Read and Write Requests; Remote Reads event=1,umask=2 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket. This is a good proxy for LLC Read Misses (including RFOs) from the remote socket unc_h_requests.writes uncore cache Read and Write Requests; Writes event=1,umask=0xc 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests unc_h_requests.writes_local uncore cache Read and Write Requests; Local Writes event=1,umask=4 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket unc_h_requests.writes_remote uncore cache Read and Write Requests; Remote Writes event=1,umask=8 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets unc_h_ring_ad_used.ccw uncore cache HA AD Ring in Use; Counterclockwise event=0x3e,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.ccw_even uncore cache HA AD Ring in Use; Counterclockwise and Even event=0x3e,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_h_ring_ad_used.ccw_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd event=0x3e,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_h_ring_ad_used.cw uncore cache HA AD Ring in Use; Clockwise event=0x3e,umask=3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_even uncore cache HA AD Ring in Use; Clockwise and Even event=0x3e,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_h_ring_ad_used.cw_odd uncore cache HA AD Ring in Use; Clockwise and Odd event=0x3e,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_h_ring_ak_used.all uncore cache HA AK Ring in Use; All event=0x3f,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw uncore cache HA AK Ring in Use; Counterclockwise event=0x3f,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_even uncore cache HA AK Ring in Use; Counterclockwise and Even event=0x3f,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_h_ring_ak_used.ccw_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd event=0x3f,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_h_ring_ak_used.cw uncore cache HA AK Ring in Use; Clockwise event=0x3f,umask=3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_even uncore cache HA AK Ring in Use; Clockwise and Even event=0x3f,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_h_ring_ak_used.cw_odd uncore cache HA AK Ring in Use; Clockwise and Odd event=0x3f,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_h_ring_bl_used.all uncore cache HA BL Ring in Use; All event=0x40,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw uncore cache HA BL Ring in Use; Counterclockwise event=0x40,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_even uncore cache HA BL Ring in Use; Counterclockwise and Even event=0x40,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_h_ring_bl_used.ccw_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd event=0x40,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_h_ring_bl_used.cw uncore cache HA BL Ring in Use; Clockwise event=0x40,umask=3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_even uncore cache HA BL Ring in Use; Clockwise and Even event=0x40,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_h_ring_bl_used.cw_odd uncore cache HA BL Ring in Use; Clockwise and Odd event=0x40,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_h_rpq_cycles_no_reg_credits.chn0 uncore cache iMC RPQ Credits Empty - Regular; Channel 0 event=0x15,umask=1 01 Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_rpq_cycles_no_reg_credits.chn1 uncore cache iMC RPQ Credits Empty - Regular; Channel 1 event=0x15,umask=2 01 Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_rpq_cycles_no_reg_credits.chn2 uncore cache iMC RPQ Credits Empty - Regular; Channel 2 event=0x15,umask=4 01 Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_rpq_cycles_no_reg_credits.chn3 uncore cache iMC RPQ Credits Empty - Regular; Channel 3 event=0x15,umask=8 01 Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_h_rpq_cycles_no_spec_credits.chn0 uncore cache iMC RPQ Credits Empty - Special; Channel 0 event=0x16,umask=1 01 Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_rpq_cycles_no_spec_credits.chn1 uncore cache iMC RPQ Credits Empty - Special; Channel 1 event=0x16,umask=2 01 Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_rpq_cycles_no_spec_credits.chn2 uncore cache iMC RPQ Credits Empty - Special; Channel 2 event=0x16,umask=4 01 Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_rpq_cycles_no_spec_credits.chn3 uncore cache iMC RPQ Credits Empty - Special; Channel 3 event=0x16,umask=8 01 Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_h_sbo0_credits_acquired.ad uncore cache SBo0 Credits Acquired; For AD Ring event=0x68,umask=1 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_h_sbo0_credits_acquired.bl uncore cache SBo0 Credits Acquired; For BL Ring event=0x68,umask=2 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_h_sbo0_credit_occupancy.ad uncore cache SBo0 Credits Occupancy; For AD Ring event=0x6a,umask=1 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_h_sbo0_credit_occupancy.bl uncore cache SBo0 Credits Occupancy; For BL Ring event=0x6a,umask=2 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_h_sbo1_credits_acquired.ad uncore cache SBo1 Credits Acquired; For AD Ring event=0x69,umask=1 01 Number of Sbo 1 credits acquired in a given cycle, per ring unc_h_sbo1_credits_acquired.bl uncore cache SBo1 Credits Acquired; For BL Ring event=0x69,umask=2 01 Number of Sbo 1 credits acquired in a given cycle, per ring unc_h_sbo1_credit_occupancy.ad uncore cache SBo1 Credits Occupancy; For AD Ring event=0x6b,umask=1 01 Number of Sbo 1 credits in use in a given cycle, per ring unc_h_sbo1_credit_occupancy.bl uncore cache SBo1 Credits Occupancy; For BL Ring event=0x6b,umask=2 01 Number of Sbo 1 credits in use in a given cycle, per ring unc_h_snoops_rsp_after_data.local uncore cache Data beat the Snoop Responses; Local Requests event=0xa,umask=1 01 Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket unc_h_snoops_rsp_after_data.remote uncore cache Data beat the Snoop Responses; Remote Requests event=0xa,umask=2 01 Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets unc_h_snoop_cycles_ne.all uncore cache Cycles with Snoops Outstanding; All Requests event=8,umask=3 01 Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets unc_h_snoop_cycles_ne.local uncore cache Cycles with Snoops Outstanding; Local Requests event=8,umask=1 01 Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket unc_h_snoop_cycles_ne.remote uncore cache Cycles with Snoops Outstanding; Remote Requests event=8,umask=2 01 Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets unc_h_snoop_occupancy.local uncore cache Tracker Snoops Outstanding Accumulator; Local Requests event=9,umask=1 01 Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket unc_h_snoop_occupancy.remote uncore cache Tracker Snoops Outstanding Accumulator; Remote Requests event=9,umask=2 01 Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets unc_h_snoop_resp.rspcnflct uncore cache Snoop Responses Received; RSPCNFLCT* event=0x21,umask=0x40 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI unc_h_snoop_resp.rspi uncore cache Snoop Responses Received; RspI event=0x21,umask=1 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_h_snoop_resp.rspifwd uncore cache Snoop Responses Received; RspIFwd event=0x21,umask=4 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE unc_h_snoop_resp.rsps uncore cache Snoop Responses Received; RspS event=0x21,umask=2 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_h_snoop_resp.rspsfwd uncore cache Snoop Responses Received; RspSFwd event=0x21,umask=8 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state unc_h_snoop_resp.rsp_fwd_wb uncore cache Snoop Responses Received; Rsp*Fwd*WB event=0x21,umask=0x20 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_h_snoop_resp.rsp_wb uncore cache Snoop Responses Received; Rsp*WB event=0x21,umask=0x10 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership unc_h_snp_resp_recv_local.other uncore cache Snoop Responses Received Local; Other event=0x60,umask=0x80 01 Number of snoop responses received for a Local request; Filters for all other snoop responses unc_h_snp_resp_recv_local.rspcnflct uncore cache Snoop Responses Received Local; RspCnflct event=0x60,umask=0x40 01 Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI unc_h_snp_resp_recv_local.rspi uncore cache Snoop Responses Received Local; RspI event=0x60,umask=1 01 Number of snoop responses received for a Local request; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_h_snp_resp_recv_local.rspifwd uncore cache Snoop Responses Received Local; RspIFwd event=0x60,umask=4 01 Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE unc_h_snp_resp_recv_local.rsps uncore cache Snoop Responses Received Local; RspS event=0x60,umask=2 01 Number of snoop responses received for a Local request; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_h_snp_resp_recv_local.rspsfwd uncore cache Snoop Responses Received Local; RspSFwd event=0x60,umask=8 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state unc_h_snp_resp_recv_local.rspxfwdxwb uncore cache Snoop Responses Received Local; Rsp*FWD*WB event=0x60,umask=0x20 01 Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_h_snp_resp_recv_local.rspxwb uncore cache Snoop Responses Received Local; Rsp*WB event=0x60,umask=0x10 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership unc_h_stall_no_sbo_credit.sbo0_ad uncore cache Stall on No Sbo Credits; For SBo0, AD Ring event=0x6c,umask=1 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_h_stall_no_sbo_credit.sbo0_bl uncore cache Stall on No Sbo Credits; For SBo0, BL Ring event=0x6c,umask=4 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_h_stall_no_sbo_credit.sbo1_ad uncore cache Stall on No Sbo Credits; For SBo1, AD Ring event=0x6c,umask=2 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_h_stall_no_sbo_credit.sbo1_bl uncore cache Stall on No Sbo Credits; For SBo1, BL Ring event=0x6c,umask=8 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_h_tad_requests_g0.region0 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 0 event=0x1b,umask=1 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0 unc_h_tad_requests_g0.region1 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 1 event=0x1b,umask=2 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1 unc_h_tad_requests_g0.region2 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 2 event=0x1b,umask=4 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2 unc_h_tad_requests_g0.region3 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 3 event=0x1b,umask=8 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3 unc_h_tad_requests_g0.region4 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 4 event=0x1b,umask=0x10 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4 unc_h_tad_requests_g0.region5 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 5 event=0x1b,umask=0x20 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5 unc_h_tad_requests_g0.region6 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 6 event=0x1b,umask=0x40 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6 unc_h_tad_requests_g0.region7 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 7 event=0x1b,umask=0x80 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7 unc_h_tad_requests_g1.region10 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 10 event=0x1c,umask=4 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10 unc_h_tad_requests_g1.region11 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 11 event=0x1c,umask=8 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11 unc_h_tad_requests_g1.region8 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 8 event=0x1c,umask=1 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8 unc_h_tad_requests_g1.region9 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 9 event=0x1c,umask=2 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9 unc_h_tracker_cycles_full.all uncore cache Tracker Cycles Full; Cycles Completely Used event=2,umask=2 01 Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries. It will not return valid count when BT is disabled unc_h_tracker_cycles_full.gp uncore cache Tracker Cycles Full; Cycles GP Completely Used event=2,umask=1 01 Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used. It will not return valid count when BT is disabled unc_h_tracker_cycles_ne.all uncore cache Tracker Cycles Not Empty; All Requests event=3,umask=3 01 Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets unc_h_tracker_cycles_ne.local uncore cache Tracker Cycles Not Empty; Local Requests event=3,umask=1 01 Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket unc_h_tracker_cycles_ne.remote uncore cache Tracker Cycles Not Empty; Remote Requests event=3,umask=2 01 Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets unc_h_tracker_occupancy.invitoe_local uncore cache Tracker Occupancy Accumulator; Local InvItoE Requests event=4,umask=0x40 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.invitoe_remote uncore cache Tracker Occupancy Accumulator; Remote InvItoE Requests event=4,umask=0x80 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.reads_local uncore cache Tracker Occupancy Accumulator; Local Read Requests event=4,umask=4 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.reads_remote uncore cache Tracker Occupancy Accumulator; Remote Read Requests event=4,umask=8 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.writes_local uncore cache Tracker Occupancy Accumulator; Local Write Requests event=4,umask=0x10 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.writes_remote uncore cache Tracker Occupancy Accumulator; Remote Write Requests event=4,umask=0x20 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_pending_occupancy.local uncore cache Data Pending Occupancy Accumulator; Local Requests event=5,umask=1 01 Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket unc_h_tracker_pending_occupancy.remote uncore cache Data Pending Occupancy Accumulator; Remote Requests event=5,umask=2 01 Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets unc_h_txr_ad.hom uncore cache Outbound NDR Ring Transactions; Non-data Responses event=0xf,umask=4 01 Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring. NDR stands for non-data response and is generally used for completions that do not include data. AD NDR is used for transactions to remote sockets unc_h_txr_ad_cycles_full.all uncore cache AD Egress Full; All event=0x2a,umask=3 01 AD Egress Full; Cycles full from both schedulers unc_h_txr_ad_cycles_full.sched0 uncore cache AD Egress Full; Scheduler 0 event=0x2a,umask=1 01 AD Egress Full; Filter for cycles full from scheduler bank 0 unc_h_txr_ad_cycles_full.sched1 uncore cache AD Egress Full; Scheduler 1 event=0x2a,umask=2 01 AD Egress Full; Filter for cycles full from scheduler bank 1 unc_h_txr_ad_cycles_ne.all uncore cache AD Egress Not Empty; All event=0x29,umask=3 01 AD Egress Not Empty; Cycles full from both schedulers unc_h_txr_ad_cycles_ne.sched0 uncore cache AD Egress Not Empty; Scheduler 0 event=0x29,umask=1 01 AD Egress Not Empty; Filter for cycles not empty from scheduler bank 0 unc_h_txr_ad_cycles_ne.sched1 uncore cache AD Egress Not Empty; Scheduler 1 event=0x29,umask=2 01 AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1 unc_h_txr_ad_inserts.all uncore cache AD Egress Allocations; All event=0x27,umask=3 01 AD Egress Allocations; Allocations from both schedulers unc_h_txr_ad_inserts.sched0 uncore cache AD Egress Allocations; Scheduler 0 event=0x27,umask=1 01 AD Egress Allocations; Filter for allocations from scheduler bank 0 unc_h_txr_ad_inserts.sched1 uncore cache AD Egress Allocations; Scheduler 1 event=0x27,umask=2 01 AD Egress Allocations; Filter for allocations from scheduler bank 1 unc_h_txr_ak_cycles_full.all uncore cache AK Egress Full; All event=0x32,umask=3 01 AK Egress Full; Cycles full from both schedulers unc_h_txr_ak_cycles_full.sched0 uncore cache AK Egress Full; Scheduler 0 event=0x32,umask=1 01 AK Egress Full; Filter for cycles full from scheduler bank 0 unc_h_txr_ak_cycles_full.sched1 uncore cache AK Egress Full; Scheduler 1 event=0x32,umask=2 01 AK Egress Full; Filter for cycles full from scheduler bank 1 unc_h_txr_ak_cycles_ne.all uncore cache AK Egress Not Empty; All event=0x31,umask=3 01 AK Egress Not Empty; Cycles full from both schedulers unc_h_txr_ak_cycles_ne.sched0 uncore cache AK Egress Not Empty; Scheduler 0 event=0x31,umask=1 01 AK Egress Not Empty; Filter for cycles not empty from scheduler bank 0 unc_h_txr_ak_cycles_ne.sched1 uncore cache AK Egress Not Empty; Scheduler 1 event=0x31,umask=2 01 AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1 unc_h_txr_ak_inserts.all uncore cache AK Egress Allocations; All event=0x2f,umask=3 01 AK Egress Allocations; Allocations from both schedulers unc_h_txr_ak_inserts.sched0 uncore cache AK Egress Allocations; Scheduler 0 event=0x2f,umask=1 01 AK Egress Allocations; Filter for allocations from scheduler bank 0 unc_h_txr_ak_inserts.sched1 uncore cache AK Egress Allocations; Scheduler 1 event=0x2f,umask=2 01 AK Egress Allocations; Filter for allocations from scheduler bank 1 unc_h_txr_bl.drs_cache uncore cache Outbound DRS Ring Transactions to Cache; Data to Cache event=0x10,umask=1 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to the cache unc_h_txr_bl.drs_core uncore cache Outbound DRS Ring Transactions to Cache; Data to Core event=0x10,umask=2 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent directly to the requesting core unc_h_txr_bl.drs_qpi uncore cache Outbound DRS Ring Transactions to Cache; Data to QPI event=0x10,umask=4 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI unc_h_txr_bl_cycles_full.all uncore cache BL Egress Full; All event=0x36,umask=3 01 BL Egress Full; Cycles full from both schedulers unc_h_txr_bl_cycles_full.sched0 uncore cache BL Egress Full; Scheduler 0 event=0x36,umask=1 01 BL Egress Full; Filter for cycles full from scheduler bank 0 unc_h_txr_bl_cycles_full.sched1 uncore cache BL Egress Full; Scheduler 1 event=0x36,umask=2 01 BL Egress Full; Filter for cycles full from scheduler bank 1 unc_h_txr_bl_cycles_ne.all uncore cache BL Egress Not Empty; All event=0x35,umask=3 01 BL Egress Not Empty; Cycles full from both schedulers unc_h_txr_bl_cycles_ne.sched0 uncore cache BL Egress Not Empty; Scheduler 0 event=0x35,umask=1 01 BL Egress Not Empty; Filter for cycles not empty from scheduler bank 0 unc_h_txr_bl_cycles_ne.sched1 uncore cache BL Egress Not Empty; Scheduler 1 event=0x35,umask=2 01 BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1 unc_h_txr_bl_inserts.all uncore cache BL Egress Allocations; All event=0x33,umask=3 01 BL Egress Allocations; Allocations from both schedulers unc_h_txr_bl_inserts.sched0 uncore cache BL Egress Allocations; Scheduler 0 event=0x33,umask=1 01 BL Egress Allocations; Filter for allocations from scheduler bank 0 unc_h_txr_bl_inserts.sched1 uncore cache BL Egress Allocations; Scheduler 1 event=0x33,umask=2 01 BL Egress Allocations; Filter for allocations from scheduler bank 1 unc_h_txr_starved.ak uncore cache Injection Starvation; For AK Ring event=0x6d,umask=1 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_h_txr_starved.bl uncore cache Injection Starvation; For BL Ring event=0x6d,umask=2 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_h_wpq_cycles_no_reg_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0 event=0x18,umask=1 01 Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_wpq_cycles_no_reg_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1 event=0x18,umask=2 01 Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_wpq_cycles_no_reg_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2 event=0x18,umask=4 01 Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_wpq_cycles_no_reg_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3 event=0x18,umask=8 01 Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_h_wpq_cycles_no_spec_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 0 event=0x19,umask=1 01 Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_wpq_cycles_no_spec_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 1 event=0x19,umask=2 01 Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_wpq_cycles_no_spec_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 2 event=0x19,umask=4 01 Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_wpq_cycles_no_spec_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 3 event=0x19,umask=8 01 Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only uncore_irp unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy; Any Source event=0x12,umask=1 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port unc_i_cache_total_occupancy.source uncore interconnect Total Write Cache Occupancy; Select Source event=0x12,umask=2 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time unc_i_clockticks uncore interconnect Clocks in the IRP event=0 01 Number of clocks in the IRP unc_i_coherent_ops.clflush uncore interconnect Coherent Ops; CLFlush event=0x13,umask=0x80 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.crd uncore interconnect Coherent Ops; CRd event=0x13,umask=2 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.drd uncore interconnect Coherent Ops; DRd event=0x13,umask=4 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.pcidcahint uncore interconnect Coherent Ops; PCIDCAHin5t event=0x13,umask=0x20 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.pcirdcur uncore interconnect Coherent Ops; PCIRdCur event=0x13,umask=1 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.pcitom uncore interconnect Coherent Ops; PCIItoM event=0x13,umask=0x10 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.rfo uncore interconnect Coherent Ops; RFO event=0x13,umask=8 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.wbmtoi uncore interconnect Coherent Ops; WbMtoI event=0x13,umask=0x40 01 Counts the number of coherency related operations servied by the IRP unc_i_misc0.2nd_atomic_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary event=0x14,umask=0x10 01 Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary unc_i_misc0.2nd_rd_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary event=0x14,umask=4 01 Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary unc_i_misc0.2nd_wr_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary event=0x14,umask=8 01 Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary unc_i_misc0.fast_rej uncore interconnect Misc Events - Set 0; Fastpath Rejects event=0x14,umask=2 01 Counts Timeouts - Set 0 : Fastpath Rejects unc_i_misc0.fast_req uncore interconnect Misc Events - Set 0; Fastpath Requests event=0x14,umask=1 01 Counts Timeouts - Set 0 : Fastpath Requests unc_i_misc0.fast_xfer uncore interconnect Misc Events - Set 0; Fastpath Transfers From Primary to Secondary event=0x14,umask=0x20 01 Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary unc_i_misc0.pf_ack_hint uncore interconnect Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary event=0x14,umask=0x40 01 Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary unc_i_misc0.pf_timeout uncore interconnect Misc Events - Set 0; Prefetch TimeOut event=0x14,umask=0x80 01 Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut unc_i_misc1.data_throttle uncore interconnect Misc Events - Set 1; Data Throttled event=0x15,umask=0x80 01 IRP throttled switch data unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1 event=0x15,umask=0x10 01 Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed unc_i_misc1.sec_rcvd_invld uncore interconnect Misc Events - Set 1; Received Invalid event=0x15,umask=0x20 01 Secondary received a transfer that did not have sufficient MESI state unc_i_misc1.sec_rcvd_vld uncore interconnect Misc Events - Set 1; Received Valid event=0x15,umask=0x40 01 Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_e uncore interconnect Misc Events - Set 1; Slow Transfer of E Line event=0x15,umask=4 01 Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_i uncore interconnect Misc Events - Set 1; Slow Transfer of I Line event=0x15,umask=1 01 Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_m uncore interconnect Misc Events - Set 1; Slow Transfer of M Line event=0x15,umask=8 01 Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_s uncore interconnect Misc Events - Set 1; Slow Transfer of S Line event=0x15,umask=2 01 Secondary received a transfer that did not have sufficient MESI state unc_i_rxr_ak_inserts uncore interconnect AK Ingress Occupancy event=0xa 01 Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring) unc_i_rxr_bl_drs_cycles_full uncore interconnect UNC_I_RxR_BL_DRS_CYCLES_FULL event=4 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_drs_inserts uncore interconnect BL Ingress Occupancy - DRS event=1 01 Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_drs_occupancy uncore interconnect UNC_I_RxR_BL_DRS_OCCUPANCY event=7 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_cycles_full uncore interconnect UNC_I_RxR_BL_NCB_CYCLES_FULL event=5 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_inserts uncore interconnect BL Ingress Occupancy - NCB event=2 01 Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_occupancy uncore interconnect UNC_I_RxR_BL_NCB_OCCUPANCY event=8 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_cycles_full uncore interconnect UNC_I_RxR_BL_NCS_CYCLES_FULL event=6 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_inserts uncore interconnect BL Ingress Occupancy - NCS event=3 01 Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_occupancy uncore interconnect UNC_I_RxR_BL_NCS_OCCUPANCY event=9 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_snoop_resp.hit_es uncore interconnect Snoop Responses; Hit E or S event=0x17,umask=4 01 Snoop Responses : Hit E or S unc_i_snoop_resp.hit_i uncore interconnect Snoop Responses; Hit I event=0x17,umask=2 01 Snoop Responses : Hit I unc_i_snoop_resp.hit_m uncore interconnect Snoop Responses; Hit M event=0x17,umask=8 01 Snoop Responses : Hit M unc_i_snoop_resp.miss uncore interconnect Snoop Responses; Miss event=0x17,umask=1 01 Snoop Responses : Miss unc_i_snoop_resp.snpcode uncore interconnect Snoop Responses; SnpCode event=0x17,umask=0x10 01 Snoop Responses : SnpCode unc_i_snoop_resp.snpdata uncore interconnect Snoop Responses; SnpData event=0x17,umask=0x20 01 Snoop Responses : SnpData unc_i_snoop_resp.snpinv uncore interconnect Snoop Responses; SnpInv event=0x17,umask=0x40 01 Snoop Responses : SnpInv unc_i_transactions.atomic uncore interconnect Inbound Transaction Count; Atomic event=0x16,umask=0x10 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions unc_i_transactions.other uncore interconnect Inbound Transaction Count; Other event=0x16,umask=0x20 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions unc_i_transactions.rd_pref uncore interconnect Inbound Transaction Count; Read Prefetches event=0x16,umask=4 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x16,umask=1 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches) unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x16,umask=2 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests unc_i_transactions.wr_pref uncore interconnect Inbound Transaction Count; Write Prefetches event=0x16,umask=8 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches unc_i_txr_ad_stall_credit_cycles uncore interconnect No AD Egress Credit Stalls event=0x18 01 Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available unc_i_txr_bl_stall_credit_cycles uncore interconnect No BL Egress Credit Stalls event=0x19 01 Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available unc_i_txr_data_inserts_ncb uncore interconnect Outbound Read Requests event=0xe 01 Counts the number of requests issued to the switch (towards the devices) unc_i_txr_data_inserts_ncs uncore interconnect Outbound Read Requests event=0xf 01 Counts the number of requests issued to the switch (towards the devices) unc_i_txr_request_occupancy uncore interconnect Outbound Request Queue Occupancy event=0xd 01 Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests uncore_ubox unc_u_event_msg.doorbell_rcvd uncore interconnect VLW Received event=0x42,umask=8 01 Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.disable uncore interconnect Filter Match event=0x41,umask=2 01 Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.enable uncore interconnect Filter Match event=0x41,umask=1 01 Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.u2c_disable uncore interconnect Filter Match event=0x41,umask=8 01 Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.u2c_enable uncore interconnect Filter Match event=0x41,umask=4 01 Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_phold_cycles.assert_to_ack uncore interconnect Cycles PHOLD Assert to Ack; Assert to ACK event=0x45,umask=1 01 PHOLD cycles. Filter from source CoreID unc_u_racu_requests uncore interconnect RACU Request event=0x46 01 Number outstanding register requests within message channel tracker unc_u_u2c_events.cmc uncore interconnect Monitor Sent to T0; Correctable Machine Check event=0x43,umask=0x10 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.livelock uncore interconnect Monitor Sent to T0; Livelock event=0x43,umask=4 01 Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.lterror uncore interconnect Monitor Sent to T0; LTError event=0x43,umask=8 01 Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.monitor_t0 uncore interconnect Monitor Sent to T0; Monitor T0 event=0x43,umask=1 01 Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.monitor_t1 uncore interconnect Monitor Sent to T0; Monitor T1 event=0x43,umask=2 01 Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.other uncore interconnect Monitor Sent to T0; Other event=0x43,umask=0x80 01 Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI unc_u_u2c_events.trap uncore interconnect Monitor Sent to T0; Trap event=0x43,umask=0x40 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.umc uncore interconnect Monitor Sent to T0; Uncorrectable Machine Check event=0x43,umask=0x20 01 Events coming from Uncore can be sent to one or all cores uncore_r2pcie unc_r2_clockticks uncore io Number of uclks in domain event=1 01 Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_r2_iio_credit.isoch_qpi0 uncore io UNC_R2_IIO_CREDIT.ISOCH_QPI0 event=0x2d,umask=4 01 unc_r2_iio_credit.isoch_qpi1 uncore io UNC_R2_IIO_CREDIT.ISOCH_QPI1 event=0x2d,umask=8 01 unc_r2_iio_credit.prq_qpi0 uncore io UNC_R2_IIO_CREDIT.PRQ_QPI0 event=0x2d,umask=1 01 unc_r2_iio_credit.prq_qpi1 uncore io UNC_R2_IIO_CREDIT.PRQ_QPI1 event=0x2d,umask=2 01 unc_r2_iio_credits_acquired.drs uncore io R2PCIe IIO Credit Acquired; DRS event=0x33,umask=8 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class unc_r2_iio_credits_acquired.ncb uncore io R2PCIe IIO Credit Acquired; NCB event=0x33,umask=0x10 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class unc_r2_iio_credits_acquired.ncs uncore io R2PCIe IIO Credit Acquired; NCS event=0x33,umask=0x20 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class unc_r2_iio_credits_used.drs uncore io R2PCIe IIO Credits in Use; DRS event=0x32,umask=8 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class unc_r2_iio_credits_used.ncb uncore io R2PCIe IIO Credits in Use; NCB event=0x32,umask=0x10 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class unc_r2_iio_credits_used.ncs uncore io R2PCIe IIO Credits in Use; NCS event=0x32,umask=0x20 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class unc_r2_ring_ad_used.all uncore io R2 AD Ring in Use; All event=7,umask=0xf 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw uncore io R2 AD Ring in Use; Counterclockwise event=7,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw_even uncore io R2 AD Ring in Use; Counterclockwise and Even event=7,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r2_ring_ad_used.ccw_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd event=7,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r2_ring_ad_used.cw uncore io R2 AD Ring in Use; Clockwise event=7,umask=3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_even uncore io R2 AD Ring in Use; Clockwise and Even event=7,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r2_ring_ad_used.cw_odd uncore io R2 AD Ring in Use; Clockwise and Odd event=7,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r2_ring_ak_bounces.dn uncore io AK Ingress Bounced; Dn event=0x12,umask=2 01 Counts the number of times when a request destined for the AK ingress bounced unc_r2_ring_ak_bounces.up uncore io AK Ingress Bounced; Up event=0x12,umask=1 01 Counts the number of times when a request destined for the AK ingress bounced unc_r2_ring_ak_used.all uncore io R2 AK Ring in Use; All event=8,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw uncore io R2 AK Ring in Use; Counterclockwise event=8,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_even uncore io R2 AK Ring in Use; Counterclockwise and Even event=8,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r2_ring_ak_used.ccw_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd event=8,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r2_ring_ak_used.cw uncore io R2 AK Ring in Use; Clockwise event=8,umask=3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_even uncore io R2 AK Ring in Use; Clockwise and Even event=8,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r2_ring_ak_used.cw_odd uncore io R2 AK Ring in Use; Clockwise and Odd event=8,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r2_ring_bl_used.all uncore io R2 BL Ring in Use; All event=9,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw uncore io R2 BL Ring in Use; Counterclockwise event=9,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_even uncore io R2 BL Ring in Use; Counterclockwise and Even event=9,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r2_ring_bl_used.ccw_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd event=9,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r2_ring_bl_used.cw uncore io R2 BL Ring in Use; Clockwise event=9,umask=3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_even uncore io R2 BL Ring in Use; Clockwise and Even event=9,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r2_ring_bl_used.cw_odd uncore io R2 BL Ring in Use; Clockwise and Odd event=9,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r2_ring_iv_used.any uncore io R2 IV Ring in Use; Any event=0xa,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r2_ring_iv_used.ccw uncore io R2 IV Ring in Use; Counterclockwise event=0xa,umask=0xc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r2_ring_iv_used.cw uncore io R2 IV Ring in Use; Clockwise event=0xa,umask=3 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r2_rxr_cycles_ne.ncb uncore io Ingress Cycles Not Empty; NCB event=0x10,umask=0x10 01 Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r2_rxr_cycles_ne.ncs uncore io Ingress Cycles Not Empty; NCS event=0x10,umask=0x20 01 Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r2_rxr_inserts.ncb uncore io Ingress Allocations; NCB event=0x11,umask=0x10 01 Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r2_rxr_inserts.ncs uncore io Ingress Allocations; NCS event=0x11,umask=0x20 01 Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r2_rxr_occupancy.drs uncore io Ingress Occupancy Accumulator; DRS event=0x13,umask=8 01 Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue unc_r2_sbo0_credits_acquired.ad uncore io SBo0 Credits Acquired; For AD Ring event=0x28,umask=1 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_r2_sbo0_credits_acquired.bl uncore io SBo0 Credits Acquired; For BL Ring event=0x28,umask=2 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_r2_sbo0_credit_occupancy.ad uncore io SBo0 Credits Occupancy; For AD Ring event=0x2a,umask=1 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_r2_sbo0_credit_occupancy.bl uncore io SBo0 Credits Occupancy; For BL Ring event=0x2a,umask=2 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_r2_stall_no_sbo_credit.sbo0_ad uncore io Stall on No Sbo Credits; For SBo0, AD Ring event=0x2c,umask=1 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r2_stall_no_sbo_credit.sbo0_bl uncore io Stall on No Sbo Credits; For SBo0, BL Ring event=0x2c,umask=4 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r2_stall_no_sbo_credit.sbo1_ad uncore io Stall on No Sbo Credits; For SBo1, AD Ring event=0x2c,umask=2 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r2_stall_no_sbo_credit.sbo1_bl uncore io Stall on No Sbo Credits; For SBo1, BL Ring event=0x2c,umask=8 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r2_txr_cycles_full.ad uncore io Egress Cycles Full; AD event=0x25,umask=1 01 Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue unc_r2_txr_cycles_full.ak uncore io Egress Cycles Full; AK event=0x25,umask=2 01 Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue unc_r2_txr_cycles_full.bl uncore io Egress Cycles Full; BL event=0x25,umask=4 01 Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue unc_r2_txr_cycles_ne.ad uncore io Egress Cycles Not Empty; AD event=0x23,umask=1 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue unc_r2_txr_cycles_ne.ak uncore io Egress Cycles Not Empty; AK event=0x23,umask=2 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue unc_r2_txr_cycles_ne.bl uncore io Egress Cycles Not Empty; BL event=0x23,umask=4 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue unc_r2_txr_nack_cw.dn_ad uncore io Egress CCW NACK; AD CCW event=0x26,umask=1 01 AD CounterClockwise Egress Queue unc_r2_txr_nack_cw.dn_ak uncore io Egress CCW NACK; AK CCW event=0x26,umask=4 01 AK CounterClockwise Egress Queue unc_r2_txr_nack_cw.dn_bl uncore io Egress CCW NACK; BL CCW event=0x26,umask=2 01 BL CounterClockwise Egress Queue unc_r2_txr_nack_cw.up_ad uncore io Egress CCW NACK; AK CCW event=0x26,umask=8 01 BL CounterClockwise Egress Queue unc_r2_txr_nack_cw.up_ak uncore io Egress CCW NACK; BL CW event=0x26,umask=0x20 01 AD Clockwise Egress Queue unc_r2_txr_nack_cw.up_bl uncore io Egress CCW NACK; BL CCW event=0x26,umask=0x10 01 AD CounterClockwise Egress Queue unc_m_act_count.byp uncore memory DRAM Activate Count; Activate due to Write event=1,umask=8 01 Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.rd uncore memory DRAM Activate Count; Activate due to Read event=1,umask=1 01 Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.wr uncore memory DRAM Activate Count; Activate due to Write event=1,umask=2 01 Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_byp_cmds.act uncore memory ACT command issued by 2 cycle bypass event=0xa1,umask=1 01 unc_m_byp_cmds.cas uncore memory CAS command issued by 2 cycle bypass event=0xa1,umask=2 01 unc_m_byp_cmds.pre uncore memory PRE command issued by 2 cycle bypass event=0xa1,umask=4 01 unc_m_cas_count.all uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre) event=4,umask=0xf 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel unc_m_cas_count.rd uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills) event=4,umask=3 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills) unc_m_cas_count.rd_reg uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre) event=4,umask=1 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_rmm uncore memory DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM event=4,umask=0x20 01 unc_m_cas_count.rd_underfill uncore memory DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued event=4,umask=2 01 DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller. This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ. While it is possible for underfills to be issed in both WMM and RMM, this event counts both unc_m_cas_count.rd_wmm uncore memory DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM event=4,umask=0x10 01 unc_m_cas_count.wr uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes) event=4,umask=0xc 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel unc_m_cas_count.wr_rmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode event=4,umask=8 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode unc_m_cas_count.wr_wmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode event=4,umask=4 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode unc_m_dclockticks uncore memory DRAM Clockticks event=0 01 unc_m_dram_pre_all uncore memory DRAM Precharge All Commands event=6 01 Counts the number of times that the precharge all command was sent unc_m_dram_refresh.high uncore memory Number of DRAM Refreshes Issued event=5,umask=4 01 Counts the number of refreshes issued unc_m_dram_refresh.panic uncore memory Number of DRAM Refreshes Issued event=5,umask=2 01 Counts the number of refreshes issued unc_m_ecc_correctable_errors uncore memory ECC Correctable Errors event=9 01 Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode unc_m_major_modes.isoch uncore memory Cycles in a Major Mode; Isoch Major Mode event=7,umask=8 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed unc_m_major_modes.partial uncore memory Cycles in a Major Mode; Partial Major Mode event=7,umask=4 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed unc_m_major_modes.read uncore memory Cycles in a Major Mode; Read Major Mode event=7,umask=1 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes unc_m_major_modes.write uncore memory Cycles in a Major Mode; Write Major Mode event=7,umask=2 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth unc_m_power_channel_dlloff uncore memory Channel DLLOFF Cycles event=0x84 01 Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode unc_m_power_channel_ppd uncore memory Channel PPD Cycles event=0x85 01 Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of unc_m_power_cke_cycles.rank0 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=1 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank1 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=2 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank2 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=4 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank3 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=8 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank4 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x10 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank5 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x20 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank6 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x40 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank7 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x80 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_critical_throttle_cycles uncore memory Critical Throttle Cycles event=0x86 01 Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event unc_m_power_pcu_throttling uncore memory UNC_M_POWER_PCU_THROTTLING event=0x42 01 unc_m_power_self_refresh uncore memory Clock-Enabled Self-Refresh event=0x43 01 Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_power_throttle_cycles.rank0 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=1 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID unc_m_power_throttle_cycles.rank1 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=2 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank2 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=4 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank3 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=8 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank4 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x10 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank5 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x20 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank6 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x40 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank7 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x80 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_preemption.rd_preempt_rd uncore memory Read Preemption Count; Read over Read Preemption event=8,umask=1 01 Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read unc_m_preemption.rd_preempt_wr uncore memory Read Preemption Count; Read over Write Preemption event=8,umask=2 01 Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write unc_m_pre_count.byp uncore memory DRAM Precharge commands.; Precharge due to bypass event=2,umask=0x10 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.page_close uncore memory DRAM Precharge commands.; Precharge due to timer expiration event=2,umask=2 01 Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring. This does not include implicit precharge commands sent in auto-precharge mode unc_m_pre_count.page_miss uncore memory DRAM Precharge commands.; Precharges due to page miss event=2,umask=1 01 Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses. This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include PRE commands sent as a result of the page close counter expiration unc_m_pre_count.rd uncore memory DRAM Precharge commands.; Precharge due to read event=2,umask=4 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.wr uncore memory DRAM Precharge commands.; Precharge due to write event=2,umask=8 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_rd_cas_prio.high uncore memory Read CAS issued with HIGH priority event=0xa0,umask=4 01 unc_m_rd_cas_prio.low uncore memory Read CAS issued with LOW priority event=0xa0,umask=1 01 unc_m_rd_cas_prio.med uncore memory Read CAS issued with MEDIUM priority event=0xa0,umask=2 01 unc_m_rd_cas_prio.panic uncore memory Read CAS issued with PANIC NON ISOCH priority (starved) event=0xa0,umask=8 01 unc_m_rd_cas_rank0.allbanks uncore memory RD_CAS Access to Rank 0; All Banks event=0xb0,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank0.bank0 uncore memory RD_CAS Access to Rank 0; Bank 0 event=0xb0 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank0.bank1 uncore memory RD_CAS Access to Rank 0; Bank 1 event=0xb0,umask=1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank0.bank10 uncore memory RD_CAS Access to Rank 0; Bank 10 event=0xb0,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank0.bank11 uncore memory RD_CAS Access to Rank 0; Bank 11 event=0xb0,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank0.bank12 uncore memory RD_CAS Access to Rank 0; Bank 12 event=0xb0,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank0.bank13 uncore memory RD_CAS Access to Rank 0; Bank 13 event=0xb0,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank0.bank14 uncore memory RD_CAS Access to Rank 0; Bank 14 event=0xb0,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank0.bank15 uncore memory RD_CAS Access to Rank 0; Bank 15 event=0xb0,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank0.bank2 uncore memory RD_CAS Access to Rank 0; Bank 2 event=0xb0,umask=2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank0.bank3 uncore memory RD_CAS Access to Rank 0; Bank 3 event=0xb0,umask=3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank0.bank4 uncore memory RD_CAS Access to Rank 0; Bank 4 event=0xb0,umask=4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank0.bank5 uncore memory RD_CAS Access to Rank 0; Bank 5 event=0xb0,umask=5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank0.bank6 uncore memory RD_CAS Access to Rank 0; Bank 6 event=0xb0,umask=6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank0.bank7 uncore memory RD_CAS Access to Rank 0; Bank 7 event=0xb0,umask=7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank0.bank8 uncore memory RD_CAS Access to Rank 0; Bank 8 event=0xb0,umask=8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank0.bank9 uncore memory RD_CAS Access to Rank 0; Bank 9 event=0xb0,umask=9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank0.bankg0 uncore memory RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb0,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank0.bankg1 uncore memory RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb0,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank0.bankg2 uncore memory RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb0,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank0.bankg3 uncore memory RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb0,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank1.allbanks uncore memory RD_CAS Access to Rank 1; All Banks event=0xb1,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank1.bank0 uncore memory RD_CAS Access to Rank 1; Bank 0 event=0xb1 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank1.bank1 uncore memory RD_CAS Access to Rank 1; Bank 1 event=0xb1,umask=1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank1.bank10 uncore memory RD_CAS Access to Rank 1; Bank 10 event=0xb1,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank1.bank11 uncore memory RD_CAS Access to Rank 1; Bank 11 event=0xb1,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank1.bank12 uncore memory RD_CAS Access to Rank 1; Bank 12 event=0xb1,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank1.bank13 uncore memory RD_CAS Access to Rank 1; Bank 13 event=0xb1,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank1.bank14 uncore memory RD_CAS Access to Rank 1; Bank 14 event=0xb1,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank1.bank15 uncore memory RD_CAS Access to Rank 1; Bank 15 event=0xb1,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank1.bank2 uncore memory RD_CAS Access to Rank 1; Bank 2 event=0xb1,umask=2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank1.bank3 uncore memory RD_CAS Access to Rank 1; Bank 3 event=0xb1,umask=3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank1.bank4 uncore memory RD_CAS Access to Rank 1; Bank 4 event=0xb1,umask=4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank1.bank5 uncore memory RD_CAS Access to Rank 1; Bank 5 event=0xb1,umask=5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank1.bank6 uncore memory RD_CAS Access to Rank 1; Bank 6 event=0xb1,umask=6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank1.bank7 uncore memory RD_CAS Access to Rank 1; Bank 7 event=0xb1,umask=7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank1.bank8 uncore memory RD_CAS Access to Rank 1; Bank 8 event=0xb1,umask=8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank1.bank9 uncore memory RD_CAS Access to Rank 1; Bank 9 event=0xb1,umask=9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank1.bankg0 uncore memory RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb1,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank1.bankg1 uncore memory RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb1,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank1.bankg2 uncore memory RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb1,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank1.bankg3 uncore memory RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb1,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank2.bank0 uncore memory RD_CAS Access to Rank 2; Bank 0 event=0xb2 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank4.allbanks uncore memory RD_CAS Access to Rank 4; All Banks event=0xb4,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank4.bank0 uncore memory RD_CAS Access to Rank 4; Bank 0 event=0xb4 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank4.bank1 uncore memory RD_CAS Access to Rank 4; Bank 1 event=0xb4,umask=1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank4.bank10 uncore memory RD_CAS Access to Rank 4; Bank 10 event=0xb4,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank4.bank11 uncore memory RD_CAS Access to Rank 4; Bank 11 event=0xb4,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank4.bank12 uncore memory RD_CAS Access to Rank 4; Bank 12 event=0xb4,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank4.bank13 uncore memory RD_CAS Access to Rank 4; Bank 13 event=0xb4,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank4.bank14 uncore memory RD_CAS Access to Rank 4; Bank 14 event=0xb4,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank4.bank15 uncore memory RD_CAS Access to Rank 4; Bank 15 event=0xb4,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank4.bank2 uncore memory RD_CAS Access to Rank 4; Bank 2 event=0xb4,umask=2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank4.bank3 uncore memory RD_CAS Access to Rank 4; Bank 3 event=0xb4,umask=3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank4.bank4 uncore memory RD_CAS Access to Rank 4; Bank 4 event=0xb4,umask=4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank4.bank5 uncore memory RD_CAS Access to Rank 4; Bank 5 event=0xb4,umask=5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank4.bank6 uncore memory RD_CAS Access to Rank 4; Bank 6 event=0xb4,umask=6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank4.bank7 uncore memory RD_CAS Access to Rank 4; Bank 7 event=0xb4,umask=7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank4.bank8 uncore memory RD_CAS Access to Rank 4; Bank 8 event=0xb4,umask=8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank4.bank9 uncore memory RD_CAS Access to Rank 4; Bank 9 event=0xb4,umask=9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank4.bankg0 uncore memory RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xb4,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank4.bankg1 uncore memory RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xb4,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank4.bankg2 uncore memory RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xb4,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank4.bankg3 uncore memory RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xb4,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank5.allbanks uncore memory RD_CAS Access to Rank 5; All Banks event=0xb5,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank5.bank0 uncore memory RD_CAS Access to Rank 5; Bank 0 event=0xb5 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank5.bank1 uncore memory RD_CAS Access to Rank 5; Bank 1 event=0xb5,umask=1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank5.bank10 uncore memory RD_CAS Access to Rank 5; Bank 10 event=0xb5,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank5.bank11 uncore memory RD_CAS Access to Rank 5; Bank 11 event=0xb5,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank5.bank12 uncore memory RD_CAS Access to Rank 5; Bank 12 event=0xb5,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank5.bank13 uncore memory RD_CAS Access to Rank 5; Bank 13 event=0xb5,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank5.bank14 uncore memory RD_CAS Access to Rank 5; Bank 14 event=0xb5,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank5.bank15 uncore memory RD_CAS Access to Rank 5; Bank 15 event=0xb5,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank5.bank2 uncore memory RD_CAS Access to Rank 5; Bank 2 event=0xb5,umask=2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank5.bank3 uncore memory RD_CAS Access to Rank 5; Bank 3 event=0xb5,umask=3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank5.bank4 uncore memory RD_CAS Access to Rank 5; Bank 4 event=0xb5,umask=4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank5.bank5 uncore memory RD_CAS Access to Rank 5; Bank 5 event=0xb5,umask=5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank5.bank6 uncore memory RD_CAS Access to Rank 5; Bank 6 event=0xb5,umask=6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank5.bank7 uncore memory RD_CAS Access to Rank 5; Bank 7 event=0xb5,umask=7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank5.bank8 uncore memory RD_CAS Access to Rank 5; Bank 8 event=0xb5,umask=8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank5.bank9 uncore memory RD_CAS Access to Rank 5; Bank 9 event=0xb5,umask=9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank5.bankg0 uncore memory RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xb5,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank5.bankg1 uncore memory RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xb5,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank5.bankg2 uncore memory RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xb5,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank5.bankg3 uncore memory RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xb5,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank6.allbanks uncore memory RD_CAS Access to Rank 6; All Banks event=0xb6,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank6.bank0 uncore memory RD_CAS Access to Rank 6; Bank 0 event=0xb6 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank6.bank1 uncore memory RD_CAS Access to Rank 6; Bank 1 event=0xb6,umask=1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank6.bank10 uncore memory RD_CAS Access to Rank 6; Bank 10 event=0xb6,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank6.bank11 uncore memory RD_CAS Access to Rank 6; Bank 11 event=0xb6,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank6.bank12 uncore memory RD_CAS Access to Rank 6; Bank 12 event=0xb6,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank6.bank13 uncore memory RD_CAS Access to Rank 6; Bank 13 event=0xb6,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank6.bank14 uncore memory RD_CAS Access to Rank 6; Bank 14 event=0xb6,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank6.bank15 uncore memory RD_CAS Access to Rank 6; Bank 15 event=0xb6,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank6.bank2 uncore memory RD_CAS Access to Rank 6; Bank 2 event=0xb6,umask=2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank6.bank3 uncore memory RD_CAS Access to Rank 6; Bank 3 event=0xb6,umask=3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank6.bank4 uncore memory RD_CAS Access to Rank 6; Bank 4 event=0xb6,umask=4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank6.bank5 uncore memory RD_CAS Access to Rank 6; Bank 5 event=0xb6,umask=5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank6.bank6 uncore memory RD_CAS Access to Rank 6; Bank 6 event=0xb6,umask=6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank6.bank7 uncore memory RD_CAS Access to Rank 6; Bank 7 event=0xb6,umask=7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank6.bank8 uncore memory RD_CAS Access to Rank 6; Bank 8 event=0xb6,umask=8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank6.bank9 uncore memory RD_CAS Access to Rank 6; Bank 9 event=0xb6,umask=9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank6.bankg0 uncore memory RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xb6,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank6.bankg1 uncore memory RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xb6,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank6.bankg2 uncore memory RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xb6,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank6.bankg3 uncore memory RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xb6,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank7.allbanks uncore memory RD_CAS Access to Rank 7; All Banks event=0xb7,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank7.bank0 uncore memory RD_CAS Access to Rank 7; Bank 0 event=0xb7 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank7.bank1 uncore memory RD_CAS Access to Rank 7; Bank 1 event=0xb7,umask=1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank7.bank10 uncore memory RD_CAS Access to Rank 7; Bank 10 event=0xb7,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank7.bank11 uncore memory RD_CAS Access to Rank 7; Bank 11 event=0xb7,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank7.bank12 uncore memory RD_CAS Access to Rank 7; Bank 12 event=0xb7,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank7.bank13 uncore memory RD_CAS Access to Rank 7; Bank 13 event=0xb7,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank7.bank14 uncore memory RD_CAS Access to Rank 7; Bank 14 event=0xb7,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank7.bank15 uncore memory RD_CAS Access to Rank 7; Bank 15 event=0xb7,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank7.bank2 uncore memory RD_CAS Access to Rank 7; Bank 2 event=0xb7,umask=2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank7.bank3 uncore memory RD_CAS Access to Rank 7; Bank 3 event=0xb7,umask=3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank7.bank4 uncore memory RD_CAS Access to Rank 7; Bank 4 event=0xb7,umask=4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank7.bank5 uncore memory RD_CAS Access to Rank 7; Bank 5 event=0xb7,umask=5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank7.bank6 uncore memory RD_CAS Access to Rank 7; Bank 6 event=0xb7,umask=6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank7.bank7 uncore memory RD_CAS Access to Rank 7; Bank 7 event=0xb7,umask=7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank7.bank8 uncore memory RD_CAS Access to Rank 7; Bank 8 event=0xb7,umask=8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank7.bank9 uncore memory RD_CAS Access to Rank 7; Bank 9 event=0xb7,umask=9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank7.bankg0 uncore memory RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xb7,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank7.bankg1 uncore memory RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xb7,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank7.bankg2 uncore memory RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xb7,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank7.bankg3 uncore memory RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xb7,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rpq_cycles_ne uncore memory Read Pending Queue Not Empty event=0x11 01 Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests unc_m_rpq_inserts uncore memory Read Pending Queue Allocations event=0x10 01 Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_m_vmse_mxb_wr_occupancy uncore memory VMSE MXB write buffer occupancy event=0x91 01 unc_m_vmse_wr_push.rmm uncore memory VMSE WR PUSH issued; VMSE write PUSH issued in RMM event=0x90,umask=2 01 unc_m_vmse_wr_push.wmm uncore memory VMSE WR PUSH issued; VMSE write PUSH issued in WMM event=0x90,umask=1 01 unc_m_wmm_to_rmm.low_thresh uncore memory Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter event=0xc0,umask=1 01 unc_m_wmm_to_rmm.starve uncore memory Transition from WMM to RMM because of low threshold event=0xc0,umask=2 01 unc_m_wmm_to_rmm.vmse_retry uncore memory Transition from WMM to RMM because of low threshold event=0xc0,umask=4 01 unc_m_wpq_cycles_full uncore memory Write Pending Queue Full Cycles event=0x22 01 Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_ne uncore memory Write Pending Queue Not Empty event=0x21 01 Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_read_hit uncore memory Write Pending Queue CAM Match event=0x23 01 Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_write_hit uncore memory Write Pending Queue CAM Match event=0x24 01 Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wrong_mm uncore memory Not getting the requested Major Mode event=0xc1 01 unc_m_wr_cas_rank0.allbanks uncore memory WR_CAS Access to Rank 0; All Banks event=0xb8,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank0.bank0 uncore memory WR_CAS Access to Rank 0; Bank 0 event=0xb8 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank0.bank1 uncore memory WR_CAS Access to Rank 0; Bank 1 event=0xb8,umask=1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank0.bank10 uncore memory WR_CAS Access to Rank 0; Bank 10 event=0xb8,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank0.bank11 uncore memory WR_CAS Access to Rank 0; Bank 11 event=0xb8,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank0.bank12 uncore memory WR_CAS Access to Rank 0; Bank 12 event=0xb8,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank0.bank13 uncore memory WR_CAS Access to Rank 0; Bank 13 event=0xb8,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank0.bank14 uncore memory WR_CAS Access to Rank 0; Bank 14 event=0xb8,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank0.bank15 uncore memory WR_CAS Access to Rank 0; Bank 15 event=0xb8,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank0.bank2 uncore memory WR_CAS Access to Rank 0; Bank 2 event=0xb8,umask=2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank0.bank3 uncore memory WR_CAS Access to Rank 0; Bank 3 event=0xb8,umask=3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank0.bank4 uncore memory WR_CAS Access to Rank 0; Bank 4 event=0xb8,umask=4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank0.bank5 uncore memory WR_CAS Access to Rank 0; Bank 5 event=0xb8,umask=5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank0.bank6 uncore memory WR_CAS Access to Rank 0; Bank 6 event=0xb8,umask=6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank0.bank7 uncore memory WR_CAS Access to Rank 0; Bank 7 event=0xb8,umask=7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank0.bank8 uncore memory WR_CAS Access to Rank 0; Bank 8 event=0xb8,umask=8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank0.bank9 uncore memory WR_CAS Access to Rank 0; Bank 9 event=0xb8,umask=9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank0.bankg0 uncore memory WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb8,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank0.bankg1 uncore memory WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb8,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank0.bankg2 uncore memory WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb8,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank0.bankg3 uncore memory WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb8,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank1.allbanks uncore memory WR_CAS Access to Rank 1; All Banks event=0xb9,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank1.bank0 uncore memory WR_CAS Access to Rank 1; Bank 0 event=0xb9 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank1.bank1 uncore memory WR_CAS Access to Rank 1; Bank 1 event=0xb9,umask=1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank1.bank10 uncore memory WR_CAS Access to Rank 1; Bank 10 event=0xb9,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank1.bank11 uncore memory WR_CAS Access to Rank 1; Bank 11 event=0xb9,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank1.bank12 uncore memory WR_CAS Access to Rank 1; Bank 12 event=0xb9,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank1.bank13 uncore memory WR_CAS Access to Rank 1; Bank 13 event=0xb9,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank1.bank14 uncore memory WR_CAS Access to Rank 1; Bank 14 event=0xb9,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank1.bank15 uncore memory WR_CAS Access to Rank 1; Bank 15 event=0xb9,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank1.bank2 uncore memory WR_CAS Access to Rank 1; Bank 2 event=0xb9,umask=2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank1.bank3 uncore memory WR_CAS Access to Rank 1; Bank 3 event=0xb9,umask=3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank1.bank4 uncore memory WR_CAS Access to Rank 1; Bank 4 event=0xb9,umask=4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank1.bank5 uncore memory WR_CAS Access to Rank 1; Bank 5 event=0xb9,umask=5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank1.bank6 uncore memory WR_CAS Access to Rank 1; Bank 6 event=0xb9,umask=6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank1.bank7 uncore memory WR_CAS Access to Rank 1; Bank 7 event=0xb9,umask=7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank1.bank8 uncore memory WR_CAS Access to Rank 1; Bank 8 event=0xb9,umask=8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank1.bank9 uncore memory WR_CAS Access to Rank 1; Bank 9 event=0xb9,umask=9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank1.bankg0 uncore memory WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb9,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank1.bankg1 uncore memory WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb9,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank1.bankg2 uncore memory WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb9,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank1.bankg3 uncore memory WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb9,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank4.allbanks uncore memory WR_CAS Access to Rank 4; All Banks event=0xbc,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank4.bank0 uncore memory WR_CAS Access to Rank 4; Bank 0 event=0xbc 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank4.bank1 uncore memory WR_CAS Access to Rank 4; Bank 1 event=0xbc,umask=1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank4.bank10 uncore memory WR_CAS Access to Rank 4; Bank 10 event=0xbc,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank4.bank11 uncore memory WR_CAS Access to Rank 4; Bank 11 event=0xbc,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank4.bank12 uncore memory WR_CAS Access to Rank 4; Bank 12 event=0xbc,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank4.bank13 uncore memory WR_CAS Access to Rank 4; Bank 13 event=0xbc,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank4.bank14 uncore memory WR_CAS Access to Rank 4; Bank 14 event=0xbc,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank4.bank15 uncore memory WR_CAS Access to Rank 4; Bank 15 event=0xbc,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank4.bank2 uncore memory WR_CAS Access to Rank 4; Bank 2 event=0xbc,umask=2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank4.bank3 uncore memory WR_CAS Access to Rank 4; Bank 3 event=0xbc,umask=3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank4.bank4 uncore memory WR_CAS Access to Rank 4; Bank 4 event=0xbc,umask=4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank4.bank5 uncore memory WR_CAS Access to Rank 4; Bank 5 event=0xbc,umask=5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank4.bank6 uncore memory WR_CAS Access to Rank 4; Bank 6 event=0xbc,umask=6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank4.bank7 uncore memory WR_CAS Access to Rank 4; Bank 7 event=0xbc,umask=7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank4.bank8 uncore memory WR_CAS Access to Rank 4; Bank 8 event=0xbc,umask=8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank4.bank9 uncore memory WR_CAS Access to Rank 4; Bank 9 event=0xbc,umask=9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank4.bankg0 uncore memory WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xbc,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank4.bankg1 uncore memory WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xbc,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank4.bankg2 uncore memory WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xbc,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank4.bankg3 uncore memory WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xbc,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank5.allbanks uncore memory WR_CAS Access to Rank 5; All Banks event=0xbd,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank5.bank0 uncore memory WR_CAS Access to Rank 5; Bank 0 event=0xbd 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank5.bank1 uncore memory WR_CAS Access to Rank 5; Bank 1 event=0xbd,umask=1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank5.bank10 uncore memory WR_CAS Access to Rank 5; Bank 10 event=0xbd,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank5.bank11 uncore memory WR_CAS Access to Rank 5; Bank 11 event=0xbd,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank5.bank12 uncore memory WR_CAS Access to Rank 5; Bank 12 event=0xbd,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank5.bank13 uncore memory WR_CAS Access to Rank 5; Bank 13 event=0xbd,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank5.bank14 uncore memory WR_CAS Access to Rank 5; Bank 14 event=0xbd,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank5.bank15 uncore memory WR_CAS Access to Rank 5; Bank 15 event=0xbd,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank5.bank2 uncore memory WR_CAS Access to Rank 5; Bank 2 event=0xbd,umask=2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank5.bank3 uncore memory WR_CAS Access to Rank 5; Bank 3 event=0xbd,umask=3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank5.bank4 uncore memory WR_CAS Access to Rank 5; Bank 4 event=0xbd,umask=4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank5.bank5 uncore memory WR_CAS Access to Rank 5; Bank 5 event=0xbd,umask=5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank5.bank6 uncore memory WR_CAS Access to Rank 5; Bank 6 event=0xbd,umask=6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank5.bank7 uncore memory WR_CAS Access to Rank 5; Bank 7 event=0xbd,umask=7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank5.bank8 uncore memory WR_CAS Access to Rank 5; Bank 8 event=0xbd,umask=8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank5.bank9 uncore memory WR_CAS Access to Rank 5; Bank 9 event=0xbd,umask=9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank5.bankg0 uncore memory WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xbd,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank5.bankg1 uncore memory WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xbd,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank5.bankg2 uncore memory WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xbd,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank5.bankg3 uncore memory WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xbd,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank6.allbanks uncore memory WR_CAS Access to Rank 6; All Banks event=0xbe,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank6.bank0 uncore memory WR_CAS Access to Rank 6; Bank 0 event=0xbe 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank6.bank1 uncore memory WR_CAS Access to Rank 6; Bank 1 event=0xbe,umask=1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank6.bank10 uncore memory WR_CAS Access to Rank 6; Bank 10 event=0xbe,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank6.bank11 uncore memory WR_CAS Access to Rank 6; Bank 11 event=0xbe,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank6.bank12 uncore memory WR_CAS Access to Rank 6; Bank 12 event=0xbe,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank6.bank13 uncore memory WR_CAS Access to Rank 6; Bank 13 event=0xbe,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank6.bank14 uncore memory WR_CAS Access to Rank 6; Bank 14 event=0xbe,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank6.bank15 uncore memory WR_CAS Access to Rank 6; Bank 15 event=0xbe,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank6.bank2 uncore memory WR_CAS Access to Rank 6; Bank 2 event=0xbe,umask=2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank6.bank3 uncore memory WR_CAS Access to Rank 6; Bank 3 event=0xbe,umask=3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank6.bank4 uncore memory WR_CAS Access to Rank 6; Bank 4 event=0xbe,umask=4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank6.bank5 uncore memory WR_CAS Access to Rank 6; Bank 5 event=0xbe,umask=5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank6.bank6 uncore memory WR_CAS Access to Rank 6; Bank 6 event=0xbe,umask=6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank6.bank7 uncore memory WR_CAS Access to Rank 6; Bank 7 event=0xbe,umask=7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank6.bank8 uncore memory WR_CAS Access to Rank 6; Bank 8 event=0xbe,umask=8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank6.bank9 uncore memory WR_CAS Access to Rank 6; Bank 9 event=0xbe,umask=9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank6.bankg0 uncore memory WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xbe,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank6.bankg1 uncore memory WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xbe,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank6.bankg2 uncore memory WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xbe,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank6.bankg3 uncore memory WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xbe,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank7.allbanks uncore memory WR_CAS Access to Rank 7; All Banks event=0xbf,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank7.bank0 uncore memory WR_CAS Access to Rank 7; Bank 0 event=0xbf 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank7.bank1 uncore memory WR_CAS Access to Rank 7; Bank 1 event=0xbf,umask=1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank7.bank10 uncore memory WR_CAS Access to Rank 7; Bank 10 event=0xbf,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank7.bank11 uncore memory WR_CAS Access to Rank 7; Bank 11 event=0xbf,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank7.bank12 uncore memory WR_CAS Access to Rank 7; Bank 12 event=0xbf,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank7.bank13 uncore memory WR_CAS Access to Rank 7; Bank 13 event=0xbf,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank7.bank14 uncore memory WR_CAS Access to Rank 7; Bank 14 event=0xbf,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank7.bank15 uncore memory WR_CAS Access to Rank 7; Bank 15 event=0xbf,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank7.bank2 uncore memory WR_CAS Access to Rank 7; Bank 2 event=0xbf,umask=2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank7.bank3 uncore memory WR_CAS Access to Rank 7; Bank 3 event=0xbf,umask=3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank7.bank4 uncore memory WR_CAS Access to Rank 7; Bank 4 event=0xbf,umask=4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank7.bank5 uncore memory WR_CAS Access to Rank 7; Bank 5 event=0xbf,umask=5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank7.bank6 uncore memory WR_CAS Access to Rank 7; Bank 6 event=0xbf,umask=6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank7.bank7 uncore memory WR_CAS Access to Rank 7; Bank 7 event=0xbf,umask=7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank7.bank8 uncore memory WR_CAS Access to Rank 7; Bank 8 event=0xbf,umask=8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank7.bank9 uncore memory WR_CAS Access to Rank 7; Bank 9 event=0xbf,umask=9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank7.bankg0 uncore memory WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xbf,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank7.bankg1 uncore memory WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xbf,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank7.bankg2 uncore memory WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xbf,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank7.bankg3 uncore memory WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xbf,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) uncore_pcu unc_p_clockticks uncore power pclk Cycles event=0 01 The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time unc_p_core0_transition_cycles uncore power Core C State Transition Cycles event=0x60 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core10_transition_cycles uncore power Core C State Transition Cycles event=0x6a 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core11_transition_cycles uncore power Core C State Transition Cycles event=0x6b 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core12_transition_cycles uncore power Core C State Transition Cycles event=0x6c 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core13_transition_cycles uncore power Core C State Transition Cycles event=0x6d 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core14_transition_cycles uncore power Core C State Transition Cycles event=0x6e 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core15_transition_cycles uncore power Core C State Transition Cycles event=0x6f 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core16_transition_cycles uncore power Core C State Transition Cycles event=0x70 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core17_transition_cycles uncore power Core C State Transition Cycles event=0x71 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core1_transition_cycles uncore power Core C State Transition Cycles event=0x61 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core2_transition_cycles uncore power Core C State Transition Cycles event=0x62 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core3_transition_cycles uncore power Core C State Transition Cycles event=0x63 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core4_transition_cycles uncore power Core C State Transition Cycles event=0x64 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core5_transition_cycles uncore power Core C State Transition Cycles event=0x65 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core6_transition_cycles uncore power Core C State Transition Cycles event=0x66 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core7_transition_cycles uncore power Core C State Transition Cycles event=0x67 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core8_transition_cycles uncore power Core C State Transition Cycles event=0x68 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core9_transition_cycles uncore power Core C State Transition Cycles event=0x69 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_demotions_core0 uncore power Core C State Demotions event=0x30 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core1 uncore power Core C State Demotions event=0x31 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core10 uncore power Core C State Demotions event=0x3a 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core11 uncore power Core C State Demotions event=0x3b 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core12 uncore power Core C State Demotions event=0x3c 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core13 uncore power Core C State Demotions event=0x3d 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core14 uncore power Core C State Demotions event=0x3e 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core15 uncore power Core C State Demotions event=0x3f 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core16 uncore power Core C State Demotions event=0x40 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core17 uncore power Core C State Demotions event=0x41 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core2 uncore power Core C State Demotions event=0x32 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core3 uncore power Core C State Demotions event=0x33 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core4 uncore power Core C State Demotions event=0x34 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core5 uncore power Core C State Demotions event=0x35 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core6 uncore power Core C State Demotions event=0x36 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core7 uncore power Core C State Demotions event=0x37 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core8 uncore power Core C State Demotions event=0x38 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core9 uncore power Core C State Demotions event=0x39 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_freq_max_limit_thermal_cycles uncore power Thermal Strongest Upper Limit Cycles event=4 01 Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input unc_p_freq_max_os_cycles uncore power OS Strongest Upper Limit Cycles event=6 01 Counts the number of cycles when the OS is the upper limit on frequency unc_p_freq_max_power_cycles uncore power Power Strongest Upper Limit Cycles event=5 01 Counts the number of cycles when power is the upper limit on frequency unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=0x73 01 Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0x74 01 Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_memory_phase_shedding_cycles uncore power Memory Phase Shedding Cycles event=0x2f 01 Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency unc_p_pkg_residency_c0_cycles uncore power Package C State Residency - C0 event=0x2a 01 Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c1e_cycles uncore power Package C State Residency - C1E event=0x4e 01 Counts the number of cycles when the package was in C1E. This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c2e_cycles uncore power Package C State Residency - C2E event=0x2b 01 Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c3_cycles uncore power Package C State Residency - C3 event=0x2c 01 Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c6_cycles uncore power Package C State Residency - C6 event=0x2d 01 Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c7_cycles uncore power Package C7 State Residency event=0x2e 01 Counts the number of cycles when the package was in C7. This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert). Residency events do not include transition times unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C-State; C0 and C1 event=0x80,occ_sel=1 01 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C-State; C3 event=0x80,occ_sel=2 01 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C-State; C6 and C7 event=0x80,occ_sel=3 01 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_prochot_external_cycles uncore power External Prochot event=0xa 01 Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip unc_p_prochot_internal_cycles uncore power Internal Prochot event=9 01 Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0x72 01 Number of cycles spent performing core C state transitions across all cores unc_p_ufs_transitions_ring_gv uncore power UNC_P_UFS_TRANSITIONS_RING_GV event=0x79 01 Ring GV with same final and initial frequency unc_p_vr_hot_cycles uncore power VR Hot event=0x42 01 VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs offcore_response.all_code_rd.llc_hit.hit_other_core_no_fwd cache Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0244 00 offcore_response.all_data_rd.llc_hit.hitm_other_core cache Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0091 00 offcore_response.all_data_rd.llc_hit.hit_other_core_no_fwd cache Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0091 00 offcore_response.all_reads.llc_hit.hitm_other_core cache Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C07F7 00 offcore_response.all_reads.llc_hit.hit_other_core_no_fwd cache Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C07F7 00 offcore_response.all_requests.llc_hit.any_response cache Counts all requests hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C8FFF 00 offcore_response.all_rfo.llc_hit.hitm_other_core cache Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122 00 offcore_response.all_rfo.llc_hit.hit_other_core_no_fwd cache Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122 00 offcore_response.demand_rfo.llc_hit.any_response cache Counts all demand data writes (RFOs) hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002 00 offcore_response.demand_rfo.llc_hit.hitm_other_core cache Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002 00 offcore_response.pf_llc_code_rd.llc_hit.any_response cache Counts prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0200 00 offcore_response.pf_llc_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100 00 offcore_response.all_code_rd.llc_miss.any_response memory Counts all demand & prefetch code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00244 00 offcore_response.all_code_rd.llc_miss.local_dram memory Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000244 00 offcore_response.all_data_rd.llc_miss.any_response memory Counts all demand & prefetch data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00091 00 offcore_response.all_data_rd.llc_miss.local_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000091 00 offcore_response.all_data_rd.llc_miss.remote_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63BC00091 00 offcore_response.all_data_rd.llc_miss.remote_hitm memory Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00091 00 offcore_response.all_data_rd.llc_miss.remote_hit_forward memory Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87FC00091 00 offcore_response.all_reads.llc_miss.any_response memory Counts all data/code/rfo reads (demand & prefetch) miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC007F7 00 offcore_response.all_reads.llc_miss.local_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x6040007F7 00 offcore_response.all_reads.llc_miss.remote_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63BC007F7 00 offcore_response.all_reads.llc_miss.remote_hitm memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC007F7 00 offcore_response.all_reads.llc_miss.remote_hit_forward memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87FC007F7 00 offcore_response.all_requests.llc_miss.any_response memory Counts all requests miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC08FFF 00 offcore_response.all_rfo.llc_miss.any_response memory Counts all demand & prefetch RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00122 00 offcore_response.all_rfo.llc_miss.local_dram memory Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000122 00 offcore_response.demand_rfo.llc_miss.any_response memory Counts all demand data writes (RFOs) miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00002 00 offcore_response.demand_rfo.llc_miss.remote_hitm memory Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00002 00 offcore_response.pf_llc_code_rd.llc_miss.any_response memory Counts prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00200 00 offcore_response.pf_llc_rfo.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00100 00 llc_misses.code_llc_prefetch uncore cache LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x191 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.data_llc_prefetch uncore cache LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x192 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.data_read uncore cache LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x182 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.mmio_read uncore cache MMIO reads. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x187,filter_nc=1 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.mmio_write uncore cache MMIO writes. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x18f,filter_nc=1 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.pcie_non_snoop_write uncore cache PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x1c8,filter_tid=0x3e 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.pcie_read uncore cache LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x19e 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.pcie_write uncore cache ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x1c8 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.rfo_llc_prefetch uncore cache LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x190 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.uncacheable uncore cache LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x187 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_references.code_llc_prefetch uncore cache L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x181 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.pcie_ns_partial_write uncore cache PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x180,filter_tid=0x3e 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.pcie_read uncore cache PCIe read current. Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x19e 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.pcie_write uncore cache PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x1c8,filter_tid=0x3e 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.streaming_full uncore cache Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x18c 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.streaming_partial uncore cache Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x18d 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) unc_c_llc_lookup.any uncore cache All LLC Misses (code+ data rd + data wr - including demand and prefetch) event=0x34,umask=0x11,filter_state=0x1 0164Bytes Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_c_llc_victims.m_state uncore cache M line evictions from LLC (writebacks to memory) event=0x37,umask=1 0164Bytes Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_ring_ad_used.down uncore cache AD Ring In Use; Down event=0x1b,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX-- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up uncore cache AD Ring In Use; Up event=0x1b,umask=3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down uncore cache AK Ring In Use; Down event=0x1c,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up uncore cache AK Ring In Use; Up event=0x1c,umask=3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down uncore cache BL Ring in Use; Down event=0x1d,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up uncore cache BL Ring in Use; Up event=0x1d,umask=3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_tor_occupancy.llc_data_read uncore cache Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode event=0x36,umask=3,filter_opc=0x182 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO unc_h_snoop_resp.rspifwd uncore cache M line forwarded from remote cache with no writeback to memory event=0x21,umask=4 0164Bytes Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE unc_h_snoop_resp.rsps uncore cache Shared line response from remote cache event=0x21,umask=2 0164Bytes Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_h_snoop_resp.rspsfwd uncore cache Shared line forwarded from remote cache event=0x21,umask=8 0164Bytes Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state unc_h_snoop_resp.rsp_fwd_wb uncore cache M line forwarded from remote cache along with writeback to memory event=0x21,umask=0x20 0164Bytes Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory uncore_qpi qpi_ctl_bandwidth_tx uncore interconnect Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data event=0,umask=4 018Bytes Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets qpi_data_bandwidth_tx uncore interconnect Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data event=0,umask=2 018Bytes Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets unc_q_clockticks uncore interconnect Number of qfclks event=0x14 01 Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. BDX does not support dynamic link speeds, so this frequency is fixed unc_q_cto_count uncore interconnect Count of CTO Events event=0x38 01 Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered unc_q_direct2core.failure_credits uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress Credits event=0x13,umask=2 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched unc_q_direct2core.failure_credits_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss event=0x13,umask=0x20 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set unc_q_direct2core.failure_credits_rbt uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid event=0x13,umask=8 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched unc_q_direct2core.failure_credits_rbt_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid event=0x13,umask=0x80 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits unc_q_direct2core.failure_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Miss event=0x13,umask=0x10 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits unc_q_direct2core.failure_rbt_hit uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Invalid event=0x13,umask=4 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set unc_q_direct2core.failure_rbt_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid event=0x13,umask=0x40 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits unc_q_direct2core.success_rbt_hit uncore interconnect Direct 2 Core Spawning; Spawn Success event=0x13,umask=1 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core unc_q_l1_power_cycles uncore interconnect Cycles in L1 event=0x12 01 Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode unc_q_rxl0p_power_cycles uncore interconnect Cycles in L0p event=0x10 01 Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_q_rxl0_power_cycles uncore interconnect Cycles in L0 event=0xf 01 Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_q_rxl_bypassed uncore interconnect Rx Flit Buffer Bypassed event=9 01 Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_q_rxl_crc_errors.link_init uncore interconnect CRC Errors Detected; LinkInit event=3,umask=1 01 Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization unc_q_rxl_crc_errors.normal_op uncore interconnect UNC_Q_RxL_CRC_ERRORS.NORMAL_OP event=3,umask=2 01 unc_q_rxl_credits_consumed_vn0.drs uncore interconnect VN0 Credit Consumed; DRS event=0x1e,umask=1 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class unc_q_rxl_credits_consumed_vn0.hom uncore interconnect VN0 Credit Consumed; HOM event=0x1e,umask=8 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class unc_q_rxl_credits_consumed_vn0.ncb uncore interconnect VN0 Credit Consumed; NCB event=0x1e,umask=2 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class unc_q_rxl_credits_consumed_vn0.ncs uncore interconnect VN0 Credit Consumed; NCS event=0x1e,umask=4 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class unc_q_rxl_credits_consumed_vn0.ndr uncore interconnect VN0 Credit Consumed; NDR event=0x1e,umask=0x20 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class unc_q_rxl_credits_consumed_vn0.snp uncore interconnect VN0 Credit Consumed; SNP event=0x1e,umask=0x10 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class unc_q_rxl_credits_consumed_vn1.drs uncore interconnect VN1 Credit Consumed; DRS event=0x39,umask=1 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class unc_q_rxl_credits_consumed_vn1.hom uncore interconnect VN1 Credit Consumed; HOM event=0x39,umask=8 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class unc_q_rxl_credits_consumed_vn1.ncb uncore interconnect VN1 Credit Consumed; NCB event=0x39,umask=2 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class unc_q_rxl_credits_consumed_vn1.ncs uncore interconnect VN1 Credit Consumed; NCS event=0x39,umask=4 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class unc_q_rxl_credits_consumed_vn1.ndr uncore interconnect VN1 Credit Consumed; NDR event=0x39,umask=0x20 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class unc_q_rxl_credits_consumed_vn1.snp uncore interconnect VN1 Credit Consumed; SNP event=0x39,umask=0x10 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class unc_q_rxl_credits_consumed_vna uncore interconnect VNA Credit Consumed event=0x1d 01 Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_cycles_ne uncore interconnect RxQ Cycles Not Empty event=0xa 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy unc_q_rxl_cycles_ne_drs.vn0 uncore interconnect RxQ Cycles Not Empty - DRS; for VN0 event=0xf,umask=1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only unc_q_rxl_cycles_ne_drs.vn1 uncore interconnect RxQ Cycles Not Empty - DRS; for VN1 event=0xf,umask=2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only unc_q_rxl_cycles_ne_hom.vn0 uncore interconnect RxQ Cycles Not Empty - HOM; for VN0 event=0x12,umask=1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only unc_q_rxl_cycles_ne_hom.vn1 uncore interconnect RxQ Cycles Not Empty - HOM; for VN1 event=0x12,umask=2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only unc_q_rxl_cycles_ne_ncb.vn0 uncore interconnect RxQ Cycles Not Empty - NCB; for VN0 event=0x10,umask=1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only unc_q_rxl_cycles_ne_ncb.vn1 uncore interconnect RxQ Cycles Not Empty - NCB; for VN1 event=0x10,umask=2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only unc_q_rxl_cycles_ne_ncs.vn0 uncore interconnect RxQ Cycles Not Empty - NCS; for VN0 event=0x11,umask=1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only unc_q_rxl_cycles_ne_ncs.vn1 uncore interconnect RxQ Cycles Not Empty - NCS; for VN1 event=0x11,umask=2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only unc_q_rxl_cycles_ne_ndr.vn0 uncore interconnect RxQ Cycles Not Empty - NDR; for VN0 event=0x14,umask=1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only unc_q_rxl_cycles_ne_ndr.vn1 uncore interconnect RxQ Cycles Not Empty - NDR; for VN1 event=0x14,umask=2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only unc_q_rxl_cycles_ne_snp.vn0 uncore interconnect RxQ Cycles Not Empty - SNP; for VN0 event=0x13,umask=1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only unc_q_rxl_cycles_ne_snp.vn1 uncore interconnect RxQ Cycles Not Empty - SNP; for VN1 event=0x13,umask=2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only unc_q_rxl_flits_g0.idle uncore interconnect Flits Received - Group 0; Idle and Null Flits event=1,umask=1 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth unc_q_rxl_flits_g1.drs uncore interconnect Flits Received - Group 1; DRS Flits (both Header and Data) event=2,umask=0x18 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data unc_q_rxl_flits_g1.drs_data uncore interconnect Flits Received - Group 1; DRS Data Flits event=2,umask=8 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header) unc_q_rxl_flits_g1.drs_nondata uncore interconnect Flits Received - Group 1; DRS Header Flits event=2,umask=0x10 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers unc_q_rxl_flits_g1.hom uncore interconnect Flits Received - Group 1; HOM Flits event=2,umask=6 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel unc_q_rxl_flits_g1.hom_nonreq uncore interconnect Flits Received - Group 1; HOM Non-Request Flits event=2,umask=4 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that unc_q_rxl_flits_g1.hom_req uncore interconnect Flits Received - Group 1; HOM Request Flits event=2,umask=2 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses unc_q_rxl_flits_g1.snp uncore interconnect Flits Received - Group 1; SNP Flits event=2,umask=1 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel unc_q_rxl_flits_g2.ncb uncore interconnect Flits Received - Group 2; Non-Coherent Rx Flits event=3,umask=0xc 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI unc_q_rxl_flits_g2.ncb_data uncore interconnect Flits Received - Group 2; Non-Coherent data Rx Flits event=3,umask=4 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers unc_q_rxl_flits_g2.ncb_nondata uncore interconnect Flits Received - Group 2; Non-Coherent non-data Rx Flits event=3,umask=8 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers unc_q_rxl_flits_g2.ncs uncore interconnect Flits Received - Group 2; Non-Coherent standard Rx Flits event=3,umask=0x10 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers unc_q_rxl_flits_g2.ndr_ad uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AD event=3,umask=1 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring unc_q_rxl_flits_g2.ndr_ak uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AK event=3,umask=2 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket unc_q_rxl_inserts uncore interconnect Rx Flit Buffer Allocations event=8 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_q_rxl_inserts_drs.vn0 uncore interconnect Rx Flit Buffer Allocations - DRS; for VN0 event=9,umask=1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits unc_q_rxl_inserts_drs.vn1 uncore interconnect Rx Flit Buffer Allocations - DRS; for VN1 event=9,umask=2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits unc_q_rxl_inserts_hom.vn0 uncore interconnect Rx Flit Buffer Allocations - HOM; for VN0 event=0xc,umask=1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits unc_q_rxl_inserts_hom.vn1 uncore interconnect Rx Flit Buffer Allocations - HOM; for VN1 event=0xc,umask=2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits unc_q_rxl_inserts_ncb.vn0 uncore interconnect Rx Flit Buffer Allocations - NCB; for VN0 event=0xa,umask=1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits unc_q_rxl_inserts_ncb.vn1 uncore interconnect Rx Flit Buffer Allocations - NCB; for VN1 event=0xa,umask=2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits unc_q_rxl_inserts_ncs.vn0 uncore interconnect Rx Flit Buffer Allocations - NCS; for VN0 event=0xb,umask=1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits unc_q_rxl_inserts_ncs.vn1 uncore interconnect Rx Flit Buffer Allocations - NCS; for VN1 event=0xb,umask=2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits unc_q_rxl_inserts_ndr.vn0 uncore interconnect Rx Flit Buffer Allocations - NDR; for VN0 event=0xe,umask=1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits unc_q_rxl_inserts_ndr.vn1 uncore interconnect Rx Flit Buffer Allocations - NDR; for VN1 event=0xe,umask=2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits unc_q_rxl_inserts_snp.vn0 uncore interconnect Rx Flit Buffer Allocations - SNP; for VN0 event=0xd,umask=1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits unc_q_rxl_inserts_snp.vn1 uncore interconnect Rx Flit Buffer Allocations - SNP; for VN1 event=0xd,umask=2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits unc_q_rxl_occupancy uncore interconnect RxQ Occupancy - All Packets event=0xb 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_q_rxl_occupancy_drs.vn0 uncore interconnect RxQ Occupancy - DRS; for VN0 event=0x15,umask=1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only unc_q_rxl_occupancy_drs.vn1 uncore interconnect RxQ Occupancy - DRS; for VN1 event=0x15,umask=2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only unc_q_rxl_occupancy_hom.vn0 uncore interconnect RxQ Occupancy - HOM; for VN0 event=0x18,umask=1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only unc_q_rxl_occupancy_hom.vn1 uncore interconnect RxQ Occupancy - HOM; for VN1 event=0x18,umask=2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only unc_q_rxl_occupancy_ncb.vn0 uncore interconnect RxQ Occupancy - NCB; for VN0 event=0x16,umask=1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only unc_q_rxl_occupancy_ncb.vn1 uncore interconnect RxQ Occupancy - NCB; for VN1 event=0x16,umask=2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only unc_q_rxl_occupancy_ncs.vn0 uncore interconnect RxQ Occupancy - NCS; for VN0 event=0x17,umask=1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only unc_q_rxl_occupancy_ncs.vn1 uncore interconnect RxQ Occupancy - NCS; for VN1 event=0x17,umask=2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only unc_q_rxl_occupancy_ndr.vn0 uncore interconnect RxQ Occupancy - NDR; for VN0 event=0x1a,umask=1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only unc_q_rxl_occupancy_ndr.vn1 uncore interconnect RxQ Occupancy - NDR; for VN1 event=0x1a,umask=2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only unc_q_rxl_occupancy_snp.vn0 uncore interconnect RxQ Occupancy - SNP; for VN0 event=0x19,umask=1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only unc_q_rxl_occupancy_snp.vn1 uncore interconnect RxQ Occupancy - SNP; for VN1 event=0x19,umask=2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only unc_q_rxl_stalls_vn0.bgf_drs uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - HOM event=0x35,umask=1 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_hom uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - DRS event=0x35,umask=8 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_ncb uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - SNP event=0x35,umask=2 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_ncs uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - NDR event=0x35,umask=4 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_ndr uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - NCS event=0x35,umask=0x20 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_snp uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - NCB event=0x35,umask=0x10 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.egress_credits uncore interconnect Stalls Sending to R3QPI on VN0; Egress Credits event=0x35,umask=0x40 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events unc_q_rxl_stalls_vn0.gv uncore interconnect Stalls Sending to R3QPI on VN0; GV event=0x35,umask=0x80 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place unc_q_rxl_stalls_vn1.bgf_drs uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - HOM event=0x3a,umask=1 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_hom uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - DRS event=0x3a,umask=8 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_ncb uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - SNP event=0x3a,umask=2 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_ncs uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - NDR event=0x3a,umask=4 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_ndr uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - NCS event=0x3a,umask=0x20 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_snp uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - NCB event=0x3a,umask=0x10 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_txl0p_power_cycles uncore interconnect Cycles in L0p event=0xd 01 Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_q_txl0_power_cycles uncore interconnect Cycles in L0 event=0xc 01 Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_q_txl_bypassed uncore interconnect Tx Flit Buffer Bypassed event=5 01 Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link unc_q_txl_crc_no_credits.almost_full uncore interconnect Cycles Stalled with no LLR Credits; LLR is almost full event=2,umask=2 01 Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets unc_q_txl_crc_no_credits.full uncore interconnect Cycles Stalled with no LLR Credits; LLR is full event=2,umask=1 01 Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets unc_q_txl_cycles_ne uncore interconnect Tx Flit Buffer Cycles not Empty event=6 01 Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link unc_q_txl_flits_g0.data uncore interconnect Flits Transferred - Group 0; Data Tx Flits event=0,umask=2 01 Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets unc_q_txl_flits_g0.non_data uncore interconnect Flits Transferred - Group 0; Non-Data protocol Tx Flits event=0,umask=4 01 Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets unc_q_txl_flits_g1.drs uncore interconnect Flits Transferred - Group 1; DRS Flits (both Header and Data) event=0,umask=0x18 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency unc_q_txl_flits_g1.drs_data uncore interconnect Flits Transferred - Group 1; DRS Data Flits event=0,umask=8 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header) unc_q_txl_flits_g1.drs_nondata uncore interconnect Flits Transferred - Group 1; DRS Header Flits event=0,umask=0x10 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers unc_q_txl_flits_g1.hom uncore interconnect Flits Transferred - Group 1; HOM Flits event=0,umask=6 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel unc_q_txl_flits_g1.hom_nonreq uncore interconnect Flits Transferred - Group 1; HOM Non-Request Flits event=0,umask=4 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that unc_q_txl_flits_g1.hom_req uncore interconnect Flits Transferred - Group 1; HOM Request Flits event=0,umask=2 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses unc_q_txl_flits_g1.snp uncore interconnect Flits Transferred - Group 1; SNP Flits event=0,umask=1 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel unc_q_txl_flits_g2.ncb uncore interconnect Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits event=1,umask=0xc 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI unc_q_txl_flits_g2.ncb_data uncore interconnect Flits Transferred - Group 2; Non-Coherent data Tx Flits event=1,umask=4 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers unc_q_txl_flits_g2.ncb_nondata uncore interconnect Flits Transferred - Group 2; Non-Coherent non-data Tx Flits event=1,umask=8 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers unc_q_txl_flits_g2.ncs uncore interconnect Flits Transferred - Group 2; Non-Coherent standard Tx Flits event=1,umask=0x10 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers unc_q_txl_flits_g2.ndr_ad uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AD event=1,umask=1 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring unc_q_txl_flits_g2.ndr_ak uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AK event=1,umask=2 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket unc_q_txl_inserts uncore interconnect Tx Flit Buffer Allocations event=4 01 Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_q_txl_occupancy uncore interconnect Tx Flit Buffer Occupancy event=7 01 Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ unc_q_txr_ad_hom_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - HOM; for VN0 event=0x26,umask=1 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD unc_q_txr_ad_hom_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - HOM; for VN1 event=0x26,umask=2 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD unc_q_txr_ad_hom_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD HOM; for VN0 event=0x22,umask=1 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD unc_q_txr_ad_hom_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD HOM; for VN1 event=0x22,umask=2 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD unc_q_txr_ad_ndr_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN0 event=0x28,umask=1 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD unc_q_txr_ad_ndr_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN1 event=0x28,umask=2 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD unc_q_txr_ad_ndr_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN0 event=0x24,umask=1 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD unc_q_txr_ad_ndr_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN1 event=0x24,umask=2 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD unc_q_txr_ad_snp_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - SNP; for VN0 event=0x27,umask=1 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD unc_q_txr_ad_snp_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - SNP; for VN1 event=0x27,umask=2 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD unc_q_txr_ad_snp_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD SNP; for VN0 event=0x23,umask=1 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD unc_q_txr_ad_snp_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD SNP; for VN1 event=0x23,umask=2 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD unc_q_txr_ak_ndr_credit_acquired uncore interconnect R3QPI Egress Credit Occupancy - AK NDR event=0x29 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_occupancy uncore interconnect R3QPI Egress Credit Occupancy - AK NDR event=0x25 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress unc_q_txr_bl_drs_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - DRS; for VN0 event=0x2a,umask=1 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - DRS; for VN1 event=0x2a,umask=2 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_acquired.vn_shr uncore interconnect R3QPI Egress Credit Occupancy - DRS; for Shared VN event=0x2a,umask=4 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - BL DRS; for VN0 event=0x1f,umask=1 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - BL DRS; for VN1 event=0x1f,umask=2 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_occupancy.vn_shr uncore interconnect R3QPI Egress Credit Occupancy - BL DRS; for Shared VN event=0x1f,umask=4 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress unc_q_txr_bl_ncb_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - NCB; for VN0 event=0x2b,umask=1 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress unc_q_txr_bl_ncb_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - NCB; for VN1 event=0x2b,umask=2 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress unc_q_txr_bl_ncb_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - BL NCB; for VN0 event=0x20,umask=1 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress unc_q_txr_bl_ncb_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - BL NCB; for VN1 event=0x20,umask=2 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress unc_q_txr_bl_ncs_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - NCS; for VN0 event=0x2c,umask=1 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress unc_q_txr_bl_ncs_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - NCS; for VN1 event=0x2c,umask=2 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress unc_q_txr_bl_ncs_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - BL NCS; for VN0 event=0x21,umask=1 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress unc_q_txr_bl_ncs_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - BL NCS; for VN1 event=0x21,umask=2 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress unc_q_vna_credit_returns uncore interconnect VNA Credits Returned event=0x1c 01 Number of VNA credits returned unc_q_vna_credit_return_occupancy uncore interconnect VNA Credits Pending Return - Occupancy event=0x1b 01 Number of VNA credits in the Rx side that are waitng to be returned back across the link uncore_r3qpi unc_r3_clockticks uncore interconnect Number of uclks in domain event=1 01 Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_r3_c_hi_ad_credits_empty.cbo10 uncore interconnect CBox AD Credits Empty event=0x1f,umask=4 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10 unc_r3_c_hi_ad_credits_empty.cbo11 uncore interconnect CBox AD Credits Empty event=0x1f,umask=8 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11 unc_r3_c_hi_ad_credits_empty.cbo12 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x10 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12 unc_r3_c_hi_ad_credits_empty.cbo13 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x20 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13 unc_r3_c_hi_ad_credits_empty.cbo14_16 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x40 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16 unc_r3_c_hi_ad_credits_empty.cbo8 uncore interconnect CBox AD Credits Empty event=0x1f,umask=1 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8 unc_r3_c_hi_ad_credits_empty.cbo9 uncore interconnect CBox AD Credits Empty event=0x1f,umask=2 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9 unc_r3_c_hi_ad_credits_empty.cbo_15_17 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x80 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17 unc_r3_c_lo_ad_credits_empty.cbo0 uncore interconnect CBox AD Credits Empty event=0x22,umask=1 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0 unc_r3_c_lo_ad_credits_empty.cbo1 uncore interconnect CBox AD Credits Empty event=0x22,umask=2 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1 unc_r3_c_lo_ad_credits_empty.cbo2 uncore interconnect CBox AD Credits Empty event=0x22,umask=4 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2 unc_r3_c_lo_ad_credits_empty.cbo3 uncore interconnect CBox AD Credits Empty event=0x22,umask=8 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3 unc_r3_c_lo_ad_credits_empty.cbo4 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x10 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4 unc_r3_c_lo_ad_credits_empty.cbo5 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x20 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5 unc_r3_c_lo_ad_credits_empty.cbo6 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x40 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6 unc_r3_c_lo_ad_credits_empty.cbo7 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x80 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7 unc_r3_ha_r2_bl_credits_empty.ha0 uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=1 01 No credits available to send to either HA or R2 on the BL Ring; HA0 unc_r3_ha_r2_bl_credits_empty.ha1 uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=2 01 No credits available to send to either HA or R2 on the BL Ring; HA1 unc_r3_ha_r2_bl_credits_empty.r2_ncb uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=4 01 No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages unc_r3_ha_r2_bl_credits_empty.r2_ncs uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=8 01 No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages unc_r3_iot_backpressure.hub uncore interconnect IOT Backpressure event=0xb,umask=2 01 unc_r3_iot_backpressure.sat uncore interconnect IOT Backpressure event=0xb,umask=1 01 unc_r3_iot_cts_hi.cts2 uncore interconnect IOT Common Trigger Sequencer - Hi event=0xd,umask=1 01 Debug Mask/Match Tie-Ins unc_r3_iot_cts_hi.cts3 uncore interconnect IOT Common Trigger Sequencer - Hi event=0xd,umask=2 01 Debug Mask/Match Tie-Ins unc_r3_iot_cts_lo.cts0 uncore interconnect IOT Common Trigger Sequencer - Lo event=0xc,umask=1 01 Debug Mask/Match Tie-Ins unc_r3_iot_cts_lo.cts1 uncore interconnect IOT Common Trigger Sequencer - Lo event=0xc,umask=2 01 Debug Mask/Match Tie-Ins unc_r3_qpi0_ad_credits_empty.vn0_hom uncore interconnect QPI0 AD Credits Empty event=0x20,umask=2 01 No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages unc_r3_qpi0_ad_credits_empty.vn0_ndr uncore interconnect QPI0 AD Credits Empty event=0x20,umask=8 01 No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages unc_r3_qpi0_ad_credits_empty.vn0_snp uncore interconnect QPI0 AD Credits Empty event=0x20,umask=4 01 No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages unc_r3_qpi0_ad_credits_empty.vn1_hom uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x10 01 No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages unc_r3_qpi0_ad_credits_empty.vn1_ndr uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x40 01 No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages unc_r3_qpi0_ad_credits_empty.vn1_snp uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x20 01 No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages unc_r3_qpi0_ad_credits_empty.vna uncore interconnect QPI0 AD Credits Empty event=0x20,umask=1 01 No credits available to send to QPI0 on the AD Ring; VNA unc_r3_qpi0_bl_credits_empty.vn1_hom uncore interconnect QPI0 BL Credits Empty event=0x21,umask=0x10 01 No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages unc_r3_qpi0_bl_credits_empty.vn1_ndr uncore interconnect QPI0 BL Credits Empty event=0x21,umask=0x40 01 No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages unc_r3_qpi0_bl_credits_empty.vn1_snp uncore interconnect QPI0 BL Credits Empty event=0x21,umask=0x20 01 No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages unc_r3_qpi0_bl_credits_empty.vna uncore interconnect QPI0 BL Credits Empty event=0x21,umask=1 01 No credits available to send to QPI0 on the BL Ring; VNA unc_r3_qpi1_ad_credits_empty.vn1_hom uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=0x10 01 No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages unc_r3_qpi1_ad_credits_empty.vn1_ndr uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=0x40 01 No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages unc_r3_qpi1_ad_credits_empty.vn1_snp uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=0x20 01 No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages unc_r3_qpi1_ad_credits_empty.vna uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=1 01 No credits available to send to QPI1 on the AD Ring; VNA unc_r3_qpi1_bl_credits_empty.vn0_hom uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=2 01 No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages unc_r3_qpi1_bl_credits_empty.vn0_ndr uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=8 01 No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages unc_r3_qpi1_bl_credits_empty.vn0_snp uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=4 01 No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages unc_r3_qpi1_bl_credits_empty.vn1_hom uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x10 01 No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages unc_r3_qpi1_bl_credits_empty.vn1_ndr uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x40 01 No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages unc_r3_qpi1_bl_credits_empty.vn1_snp uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x20 01 No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages unc_r3_qpi1_bl_credits_empty.vna uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=1 01 No credits available to send to QPI1 on the BL Ring; VNA unc_r3_ring_ad_used.all uncore interconnect R3 AD Ring in Use; All event=7,umask=0xf 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw uncore interconnect R3 AD Ring in Use; Counterclockwise event=7,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw_even uncore interconnect R3 AD Ring in Use; Counterclockwise and Even event=7,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r3_ring_ad_used.ccw_odd uncore interconnect R3 AD Ring in Use; Counterclockwise and Odd event=7,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r3_ring_ad_used.cw uncore interconnect R3 AD Ring in Use; Clockwise event=7,umask=3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_even uncore interconnect R3 AD Ring in Use; Clockwise and Even event=7,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r3_ring_ad_used.cw_odd uncore interconnect R3 AD Ring in Use; Clockwise and Odd event=7,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r3_ring_ak_used.all uncore interconnect R3 AK Ring in Use; All event=8,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw uncore interconnect R3 AK Ring in Use; Counterclockwise event=8,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw_even uncore interconnect R3 AK Ring in Use; Counterclockwise and Even event=8,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r3_ring_ak_used.ccw_odd uncore interconnect R3 AK Ring in Use; Counterclockwise and Odd event=8,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r3_ring_ak_used.cw uncore interconnect R3 AK Ring in Use; Clockwise event=8,umask=3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.cw_even uncore interconnect R3 AK Ring in Use; Clockwise and Even event=8,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r3_ring_ak_used.cw_odd uncore interconnect R3 AK Ring in Use; Clockwise and Odd event=8,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r3_ring_bl_used.all uncore interconnect R3 BL Ring in Use; All event=9,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw uncore interconnect R3 BL Ring in Use; Counterclockwise event=9,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw_even uncore interconnect R3 BL Ring in Use; Counterclockwise and Even event=9,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r3_ring_bl_used.ccw_odd uncore interconnect R3 BL Ring in Use; Counterclockwise and Odd event=9,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r3_ring_bl_used.cw uncore interconnect R3 BL Ring in Use; Clockwise event=9,umask=3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_even uncore interconnect R3 BL Ring in Use; Clockwise and Even event=9,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r3_ring_bl_used.cw_odd uncore interconnect R3 BL Ring in Use; Clockwise and Odd event=9,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r3_ring_iv_used.any uncore interconnect R3 IV Ring in Use; Any event=0xa,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_iv_used.cw uncore interconnect R3 IV Ring in Use; Clockwise event=0xa,umask=3 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_sink_starved.ak uncore interconnect Ring Stop Starved; AK event=0xe,umask=2 01 Number of cycles the ringstop is in starvation (per ring) unc_r3_rxr_cycles_ne.hom uncore interconnect Ingress Cycles Not Empty; HOM event=0x10,umask=1 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_cycles_ne.ndr uncore interconnect Ingress Cycles Not Empty; NDR event=0x10,umask=4 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_cycles_ne.snp uncore interconnect Ingress Cycles Not Empty; SNP event=0x10,umask=2 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_cycles_ne_vn1.drs uncore interconnect VN1 Ingress Cycles Not Empty; DRS event=0x14,umask=8 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue unc_r3_rxr_cycles_ne_vn1.hom uncore interconnect VN1 Ingress Cycles Not Empty; HOM event=0x14,umask=1 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_cycles_ne_vn1.ncb uncore interconnect VN1 Ingress Cycles Not Empty; NCB event=0x14,umask=0x10 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r3_rxr_cycles_ne_vn1.ncs uncore interconnect VN1 Ingress Cycles Not Empty; NCS event=0x14,umask=0x20 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r3_rxr_cycles_ne_vn1.ndr uncore interconnect VN1 Ingress Cycles Not Empty; NDR event=0x14,umask=4 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_cycles_ne_vn1.snp uncore interconnect VN1 Ingress Cycles Not Empty; SNP event=0x14,umask=2 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_inserts.drs uncore interconnect Ingress Allocations; DRS event=0x11,umask=8 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue unc_r3_rxr_inserts.hom uncore interconnect Ingress Allocations; HOM event=0x11,umask=1 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_inserts.ncb uncore interconnect Ingress Allocations; NCB event=0x11,umask=0x10 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r3_rxr_inserts.ncs uncore interconnect Ingress Allocations; NCS event=0x11,umask=0x20 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r3_rxr_inserts.ndr uncore interconnect Ingress Allocations; NDR event=0x11,umask=4 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_inserts.snp uncore interconnect Ingress Allocations; SNP event=0x11,umask=2 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_inserts_vn1.drs uncore interconnect VN1 Ingress Allocations; DRS event=0x15,umask=8 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue unc_r3_rxr_inserts_vn1.hom uncore interconnect VN1 Ingress Allocations; HOM event=0x15,umask=1 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_inserts_vn1.ncb uncore interconnect VN1 Ingress Allocations; NCB event=0x15,umask=0x10 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r3_rxr_inserts_vn1.ncs uncore interconnect VN1 Ingress Allocations; NCS event=0x15,umask=0x20 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r3_rxr_inserts_vn1.ndr uncore interconnect VN1 Ingress Allocations; NDR event=0x15,umask=4 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_inserts_vn1.snp uncore interconnect VN1 Ingress Allocations; SNP event=0x15,umask=2 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_occupancy_vn1.drs uncore interconnect VN1 Ingress Occupancy Accumulator; DRS event=0x13,umask=8 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue unc_r3_rxr_occupancy_vn1.hom uncore interconnect VN1 Ingress Occupancy Accumulator; HOM event=0x13,umask=1 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue unc_r3_rxr_occupancy_vn1.ncb uncore interconnect VN1 Ingress Occupancy Accumulator; NCB event=0x13,umask=0x10 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue unc_r3_rxr_occupancy_vn1.ncs uncore interconnect VN1 Ingress Occupancy Accumulator; NCS event=0x13,umask=0x20 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue unc_r3_rxr_occupancy_vn1.ndr uncore interconnect VN1 Ingress Occupancy Accumulator; NDR event=0x13,umask=4 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue unc_r3_rxr_occupancy_vn1.snp uncore interconnect VN1 Ingress Occupancy Accumulator; SNP event=0x13,umask=2 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue unc_r3_sbo0_credits_acquired.ad uncore interconnect SBo0 Credits Acquired; For AD Ring event=0x28,umask=1 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_r3_sbo0_credits_acquired.bl uncore interconnect SBo0 Credits Acquired; For BL Ring event=0x28,umask=2 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_r3_sbo0_credit_occupancy.ad uncore interconnect SBo0 Credits Occupancy; For AD Ring event=0x2a,umask=1 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_r3_sbo0_credit_occupancy.bl uncore interconnect SBo0 Credits Occupancy; For BL Ring event=0x2a,umask=2 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_r3_sbo1_credits_acquired.ad uncore interconnect SBo1 Credits Acquired; For AD Ring event=0x29,umask=1 01 Number of Sbo 1 credits acquired in a given cycle, per ring unc_r3_sbo1_credits_acquired.bl uncore interconnect SBo1 Credits Acquired; For BL Ring event=0x29,umask=2 01 Number of Sbo 1 credits acquired in a given cycle, per ring unc_r3_sbo1_credit_occupancy.ad uncore interconnect SBo1 Credits Occupancy; For AD Ring event=0x2b,umask=1 01 Number of Sbo 1 credits in use in a given cycle, per ring unc_r3_sbo1_credit_occupancy.bl uncore interconnect SBo1 Credits Occupancy; For BL Ring event=0x2b,umask=2 01 Number of Sbo 1 credits in use in a given cycle, per ring unc_r3_stall_no_sbo_credit.sbo0_ad uncore interconnect Stall on No Sbo Credits; For SBo0, AD Ring event=0x2c,umask=1 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r3_stall_no_sbo_credit.sbo0_bl uncore interconnect Stall on No Sbo Credits; For SBo0, BL Ring event=0x2c,umask=4 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r3_stall_no_sbo_credit.sbo1_ad uncore interconnect Stall on No Sbo Credits; For SBo1, AD Ring event=0x2c,umask=2 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r3_stall_no_sbo_credit.sbo1_bl uncore interconnect Stall on No Sbo Credits; For SBo1, BL Ring event=0x2c,umask=8 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r3_txr_nack.dn_ad uncore interconnect Egress CCW NACK; AD CCW event=0x26,umask=1 01 AD CounterClockwise Egress Queue unc_r3_txr_nack.dn_ak uncore interconnect Egress CCW NACK; AK CCW event=0x26,umask=4 01 AK CounterClockwise Egress Queue unc_r3_txr_nack.dn_bl uncore interconnect Egress CCW NACK; BL CCW event=0x26,umask=2 01 BL CounterClockwise Egress Queue unc_r3_txr_nack.up_ad uncore interconnect Egress CCW NACK; AK CCW event=0x26,umask=8 01 BL CounterClockwise Egress Queue unc_r3_txr_nack.up_ak uncore interconnect Egress CCW NACK; BL CW event=0x26,umask=0x20 01 AD Clockwise Egress Queue unc_r3_txr_nack.up_bl uncore interconnect Egress CCW NACK; BL CCW event=0x26,umask=0x10 01 AD CounterClockwise Egress Queue unc_r3_vn0_credits_reject.drs uncore interconnect VN0 Credit Acquisition Failed on DRS; DRS Message Class event=0x37,umask=8 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn0_credits_reject.hom uncore interconnect VN0 Credit Acquisition Failed on DRS; HOM Message Class event=0x37,umask=1 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn0_credits_reject.ncb uncore interconnect VN0 Credit Acquisition Failed on DRS; NCB Message Class event=0x37,umask=0x10 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_r3_vn0_credits_reject.ncs uncore interconnect VN0 Credit Acquisition Failed on DRS; NCS Message Class event=0x37,umask=0x20 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? unc_r3_vn0_credits_reject.ndr uncore interconnect VN0 Credit Acquisition Failed on DRS; NDR Message Class event=0x37,umask=4 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn0_credits_reject.snp uncore interconnect VN0 Credit Acquisition Failed on DRS; SNP Message Class event=0x37,umask=2 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class unc_r3_vn0_credits_used.drs uncore interconnect VN0 Credit Used; DRS Message Class event=0x36,umask=8 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn0_credits_used.hom uncore interconnect VN0 Credit Used; HOM Message Class event=0x36,umask=1 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn0_credits_used.ncb uncore interconnect VN0 Credit Used; NCB Message Class event=0x36,umask=0x10 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_r3_vn0_credits_used.ncs uncore interconnect VN0 Credit Used; NCS Message Class event=0x36,umask=0x20 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? unc_r3_vn0_credits_used.ndr uncore interconnect VN0 Credit Used; NDR Message Class event=0x36,umask=4 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn0_credits_used.snp uncore interconnect VN0 Credit Used; SNP Message Class event=0x36,umask=2 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class unc_r3_vn1_credits_reject.drs uncore interconnect VN1 Credit Acquisition Failed on DRS; DRS Message Class event=0x39,umask=8 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn1_credits_reject.hom uncore interconnect VN1 Credit Acquisition Failed on DRS; HOM Message Class event=0x39,umask=1 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn1_credits_reject.ncb uncore interconnect VN1 Credit Acquisition Failed on DRS; NCB Message Class event=0x39,umask=0x10 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_r3_vn1_credits_reject.ncs uncore interconnect VN1 Credit Acquisition Failed on DRS; NCS Message Class event=0x39,umask=0x20 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? unc_r3_vn1_credits_reject.ndr uncore interconnect VN1 Credit Acquisition Failed on DRS; NDR Message Class event=0x39,umask=4 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn1_credits_reject.snp uncore interconnect VN1 Credit Acquisition Failed on DRS; SNP Message Class event=0x39,umask=2 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class unc_r3_vn1_credits_used.drs uncore interconnect VN1 Credit Used; DRS Message Class event=0x38,umask=8 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn1_credits_used.hom uncore interconnect VN1 Credit Used; HOM Message Class event=0x38,umask=1 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn1_credits_used.ncb uncore interconnect VN1 Credit Used; NCB Message Class event=0x38,umask=0x10 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_r3_vn1_credits_used.ncs uncore interconnect VN1 Credit Used; NCS Message Class event=0x38,umask=0x20 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? unc_r3_vn1_credits_used.ndr uncore interconnect VN1 Credit Used; NDR Message Class event=0x38,umask=4 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn1_credits_used.snp uncore interconnect VN1 Credit Used; SNP Message Class event=0x38,umask=2 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class unc_r3_vna_credits_acquired.ad uncore interconnect VNA credit Acquisitions; HOM Message Class event=0x33,umask=1 01 Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vna_credits_acquired.bl uncore interconnect VNA credit Acquisitions; HOM Message Class event=0x33,umask=4 01 Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vna_credits_reject.drs uncore interconnect VNA Credit Reject; DRS Message Class event=0x34,umask=8 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vna_credits_reject.hom uncore interconnect VNA Credit Reject; HOM Message Class event=0x34,umask=1 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vna_credits_reject.ncb uncore interconnect VNA Credit Reject; NCB Message Class event=0x34,umask=0x10 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_r3_vna_credits_reject.ncs uncore interconnect VNA Credit Reject; NCS Message Class event=0x34,umask=0x20 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS) unc_r3_vna_credits_reject.ndr uncore interconnect VNA Credit Reject; NDR Message Class event=0x34,umask=4 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vna_credits_reject.snp uncore interconnect VNA Credit Reject; SNP Message Class event=0x34,umask=2 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class uncore_sbox unc_s_bounce_control uncore interconnect Bounce Control event=0xa 01 unc_s_clockticks uncore interconnect Uncore Clocks event=0 01 unc_s_fast_asserted uncore interconnect FaST wire asserted event=9 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_s_ring_ad_used.all uncore interconnect AD Ring In Use; All event=0x1b,umask=0xf 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ad_used.down uncore interconnect AD Ring In Use; Down event=0x1b,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ad_used.down_even uncore interconnect AD Ring In Use; Down and Event event=0x1b,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ad_used.down_odd uncore interconnect AD Ring In Use; Down and Odd event=0x1b,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ad_used.up uncore interconnect AD Ring In Use; Up event=0x1b,umask=3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ad_used.up_even uncore interconnect AD Ring In Use; Up and Even event=0x1b,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ad_used.up_odd uncore interconnect AD Ring In Use; Up and Odd event=0x1b,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_ak_used.all uncore interconnect AK Ring In Use; All event=0x1c,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ak_used.down uncore interconnect AK Ring In Use; Down event=0x1c,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ak_used.down_even uncore interconnect AK Ring In Use; Down and Event event=0x1c,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ak_used.down_odd uncore interconnect AK Ring In Use; Down and Odd event=0x1c,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ak_used.up uncore interconnect AK Ring In Use; Up event=0x1c,umask=3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ak_used.up_even uncore interconnect AK Ring In Use; Up and Even event=0x1c,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ak_used.up_odd uncore interconnect AK Ring In Use; Up and Odd event=0x1c,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_bl_used.all uncore interconnect BL Ring in Use; All event=0x1d,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_bl_used.down uncore interconnect BL Ring in Use; Down event=0x1d,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_bl_used.down_even uncore interconnect BL Ring in Use; Down and Event event=0x1d,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_bl_used.down_odd uncore interconnect BL Ring in Use; Down and Odd event=0x1d,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_bl_used.up uncore interconnect BL Ring in Use; Up event=0x1d,umask=3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_bl_used.up_even uncore interconnect BL Ring in Use; Up and Even event=0x1d,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_bl_used.up_odd uncore interconnect BL Ring in Use; Up and Odd event=0x1d,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_bounces.ad_cache uncore interconnect Number of LLC responses that bounced on the Ring event=5,umask=1 01 unc_s_ring_bounces.ak_core uncore interconnect Number of LLC responses that bounced on the Ring.; Acknowledgements to core event=5,umask=2 01 unc_s_ring_bounces.bl_core uncore interconnect Number of LLC responses that bounced on the Ring.; Data Responses to core event=5,umask=4 01 unc_s_ring_bounces.iv_core uncore interconnect Number of LLC responses that bounced on the Ring.; Snoops of processor's cache event=5,umask=8 01 unc_s_ring_iv_used.dn uncore interconnect BL Ring in Use; Any event=0x1e,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_s_ring_iv_used.up uncore interconnect BL Ring in Use; Any event=0x1e,umask=3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_s_ring_sink_starved.ad_cache uncore interconnect UNC_S_RING_SINK_STARVED.AD_CACHE event=6,umask=1 01 unc_s_ring_sink_starved.ak_core uncore interconnect UNC_S_RING_SINK_STARVED.AK_CORE event=6,umask=2 01 unc_s_ring_sink_starved.bl_core uncore interconnect UNC_S_RING_SINK_STARVED.BL_CORE event=6,umask=4 01 unc_s_ring_sink_starved.iv_core uncore interconnect UNC_S_RING_SINK_STARVED.IV_CORE event=6,umask=8 01 unc_s_rxr_busy_starved.ad_bnc uncore interconnect Injection Starvation; AD - Bounces event=0x15,umask=2 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent unc_s_rxr_busy_starved.ad_crd uncore interconnect Injection Starvation; AD - Credits event=0x15,umask=1 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent unc_s_rxr_busy_starved.bl_bnc uncore interconnect Injection Starvation; BL - Bounces event=0x15,umask=8 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent unc_s_rxr_busy_starved.bl_crd uncore interconnect Injection Starvation; BL - Credits event=0x15,umask=4 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent unc_s_rxr_bypass.ad_bnc uncore interconnect Bypass; AD - Bounces event=0x12,umask=2 01 Bypass the Sbo Ingress unc_s_rxr_bypass.ad_crd uncore interconnect Bypass; AD - Credits event=0x12,umask=1 01 Bypass the Sbo Ingress unc_s_rxr_bypass.ak uncore interconnect Bypass; AK event=0x12,umask=0x10 01 Bypass the Sbo Ingress unc_s_rxr_bypass.bl_bnc uncore interconnect Bypass; BL - Bounces event=0x12,umask=8 01 Bypass the Sbo Ingress unc_s_rxr_bypass.bl_crd uncore interconnect Bypass; BL - Credits event=0x12,umask=4 01 Bypass the Sbo Ingress unc_s_rxr_bypass.iv uncore interconnect Bypass; IV event=0x12,umask=0x20 01 Bypass the Sbo Ingress unc_s_rxr_crd_starved.ad_bnc uncore interconnect Injection Starvation; AD - Bounces event=0x14,umask=2 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.ad_crd uncore interconnect Injection Starvation; AD - Credits event=0x14,umask=1 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.ak uncore interconnect Injection Starvation; AK event=0x14,umask=0x10 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.bl_bnc uncore interconnect Injection Starvation; BL - Bounces event=0x14,umask=8 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.bl_crd uncore interconnect Injection Starvation; BL - Credits event=0x14,umask=4 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.ifv uncore interconnect Injection Starvation; IVF Credit event=0x14,umask=0x40 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.iv uncore interconnect Injection Starvation; IV event=0x14,umask=0x20 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_inserts.ad_bnc uncore interconnect Ingress Allocations; AD - Bounces event=0x13,umask=2 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.ad_crd uncore interconnect Ingress Allocations; AD - Credits event=0x13,umask=1 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.ak uncore interconnect Ingress Allocations; AK event=0x13,umask=0x10 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.bl_bnc uncore interconnect Ingress Allocations; BL - Bounces event=0x13,umask=8 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.bl_crd uncore interconnect Ingress Allocations; BL - Credits event=0x13,umask=4 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.iv uncore interconnect Ingress Allocations; IV event=0x13,umask=0x20 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.ad_bnc uncore interconnect Ingress Occupancy; AD - Bounces event=0x11,umask=2 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.ad_crd uncore interconnect Ingress Occupancy; AD - Credits event=0x11,umask=1 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.ak uncore interconnect Ingress Occupancy; AK event=0x11,umask=0x10 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.bl_bnc uncore interconnect Ingress Occupancy; BL - Bounces event=0x11,umask=8 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.bl_crd uncore interconnect Ingress Occupancy; BL - Credits event=0x11,umask=4 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.iv uncore interconnect Ingress Occupancy; IV event=0x11,umask=0x20 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_txr_ads_used.ad uncore interconnect UNC_S_TxR_ADS_USED.AD event=4,umask=1 01 unc_s_txr_ads_used.ak uncore interconnect UNC_S_TxR_ADS_USED.AK event=4,umask=2 01 unc_s_txr_ads_used.bl uncore interconnect UNC_S_TxR_ADS_USED.BL event=4,umask=4 01 unc_s_txr_inserts.ad_bnc uncore interconnect Egress Allocations; AD - Bounces event=2,umask=2 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.ad_crd uncore interconnect Egress Allocations; AD - Credits event=2,umask=1 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.ak uncore interconnect Egress Allocations; AK event=2,umask=0x10 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.bl_bnc uncore interconnect Egress Allocations; BL - Bounces event=2,umask=8 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.bl_crd uncore interconnect Egress Allocations; BL - Credits event=2,umask=4 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.iv uncore interconnect Egress Allocations; IV event=2,umask=0x20 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_occupancy.ad_bnc uncore interconnect Egress Occupancy; AD - Bounces event=1,umask=2 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.ad_crd uncore interconnect Egress Occupancy; AD - Credits event=1,umask=1 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.ak uncore interconnect Egress Occupancy; AK event=1,umask=0x10 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.bl_bnc uncore interconnect Egress Occupancy; BL - Bounces event=1,umask=8 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.bl_crd uncore interconnect Egress Occupancy; BL - Credits event=1,umask=4 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.iv uncore interconnect Egress Occupancy; IV event=1,umask=0x20 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_starved.ad uncore interconnect Injection Starvation; Onto AD Ring event=3,umask=1 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_s_txr_starved.ak uncore interconnect Injection Starvation; Onto AK Ring event=3,umask=2 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_s_txr_starved.bl uncore interconnect Injection Starvation; Onto BL Ring event=3,umask=4 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_s_txr_starved.iv uncore interconnect Injection Starvation; Onto IV Ring event=3,umask=8 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_u_clockticks uncore interconnect Clockticks in the UBOX using a dedicated 48-bit Fixed Counter event=0xff 01 llc_misses.mem_read uncore memory read requests to memory controller. Derived from unc_m_cas_count.rd event=4,umask=3 0164Bytes DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills) llc_misses.mem_write uncore memory write requests to memory controller. Derived from unc_m_cas_count.wr event=4,umask=0xc 0164Bytes DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel unc_m_clockticks uncore memory Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter event=0xff 01 unc_m_clockticks_p uncore memory Clockticks in the Memory Controller using one of the programmable counters event=0 01 unc_m_dclockticks uncore memory This event is deprecated. Refer to new event UNC_M_CLOCKTICKS_P event=0 01 l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=1 00 Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace l1d_pend_miss.fb_full cache Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch event=0x48,period=2000003,umask=2 00 Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions l1d_pend_miss.pending cache L1D miss outstandings duration in cycles event=0x48,period=2000003,umask=1 00 Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=2000003,umask=1 00 Counts duration of L1D miss outstanding in cycles l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=0x1f 00 Counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_out.non_silent cache Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped event=0xf2,period=200003,umask=2 00 Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped l2_lines_out.silent cache Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event event=0xf2,period=200003,umask=1 00 l2_lines_out.useless_hwpf cache Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache event=0xf2,period=200003,umask=4 00 l2_lines_out.useless_pref cache This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF event=0xf2,period=200003,umask=4 10 l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=0xe1 00 Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache event=0x24,period=200003,umask=0x27 00 Demand requests that miss L2 cache l2_rqsts.all_demand_references cache Demand requests to L2 cache event=0x24,period=200003,umask=0xe7 00 Demand requests to L2 cache l2_rqsts.all_pf cache Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches event=0x24,period=200003,umask=0xf8 00 Counts the total number of requests from the L2 hardware prefetchers l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2, no rejects event=0x24,period=200003,umask=0x21 00 Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted l2_rqsts.miss cache All requests that miss L2 cache event=0x24,period=200003,umask=0x3f 00 All requests that miss L2 cache l2_rqsts.pf_hit cache Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache event=0x24,period=200003,umask=0xd8 00 Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache l2_rqsts.pf_miss cache Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache event=0x24,period=200003,umask=0x38 00 Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache l2_rqsts.references cache All L2 requests event=0x24,period=200003,umask=0xff 00 All L2 requests l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40 00 Counts L2 writebacks that access L2 cache longest_lat_cache.miss cache Core-originated cacheable demand requests missed L3 Spec update: SKL057 event=0x2e,period=100003,umask=0x41 00 Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3 Spec update: SKL057 longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to L3 Spec update: SKL057 event=0x2e,period=100003,umask=0x4f 00 Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3 Spec update: SKL057 mem_inst_retired.all_loads cache Retired load instructions Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x81 00 Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW Supports address when precise (Precise event) mem_inst_retired.all_stores cache Retired store instructions Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x82 00 Counts all retired store instructions Supports address when precise (Precise event) mem_inst_retired.any cache All retired memory instructions Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x83 00 Counts all retired memory instructions - loads and stores Supports address when precise (Precise event) mem_inst_retired.lock_loads cache Retired load instructions with locked access Supports address when precise (Precise event) event=0xd0,period=100007,umask=0x21 00 mem_load_l3_hit_retired.xsnp_hit cache Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) event=0xd2,period=20011,umask=2 00 Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hitm cache Retired load instructions which data sources were HitM responses from shared L3 Supports address when precise (Precise event) event=0xd2,period=20011,umask=4 00 Retired load instructions which data sources were HitM responses from shared L3 Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_miss cache Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) event=0xd2,period=20011,umask=1 00 mem_load_l3_hit_retired.xsnp_none cache Retired load instructions which data sources were hits in L3 without snoops required Supports address when precise (Precise event) event=0xd2,period=100003,umask=8 00 Retired load instructions which data sources were hits in L3 without snoops required Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_dram cache Retired load instructions which data sources missed L3 but serviced from remote dram Supports address when precise (Precise event) event=0xd3,period=100007,umask=2 00 mem_load_l3_miss_retired.remote_fwd cache Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise event=0xd3,period=100007,umask=8 00 Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise mem_load_l3_miss_retired.remote_hitm cache Retired load instructions whose data sources was remote HITM Supports address when precise (Precise event) event=0xd3,period=100007,umask=4 00 Retired load instructions whose data sources was remote HITM Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_pmm cache Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches Supports address when precise (Precise event) event=0xd3,period=100007,umask=0x10 00 Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode) Supports address when precise (Precise event) mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or lock Supports address when precise (Precise event) event=0xd4,period=100007,umask=4 00 mem_load_retired.fb_hit cache Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) event=0xd1,period=100007,umask=0x40 00 Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) mem_load_retired.l1_hit cache Retired load instructions with L1 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=2000003,umask=1 00 Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source Supports address when precise (Precise event) mem_load_retired.l1_miss cache Retired load instructions missed L1 cache as data sources Supports address when precise (Precise event) event=0xd1,period=100003,umask=8 00 Counts retired load instructions with at least one uop that missed in the L1 cache Supports address when precise (Precise event) mem_load_retired.l2_hit cache Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=100003,umask=2 00 Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) mem_load_retired.l2_miss cache Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) event=0xd1,period=50021,umask=0x10 00 Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) mem_load_retired.l3_hit cache Retired load instructions with L3 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=50021,umask=4 00 Counts retired load instructions with at least one uop that hit in the L3 cache Supports address when precise (Precise event) mem_load_retired.l3_miss cache Retired load instructions missed L3 cache as data sources Supports address when precise (Precise event) event=0xd1,period=100007,umask=0x20 00 Counts retired load instructions with at least one uop that missed in the L3 cache Supports address when precise (Precise event) mem_load_retired.local_pmm cache Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x80 00 Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode) Supports address when precise (Precise event) ocr.all_data_rd.l3_hit.any_snoop cache OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0491 00 ocr.all_data_rd.l3_hit.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0491 00 ocr.all_data_rd.l3_hit.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0491 00 ocr.all_data_rd.l3_hit.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0491 00 ocr.all_data_rd.l3_hit.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0491 00 ocr.all_data_rd.l3_hit.snoop_hit_with_fwd cache OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0491 00 ocr.all_data_rd.l3_hit.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0491 00 ocr.all_data_rd.l3_hit.snoop_none cache OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0491 00 ocr.all_data_rd.l3_hit_e.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080491 00 ocr.all_data_rd.l3_hit_e.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080491 00 ocr.all_data_rd.l3_hit_e.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080491 00 ocr.all_data_rd.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080491 00 ocr.all_data_rd.l3_hit_e.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080491 00 ocr.all_data_rd.l3_hit_e.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080491 00 ocr.all_data_rd.l3_hit_e.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080491 00 ocr.all_data_rd.l3_hit_f.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200491 00 ocr.all_data_rd.l3_hit_f.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200491 00 ocr.all_data_rd.l3_hit_f.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200491 00 ocr.all_data_rd.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200491 00 ocr.all_data_rd.l3_hit_f.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200491 00 ocr.all_data_rd.l3_hit_f.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200491 00 ocr.all_data_rd.l3_hit_f.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200491 00 ocr.all_data_rd.l3_hit_m.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040491 00 ocr.all_data_rd.l3_hit_m.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040491 00 ocr.all_data_rd.l3_hit_m.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040491 00 ocr.all_data_rd.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040491 00 ocr.all_data_rd.l3_hit_m.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040491 00 ocr.all_data_rd.l3_hit_m.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040491 00 ocr.all_data_rd.l3_hit_m.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040491 00 ocr.all_data_rd.l3_hit_s.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100491 00 ocr.all_data_rd.l3_hit_s.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100491 00 ocr.all_data_rd.l3_hit_s.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100491 00 ocr.all_data_rd.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100491 00 ocr.all_data_rd.l3_hit_s.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100491 00 ocr.all_data_rd.l3_hit_s.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100491 00 ocr.all_data_rd.l3_hit_s.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100491 00 ocr.all_pf_data_rd.l3_hit.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0490 00 ocr.all_pf_data_rd.l3_hit.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0490 00 ocr.all_pf_data_rd.l3_hit.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0490 00 ocr.all_pf_data_rd.l3_hit.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0490 00 ocr.all_pf_data_rd.l3_hit.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0490 00 ocr.all_pf_data_rd.l3_hit.snoop_hit_with_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0490 00 ocr.all_pf_data_rd.l3_hit.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0490 00 ocr.all_pf_data_rd.l3_hit.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0490 00 ocr.all_pf_data_rd.l3_hit_e.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080490 00 ocr.all_pf_data_rd.l3_hit_e.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080490 00 ocr.all_pf_data_rd.l3_hit_e.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080490 00 ocr.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080490 00 ocr.all_pf_data_rd.l3_hit_e.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080490 00 ocr.all_pf_data_rd.l3_hit_e.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080490 00 ocr.all_pf_data_rd.l3_hit_e.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080490 00 ocr.all_pf_data_rd.l3_hit_f.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200490 00 ocr.all_pf_data_rd.l3_hit_f.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200490 00 ocr.all_pf_data_rd.l3_hit_f.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200490 00 ocr.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200490 00 ocr.all_pf_data_rd.l3_hit_f.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200490 00 ocr.all_pf_data_rd.l3_hit_f.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200490 00 ocr.all_pf_data_rd.l3_hit_f.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200490 00 ocr.all_pf_data_rd.l3_hit_m.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040490 00 ocr.all_pf_data_rd.l3_hit_m.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040490 00 ocr.all_pf_data_rd.l3_hit_m.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040490 00 ocr.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040490 00 ocr.all_pf_data_rd.l3_hit_m.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040490 00 ocr.all_pf_data_rd.l3_hit_m.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040490 00 ocr.all_pf_data_rd.l3_hit_m.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040490 00 ocr.all_pf_data_rd.l3_hit_s.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100490 00 ocr.all_pf_data_rd.l3_hit_s.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100490 00 ocr.all_pf_data_rd.l3_hit_s.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100490 00 ocr.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100490 00 ocr.all_pf_data_rd.l3_hit_s.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100490 00 ocr.all_pf_data_rd.l3_hit_s.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100490 00 ocr.all_pf_data_rd.l3_hit_s.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100490 00 ocr.all_pf_rfo.l3_hit.any_snoop cache OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0120 00 ocr.all_pf_rfo.l3_hit.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0120 00 ocr.all_pf_rfo.l3_hit.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0120 00 ocr.all_pf_rfo.l3_hit.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0120 00 ocr.all_pf_rfo.l3_hit.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0120 00 ocr.all_pf_rfo.l3_hit.snoop_hit_with_fwd cache OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0120 00 ocr.all_pf_rfo.l3_hit.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0120 00 ocr.all_pf_rfo.l3_hit.snoop_none cache OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0120 00 ocr.all_pf_rfo.l3_hit_e.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080120 00 ocr.all_pf_rfo.l3_hit_e.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080120 00 ocr.all_pf_rfo.l3_hit_e.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080120 00 ocr.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080120 00 ocr.all_pf_rfo.l3_hit_e.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080120 00 ocr.all_pf_rfo.l3_hit_e.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080120 00 ocr.all_pf_rfo.l3_hit_e.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080120 00 ocr.all_pf_rfo.l3_hit_f.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200120 00 ocr.all_pf_rfo.l3_hit_f.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200120 00 ocr.all_pf_rfo.l3_hit_f.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200120 00 ocr.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200120 00 ocr.all_pf_rfo.l3_hit_f.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200120 00 ocr.all_pf_rfo.l3_hit_f.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200120 00 ocr.all_pf_rfo.l3_hit_f.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200120 00 ocr.all_pf_rfo.l3_hit_m.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040120 00 ocr.all_pf_rfo.l3_hit_m.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040120 00 ocr.all_pf_rfo.l3_hit_m.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040120 00 ocr.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040120 00 ocr.all_pf_rfo.l3_hit_m.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040120 00 ocr.all_pf_rfo.l3_hit_m.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040120 00 ocr.all_pf_rfo.l3_hit_m.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040120 00 ocr.all_pf_rfo.l3_hit_s.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100120 00 ocr.all_pf_rfo.l3_hit_s.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100120 00 ocr.all_pf_rfo.l3_hit_s.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100120 00 ocr.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100120 00 ocr.all_pf_rfo.l3_hit_s.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100120 00 ocr.all_pf_rfo.l3_hit_s.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100120 00 ocr.all_pf_rfo.l3_hit_s.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100120 00 ocr.all_reads.l3_hit.any_snoop cache OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C07F7 00 ocr.all_reads.l3_hit.hitm_other_core cache OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C07F7 00 ocr.all_reads.l3_hit.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C07F7 00 ocr.all_reads.l3_hit.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C07F7 00 ocr.all_reads.l3_hit.no_snoop_needed cache OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C07F7 00 ocr.all_reads.l3_hit.snoop_hit_with_fwd cache OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C07F7 00 ocr.all_reads.l3_hit.snoop_miss cache OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C07F7 00 ocr.all_reads.l3_hit.snoop_none cache OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C07F7 00 ocr.all_reads.l3_hit_e.any_snoop cache OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800807F7 00 ocr.all_reads.l3_hit_e.hitm_other_core cache OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000807F7 00 ocr.all_reads.l3_hit_e.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000807F7 00 ocr.all_reads.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000807F7 00 ocr.all_reads.l3_hit_e.no_snoop_needed cache OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000807F7 00 ocr.all_reads.l3_hit_e.snoop_miss cache OCR.ALL_READS.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000807F7 00 ocr.all_reads.l3_hit_e.snoop_none cache OCR.ALL_READS.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800807F7 00 ocr.all_reads.l3_hit_f.any_snoop cache OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F802007F7 00 ocr.all_reads.l3_hit_f.hitm_other_core cache OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10002007F7 00 ocr.all_reads.l3_hit_f.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8002007F7 00 ocr.all_reads.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4002007F7 00 ocr.all_reads.l3_hit_f.no_snoop_needed cache OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1002007F7 00 ocr.all_reads.l3_hit_f.snoop_miss cache OCR.ALL_READS.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2002007F7 00 ocr.all_reads.l3_hit_f.snoop_none cache OCR.ALL_READS.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x802007F7 00 ocr.all_reads.l3_hit_m.any_snoop cache OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800407F7 00 ocr.all_reads.l3_hit_m.hitm_other_core cache OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000407F7 00 ocr.all_reads.l3_hit_m.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000407F7 00 ocr.all_reads.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000407F7 00 ocr.all_reads.l3_hit_m.no_snoop_needed cache OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000407F7 00 ocr.all_reads.l3_hit_m.snoop_miss cache OCR.ALL_READS.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000407F7 00 ocr.all_reads.l3_hit_m.snoop_none cache OCR.ALL_READS.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800407F7 00 ocr.all_reads.l3_hit_s.any_snoop cache OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F801007F7 00 ocr.all_reads.l3_hit_s.hitm_other_core cache OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10001007F7 00 ocr.all_reads.l3_hit_s.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8001007F7 00 ocr.all_reads.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4001007F7 00 ocr.all_reads.l3_hit_s.no_snoop_needed cache OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1001007F7 00 ocr.all_reads.l3_hit_s.snoop_miss cache OCR.ALL_READS.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2001007F7 00 ocr.all_reads.l3_hit_s.snoop_none cache OCR.ALL_READS.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x801007F7 00 ocr.all_rfo.l3_hit.any_snoop cache OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0122 00 ocr.all_rfo.l3_hit.hitm_other_core cache OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122 00 ocr.all_rfo.l3_hit.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0122 00 ocr.all_rfo.l3_hit.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122 00 ocr.all_rfo.l3_hit.no_snoop_needed cache OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0122 00 ocr.all_rfo.l3_hit.snoop_hit_with_fwd cache OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0122 00 ocr.all_rfo.l3_hit.snoop_miss cache OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0122 00 ocr.all_rfo.l3_hit.snoop_none cache OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0122 00 ocr.all_rfo.l3_hit_e.any_snoop cache OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080122 00 ocr.all_rfo.l3_hit_e.hitm_other_core cache OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080122 00 ocr.all_rfo.l3_hit_e.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080122 00 ocr.all_rfo.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080122 00 ocr.all_rfo.l3_hit_e.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080122 00 ocr.all_rfo.l3_hit_e.snoop_miss cache OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080122 00 ocr.all_rfo.l3_hit_e.snoop_none cache OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080122 00 ocr.all_rfo.l3_hit_f.any_snoop cache OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200122 00 ocr.all_rfo.l3_hit_f.hitm_other_core cache OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200122 00 ocr.all_rfo.l3_hit_f.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200122 00 ocr.all_rfo.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200122 00 ocr.all_rfo.l3_hit_f.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200122 00 ocr.all_rfo.l3_hit_f.snoop_miss cache OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200122 00 ocr.all_rfo.l3_hit_f.snoop_none cache OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200122 00 ocr.all_rfo.l3_hit_m.any_snoop cache OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040122 00 ocr.all_rfo.l3_hit_m.hitm_other_core cache OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040122 00 ocr.all_rfo.l3_hit_m.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040122 00 ocr.all_rfo.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040122 00 ocr.all_rfo.l3_hit_m.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040122 00 ocr.all_rfo.l3_hit_m.snoop_miss cache OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040122 00 ocr.all_rfo.l3_hit_m.snoop_none cache OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040122 00 ocr.all_rfo.l3_hit_s.any_snoop cache OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100122 00 ocr.all_rfo.l3_hit_s.hitm_other_core cache OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100122 00 ocr.all_rfo.l3_hit_s.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100122 00 ocr.all_rfo.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100122 00 ocr.all_rfo.l3_hit_s.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100122 00 ocr.all_rfo.l3_hit_s.snoop_miss cache OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100122 00 ocr.all_rfo.l3_hit_s.snoop_none cache OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100122 00 ocr.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004 00 ocr.demand_code_rd.l3_hit.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004 00 ocr.demand_code_rd.l3_hit.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0004 00 ocr.demand_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004 00 ocr.demand_code_rd.l3_hit.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004 00 ocr.demand_code_rd.l3_hit.snoop_hit_with_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0004 00 ocr.demand_code_rd.l3_hit.snoop_miss cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0004 00 ocr.demand_code_rd.l3_hit.snoop_none cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0004 00 ocr.demand_code_rd.l3_hit_e.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080004 00 ocr.demand_code_rd.l3_hit_e.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080004 00 ocr.demand_code_rd.l3_hit_e.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080004 00 ocr.demand_code_rd.l3_hit_e.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080004 00 ocr.demand_code_rd.l3_hit_e.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080004 00 ocr.demand_code_rd.l3_hit_e.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080004 00 ocr.demand_code_rd.l3_hit_e.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080004 00 ocr.demand_code_rd.l3_hit_f.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200004 00 ocr.demand_code_rd.l3_hit_f.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200004 00 ocr.demand_code_rd.l3_hit_f.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200004 00 ocr.demand_code_rd.l3_hit_f.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200004 00 ocr.demand_code_rd.l3_hit_f.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200004 00 ocr.demand_code_rd.l3_hit_f.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200200004 00 ocr.demand_code_rd.l3_hit_f.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80200004 00 ocr.demand_code_rd.l3_hit_m.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040004 00 ocr.demand_code_rd.l3_hit_m.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040004 00 ocr.demand_code_rd.l3_hit_m.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040004 00 ocr.demand_code_rd.l3_hit_m.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040004 00 ocr.demand_code_rd.l3_hit_m.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040004 00 ocr.demand_code_rd.l3_hit_m.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040004 00 ocr.demand_code_rd.l3_hit_m.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040004 00 ocr.demand_code_rd.l3_hit_s.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100004 00 ocr.demand_code_rd.l3_hit_s.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100004 00 ocr.demand_code_rd.l3_hit_s.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100004 00 ocr.demand_code_rd.l3_hit_s.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100004 00 ocr.demand_code_rd.l3_hit_s.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100004 00 ocr.demand_code_rd.l3_hit_s.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100004 00 ocr.demand_code_rd.l3_hit_s.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100004 00 ocr.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001 00 ocr.demand_data_rd.l3_hit.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001 00 ocr.demand_data_rd.l3_hit.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 00 ocr.demand_data_rd.l3_hit.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0001 00 ocr.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001 00 ocr.demand_data_rd.l3_hit.snoop_none cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0001 00 ocr.demand_data_rd.l3_hit_e.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080001 00 ocr.demand_data_rd.l3_hit_e.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080001 00 ocr.demand_data_rd.l3_hit_e.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080001 00 ocr.demand_data_rd.l3_hit_e.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080001 00 ocr.demand_data_rd.l3_hit_e.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080001 00 ocr.demand_data_rd.l3_hit_e.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080001 00 ocr.demand_data_rd.l3_hit_e.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080001 00 ocr.demand_data_rd.l3_hit_f.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200001 00 ocr.demand_data_rd.l3_hit_f.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200001 00 ocr.demand_data_rd.l3_hit_f.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200001 00 ocr.demand_data_rd.l3_hit_f.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200001 00 ocr.demand_data_rd.l3_hit_f.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200001 00 ocr.demand_data_rd.l3_hit_f.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200200001 00 ocr.demand_data_rd.l3_hit_f.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80200001 00 ocr.demand_data_rd.l3_hit_m.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040001 00 ocr.demand_data_rd.l3_hit_m.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040001 00 ocr.demand_data_rd.l3_hit_m.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040001 00 ocr.demand_data_rd.l3_hit_m.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040001 00 ocr.demand_data_rd.l3_hit_m.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040001 00 ocr.demand_data_rd.l3_hit_m.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040001 00 ocr.demand_data_rd.l3_hit_m.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040001 00 ocr.demand_data_rd.l3_hit_s.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100001 00 ocr.demand_data_rd.l3_hit_s.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100001 00 ocr.demand_data_rd.l3_hit_s.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100001 00 ocr.demand_data_rd.l3_hit_s.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100001 00 ocr.demand_data_rd.l3_hit_s.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100001 00 ocr.demand_data_rd.l3_hit_s.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100001 00 ocr.demand_data_rd.l3_hit_s.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100001 00 ocr.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002 00 ocr.demand_rfo.l3_hit.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002 00 ocr.demand_rfo.l3_hit.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0002 00 ocr.demand_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002 00 ocr.demand_rfo.l3_hit.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002 00 ocr.demand_rfo.l3_hit.snoop_hit_with_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0002 00 ocr.demand_rfo.l3_hit.snoop_miss cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0002 00 ocr.demand_rfo.l3_hit.snoop_none cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0002 00 ocr.demand_rfo.l3_hit_e.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080002 00 ocr.demand_rfo.l3_hit_e.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080002 00 ocr.demand_rfo.l3_hit_e.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080002 00 ocr.demand_rfo.l3_hit_e.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080002 00 ocr.demand_rfo.l3_hit_e.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080002 00 ocr.demand_rfo.l3_hit_e.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200080002 00 ocr.demand_rfo.l3_hit_e.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80080002 00 ocr.demand_rfo.l3_hit_f.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200002 00 ocr.demand_rfo.l3_hit_f.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200002 00 ocr.demand_rfo.l3_hit_f.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200002 00 ocr.demand_rfo.l3_hit_f.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200002 00 ocr.demand_rfo.l3_hit_f.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200002 00 ocr.demand_rfo.l3_hit_f.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200200002 00 ocr.demand_rfo.l3_hit_f.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80200002 00 ocr.demand_rfo.l3_hit_m.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040002 00 ocr.demand_rfo.l3_hit_m.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040002 00 ocr.demand_rfo.l3_hit_m.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040002 00 ocr.demand_rfo.l3_hit_m.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040002 00 ocr.demand_rfo.l3_hit_m.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040002 00 ocr.demand_rfo.l3_hit_m.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200040002 00 ocr.demand_rfo.l3_hit_m.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80040002 00 ocr.demand_rfo.l3_hit_s.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100002 00 ocr.demand_rfo.l3_hit_s.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100002 00 ocr.demand_rfo.l3_hit_s.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100002 00 ocr.demand_rfo.l3_hit_s.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100002 00 ocr.demand_rfo.l3_hit_s.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100002 00 ocr.demand_rfo.l3_hit_s.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200100002 00 ocr.demand_rfo.l3_hit_s.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80100002 00 ocr.other.l3_hit.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C8000 00 ocr.other.l3_hit.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C8000 00 ocr.other.l3_hit.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C8000 00 ocr.other.l3_hit.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C8000 00 ocr.other.l3_hit.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C8000 00 ocr.other.l3_hit.snoop_hit_with_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C8000 00 ocr.other.l3_hit.snoop_miss cache Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C8000 00 ocr.other.l3_hit.snoop_none cache Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C8000 00 ocr.other.l3_hit_e.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80088000 00 ocr.other.l3_hit_e.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000088000 00 ocr.other.l3_hit_e.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800088000 00 ocr.other.l3_hit_e.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400088000 00 ocr.other.l3_hit_e.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100088000 00 ocr.other.l3_hit_e.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200088000 00 ocr.other.l3_hit_e.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80088000 00 ocr.other.l3_hit_f.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80208000 00 ocr.other.l3_hit_f.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000208000 00 ocr.other.l3_hit_f.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800208000 00 ocr.other.l3_hit_f.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400208000 00 ocr.other.l3_hit_f.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100208000 00 ocr.other.l3_hit_f.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200208000 00 ocr.other.l3_hit_f.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80208000 00 ocr.other.l3_hit_m.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80048000 00 ocr.other.l3_hit_m.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000048000 00 ocr.other.l3_hit_m.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800048000 00 ocr.other.l3_hit_m.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400048000 00 ocr.other.l3_hit_m.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100048000 00 ocr.other.l3_hit_m.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200048000 00 ocr.other.l3_hit_m.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80048000 00 ocr.other.l3_hit_s.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80108000 00 ocr.other.l3_hit_s.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000108000 00 ocr.other.l3_hit_s.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800108000 00 ocr.other.l3_hit_s.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400108000 00 ocr.other.l3_hit_s.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100108000 00 ocr.other.l3_hit_s.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200108000 00 ocr.other.l3_hit_s.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80108000 00 ocr.pf_l1d_and_sw.l3_hit.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0400 00 ocr.pf_l1d_and_sw.l3_hit.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0400 00 ocr.pf_l1d_and_sw.l3_hit.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0400 00 ocr.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0400 00 ocr.pf_l1d_and_sw.l3_hit.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0400 00 ocr.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0400 00 ocr.pf_l1d_and_sw.l3_hit.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0400 00 ocr.pf_l1d_and_sw.l3_hit.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0400 00 ocr.pf_l1d_and_sw.l3_hit_e.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080400 00 ocr.pf_l1d_and_sw.l3_hit_e.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080400 00 ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080400 00 ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080400 00 ocr.pf_l1d_and_sw.l3_hit_e.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080400 00 ocr.pf_l1d_and_sw.l3_hit_e.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200080400 00 ocr.pf_l1d_and_sw.l3_hit_e.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80080400 00 ocr.pf_l1d_and_sw.l3_hit_f.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200400 00 ocr.pf_l1d_and_sw.l3_hit_f.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200400 00 ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200400 00 ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200400 00 ocr.pf_l1d_and_sw.l3_hit_f.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200400 00 ocr.pf_l1d_and_sw.l3_hit_f.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200200400 00 ocr.pf_l1d_and_sw.l3_hit_f.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80200400 00 ocr.pf_l1d_and_sw.l3_hit_m.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040400 00 ocr.pf_l1d_and_sw.l3_hit_m.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040400 00 ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040400 00 ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040400 00 ocr.pf_l1d_and_sw.l3_hit_m.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040400 00 ocr.pf_l1d_and_sw.l3_hit_m.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200040400 00 ocr.pf_l1d_and_sw.l3_hit_m.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80040400 00 ocr.pf_l1d_and_sw.l3_hit_s.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100400 00 ocr.pf_l1d_and_sw.l3_hit_s.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100400 00 ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100400 00 ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100400 00 ocr.pf_l1d_and_sw.l3_hit_s.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100400 00 ocr.pf_l1d_and_sw.l3_hit_s.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200100400 00 ocr.pf_l1d_and_sw.l3_hit_s.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80100400 00 ocr.pf_l2_data_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010 00 ocr.pf_l2_data_rd.l3_hit.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010 00 ocr.pf_l2_data_rd.l3_hit.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0010 00 ocr.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010 00 ocr.pf_l2_data_rd.l3_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010 00 ocr.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0010 00 ocr.pf_l2_data_rd.l3_hit.snoop_miss cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0010 00 ocr.pf_l2_data_rd.l3_hit.snoop_none cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0010 00 ocr.pf_l2_data_rd.l3_hit_e.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080010 00 ocr.pf_l2_data_rd.l3_hit_e.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080010 00 ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080010 00 ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080010 00 ocr.pf_l2_data_rd.l3_hit_e.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080010 00 ocr.pf_l2_data_rd.l3_hit_e.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080010 00 ocr.pf_l2_data_rd.l3_hit_e.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080010 00 ocr.pf_l2_data_rd.l3_hit_f.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200010 00 ocr.pf_l2_data_rd.l3_hit_f.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200010 00 ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200010 00 ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200010 00 ocr.pf_l2_data_rd.l3_hit_f.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200010 00 ocr.pf_l2_data_rd.l3_hit_f.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200200010 00 ocr.pf_l2_data_rd.l3_hit_f.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80200010 00 ocr.pf_l2_data_rd.l3_hit_m.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040010 00 ocr.pf_l2_data_rd.l3_hit_m.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040010 00 ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040010 00 ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040010 00 ocr.pf_l2_data_rd.l3_hit_m.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040010 00 ocr.pf_l2_data_rd.l3_hit_m.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040010 00 ocr.pf_l2_data_rd.l3_hit_m.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040010 00 ocr.pf_l2_data_rd.l3_hit_s.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100010 00 ocr.pf_l2_data_rd.l3_hit_s.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100010 00 ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100010 00 ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100010 00 ocr.pf_l2_data_rd.l3_hit_s.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100010 00 ocr.pf_l2_data_rd.l3_hit_s.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100010 00 ocr.pf_l2_data_rd.l3_hit_s.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100010 00 ocr.pf_l2_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020 00 ocr.pf_l2_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020 00 ocr.pf_l2_rfo.l3_hit.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0020 00 ocr.pf_l2_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020 00 ocr.pf_l2_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020 00 ocr.pf_l2_rfo.l3_hit.snoop_hit_with_fwd cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0020 00 ocr.pf_l2_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0020 00 ocr.pf_l2_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0020 00 ocr.pf_l2_rfo.l3_hit_e.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080020 00 ocr.pf_l2_rfo.l3_hit_e.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080020 00 ocr.pf_l2_rfo.l3_hit_e.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080020 00 ocr.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080020 00 ocr.pf_l2_rfo.l3_hit_e.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080020 00 ocr.pf_l2_rfo.l3_hit_e.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200080020 00 ocr.pf_l2_rfo.l3_hit_e.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80080020 00 ocr.pf_l2_rfo.l3_hit_f.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200020 00 ocr.pf_l2_rfo.l3_hit_f.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200020 00 ocr.pf_l2_rfo.l3_hit_f.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200020 00 ocr.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200020 00 ocr.pf_l2_rfo.l3_hit_f.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200020 00 ocr.pf_l2_rfo.l3_hit_f.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200200020 00 ocr.pf_l2_rfo.l3_hit_f.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80200020 00 ocr.pf_l2_rfo.l3_hit_m.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040020 00 ocr.pf_l2_rfo.l3_hit_m.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040020 00 ocr.pf_l2_rfo.l3_hit_m.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040020 00 ocr.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040020 00 ocr.pf_l2_rfo.l3_hit_m.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040020 00 ocr.pf_l2_rfo.l3_hit_m.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200040020 00 ocr.pf_l2_rfo.l3_hit_m.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80040020 00 ocr.pf_l2_rfo.l3_hit_s.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100020 00 ocr.pf_l2_rfo.l3_hit_s.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100020 00 ocr.pf_l2_rfo.l3_hit_s.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100020 00 ocr.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100020 00 ocr.pf_l2_rfo.l3_hit_s.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100020 00 ocr.pf_l2_rfo.l3_hit_s.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200100020 00 ocr.pf_l2_rfo.l3_hit_s.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80100020 00 ocr.pf_l3_data_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080 00 ocr.pf_l3_data_rd.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0080 00 ocr.pf_l3_data_rd.l3_hit.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0080 00 ocr.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0080 00 ocr.pf_l3_data_rd.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0080 00 ocr.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0080 00 ocr.pf_l3_data_rd.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0080 00 ocr.pf_l3_data_rd.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0080 00 ocr.pf_l3_data_rd.l3_hit_e.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080080 00 ocr.pf_l3_data_rd.l3_hit_e.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080080 00 ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080080 00 ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080080 00 ocr.pf_l3_data_rd.l3_hit_e.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080080 00 ocr.pf_l3_data_rd.l3_hit_e.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080080 00 ocr.pf_l3_data_rd.l3_hit_e.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080080 00 ocr.pf_l3_data_rd.l3_hit_f.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200080 00 ocr.pf_l3_data_rd.l3_hit_f.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200080 00 ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200080 00 ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200080 00 ocr.pf_l3_data_rd.l3_hit_f.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200080 00 ocr.pf_l3_data_rd.l3_hit_f.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200200080 00 ocr.pf_l3_data_rd.l3_hit_f.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80200080 00 ocr.pf_l3_data_rd.l3_hit_m.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040080 00 ocr.pf_l3_data_rd.l3_hit_m.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040080 00 ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040080 00 ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040080 00 ocr.pf_l3_data_rd.l3_hit_m.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040080 00 ocr.pf_l3_data_rd.l3_hit_m.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040080 00 ocr.pf_l3_data_rd.l3_hit_m.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040080 00 ocr.pf_l3_data_rd.l3_hit_s.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100080 00 ocr.pf_l3_data_rd.l3_hit_s.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100080 00 ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100080 00 ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100080 00 ocr.pf_l3_data_rd.l3_hit_s.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100080 00 ocr.pf_l3_data_rd.l3_hit_s.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100080 00 ocr.pf_l3_data_rd.l3_hit_s.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100080 00 ocr.pf_l3_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100 00 ocr.pf_l3_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0100 00 ocr.pf_l3_rfo.l3_hit.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0100 00 ocr.pf_l3_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0100 00 ocr.pf_l3_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0100 00 ocr.pf_l3_rfo.l3_hit.snoop_hit_with_fwd cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0100 00 ocr.pf_l3_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0100 00 ocr.pf_l3_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0100 00 ocr.pf_l3_rfo.l3_hit_e.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080100 00 ocr.pf_l3_rfo.l3_hit_e.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080100 00 ocr.pf_l3_rfo.l3_hit_e.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080100 00 ocr.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080100 00 ocr.pf_l3_rfo.l3_hit_e.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080100 00 ocr.pf_l3_rfo.l3_hit_e.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200080100 00 ocr.pf_l3_rfo.l3_hit_e.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80080100 00 ocr.pf_l3_rfo.l3_hit_f.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200100 00 ocr.pf_l3_rfo.l3_hit_f.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200100 00 ocr.pf_l3_rfo.l3_hit_f.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200100 00 ocr.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200100 00 ocr.pf_l3_rfo.l3_hit_f.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200100 00 ocr.pf_l3_rfo.l3_hit_f.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200200100 00 ocr.pf_l3_rfo.l3_hit_f.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80200100 00 ocr.pf_l3_rfo.l3_hit_m.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040100 00 ocr.pf_l3_rfo.l3_hit_m.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040100 00 ocr.pf_l3_rfo.l3_hit_m.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040100 00 ocr.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040100 00 ocr.pf_l3_rfo.l3_hit_m.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040100 00 ocr.pf_l3_rfo.l3_hit_m.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200040100 00 ocr.pf_l3_rfo.l3_hit_m.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80040100 00 ocr.pf_l3_rfo.l3_hit_s.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100100 00 ocr.pf_l3_rfo.l3_hit_s.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100100 00 ocr.pf_l3_rfo.l3_hit_s.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100100 00 ocr.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100100 00 ocr.pf_l3_rfo.l3_hit_s.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100100 00 ocr.pf_l3_rfo.l3_hit_s.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200100100 00 ocr.pf_l3_rfo.l3_hit_s.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80100100 00 offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=8 00 Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests.all_requests cache Any memory transaction that reached the SQ event=0xb0,period=100003,umask=0x80 00 Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc. offcore_requests.demand_code_rd cache Cacheable and non-cacheable code read requests event=0xb0,period=100003,umask=2 00 Counts both cacheable and non-cacheable code read requests offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=1 00 Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=4 00 Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_requests_buffer.sq_full cache Offcore requests buffer cannot take more entries for this thread core event=0xb2,period=2000003,umask=1 00 Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=8 00 Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=8 00 Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_code_rd cache Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=2 00 Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=1 00 Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=4 00 Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_code_rd cache Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle event=0x60,period=2000003,umask=2 00 Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue event=0x60,period=2000003,umask=1 00 Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue event=0x60,cmask=6,period=2000003,umask=1 00 offcore_requests_outstanding.demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,period=2000003,umask=4 00 Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_response.all_data_rd.any_response cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10491 10 offcore_response.all_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0491 10 offcore_response.all_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0491 10 offcore_response.all_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0491 10 offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0491 10 offcore_response.all_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0491 10 offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0491 10 offcore_response.all_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0491 10 offcore_response.all_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0491 10 offcore_response.all_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080491 10 offcore_response.all_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080491 10 offcore_response.all_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080491 10 offcore_response.all_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080491 10 offcore_response.all_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080491 10 offcore_response.all_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080491 10 offcore_response.all_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080491 10 offcore_response.all_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200491 10 offcore_response.all_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200491 10 offcore_response.all_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200491 10 offcore_response.all_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200491 10 offcore_response.all_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200491 10 offcore_response.all_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200491 10 offcore_response.all_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200491 10 offcore_response.all_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040491 10 offcore_response.all_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040491 10 offcore_response.all_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040491 10 offcore_response.all_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040491 10 offcore_response.all_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040491 10 offcore_response.all_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040491 10 offcore_response.all_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040491 10 offcore_response.all_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100491 10 offcore_response.all_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100491 10 offcore_response.all_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100491 10 offcore_response.all_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100491 10 offcore_response.all_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100491 10 offcore_response.all_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100491 10 offcore_response.all_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100491 10 offcore_response.all_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400491 10 offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400491 10 offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400491 10 offcore_response.all_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020491 10 offcore_response.all_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020491 10 offcore_response.all_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020491 10 offcore_response.all_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020491 10 offcore_response.all_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020491 10 offcore_response.all_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020491 10 offcore_response.all_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020491 10 offcore_response.all_pf_data_rd.any_response cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10490 10 offcore_response.all_pf_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0490 10 offcore_response.all_pf_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0490 10 offcore_response.all_pf_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0490 10 offcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0490 10 offcore_response.all_pf_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0490 10 offcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0490 10 offcore_response.all_pf_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0490 10 offcore_response.all_pf_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0490 10 offcore_response.all_pf_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080490 10 offcore_response.all_pf_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080490 10 offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080490 10 offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080490 10 offcore_response.all_pf_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080490 10 offcore_response.all_pf_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080490 10 offcore_response.all_pf_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080490 10 offcore_response.all_pf_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200490 10 offcore_response.all_pf_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200490 10 offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200490 10 offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200490 10 offcore_response.all_pf_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200490 10 offcore_response.all_pf_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200490 10 offcore_response.all_pf_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200490 10 offcore_response.all_pf_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040490 10 offcore_response.all_pf_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040490 10 offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040490 10 offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040490 10 offcore_response.all_pf_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040490 10 offcore_response.all_pf_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040490 10 offcore_response.all_pf_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040490 10 offcore_response.all_pf_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100490 10 offcore_response.all_pf_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100490 10 offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100490 10 offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100490 10 offcore_response.all_pf_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100490 10 offcore_response.all_pf_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100490 10 offcore_response.all_pf_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100490 10 offcore_response.all_pf_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400490 10 offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400490 10 offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400490 10 offcore_response.all_pf_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020490 10 offcore_response.all_pf_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020490 10 offcore_response.all_pf_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020490 10 offcore_response.all_pf_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020490 10 offcore_response.all_pf_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020490 10 offcore_response.all_pf_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020490 10 offcore_response.all_pf_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020490 10 offcore_response.all_pf_rfo.any_response cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10120 10 offcore_response.all_pf_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0120 10 offcore_response.all_pf_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0120 10 offcore_response.all_pf_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0120 10 offcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0120 10 offcore_response.all_pf_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0120 10 offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0120 10 offcore_response.all_pf_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0120 10 offcore_response.all_pf_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0120 10 offcore_response.all_pf_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080120 10 offcore_response.all_pf_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080120 10 offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080120 10 offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080120 10 offcore_response.all_pf_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080120 10 offcore_response.all_pf_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080120 10 offcore_response.all_pf_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080120 10 offcore_response.all_pf_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200120 10 offcore_response.all_pf_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200120 10 offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200120 10 offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200120 10 offcore_response.all_pf_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200120 10 offcore_response.all_pf_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200120 10 offcore_response.all_pf_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200120 10 offcore_response.all_pf_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040120 10 offcore_response.all_pf_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040120 10 offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040120 10 offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040120 10 offcore_response.all_pf_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040120 10 offcore_response.all_pf_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040120 10 offcore_response.all_pf_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040120 10 offcore_response.all_pf_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100120 10 offcore_response.all_pf_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100120 10 offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100120 10 offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100120 10 offcore_response.all_pf_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100120 10 offcore_response.all_pf_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100120 10 offcore_response.all_pf_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100120 10 offcore_response.all_pf_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400120 10 offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400120 10 offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400120 10 offcore_response.all_pf_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020120 10 offcore_response.all_pf_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020120 10 offcore_response.all_pf_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020120 10 offcore_response.all_pf_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020120 10 offcore_response.all_pf_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020120 10 offcore_response.all_pf_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020120 10 offcore_response.all_pf_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020120 10 offcore_response.all_reads.any_response cache This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x107F7 10 offcore_response.all_reads.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C07F7 10 offcore_response.all_reads.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C07F7 10 offcore_response.all_reads.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C07F7 10 offcore_response.all_reads.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C07F7 10 offcore_response.all_reads.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C07F7 10 offcore_response.all_reads.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C07F7 10 offcore_response.all_reads.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C07F7 10 offcore_response.all_reads.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C07F7 10 offcore_response.all_reads.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800807F7 10 offcore_response.all_reads.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000807F7 10 offcore_response.all_reads.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000807F7 10 offcore_response.all_reads.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000807F7 10 offcore_response.all_reads.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000807F7 10 offcore_response.all_reads.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000807F7 10 offcore_response.all_reads.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800807F7 10 offcore_response.all_reads.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F802007F7 10 offcore_response.all_reads.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10002007F7 10 offcore_response.all_reads.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8002007F7 10 offcore_response.all_reads.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4002007F7 10 offcore_response.all_reads.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1002007F7 10 offcore_response.all_reads.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2002007F7 10 offcore_response.all_reads.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x802007F7 10 offcore_response.all_reads.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800407F7 10 offcore_response.all_reads.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000407F7 10 offcore_response.all_reads.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000407F7 10 offcore_response.all_reads.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000407F7 10 offcore_response.all_reads.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000407F7 10 offcore_response.all_reads.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000407F7 10 offcore_response.all_reads.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800407F7 10 offcore_response.all_reads.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F801007F7 10 offcore_response.all_reads.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10001007F7 10 offcore_response.all_reads.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8001007F7 10 offcore_response.all_reads.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4001007F7 10 offcore_response.all_reads.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1001007F7 10 offcore_response.all_reads.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2001007F7 10 offcore_response.all_reads.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x801007F7 10 offcore_response.all_reads.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F804007F7 10 offcore_response.all_reads.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x804007F7 10 offcore_response.all_reads.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1004007F7 10 offcore_response.all_reads.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800207F7 10 offcore_response.all_reads.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000207F7 10 offcore_response.all_reads.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000207F7 10 offcore_response.all_reads.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000207F7 10 offcore_response.all_reads.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000207F7 10 offcore_response.all_reads.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000207F7 10 offcore_response.all_reads.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800207F7 10 offcore_response.all_rfo.any_response cache This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10122 10 offcore_response.all_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0122 10 offcore_response.all_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122 10 offcore_response.all_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0122 10 offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122 10 offcore_response.all_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0122 10 offcore_response.all_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0122 10 offcore_response.all_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0122 10 offcore_response.all_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0122 10 offcore_response.all_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080122 10 offcore_response.all_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080122 10 offcore_response.all_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080122 10 offcore_response.all_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080122 10 offcore_response.all_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080122 10 offcore_response.all_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080122 10 offcore_response.all_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080122 10 offcore_response.all_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200122 10 offcore_response.all_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200122 10 offcore_response.all_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200122 10 offcore_response.all_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200122 10 offcore_response.all_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200122 10 offcore_response.all_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200122 10 offcore_response.all_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200122 10 offcore_response.all_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040122 10 offcore_response.all_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040122 10 offcore_response.all_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040122 10 offcore_response.all_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040122 10 offcore_response.all_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040122 10 offcore_response.all_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040122 10 offcore_response.all_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040122 10 offcore_response.all_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100122 10 offcore_response.all_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100122 10 offcore_response.all_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100122 10 offcore_response.all_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100122 10 offcore_response.all_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100122 10 offcore_response.all_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100122 10 offcore_response.all_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100122 10 offcore_response.all_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400122 10 offcore_response.all_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400122 10 offcore_response.all_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400122 10 offcore_response.all_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020122 10 offcore_response.all_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020122 10 offcore_response.all_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020122 10 offcore_response.all_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020122 10 offcore_response.all_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020122 10 offcore_response.all_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020122 10 offcore_response.all_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020122 10 offcore_response.demand_code_rd.any_response cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10004 10 offcore_response.demand_code_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004 10 offcore_response.demand_code_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004 10 offcore_response.demand_code_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0004 10 offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004 10 offcore_response.demand_code_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004 10 offcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0004 10 offcore_response.demand_code_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0004 10 offcore_response.demand_code_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0004 10 offcore_response.demand_code_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080004 10 offcore_response.demand_code_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080004 10 offcore_response.demand_code_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080004 10 offcore_response.demand_code_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080004 10 offcore_response.demand_code_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080004 10 offcore_response.demand_code_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080004 10 offcore_response.demand_code_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080004 10 offcore_response.demand_code_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200004 10 offcore_response.demand_code_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200004 10 offcore_response.demand_code_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200004 10 offcore_response.demand_code_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200004 10 offcore_response.demand_code_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200004 10 offcore_response.demand_code_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200004 10 offcore_response.demand_code_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200004 10 offcore_response.demand_code_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040004 10 offcore_response.demand_code_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040004 10 offcore_response.demand_code_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040004 10 offcore_response.demand_code_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040004 10 offcore_response.demand_code_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040004 10 offcore_response.demand_code_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040004 10 offcore_response.demand_code_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040004 10 offcore_response.demand_code_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100004 10 offcore_response.demand_code_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100004 10 offcore_response.demand_code_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100004 10 offcore_response.demand_code_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100004 10 offcore_response.demand_code_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100004 10 offcore_response.demand_code_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100004 10 offcore_response.demand_code_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100004 10 offcore_response.demand_code_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400004 10 offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400004 10 offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400004 10 offcore_response.demand_code_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020004 10 offcore_response.demand_code_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020004 10 offcore_response.demand_code_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020004 10 offcore_response.demand_code_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020004 10 offcore_response.demand_code_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020004 10 offcore_response.demand_code_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020004 10 offcore_response.demand_code_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020004 10 offcore_response.demand_data_rd.any_response cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10001 10 offcore_response.demand_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001 10 offcore_response.demand_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 10 offcore_response.demand_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001 10 offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 10 offcore_response.demand_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001 10 offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0001 10 offcore_response.demand_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001 10 offcore_response.demand_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0001 10 offcore_response.demand_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080001 10 offcore_response.demand_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080001 10 offcore_response.demand_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080001 10 offcore_response.demand_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080001 10 offcore_response.demand_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080001 10 offcore_response.demand_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080001 10 offcore_response.demand_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080001 10 offcore_response.demand_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200001 10 offcore_response.demand_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200001 10 offcore_response.demand_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200001 10 offcore_response.demand_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200001 10 offcore_response.demand_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200001 10 offcore_response.demand_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200001 10 offcore_response.demand_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200001 10 offcore_response.demand_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040001 10 offcore_response.demand_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040001 10 offcore_response.demand_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040001 10 offcore_response.demand_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040001 10 offcore_response.demand_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040001 10 offcore_response.demand_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040001 10 offcore_response.demand_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040001 10 offcore_response.demand_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100001 10 offcore_response.demand_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100001 10 offcore_response.demand_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100001 10 offcore_response.demand_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100001 10 offcore_response.demand_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100001 10 offcore_response.demand_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100001 10 offcore_response.demand_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100001 10 offcore_response.demand_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400001 10 offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400001 10 offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400001 10 offcore_response.demand_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020001 10 offcore_response.demand_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020001 10 offcore_response.demand_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020001 10 offcore_response.demand_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020001 10 offcore_response.demand_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020001 10 offcore_response.demand_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020001 10 offcore_response.demand_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020001 10 offcore_response.demand_rfo.any_response cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10002 10 offcore_response.demand_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002 10 offcore_response.demand_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002 10 offcore_response.demand_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0002 10 offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002 10 offcore_response.demand_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002 10 offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0002 10 offcore_response.demand_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0002 10 offcore_response.demand_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0002 10 offcore_response.demand_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080002 10 offcore_response.demand_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080002 10 offcore_response.demand_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080002 10 offcore_response.demand_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080002 10 offcore_response.demand_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080002 10 offcore_response.demand_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080002 10 offcore_response.demand_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080002 10 offcore_response.demand_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200002 10 offcore_response.demand_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200002 10 offcore_response.demand_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200002 10 offcore_response.demand_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200002 10 offcore_response.demand_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200002 10 offcore_response.demand_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200002 10 offcore_response.demand_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200002 10 offcore_response.demand_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040002 10 offcore_response.demand_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040002 10 offcore_response.demand_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040002 10 offcore_response.demand_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040002 10 offcore_response.demand_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040002 10 offcore_response.demand_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040002 10 offcore_response.demand_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040002 10 offcore_response.demand_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100002 10 offcore_response.demand_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100002 10 offcore_response.demand_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100002 10 offcore_response.demand_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100002 10 offcore_response.demand_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100002 10 offcore_response.demand_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100002 10 offcore_response.demand_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100002 10 offcore_response.demand_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400002 10 offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400002 10 offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400002 10 offcore_response.demand_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020002 10 offcore_response.demand_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020002 10 offcore_response.demand_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020002 10 offcore_response.demand_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020002 10 offcore_response.demand_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020002 10 offcore_response.demand_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020002 10 offcore_response.demand_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020002 10 offcore_response.other.any_response cache This event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x18000 10 offcore_response.other.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C8000 10 offcore_response.other.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C8000 10 offcore_response.other.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C8000 10 offcore_response.other.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C8000 10 offcore_response.other.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C8000 10 offcore_response.other.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C8000 10 offcore_response.other.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C8000 10 offcore_response.other.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C8000 10 offcore_response.other.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80088000 10 offcore_response.other.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000088000 10 offcore_response.other.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800088000 10 offcore_response.other.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400088000 10 offcore_response.other.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100088000 10 offcore_response.other.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200088000 10 offcore_response.other.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80088000 10 offcore_response.other.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80208000 10 offcore_response.other.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000208000 10 offcore_response.other.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800208000 10 offcore_response.other.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400208000 10 offcore_response.other.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100208000 10 offcore_response.other.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200208000 10 offcore_response.other.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80208000 10 offcore_response.other.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80048000 10 offcore_response.other.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000048000 10 offcore_response.other.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800048000 10 offcore_response.other.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400048000 10 offcore_response.other.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100048000 10 offcore_response.other.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200048000 10 offcore_response.other.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80048000 10 offcore_response.other.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80108000 10 offcore_response.other.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000108000 10 offcore_response.other.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800108000 10 offcore_response.other.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400108000 10 offcore_response.other.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100108000 10 offcore_response.other.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200108000 10 offcore_response.other.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80108000 10 offcore_response.other.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80408000 10 offcore_response.other.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80408000 10 offcore_response.other.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100408000 10 offcore_response.other.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80028000 10 offcore_response.other.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000028000 10 offcore_response.other.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800028000 10 offcore_response.other.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400028000 10 offcore_response.other.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100028000 10 offcore_response.other.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200028000 10 offcore_response.other.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80028000 10 offcore_response.pf_l1d_and_sw.any_response cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10400 10 offcore_response.pf_l1d_and_sw.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100400 10 offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400400 10 offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400400 10 offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400400 10 offcore_response.pf_l1d_and_sw.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020400 10 offcore_response.pf_l1d_and_sw.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020400 10 offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020400 10 offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020400 10 offcore_response.pf_l1d_and_sw.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020400 10 offcore_response.pf_l1d_and_sw.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020400 10 offcore_response.pf_l1d_and_sw.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020400 10 offcore_response.pf_l2_data_rd.any_response cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10010 10 offcore_response.pf_l2_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010 10 offcore_response.pf_l2_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010 10 offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0010 10 offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010 10 offcore_response.pf_l2_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010 10 offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0010 10 offcore_response.pf_l2_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0010 10 offcore_response.pf_l2_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0010 10 offcore_response.pf_l2_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080010 10 offcore_response.pf_l2_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200010 10 offcore_response.pf_l2_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040010 10 offcore_response.pf_l2_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100010 10 offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400010 10 offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400010 10 offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400010 10 offcore_response.pf_l2_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020010 10 offcore_response.pf_l2_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020010 10 offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020010 10 offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020010 10 offcore_response.pf_l2_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020010 10 offcore_response.pf_l2_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020010 10 offcore_response.pf_l2_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020010 10 offcore_response.pf_l2_rfo.any_response cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10020 10 offcore_response.pf_l2_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020 10 offcore_response.pf_l2_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020 10 offcore_response.pf_l2_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0020 10 offcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020 10 offcore_response.pf_l2_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020 10 offcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0020 10 offcore_response.pf_l2_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0020 10 offcore_response.pf_l2_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0020 10 offcore_response.pf_l2_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080020 10 offcore_response.pf_l2_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080020 10 offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080020 10 offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080020 10 offcore_response.pf_l2_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080020 10 offcore_response.pf_l2_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080020 10 offcore_response.pf_l2_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080020 10 offcore_response.pf_l2_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200020 10 offcore_response.pf_l2_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200020 10 offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200020 10 offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200020 10 offcore_response.pf_l2_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200020 10 offcore_response.pf_l2_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200020 10 offcore_response.pf_l2_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200020 10 offcore_response.pf_l2_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040020 10 offcore_response.pf_l2_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040020 10 offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040020 10 offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040020 10 offcore_response.pf_l2_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040020 10 offcore_response.pf_l2_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040020 10 offcore_response.pf_l2_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040020 10 offcore_response.pf_l2_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100020 10 offcore_response.pf_l2_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100020 10 offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100020 10 offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100020 10 offcore_response.pf_l2_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100020 10 offcore_response.pf_l2_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100020 10 offcore_response.pf_l2_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100020 10 offcore_response.pf_l2_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400020 10 offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400020 10 offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400020 10 offcore_response.pf_l2_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020020 10 offcore_response.pf_l2_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020020 10 offcore_response.pf_l2_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020020 10 offcore_response.pf_l2_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020020 10 offcore_response.pf_l2_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020020 10 offcore_response.pf_l2_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020020 10 offcore_response.pf_l2_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020020 10 offcore_response.pf_l3_data_rd.any_response cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10080 10 offcore_response.pf_l3_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080 10 offcore_response.pf_l3_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0080 10 offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0080 10 offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0080 10 offcore_response.pf_l3_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0080 10 offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0080 10 offcore_response.pf_l3_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0080 10 offcore_response.pf_l3_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0080 10 offcore_response.pf_l3_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080080 10 offcore_response.pf_l3_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200080 10 offcore_response.pf_l3_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040080 10 offcore_response.pf_l3_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100080 10 offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400080 10 offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400080 10 offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400080 10 offcore_response.pf_l3_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020080 10 offcore_response.pf_l3_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020080 10 offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020080 10 offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020080 10 offcore_response.pf_l3_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020080 10 offcore_response.pf_l3_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020080 10 offcore_response.pf_l3_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020080 10 offcore_response.pf_l3_rfo.any_response cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10100 10 offcore_response.pf_l3_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100 10 offcore_response.pf_l3_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0100 10 offcore_response.pf_l3_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0100 10 offcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0100 10 offcore_response.pf_l3_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0100 10 offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0100 10 offcore_response.pf_l3_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0100 10 offcore_response.pf_l3_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0100 10 offcore_response.pf_l3_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080100 10 offcore_response.pf_l3_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080100 10 offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080100 10 offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080100 10 offcore_response.pf_l3_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080100 10 offcore_response.pf_l3_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080100 10 offcore_response.pf_l3_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080100 10 offcore_response.pf_l3_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200100 10 offcore_response.pf_l3_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200100 10 offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200100 10 offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200100 10 offcore_response.pf_l3_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200100 10 offcore_response.pf_l3_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200100 10 offcore_response.pf_l3_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200100 10 offcore_response.pf_l3_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040100 10 offcore_response.pf_l3_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040100 10 offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040100 10 offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040100 10 offcore_response.pf_l3_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040100 10 offcore_response.pf_l3_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040100 10 offcore_response.pf_l3_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040100 10 offcore_response.pf_l3_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100100 10 offcore_response.pf_l3_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100100 10 offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100100 10 offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100100 10 offcore_response.pf_l3_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100100 10 offcore_response.pf_l3_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100100 10 offcore_response.pf_l3_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100100 10 offcore_response.pf_l3_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400100 10 offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400100 10 offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400100 10 offcore_response.pf_l3_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020100 10 offcore_response.pf_l3_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020100 10 offcore_response.pf_l3_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020100 10 offcore_response.pf_l3_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020100 10 offcore_response.pf_l3_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020100 10 offcore_response.pf_l3_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020100 10 offcore_response.pf_l3_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020100 10 sq_misc.split_lock cache Number of cache line split locks sent to uncore event=0xf4,period=100003,umask=0x10 00 Counts the number of cache line split locks sent to the uncore sw_prefetch_access.any cache Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed event=0x32,period=2000003,umask=0xf 00 sw_prefetch_access.nta cache Number of PREFETCHNTA instructions executed event=0x32,period=2000003,umask=1 00 sw_prefetch_access.prefetchw cache Number of PREFETCHW instructions executed event=0x32,period=2000003,umask=8 00 sw_prefetch_access.t0 cache Number of PREFETCHT0 instructions executed event=0x32,period=2000003,umask=2 00 sw_prefetch_access.t1_t2 cache Number of PREFETCHT1 or PREFETCHT2 instructions executed event=0x32,period=2000003,umask=4 00 fp_arith_inst_retired.128b_packed_double floating point Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=4 00 Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.128b_packed_single floating point Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=8 00 Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_double floating point Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x10 00 Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_single floating point Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x20 00 Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.4_flops floating point Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=1000003,umask=0x18 00 Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_double floating point Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x40 00 Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_single floating point Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x80 00 Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.8_flops floating point Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=1000003,umask=0x18 00 Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar floating point Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=3 00 Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_double floating point Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=1 00 Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_single floating point Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=2 00 Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired2.128bit_packed_bf16 floating point Intel AVX-512 computational 512-bit packed BFloat16 instructions retired event=0xcf,period=2000003,umask=0x20 00 Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floating-point instruction retired. Applies to the ZMM based VDPBF16PS instruction. Each count represents 64 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake fp_arith_inst_retired2.256bit_packed_bf16 floating point Intel AVX-512 computational 128-bit packed BFloat16 instructions retired event=0xcf,period=2000003,umask=0x40 00 Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floating-point instruction retired. Applies to the XMM based VDPBF16PS instruction. Each count represents 16 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake fp_arith_inst_retired2.512bit_packed_bf16 floating point Intel AVX-512 computational 256-bit packed BFloat16 instructions retired event=0xcf,period=2000003,umask=0x80 00 Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floating-point instruction retired. Applies to the YMM based VDPBF16PS instruction. Each count represents 32 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e 00 Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 baclears.any frontend Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end event=0xe6,period=100003,umask=1 00 Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore decode.lcp frontend Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP] event=0x87,period=2000003,umask=1 00 Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP] dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE switches event=0xab,period=2000003,umask=1 00 This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=2 00 Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x12 00 frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x13 00 frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle (Must be precise) event=0xc6,period=100007,umask=1,frontend=0x400106 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Must be precise) frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x408006 00 frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x401006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_2 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x400206 00 frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x410006 00 frontend_retired.latency_ge_2_bubbles_ge_2 frontend Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x200206 00 frontend_retired.latency_ge_2_bubbles_ge_3 frontend Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x300206 00 frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x402006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x400406 00 frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x420006 00 frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x404006 00 frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x400806 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) icache_16b.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache miss event=0x80,period=2000003,umask=4 00 Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity icache_64b.iftag_hit frontend Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=1 00 icache_64b.iftag_miss frontend Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=2 00 icache_64b.iftag_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS] event=0x83,period=200003,umask=4 00 icache_tag.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL] event=0x83,period=200003,umask=4 00 idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK] event=0x79,cmask=4,period=2000003,umask=0x18 00 Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK] idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY] event=0x79,cmask=1,period=2000003,umask=0x18 00 Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_ANY] idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24 00 Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24 00 Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=8 00 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ idq.dsb_cycles_any frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS] event=0x79,cmask=1,period=2000003,umask=0x18 00 Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS] idq.dsb_cycles_ok frontend Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS] event=0x79,cmask=4,period=2000003,umask=0x18 00 Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS] idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=8 00 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=4 00 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=4 00 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10 00 Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20 00 Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ idq.ms_switches frontend Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer event=0x79,cmask=1,edge=1,period=2000003,umask=0x30 00 Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30 00 Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=1 00 Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=4,period=2000003,umask=1 00 Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=3,period=2000003,umask=1 00 Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3 idq_uops_not_delivered.cycles_le_2_uop_deliv.core frontend Cycles with less than 2 uops delivered by the front end event=0x9c,cmask=2,period=2000003,umask=1 00 Cycles with less than 2 uops delivered by the front-end idq_uops_not_delivered.cycles_le_3_uop_deliv.core frontend Cycles with less than 3 uops delivered by the front end event=0x9c,cmask=1,period=2000003,umask=1 00 Cycles with less than 3 uops delivered by the front-end cycle_activity.cycles_l3_miss memory Cycles while L3 cache miss demand load is outstanding event=0xa3,cmask=2,period=2000003,umask=2 00 cycle_activity.stalls_l3_miss memory Execution stalls while L3 cache miss demand load is outstanding event=0xa3,cmask=6,period=2000003,umask=6 00 hle_retired.aborted memory Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event) event=0xc8,period=2000003,umask=4 00 Number of times HLE abort was triggered (Precise event) hle_retired.aborted_events memory Number of times an HLE execution aborted due to unfriendly events (such as interrupts) event=0xc8,period=2000003,umask=0x80 00 hle_retired.aborted_mem memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=2000003,umask=8 00 hle_retired.aborted_memtype memory Number of times an HLE execution aborted due to incompatible memory type event=0xc8,period=2000003,umask=0x40 00 Number of times an HLE execution aborted due to incompatible memory type hle_retired.aborted_timer memory Number of times an HLE execution aborted due to hardware timer expiration event=0xc8,period=2000003,umask=0x10 00 hle_retired.aborted_unfriendly memory Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) event=0xc8,period=2000003,umask=0x20 00 hle_retired.commit memory Number of times an HLE execution successfully committed event=0xc8,period=2000003,umask=2 00 Number of times HLE commit succeeded hle_retired.start memory Number of times an HLE execution started event=0xc8,period=2000003,umask=1 00 Number of times we entered an HLE region. Does not count nested transactions machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts Spec update: SKL089 event=0xc3,period=100003,umask=2 00 Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer Spec update: SKL089 ocr.all_data_rd.l3_miss.any_snoop memory OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000491 00 ocr.all_data_rd.l3_miss.hitm_other_core memory OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000491 00 ocr.all_data_rd.l3_miss.hit_other_core_fwd memory OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000491 00 ocr.all_data_rd.l3_miss.hit_other_core_no_fwd memory OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000491 00 ocr.all_data_rd.l3_miss.no_snoop_needed memory OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000491 00 ocr.all_data_rd.l3_miss.remote_hitm memory OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00491 00 ocr.all_data_rd.l3_miss.remote_hit_forward memory OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00491 00 ocr.all_data_rd.l3_miss.snoop_miss memory OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000491 00 ocr.all_data_rd.l3_miss.snoop_none memory OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000491 00 ocr.all_data_rd.l3_miss_local_dram.any_snoop memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000491 00 ocr.all_data_rd.l3_miss_local_dram.hitm_other_core memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000491 00 ocr.all_data_rd.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000491 00 ocr.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000491 00 ocr.all_data_rd.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000491 00 ocr.all_data_rd.l3_miss_local_dram.snoop_miss memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000491 00 ocr.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000491 00 ocr.all_data_rd.l3_miss_local_dram.snoop_none memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000491 00 ocr.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000491 00 ocr.all_pf_data_rd.l3_miss.any_snoop memory OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000490 00 ocr.all_pf_data_rd.l3_miss.hitm_other_core memory OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000490 00 ocr.all_pf_data_rd.l3_miss.hit_other_core_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000490 00 ocr.all_pf_data_rd.l3_miss.hit_other_core_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000490 00 ocr.all_pf_data_rd.l3_miss.no_snoop_needed memory OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000490 00 ocr.all_pf_data_rd.l3_miss.remote_hitm memory OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00490 00 ocr.all_pf_data_rd.l3_miss.remote_hit_forward memory OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00490 00 ocr.all_pf_data_rd.l3_miss.snoop_miss memory OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000490 00 ocr.all_pf_data_rd.l3_miss.snoop_none memory OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.any_snoop memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.hitm_other_core memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.snoop_none memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000490 00 ocr.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000490 00 ocr.all_pf_rfo.l3_miss.any_snoop memory OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000120 00 ocr.all_pf_rfo.l3_miss.hitm_other_core memory OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000120 00 ocr.all_pf_rfo.l3_miss.hit_other_core_fwd memory OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000120 00 ocr.all_pf_rfo.l3_miss.hit_other_core_no_fwd memory OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000120 00 ocr.all_pf_rfo.l3_miss.no_snoop_needed memory OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000120 00 ocr.all_pf_rfo.l3_miss.remote_hitm memory OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00120 00 ocr.all_pf_rfo.l3_miss.remote_hit_forward memory OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00120 00 ocr.all_pf_rfo.l3_miss.snoop_miss memory OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000120 00 ocr.all_pf_rfo.l3_miss.snoop_none memory OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000120 00 ocr.all_pf_rfo.l3_miss_local_dram.any_snoop memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000120 00 ocr.all_pf_rfo.l3_miss_local_dram.hitm_other_core memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000120 00 ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000120 00 ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000120 00 ocr.all_pf_rfo.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000120 00 ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000120 00 ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000120 00 ocr.all_pf_rfo.l3_miss_local_dram.snoop_none memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000120 00 ocr.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000120 00 ocr.all_reads.l3_miss.any_snoop memory OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC0007F7 00 ocr.all_reads.l3_miss.hitm_other_core memory OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C0007F7 00 ocr.all_reads.l3_miss.hit_other_core_fwd memory OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C0007F7 00 ocr.all_reads.l3_miss.hit_other_core_no_fwd memory OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C0007F7 00 ocr.all_reads.l3_miss.no_snoop_needed memory OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C0007F7 00 ocr.all_reads.l3_miss.remote_hitm memory OCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_READS.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC007F7 00 ocr.all_reads.l3_miss.remote_hit_forward memory OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC007F7 00 ocr.all_reads.l3_miss.snoop_miss memory OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C0007F7 00 ocr.all_reads.l3_miss.snoop_none memory OCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READS.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC0007F7 00 ocr.all_reads.l3_miss_local_dram.any_snoop memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F840007F7 00 ocr.all_reads.l3_miss_local_dram.hitm_other_core memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10040007F7 00 ocr.all_reads.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8040007F7 00 ocr.all_reads.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4040007F7 00 ocr.all_reads.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1040007F7 00 ocr.all_reads.l3_miss_local_dram.snoop_miss memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2040007F7 00 ocr.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x6040007F7 00 ocr.all_reads.l3_miss_local_dram.snoop_none memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x840007F7 00 ocr.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B8007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F900007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10100007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8100007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4100007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1100007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2100007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x900007F7 00 ocr.all_rfo.l3_miss.any_snoop memory OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000122 00 ocr.all_rfo.l3_miss.hitm_other_core memory OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000122 00 ocr.all_rfo.l3_miss.hit_other_core_fwd memory OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000122 00 ocr.all_rfo.l3_miss.hit_other_core_no_fwd memory OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000122 00 ocr.all_rfo.l3_miss.no_snoop_needed memory OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000122 00 ocr.all_rfo.l3_miss.remote_hitm memory OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00122 00 ocr.all_rfo.l3_miss.remote_hit_forward memory OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00122 00 ocr.all_rfo.l3_miss.snoop_miss memory OCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000122 00 ocr.all_rfo.l3_miss.snoop_none memory OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000122 00 ocr.all_rfo.l3_miss_local_dram.any_snoop memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000122 00 ocr.all_rfo.l3_miss_local_dram.hitm_other_core memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000122 00 ocr.all_rfo.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000122 00 ocr.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000122 00 ocr.all_rfo.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000122 00 ocr.all_rfo.l3_miss_local_dram.snoop_miss memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000122 00 ocr.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000122 00 ocr.all_rfo.l3_miss_local_dram.snoop_none memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000122 00 ocr.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000122 00 ocr.demand_code_rd.l3_miss.any_snoop memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000004 00 ocr.demand_code_rd.l3_miss.hitm_other_core memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000004 00 ocr.demand_code_rd.l3_miss.hit_other_core_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000004 00 ocr.demand_code_rd.l3_miss.hit_other_core_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000004 00 ocr.demand_code_rd.l3_miss.no_snoop_needed memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000004 00 ocr.demand_code_rd.l3_miss.remote_hitm memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00004 00 ocr.demand_code_rd.l3_miss.remote_hit_forward memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00004 00 ocr.demand_code_rd.l3_miss.snoop_miss memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000004 00 ocr.demand_code_rd.l3_miss.snoop_none memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000004 00 ocr.demand_code_rd.l3_miss_local_dram.any_snoop memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000004 00 ocr.demand_code_rd.l3_miss_local_dram.hitm_other_core memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000004 00 ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000004 00 ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000004 00 ocr.demand_code_rd.l3_miss_local_dram.no_snoop_needed memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000004 00 ocr.demand_code_rd.l3_miss_local_dram.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000004 00 ocr.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000004 00 ocr.demand_code_rd.l3_miss_local_dram.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000004 00 ocr.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x210000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x90000004 00 ocr.demand_data_rd.l3_miss.any_snoop memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000001 00 ocr.demand_data_rd.l3_miss.hitm_other_core memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000001 00 ocr.demand_data_rd.l3_miss.hit_other_core_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000001 00 ocr.demand_data_rd.l3_miss.hit_other_core_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000001 00 ocr.demand_data_rd.l3_miss.no_snoop_needed memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000001 00 ocr.demand_data_rd.l3_miss.remote_hitm memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00001 00 ocr.demand_data_rd.l3_miss.remote_hit_forward memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00001 00 ocr.demand_data_rd.l3_miss.snoop_miss memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000001 00 ocr.demand_data_rd.l3_miss.snoop_none memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000001 00 ocr.demand_data_rd.l3_miss_local_dram.any_snoop memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000001 00 ocr.demand_data_rd.l3_miss_local_dram.hitm_other_core memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000001 00 ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000001 00 ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000001 00 ocr.demand_data_rd.l3_miss_local_dram.no_snoop_needed memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000001 00 ocr.demand_data_rd.l3_miss_local_dram.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000001 00 ocr.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000001 00 ocr.demand_data_rd.l3_miss_local_dram.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000001 00 ocr.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x210000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x90000001 00 ocr.demand_rfo.l3_miss.any_snoop memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000002 00 ocr.demand_rfo.l3_miss.hitm_other_core memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000002 00 ocr.demand_rfo.l3_miss.hit_other_core_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000002 00 ocr.demand_rfo.l3_miss.hit_other_core_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000002 00 ocr.demand_rfo.l3_miss.no_snoop_needed memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000002 00 ocr.demand_rfo.l3_miss.remote_hitm memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00002 00 ocr.demand_rfo.l3_miss.remote_hit_forward memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00002 00 ocr.demand_rfo.l3_miss.snoop_miss memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000002 00 ocr.demand_rfo.l3_miss.snoop_none memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000002 00 ocr.demand_rfo.l3_miss_local_dram.any_snoop memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000002 00 ocr.demand_rfo.l3_miss_local_dram.hitm_other_core memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000002 00 ocr.demand_rfo.l3_miss_local_dram.hit_other_core_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000002 00 ocr.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000002 00 ocr.demand_rfo.l3_miss_local_dram.no_snoop_needed memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000002 00 ocr.demand_rfo.l3_miss_local_dram.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x204000002 00 ocr.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000002 00 ocr.demand_rfo.l3_miss_local_dram.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x84000002 00 ocr.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.any_snoop memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x210000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x90000002 00 ocr.other.l3_miss.any_snoop memory Counts any other requests OCR.OTHER.L3_MISS.ANY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC008000 00 ocr.other.l3_miss.hitm_other_core memory Counts any other requests OCR.OTHER.L3_MISS.HITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C008000 00 ocr.other.l3_miss.hit_other_core_fwd memory Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C008000 00 ocr.other.l3_miss.hit_other_core_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C008000 00 ocr.other.l3_miss.no_snoop_needed memory Counts any other requests OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C008000 00 ocr.other.l3_miss.remote_hitm memory Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC08000 00 ocr.other.l3_miss.remote_hit_forward memory Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC08000 00 ocr.other.l3_miss.snoop_miss memory Counts any other requests OCR.OTHER.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C008000 00 ocr.other.l3_miss.snoop_none memory Counts any other requests OCR.OTHER.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC008000 00 ocr.other.l3_miss_local_dram.any_snoop memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84008000 00 ocr.other.l3_miss_local_dram.hitm_other_core memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004008000 00 ocr.other.l3_miss_local_dram.hit_other_core_fwd memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804008000 00 ocr.other.l3_miss_local_dram.hit_other_core_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404008000 00 ocr.other.l3_miss_local_dram.no_snoop_needed memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104008000 00 ocr.other.l3_miss_local_dram.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x204008000 00 ocr.other.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604008000 00 ocr.other.l3_miss_local_dram.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x84008000 00 ocr.other.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B808000 00 ocr.other.l3_miss_remote_hop1_dram.any_snoop memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90008000 00 ocr.other.l3_miss_remote_hop1_dram.hitm_other_core memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010008000 00 ocr.other.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810008000 00 ocr.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410008000 00 ocr.other.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110008000 00 ocr.other.l3_miss_remote_hop1_dram.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x210008000 00 ocr.other.l3_miss_remote_hop1_dram.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x90008000 00 ocr.pf_l1d_and_sw.l3_miss.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000400 00 ocr.pf_l1d_and_sw.l3_miss.hitm_other_core memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000400 00 ocr.pf_l1d_and_sw.l3_miss.hit_other_core_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000400 00 ocr.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000400 00 ocr.pf_l1d_and_sw.l3_miss.no_snoop_needed memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000400 00 ocr.pf_l1d_and_sw.l3_miss.remote_hitm memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00400 00 ocr.pf_l1d_and_sw.l3_miss.remote_hit_forward memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00400 00 ocr.pf_l1d_and_sw.l3_miss.snoop_miss memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000400 00 ocr.pf_l1d_and_sw.l3_miss.snoop_none memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x204000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_none memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x84000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x210000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x90000400 00 ocr.pf_l2_data_rd.l3_miss.any_snoop memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000010 00 ocr.pf_l2_data_rd.l3_miss.hitm_other_core memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000010 00 ocr.pf_l2_data_rd.l3_miss.hit_other_core_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000010 00 ocr.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000010 00 ocr.pf_l2_data_rd.l3_miss.no_snoop_needed memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000010 00 ocr.pf_l2_data_rd.l3_miss.remote_hitm memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00010 00 ocr.pf_l2_data_rd.l3_miss.remote_hit_forward memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00010 00 ocr.pf_l2_data_rd.l3_miss.snoop_miss memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000010 00 ocr.pf_l2_data_rd.l3_miss.snoop_none memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.any_snoop memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000010 00 ocr.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x210000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x90000010 00 ocr.pf_l2_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000020 00 ocr.pf_l2_rfo.l3_miss.hitm_other_core memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000020 00 ocr.pf_l2_rfo.l3_miss.hit_other_core_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000020 00 ocr.pf_l2_rfo.l3_miss.hit_other_core_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000020 00 ocr.pf_l2_rfo.l3_miss.no_snoop_needed memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000020 00 ocr.pf_l2_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00020 00 ocr.pf_l2_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00020 00 ocr.pf_l2_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000020 00 ocr.pf_l2_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.hitm_other_core memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000020 00 ocr.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x210000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x90000020 00 ocr.pf_l3_data_rd.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000080 00 ocr.pf_l3_data_rd.l3_miss.hitm_other_core memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000080 00 ocr.pf_l3_data_rd.l3_miss.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000080 00 ocr.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000080 00 ocr.pf_l3_data_rd.l3_miss.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000080 00 ocr.pf_l3_data_rd.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00080 00 ocr.pf_l3_data_rd.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00080 00 ocr.pf_l3_data_rd.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000080 00 ocr.pf_l3_data_rd.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000080 00 ocr.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x210000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x90000080 00 ocr.pf_l3_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000100 00 ocr.pf_l3_rfo.l3_miss.hitm_other_core memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000100 00 ocr.pf_l3_rfo.l3_miss.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000100 00 ocr.pf_l3_rfo.l3_miss.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000100 00 ocr.pf_l3_rfo.l3_miss.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000100 00 ocr.pf_l3_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00100 00 ocr.pf_l3_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00100 00 ocr.pf_l3_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000100 00 ocr.pf_l3_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000100 00 ocr.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x210000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x90000100 00 offcore_requests.l3_miss_demand_data_rd memory Demand Data Read requests who miss L3 cache event=0xb0,period=100003,umask=0x10 00 Demand Data Read requests who miss L3 cache offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd memory Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ event=0x60,cmask=1,period=2000003,umask=0x10 00 offcore_requests_outstanding.l3_miss_demand_data_rd memory Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle event=0x60,period=2000003,umask=0x10 00 offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6 memory Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ event=0x60,cmask=6,period=2000003,umask=0x10 00 offcore_response.all_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000491 10 offcore_response.all_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000491 10 offcore_response.all_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000491 10 offcore_response.all_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000491 10 offcore_response.all_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000491 10 offcore_response.all_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00491 10 offcore_response.all_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00491 10 offcore_response.all_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000491 10 offcore_response.all_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000491 10 offcore_response.all_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000491 10 offcore_response.all_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000491 10 offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000491 10 offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000491 10 offcore_response.all_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000491 10 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000491 10 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000491 10 offcore_response.all_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000491 10 offcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000491 10 offcore_response.all_pf_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000490 10 offcore_response.all_pf_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000490 10 offcore_response.all_pf_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000490 10 offcore_response.all_pf_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000490 10 offcore_response.all_pf_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000490 10 offcore_response.all_pf_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00490 10 offcore_response.all_pf_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00490 10 offcore_response.all_pf_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000490 10 offcore_response.all_pf_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000490 10 offcore_response.all_pf_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000120 10 offcore_response.all_pf_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000120 10 offcore_response.all_pf_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000120 10 offcore_response.all_pf_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000120 10 offcore_response.all_pf_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000120 10 offcore_response.all_pf_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00120 10 offcore_response.all_pf_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00120 10 offcore_response.all_pf_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000120 10 offcore_response.all_pf_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000120 10 offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000120 10 offcore_response.all_reads.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC0007F7 10 offcore_response.all_reads.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C0007F7 10 offcore_response.all_reads.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C0007F7 10 offcore_response.all_reads.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C0007F7 10 offcore_response.all_reads.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C0007F7 10 offcore_response.all_reads.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC007F7 10 offcore_response.all_reads.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC007F7 10 offcore_response.all_reads.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C0007F7 10 offcore_response.all_reads.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC0007F7 10 offcore_response.all_reads.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F840007F7 10 offcore_response.all_reads.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10040007F7 10 offcore_response.all_reads.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8040007F7 10 offcore_response.all_reads.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4040007F7 10 offcore_response.all_reads.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1040007F7 10 offcore_response.all_reads.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2040007F7 10 offcore_response.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x6040007F7 10 offcore_response.all_reads.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x840007F7 10 offcore_response.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B8007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F900007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10100007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8100007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4100007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1100007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2100007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x900007F7 10 offcore_response.all_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000122 10 offcore_response.all_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000122 10 offcore_response.all_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000122 10 offcore_response.all_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000122 10 offcore_response.all_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000122 10 offcore_response.all_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00122 10 offcore_response.all_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00122 10 offcore_response.all_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000122 10 offcore_response.all_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000122 10 offcore_response.all_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000122 10 offcore_response.all_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000122 10 offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000122 10 offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000122 10 offcore_response.all_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000122 10 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000122 10 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000122 10 offcore_response.all_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000122 10 offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000122 10 offcore_response.demand_code_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000004 10 offcore_response.demand_code_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000004 10 offcore_response.demand_code_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000004 10 offcore_response.demand_code_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000004 10 offcore_response.demand_code_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000004 10 offcore_response.demand_code_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00004 10 offcore_response.demand_code_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00004 10 offcore_response.demand_code_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000004 10 offcore_response.demand_code_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000004 10 offcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000004 10 offcore_response.demand_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000001 10 offcore_response.demand_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000001 10 offcore_response.demand_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000001 10 offcore_response.demand_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000001 10 offcore_response.demand_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000001 10 offcore_response.demand_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00001 10 offcore_response.demand_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00001 10 offcore_response.demand_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000001 10 offcore_response.demand_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000001 10 offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000001 10 offcore_response.demand_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000002 10 offcore_response.demand_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000002 10 offcore_response.demand_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000002 10 offcore_response.demand_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000002 10 offcore_response.demand_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000002 10 offcore_response.demand_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00002 10 offcore_response.demand_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00002 10 offcore_response.demand_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000002 10 offcore_response.demand_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000002 10 offcore_response.demand_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000002 10 offcore_response.demand_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000002 10 offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000002 10 offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000002 10 offcore_response.demand_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000002 10 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000002 10 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000002 10 offcore_response.demand_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000002 10 offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000002 10 offcore_response.other.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC008000 10 offcore_response.other.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C008000 10 offcore_response.other.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C008000 10 offcore_response.other.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C008000 10 offcore_response.other.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C008000 10 offcore_response.other.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC08000 10 offcore_response.other.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC08000 10 offcore_response.other.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C008000 10 offcore_response.other.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC008000 10 offcore_response.other.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84008000 10 offcore_response.other.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004008000 10 offcore_response.other.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804008000 10 offcore_response.other.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404008000 10 offcore_response.other.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104008000 10 offcore_response.other.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204008000 10 offcore_response.other.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604008000 10 offcore_response.other.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84008000 10 offcore_response.other.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B808000 10 offcore_response.other.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90008000 10 offcore_response.other.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010008000 10 offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810008000 10 offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410008000 10 offcore_response.other.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110008000 10 offcore_response.other.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210008000 10 offcore_response.other.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90008000 10 offcore_response.pf_l1d_and_sw.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000400 10 offcore_response.pf_l1d_and_sw.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000400 10 offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000400 10 offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000400 10 offcore_response.pf_l1d_and_sw.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000400 10 offcore_response.pf_l1d_and_sw.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00400 10 offcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00400 10 offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000400 10 offcore_response.pf_l1d_and_sw.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000400 10 offcore_response.pf_l2_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000010 10 offcore_response.pf_l2_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000010 10 offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000010 10 offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000010 10 offcore_response.pf_l2_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000010 10 offcore_response.pf_l2_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00010 10 offcore_response.pf_l2_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00010 10 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000010 10 offcore_response.pf_l2_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000010 10 offcore_response.pf_l2_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000020 10 offcore_response.pf_l2_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000020 10 offcore_response.pf_l2_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000020 10 offcore_response.pf_l2_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000020 10 offcore_response.pf_l2_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000020 10 offcore_response.pf_l2_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00020 10 offcore_response.pf_l2_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00020 10 offcore_response.pf_l2_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000020 10 offcore_response.pf_l2_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000020 10 offcore_response.pf_l3_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000080 10 offcore_response.pf_l3_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000080 10 offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000080 10 offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000080 10 offcore_response.pf_l3_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000080 10 offcore_response.pf_l3_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00080 10 offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00080 10 offcore_response.pf_l3_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000080 10 offcore_response.pf_l3_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000080 10 offcore_response.pf_l3_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000100 10 offcore_response.pf_l3_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000100 10 offcore_response.pf_l3_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000100 10 offcore_response.pf_l3_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000100 10 offcore_response.pf_l3_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000100 10 offcore_response.pf_l3_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00100 10 offcore_response.pf_l3_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00100 10 offcore_response.pf_l3_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000100 10 offcore_response.pf_l3_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000100 10 rtm_retired.aborted memory Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Must be precise) event=0xc9,period=2000003,umask=4 00 Number of times RTM abort was triggered (Must be precise) rtm_retired.aborted_events memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=2000003,umask=0x80 00 Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) rtm_retired.aborted_mem memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=2000003,umask=8 00 Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) rtm_retired.aborted_memtype memory Number of times an RTM execution aborted due to incompatible memory type event=0xc9,period=2000003,umask=0x40 00 Number of times an RTM execution aborted due to incompatible memory type rtm_retired.aborted_timer memory Number of times an RTM execution aborted due to uncommon conditions event=0xc9,period=2000003,umask=0x10 00 rtm_retired.aborted_unfriendly memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=2000003,umask=0x20 00 Number of times an RTM execution aborted due to HLE-unfriendly instructions rtm_retired.commit memory Number of times an RTM execution successfully committed event=0xc9,period=2000003,umask=2 00 Number of times RTM commit succeeded rtm_retired.start memory Number of times an RTM execution started event=0xc9,period=2000003,umask=1 00 Number of times we entered an RTM region. Does not count nested transactions tx_exec.misc2 memory Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region event=0x5d,period=2000003,umask=2 00 Unfriendly TSX abort triggered by a vzeroupper instruction tx_exec.misc5 memory Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region event=0x5d,period=2000003,umask=0x10 00 Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region tx_mem.abort_capacity memory Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes event=0x54,period=2000003,umask=2 00 tx_mem.abort_conflict memory Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address event=0x54,period=2000003,umask=1 00 Number of times a TSX line had a cache conflict tx_mem.abort_hle_elision_buffer_mismatch memory Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer event=0x54,period=2000003,umask=0x10 00 Number of times a TSX Abort was triggered due to release/commit but data and address mismatch tx_mem.abort_hle_elision_buffer_not_empty memory Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero event=0x54,period=2000003,umask=8 00 Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer event=0x54,period=2000003,umask=0x20 00 Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer tx_mem.abort_hle_store_to_elided_lock memory Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer event=0x54,period=2000003,umask=4 00 Number of times a TSX Abort was triggered due to a non-release/commit store to lock tx_mem.hle_elision_buffer_full memory Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero event=0x54,period=2000003,umask=0x40 00 Number of times we could not allocate Lock Buffer core_power.lvl0_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule event=0x28,period=200003,umask=7 00 Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes core_power.lvl1_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule event=0x28,period=200003,umask=0x18 00 Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions core_power.lvl2_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule event=0x28,period=200003,umask=0x20 00 Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions core_power.throttle other Core cycles the core was throttled due to a pending power level request event=0x28,period=200003,umask=0x40 00 Core cycles the out-of-order engine was throttled due to a pending power level request core_snoop_response.rsp_ifwdfe other CORE_SNOOP_RESPONSE.RSP_IFWDFE event=0xef,period=2000003,umask=0x20 00 core_snoop_response.rsp_ifwdm other CORE_SNOOP_RESPONSE.RSP_IFWDM event=0xef,period=2000003,umask=0x10 00 core_snoop_response.rsp_ihitfse other CORE_SNOOP_RESPONSE.RSP_IHITFSE event=0xef,period=2000003,umask=2 00 core_snoop_response.rsp_ihiti other CORE_SNOOP_RESPONSE.RSP_IHITI event=0xef,period=2000003,umask=1 00 core_snoop_response.rsp_sfwdfe other CORE_SNOOP_RESPONSE.RSP_SFWDFE event=0xef,period=2000003,umask=0x40 00 core_snoop_response.rsp_sfwdm other CORE_SNOOP_RESPONSE.RSP_SFWDM event=0xef,period=2000003,umask=8 00 core_snoop_response.rsp_shitfse other CORE_SNOOP_RESPONSE.RSP_SHITFSE event=0xef,period=2000003,umask=4 00 hw_interrupts.received other Number of hardware interrupts received by the processor event=0xcb,period=203,umask=1 00 Counts the number of hardware interruptions received by the processor idi_misc.wb_downgrade other Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly event=0xfe,period=100003,umask=4 00 Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly idi_misc.wb_upgrade other Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly event=0xfe,period=100003,umask=2 00 Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly ocr.all_data_rd.any_response other OCR.ALL_DATA_RD.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10491 00 ocr.all_data_rd.pmm_hit_local_pmm.any_snoop other OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400491 00 ocr.all_data_rd.pmm_hit_local_pmm.snoop_none other OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400491 00 ocr.all_data_rd.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400491 00 ocr.all_data_rd.supplier_none.any_snoop other OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020491 00 ocr.all_data_rd.supplier_none.hitm_other_core other OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020491 00 ocr.all_data_rd.supplier_none.hit_other_core_fwd other OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020491 00 ocr.all_data_rd.supplier_none.hit_other_core_no_fwd other OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020491 00 ocr.all_data_rd.supplier_none.no_snoop_needed other OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020491 00 ocr.all_data_rd.supplier_none.snoop_miss other OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020491 00 ocr.all_data_rd.supplier_none.snoop_none other OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020491 00 ocr.all_pf_data_rd.any_response other OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10490 00 ocr.all_pf_data_rd.pmm_hit_local_pmm.any_snoop other OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400490 00 ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_none other OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400490 00 ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400490 00 ocr.all_pf_data_rd.supplier_none.any_snoop other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020490 00 ocr.all_pf_data_rd.supplier_none.hitm_other_core other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020490 00 ocr.all_pf_data_rd.supplier_none.hit_other_core_fwd other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020490 00 ocr.all_pf_data_rd.supplier_none.hit_other_core_no_fwd other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020490 00 ocr.all_pf_data_rd.supplier_none.no_snoop_needed other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020490 00 ocr.all_pf_data_rd.supplier_none.snoop_miss other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020490 00 ocr.all_pf_data_rd.supplier_none.snoop_none other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020490 00 ocr.all_pf_rfo.any_response other OCR.ALL_PF_RFO.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10120 00 ocr.all_pf_rfo.pmm_hit_local_pmm.any_snoop other OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400120 00 ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_none other OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400120 00 ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400120 00 ocr.all_pf_rfo.supplier_none.any_snoop other OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020120 00 ocr.all_pf_rfo.supplier_none.hitm_other_core other OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020120 00 ocr.all_pf_rfo.supplier_none.hit_other_core_fwd other OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020120 00 ocr.all_pf_rfo.supplier_none.hit_other_core_no_fwd other OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020120 00 ocr.all_pf_rfo.supplier_none.no_snoop_needed other OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020120 00 ocr.all_pf_rfo.supplier_none.snoop_miss other OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020120 00 ocr.all_pf_rfo.supplier_none.snoop_none other OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020120 00 ocr.all_reads.any_response other OCR.ALL_READS.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x107F7 00 ocr.all_reads.pmm_hit_local_pmm.any_snoop other OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F804007F7 00 ocr.all_reads.pmm_hit_local_pmm.snoop_none other OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x804007F7 00 ocr.all_reads.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1004007F7 00 ocr.all_reads.supplier_none.any_snoop other OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800207F7 00 ocr.all_reads.supplier_none.hitm_other_core other OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000207F7 00 ocr.all_reads.supplier_none.hit_other_core_fwd other OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000207F7 00 ocr.all_reads.supplier_none.hit_other_core_no_fwd other OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000207F7 00 ocr.all_reads.supplier_none.no_snoop_needed other OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000207F7 00 ocr.all_reads.supplier_none.snoop_miss other OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000207F7 00 ocr.all_reads.supplier_none.snoop_none other OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800207F7 00 ocr.all_rfo.any_response other OCR.ALL_RFO.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10122 00 ocr.all_rfo.pmm_hit_local_pmm.any_snoop other OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400122 00 ocr.all_rfo.pmm_hit_local_pmm.snoop_none other OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400122 00 ocr.all_rfo.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400122 00 ocr.all_rfo.supplier_none.any_snoop other OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020122 00 ocr.all_rfo.supplier_none.hitm_other_core other OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020122 00 ocr.all_rfo.supplier_none.hit_other_core_fwd other OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020122 00 ocr.all_rfo.supplier_none.hit_other_core_no_fwd other OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020122 00 ocr.all_rfo.supplier_none.no_snoop_needed other OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020122 00 ocr.all_rfo.supplier_none.snoop_miss other OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020122 00 ocr.all_rfo.supplier_none.snoop_none other OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020122 00 ocr.demand_code_rd.any_response other Counts all demand code reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10004 00 ocr.demand_code_rd.pmm_hit_local_pmm.any_snoop other Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400004 00 ocr.demand_code_rd.pmm_hit_local_pmm.snoop_none other Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400004 00 ocr.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed other Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400004 00 ocr.demand_code_rd.supplier_none.any_snoop other Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020004 00 ocr.demand_code_rd.supplier_none.hitm_other_core other Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020004 00 ocr.demand_code_rd.supplier_none.hit_other_core_fwd other Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020004 00 ocr.demand_code_rd.supplier_none.hit_other_core_no_fwd other Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020004 00 ocr.demand_code_rd.supplier_none.no_snoop_needed other Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020004 00 ocr.demand_code_rd.supplier_none.snoop_miss other Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020004 00 ocr.demand_code_rd.supplier_none.snoop_none other Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020004 00 ocr.demand_data_rd.any_response other Counts demand data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10001 00 ocr.demand_data_rd.pmm_hit_local_pmm.any_snoop other Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400001 00 ocr.demand_data_rd.pmm_hit_local_pmm.snoop_none other Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400001 00 ocr.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed other Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400001 00 ocr.demand_data_rd.supplier_none.any_snoop other Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020001 00 ocr.demand_data_rd.supplier_none.hitm_other_core other Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020001 00 ocr.demand_data_rd.supplier_none.hit_other_core_fwd other Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020001 00 ocr.demand_data_rd.supplier_none.hit_other_core_no_fwd other Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020001 00 ocr.demand_data_rd.supplier_none.no_snoop_needed other Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020001 00 ocr.demand_data_rd.supplier_none.snoop_miss other Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020001 00 ocr.demand_data_rd.supplier_none.snoop_none other Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020001 00 ocr.demand_rfo.any_response other Counts all demand data writes (RFOs) have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10002 00 ocr.demand_rfo.pmm_hit_local_pmm.any_snoop other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400002 00 ocr.demand_rfo.pmm_hit_local_pmm.snoop_none other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400002 00 ocr.demand_rfo.pmm_hit_local_pmm.snoop_not_needed other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400002 00 ocr.demand_rfo.supplier_none.any_snoop other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020002 00 ocr.demand_rfo.supplier_none.hitm_other_core other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020002 00 ocr.demand_rfo.supplier_none.hit_other_core_fwd other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020002 00 ocr.demand_rfo.supplier_none.hit_other_core_no_fwd other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020002 00 ocr.demand_rfo.supplier_none.no_snoop_needed other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020002 00 ocr.demand_rfo.supplier_none.snoop_miss other Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200020002 00 ocr.demand_rfo.supplier_none.snoop_none other Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80020002 00 ocr.other.any_response other Counts any other requests have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x18000 00 ocr.other.pmm_hit_local_pmm.any_snoop other Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80408000 00 ocr.other.pmm_hit_local_pmm.snoop_none other Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80408000 00 ocr.other.pmm_hit_local_pmm.snoop_not_needed other Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100408000 00 ocr.other.supplier_none.any_snoop other Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80028000 00 ocr.other.supplier_none.hitm_other_core other Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000028000 00 ocr.other.supplier_none.hit_other_core_fwd other Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800028000 00 ocr.other.supplier_none.hit_other_core_no_fwd other Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400028000 00 ocr.other.supplier_none.no_snoop_needed other Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100028000 00 ocr.other.supplier_none.snoop_miss other Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200028000 00 ocr.other.supplier_none.snoop_none other Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80028000 00 ocr.pf_l1d_and_sw.any_response other Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10400 00 ocr.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400400 00 ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400400 00 ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400400 00 ocr.pf_l1d_and_sw.supplier_none.any_snoop other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020400 00 ocr.pf_l1d_and_sw.supplier_none.hitm_other_core other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020400 00 ocr.pf_l1d_and_sw.supplier_none.hit_other_core_fwd other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020400 00 ocr.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020400 00 ocr.pf_l1d_and_sw.supplier_none.no_snoop_needed other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020400 00 ocr.pf_l1d_and_sw.supplier_none.snoop_miss other Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200020400 00 ocr.pf_l1d_and_sw.supplier_none.snoop_none other Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80020400 00 ocr.pf_l2_data_rd.any_response other Counts prefetch (that bring data to L2) data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10010 00 ocr.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400010 00 ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400010 00 ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400010 00 ocr.pf_l2_data_rd.supplier_none.any_snoop other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020010 00 ocr.pf_l2_data_rd.supplier_none.hitm_other_core other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020010 00 ocr.pf_l2_data_rd.supplier_none.hit_other_core_fwd other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020010 00 ocr.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020010 00 ocr.pf_l2_data_rd.supplier_none.no_snoop_needed other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020010 00 ocr.pf_l2_data_rd.supplier_none.snoop_miss other Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020010 00 ocr.pf_l2_data_rd.supplier_none.snoop_none other Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020010 00 ocr.pf_l2_rfo.any_response other Counts all prefetch (that bring data to L2) RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10020 00 ocr.pf_l2_rfo.pmm_hit_local_pmm.any_snoop other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400020 00 ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_none other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400020 00 ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400020 00 ocr.pf_l2_rfo.supplier_none.any_snoop other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020020 00 ocr.pf_l2_rfo.supplier_none.hitm_other_core other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020020 00 ocr.pf_l2_rfo.supplier_none.hit_other_core_fwd other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020020 00 ocr.pf_l2_rfo.supplier_none.hit_other_core_no_fwd other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020020 00 ocr.pf_l2_rfo.supplier_none.no_snoop_needed other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020020 00 ocr.pf_l2_rfo.supplier_none.snoop_miss other Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020020 00 ocr.pf_l2_rfo.supplier_none.snoop_none other Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020020 00 ocr.pf_l3_data_rd.any_response other Counts all prefetch (that bring data to LLC only) data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10080 00 ocr.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400080 00 ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400080 00 ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400080 00 ocr.pf_l3_data_rd.supplier_none.any_snoop other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020080 00 ocr.pf_l3_data_rd.supplier_none.hitm_other_core other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020080 00 ocr.pf_l3_data_rd.supplier_none.hit_other_core_fwd other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020080 00 ocr.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020080 00 ocr.pf_l3_data_rd.supplier_none.no_snoop_needed other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020080 00 ocr.pf_l3_data_rd.supplier_none.snoop_miss other Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020080 00 ocr.pf_l3_data_rd.supplier_none.snoop_none other Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020080 00 ocr.pf_l3_rfo.any_response other Counts all prefetch (that bring data to LLC only) RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10100 00 ocr.pf_l3_rfo.pmm_hit_local_pmm.any_snoop other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400100 00 ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_none other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400100 00 ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400100 00 ocr.pf_l3_rfo.supplier_none.any_snoop other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020100 00 ocr.pf_l3_rfo.supplier_none.hitm_other_core other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020100 00 ocr.pf_l3_rfo.supplier_none.hit_other_core_fwd other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020100 00 ocr.pf_l3_rfo.supplier_none.hit_other_core_no_fwd other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020100 00 ocr.pf_l3_rfo.supplier_none.no_snoop_needed other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020100 00 ocr.pf_l3_rfo.supplier_none.snoop_miss other Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020100 00 ocr.pf_l3_rfo.supplier_none.snoop_none other Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020100 00 arith.divider_active pipeline Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations event=0x14,cmask=1,period=2000003,umask=1 00 br_inst_retired.all_branches pipeline All (macro) branch instructions retired Spec update: SKL091 event=0xc4,period=400009 00 Counts all (macro) branch instructions retired Spec update: SKL091 br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired Spec update: SKL091 (Must be precise) event=0xc4,period=400009,umask=4 00 This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired Spec update: SKL091 (Must be precise) br_inst_retired.cond pipeline Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL] Spec update: SKL091 event=0xc4,period=400009,umask=1 00 This event counts conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL] Spec update: SKL091 br_inst_retired.conditional pipeline Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND] Spec update: SKL091 (Precise event) event=0xc4,period=400009,umask=1 00 This event counts conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND] Spec update: SKL091 (Precise event) br_inst_retired.cond_ntaken pipeline Not taken branch instructions retired Spec update: SKL091 event=0xc4,period=400009,umask=0x10 00 This event counts not taken branch instructions retired Spec update: SKL091 br_inst_retired.far_branch pipeline Far branch instructions retired Spec update: SKL091 (Precise event) event=0xc4,period=100007,umask=0x40 00 This event counts far branch instructions retired Spec update: SKL091 (Precise event) br_inst_retired.near_call pipeline Direct and indirect near call instructions retired Spec update: SKL091 (Precise event) event=0xc4,period=100007,umask=2 00 This event counts both direct and indirect near call instructions retired Spec update: SKL091 (Precise event) br_inst_retired.near_return pipeline Return instructions retired Spec update: SKL091 (Precise event) event=0xc4,period=100007,umask=8 00 This event counts return instructions retired Spec update: SKL091 (Precise event) br_inst_retired.near_taken pipeline Taken branch instructions retired Spec update: SKL091 (Precise event) event=0xc4,period=400009,umask=0x20 00 This event counts taken branch instructions retired Spec update: SKL091 (Precise event) br_inst_retired.not_taken pipeline Not taken branch instructions retired Spec update: SKL091 event=0xc4,period=400009,umask=0x10 00 This event counts not taken branch instructions retired Spec update: SKL091 br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009 00 Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired (Must be precise) event=0xc5,period=400009,umask=4 00 This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise) br_misp_retired.near_call pipeline Mispredicted direct and indirect near call instructions retired (Precise event) event=0xc5,period=400009,umask=2 00 Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event) br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20 00 cpu_clk_thread_unhalted.one_thread_active pipeline Core crystal clock cycles when this thread is unhalted and the other thread is halted event=0x3c,period=25003,umask=2 00 cpu_clk_thread_unhalted.ref_xclk pipeline Core crystal clock cycles when the thread is unhalted event=0x3c,period=25003,umask=1 00 cpu_clk_thread_unhalted.ref_xclk_any pipeline Core crystal clock cycles when at least one thread on the physical core is unhalted event=0x3c,any=1,period=25003,umask=1 00 cpu_clk_unhalted.one_thread_active pipeline Core crystal clock cycles when this thread is unhalted and the other thread is halted event=0x3c,period=25003,umask=2 00 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_xclk pipeline Core crystal clock cycles when the thread is unhalted event=0x3c,period=25003,umask=1 00 cpu_clk_unhalted.ref_xclk_any pipeline Core crystal clock cycles when at least one thread on the physical core is unhalted event=0x3c,any=1,period=25003,umask=1 00 cpu_clk_unhalted.ring0_trans pipeline Counts when there is a transition from ring 1, 2 or 3 to ring 0 event=0x3c,cmask=1,edge=1,period=100007 00 Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel) cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003 00 Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cycle_activity.cycles_mem_any pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=16,period=2000003,umask=0x10 00 cycle_activity.stalls_mem_any pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=20,period=2000003,umask=0x14 00 exe_activity.bound_on_stores pipeline Cycles where the Store Buffer was full and no outstanding load event=0xa6,period=2000003,umask=0x40 00 exe_activity.exe_bound_0_ports pipeline Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load event=0xa6,period=2000003,umask=1 00 Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP] event=0x87,period=2000003,umask=1 00 Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP] inst_decoded.decoders pipeline Instruction decoders utilized in a cycle event=0x55,period=2000003,umask=1 00 Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003 00 Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event Spec update: SKL091, SKL044 event=0xc0,period=2000003 00 Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two) Spec update: SKL091, SKL044 inst_retired.nop pipeline Number of all retired NOP instructions Spec update: SKL091, SKL044 (Precise event) event=0xc0,period=2000003,umask=2 00 inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: SKL091, SKL044 (Must be precise) event=0xc0,period=2000003,umask=1 00 A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled Spec update: SKL091, SKL044 (Must be precise) inst_retired.total_cycles_ps pipeline Number of cycles using always true condition applied to PEBS instructions retired event Spec update: SKL091, SKL044 (Must be precise) event=0xc0,cmask=10,inv=1,period=2000003,umask=1 00 Number of cycles using an always true condition applied to PEBS instructions retired event. (inst_ret< 16) Spec update: SKL091, SKL044 (Must be precise) int_misc.clears_count pipeline Clears speculative count event=0xd,cmask=1,edge=1,period=2000003,umask=1 00 Counts the number of speculative clears due to any type of branch misprediction or machine clears int_misc.clear_resteer_cycles pipeline Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events event=0xd,period=2000003,umask=0x80 00 int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) event=0xd,period=2000003,umask=1 00 Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event int_misc.recovery_cycles_any pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) event=0xd,any=1,period=2000003,umask=1 00 ld_blocks.no_sr pipeline The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=3,period=100003,umask=8 00 The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks.store_forward pipeline Loads blocked due to overlapping with a preceding store that cannot be forwarded event=3,period=100003,umask=2 00 Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=7,period=100003,umask=1 00 Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased load_hit_pre.sw_pf pipeline Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch event=0x4c,period=100003,umask=1 00 Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions lsd.cycles_4_uops pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_OK] event=0xa8,cmask=4,period=2000003,umask=1 00 Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_OK] lsd.cycles_ok pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS] event=0xa8,cmask=4,period=2000003,umask=1 00 Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_4_UOPS] lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=1 00 Number of uops delivered to the back-end by the LSD(Loop Stream Detector) other_assists.any pipeline Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists event=0xc1,period=100003,umask=0x3f 00 partial_rat_stalls.scoreboard pipeline Cycles where the pipeline is stalled due to serializing operations event=0x59,period=2000003,umask=1 00 This event counts cycles during which the microcode scoreboard stalls happen resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=1 00 Counts resource-related stall cycles resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=8 00 Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end rob_misc_events.lbr_inserts pipeline Increments whenever there is an update to the LBR array event=0xcc,period=2000003,umask=0x20 00 Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT rob_misc_events.pause_inst pipeline Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products event=0xcc,period=2000003,umask=0x40 00 rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=1 00 Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues event=0x5e,cmask=1,edge=1,inv=1,period=2000003,umask=1 00 Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues uops_dispatched_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=1 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=2 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1 uops_dispatched_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=4 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2 uops_dispatched_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=8 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5 uops_dispatched_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6 uops_dispatched_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7 uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core event=0xb1,cmask=1,inv=1,period=2000003,umask=2 00 uops_executed.cycles_ge_1_uop_exec pipeline Cycles where at least 1 uop was executed per-thread event=0xb1,cmask=1,period=2000003,umask=1 00 Cycles where at least 1 uop was executed per-thread uops_executed.cycles_ge_2_uops_exec pipeline Cycles where at least 2 uops were executed per-thread event=0xb1,cmask=2,period=2000003,umask=1 00 Cycles where at least 2 uops were executed per-thread uops_executed.cycles_ge_3_uops_exec pipeline Cycles where at least 3 uops were executed per-thread event=0xb1,cmask=3,period=2000003,umask=1 00 Cycles where at least 3 uops were executed per-thread uops_executed.cycles_ge_4_uops_exec pipeline Cycles where at least 4 uops were executed per-thread event=0xb1,cmask=4,period=2000003,umask=1 00 Cycles where at least 4 uops were executed per-thread uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=1 00 Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=1 00 Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=1 00 Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_issued.vector_width_mismatch pipeline Uops inserted at issue-stage in order to preserve upper bits of vector registers event=0xe,period=2000003,umask=2 00 Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide uops_retired.macro_fused pipeline Number of macro-fused uops retired. (non precise) event=0xc2,period=2000003,umask=4 00 Counts the number of macro-fused uops retired. (non precise) uops_retired.retire_slots pipeline Retirement slots used event=0xc2,period=2000003,umask=2 00 Counts the retirement slots used uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=2 00 This event counts cycles without actually retired uops uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=16,inv=1,period=2000003,umask=2 00 Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event uncore_cha llc_misses.mmio_read uncore cache MMIO reads. Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x40040e33 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_misses.mmio_write uncore cache MMIO writes. Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x40041e33 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_misses.uncacheable uncore cache LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x40e33 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_references.streaming_full uncore cache Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x41833 0164Bytes TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_references.streaming_partial uncore cache Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x41a33 0164Bytes TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_ag0_ad_crd_acquired.tgr0 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 0 event=0x80,umask=1 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr1 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 1 event=0x80,umask=2 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr2 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 2 event=0x80,umask=4 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr3 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 3 event=0x80,umask=8 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr4 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 4 event=0x80,umask=0x10 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr5 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 5 event=0x80,umask=0x20 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr0 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 0 event=0x82,umask=1 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr1 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 1 event=0x82,umask=2 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr2 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 2 event=0x82,umask=4 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr3 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 3 event=0x82,umask=8 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr4 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 4 event=0x82,umask=0x10 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr5 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 5 event=0x82,umask=0x20 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr0 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 0 event=0x88,umask=1 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr1 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 1 event=0x88,umask=2 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr2 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 2 event=0x88,umask=4 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr3 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 3 event=0x88,umask=8 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr4 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 4 event=0x88,umask=0x10 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr5 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 5 event=0x88,umask=0x20 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr0 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 0 event=0x8a,umask=1 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr1 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 1 event=0x8a,umask=2 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr2 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 2 event=0x8a,umask=4 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr3 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 3 event=0x8a,umask=8 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr4 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 4 event=0x8a,umask=0x10 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr5 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 5 event=0x8a,umask=0x20 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr0 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 0 event=0x84,umask=1 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr1 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 1 event=0x84,umask=2 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr2 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 2 event=0x84,umask=4 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr3 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 3 event=0x84,umask=8 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr4 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 4 event=0x84,umask=0x10 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr5 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 5 event=0x84,umask=0x20 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr0 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 0 event=0x86,umask=1 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr1 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 1 event=0x86,umask=2 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr2 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 2 event=0x86,umask=4 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr3 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 3 event=0x86,umask=8 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr4 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 4 event=0x86,umask=0x10 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr5 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 5 event=0x86,umask=0x20 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr0 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 0 event=0x8e,umask=1 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr1 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 1 event=0x8e,umask=2 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr2 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 2 event=0x8e,umask=4 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr3 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 3 event=0x8e,umask=8 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr4 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 4 event=0x8e,umask=0x10 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr5 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 5 event=0x8e,umask=0x20 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr0 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 0 event=0x8c,umask=1 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr1 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 1 event=0x8c,umask=2 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr2 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 2 event=0x8c,umask=4 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr3 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 3 event=0x8c,umask=8 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr4 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 4 event=0x8c,umask=0x10 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr5 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 5 event=0x8c,umask=0x20 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_bypass_cha_imc.intermediate uncore cache CHA to iMC Bypass; Intermediate bypass Taken event=0x57,umask=2 01 Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass unc_cha_bypass_cha_imc.not_taken uncore cache CHA to iMC Bypass; Not Taken event=0x57,umask=4 01 Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted unc_cha_bypass_cha_imc.taken uncore cache CHA to iMC Bypass; Taken event=0x57,umask=1 01 Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass unc_cha_clockticks uncore cache Uncore cache clock ticks event=0 01 Counts clockticks of the clock controlling the uncore caching and home agent (CHA) unc_cha_cms_clockticks uncore cache CMS Clockticks event=0xc0 01 unc_cha_core_pma.c1_state uncore cache Core PMA Events; C1 State event=0x17,umask=1 01 unc_cha_core_pma.c1_transition uncore cache Core PMA Events; C1 Transition event=0x17,umask=2 01 unc_cha_core_pma.c6_state uncore cache Core PMA Events; C6 State event=0x17,umask=4 01 unc_cha_core_pma.c6_transition uncore cache Core PMA Events; C6 Transition event=0x17,umask=8 01 unc_cha_core_pma.gv uncore cache Core PMA Events; GV event=0x17,umask=0x10 01 unc_cha_core_snp.any_gtone uncore cache Core Cross Snoops Issued; Any Cycle with Multiple Snoops event=0x33,umask=0xe2 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.any_one uncore cache Core Cross Snoops Issued; Any Single Snoop event=0x33,umask=0xe1 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.any_remote uncore cache Core Cross Snoops Issued; Any Snoop to Remote Node event=0x33,umask=0xe4 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_gtone uncore cache Core Cross Snoops Issued; Multiple Core Requests event=0x33,umask=0x42 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_one uncore cache Core Cross Snoops Issued; Single Core Requests event=0x33,umask=0x41 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_remote uncore cache Core Cross Snoops Issued; Core Request to Remote Node event=0x33,umask=0x44 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_gtone uncore cache Core Cross Snoops Issued; Multiple Eviction event=0x33,umask=0x82 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_one uncore cache Core Cross Snoops Issued; Single Eviction event=0x33,umask=0x81 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_remote uncore cache Core Cross Snoops Issued; Eviction to Remote Node event=0x33,umask=0x84 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_gtone uncore cache Core Cross Snoops Issued; Multiple External Snoops event=0x33,umask=0x22 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_one uncore cache Core Cross Snoops Issued; Single External Snoops event=0x33,umask=0x21 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_remote uncore cache Core Cross Snoops Issued; External Snoop to Remote Node event=0x33,umask=0x24 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_counter0_occupancy uncore cache Counter 0 Occupancy event=0x1f 01 Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry unc_cha_dir_lookup.no_snp uncore cache Multi-socket cacheline Directory state lookups; Snoop Not Needed event=0x53,umask=2 01 Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed unc_cha_dir_lookup.snp uncore cache Multi-socket cacheline Directory state lookups; Snoop Needed event=0x53,umask=1 01 Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed unc_cha_dir_update.ha uncore cache Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe event=0x54,umask=1 01 Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_dir_update.tor uncore cache Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe event=0x54,umask=2 01 Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_egress_ordering.iv_snoopgo_dn uncore cache Egress Blocking due to Ordering requirements; Down event=0xae,umask=4 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_egress_ordering.iv_snoopgo_up uncore cache Egress Blocking due to Ordering requirements; Up event=0xae,umask=1 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_fast_asserted.horz uncore cache FaST wire asserted; Horizontal event=0xa5,umask=2 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_cha_fast_asserted.vert uncore cache FaST wire asserted; Vertical event=0xa5,umask=1 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_cha_hitme_hit.ex_rds uncore cache Read request from a remote socket which hit in the HitMe Cache to a line In the E state event=0x5f,umask=1 01 Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*) unc_cha_hitme_hit.shared_ownreq uncore cache Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv* event=0x5f,umask=4 01 unc_cha_hitme_hit.wbmtoe uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoE event=0x5f,umask=8 01 unc_cha_hitme_hit.wbmtoi_or_s uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5f,umask=0x10 01 unc_cha_hitme_lookup.read uncore cache Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv* event=0x5e,umask=1 01 unc_cha_hitme_lookup.write uncore cache Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5e,umask=2 01 unc_cha_hitme_miss.notshared_rdinvown uncore cache Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x40 01 unc_cha_hitme_miss.read_or_inv uncore cache Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv* event=0x60,umask=0x80 01 unc_cha_hitme_miss.shared_rdinvown uncore cache Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x20 01 unc_cha_hitme_update.deallocate uncore cache Counts the number of Allocate/Update to HitMe Cache; Deallocate HitME$ on Reads without RspFwdI* event=0x61,umask=0x10 01 unc_cha_hitme_update.deallocate_rspfwdi_loc uncore cache Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request event=0x61,umask=1 01 Received RspFwdI* for a local request, but converted HitME$ to SF entry unc_cha_hitme_update.rdinvown uncore cache Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI* event=0x61,umask=8 01 unc_cha_hitme_update.rspfwdi_rem uncore cache Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request event=0x61,umask=2 01 Updated HitME$ on RspFwdI* or local HitM/E received for a remote request unc_cha_hitme_update.shared uncore cache Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed event=0x61,umask=4 01 unc_cha_horz_ring_ad_in_use.left_even uncore cache Horizontal AD Ring In Use; Left and Even event=0xa7,umask=1 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.left_odd uncore cache Horizontal AD Ring In Use; Left and Odd event=0xa7,umask=2 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_even uncore cache Horizontal AD Ring In Use; Right and Even event=0xa7,umask=4 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_odd uncore cache Horizontal AD Ring In Use; Right and Odd event=0xa7,umask=8 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_even uncore cache Horizontal AK Ring In Use; Left and Even event=0xa9,umask=1 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_odd uncore cache Horizontal AK Ring In Use; Left and Odd event=0xa9,umask=2 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_even uncore cache Horizontal AK Ring In Use; Right and Even event=0xa9,umask=4 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_odd uncore cache Horizontal AK Ring In Use; Right and Odd event=0xa9,umask=8 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_even uncore cache Horizontal BL Ring in Use; Left and Even event=0xab,umask=1 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_odd uncore cache Horizontal BL Ring in Use; Left and Odd event=0xab,umask=2 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_even uncore cache Horizontal BL Ring in Use; Right and Even event=0xab,umask=4 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_odd uncore cache Horizontal BL Ring in Use; Right and Odd event=0xab,umask=8 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_iv_in_use.left uncore cache Horizontal IV Ring in Use; Left event=0xad,umask=1 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_horz_ring_iv_in_use.right uncore cache Horizontal IV Ring in Use; Right event=0xad,umask=4 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_imc_reads_count.normal uncore cache Normal priority reads issued to the memory controller from the CHA event=0x59,umask=1 01 Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA unc_cha_imc_reads_count.priority uncore cache HA to iMC Reads Issued; ISOCH event=0x59,umask=2 01 Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads unc_cha_imc_writes_count.full uncore cache CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH event=0x5b,umask=1 01 Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels unc_cha_imc_writes_count.full_mig uncore cache Writes Issued to the iMC by the HA; Full Line MIG event=0x5b,umask=0x10 01 Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_imc_writes_count.full_priority uncore cache Writes Issued to the iMC by the HA; ISOCH Full Line event=0x5b,umask=4 01 Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_imc_writes_count.partial uncore cache Writes Issued to the iMC by the HA; Partial Non-ISOCH event=0x5b,umask=2 01 Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_imc_writes_count.partial_mig uncore cache Writes Issued to the iMC by the HA; Partial MIG event=0x5b,umask=0x20 01 Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only unc_cha_imc_writes_count.partial_priority uncore cache Writes Issued to the iMC by the HA; ISOCH Partial event=0x5b,umask=8 01 Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_iodc_alloc.invitom uncore cache Counts Number of times IODC entry allocation is attempted; Number of IODC allocations event=0x62,umask=1 01 unc_cha_iodc_alloc.iodcfull uncore cache Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full event=0x62,umask=2 01 unc_cha_iodc_alloc.osbgated uncore cache Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate event=0x62,umask=4 01 unc_cha_iodc_dealloc.all uncore cache Counts number of IODC deallocations; IODC deallocated due to any reason event=0x63,umask=0x10 01 unc_cha_iodc_dealloc.snpout uncore cache Counts number of IODC deallocations; IODC deallocated due to conflicting transaction event=0x63,umask=8 01 unc_cha_iodc_dealloc.wbmtoe uncore cache Counts number of IODC deallocations; IODC deallocated due to WbMtoE event=0x63,umask=1 01 unc_cha_iodc_dealloc.wbmtoi uncore cache Counts number of IODC deallocations; IODC deallocated due to WbMtoI event=0x63,umask=2 01 unc_cha_iodc_dealloc.wbpushmtoi uncore cache Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI event=0x63,umask=4 01 Moved to Cbo section unc_cha_llc_lookup.any uncore cache Cache and Snoop Filter Lookups; Any Request event=0x34,umask=0x11 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_cha_llc_lookup.data_read uncore cache Cache and Snoop Filter Lookups; Data Read Request event=0x34,umask=3 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions unc_cha_llc_lookup.local uncore cache Cache and Snoop Filter Lookups; Local event=0x34,umask=0x31 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state unc_cha_llc_lookup.remote uncore cache Cache and Snoop Filter Lookups; Remote event=0x34,umask=0x91 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state unc_cha_llc_lookup.remote_snoop uncore cache Cache and Snoop Filter Lookups; External Snoop Request event=0x34,umask=9 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ unc_cha_llc_lookup.write uncore cache Cache and Snoop Filter Lookups; Write Requests event=0x34,umask=5 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_cha_llc_victims.e_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E event=0x37,umask=2 11 unc_cha_llc_victims.f_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F event=0x37,umask=8 11 unc_cha_llc_victims.local uncore cache This event is deprecated event=0x37,umask=0x20 11 unc_cha_llc_victims.local_all uncore cache Lines Victimized; Local - All Lines event=0x37,umask=0x2f 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_e uncore cache Lines Victimized; Local - Lines in E State event=0x37,umask=0x22 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_f uncore cache Lines Victimized; Local - Lines in F State event=0x37,umask=0x28 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_m uncore cache Lines Victimized; Local - Lines in M State event=0x37,umask=0x21 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_s uncore cache Lines Victimized; Local - Lines in S State event=0x37,umask=0x24 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.m_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M event=0x37,umask=1 11 unc_cha_llc_victims.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL event=0x37,umask=0x80 11 unc_cha_llc_victims.remote_all uncore cache Lines Victimized; Remote - All Lines event=0x37,umask=0x8f 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_e uncore cache Lines Victimized; Remote - Lines in E State event=0x37,umask=0x82 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_f uncore cache Lines Victimized; Remote - Lines in F State event=0x37,umask=0x88 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_m uncore cache Lines Victimized; Remote - Lines in M State event=0x37,umask=0x81 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_s uncore cache Lines Victimized; Remote - Lines in S State event=0x37,umask=0x84 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.s_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S event=0x37,umask=4 11 unc_cha_llc_victims.total_e uncore cache Lines Victimized; Lines in E state event=0x37,umask=2 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_f uncore cache Lines Victimized; Lines in F State event=0x37,umask=8 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_m uncore cache Lines Victimized; Lines in M state event=0x37,umask=1 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_s uncore cache Lines Victimized; Lines in S State event=0x37,umask=4 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_misc.cv0_pref_miss uncore cache Cbo Misc; CV0 Prefetch Miss event=0x39,umask=0x20 01 Miscellaneous events in the Cbo unc_cha_misc.cv0_pref_vic uncore cache Cbo Misc; CV0 Prefetch Victim event=0x39,umask=0x10 01 Miscellaneous events in the Cbo unc_cha_misc.rfo_hit_s uncore cache Number of times that an RFO hit in S state event=0x39,umask=8 01 Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state unc_cha_misc.rspi_was_fse uncore cache Cbo Misc; Silent Snoop Eviction event=0x39,umask=1 01 Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings unc_cha_misc.wc_aliasing uncore cache Cbo Misc; Write Combining Aliasing event=0x39,umask=2 01 Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing unc_cha_osb uncore cache OSB Snoop Broadcast event=0x55 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_pmm_memmode_nm_setconflicts.iodc uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in IODC event=0x64,umask=0x10 01 2LM related events; Counts the number of times CHA saw NM Set conflict in IODC unc_cha_pmm_memmode_nm_setconflicts.llc uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=2 01 NM evictions due to another read to the same near memory set in the LLC unc_cha_pmm_memmode_nm_setconflicts.sf uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=1 01 NM evictions due to another read to the same near memory set in the SF unc_cha_pmm_memmode_nm_setconflicts.tor uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in TOR event=0x64,umask=4 01 No Reject in the CHA due to a pending read to the same near memory set in the TOR unc_cha_pmm_memmode_nm_setconflicts.tor_reject uncore cache Memory mode related events; Counts the number of times CHA saw NM Set conflict in TOR and the transaction was rejected event=0x64,umask=8 01 Rejects in the CHA due to a pending read to the same near memory set in the TOR unc_cha_read_no_credits.edc0_smi2 uncore cache CHA iMC CHNx READ Credits Empty; EDC0_SMI2 event=0x58,umask=4 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only unc_cha_read_no_credits.edc1_smi3 uncore cache CHA iMC CHNx READ Credits Empty; EDC1_SMI3 event=0x58,umask=8 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only unc_cha_read_no_credits.edc2_smi4 uncore cache CHA iMC CHNx READ Credits Empty; EDC2_SMI4 event=0x58,umask=0x10 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only unc_cha_read_no_credits.edc3_smi5 uncore cache CHA iMC CHNx READ Credits Empty; EDC3_SMI5 event=0x58,umask=0x20 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only unc_cha_read_no_credits.mc0_smi0 uncore cache CHA iMC CHNx READ Credits Empty; MC0_SMI0 event=0x58,umask=1 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only unc_cha_read_no_credits.mc1_smi1 uncore cache CHA iMC CHNx READ Credits Empty; MC1_SMI1 event=0x58,umask=2 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only unc_cha_requests.invitoe_local uncore cache Local requests for exclusive ownership of a cache line without receiving data event=0x50,umask=0x10 01 Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_remote uncore cache Local requests for exclusive ownership of a cache line without receiving data event=0x50,umask=0x20 01 Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.reads uncore cache Read requests event=0x50,umask=3 01 Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.reads_local uncore cache Read requests from a unit on this socket event=0x50,umask=1 01 Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.reads_remote uncore cache Read requests from a remote socket event=0x50,umask=2 01 Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.writes uncore cache Write requests event=0x50,umask=0xc 01 Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_local uncore cache Write Requests from a unit on this socket event=0x50,umask=4 01 Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_remote uncore cache Read and Write Requests; Writes Remote event=0x50,umask=8 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc) unc_cha_ring_bounces_horz.ad uncore cache Messages that bounced on the Horizontal Ring.; AD event=0xa1,umask=1 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.ak uncore cache Messages that bounced on the Horizontal Ring.; AK event=0xa1,umask=2 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.bl uncore cache Messages that bounced on the Horizontal Ring.; BL event=0xa1,umask=4 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.iv uncore cache Messages that bounced on the Horizontal Ring.; IV event=0xa1,umask=8 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_vert.ad uncore cache Messages that bounced on the Vertical Ring.; AD event=0xa0,umask=1 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.ak uncore cache Messages that bounced on the Vertical Ring.; Acknowledgements to core event=0xa0,umask=2 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.bl uncore cache Messages that bounced on the Vertical Ring.; Data Responses to core event=0xa0,umask=4 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.iv uncore cache Messages that bounced on the Vertical Ring.; Snoops of processor's cache event=0xa0,umask=8 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_sink_starved_horz.ad uncore cache Sink Starvation on Horizontal Ring; AD event=0xa3,umask=1 01 unc_cha_ring_sink_starved_horz.ak uncore cache Sink Starvation on Horizontal Ring; AK event=0xa3,umask=2 01 unc_cha_ring_sink_starved_horz.ak_ag1 uncore cache Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1 event=0xa3,umask=0x20 01 unc_cha_ring_sink_starved_horz.bl uncore cache Sink Starvation on Horizontal Ring; BL event=0xa3,umask=4 01 unc_cha_ring_sink_starved_horz.iv uncore cache Sink Starvation on Horizontal Ring; IV event=0xa3,umask=8 01 unc_cha_ring_sink_starved_vert.ad uncore cache Sink Starvation on Vertical Ring; AD event=0xa2,umask=1 01 unc_cha_ring_sink_starved_vert.ak uncore cache Sink Starvation on Vertical Ring; Acknowledgements to core event=0xa2,umask=2 01 unc_cha_ring_sink_starved_vert.bl uncore cache Sink Starvation on Vertical Ring; Data Responses to core event=0xa2,umask=4 01 unc_cha_ring_sink_starved_vert.iv uncore cache Sink Starvation on Vertical Ring; Snoops of processor's cache event=0xa2,umask=8 01 unc_cha_ring_src_thrtl uncore cache Source Throttle event=0xa4 01 unc_cha_rxc_inserts.ipq uncore cache Ingress (from CMS) Allocations; IPQ event=0x13,umask=4 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq uncore cache Ingress (from CMS) Allocations; IRQ event=0x13,umask=1 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq_rej uncore cache Ingress (from CMS) Allocations; IRQ Rejected event=0x13,umask=2 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq uncore cache Ingress (from CMS) Allocations; PRQ event=0x13,umask=0x10 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq_rej uncore cache Ingress (from CMS) Allocations; PRQ event=0x13,umask=0x20 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.rrq uncore cache Ingress (from CMS) Allocations; RRQ event=0x13,umask=0x40 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.wbq uncore cache Ingress (from CMS) Allocations; WBQ event=0x13,umask=0x80 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_ipq0_reject.ad_req_vn0 uncore cache Ingress Probe Queue Rejects; AD REQ on VN0 event=0x22,umask=1 01 unc_cha_rxc_ipq0_reject.ad_rsp_vn0 uncore cache Ingress Probe Queue Rejects; AD RSP on VN0 event=0x22,umask=2 01 unc_cha_rxc_ipq0_reject.ak_non_upi uncore cache Ingress Probe Queue Rejects; Non UPI AK Request event=0x22,umask=0x40 01 unc_cha_rxc_ipq0_reject.bl_ncb_vn0 uncore cache Ingress Probe Queue Rejects; BL NCB on VN0 event=0x22,umask=0x10 01 unc_cha_rxc_ipq0_reject.bl_ncs_vn0 uncore cache Ingress Probe Queue Rejects; BL NCS on VN0 event=0x22,umask=0x20 01 unc_cha_rxc_ipq0_reject.bl_rsp_vn0 uncore cache Ingress Probe Queue Rejects; BL RSP on VN0 event=0x22,umask=4 01 unc_cha_rxc_ipq0_reject.bl_wb_vn0 uncore cache Ingress Probe Queue Rejects; BL WB on VN0 event=0x22,umask=8 01 unc_cha_rxc_ipq0_reject.iv_non_upi uncore cache Ingress Probe Queue Rejects; Non UPI IV Request event=0x22,umask=0x80 01 unc_cha_rxc_ipq1_reject.allow_snp uncore cache Ingress Probe Queue Rejects; Allow Snoop event=0x23,umask=0x40 01 unc_cha_rxc_ipq1_reject.any0 uncore cache Ingress Probe Queue Rejects; ANY0 event=0x23,umask=1 01 unc_cha_rxc_ipq1_reject.ha uncore cache Ingress Probe Queue Rejects; HA event=0x23,umask=2 01 unc_cha_rxc_ipq1_reject.llc_or_sf_way uncore cache Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x23,umask=0x20 01 unc_cha_rxc_ipq1_reject.llc_victim uncore cache Ingress Probe Queue Rejects; LLC Victim event=0x23,umask=4 01 unc_cha_rxc_ipq1_reject.pa_match uncore cache Ingress Probe Queue Rejects; PhyAddr Match event=0x23,umask=0x80 01 unc_cha_rxc_ipq1_reject.sf_victim uncore cache Ingress Probe Queue Rejects; SF Victim event=0x23,umask=8 01 unc_cha_rxc_ipq1_reject.victim uncore cache Ingress Probe Queue Rejects; Victim event=0x23,umask=0x10 01 unc_cha_rxc_irq0_reject.ad_req_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD REQ on VN0 event=0x18,umask=1 01 unc_cha_rxc_irq0_reject.ad_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD RSP on VN0 event=0x18,umask=2 01 unc_cha_rxc_irq0_reject.ak_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI AK Request event=0x18,umask=0x40 01 unc_cha_rxc_irq0_reject.bl_ncb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCB on VN0 event=0x18,umask=0x10 01 unc_cha_rxc_irq0_reject.bl_ncs_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCS on VN0 event=0x18,umask=0x20 01 unc_cha_rxc_irq0_reject.bl_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL RSP on VN0 event=0x18,umask=4 01 unc_cha_rxc_irq0_reject.bl_wb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL WB on VN0 event=0x18,umask=8 01 unc_cha_rxc_irq0_reject.iv_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI IV Request event=0x18,umask=0x80 01 unc_cha_rxc_irq1_reject.allow_snp uncore cache Ingress (from CMS) Request Queue Rejects; Allow Snoop event=0x19,umask=0x40 01 unc_cha_rxc_irq1_reject.any0 uncore cache Ingress (from CMS) Request Queue Rejects; ANY0 event=0x19,umask=1 01 unc_cha_rxc_irq1_reject.ha uncore cache Ingress (from CMS) Request Queue Rejects; HA event=0x19,umask=2 01 unc_cha_rxc_irq1_reject.llc_or_sf_way uncore cache Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x19,umask=0x20 01 unc_cha_rxc_irq1_reject.llc_victim uncore cache Ingress (from CMS) Request Queue Rejects; LLC Victim event=0x19,umask=4 01 unc_cha_rxc_irq1_reject.pa_match uncore cache Ingress (from CMS) Request Queue Rejects; PhyAddr Match event=0x19,umask=0x80 01 unc_cha_rxc_irq1_reject.sf_victim uncore cache Ingress (from CMS) Request Queue Rejects; SF Victim event=0x19,umask=8 01 unc_cha_rxc_irq1_reject.victim uncore cache Ingress (from CMS) Request Queue Rejects; Victim event=0x19,umask=0x10 01 unc_cha_rxc_ismq0_reject.ad_req_vn0 uncore cache ISMQ Rejects; AD REQ on VN0 event=0x24,umask=1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.ad_rsp_vn0 uncore cache ISMQ Rejects; AD RSP on VN0 event=0x24,umask=2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.ak_non_upi uncore cache ISMQ Rejects; Non UPI AK Request event=0x24,umask=0x40 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_ncb_vn0 uncore cache ISMQ Rejects; BL NCB on VN0 event=0x24,umask=0x10 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_ncs_vn0 uncore cache ISMQ Rejects; BL NCS on VN0 event=0x24,umask=0x20 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_rsp_vn0 uncore cache ISMQ Rejects; BL RSP on VN0 event=0x24,umask=4 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_wb_vn0 uncore cache ISMQ Rejects; BL WB on VN0 event=0x24,umask=8 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.iv_non_upi uncore cache ISMQ Rejects; Non UPI IV Request event=0x24,umask=0x80 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.ad_req_vn0 uncore cache ISMQ Retries; AD REQ on VN0 event=0x2c,umask=1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.ad_rsp_vn0 uncore cache ISMQ Retries; AD RSP on VN0 event=0x2c,umask=2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.ak_non_upi uncore cache ISMQ Retries; Non UPI AK Request event=0x2c,umask=0x40 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_ncb_vn0 uncore cache ISMQ Retries; BL NCB on VN0 event=0x2c,umask=0x10 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_ncs_vn0 uncore cache ISMQ Retries; BL NCS on VN0 event=0x2c,umask=0x20 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_rsp_vn0 uncore cache ISMQ Retries; BL RSP on VN0 event=0x2c,umask=4 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_wb_vn0 uncore cache ISMQ Retries; BL WB on VN0 event=0x2c,umask=8 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.iv_non_upi uncore cache ISMQ Retries; Non UPI IV Request event=0x2c,umask=0x80 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_reject.any0 uncore cache ISMQ Rejects; ANY0 event=0x25,umask=1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_reject.ha uncore cache ISMQ Rejects; HA event=0x25,umask=2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_retry.any0 uncore cache ISMQ Retries; ANY0 event=0x2d,umask=1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_retry.ha uncore cache ISMQ Retries; HA event=0x2d,umask=2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_occupancy.ipq uncore cache Ingress (from CMS) Occupancy; IPQ event=0x11,umask=4 01 Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.irq uncore cache Ingress (from CMS) Occupancy; IRQ event=0x11,umask=1 01 Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.rrq uncore cache Ingress (from CMS) Occupancy; RRQ event=0x11,umask=0x40 01 Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.wbq uncore cache Ingress (from CMS) Occupancy; WBQ event=0x11,umask=0x80 01 Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_other0_retry.ad_req_vn0 uncore cache Other Retries; AD REQ on VN0 event=0x2e,umask=1 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.ad_rsp_vn0 uncore cache Other Retries; AD RSP on VN0 event=0x2e,umask=2 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.ak_non_upi uncore cache Other Retries; Non UPI AK Request event=0x2e,umask=0x40 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_ncb_vn0 uncore cache Other Retries; BL NCB on VN0 event=0x2e,umask=0x10 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_ncs_vn0 uncore cache Other Retries; BL NCS on VN0 event=0x2e,umask=0x20 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_rsp_vn0 uncore cache Other Retries; BL RSP on VN0 event=0x2e,umask=4 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_wb_vn0 uncore cache Other Retries; BL WB on VN0 event=0x2e,umask=8 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.iv_non_upi uncore cache Other Retries; Non UPI IV Request event=0x2e,umask=0x80 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.allow_snp uncore cache Other Retries; Allow Snoop event=0x2f,umask=0x40 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.any0 uncore cache Other Retries; ANY0 event=0x2f,umask=1 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.ha uncore cache Other Retries; HA event=0x2f,umask=2 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.llc_or_sf_way uncore cache Other Retries; Merging these two together to make room for ANY_REJECT_*0 event=0x2f,umask=0x20 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.llc_victim uncore cache Other Retries; LLC Victim event=0x2f,umask=4 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.pa_match uncore cache Other Retries; PhyAddr Match event=0x2f,umask=0x80 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.sf_victim uncore cache Other Retries; SF Victim event=0x2f,umask=8 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.victim uncore cache Other Retries; Victim event=0x2f,umask=0x10 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_prq0_reject.ad_req_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD REQ on VN0 event=0x20,umask=1 01 unc_cha_rxc_prq0_reject.ad_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD RSP on VN0 event=0x20,umask=2 01 unc_cha_rxc_prq0_reject.ak_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI AK Request event=0x20,umask=0x40 01 unc_cha_rxc_prq0_reject.bl_ncb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCB on VN0 event=0x20,umask=0x10 01 unc_cha_rxc_prq0_reject.bl_ncs_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCS on VN0 event=0x20,umask=0x20 01 unc_cha_rxc_prq0_reject.bl_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL RSP on VN0 event=0x20,umask=4 01 unc_cha_rxc_prq0_reject.bl_wb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL WB on VN0 event=0x20,umask=8 01 unc_cha_rxc_prq0_reject.iv_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI IV Request event=0x20,umask=0x80 01 unc_cha_rxc_prq1_reject.allow_snp uncore cache Ingress (from CMS) Request Queue Rejects; Allow Snoop event=0x21,umask=0x40 01 unc_cha_rxc_prq1_reject.any0 uncore cache Ingress (from CMS) Request Queue Rejects; ANY0 event=0x21,umask=1 01 unc_cha_rxc_prq1_reject.ha uncore cache Ingress (from CMS) Request Queue Rejects; HA event=0x21,umask=2 01 unc_cha_rxc_prq1_reject.llc_or_sf_way uncore cache Ingress (from CMS) Request Queue Rejects; LLC OR SF Way event=0x21,umask=0x20 01 unc_cha_rxc_prq1_reject.llc_victim uncore cache Ingress (from CMS) Request Queue Rejects; LLC Victim event=0x21,umask=4 01 unc_cha_rxc_prq1_reject.pa_match uncore cache Ingress (from CMS) Request Queue Rejects; PhyAddr Match event=0x21,umask=0x80 01 unc_cha_rxc_prq1_reject.sf_victim uncore cache Ingress (from CMS) Request Queue Rejects; SF Victim event=0x21,umask=8 01 unc_cha_rxc_prq1_reject.victim uncore cache Ingress (from CMS) Request Queue Rejects; Victim event=0x21,umask=0x10 01 unc_cha_rxc_req_q0_retry.ad_req_vn0 uncore cache Request Queue Retries; AD REQ on VN0 event=0x2a,umask=1 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.ad_rsp_vn0 uncore cache Request Queue Retries; AD RSP on VN0 event=0x2a,umask=2 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.ak_non_upi uncore cache Request Queue Retries; Non UPI AK Request event=0x2a,umask=0x40 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_ncb_vn0 uncore cache Request Queue Retries; BL NCB on VN0 event=0x2a,umask=0x10 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_ncs_vn0 uncore cache Request Queue Retries; BL NCS on VN0 event=0x2a,umask=0x20 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_rsp_vn0 uncore cache Request Queue Retries; BL RSP on VN0 event=0x2a,umask=4 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_wb_vn0 uncore cache Request Queue Retries; BL WB on VN0 event=0x2a,umask=8 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.iv_non_upi uncore cache Request Queue Retries; Non UPI IV Request event=0x2a,umask=0x80 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.allow_snp uncore cache Request Queue Retries; Allow Snoop event=0x2b,umask=0x40 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.any0 uncore cache Request Queue Retries; ANY0 event=0x2b,umask=1 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.ha uncore cache Request Queue Retries; HA event=0x2b,umask=2 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.llc_or_sf_way uncore cache Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0 event=0x2b,umask=0x20 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.llc_victim uncore cache Request Queue Retries; LLC Victim event=0x2b,umask=4 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.pa_match uncore cache Request Queue Retries; PhyAddr Match event=0x2b,umask=0x80 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.sf_victim uncore cache Request Queue Retries; SF Victim event=0x2b,umask=8 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.victim uncore cache Request Queue Retries; Victim event=0x2b,umask=0x10 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_rrq0_reject.ad_req_vn0 uncore cache RRQ Rejects; AD REQ on VN0 event=0x26,umask=1 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.ad_rsp_vn0 uncore cache RRQ Rejects; AD RSP on VN0 event=0x26,umask=2 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.ak_non_upi uncore cache RRQ Rejects; Non UPI AK Request event=0x26,umask=0x40 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_ncb_vn0 uncore cache RRQ Rejects; BL NCB on VN0 event=0x26,umask=0x10 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_ncs_vn0 uncore cache RRQ Rejects; BL NCS on VN0 event=0x26,umask=0x20 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_rsp_vn0 uncore cache RRQ Rejects; BL RSP on VN0 event=0x26,umask=4 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_wb_vn0 uncore cache RRQ Rejects; BL WB on VN0 event=0x26,umask=8 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.iv_non_upi uncore cache RRQ Rejects; Non UPI IV Request event=0x26,umask=0x80 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.allow_snp uncore cache RRQ Rejects; Allow Snoop event=0x27,umask=0x40 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.any0 uncore cache RRQ Rejects; ANY0 event=0x27,umask=1 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.ha uncore cache RRQ Rejects; HA event=0x27,umask=2 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.llc_or_sf_way uncore cache RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x27,umask=0x20 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.llc_victim uncore cache RRQ Rejects; LLC Victim event=0x27,umask=4 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.pa_match uncore cache RRQ Rejects; PhyAddr Match event=0x27,umask=0x80 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.sf_victim uncore cache RRQ Rejects; SF Victim event=0x27,umask=8 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.victim uncore cache RRQ Rejects; Victim event=0x27,umask=0x10 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_wbq0_reject.ad_req_vn0 uncore cache WBQ Rejects; AD REQ on VN0 event=0x28,umask=1 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.ad_rsp_vn0 uncore cache WBQ Rejects; AD RSP on VN0 event=0x28,umask=2 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.ak_non_upi uncore cache WBQ Rejects; Non UPI AK Request event=0x28,umask=0x40 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_ncb_vn0 uncore cache WBQ Rejects; BL NCB on VN0 event=0x28,umask=0x10 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_ncs_vn0 uncore cache WBQ Rejects; BL NCS on VN0 event=0x28,umask=0x20 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_rsp_vn0 uncore cache WBQ Rejects; BL RSP on VN0 event=0x28,umask=4 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_wb_vn0 uncore cache WBQ Rejects; BL WB on VN0 event=0x28,umask=8 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.iv_non_upi uncore cache WBQ Rejects; Non UPI IV Request event=0x28,umask=0x80 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.allow_snp uncore cache WBQ Rejects; Allow Snoop event=0x29,umask=0x40 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.any0 uncore cache WBQ Rejects; ANY0 event=0x29,umask=1 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.ha uncore cache WBQ Rejects; HA event=0x29,umask=2 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.llc_or_sf_way uncore cache WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x29,umask=0x20 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.llc_victim uncore cache WBQ Rejects; LLC Victim event=0x29,umask=4 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.pa_match uncore cache WBQ Rejects; PhyAddr Match event=0x29,umask=0x80 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.sf_victim uncore cache WBQ Rejects; SF Victim event=0x29,umask=8 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.victim uncore cache WBQ Rejects; Victim event=0x29,umask=0x10 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxr_busy_starved.ad_bnc uncore cache Transgress Injection Starvation; AD - Bounce event=0xb4,umask=1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.ad_crd uncore cache Transgress Injection Starvation; AD - Credit event=0xb4,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_bnc uncore cache Transgress Injection Starvation; BL - Bounce event=0xb4,umask=4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_crd uncore cache Transgress Injection Starvation; BL - Credit event=0xb4,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_bypass.ad_bnc uncore cache Transgress Ingress Bypass; AD - Bounce event=0xb2,umask=1 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ad_crd uncore cache Transgress Ingress Bypass; AD - Credit event=0xb2,umask=0x10 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ak_bnc uncore cache Transgress Ingress Bypass; AK - Bounce event=0xb2,umask=2 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_bnc uncore cache Transgress Ingress Bypass; BL - Bounce event=0xb2,umask=4 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_crd uncore cache Transgress Ingress Bypass; BL - Credit event=0xb2,umask=0x40 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.iv_bnc uncore cache Transgress Ingress Bypass; IV - Bounce event=0xb2,umask=8 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_crd_starved.ad_bnc uncore cache Transgress Injection Starvation; AD - Bounce event=0xb3,umask=1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ad_crd uncore cache Transgress Injection Starvation; AD - Credit event=0xb3,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ak_bnc uncore cache Transgress Injection Starvation; AK - Bounce event=0xb3,umask=2 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_bnc uncore cache Transgress Injection Starvation; BL - Bounce event=0xb3,umask=4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_crd uncore cache Transgress Injection Starvation; BL - Credit event=0xb3,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ifv uncore cache Transgress Injection Starvation; IFV - Credit event=0xb3,umask=0x80 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.iv_bnc uncore cache Transgress Injection Starvation; IV - Bounce event=0xb3,umask=8 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_inserts.ad_bnc uncore cache Transgress Ingress Allocations; AD - Bounce event=0xb1,umask=1 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ad_crd uncore cache Transgress Ingress Allocations; AD - Credit event=0xb1,umask=0x10 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ak_bnc uncore cache Transgress Ingress Allocations; AK - Bounce event=0xb1,umask=2 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_bnc uncore cache Transgress Ingress Allocations; BL - Bounce event=0xb1,umask=4 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_crd uncore cache Transgress Ingress Allocations; BL - Credit event=0xb1,umask=0x40 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.iv_bnc uncore cache Transgress Ingress Allocations; IV - Bounce event=0xb1,umask=8 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_bnc uncore cache Transgress Ingress Occupancy; AD - Bounce event=0xb0,umask=1 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_crd uncore cache Transgress Ingress Occupancy; AD - Credit event=0xb0,umask=0x10 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ak_bnc uncore cache Transgress Ingress Occupancy; AK - Bounce event=0xb0,umask=2 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_bnc uncore cache Transgress Ingress Occupancy; BL - Bounce event=0xb0,umask=4 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_crd uncore cache Transgress Ingress Occupancy; BL - Credit event=0xb0,umask=0x40 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.iv_bnc uncore cache Transgress Ingress Occupancy; IV - Bounce event=0xb0,umask=8 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_sf_eviction.e_state uncore cache Snoop filter capacity evictions for E-state entries event=0x3d,umask=2 01 Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.m_state uncore cache Snoop filter capacity evictions for M-state entries event=0x3d,umask=1 01 Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.s_state uncore cache Snoop filter capacity evictions for S-state entries event=0x3d,umask=4 01 Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_snoops_sent.all uncore cache Snoops Sent; All event=0x51,umask=1 01 Counts the number of snoops issued by the HA unc_cha_snoops_sent.bcst_local uncore cache Snoops Sent; Broadcast snoop for Local Requests event=0x51,umask=0x10 01 Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.bcst_remote uncore cache Snoops Sent; Broadcast snoops for Remote Requests event=0x51,umask=0x20 01 Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets unc_cha_snoops_sent.direct_local uncore cache Snoops Sent; Directed snoops for Local Requests event=0x51,umask=0x40 01 Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.direct_remote uncore cache Snoops Sent; Directed snoops for Remote Requests event=0x51,umask=0x80 01 Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets unc_cha_snoops_sent.local uncore cache Snoops Sent; Broadcast or directed Snoops sent for Local Requests event=0x51,umask=4 01 Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket unc_cha_snoops_sent.remote uncore cache Snoops Sent; Broadcast or directed Snoops sent for Remote Requests event=0x51,umask=8 01 Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket unc_cha_snoop_resp.rspcnflcts uncore cache RspCnflct* Snoop Responses Received event=0x5c,umask=0x40 01 Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI unc_cha_snoop_resp.rspfwd uncore cache Snoop Responses Received; RspFwd event=0x5c,umask=0x80 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp.rspi uncore cache RspI Snoop Responses Received event=0x5c,umask=1 01 Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data) unc_cha_snoop_resp.rspifwd uncore cache RspIFwd Snoop Responses Received event=0x5c,umask=4 01 Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states unc_cha_snoop_resp.rsps uncore cache Snoop Responses Received : RspS event=0x5c,umask=2 01 Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_cha_snoop_resp.rspsfwd uncore cache RspSFwd Snoop Responses Received event=0x5c,umask=8 01 Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state unc_cha_snoop_resp.rsp_fwd_wb uncore cache Rsp*Fwd*WB Snoop Responses Received event=0x5c,umask=0x20 01 Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory unc_cha_snoop_resp.rsp_wbwb uncore cache Rsp*WB Snoop Responses Received event=0x5c,umask=0x10 01 Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership unc_cha_snoop_resp_local.rspcnflct uncore cache Snoop Responses Received Local; RspCnflct event=0x5d,umask=0x40 01 Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI unc_cha_snoop_resp_local.rspfwd uncore cache Snoop Responses Received Local; RspFwd event=0x5d,umask=0x80 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp_local.rspi uncore cache Snoop Responses Received Local; RspI event=0x5d,umask=1 01 Number of snoop responses received for a Local request; Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_cha_snoop_resp_local.rspifwd uncore cache Snoop Responses Received Local; RspIFwd event=0x5d,umask=4 01 Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE unc_cha_snoop_resp_local.rsps uncore cache Snoop Responses Received Local; RspS event=0x5d,umask=2 01 Number of snoop responses received for a Local request; Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_cha_snoop_resp_local.rspsfwd uncore cache Snoop Responses Received Local; RspSFwd event=0x5d,umask=8 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state unc_cha_snoop_resp_local.rsp_fwd_wb uncore cache Snoop Responses Received Local; Rsp*FWD*WB event=0x5d,umask=0x20 01 Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_cha_snoop_resp_local.rsp_wb uncore cache Snoop Responses Received Local; Rsp*WB event=0x5d,umask=0x10 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 0 event=0xd0,umask=1 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 1 event=0xd0,umask=2 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 2 event=0xd0,umask=4 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 3 event=0xd0,umask=8 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 4 event=0xd0,umask=0x10 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 5 event=0xd0,umask=0x20 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 0 event=0xd2,umask=1 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 1 event=0xd2,umask=2 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 2 event=0xd2,umask=4 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 3 event=0xd2,umask=8 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 4 event=0xd2,umask=0x10 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 5 event=0xd2,umask=0x20 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 0 event=0xd4,umask=1 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 1 event=0xd4,umask=2 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 2 event=0xd4,umask=4 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 3 event=0xd4,umask=8 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 4 event=0xd4,umask=0x10 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 5 event=0xd4,umask=0x20 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 0 event=0xd6,umask=1 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 1 event=0xd6,umask=2 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 2 event=0xd6,umask=4 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 3 event=0xd6,umask=8 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 4 event=0xd6,umask=0x10 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 5 event=0xd6,umask=0x20 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_tor_inserts.all uncore cache TOR Inserts; All event=0x35,umask=0xff 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.all_hit uncore cache TOR Inserts; Hits from Local event=0x35,umask=0x15 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.all_io_ia uncore cache TOR Inserts; All from Local iA and IO event=0x35,umask=0x35 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests unc_cha_tor_inserts.all_miss uncore cache TOR Inserts; Misses from Local event=0x35,umask=0x25 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.evict uncore cache TOR Inserts; SF/LLC Evictions event=0x35,umask=2 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.hit uncore cache TOR Inserts; Hit (Not a Miss) event=0x35,umask=0x10 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true) unc_cha_tor_inserts.ia uncore cache TOR Inserts; All from Local iA event=0x35,umask=0x31 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores unc_cha_tor_inserts.ia_hit uncore cache TOR Inserts; Hits from Local iA event=0x35,umask=0x11 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ia_hit_crd uncore cache TOR Inserts : CRds issued by iA Cores that Hit the LLC event=0x35,umask=0x11,config1=0x4023300000000 01 TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd uncore cache TOR Inserts : DRds issued by iA Cores that Hit the LLC event=0x35,umask=0x11,config1=0x4043300000000 01 TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcrd uncore cache UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD event=0x35,umask=0x11,config1=0x4b23300000000 01 unc_cha_tor_inserts.ia_hit_llcprefdrd uncore cache UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD event=0x35,umask=0x11,config1=0x4b43300000000 01 unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC event=0x35,umask=0x11,config1=0x4b03300000000 01 TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Hit the LLC event=0x35,umask=0x11,config1=0x4003300000000 01 TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss uncore cache TOR Inserts : All requests from iA Cores that Missed the LLC event=0x35,umask=0x21 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd uncore cache TOR Inserts : CRds issued by iA Cores that Missed the LLC event=0x35,umask=0x21,config1=0x4023300000000 01 TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC event=0x35,umask=0x21,config1=0x4043300000000 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefcrd uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD event=0x35,umask=0x21,config1=0x4b23300000000 01 unc_cha_tor_inserts.ia_miss_llcprefdrd uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD event=0x35,umask=0x21,config1=0x4b43300000000 01 unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC event=0x35,umask=0x21,config1=0x4b03300000000 01 TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC event=0x35,umask=0x21,config1=0x4003300000000 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io uncore cache TOR Inserts; All from Local IO event=0x35,umask=0x34 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic unc_cha_tor_inserts.io_hit uncore cache TOR Inserts; Hits from Local IO event=0x35,umask=0x14 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.io_miss uncore cache TOR Inserts; Misses from Local IO event=0x35,umask=0x24 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.io_miss_itom uncore cache TOR Inserts; ItoM misses from Local IO event=0x35,umask=0x24,config1=0x4903300000000 01 Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership unc_cha_tor_inserts.io_miss_rdcur uncore cache TOR Inserts; RdCur misses from Local IO event=0x35,umask=0x24,config1=0x43c3300000000 01 Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state unc_cha_tor_inserts.io_miss_rfo uncore cache TOR Inserts; RFO misses from Local IO event=0x35,umask=0x24,config1=0x4003300000000 01 Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify unc_cha_tor_inserts.ipq uncore cache TOR Inserts; IPQ event=0x35,umask=8 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ipq_hit uncore cache This event is deprecated event=0x35,umask=0x18 11 unc_cha_tor_inserts.ipq_miss uncore cache This event is deprecated event=0x35,umask=0x28 11 unc_cha_tor_inserts.irq uncore cache TOR Inserts; IRQ event=0x35,umask=1 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.loc_all uncore cache This event is deprecated event=0x35,umask=0x37 11 unc_cha_tor_inserts.miss uncore cache TOR Inserts; Miss event=0x35,umask=0x20 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com unc_cha_tor_inserts.prq uncore cache TOR Inserts; PRQ event=0x35,umask=4 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.rem_all uncore cache This event is deprecated event=0x35,umask=0x30 11 unc_cha_tor_inserts.rrq_hit uncore cache This event is deprecated event=0x35,umask=0x50 11 unc_cha_tor_inserts.rrq_miss uncore cache This event is deprecated event=0x35,umask=0x60 11 unc_cha_tor_inserts.wbq_hit uncore cache This event is deprecated event=0x35,umask=0x90 11 unc_cha_tor_inserts.wbq_miss uncore cache This event is deprecated event=0x35,umask=0xa0 11 unc_cha_tor_occupancy.all uncore cache TOR Occupancy : All event=0x36,umask=0xff 01 TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.all_from_loc uncore cache TOR Occupancy; All from Local event=0x36,umask=0x37 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests unc_cha_tor_occupancy.all_hit uncore cache TOR Occupancy; Hits from Local event=0x36,umask=0x17 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.all_miss uncore cache TOR Occupancy; Misses from Local event=0x36,umask=0x27 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.evict uncore cache TOR Occupancy; SF/LLC Evictions event=0x36,umask=2 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_occupancy.hit uncore cache TOR Occupancy; Hit (Not a Miss) event=0x36,umask=0x10 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true) unc_cha_tor_occupancy.ia uncore cache TOR Occupancy; All from Local iA event=0x36,umask=0x31 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally initiated requests from iA Cores unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy; Hits from Local iA event=0x36,umask=0x11 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Hit the LLC event=0x36,umask=0x11,config1=0x4023300000000 01 TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Hit the LLC event=0x36,umask=0x11,config1=0x4043300000000 01 TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefcrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD event=0x36,umask=0x11,config1=0x4b23300000000 01 unc_cha_tor_occupancy.ia_hit_llcprefdrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD event=0x36,umask=0x11,config1=0x4b43300000000 01 unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC event=0x36,umask=0x11,config1=0x4b03300000000 01 TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Hit the LLC event=0x36,umask=0x11,config1=0x4003300000000 01 TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy; Misses from Local iA event=0x36,umask=0x21 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Missed the LLC event=0x36,umask=0x21,config1=0x4023300000000 01 TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC event=0x36,umask=0x21,config1=0x4043300000000 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefcrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD event=0x36,umask=0x21,config1=0x4b23300000000 01 unc_cha_tor_occupancy.ia_miss_llcprefdrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD event=0x36,umask=0x21,config1=0x4b43300000000 01 unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC event=0x36,umask=0x21,config1=0x4b03300000000 01 TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC event=0x36,umask=0x21,config1=0x4003300000000 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io uncore cache TOR Occupancy; All from Local IO event=0x36,umask=0x34 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally generated IO traffic unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy; Hits from Local IO event=0x36,umask=0x14 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy; Misses from Local IO event=0x36,umask=0x24 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy; ITOM Misses from Local IO event=0x36,umask=0x24,config1=0x4903300000000 01 For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership unc_cha_tor_occupancy.io_miss_rdcur uncore cache TOR Occupancy; RDCUR misses from Local IO event=0x36,umask=0x24,config1=0x43c3300000000 01 For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy; RFO misses from Local IO event=0x36,umask=0x24,config1=0x4003300000000 01 For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify unc_cha_tor_occupancy.ipq uncore cache TOR Occupancy; IPQ event=0x36,umask=8 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.ipq_hit uncore cache This event is deprecated event=0x36,umask=0x18 11 unc_cha_tor_occupancy.ipq_miss uncore cache This event is deprecated event=0x36,umask=0x28 11 unc_cha_tor_occupancy.irq uncore cache TOR Occupancy; IRQ event=0x36,umask=1 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.loc_all uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC event=0x36,umask=0x37 11 unc_cha_tor_occupancy.miss uncore cache TOR Occupancy; Miss event=0x36,umask=0x20 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com unc_cha_tor_occupancy.prq uncore cache TOR Occupancy; PRQ event=0x36,umask=4 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_txr_horz_ads_used.ad_bnc uncore cache CMS Horizontal ADS Used; AD - Bounce event=0x9d,umask=1 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.ad_crd uncore cache CMS Horizontal ADS Used; AD - Credit event=0x9d,umask=0x10 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.ak_bnc uncore cache CMS Horizontal ADS Used; AK - Bounce event=0x9d,umask=2 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_bnc uncore cache CMS Horizontal ADS Used; BL - Bounce event=0x9d,umask=4 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_crd uncore cache CMS Horizontal ADS Used; BL - Credit event=0x9d,umask=0x40 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_bnc uncore cache CMS Horizontal Bypass Used; AD - Bounce event=0x9f,umask=1 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_crd uncore cache CMS Horizontal Bypass Used; AD - Credit event=0x9f,umask=0x10 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ak_bnc uncore cache CMS Horizontal Bypass Used; AK - Bounce event=0x9f,umask=2 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_bnc uncore cache CMS Horizontal Bypass Used; BL - Bounce event=0x9f,umask=4 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_crd uncore cache CMS Horizontal Bypass Used; BL - Credit event=0x9f,umask=0x40 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.iv_bnc uncore cache CMS Horizontal Bypass Used; IV - Bounce event=0x9f,umask=8 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_cycles_full.ad_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; AD - Bounce event=0x96,umask=1 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Full; AD - Credit event=0x96,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ak_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; AK - Bounce event=0x96,umask=2 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; BL - Bounce event=0x96,umask=4 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Full; BL - Credit event=0x96,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.iv_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; IV - Bounce event=0x96,umask=8 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce event=0x97,umask=1 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit event=0x97,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ak_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce event=0x97,umask=2 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce event=0x97,umask=4 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit event=0x97,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.iv_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce event=0x97,umask=8 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_bnc uncore cache CMS Horizontal Egress Inserts; AD - Bounce event=0x95,umask=1 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_crd uncore cache CMS Horizontal Egress Inserts; AD - Credit event=0x95,umask=0x10 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ak_bnc uncore cache CMS Horizontal Egress Inserts; AK - Bounce event=0x95,umask=2 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_bnc uncore cache CMS Horizontal Egress Inserts; BL - Bounce event=0x95,umask=4 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_crd uncore cache CMS Horizontal Egress Inserts; BL - Credit event=0x95,umask=0x40 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.iv_bnc uncore cache CMS Horizontal Egress Inserts; IV - Bounce event=0x95,umask=8 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_nack.ad_bnc uncore cache CMS Horizontal Egress NACKs; AD - Bounce event=0x99,umask=1 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ad_crd uncore cache CMS Horizontal Egress NACKs; AD - Credit event=0x99,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ak_bnc uncore cache CMS Horizontal Egress NACKs; AK - Bounce event=0x99,umask=2 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_bnc uncore cache CMS Horizontal Egress NACKs; BL - Bounce event=0x99,umask=4 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_crd uncore cache CMS Horizontal Egress NACKs; BL - Credit event=0x99,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.iv_bnc uncore cache CMS Horizontal Egress NACKs; IV - Bounce event=0x99,umask=8 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_occupancy.ad_bnc uncore cache CMS Horizontal Egress Occupancy; AD - Bounce event=0x94,umask=1 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ad_crd uncore cache CMS Horizontal Egress Occupancy; AD - Credit event=0x94,umask=0x10 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ak_bnc uncore cache CMS Horizontal Egress Occupancy; AK - Bounce event=0x94,umask=2 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_bnc uncore cache CMS Horizontal Egress Occupancy; BL - Bounce event=0x94,umask=4 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_crd uncore cache CMS Horizontal Egress Occupancy; BL - Credit event=0x94,umask=0x40 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.iv_bnc uncore cache CMS Horizontal Egress Occupancy; IV - Bounce event=0x94,umask=8 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_starved.ad_bnc uncore cache CMS Horizontal Egress Injection Starvation; AD - Bounce event=0x9b,umask=1 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.ak_bnc uncore cache CMS Horizontal Egress Injection Starvation; AK - Bounce event=0x9b,umask=2 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.bl_bnc uncore cache CMS Horizontal Egress Injection Starvation; BL - Bounce event=0x9b,umask=4 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.iv_bnc uncore cache CMS Horizontal Egress Injection Starvation; IV - Bounce event=0x9b,umask=8 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_vert_ads_used.ad_ag0 uncore cache CMS Vertical ADS Used; AD - Agent 0 event=0x9c,umask=1 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ad_ag1 uncore cache CMS Vertical ADS Used; AD - Agent 1 event=0x9c,umask=0x10 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ak_ag0 uncore cache CMS Vertical ADS Used; AK - Agent 0 event=0x9c,umask=2 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ak_ag1 uncore cache CMS Vertical ADS Used; AK - Agent 1 event=0x9c,umask=0x20 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag0 uncore cache CMS Vertical ADS Used; BL - Agent 0 event=0x9c,umask=4 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag1 uncore cache CMS Vertical ADS Used; BL - Agent 1 event=0x9c,umask=0x40 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag0 uncore cache CMS Vertical ADS Used; AD - Agent 0 event=0x9e,umask=1 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag1 uncore cache CMS Vertical ADS Used; AD - Agent 1 event=0x9e,umask=0x10 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag0 uncore cache CMS Vertical ADS Used; AK - Agent 0 event=0x9e,umask=2 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag1 uncore cache CMS Vertical ADS Used; AK - Agent 1 event=0x9e,umask=0x20 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag0 uncore cache CMS Vertical ADS Used; BL - Agent 0 event=0x9e,umask=4 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag1 uncore cache CMS Vertical ADS Used; BL - Agent 1 event=0x9e,umask=0x40 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.iv uncore cache CMS Vertical ADS Used; IV event=0x9e,umask=8 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_cycles_full.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0 event=0x92,umask=1 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_full.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1 event=0x92,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_cycles_full.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0 event=0x92,umask=2 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_full.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1 event=0x92,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_full.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0 event=0x92,umask=4 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_full.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1 event=0x92,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_full.iv uncore cache Cycles CMS Vertical Egress Queue Is Full; IV event=0x92,umask=8 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_cycles_ne.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0 event=0x93,umask=1 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_ne.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1 event=0x93,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_cycles_ne.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0 event=0x93,umask=2 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_ne.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1 event=0x93,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_ne.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0 event=0x93,umask=4 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_ne.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1 event=0x93,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_ne.iv uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; IV event=0x93,umask=8 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_inserts.ad_ag0 uncore cache CMS Vert Egress Allocations; AD - Agent 0 event=0x91,umask=1 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_inserts.ad_ag1 uncore cache CMS Vert Egress Allocations; AD - Agent 1 event=0x91,umask=0x10 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_inserts.ak_ag0 uncore cache CMS Vert Egress Allocations; AK - Agent 0 event=0x91,umask=2 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_inserts.ak_ag1 uncore cache CMS Vert Egress Allocations; AK - Agent 1 event=0x91,umask=0x20 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_inserts.bl_ag0 uncore cache CMS Vert Egress Allocations; BL - Agent 0 event=0x91,umask=4 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_inserts.bl_ag1 uncore cache CMS Vert Egress Allocations; BL - Agent 1 event=0x91,umask=0x40 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_inserts.iv uncore cache CMS Vert Egress Allocations; IV event=0x91,umask=8 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_nack.ad_ag0 uncore cache CMS Vertical Egress NACKs; AD - Agent 0 event=0x98,umask=1 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.ad_ag1 uncore cache CMS Vertical Egress NACKs; AD - Agent 1 event=0x98,umask=0x10 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.ak_ag0 uncore cache CMS Vertical Egress NACKs; AK - Agent 0 event=0x98,umask=2 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.ak_ag1 uncore cache CMS Vertical Egress NACKs; AK - Agent 1 event=0x98,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.bl_ag0 uncore cache CMS Vertical Egress NACKs; BL - Agent 0 event=0x98,umask=4 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.bl_ag1 uncore cache CMS Vertical Egress NACKs; BL - Agent 1 event=0x98,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.iv uncore cache CMS Vertical Egress NACKs; IV event=0x98,umask=8 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_occupancy.ad_ag0 uncore cache CMS Vert Egress Occupancy; AD - Agent 0 event=0x90,umask=1 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_occupancy.ad_ag1 uncore cache CMS Vert Egress Occupancy; AD - Agent 1 event=0x90,umask=0x10 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_occupancy.ak_ag0 uncore cache CMS Vert Egress Occupancy; AK - Agent 0 event=0x90,umask=2 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_occupancy.ak_ag1 uncore cache CMS Vert Egress Occupancy; AK - Agent 1 event=0x90,umask=0x20 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_occupancy.bl_ag0 uncore cache CMS Vert Egress Occupancy; BL - Agent 0 event=0x90,umask=4 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_occupancy.bl_ag1 uncore cache CMS Vert Egress Occupancy; BL - Agent 1 event=0x90,umask=0x40 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_occupancy.iv uncore cache CMS Vert Egress Occupancy; IV event=0x90,umask=8 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_starved.ad_ag0 uncore cache CMS Vertical Egress Injection Starvation; AD - Agent 0 event=0x9a,umask=1 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.ad_ag1 uncore cache CMS Vertical Egress Injection Starvation; AD - Agent 1 event=0x9a,umask=0x10 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.ak_ag0 uncore cache CMS Vertical Egress Injection Starvation; AK - Agent 0 event=0x9a,umask=2 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.ak_ag1 uncore cache CMS Vertical Egress Injection Starvation; AK - Agent 1 event=0x9a,umask=0x20 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.bl_ag0 uncore cache CMS Vertical Egress Injection Starvation; BL - Agent 0 event=0x9a,umask=4 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.bl_ag1 uncore cache CMS Vertical Egress Injection Starvation; BL - Agent 1 event=0x9a,umask=0x40 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.iv uncore cache CMS Vertical Egress Injection Starvation; IV event=0x9a,umask=8 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_upi_credits_acquired.ad_req uncore cache UPI Ingress Credit Allocations; AD REQ Credits event=0x38,umask=4 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.ad_rsp uncore cache UPI Ingress Credit Allocations; AD RSP VN0 Credits event=0x38,umask=8 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_ncb uncore cache UPI Ingress Credit Allocations; BL NCB Credits event=0x38,umask=0x40 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_ncs uncore cache UPI Ingress Credit Allocations; BL NCS Credits event=0x38,umask=0x80 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_rsp uncore cache UPI Ingress Credit Allocations; BL RSP Credits event=0x38,umask=0x10 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_wb uncore cache UPI Ingress Credit Allocations; BL DRS Credits event=0x38,umask=0x20 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.vn0 uncore cache UPI Ingress Credit Allocations; VN0 Credits event=0x38,umask=2 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.vna uncore cache UPI Ingress Credit Allocations; VNA Credits event=0x38,umask=1 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_ad_req uncore cache UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits event=0x3b,umask=4 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_ad_rsp uncore cache UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits event=0x3b,umask=8 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_ncb uncore cache UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits event=0x3b,umask=0x40 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_ncs uncore cache UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits event=0x3b,umask=0x80 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_rsp uncore cache UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits event=0x3b,umask=0x10 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_wb uncore cache UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits event=0x3b,umask=0x20 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vna_ad uncore cache UPI Ingress Credits In Use Cycles; AD VNA Credits event=0x3b,umask=1 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vna_bl uncore cache UPI Ingress Credits In Use Cycles; BL VNA Credits event=0x3b,umask=2 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_vert_ring_ad_in_use.dn_even uncore cache Vertical AD Ring In Use; Down and Even event=0xa6,umask=4 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.dn_odd uncore cache Vertical AD Ring In Use; Down and Odd event=0xa6,umask=8 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_even uncore cache Vertical AD Ring In Use; Up and Even event=0xa6,umask=1 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_odd uncore cache Vertical AD Ring In Use; Up and Odd event=0xa6,umask=2 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_even uncore cache Vertical AK Ring In Use; Down and Even event=0xa8,umask=4 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_odd uncore cache Vertical AK Ring In Use; Down and Odd event=0xa8,umask=8 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_even uncore cache Vertical AK Ring In Use; Up and Even event=0xa8,umask=1 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_odd uncore cache Vertical AK Ring In Use; Up and Odd event=0xa8,umask=2 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_even uncore cache Vertical BL Ring in Use; Down and Even event=0xaa,umask=4 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_odd uncore cache Vertical BL Ring in Use; Down and Odd event=0xaa,umask=8 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_even uncore cache Vertical BL Ring in Use; Up and Even event=0xaa,umask=1 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_odd uncore cache Vertical BL Ring in Use; Up and Odd event=0xaa,umask=2 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_iv_in_use.dn uncore cache Vertical IV Ring in Use; Down event=0xac,umask=4 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_vert_ring_iv_in_use.up uncore cache Vertical IV Ring in Use; Up event=0xac,umask=1 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_wb_push_mtoi.llc uncore cache WbPushMtoI; Pushed to LLC event=0x56,umask=1 01 Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC unc_cha_wb_push_mtoi.mem uncore cache WbPushMtoI; Pushed to Memory event=0x56,umask=2 01 Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM) unc_cha_write_no_credits.edc0_smi2 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2 event=0x5a,umask=4 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only unc_cha_write_no_credits.edc1_smi3 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3 event=0x5a,umask=8 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only unc_cha_write_no_credits.edc2_smi4 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4 event=0x5a,umask=0x10 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only unc_cha_write_no_credits.edc3_smi5 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5 event=0x5a,umask=0x20 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only unc_cha_write_no_credits.mc0_smi0 uncore cache CHA iMC CHNx WRITE Credits Empty; MC0_SMI0 event=0x5a,umask=1 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only unc_cha_write_no_credits.mc1_smi1 uncore cache CHA iMC CHNx WRITE Credits Empty; MC1_SMI1 event=0x5a,umask=2 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only unc_cha_xsnp_resp.any_rspi_fwdfe uncore cache Core Cross Snoop Responses; Any RspIFwdFE event=0x32,umask=0xe4 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E unc_cha_xsnp_resp.any_rspi_fwdm uncore cache Core Cross Snoop Responses event=0x32,umask=0xf0 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M unc_cha_xsnp_resp.any_rsps_fwdfe uncore cache Core Cross Snoop Responses; Any RspSFwdFE event=0x32,umask=0xe2 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E unc_cha_xsnp_resp.any_rsps_fwdm uncore cache Core Cross Snoop Responses; Any RspSFwdM event=0x32,umask=0xe8 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M unc_cha_xsnp_resp.any_rsp_hitfse uncore cache Core Cross Snoop Responses; Any RspHitFSE event=0x32,umask=0xe1 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E unc_cha_xsnp_resp.core_rspi_fwdfe uncore cache Core Cross Snoop Responses; Core RspIFwdFE event=0x32,umask=0x44 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E unc_cha_xsnp_resp.core_rspi_fwdm uncore cache Core Cross Snoop Responses; Core RspIFwdM event=0x32,umask=0x50 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M unc_cha_xsnp_resp.core_rsps_fwdfe uncore cache Core Cross Snoop Responses; Core RspSFwdFE event=0x32,umask=0x42 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E unc_cha_xsnp_resp.core_rsps_fwdm uncore cache Core Cross Snoop Responses; Core RspSFwdM event=0x32,umask=0x48 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M unc_cha_xsnp_resp.core_rsp_hitfse uncore cache Core Cross Snoop Responses; Core RspHitFSE event=0x32,umask=0x41 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E unc_cha_xsnp_resp.evict_rspi_fwdfe uncore cache Core Cross Snoop Responses; Evict RspIFwdFE event=0x32,umask=0x84 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E unc_cha_xsnp_resp.evict_rspi_fwdm uncore cache Core Cross Snoop Responses; Evict RspIFwdM event=0x32,umask=0x90 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M unc_cha_xsnp_resp.evict_rsps_fwdfe uncore cache Core Cross Snoop Responses; Evict RspSFwdFE event=0x32,umask=0x82 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E unc_cha_xsnp_resp.evict_rsps_fwdm uncore cache Core Cross Snoop Responses; Evict RspSFwdM event=0x32,umask=0x88 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M unc_cha_xsnp_resp.evict_rsp_hitfse uncore cache Core Cross Snoop Responses; Evict RspHitFSE event=0x32,umask=0x81 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E unc_cha_xsnp_resp.ext_rspi_fwdfe uncore cache Core Cross Snoop Responses; External RspIFwdFE event=0x32,umask=0x24 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E unc_cha_xsnp_resp.ext_rspi_fwdm uncore cache Core Cross Snoop Responses; External RspIFwdM event=0x32,umask=0x30 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M unc_cha_xsnp_resp.ext_rsps_fwdfe uncore cache Core Cross Snoop Responses; External RspSFwdFE event=0x32,umask=0x22 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E unc_cha_xsnp_resp.ext_rsps_fwdm uncore cache Core Cross Snoop Responses; External RspSFwdM event=0x32,umask=0x28 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M unc_cha_xsnp_resp.ext_rsp_hitfse uncore cache Core Cross Snoop Responses; External RspHitFSE event=0x32,umask=0x21 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E unc_c_clockticks uncore cache This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS event=0 11 unc_c_fast_asserted uncore cache This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ event=0xa5,umask=2 11 unc_c_llc_lookup.any uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY event=0x34,umask=0x11 11 unc_c_llc_lookup.data_read uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ event=0x34,umask=3 11 unc_c_llc_lookup.local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL event=0x34,umask=0x31 11 unc_c_llc_lookup.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE event=0x34,umask=0x91 11 unc_c_llc_lookup.remote_snoop uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP event=0x34,umask=9 11 unc_c_llc_lookup.write uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE event=0x34,umask=5 11 unc_c_llc_victims.e_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E event=0x37,umask=2 11 unc_c_llc_victims.f_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F event=0x37,umask=8 11 unc_c_llc_victims.local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL event=0x37,umask=0x2f 11 unc_c_llc_victims.m_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M event=0x37,umask=1 11 unc_c_llc_victims.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL event=0x37,umask=0x80 11 unc_c_llc_victims.s_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S event=0x37,umask=4 11 unc_c_ring_src_thrtl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL event=0xa4 11 unc_c_tor_inserts.evict uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT event=0x35,umask=2 11 unc_c_tor_inserts.hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT event=0x35,umask=0x10 11 unc_c_tor_inserts.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ event=0x35,umask=8 11 unc_c_tor_inserts.ipq_hit uncore cache This event is deprecated event=0x35,umask=0x18 11 unc_c_tor_inserts.ipq_miss uncore cache This event is deprecated event=0x35,umask=0x28 11 unc_c_tor_inserts.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA event=0x35,umask=0x31 11 unc_c_tor_inserts.irq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT event=0x35,umask=0x11 11 unc_c_tor_inserts.irq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS event=0x35,umask=0x21 11 unc_c_tor_inserts.loc_all uncore cache This event is deprecated event=0x35,umask=0x37 11 unc_c_tor_inserts.loc_ia uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA event=0x35,umask=0x31 11 unc_c_tor_inserts.loc_io uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO event=0x35,umask=0x34 11 unc_c_tor_inserts.miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS event=0x35,umask=0x20 11 unc_c_tor_inserts.prq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ event=0x35,umask=4 11 unc_c_tor_inserts.prq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT event=0x35,umask=0x14 11 unc_c_tor_inserts.prq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS event=0x35,umask=0x24 11 unc_c_tor_inserts.rem_all uncore cache This event is deprecated event=0x35,umask=0x30 11 unc_c_tor_inserts.rrq_hit uncore cache This event is deprecated event=0x35,umask=0x50 11 unc_c_tor_inserts.rrq_miss uncore cache This event is deprecated event=0x35,umask=0x60 11 unc_c_tor_inserts.wbq_hit uncore cache This event is deprecated event=0x35,umask=0x90 11 unc_c_tor_inserts.wbq_miss uncore cache This event is deprecated event=0x35,umask=0xa0 11 unc_c_tor_occupancy.evict uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT event=0x36,umask=2 11 unc_c_tor_occupancy.hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT event=0x36,umask=0x10 11 unc_c_tor_occupancy.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ event=0x36,umask=8 11 unc_c_tor_occupancy.ipq_hit uncore cache This event is deprecated event=0x36,umask=0x18 11 unc_c_tor_occupancy.ipq_miss uncore cache This event is deprecated event=0x36,umask=0x28 11 unc_c_tor_occupancy.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA event=0x36,umask=0x31 11 unc_c_tor_occupancy.irq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT event=0x36,umask=0x11 11 unc_c_tor_occupancy.irq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS event=0x36,umask=0x21 11 unc_c_tor_occupancy.loc_all uncore cache This event is deprecated event=0x36,umask=0x37 11 unc_c_tor_occupancy.loc_ia uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA event=0x36,umask=0x31 11 unc_c_tor_occupancy.loc_io uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO event=0x36,umask=0x34 11 unc_c_tor_occupancy.miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS event=0x36,umask=0x20 11 unc_c_tor_occupancy.prq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ event=0x36,umask=4 11 unc_c_tor_occupancy.prq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT event=0x36,umask=0x14 11 unc_c_tor_occupancy.prq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS event=0x36,umask=0x24 11 unc_h_ag0_ad_crd_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0 event=0x80,umask=1 11 unc_h_ag0_ad_crd_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1 event=0x80,umask=2 11 unc_h_ag0_ad_crd_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2 event=0x80,umask=4 11 unc_h_ag0_ad_crd_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3 event=0x80,umask=8 11 unc_h_ag0_ad_crd_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4 event=0x80,umask=0x10 11 unc_h_ag0_ad_crd_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5 event=0x80,umask=0x20 11 unc_h_ag0_ad_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0 event=0x82,umask=1 11 unc_h_ag0_ad_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1 event=0x82,umask=2 11 unc_h_ag0_ad_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2 event=0x82,umask=4 11 unc_h_ag0_ad_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3 event=0x82,umask=8 11 unc_h_ag0_ad_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4 event=0x82,umask=0x10 11 unc_h_ag0_ad_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5 event=0x82,umask=0x20 11 unc_h_ag0_bl_crd_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0 event=0x88,umask=1 11 unc_h_ag0_bl_crd_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1 event=0x88,umask=2 11 unc_h_ag0_bl_crd_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2 event=0x88,umask=4 11 unc_h_ag0_bl_crd_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3 event=0x88,umask=8 11 unc_h_ag0_bl_crd_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4 event=0x88,umask=0x10 11 unc_h_ag0_bl_crd_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5 event=0x88,umask=0x20 11 unc_h_ag0_bl_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0 event=0x8a,umask=1 11 unc_h_ag0_bl_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1 event=0x8a,umask=2 11 unc_h_ag0_bl_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2 event=0x8a,umask=4 11 unc_h_ag0_bl_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3 event=0x8a,umask=8 11 unc_h_ag0_bl_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4 event=0x8a,umask=0x10 11 unc_h_ag0_bl_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5 event=0x8a,umask=0x20 11 unc_h_ag1_ad_crd_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0 event=0x84,umask=1 11 unc_h_ag1_ad_crd_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1 event=0x84,umask=2 11 unc_h_ag1_ad_crd_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2 event=0x84,umask=4 11 unc_h_ag1_ad_crd_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3 event=0x84,umask=8 11 unc_h_ag1_ad_crd_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4 event=0x84,umask=0x10 11 unc_h_ag1_ad_crd_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5 event=0x84,umask=0x20 11 unc_h_ag1_ad_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0 event=0x86,umask=1 11 unc_h_ag1_ad_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1 event=0x86,umask=2 11 unc_h_ag1_ad_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2 event=0x86,umask=4 11 unc_h_ag1_ad_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3 event=0x86,umask=8 11 unc_h_ag1_ad_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4 event=0x86,umask=0x10 11 unc_h_ag1_ad_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5 event=0x86,umask=0x20 11 unc_h_ag1_bl_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0 event=0x8e,umask=1 11 unc_h_ag1_bl_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1 event=0x8e,umask=2 11 unc_h_ag1_bl_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2 event=0x8e,umask=4 11 unc_h_ag1_bl_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3 event=0x8e,umask=8 11 unc_h_ag1_bl_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4 event=0x8e,umask=0x10 11 unc_h_ag1_bl_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5 event=0x8e,umask=0x20 11 unc_h_ag1_bl_credits_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0 event=0x8c,umask=1 11 unc_h_ag1_bl_credits_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1 event=0x8c,umask=2 11 unc_h_ag1_bl_credits_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2 event=0x8c,umask=4 11 unc_h_ag1_bl_credits_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3 event=0x8c,umask=8 11 unc_h_ag1_bl_credits_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4 event=0x8c,umask=0x10 11 unc_h_ag1_bl_credits_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5 event=0x8c,umask=0x20 11 unc_h_bypass_cha_imc.intermediate uncore cache This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE event=0x57,umask=2 11 unc_h_bypass_cha_imc.not_taken uncore cache This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN event=0x57,umask=4 11 unc_h_bypass_cha_imc.taken uncore cache This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN event=0x57,umask=1 11 unc_h_clock uncore cache This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS event=0xc0 11 unc_h_core_pma.c1_state uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE event=0x17,umask=1 11 unc_h_core_pma.c1_transition uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION event=0x17,umask=2 11 unc_h_core_pma.c6_state uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE event=0x17,umask=4 11 unc_h_core_pma.c6_transition uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION event=0x17,umask=8 11 unc_h_core_pma.gv uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV event=0x17,umask=0x10 11 unc_h_core_snp.any_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE event=0x33,umask=0xe2 11 unc_h_core_snp.any_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE event=0x33,umask=0xe1 11 unc_h_core_snp.any_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE event=0x33,umask=0xe4 11 unc_h_core_snp.core_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE event=0x33,umask=0x42 11 unc_h_core_snp.core_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE event=0x33,umask=0x41 11 unc_h_core_snp.core_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE event=0x33,umask=0x44 11 unc_h_core_snp.evict_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE event=0x33,umask=0x82 11 unc_h_core_snp.evict_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE event=0x33,umask=0x81 11 unc_h_core_snp.evict_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE event=0x33,umask=0x84 11 unc_h_core_snp.ext_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE event=0x33,umask=0x22 11 unc_h_core_snp.ext_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE event=0x33,umask=0x21 11 unc_h_core_snp.ext_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE event=0x33,umask=0x24 11 unc_h_counter0_occupancy uncore cache This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY event=0x1f 11 unc_h_dir_lookup.no_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP event=0x53,umask=2 11 unc_h_dir_lookup.snp uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP event=0x53,umask=1 11 unc_h_dir_update.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA event=0x54,umask=1 11 unc_h_dir_update.tor uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR event=0x54,umask=2 11 unc_h_egress_ordering.iv_snoopgo_dn uncore cache This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN event=0xae,umask=4 11 unc_h_egress_ordering.iv_snoopgo_up uncore cache This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP event=0xae,umask=1 11 unc_h_hitme_hit.ex_rds uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS event=0x5f,umask=1 11 unc_h_hitme_hit.shared_ownreq uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ event=0x5f,umask=4 11 unc_h_hitme_hit.wbmtoe uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE event=0x5f,umask=8 11 unc_h_hitme_hit.wbmtoi_or_s uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S event=0x5f,umask=0x10 11 unc_h_hitme_lookup.read uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ event=0x5e,umask=1 11 unc_h_hitme_lookup.write uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE event=0x5e,umask=2 11 unc_h_hitme_miss.notshared_rdinvown uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN event=0x60,umask=0x40 11 unc_h_hitme_miss.read_or_inv uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV event=0x60,umask=0x80 11 unc_h_hitme_miss.shared_rdinvown uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN event=0x60,umask=0x20 11 unc_h_hitme_update.deallocate uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE event=0x61,umask=0x10 11 unc_h_hitme_update.deallocate_rspfwdi_loc uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC event=0x61,umask=1 11 unc_h_hitme_update.rdinvown uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN event=0x61,umask=8 11 unc_h_hitme_update.rspfwdi_rem uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM event=0x61,umask=2 11 unc_h_hitme_update.shared uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED event=0x61,umask=4 11 unc_h_horz_ring_ad_in_use.left_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN event=0xa7,umask=1 11 unc_h_horz_ring_ad_in_use.left_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD event=0xa7,umask=2 11 unc_h_horz_ring_ad_in_use.right_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN event=0xa7,umask=4 11 unc_h_horz_ring_ad_in_use.right_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD event=0xa7,umask=8 11 unc_h_horz_ring_ak_in_use.left_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN event=0xa9,umask=1 11 unc_h_horz_ring_ak_in_use.left_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD event=0xa9,umask=2 11 unc_h_horz_ring_ak_in_use.right_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN event=0xa9,umask=4 11 unc_h_horz_ring_ak_in_use.right_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD event=0xa9,umask=8 11 unc_h_horz_ring_bl_in_use.left_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN event=0xab,umask=1 11 unc_h_horz_ring_bl_in_use.left_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD event=0xab,umask=2 11 unc_h_horz_ring_bl_in_use.right_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN event=0xab,umask=4 11 unc_h_horz_ring_bl_in_use.right_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD event=0xab,umask=8 11 unc_h_horz_ring_iv_in_use.left uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT event=0xad,umask=1 11 unc_h_horz_ring_iv_in_use.right uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT event=0xad,umask=4 11 unc_h_imc_reads_count.normal uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL event=0x59,umask=1 11 unc_h_imc_reads_count.priority uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY event=0x59,umask=2 11 unc_h_imc_writes_count.full uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL event=0x5b,umask=1 11 unc_h_imc_writes_count.full_mig uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG event=0x5b,umask=0x10 11 unc_h_imc_writes_count.full_priority uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY event=0x5b,umask=4 11 unc_h_imc_writes_count.partial uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL event=0x5b,umask=2 11 unc_h_imc_writes_count.partial_mig uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG event=0x5b,umask=0x20 11 unc_h_imc_writes_count.partial_priority uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY event=0x5b,umask=8 11 unc_h_iodc_alloc.invitom uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM event=0x62,umask=1 11 unc_h_iodc_alloc.iodcfull uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL event=0x62,umask=2 11 unc_h_iodc_alloc.osbgated uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED event=0x62,umask=4 11 unc_h_iodc_dealloc.all uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL event=0x63,umask=0x10 11 unc_h_iodc_dealloc.snpout uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT event=0x63,umask=8 11 unc_h_iodc_dealloc.wbmtoe uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE event=0x63,umask=1 11 unc_h_iodc_dealloc.wbmtoi uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI event=0x63,umask=2 11 unc_h_iodc_dealloc.wbpushmtoi uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI event=0x63,umask=4 11 unc_h_misc.cv0_pref_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS event=0x39,umask=0x20 11 unc_h_misc.cv0_pref_vic uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC event=0x39,umask=0x10 11 unc_h_misc.rfo_hit_s uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S event=0x39,umask=8 11 unc_h_misc.rspi_was_fse uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE event=0x39,umask=1 11 unc_h_misc.wc_aliasing uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING event=0x39,umask=2 11 unc_h_osb uncore cache This event is deprecated. Refer to new event UNC_CHA_OSB event=0x55 11 unc_h_read_no_credits.edc0_smi2 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2 event=0x58,umask=4 11 unc_h_read_no_credits.edc1_smi3 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3 event=0x58,umask=8 11 unc_h_read_no_credits.edc2_smi4 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4 event=0x58,umask=0x10 11 unc_h_read_no_credits.edc3_smi5 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5 event=0x58,umask=0x20 11 unc_h_read_no_credits.mc0_smi0 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0 event=0x58,umask=1 11 unc_h_read_no_credits.mc1_smi1 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1 event=0x58,umask=2 11 unc_h_requests.invitoe_local uncore cache This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL event=0x50,umask=0x10 11 unc_h_requests.invitoe_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE event=0x50,umask=0x20 11 unc_h_requests.reads uncore cache read requests from home agent event=0x50,umask=3 11 unc_h_requests.reads_local uncore cache read requests from local home agent event=0x50,umask=1 11 unc_h_requests.reads_remote uncore cache read requests from remote home agent event=0x50,umask=2 11 unc_h_requests.writes uncore cache write requests from home agent event=0x50,umask=0xc 11 unc_h_requests.writes_local uncore cache write requests from local home agent event=0x50,umask=4 11 unc_h_requests.writes_remote uncore cache write requests from remote home agent event=0x50,umask=8 11 unc_h_ring_bounces_horz.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD event=0xa1,umask=1 11 unc_h_ring_bounces_horz.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK event=0xa1,umask=2 11 unc_h_ring_bounces_horz.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL event=0xa1,umask=4 11 unc_h_ring_bounces_horz.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV event=0xa1,umask=8 11 unc_h_ring_bounces_vert.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD event=0xa0,umask=1 11 unc_h_ring_bounces_vert.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK event=0xa0,umask=2 11 unc_h_ring_bounces_vert.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL event=0xa0,umask=4 11 unc_h_ring_bounces_vert.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV event=0xa0,umask=8 11 unc_h_ring_sink_starved_horz.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD event=0xa3,umask=1 11 unc_h_ring_sink_starved_horz.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK event=0xa3,umask=2 11 unc_h_ring_sink_starved_horz.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1 event=0xa3,umask=0x20 11 unc_h_ring_sink_starved_horz.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL event=0xa3,umask=4 11 unc_h_ring_sink_starved_horz.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV event=0xa3,umask=8 11 unc_h_ring_sink_starved_vert.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD event=0xa2,umask=1 11 unc_h_ring_sink_starved_vert.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK event=0xa2,umask=2 11 unc_h_ring_sink_starved_vert.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL event=0xa2,umask=4 11 unc_h_ring_sink_starved_vert.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV event=0xa2,umask=8 11 unc_h_rxc_inserts.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ event=0x13,umask=4 11 unc_h_rxc_inserts.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ event=0x13,umask=1 11 unc_h_rxc_inserts.irq_rej uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ event=0x13,umask=2 11 unc_h_rxc_inserts.prq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ event=0x13,umask=0x10 11 unc_h_rxc_inserts.prq_rej uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ event=0x13,umask=0x20 11 unc_h_rxc_inserts.rrq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ event=0x13,umask=0x40 11 unc_h_rxc_inserts.wbq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ event=0x13,umask=0x80 11 unc_h_rxc_ipq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0 event=0x22,umask=1 11 unc_h_rxc_ipq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0 event=0x22,umask=2 11 unc_h_rxc_ipq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0 event=0x22,umask=0x10 11 unc_h_rxc_ipq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0 event=0x22,umask=0x20 11 unc_h_rxc_ipq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0 event=0x22,umask=4 11 unc_h_rxc_ipq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0 event=0x22,umask=8 11 unc_h_rxc_ipq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP event=0x23,umask=0x40 11 unc_h_rxc_ipq1_reject.any_ipq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0 event=0x23,umask=1 11 unc_h_rxc_ipq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA event=0x23,umask=2 11 unc_h_rxc_ipq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY event=0x23,umask=0x20 11 unc_h_rxc_ipq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM event=0x23,umask=4 11 unc_h_rxc_ipq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH event=0x23,umask=0x80 11 unc_h_rxc_ipq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM event=0x23,umask=8 11 unc_h_rxc_ipq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM event=0x23,umask=0x10 11 unc_h_rxc_irq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0 event=0x18,umask=1 11 unc_h_rxc_irq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0 event=0x18,umask=2 11 unc_h_rxc_irq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0 event=0x18,umask=0x10 11 unc_h_rxc_irq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0 event=0x18,umask=0x20 11 unc_h_rxc_irq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0 event=0x18,umask=4 11 unc_h_rxc_irq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0 event=0x18,umask=8 11 unc_h_rxc_irq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP event=0x19,umask=0x40 11 unc_h_rxc_irq1_reject.any_reject_irq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0 event=0x19,umask=1 11 unc_h_rxc_irq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA event=0x19,umask=2 11 unc_h_rxc_irq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY event=0x19,umask=0x20 11 unc_h_rxc_irq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM event=0x19,umask=4 11 unc_h_rxc_irq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH event=0x19,umask=0x80 11 unc_h_rxc_irq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM event=0x19,umask=8 11 unc_h_rxc_irq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM event=0x19,umask=0x10 11 unc_h_rxc_ismq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0 event=0x24,umask=1 11 unc_h_rxc_ismq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0 event=0x24,umask=2 11 unc_h_rxc_ismq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0 event=0x24,umask=0x10 11 unc_h_rxc_ismq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0 event=0x24,umask=0x20 11 unc_h_rxc_ismq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0 event=0x24,umask=4 11 unc_h_rxc_ismq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0 event=0x24,umask=8 11 unc_h_rxc_ismq0_retry.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0 event=0x2c,umask=1 11 unc_h_rxc_ismq0_retry.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0 event=0x2c,umask=2 11 unc_h_rxc_ismq0_retry.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0 event=0x2c,umask=0x10 11 unc_h_rxc_ismq0_retry.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0 event=0x2c,umask=0x20 11 unc_h_rxc_ismq0_retry.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0 event=0x2c,umask=4 11 unc_h_rxc_ismq0_retry.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0 event=0x2c,umask=8 11 unc_h_rxc_ismq1_reject.any_ismq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0 event=0x25,umask=1 11 unc_h_rxc_ismq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA event=0x25,umask=2 11 unc_h_rxc_ismq1_retry.any uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0 event=0x2d,umask=1 11 unc_h_rxc_ismq1_retry.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA event=0x2d,umask=2 11 unc_h_rxc_occupancy.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ event=0x11,umask=4 11 unc_h_rxc_occupancy.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ event=0x11,umask=1 11 unc_h_rxc_occupancy.rrq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ event=0x11,umask=0x40 11 unc_h_rxc_occupancy.wbq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ event=0x11,umask=0x80 11 unc_h_rxc_other0_retry.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0 event=0x2e,umask=1 11 unc_h_rxc_other0_retry.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0 event=0x2e,umask=2 11 unc_h_rxc_other0_retry.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0 event=0x2e,umask=0x10 11 unc_h_rxc_other0_retry.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0 event=0x2e,umask=0x20 11 unc_h_rxc_other0_retry.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0 event=0x2e,umask=4 11 unc_h_rxc_other0_retry.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0 event=0x2e,umask=8 11 unc_h_rxc_other1_retry.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP event=0x2f,umask=0x40 11 unc_h_rxc_other1_retry.any uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0 event=0x2f,umask=1 11 unc_h_rxc_other1_retry.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA event=0x2f,umask=2 11 unc_h_rxc_other1_retry.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY event=0x2f,umask=0x20 11 unc_h_rxc_other1_retry.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM event=0x2f,umask=4 11 unc_h_rxc_other1_retry.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH event=0x2f,umask=0x80 11 unc_h_rxc_other1_retry.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM event=0x2f,umask=8 11 unc_h_rxc_other1_retry.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM event=0x2f,umask=0x10 11 unc_h_rxc_prq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0 event=0x20,umask=1 11 unc_h_rxc_prq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0 event=0x20,umask=2 11 unc_h_rxc_prq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0 event=0x20,umask=0x10 11 unc_h_rxc_prq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0 event=0x20,umask=0x20 11 unc_h_rxc_prq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0 event=0x20,umask=4 11 unc_h_rxc_prq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0 event=0x20,umask=8 11 unc_h_rxc_prq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP event=0x21,umask=0x40 11 unc_h_rxc_prq1_reject.any_prq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0 event=0x21,umask=1 11 unc_h_rxc_prq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA event=0x21,umask=2 11 unc_h_rxc_prq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY event=0x21,umask=0x20 11 unc_h_rxc_prq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM event=0x21,umask=4 11 unc_h_rxc_prq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH event=0x21,umask=0x80 11 unc_h_rxc_prq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM event=0x21,umask=8 11 unc_h_rxc_prq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM event=0x21,umask=0x10 11 unc_h_rxc_req_q0_retry.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0 event=0x2a,umask=1 11 unc_h_rxc_req_q0_retry.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0 event=0x2a,umask=2 11 unc_h_rxc_req_q0_retry.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0 event=0x2a,umask=0x10 11 unc_h_rxc_req_q0_retry.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0 event=0x2a,umask=0x20 11 unc_h_rxc_req_q0_retry.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0 event=0x2a,umask=4 11 unc_h_rxc_req_q0_retry.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0 event=0x2a,umask=8 11 unc_h_rxc_req_q1_retry.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP event=0x2b,umask=0x40 11 unc_h_rxc_req_q1_retry.any uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0 event=0x2b,umask=1 11 unc_h_rxc_req_q1_retry.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA event=0x2b,umask=2 11 unc_h_rxc_req_q1_retry.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY event=0x2b,umask=0x20 11 unc_h_rxc_req_q1_retry.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM event=0x2b,umask=4 11 unc_h_rxc_req_q1_retry.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH event=0x2b,umask=0x80 11 unc_h_rxc_req_q1_retry.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM event=0x2b,umask=8 11 unc_h_rxc_req_q1_retry.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM event=0x2b,umask=0x10 11 unc_h_rxc_rrq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0 event=0x26,umask=1 11 unc_h_rxc_rrq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0 event=0x26,umask=2 11 unc_h_rxc_rrq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0 event=0x26,umask=0x10 11 unc_h_rxc_rrq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0 event=0x26,umask=0x20 11 unc_h_rxc_rrq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0 event=0x26,umask=4 11 unc_h_rxc_rrq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0 event=0x26,umask=8 11 unc_h_rxc_rrq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP event=0x27,umask=0x40 11 unc_h_rxc_rrq1_reject.any_rrq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0 event=0x27,umask=1 11 unc_h_rxc_rrq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA event=0x27,umask=2 11 unc_h_rxc_rrq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY event=0x27,umask=0x20 11 unc_h_rxc_rrq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM event=0x27,umask=4 11 unc_h_rxc_rrq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH event=0x27,umask=0x80 11 unc_h_rxc_rrq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM event=0x27,umask=8 11 unc_h_rxc_rrq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM event=0x27,umask=0x10 11 unc_h_rxc_wbq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0 event=0x28,umask=1 11 unc_h_rxc_wbq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0 event=0x28,umask=2 11 unc_h_rxc_wbq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0 event=0x28,umask=0x10 11 unc_h_rxc_wbq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0 event=0x28,umask=0x20 11 unc_h_rxc_wbq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0 event=0x28,umask=4 11 unc_h_rxc_wbq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0 event=0x28,umask=8 11 unc_h_rxc_wbq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP event=0x29,umask=0x40 11 unc_h_rxc_wbq1_reject.any_wbq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0 event=0x29,umask=1 11 unc_h_rxc_wbq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA event=0x29,umask=2 11 unc_h_rxc_wbq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY event=0x29,umask=0x20 11 unc_h_rxc_wbq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM event=0x29,umask=4 11 unc_h_rxc_wbq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH event=0x29,umask=0x80 11 unc_h_rxc_wbq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM event=0x29,umask=8 11 unc_h_rxc_wbq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM event=0x29,umask=0x10 11 unc_h_rxr_busy_starved.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC event=0xb4,umask=1 11 unc_h_rxr_busy_starved.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD event=0xb4,umask=0x10 11 unc_h_rxr_busy_starved.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC event=0xb4,umask=4 11 unc_h_rxr_busy_starved.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD event=0xb4,umask=0x40 11 unc_h_rxr_bypass.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC event=0xb2,umask=1 11 unc_h_rxr_bypass.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD event=0xb2,umask=0x10 11 unc_h_rxr_bypass.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC event=0xb2,umask=2 11 unc_h_rxr_bypass.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC event=0xb2,umask=4 11 unc_h_rxr_bypass.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD event=0xb2,umask=0x40 11 unc_h_rxr_bypass.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC event=0xb2,umask=8 11 unc_h_rxr_crd_starved.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC event=0xb3,umask=1 11 unc_h_rxr_crd_starved.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD event=0xb3,umask=0x10 11 unc_h_rxr_crd_starved.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC event=0xb3,umask=2 11 unc_h_rxr_crd_starved.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC event=0xb3,umask=4 11 unc_h_rxr_crd_starved.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD event=0xb3,umask=0x40 11 unc_h_rxr_crd_starved.ifv uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV event=0xb3,umask=0x80 11 unc_h_rxr_crd_starved.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC event=0xb3,umask=8 11 unc_h_rxr_inserts.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC event=0xb1,umask=1 11 unc_h_rxr_inserts.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD event=0xb1,umask=0x10 11 unc_h_rxr_inserts.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC event=0xb1,umask=2 11 unc_h_rxr_inserts.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC event=0xb1,umask=4 11 unc_h_rxr_inserts.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD event=0xb1,umask=0x40 11 unc_h_rxr_inserts.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC event=0xb1,umask=8 11 unc_h_rxr_occupancy.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC event=0xb0,umask=1 11 unc_h_rxr_occupancy.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD event=0xb0,umask=0x10 11 unc_h_rxr_occupancy.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC event=0xb0,umask=2 11 unc_h_rxr_occupancy.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC event=0xb0,umask=4 11 unc_h_rxr_occupancy.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD event=0xb0,umask=0x40 11 unc_h_rxr_occupancy.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC event=0xb0,umask=8 11 unc_h_sf_eviction.e_state uncore cache This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE event=0x3d,umask=2 11 unc_h_sf_eviction.m_state uncore cache This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE event=0x3d,umask=1 11 unc_h_sf_eviction.s_state uncore cache This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE event=0x3d,umask=4 11 unc_h_snoops_sent. uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL event=0x51,umask=1 11 unc_h_snoops_sent.bcst_loc uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL event=0x51,umask=0x10 11 unc_h_snoops_sent.bcst_rem uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE event=0x51,umask=0x20 11 unc_h_snoops_sent.direct_loc uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL event=0x51,umask=0x40 11 unc_h_snoops_sent.direct_rem uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE event=0x51,umask=0x80 11 unc_h_snoops_sent.local uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL event=0x51,umask=4 11 unc_h_snoops_sent.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE event=0x51,umask=8 11 unc_h_snoop_resp.rspcnflct uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS event=0x5c,umask=0x40 11 unc_h_snoop_resp.rspfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD event=0x5c,umask=0x80 11 unc_h_snoop_resp.rspi uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI event=0x5c,umask=1 11 unc_h_snoop_resp.rspifwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD event=0x5c,umask=4 11 unc_h_snoop_resp.rsps uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS event=0x5c,umask=2 11 unc_h_snoop_resp.rspsfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD event=0x5c,umask=8 11 unc_h_snoop_resp.rsp_fwd_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB event=0x5c,umask=0x20 11 unc_h_snoop_resp.rsp_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB event=0x5c,umask=0x10 11 unc_h_snp_rsp_rcv_local.rspcnflct uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT event=0x5d,umask=0x40 11 unc_h_snp_rsp_rcv_local.rspfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD event=0x5d,umask=0x80 11 unc_h_snp_rsp_rcv_local.rspi uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI event=0x5d,umask=1 11 unc_h_snp_rsp_rcv_local.rspifwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD event=0x5d,umask=4 11 unc_h_snp_rsp_rcv_local.rsps uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS event=0x5d,umask=2 11 unc_h_snp_rsp_rcv_local.rspsfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD event=0x5d,umask=8 11 unc_h_snp_rsp_rcv_local.rsp_fwd_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB event=0x5d,umask=0x20 11 unc_h_snp_rsp_rcv_local.rsp_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB event=0x5d,umask=0x10 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0 event=0xd0,umask=1 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1 event=0xd0,umask=2 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2 event=0xd0,umask=4 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3 event=0xd0,umask=8 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4 event=0xd0,umask=0x10 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5 event=0xd0,umask=0x20 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0 event=0xd2,umask=1 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1 event=0xd2,umask=2 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2 event=0xd2,umask=4 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3 event=0xd2,umask=8 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4 event=0xd2,umask=0x10 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5 event=0xd2,umask=0x20 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0 event=0xd4,umask=1 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1 event=0xd4,umask=2 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2 event=0xd4,umask=4 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3 event=0xd4,umask=8 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4 event=0xd4,umask=0x10 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5 event=0xd4,umask=0x20 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0 event=0xd6,umask=1 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1 event=0xd6,umask=2 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2 event=0xd6,umask=4 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3 event=0xd6,umask=8 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4 event=0xd6,umask=0x10 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5 event=0xd6,umask=0x20 11 unc_h_txr_horz_ads_used.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC event=0x9d,umask=1 11 unc_h_txr_horz_ads_used.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD event=0x9d,umask=0x10 11 unc_h_txr_horz_ads_used.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC event=0x9d,umask=2 11 unc_h_txr_horz_ads_used.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC event=0x9d,umask=4 11 unc_h_txr_horz_ads_used.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD event=0x9d,umask=0x40 11 unc_h_txr_horz_bypass.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC event=0x9f,umask=1 11 unc_h_txr_horz_bypass.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD event=0x9f,umask=0x10 11 unc_h_txr_horz_bypass.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC event=0x9f,umask=2 11 unc_h_txr_horz_bypass.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC event=0x9f,umask=4 11 unc_h_txr_horz_bypass.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD event=0x9f,umask=0x40 11 unc_h_txr_horz_bypass.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC event=0x9f,umask=8 11 unc_h_txr_horz_cycles_full.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC event=0x96,umask=1 11 unc_h_txr_horz_cycles_full.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD event=0x96,umask=0x10 11 unc_h_txr_horz_cycles_full.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC event=0x96,umask=2 11 unc_h_txr_horz_cycles_full.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC event=0x96,umask=4 11 unc_h_txr_horz_cycles_full.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD event=0x96,umask=0x40 11 unc_h_txr_horz_cycles_full.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC event=0x96,umask=8 11 unc_h_txr_horz_cycles_ne.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC event=0x97,umask=1 11 unc_h_txr_horz_cycles_ne.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD event=0x97,umask=0x10 11 unc_h_txr_horz_cycles_ne.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC event=0x97,umask=2 11 unc_h_txr_horz_cycles_ne.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC event=0x97,umask=4 11 unc_h_txr_horz_cycles_ne.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD event=0x97,umask=0x40 11 unc_h_txr_horz_cycles_ne.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC event=0x97,umask=8 11 unc_h_txr_horz_inserts.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC event=0x95,umask=1 11 unc_h_txr_horz_inserts.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD event=0x95,umask=0x10 11 unc_h_txr_horz_inserts.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC event=0x95,umask=2 11 unc_h_txr_horz_inserts.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC event=0x95,umask=4 11 unc_h_txr_horz_inserts.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD event=0x95,umask=0x40 11 unc_h_txr_horz_inserts.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC event=0x95,umask=8 11 unc_h_txr_horz_nack.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC event=0x99,umask=1 11 unc_h_txr_horz_nack.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD event=0x99,umask=0x20 11 unc_h_txr_horz_nack.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC event=0x99,umask=2 11 unc_h_txr_horz_nack.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC event=0x99,umask=4 11 unc_h_txr_horz_nack.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD event=0x99,umask=0x40 11 unc_h_txr_horz_nack.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC event=0x99,umask=8 11 unc_h_txr_horz_occupancy.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC event=0x94,umask=1 11 unc_h_txr_horz_occupancy.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD event=0x94,umask=0x10 11 unc_h_txr_horz_occupancy.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC event=0x94,umask=2 11 unc_h_txr_horz_occupancy.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC event=0x94,umask=4 11 unc_h_txr_horz_occupancy.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD event=0x94,umask=0x40 11 unc_h_txr_horz_occupancy.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC event=0x94,umask=8 11 unc_h_txr_horz_starved.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC event=0x9b,umask=1 11 unc_h_txr_horz_starved.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC event=0x9b,umask=2 11 unc_h_txr_horz_starved.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC event=0x9b,umask=4 11 unc_h_txr_horz_starved.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC event=0x9b,umask=8 11 unc_h_txr_vert_ads_used.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0 event=0x9c,umask=1 11 unc_h_txr_vert_ads_used.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1 event=0x9c,umask=0x10 11 unc_h_txr_vert_ads_used.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0 event=0x9c,umask=2 11 unc_h_txr_vert_ads_used.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1 event=0x9c,umask=0x20 11 unc_h_txr_vert_ads_used.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0 event=0x9c,umask=4 11 unc_h_txr_vert_ads_used.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1 event=0x9c,umask=0x40 11 unc_h_txr_vert_bypass.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0 event=0x9e,umask=1 11 unc_h_txr_vert_bypass.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1 event=0x9e,umask=0x10 11 unc_h_txr_vert_bypass.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0 event=0x9e,umask=2 11 unc_h_txr_vert_bypass.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1 event=0x9e,umask=0x20 11 unc_h_txr_vert_bypass.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0 event=0x9e,umask=4 11 unc_h_txr_vert_bypass.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1 event=0x9e,umask=0x40 11 unc_h_txr_vert_bypass.iv_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV event=0x9e,umask=8 11 unc_h_txr_vert_cycles_full.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0 event=0x92,umask=1 11 unc_h_txr_vert_cycles_full.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1 event=0x92,umask=0x10 11 unc_h_txr_vert_cycles_full.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0 event=0x92,umask=2 11 unc_h_txr_vert_cycles_full.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1 event=0x92,umask=0x20 11 unc_h_txr_vert_cycles_full.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0 event=0x92,umask=4 11 unc_h_txr_vert_cycles_full.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1 event=0x92,umask=0x40 11 unc_h_txr_vert_cycles_full.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV event=0x92,umask=8 11 unc_h_txr_vert_cycles_ne.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0 event=0x93,umask=1 11 unc_h_txr_vert_cycles_ne.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1 event=0x93,umask=0x10 11 unc_h_txr_vert_cycles_ne.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0 event=0x93,umask=2 11 unc_h_txr_vert_cycles_ne.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1 event=0x93,umask=0x20 11 unc_h_txr_vert_cycles_ne.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0 event=0x93,umask=4 11 unc_h_txr_vert_cycles_ne.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1 event=0x93,umask=0x40 11 unc_h_txr_vert_cycles_ne.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV event=0x93,umask=8 11 unc_h_txr_vert_inserts.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0 event=0x91,umask=1 11 unc_h_txr_vert_inserts.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1 event=0x91,umask=0x10 11 unc_h_txr_vert_inserts.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0 event=0x91,umask=2 11 unc_h_txr_vert_inserts.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1 event=0x91,umask=0x20 11 unc_h_txr_vert_inserts.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0 event=0x91,umask=4 11 unc_h_txr_vert_inserts.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1 event=0x91,umask=0x40 11 unc_h_txr_vert_inserts.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV event=0x91,umask=8 11 unc_h_txr_vert_nack.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0 event=0x98,umask=1 11 unc_h_txr_vert_nack.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1 event=0x98,umask=0x10 11 unc_h_txr_vert_nack.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0 event=0x98,umask=2 11 unc_h_txr_vert_nack.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1 event=0x98,umask=0x20 11 unc_h_txr_vert_nack.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0 event=0x98,umask=4 11 unc_h_txr_vert_nack.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1 event=0x98,umask=0x40 11 unc_h_txr_vert_nack.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV event=0x98,umask=8 11 unc_h_txr_vert_occupancy.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0 event=0x90,umask=1 11 unc_h_txr_vert_occupancy.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1 event=0x90,umask=0x10 11 unc_h_txr_vert_occupancy.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0 event=0x90,umask=2 11 unc_h_txr_vert_occupancy.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1 event=0x90,umask=0x20 11 unc_h_txr_vert_occupancy.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0 event=0x90,umask=4 11 unc_h_txr_vert_occupancy.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1 event=0x90,umask=0x40 11 unc_h_txr_vert_occupancy.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV event=0x90,umask=8 11 unc_h_txr_vert_starved.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0 event=0x9a,umask=1 11 unc_h_txr_vert_starved.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1 event=0x9a,umask=0x10 11 unc_h_txr_vert_starved.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0 event=0x9a,umask=2 11 unc_h_txr_vert_starved.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1 event=0x9a,umask=0x20 11 unc_h_txr_vert_starved.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0 event=0x9a,umask=4 11 unc_h_txr_vert_starved.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1 event=0x9a,umask=0x40 11 unc_h_txr_vert_starved.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV event=0x9a,umask=8 11 unc_h_vert_ring_ad_in_use.dn_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN event=0xa6,umask=4 11 unc_h_vert_ring_ad_in_use.dn_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD event=0xa6,umask=8 11 unc_h_vert_ring_ad_in_use.up_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN event=0xa6,umask=1 11 unc_h_vert_ring_ad_in_use.up_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD event=0xa6,umask=2 11 unc_h_vert_ring_ak_in_use.dn_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN event=0xa8,umask=4 11 unc_h_vert_ring_ak_in_use.dn_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD event=0xa8,umask=8 11 unc_h_vert_ring_ak_in_use.up_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN event=0xa8,umask=1 11 unc_h_vert_ring_ak_in_use.up_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD event=0xa8,umask=2 11 unc_h_vert_ring_bl_in_use.dn_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN event=0xaa,umask=4 11 unc_h_vert_ring_bl_in_use.dn_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD event=0xaa,umask=8 11 unc_h_vert_ring_bl_in_use.up_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN event=0xaa,umask=1 11 unc_h_vert_ring_bl_in_use.up_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD event=0xaa,umask=2 11 unc_h_vert_ring_iv_in_use.dn uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN event=0xac,umask=4 11 unc_h_vert_ring_iv_in_use.up uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP event=0xac,umask=1 11 unc_h_wb_push_mtoi.llc uncore cache This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC event=0x56,umask=1 11 unc_h_wb_push_mtoi.mem uncore cache This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM event=0x56,umask=2 11 unc_h_write_no_credits.edc0_smi2 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2 event=0x5a,umask=4 11 unc_h_write_no_credits.edc1_smi3 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3 event=0x5a,umask=8 11 unc_h_write_no_credits.edc2_smi4 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4 event=0x5a,umask=0x10 11 unc_h_write_no_credits.edc3_smi5 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5 event=0x5a,umask=0x20 11 unc_h_write_no_credits.mc0_smi0 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0 event=0x5a,umask=1 11 unc_h_write_no_credits.mc1_smi1 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1 event=0x5a,umask=2 11 unc_h_xsnp_resp.any_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE event=0x32,umask=0xe4 11 unc_h_xsnp_resp.any_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM event=0x32,umask=0xf0 11 unc_h_xsnp_resp.any_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE event=0x32,umask=0xe2 11 unc_h_xsnp_resp.any_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM event=0x32,umask=0xe8 11 unc_h_xsnp_resp.any_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE event=0x32,umask=0xe1 11 unc_h_xsnp_resp.core_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE event=0x32,umask=0x44 11 unc_h_xsnp_resp.core_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM event=0x32,umask=0x50 11 unc_h_xsnp_resp.core_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE event=0x32,umask=0x42 11 unc_h_xsnp_resp.core_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM event=0x32,umask=0x48 11 unc_h_xsnp_resp.core_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE event=0x32,umask=0x41 11 unc_h_xsnp_resp.evict_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE event=0x32,umask=0x84 11 unc_h_xsnp_resp.evict_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM event=0x32,umask=0x90 11 unc_h_xsnp_resp.evict_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE event=0x32,umask=0x82 11 unc_h_xsnp_resp.evict_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM event=0x32,umask=0x88 11 unc_h_xsnp_resp.evict_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE event=0x32,umask=0x81 11 unc_h_xsnp_resp.ext_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE event=0x32,umask=0x24 11 unc_h_xsnp_resp.ext_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM event=0x32,umask=0x30 11 unc_h_xsnp_resp.ext_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE event=0x32,umask=0x22 11 unc_h_xsnp_resp.ext_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM event=0x32,umask=0x28 11 unc_h_xsnp_resp.ext_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE event=0x32,umask=0x21 11 unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy; Any Source event=0xf,umask=1 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port unc_i_cache_total_occupancy.iv_q uncore interconnect Total Write Cache Occupancy; Snoops event=0xf,umask=2 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_cache_total_occupancy.mem uncore interconnect Total IRP occupancy of inbound read and write requests event=0xf,umask=4 01 Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy unc_i_clockticks uncore interconnect IRP Clocks event=1 01 unc_i_coherent_ops.clflush uncore interconnect Coherent Ops; CLFlush event=0x10,umask=0x80 01 Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.crd uncore interconnect Coherent Ops; CRd event=0x10,umask=2 01 Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.drd uncore interconnect Coherent Ops; DRd event=0x10,umask=4 01 Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.pcidcahint uncore interconnect Coherent Ops; PCIDCAHin5t event=0x10,umask=0x20 01 Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.pcirdcur uncore interconnect Coherent Ops; PCIRdCur event=0x10,umask=1 01 Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.pcitom uncore interconnect PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline event=0x10,umask=0x10 01 PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache unc_i_coherent_ops.rfo uncore interconnect RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline event=0x10,umask=8 01 RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache unc_i_coherent_ops.wbmtoi uncore interconnect Coherent Ops; WbMtoI event=0x10,umask=0x40 01 Counts the number of coherency related operations serviced by the IRP unc_i_faf_full uncore interconnect FAF RF full event=0x17 01 unc_i_faf_inserts uncore interconnect Inbound read requests received by the IRP and inserted into the FAF queue event=0x18 01 Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP unc_i_faf_occupancy uncore interconnect Occupancy of the IRP FAF queue event=0x19 01 Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP unc_i_faf_transactions uncore interconnect FAF allocation -- sent to ADQ event=0x16 01 unc_i_irp_all.inbound_inserts uncore interconnect All Inserts Inbound (p2p + faf + cset) event=0x1e,umask=1 01 unc_i_irp_all.outbound_inserts uncore interconnect All Inserts Outbound (BL, AK, Snoops) event=0x1e,umask=2 01 unc_i_misc0.2nd_atomic_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary event=0x1c,umask=0x10 01 unc_i_misc0.2nd_rd_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary event=0x1c,umask=4 01 unc_i_misc0.2nd_wr_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary event=0x1c,umask=8 01 unc_i_misc0.fast_rej uncore interconnect Misc Events - Set 0; Fastpath Rejects event=0x1c,umask=2 01 unc_i_misc0.fast_req uncore interconnect Misc Events - Set 0; Fastpath Requests event=0x1c,umask=1 01 unc_i_misc0.fast_xfer uncore interconnect Misc Events - Set 0; Fastpath Transfers From Primary to Secondary event=0x1c,umask=0x20 01 unc_i_misc0.pf_ack_hint uncore interconnect Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary event=0x1c,umask=0x40 01 unc_i_misc0.unknown uncore interconnect Misc Events - Set 0 event=0x1c,umask=0x80 01 unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1; Lost Forward event=0x1d,umask=0x10 01 Snoop pulled away ownership before a write was committed unc_i_misc1.sec_rcvd_invld uncore interconnect Misc Events - Set 1; Received Invalid event=0x1d,umask=0x20 01 Secondary received a transfer that did not have sufficient MESI state unc_i_misc1.sec_rcvd_vld uncore interconnect Misc Events - Set 1; Received Valid event=0x1d,umask=0x40 01 Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_e uncore interconnect Misc Events - Set 1; Slow Transfer of E Line event=0x1d,umask=4 01 Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_i uncore interconnect Misc Events - Set 1; Slow Transfer of I Line event=0x1d,umask=1 01 Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_m uncore interconnect Misc Events - Set 1; Slow Transfer of M Line event=0x1d,umask=8 01 Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_s uncore interconnect Misc Events - Set 1; Slow Transfer of S Line event=0x1d,umask=2 01 Secondary received a transfer that did not have sufficient MESI state unc_i_p2p_inserts uncore interconnect P2P Requests event=0x14 01 P2P requests from the ITC unc_i_p2p_occupancy uncore interconnect P2P Occupancy event=0x15 01 P2P B & S Queue Occupancy unc_i_p2p_transactions.cmpl uncore interconnect P2P Transactions; P2P completions event=0x13,umask=8 01 unc_i_p2p_transactions.loc uncore interconnect P2P Transactions; match if local only event=0x13,umask=0x40 01 unc_i_p2p_transactions.loc_and_tgt_match uncore interconnect P2P Transactions; match if local and target matches event=0x13,umask=0x80 01 unc_i_p2p_transactions.msg uncore interconnect P2P Transactions; P2P Message event=0x13,umask=4 01 unc_i_p2p_transactions.rd uncore interconnect P2P Transactions; P2P reads event=0x13,umask=1 01 unc_i_p2p_transactions.rem uncore interconnect P2P Transactions; Match if remote only event=0x13,umask=0x10 01 unc_i_p2p_transactions.rem_and_tgt_match uncore interconnect P2P Transactions; match if remote and target matches event=0x13,umask=0x20 01 unc_i_p2p_transactions.wr uncore interconnect P2P Transactions; P2P Writes event=0x13,umask=2 01 unc_i_snoop_resp.all_hit uncore interconnect Responses to snoops of any type that hit M, E, S or I line in the IIO event=0x12,umask=0x7e 01 Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO unc_i_snoop_resp.all_hit_es uncore interconnect Responses to snoops of any type that hit E or S line in the IIO cache event=0x12,umask=0x74 01 Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache unc_i_snoop_resp.all_hit_i uncore interconnect Responses to snoops of any type that hit I line in the IIO cache event=0x12,umask=0x72 01 Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache unc_i_snoop_resp.all_hit_m uncore interconnect Responses to snoops of any type that hit M line in the IIO cache event=0x12,umask=0x78 01 Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache unc_i_snoop_resp.all_miss uncore interconnect Responses to snoops of any type that miss the IIO cache event=0x12,umask=0x71 01 Responses to snoops of any type (code, data, invalidate) that miss the IIO cache unc_i_snoop_resp.hit_es uncore interconnect Snoop Responses; Hit E or S event=0x12,umask=4 01 unc_i_snoop_resp.hit_i uncore interconnect Snoop Responses; Hit I event=0x12,umask=2 01 unc_i_snoop_resp.hit_m uncore interconnect Snoop Responses; Hit M event=0x12,umask=8 01 unc_i_snoop_resp.miss uncore interconnect Snoop Responses; Miss event=0x12,umask=1 01 unc_i_snoop_resp.snpcode uncore interconnect Snoop Responses; SnpCode event=0x12,umask=0x10 01 unc_i_snoop_resp.snpdata uncore interconnect Snoop Responses; SnpData event=0x12,umask=0x20 01 unc_i_snoop_resp.snpinv uncore interconnect Snoop Responses; SnpInv event=0x12,umask=0x40 01 unc_i_transactions.atomic uncore interconnect Inbound Transaction Count; Atomic event=0x11,umask=0x10 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions unc_i_transactions.other uncore interconnect Inbound Transaction Count; Other event=0x11,umask=0x20 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions unc_i_transactions.rd_pref uncore interconnect Inbound Transaction Count; Read Prefetches event=0x11,umask=4 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x11,umask=1 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches) unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x11,umask=2 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry unc_i_transactions.wr_pref uncore interconnect Inbound write (fast path) requests received by the IRP event=0x11,umask=8 01 Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh unc_i_txc_ak_inserts uncore interconnect AK Egress Allocations event=0xb 01 unc_i_txc_bl_drs_cycles_full uncore interconnect BL DRS Egress Cycles Full event=5 01 unc_i_txc_bl_drs_inserts uncore interconnect BL DRS Egress Inserts event=2 01 unc_i_txc_bl_drs_occupancy uncore interconnect BL DRS Egress Occupancy event=8 01 unc_i_txc_bl_ncb_cycles_full uncore interconnect BL NCB Egress Cycles Full event=6 01 unc_i_txc_bl_ncb_inserts uncore interconnect BL NCB Egress Inserts event=3 01 unc_i_txc_bl_ncb_occupancy uncore interconnect BL NCB Egress Occupancy event=9 01 unc_i_txc_bl_ncs_cycles_full uncore interconnect BL NCS Egress Cycles Full event=7 01 unc_i_txc_bl_ncs_inserts uncore interconnect BL NCS Egress Inserts event=4 01 unc_i_txc_bl_ncs_occupancy uncore interconnect BL NCS Egress Occupancy event=0xa 01 unc_i_txr2_ad_stall_credit_cycles uncore interconnect No AD Egress Credit Stalls event=0x1a 01 Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available unc_i_txr2_bl_stall_credit_cycles uncore interconnect No BL Egress Credit Stalls event=0x1b 01 Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available unc_i_txs_data_inserts_ncb uncore interconnect Outbound Read Requests event=0xd 01 Counts the number of requests issued to the switch (towards the devices) unc_i_txs_data_inserts_ncs uncore interconnect Outbound Read Requests event=0xe 01 Counts the number of requests issued to the switch (towards the devices) unc_i_txs_request_occupancy uncore interconnect Outbound Request Queue Occupancy event=0xc 01 Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests uncore_m2m unc_m2m_ag0_ad_crd_acquired.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 0 event=0x80,umask=1 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 1 event=0x80,umask=2 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 2 event=0x80,umask=4 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 3 event=0x80,umask=8 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 4 event=0x80,umask=0x10 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 5 event=0x80,umask=0x20 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 0 event=0x82,umask=1 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 1 event=0x82,umask=2 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 2 event=0x82,umask=4 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 3 event=0x82,umask=8 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 4 event=0x82,umask=0x10 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 5 event=0x82,umask=0x20 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 0 event=0x88,umask=1 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 1 event=0x88,umask=2 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 2 event=0x88,umask=4 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 3 event=0x88,umask=8 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 4 event=0x88,umask=0x10 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 5 event=0x88,umask=0x20 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 0 event=0x8a,umask=1 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 1 event=0x8a,umask=2 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 2 event=0x8a,umask=4 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 3 event=0x8a,umask=8 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 4 event=0x8a,umask=0x10 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 5 event=0x8a,umask=0x20 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 0 event=0x84,umask=1 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 1 event=0x84,umask=2 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 2 event=0x84,umask=4 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 3 event=0x84,umask=8 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 4 event=0x84,umask=0x10 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 5 event=0x84,umask=0x20 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 0 event=0x86,umask=1 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 1 event=0x86,umask=2 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 2 event=0x86,umask=4 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 3 event=0x86,umask=8 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 4 event=0x86,umask=0x10 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 5 event=0x86,umask=0x20 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 0 event=0x8e,umask=1 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 1 event=0x8e,umask=2 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 2 event=0x8e,umask=4 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 3 event=0x8e,umask=8 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 4 event=0x8e,umask=0x10 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 5 event=0x8e,umask=0x20 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 0 event=0x8c,umask=1 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 1 event=0x8c,umask=2 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 2 event=0x8c,umask=4 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 3 event=0x8c,umask=8 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 4 event=0x8c,umask=0x10 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 5 event=0x8c,umask=0x20 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_bypass_m2m_egress.not_taken uncore interconnect Traffic in which the M2M to iMC Bypass was not taken event=0x22,umask=2 01 Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken unc_m2m_bypass_m2m_egress.taken uncore interconnect M2M to iMC Bypass; Taken event=0x22,umask=1 01 unc_m2m_bypass_m2m_ingress.not_taken uncore interconnect M2M to iMC Bypass; Not Taken event=0x21,umask=2 01 unc_m2m_bypass_m2m_ingress.taken uncore interconnect M2M to iMC Bypass; Taken event=0x21,umask=1 01 unc_m2m_clockticks uncore interconnect Cycles - at UCLK event=0 01 unc_m2m_cms_clockticks uncore interconnect CMS Clockticks event=0xc0 01 unc_m2m_direct2core_not_taken_dirstate uncore interconnect Cycles when direct to core mode (which bypasses the CHA) was disabled event=0x24 01 Counts cycles when direct to core mode (which bypasses the CHA) was disabled unc_m2m_direct2core_taken uncore interconnect Messages sent direct to core (bypassing the CHA) event=0x23 01 Counts when messages were sent direct to core (bypassing the CHA) unc_m2m_direct2core_txn_override uncore interconnect Number of reads in which direct to core transaction were overridden event=0x25 01 Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden unc_m2m_direct2upi_not_taken_credits uncore interconnect Number of reads in which direct to Intel(R) UPI transactions were overridden event=0x28 01 Counts reads in which direct to Intel(R) Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden unc_m2m_direct2upi_not_taken_dirstate uncore interconnect Cycles when direct to Intel(R) UPI was disabled event=0x27 01 Counts cycles when the ability to send messages direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was disabled unc_m2m_direct2upi_taken uncore interconnect Messages sent direct to the Intel(R) UPI event=0x26 01 Counts when messages were sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) unc_m2m_direct2upi_txn_override uncore interconnect Number of reads that a message sent direct2 Intel(R) UPI was overridden event=0x29 01 Counts when a read message that was sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was overridden unc_m2m_directory_hit.clean_a uncore interconnect Directory Hit; On NonDirty Line in A State event=0x2a,umask=0x80 01 unc_m2m_directory_hit.clean_i uncore interconnect Directory Hit; On NonDirty Line in I State event=0x2a,umask=0x10 01 unc_m2m_directory_hit.clean_p uncore interconnect Directory Hit; On NonDirty Line in L State event=0x2a,umask=0x40 01 unc_m2m_directory_hit.clean_s uncore interconnect Directory Hit; On NonDirty Line in S State event=0x2a,umask=0x20 01 unc_m2m_directory_hit.dirty_a uncore interconnect Directory Hit; On Dirty Line in A State event=0x2a,umask=8 01 unc_m2m_directory_hit.dirty_i uncore interconnect Directory Hit; On Dirty Line in I State event=0x2a,umask=1 01 unc_m2m_directory_hit.dirty_p uncore interconnect Directory Hit; On Dirty Line in L State event=0x2a,umask=4 01 unc_m2m_directory_hit.dirty_s uncore interconnect Directory Hit; On Dirty Line in S State event=0x2a,umask=2 01 unc_m2m_directory_lookup.any uncore interconnect Multi-socket cacheline Directory lookups (any state found) event=0x2d,umask=1 01 Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused) unc_m2m_directory_lookup.state_a uncore interconnect Multi-socket cacheline Directory lookups (cacheline found in A state) event=0x2d,umask=8 01 Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket unc_m2m_directory_lookup.state_i uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in I state) event=0x2d,umask=2 01 Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket unc_m2m_directory_lookup.state_s uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in S state) event=0x2d,umask=4 01 Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket unc_m2m_directory_miss.clean_a uncore interconnect Directory Miss; On NonDirty Line in A State event=0x2b,umask=0x80 01 unc_m2m_directory_miss.clean_i uncore interconnect Directory Miss; On NonDirty Line in I State event=0x2b,umask=0x10 01 unc_m2m_directory_miss.clean_p uncore interconnect Directory Miss; On NonDirty Line in L State event=0x2b,umask=0x40 01 unc_m2m_directory_miss.clean_s uncore interconnect Directory Miss; On NonDirty Line in S State event=0x2b,umask=0x20 01 unc_m2m_directory_miss.dirty_a uncore interconnect Directory Miss; On Dirty Line in A State event=0x2b,umask=8 01 unc_m2m_directory_miss.dirty_i uncore interconnect Directory Miss; On Dirty Line in I State event=0x2b,umask=1 01 unc_m2m_directory_miss.dirty_p uncore interconnect Directory Miss; On Dirty Line in L State event=0x2b,umask=4 01 unc_m2m_directory_miss.dirty_s uncore interconnect Directory Miss; On Dirty Line in S State event=0x2b,umask=2 01 unc_m2m_directory_update.a2i uncore interconnect Multi-socket cacheline Directory update from A to I event=0x2e,umask=0x20 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid) unc_m2m_directory_update.a2s uncore interconnect Multi-socket cacheline Directory update from A to S event=0x2e,umask=0x40 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared) unc_m2m_directory_update.any uncore interconnect Multi-socket cacheline Directory update from/to Any state event=0x2e,umask=1 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state unc_m2m_directory_update.i2a uncore interconnect Multi-socket cacheline Directory update from I to A event=0x2e,umask=4 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll) unc_m2m_directory_update.i2s uncore interconnect Multi-socket cacheline Directory update from I to S event=0x2e,umask=2 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared) unc_m2m_directory_update.s2a uncore interconnect Multi-socket cacheline Directory update from S to A event=0x2e,umask=0x10 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll) unc_m2m_directory_update.s2i uncore interconnect Multi-socket cacheline Directory update from S to I event=0x2e,umask=8 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid) unc_m2m_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements; Down event=0xae,umask=4 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements; Up event=0xae,umask=1 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_fast_asserted.horz uncore interconnect FaST wire asserted; Horizontal event=0xa5,umask=2 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_m2m_fast_asserted.vert uncore interconnect FaST wire asserted; Vertical event=0xa5,umask=1 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_m2m_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use; Left and Even event=0xa7,umask=1 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use; Left and Odd event=0xa7,umask=2 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use; Right and Even event=0xa7,umask=4 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use; Right and Odd event=0xa7,umask=8 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use; Left and Even event=0xa9,umask=1 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use; Left and Odd event=0xa9,umask=2 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use; Right and Even event=0xa9,umask=4 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use; Right and Odd event=0xa9,umask=8 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use; Left and Even event=0xab,umask=1 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use; Left and Odd event=0xab,umask=2 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use; Right and Even event=0xab,umask=4 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use; Right and Odd event=0xab,umask=8 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use; Left event=0xad,umask=1 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use; Right event=0xad,umask=4 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_imc_reads.all uncore interconnect Reads to iMC issued event=0x37,umask=4 01 Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller) unc_m2m_imc_reads.from_transgress uncore interconnect M2M Reads Issued to iMC; All, regardless of priority event=0x37,umask=0x10 01 unc_m2m_imc_reads.isoch uncore interconnect M2M Reads Issued to iMC; Critical Priority event=0x37,umask=2 01 unc_m2m_imc_reads.normal uncore interconnect Reads to iMC issued at Normal Priority (Non-Isochronous) event=0x37,umask=1 01 Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads unc_m2m_imc_reads.to_pmm uncore interconnect Read requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M event=0x37,umask=8 01 M2M Reads Issued to iMC; All, regardless of priority unc_m2m_imc_writes.all uncore interconnect Writes to iMC issued event=0x38,umask=0x10 01 Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller) unc_m2m_imc_writes.from_transgress uncore interconnect M2M Writes Issued to iMC; All, regardless of priority event=0x38,umask=0x40 01 unc_m2m_imc_writes.full uncore interconnect M2M Writes Issued to iMC; Full Line Non-ISOCH event=0x38,umask=1 01 unc_m2m_imc_writes.full_isoch uncore interconnect M2M Writes Issued to iMC; ISOCH Full Line event=0x38,umask=4 01 unc_m2m_imc_writes.ni uncore interconnect M2M Writes Issued to iMC; All, regardless of priority event=0x38,umask=0x80 01 unc_m2m_imc_writes.partial uncore interconnect Partial Non-Isochronous writes to the iMC event=0x38,umask=2 01 Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes unc_m2m_imc_writes.partial_isoch uncore interconnect M2M Writes Issued to iMC; ISOCH Partial event=0x38,umask=8 01 unc_m2m_imc_writes.to_pmm uncore interconnect Write requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M event=0x38,umask=0x20 01 M2M Writes Issued to iMC; All, regardless of priority unc_m2m_pkt_match.mc uncore interconnect Number Packet Header Matches; MC Match event=0x4c,umask=2 01 unc_m2m_pkt_match.mesh uncore interconnect Number Packet Header Matches; Mesh Match event=0x4c,umask=1 01 unc_m2m_pmm_rpq_cycles_reg_credits.chn0 uncore interconnect M2M->iMC RPQ Cycles w/Credits - Regular; Channel 0 event=0x4f,umask=1 01 unc_m2m_pmm_rpq_cycles_reg_credits.chn1 uncore interconnect M2M->iMC RPQ Cycles w/Credits - Regular; Channel 1 event=0x4f,umask=2 01 unc_m2m_pmm_rpq_cycles_reg_credits.chn2 uncore interconnect M2M->iMC RPQ Cycles w/Credits - Regular; Channel 2 event=0x4f,umask=4 01 unc_m2m_pmm_wpq_cycles_reg_credits.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0 event=0x51,umask=1 01 unc_m2m_pmm_wpq_cycles_reg_credits.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1 event=0x51,umask=2 01 unc_m2m_pmm_wpq_cycles_reg_credits.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2 event=0x51,umask=4 01 unc_m2m_prefcam_cycles_full uncore interconnect Prefetch CAM Cycles Full event=0x53 01 unc_m2m_prefcam_cycles_ne uncore interconnect Prefetch CAM Cycles Not Empty event=0x54 01 unc_m2m_prefcam_demand_promotions uncore interconnect Prefetch requests that got turn into a demand request event=0x56 01 Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory) unc_m2m_prefcam_inserts uncore interconnect Inserts into the Memory Controller Prefetch Queue event=0x57 01 Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory unc_m2m_prefcam_occupancy uncore interconnect Prefetch CAM Occupancy event=0x55 01 unc_m2m_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring.; AD event=0xa1,umask=1 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring.; AK event=0xa1,umask=2 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring.; BL event=0xa1,umask=4 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring.; IV event=0xa1,umask=8 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring.; AD event=0xa0,umask=1 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring.; Acknowledgements to core event=0xa0,umask=2 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring.; Data Responses to core event=0xa0,umask=4 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring.; Snoops of processor's cache event=0xa0,umask=8 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring; AD event=0xa3,umask=1 01 unc_m2m_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring; AK event=0xa3,umask=2 01 unc_m2m_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1 event=0xa3,umask=0x20 01 unc_m2m_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring; BL event=0xa3,umask=4 01 unc_m2m_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring; IV event=0xa3,umask=8 01 unc_m2m_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring; AD event=0xa2,umask=1 01 unc_m2m_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring; Acknowledgements to core event=0xa2,umask=2 01 unc_m2m_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring; Data Responses to core event=0xa2,umask=4 01 unc_m2m_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring; Snoops of processor's cache event=0xa2,umask=8 01 unc_m2m_ring_src_thrtl uncore interconnect Source Throttle event=0xa4 01 unc_m2m_rpq_cycles_no_spec_credits.chn0 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0 event=0x44,umask=1 11 unc_m2m_rpq_cycles_no_spec_credits.chn1 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1 event=0x44,umask=2 11 unc_m2m_rpq_cycles_no_spec_credits.chn2 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2 event=0x44,umask=4 11 unc_m2m_rpq_cycles_reg_credits.chn0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0 event=0x43,umask=1 01 unc_m2m_rpq_cycles_reg_credits.chn1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1 event=0x43,umask=2 01 unc_m2m_rpq_cycles_reg_credits.chn2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2 event=0x43,umask=4 01 unc_m2m_rpq_cycles_spec_credits.chn0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special; Channel 0 event=0x44,umask=1 01 unc_m2m_rpq_cycles_spec_credits.chn1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special; Channel 1 event=0x44,umask=2 01 unc_m2m_rpq_cycles_spec_credits.chn2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special; Channel 2 event=0x44,umask=4 01 unc_m2m_rxc_ad_cycles_full uncore interconnect AD Ingress (from CMS) Full event=4 01 unc_m2m_rxc_ad_cycles_ne uncore interconnect AD Ingress (from CMS) Not Empty event=3 01 unc_m2m_rxc_ad_inserts uncore interconnect AD Ingress (from CMS) Queue Inserts event=1 01 Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and unc_m2m_rxc_ad_occupancy uncore interconnect AD Ingress (from CMS) Occupancy event=2 01 unc_m2m_rxc_bl_cycles_full uncore interconnect BL Ingress (from CMS) Full event=8 01 unc_m2m_rxc_bl_cycles_ne uncore interconnect BL Ingress (from CMS) Not Empty event=7 01 unc_m2m_rxc_bl_inserts uncore interconnect BL Ingress (from CMS) Allocations event=5 01 unc_m2m_rxc_bl_occupancy uncore interconnect BL Ingress (from CMS) Occupancy event=6 01 unc_m2m_rxr_busy_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb4,umask=1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb4,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb4,umask=4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb4,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_bypass.ad_bnc uncore interconnect Transgress Ingress Bypass; AD - Bounce event=0xb2,umask=1 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass; AD - Credit event=0xb2,umask=0x10 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ak_bnc uncore interconnect Transgress Ingress Bypass; AK - Bounce event=0xb2,umask=2 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_bnc uncore interconnect Transgress Ingress Bypass; BL - Bounce event=0xb2,umask=4 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass; BL - Credit event=0xb2,umask=0x40 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.iv_bnc uncore interconnect Transgress Ingress Bypass; IV - Bounce event=0xb2,umask=8 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_crd_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb3,umask=1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb3,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ak_bnc uncore interconnect Transgress Injection Starvation; AK - Bounce event=0xb3,umask=2 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb3,umask=4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb3,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation; IFV - Credit event=0xb3,umask=0x80 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.iv_bnc uncore interconnect Transgress Injection Starvation; IV - Bounce event=0xb3,umask=8 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_inserts.ad_bnc uncore interconnect Transgress Ingress Allocations; AD - Bounce event=0xb1,umask=1 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations; AD - Credit event=0xb1,umask=0x10 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ak_bnc uncore interconnect Transgress Ingress Allocations; AK - Bounce event=0xb1,umask=2 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_bnc uncore interconnect Transgress Ingress Allocations; BL - Bounce event=0xb1,umask=4 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations; BL - Credit event=0xb1,umask=0x40 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.iv_bnc uncore interconnect Transgress Ingress Allocations; IV - Bounce event=0xb1,umask=8 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_bnc uncore interconnect Transgress Ingress Occupancy; AD - Bounce event=0xb0,umask=1 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy; AD - Credit event=0xb0,umask=0x10 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ak_bnc uncore interconnect Transgress Ingress Occupancy; AK - Bounce event=0xb0,umask=2 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_bnc uncore interconnect Transgress Ingress Occupancy; BL - Bounce event=0xb0,umask=4 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy; BL - Credit event=0xb0,umask=0x40 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.iv_bnc uncore interconnect Transgress Ingress Occupancy; IV - Bounce event=0xb0,umask=8 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 0 event=0xd0,umask=1 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 1 event=0xd0,umask=2 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 2 event=0xd0,umask=4 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 3 event=0xd0,umask=8 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 4 event=0xd0,umask=0x10 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 5 event=0xd0,umask=0x20 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 0 event=0xd2,umask=1 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 1 event=0xd2,umask=2 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 2 event=0xd2,umask=4 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 3 event=0xd2,umask=8 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 4 event=0xd2,umask=0x10 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 5 event=0xd2,umask=0x20 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 0 event=0xd4,umask=1 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 1 event=0xd4,umask=2 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 2 event=0xd4,umask=4 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 3 event=0xd4,umask=8 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 4 event=0xd4,umask=0x10 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 5 event=0xd4,umask=0x20 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 0 event=0xd6,umask=1 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 1 event=0xd6,umask=2 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 2 event=0xd6,umask=4 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 3 event=0xd6,umask=8 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 4 event=0xd6,umask=0x10 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 5 event=0xd6,umask=0x20 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_tag_hit.nm_rd_hit_clean uncore interconnect Clean line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM event=0x2c,umask=1 01 Tag Hit; Read Hit from NearMem, Clean Line unc_m2m_tag_hit.nm_rd_hit_dirty uncore interconnect Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode event=0x2c,umask=2 01 Tag Hit; Read Hit from NearMem, Dirty Line unc_m2m_tag_hit.nm_ufill_hit_clean uncore interconnect Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode event=0x2c,umask=4 01 Tag Hit; Underfill Rd Hit from NearMem, Clean Line unc_m2m_tag_hit.nm_ufill_hit_dirty uncore interconnect Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode event=0x2c,umask=8 01 Tag Hit; Underfill Rd Hit from NearMem, Dirty Line unc_m2m_tgr_ad_credits uncore interconnect Number AD Ingress Credits event=0x41 01 unc_m2m_tgr_bl_credits uncore interconnect Number BL Ingress Credits event=0x42 01 unc_m2m_tracker_cycles_full.ch0 uncore interconnect Tracker Cycles Full; Channel 0 event=0x45,umask=1 01 unc_m2m_tracker_cycles_full.ch1 uncore interconnect Tracker Cycles Full; Channel 1 event=0x45,umask=2 01 unc_m2m_tracker_cycles_full.ch2 uncore interconnect Tracker Cycles Full; Channel 2 event=0x45,umask=4 01 unc_m2m_tracker_cycles_ne.ch0 uncore interconnect Tracker Cycles Not Empty; Channel 0 event=0x46,umask=1 01 unc_m2m_tracker_cycles_ne.ch1 uncore interconnect Tracker Cycles Not Empty; Channel 1 event=0x46,umask=2 01 unc_m2m_tracker_cycles_ne.ch2 uncore interconnect Tracker Cycles Not Empty; Channel 2 event=0x46,umask=4 01 unc_m2m_tracker_inserts.ch0 uncore interconnect Tracker Inserts; Channel 0 event=0x49,umask=1 01 unc_m2m_tracker_inserts.ch1 uncore interconnect Tracker Inserts; Channel 1 event=0x49,umask=2 01 unc_m2m_tracker_inserts.ch2 uncore interconnect Tracker Inserts; Channel 2 event=0x49,umask=4 01 unc_m2m_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy; Channel 0 event=0x47,umask=1 01 unc_m2m_tracker_occupancy.ch1 uncore interconnect Tracker Occupancy; Channel 1 event=0x47,umask=2 01 unc_m2m_tracker_occupancy.ch2 uncore interconnect Tracker Occupancy; Channel 2 event=0x47,umask=4 01 unc_m2m_tracker_pending_occupancy uncore interconnect Data Pending Occupancy event=0x48 01 unc_m2m_txc_ad_credits_acquired uncore interconnect AD Egress (to CMS) Credit Acquired event=0xd 01 unc_m2m_txc_ad_credit_occupancy uncore interconnect AD Egress (to CMS) Credits Occupancy event=0xe 01 unc_m2m_txc_ad_cycles_full uncore interconnect AD Egress (to CMS) Full event=0xc 01 unc_m2m_txc_ad_cycles_ne uncore interconnect AD Egress (to CMS) Not Empty event=0xb 01 unc_m2m_txc_ad_inserts uncore interconnect AD Egress (to CMS) Allocations event=9 01 unc_m2m_txc_ad_no_credit_cycles uncore interconnect Cycles with No AD Egress (to CMS) Credits event=0xf 01 unc_m2m_txc_ad_no_credit_stalled uncore interconnect Cycles Stalled with No AD Egress (to CMS) Credits event=0x10 01 unc_m2m_txc_ad_occupancy uncore interconnect AD Egress (to CMS) Occupancy event=0xa 01 unc_m2m_txc_ak.crd_cbo uncore interconnect Outbound Ring Transactions on AK; CRD Transactions to Cbo event=0x39,umask=2 01 unc_m2m_txc_ak.ndr uncore interconnect Outbound Ring Transactions on AK; NDR Transactions event=0x39,umask=1 01 unc_m2m_txc_ak_credits_acquired.cms0 uncore interconnect AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side event=0x1d,umask=1 01 unc_m2m_txc_ak_credits_acquired.cms1 uncore interconnect AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side event=0x1d,umask=2 01 unc_m2m_txc_ak_credit_occupancy.cms0 uncore interconnect AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side event=0x1e,umask=1 01 unc_m2m_txc_ak_credit_occupancy.cms1 uncore interconnect AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side event=0x1e,umask=2 01 unc_m2m_txc_ak_cycles_full.all uncore interconnect AK Egress (to CMS) Full; All event=0x14,umask=3 01 unc_m2m_txc_ak_cycles_full.cms0 uncore interconnect AK Egress (to CMS) Full; Common Mesh Stop - Near Side event=0x14,umask=1 01 unc_m2m_txc_ak_cycles_full.cms1 uncore interconnect AK Egress (to CMS) Full; Common Mesh Stop - Far Side event=0x14,umask=2 01 unc_m2m_txc_ak_cycles_full.rdcrd0 uncore interconnect AK Egress (to CMS) Full; Read Credit Request event=0x14,umask=8 01 unc_m2m_txc_ak_cycles_full.rdcrd1 uncore interconnect AK Egress (to CMS) Full; Read Credit Request event=0x14,umask=0x88 01 unc_m2m_txc_ak_cycles_full.wrcmp0 uncore interconnect AK Egress (to CMS) Full; Write Compare Request event=0x14,umask=0x20 01 unc_m2m_txc_ak_cycles_full.wrcmp1 uncore interconnect AK Egress (to CMS) Full; Write Compare Request event=0x14,umask=0xa0 01 unc_m2m_txc_ak_cycles_full.wrcrd0 uncore interconnect AK Egress (to CMS) Full; Write Credit Request event=0x14,umask=0x10 01 unc_m2m_txc_ak_cycles_full.wrcrd1 uncore interconnect AK Egress (to CMS) Full; Write Credit Request event=0x14,umask=0x90 01 unc_m2m_txc_ak_cycles_ne.all uncore interconnect AK Egress (to CMS) Not Empty; All event=0x13,umask=3 01 unc_m2m_txc_ak_cycles_ne.cms0 uncore interconnect AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side event=0x13,umask=1 01 unc_m2m_txc_ak_cycles_ne.cms1 uncore interconnect AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side event=0x13,umask=2 01 unc_m2m_txc_ak_cycles_ne.rdcrd uncore interconnect AK Egress (to CMS) Not Empty; Read Credit Request event=0x13,umask=8 01 unc_m2m_txc_ak_cycles_ne.wrcmp uncore interconnect AK Egress (to CMS) Not Empty; Write Compare Request event=0x13,umask=0x20 01 unc_m2m_txc_ak_cycles_ne.wrcrd uncore interconnect AK Egress (to CMS) Not Empty; Write Credit Request event=0x13,umask=0x10 01 unc_m2m_txc_ak_inserts.all uncore interconnect AK Egress (to CMS) Allocations; All event=0x11,umask=3 01 unc_m2m_txc_ak_inserts.cms0 uncore interconnect AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side event=0x11,umask=1 01 unc_m2m_txc_ak_inserts.cms1 uncore interconnect AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side event=0x11,umask=2 01 unc_m2m_txc_ak_inserts.pref_rd_cam_hit uncore interconnect AK Egress (to CMS) Allocations; Prefetch Read Cam Hit event=0x11,umask=0x40 01 unc_m2m_txc_ak_inserts.rdcrd uncore interconnect AK Egress (to CMS) Allocations; Read Credit Request event=0x11,umask=8 01 unc_m2m_txc_ak_inserts.wrcmp uncore interconnect AK Egress (to CMS) Allocations; Write Compare Request event=0x11,umask=0x20 01 unc_m2m_txc_ak_inserts.wrcrd uncore interconnect AK Egress (to CMS) Allocations; Write Credit Request event=0x11,umask=0x10 01 unc_m2m_txc_ak_no_credit_cycles.cms0 uncore interconnect Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x1f,umask=1 01 unc_m2m_txc_ak_no_credit_cycles.cms1 uncore interconnect Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x1f,umask=2 01 unc_m2m_txc_ak_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x20,umask=1 01 unc_m2m_txc_ak_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x20,umask=2 01 unc_m2m_txc_ak_occupancy.all uncore interconnect AK Egress (to CMS) Occupancy; All event=0x12,umask=3 01 unc_m2m_txc_ak_occupancy.cms0 uncore interconnect AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side event=0x12,umask=1 01 unc_m2m_txc_ak_occupancy.cms1 uncore interconnect AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side event=0x12,umask=2 01 unc_m2m_txc_ak_occupancy.rdcrd uncore interconnect AK Egress (to CMS) Occupancy; Read Credit Request event=0x12,umask=8 01 unc_m2m_txc_ak_occupancy.wrcmp uncore interconnect AK Egress (to CMS) Occupancy; Write Compare Request event=0x12,umask=0x20 01 unc_m2m_txc_ak_occupancy.wrcrd uncore interconnect AK Egress (to CMS) Occupancy; Write Credit Request event=0x12,umask=0x10 01 unc_m2m_txc_ak_sideband.rd uncore interconnect AK Egress (to CMS) Sideband event=0x6b,umask=1 01 unc_m2m_txc_ak_sideband.wr uncore interconnect AK Egress (to CMS) Sideband event=0x6b,umask=2 01 unc_m2m_txc_bl.drs_cache uncore interconnect Outbound DRS Ring Transactions to Cache; Data to Cache event=0x40,umask=1 01 unc_m2m_txc_bl.drs_core uncore interconnect Outbound DRS Ring Transactions to Cache; Data to Core event=0x40,umask=2 01 unc_m2m_txc_bl.drs_upi uncore interconnect Outbound DRS Ring Transactions to Cache; Data to QPI event=0x40,umask=4 01 unc_m2m_txc_bl_credits_acquired.cms0 uncore interconnect BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side event=0x19,umask=1 01 unc_m2m_txc_bl_credits_acquired.cms1 uncore interconnect BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side event=0x19,umask=2 01 unc_m2m_txc_bl_credit_occupancy.cms0 uncore interconnect BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side event=0x1a,umask=1 01 unc_m2m_txc_bl_credit_occupancy.cms1 uncore interconnect BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side event=0x1a,umask=2 01 unc_m2m_txc_bl_cycles_full.all uncore interconnect BL Egress (to CMS) Full; All event=0x18,umask=3 01 unc_m2m_txc_bl_cycles_full.cms0 uncore interconnect BL Egress (to CMS) Full; Common Mesh Stop - Near Side event=0x18,umask=1 01 unc_m2m_txc_bl_cycles_full.cms1 uncore interconnect BL Egress (to CMS) Full; Common Mesh Stop - Far Side event=0x18,umask=2 01 unc_m2m_txc_bl_cycles_ne.all uncore interconnect BL Egress (to CMS) Not Empty; All event=0x17,umask=3 01 unc_m2m_txc_bl_cycles_ne.cms0 uncore interconnect BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side event=0x17,umask=1 01 unc_m2m_txc_bl_cycles_ne.cms1 uncore interconnect BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side event=0x17,umask=2 01 unc_m2m_txc_bl_inserts.all uncore interconnect BL Egress (to CMS) Allocations; All event=0x15,umask=3 01 unc_m2m_txc_bl_inserts.cms0 uncore interconnect BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side event=0x15,umask=1 01 unc_m2m_txc_bl_inserts.cms1 uncore interconnect BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side event=0x15,umask=2 01 unc_m2m_txc_bl_no_credit_cycles.cms0 uncore interconnect Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x1b,umask=1 01 unc_m2m_txc_bl_no_credit_cycles.cms1 uncore interconnect Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x1b,umask=2 01 unc_m2m_txc_bl_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x1c,umask=1 01 unc_m2m_txc_bl_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x1c,umask=2 01 unc_m2m_txc_bl_occupancy.all uncore interconnect BL Egress (to CMS) Occupancy; All event=0x16,umask=3 01 unc_m2m_txc_bl_occupancy.cms0 uncore interconnect BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side event=0x16,umask=1 01 unc_m2m_txc_bl_occupancy.cms1 uncore interconnect BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side event=0x16,umask=2 01 unc_m2m_txr_horz_ads_used.ad_bnc uncore interconnect CMS Horizontal ADS Used; AD - Bounce event=0x9d,umask=1 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used; AD - Credit event=0x9d,umask=0x10 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.ak_bnc uncore interconnect CMS Horizontal ADS Used; AK - Bounce event=0x9d,umask=2 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_bnc uncore interconnect CMS Horizontal ADS Used; BL - Bounce event=0x9d,umask=4 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used; BL - Credit event=0x9d,umask=0x40 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_bnc uncore interconnect CMS Horizontal Bypass Used; AD - Bounce event=0x9f,umask=1 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used; AD - Credit event=0x9f,umask=0x10 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ak_bnc uncore interconnect CMS Horizontal Bypass Used; AK - Bounce event=0x9f,umask=2 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_bnc uncore interconnect CMS Horizontal Bypass Used; BL - Bounce event=0x9f,umask=4 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used; BL - Credit event=0x9f,umask=0x40 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.iv_bnc uncore interconnect CMS Horizontal Bypass Used; IV - Bounce event=0x9f,umask=8 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_cycles_full.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Bounce event=0x96,umask=1 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Credit event=0x96,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AK - Bounce event=0x96,umask=2 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Bounce event=0x96,umask=4 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Credit event=0x96,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; IV - Bounce event=0x96,umask=8 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce event=0x97,umask=1 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit event=0x97,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce event=0x97,umask=2 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce event=0x97,umask=4 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit event=0x97,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce event=0x97,umask=8 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_bnc uncore interconnect CMS Horizontal Egress Inserts; AD - Bounce event=0x95,umask=1 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts; AD - Credit event=0x95,umask=0x10 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ak_bnc uncore interconnect CMS Horizontal Egress Inserts; AK - Bounce event=0x95,umask=2 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_bnc uncore interconnect CMS Horizontal Egress Inserts; BL - Bounce event=0x95,umask=4 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts; BL - Credit event=0x95,umask=0x40 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.iv_bnc uncore interconnect CMS Horizontal Egress Inserts; IV - Bounce event=0x95,umask=8 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_nack.ad_bnc uncore interconnect CMS Horizontal Egress NACKs; AD - Bounce event=0x99,umask=1 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs; AD - Credit event=0x99,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ak_bnc uncore interconnect CMS Horizontal Egress NACKs; AK - Bounce event=0x99,umask=2 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_bnc uncore interconnect CMS Horizontal Egress NACKs; BL - Bounce event=0x99,umask=4 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs; BL - Credit event=0x99,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.iv_bnc uncore interconnect CMS Horizontal Egress NACKs; IV - Bounce event=0x99,umask=8 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_occupancy.ad_bnc uncore interconnect CMS Horizontal Egress Occupancy; AD - Bounce event=0x94,umask=1 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy; AD - Credit event=0x94,umask=0x10 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ak_bnc uncore interconnect CMS Horizontal Egress Occupancy; AK - Bounce event=0x94,umask=2 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_bnc uncore interconnect CMS Horizontal Egress Occupancy; BL - Bounce event=0x94,umask=4 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy; BL - Credit event=0x94,umask=0x40 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.iv_bnc uncore interconnect CMS Horizontal Egress Occupancy; IV - Bounce event=0x94,umask=8 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_starved.ad_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AD - Bounce event=0x9b,umask=1 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.ak_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AK - Bounce event=0x9b,umask=2 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.bl_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; BL - Bounce event=0x9b,umask=4 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.iv_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; IV - Bounce event=0x9b,umask=8 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9c,umask=1 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9c,umask=0x10 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9c,umask=2 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9c,umask=0x20 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9c,umask=4 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9c,umask=0x40 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9e,umask=1 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9e,umask=0x10 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9e,umask=2 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9e,umask=0x20 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9e,umask=4 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9e,umask=0x40 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.iv uncore interconnect CMS Vertical ADS Used; IV event=0x9e,umask=8 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_cycles_full.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0 event=0x92,umask=1 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_full.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1 event=0x92,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_cycles_full.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0 event=0x92,umask=2 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_full.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1 event=0x92,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_full.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0 event=0x92,umask=4 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_full.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1 event=0x92,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_full.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Full; IV event=0x92,umask=8 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_cycles_ne.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0 event=0x93,umask=1 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_ne.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1 event=0x93,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_cycles_ne.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0 event=0x93,umask=2 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_ne.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1 event=0x93,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_ne.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0 event=0x93,umask=4 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_ne.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1 event=0x93,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_ne.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; IV event=0x93,umask=8 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_inserts.ad_ag0 uncore interconnect CMS Vert Egress Allocations; AD - Agent 0 event=0x91,umask=1 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_inserts.ad_ag1 uncore interconnect CMS Vert Egress Allocations; AD - Agent 1 event=0x91,umask=0x10 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_inserts.ak_ag0 uncore interconnect CMS Vert Egress Allocations; AK - Agent 0 event=0x91,umask=2 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_inserts.ak_ag1 uncore interconnect CMS Vert Egress Allocations; AK - Agent 1 event=0x91,umask=0x20 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_inserts.bl_ag0 uncore interconnect CMS Vert Egress Allocations; BL - Agent 0 event=0x91,umask=4 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_inserts.bl_ag1 uncore interconnect CMS Vert Egress Allocations; BL - Agent 1 event=0x91,umask=0x40 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_inserts.iv uncore interconnect CMS Vert Egress Allocations; IV event=0x91,umask=8 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_nack.ad_ag0 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 0 event=0x98,umask=1 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.ad_ag1 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 1 event=0x98,umask=0x10 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.ak_ag0 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 0 event=0x98,umask=2 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.ak_ag1 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 1 event=0x98,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.bl_ag0 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 0 event=0x98,umask=4 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.bl_ag1 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 1 event=0x98,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.iv uncore interconnect CMS Vertical Egress NACKs; IV event=0x98,umask=8 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_occupancy.ad_ag0 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 0 event=0x90,umask=1 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_occupancy.ad_ag1 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 1 event=0x90,umask=0x10 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_occupancy.ak_ag0 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 0 event=0x90,umask=2 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_occupancy.ak_ag1 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 1 event=0x90,umask=0x20 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_occupancy.bl_ag0 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 0 event=0x90,umask=4 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_occupancy.bl_ag1 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 1 event=0x90,umask=0x40 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_occupancy.iv uncore interconnect CMS Vert Egress Occupancy; IV event=0x90,umask=8 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_starved.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 0 event=0x9a,umask=1 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 1 event=0x9a,umask=0x10 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 0 event=0x9a,umask=2 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 1 event=0x9a,umask=0x20 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 0 event=0x9a,umask=4 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 1 event=0x9a,umask=0x40 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.iv uncore interconnect CMS Vertical Egress Injection Starvation; IV event=0x9a,umask=8 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use; Down and Even event=0xa6,umask=4 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use; Down and Odd event=0xa6,umask=8 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use; Up and Even event=0xa6,umask=1 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use; Up and Odd event=0xa6,umask=2 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use; Down and Even event=0xa8,umask=4 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use; Down and Odd event=0xa8,umask=8 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use; Up and Even event=0xa8,umask=1 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use; Up and Odd event=0xa8,umask=2 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use; Down and Even event=0xaa,umask=4 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use; Down and Odd event=0xaa,umask=8 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use; Up and Even event=0xaa,umask=1 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use; Up and Odd event=0xaa,umask=2 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use; Down event=0xac,umask=4 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use; Up event=0xac,umask=1 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_wpq_cycles_no_reg_credits.chn0 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0 event=0x4d,umask=1 11 unc_m2m_wpq_cycles_no_reg_credits.chn1 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1 event=0x4d,umask=2 11 unc_m2m_wpq_cycles_no_reg_credits.chn2 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2 event=0x4d,umask=4 11 unc_m2m_wpq_cycles_reg_credits.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0 event=0x4d,umask=1 01 unc_m2m_wpq_cycles_reg_credits.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1 event=0x4d,umask=2 01 unc_m2m_wpq_cycles_reg_credits.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2 event=0x4d,umask=4 01 unc_m2m_wpq_cycles_spec_credits.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special; Channel 0 event=0x4e,umask=1 01 unc_m2m_wpq_cycles_spec_credits.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special; Channel 1 event=0x4e,umask=2 01 unc_m2m_wpq_cycles_spec_credits.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special; Channel 2 event=0x4e,umask=4 01 unc_m2m_write_tracker_cycles_full.ch0 uncore interconnect Write Tracker Cycles Full; Channel 0 event=0x4a,umask=1 01 unc_m2m_write_tracker_cycles_full.ch1 uncore interconnect Write Tracker Cycles Full; Channel 1 event=0x4a,umask=2 01 unc_m2m_write_tracker_cycles_full.ch2 uncore interconnect Write Tracker Cycles Full; Channel 2 event=0x4a,umask=4 01 unc_m2m_write_tracker_cycles_ne.ch0 uncore interconnect Write Tracker Cycles Not Empty; Channel 0 event=0x4b,umask=1 01 unc_m2m_write_tracker_cycles_ne.ch1 uncore interconnect Write Tracker Cycles Not Empty; Channel 1 event=0x4b,umask=2 01 unc_m2m_write_tracker_cycles_ne.ch2 uncore interconnect Write Tracker Cycles Not Empty; Channel 2 event=0x4b,umask=4 01 unc_m2m_write_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts; Channel 0 event=0x61,umask=1 01 unc_m2m_write_tracker_inserts.ch1 uncore interconnect Write Tracker Inserts; Channel 1 event=0x61,umask=2 01 unc_m2m_write_tracker_inserts.ch2 uncore interconnect Write Tracker Inserts; Channel 2 event=0x61,umask=4 01 unc_m2m_write_tracker_occupancy.ch0 uncore interconnect Write Tracker Occupancy; Channel 0 event=0x60,umask=1 01 unc_m2m_write_tracker_occupancy.ch1 uncore interconnect Write Tracker Occupancy; Channel 1 event=0x60,umask=2 01 unc_m2m_write_tracker_occupancy.ch2 uncore interconnect Write Tracker Occupancy; Channel 2 event=0x60,umask=4 01 uncore_m3upi unc_m3upi_ag0_ad_crd_acquired.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 0 event=0x80,umask=1 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 1 event=0x80,umask=2 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 2 event=0x80,umask=4 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 3 event=0x80,umask=8 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 4 event=0x80,umask=0x10 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 5 event=0x80,umask=0x20 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 0 event=0x82,umask=1 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 1 event=0x82,umask=2 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 2 event=0x82,umask=4 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 3 event=0x82,umask=8 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 4 event=0x82,umask=0x10 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 5 event=0x82,umask=0x20 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 0 event=0x88,umask=1 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 1 event=0x88,umask=2 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 2 event=0x88,umask=4 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 3 event=0x88,umask=8 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 4 event=0x88,umask=0x10 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 5 event=0x88,umask=0x20 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 0 event=0x8a,umask=1 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 1 event=0x8a,umask=2 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 2 event=0x8a,umask=4 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 3 event=0x8a,umask=8 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 4 event=0x8a,umask=0x10 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 5 event=0x8a,umask=0x20 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 0 event=0x84,umask=1 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 1 event=0x84,umask=2 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 2 event=0x84,umask=4 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 3 event=0x84,umask=8 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 4 event=0x84,umask=0x10 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 5 event=0x84,umask=0x20 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 0 event=0x86,umask=1 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 1 event=0x86,umask=2 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 2 event=0x86,umask=4 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 3 event=0x86,umask=8 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 4 event=0x86,umask=0x10 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 5 event=0x86,umask=0x20 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 0 event=0x8e,umask=1 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 1 event=0x8e,umask=2 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 2 event=0x8e,umask=4 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 3 event=0x8e,umask=8 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 4 event=0x8e,umask=0x10 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 5 event=0x8e,umask=0x20 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 0 event=0x8c,umask=1 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 1 event=0x8c,umask=2 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 2 event=0x8c,umask=4 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 3 event=0x8c,umask=8 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 4 event=0x8c,umask=0x10 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 5 event=0x8c,umask=0x20 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_cha_ad_credits_empty.req uncore interconnect CBox AD Credits Empty; Requests event=0x22,umask=4 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.snp uncore interconnect CBox AD Credits Empty; Snoops event=0x22,umask=8 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.vna uncore interconnect CBox AD Credits Empty; VNA Messages event=0x22,umask=1 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.wb uncore interconnect CBox AD Credits Empty; Writebacks event=0x22,umask=2 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_clockticks uncore interconnect Number of uclks in domain event=1 01 Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_m3upi_cms_clockticks uncore interconnect CMS Clockticks event=0xc0 01 unc_m3upi_d2c_sent uncore interconnect D2C Sent event=0x2b 01 Count cases BL sends direct to core unc_m3upi_d2u_sent uncore interconnect D2U Sent event=0x2a 01 Cases where SMI3 sends D2U command unc_m3upi_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements; Down event=0xae,umask=4 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements; Up event=0xae,umask=1 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_fast_asserted.horz uncore interconnect FaST wire asserted; Horizontal event=0xa5,umask=2 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_m3upi_fast_asserted.vert uncore interconnect FaST wire asserted; Vertical event=0xa5,umask=1 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_m3upi_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use; Left and Even event=0xa7,umask=1 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use; Left and Odd event=0xa7,umask=2 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use; Right and Even event=0xa7,umask=4 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use; Right and Odd event=0xa7,umask=8 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use; Left and Even event=0xa9,umask=1 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use; Left and Odd event=0xa9,umask=2 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use; Right and Even event=0xa9,umask=4 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use; Right and Odd event=0xa9,umask=8 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use; Left and Even event=0xab,umask=1 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use; Left and Odd event=0xab,umask=2 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use; Right and Even event=0xab,umask=4 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use; Right and Odd event=0xab,umask=8 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use; Left event=0xad,umask=1 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use; Right event=0xad,umask=4 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_m2_bl_credits_empty.iio0_iio1_ncb uncore interconnect M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) event=0x23,umask=1 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio2_ncb uncore interconnect M2 BL Credits Empty; IIO2 event=0x23,umask=2 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio3_ncb uncore interconnect M2 BL Credits Empty; IIO3 event=0x23,umask=4 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio4_ncb uncore interconnect M2 BL Credits Empty; IIO4 event=0x23,umask=8 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio5_ncb uncore interconnect M2 BL Credits Empty; IIO5 event=0x23,umask=0x10 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs uncore interconnect M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together event=0x23,umask=0x20 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs_sel uncore interconnect M2 BL Credits Empty; Selected M2p BL NCS credits event=0x23,umask=0x40 01 No vn0 and vna credits available to send to M2 unc_m3upi_multi_slot_rcvd.ad_slot0 uncore interconnect Multi Slot Flit Received; AD - Slot 0 event=0x3e,umask=1 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot1 uncore interconnect Multi Slot Flit Received; AD - Slot 1 event=0x3e,umask=2 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot2 uncore interconnect Multi Slot Flit Received; AD - Slot 2 event=0x3e,umask=4 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot0 uncore interconnect Multi Slot Flit Received; AK - Slot 0 event=0x3e,umask=0x10 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot2 uncore interconnect Multi Slot Flit Received; AK - Slot 2 event=0x3e,umask=0x20 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.bl_slot0 uncore interconnect Multi Slot Flit Received; BL - Slot 0 event=0x3e,umask=8 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring.; AD event=0xa1,umask=1 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring.; AK event=0xa1,umask=2 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring.; BL event=0xa1,umask=4 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring.; IV event=0xa1,umask=8 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring.; AD event=0xa0,umask=1 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring.; Acknowledgements to core event=0xa0,umask=2 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring.; Data Responses to core event=0xa0,umask=4 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring.; Snoops of processor's cache event=0xa0,umask=8 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring; AD event=0xa3,umask=1 01 unc_m3upi_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring; AK event=0xa3,umask=2 01 unc_m3upi_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1 event=0xa3,umask=0x20 01 unc_m3upi_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring; BL event=0xa3,umask=4 01 unc_m3upi_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring; IV event=0xa3,umask=8 01 unc_m3upi_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring; AD event=0xa2,umask=1 01 unc_m3upi_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring; Acknowledgements to core event=0xa2,umask=2 01 unc_m3upi_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring; Data Responses to core event=0xa2,umask=4 01 unc_m3upi_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring; Snoops of processor's cache event=0xa2,umask=8 01 unc_m3upi_ring_src_thrtl uncore interconnect Source Throttle event=0xa4 01 unc_m3upi_rxc_arb_lost_vn0.ad_req uncore interconnect Lost Arb for VN0; REQ on AD event=0x4b,umask=1 01 VN0 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn0.ad_rsp uncore interconnect Lost Arb for VN0; RSP on AD event=0x4b,umask=4 01 VN0 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.ad_snp uncore interconnect Lost Arb for VN0; SNP on AD event=0x4b,umask=2 01 VN0 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn0.bl_ncb uncore interconnect Lost Arb for VN0; NCB on BL event=0x4b,umask=0x20 01 VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn0.bl_ncs uncore interconnect Lost Arb for VN0; NCS on BL event=0x4b,umask=0x40 01 VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn0.bl_rsp uncore interconnect Lost Arb for VN0; RSP on BL event=0x4b,umask=8 01 VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.bl_wb uncore interconnect Lost Arb for VN0; WB on BL event=0x4b,umask=0x10 01 VN0 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_lost_vn1.ad_req uncore interconnect Lost Arb for VN1; REQ on AD event=0x4c,umask=1 01 VN1 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn1.ad_rsp uncore interconnect Lost Arb for VN1; RSP on AD event=0x4c,umask=4 01 VN1 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.ad_snp uncore interconnect Lost Arb for VN1; SNP on AD event=0x4c,umask=2 01 VN1 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn1.bl_ncb uncore interconnect Lost Arb for VN1; NCB on BL event=0x4c,umask=0x20 01 VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn1.bl_ncs uncore interconnect Lost Arb for VN1; NCS on BL event=0x4c,umask=0x40 01 VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn1.bl_rsp uncore interconnect Lost Arb for VN1; RSP on BL event=0x4c,umask=8 01 VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.bl_wb uncore interconnect Lost Arb for VN1; WB on BL event=0x4c,umask=0x10 01 VN1 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_misc.adbl_parallel_win uncore interconnect Arb Miscellaneous; AD, BL Parallel Win event=0x4d,umask=0x40 01 AD and BL messages won arbitration concurrently / in parallel unc_m3upi_rxc_arb_misc.no_prog_ad_vn0 uncore interconnect Arb Miscellaneous; No Progress on Pending AD VN0 event=0x4d,umask=4 01 Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_ad_vn1 uncore interconnect Arb Miscellaneous; No Progress on Pending AD VN1 event=0x4d,umask=8 01 Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn0 uncore interconnect Arb Miscellaneous; No Progress on Pending BL VN0 event=0x4d,umask=0x10 01 Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn1 uncore interconnect Arb Miscellaneous; No Progress on Pending BL VN1 event=0x4d,umask=0x20 01 Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.par_bias_vn0 uncore interconnect Arb Miscellaneous; Parallel Bias to VN0 event=0x4d,umask=1 01 VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl unc_m3upi_rxc_arb_misc.par_bias_vn1 uncore interconnect Arb Miscellaneous; Parallel Bias to VN1 event=0x4d,umask=2 01 VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl unc_m3upi_rxc_arb_noad_req_vn0.ad_req uncore interconnect Can't Arb for VN0; REQ on AD event=0x49,umask=1 01 VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noad_req_vn0.ad_rsp uncore interconnect Can't Arb for VN0; RSP on AD event=0x49,umask=4 01 VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn0.ad_snp uncore interconnect Can't Arb for VN0; SNP on AD event=0x49,umask=2 01 VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_noad_req_vn0.bl_ncb uncore interconnect Can't Arb for VN0; NCB on BL event=0x49,umask=0x20 01 VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_noad_req_vn0.bl_ncs uncore interconnect Can't Arb for VN0; NCS on BL event=0x49,umask=0x40 01 VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noad_req_vn0.bl_rsp uncore interconnect Can't Arb for VN0; RSP on BL event=0x49,umask=8 01 VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn0.bl_wb uncore interconnect Can't Arb for VN0; WB on BL event=0x49,umask=0x10 01 VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_noad_req_vn1.ad_req uncore interconnect Can't Arb for VN1; REQ on AD event=0x4a,umask=1 01 VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noad_req_vn1.ad_rsp uncore interconnect Can't Arb for VN1; RSP on AD event=0x4a,umask=4 01 VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn1.ad_snp uncore interconnect Can't Arb for VN1; SNP on AD event=0x4a,umask=2 01 VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_noad_req_vn1.bl_ncb uncore interconnect Can't Arb for VN1; NCB on BL event=0x4a,umask=0x20 01 VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_noad_req_vn1.bl_ncs uncore interconnect Can't Arb for VN1; NCS on BL event=0x4a,umask=0x40 01 VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noad_req_vn1.bl_rsp uncore interconnect Can't Arb for VN1; RSP on BL event=0x4a,umask=8 01 VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn1.bl_wb uncore interconnect Can't Arb for VN1; WB on BL event=0x4a,umask=0x10 01 VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_nocred_vn0.ad_req uncore interconnect No Credits to Arb for VN0; REQ on AD event=0x47,umask=1 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocred_vn0.ad_rsp uncore interconnect No Credits to Arb for VN0; RSP on AD event=0x47,umask=4 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn0.ad_snp uncore interconnect No Credits to Arb for VN0; SNP on AD event=0x47,umask=2 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocred_vn0.bl_ncb uncore interconnect No Credits to Arb for VN0; NCB on BL event=0x47,umask=0x20 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_nocred_vn0.bl_ncs uncore interconnect No Credits to Arb for VN0; NCS on BL event=0x47,umask=0x40 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocred_vn0.bl_rsp uncore interconnect No Credits to Arb for VN0; RSP on BL event=0x47,umask=8 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn0.bl_wb uncore interconnect No Credits to Arb for VN0; WB on BL event=0x47,umask=0x10 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_nocred_vn1.ad_req uncore interconnect No Credits to Arb for VN1; REQ on AD event=0x48,umask=1 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocred_vn1.ad_rsp uncore interconnect No Credits to Arb for VN1; RSP on AD event=0x48,umask=4 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn1.ad_snp uncore interconnect No Credits to Arb for VN1; SNP on AD event=0x48,umask=2 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocred_vn1.bl_ncb uncore interconnect No Credits to Arb for VN1; NCB on BL event=0x48,umask=0x20 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_nocred_vn1.bl_ncs uncore interconnect No Credits to Arb for VN1; NCS on BL event=0x48,umask=0x40 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocred_vn1.bl_rsp uncore interconnect No Credits to Arb for VN1; RSP on BL event=0x48,umask=8 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn1.bl_wb uncore interconnect No Credits to Arb for VN1; WB on BL event=0x48,umask=0x10 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_bypassed.ad_s0_bl_arb uncore interconnect Ingress Queue Bypasses; AD to Slot 0 on BL Arb event=0x40,umask=2 01 Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration unc_m3upi_rxc_bypassed.ad_s0_idle uncore interconnect Ingress Queue Bypasses; AD to Slot 0 on Idle event=0x40,umask=1 01 Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle unc_m3upi_rxc_bypassed.ad_s1_bl_slot uncore interconnect Ingress Queue Bypasses; AD + BL to Slot 1 event=0x40,umask=4 01 Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit unc_m3upi_rxc_bypassed.ad_s2_bl_slot uncore interconnect Ingress Queue Bypasses; AD + BL to Slot 2 event=0x40,umask=8 01 Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit unc_m3upi_rxc_collision_vn0.ad_req uncore interconnect VN0 message lost contest for flit; REQ on AD event=0x50,umask=1 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_collision_vn0.ad_rsp uncore interconnect VN0 message lost contest for flit; RSP on AD event=0x50,umask=4 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn0.ad_snp uncore interconnect VN0 message lost contest for flit; SNP on AD event=0x50,umask=2 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_collision_vn0.bl_ncb uncore interconnect VN0 message lost contest for flit; NCB on BL event=0x50,umask=0x20 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_collision_vn0.bl_ncs uncore interconnect VN0 message lost contest for flit; NCS on BL event=0x50,umask=0x40 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_collision_vn0.bl_rsp uncore interconnect VN0 message lost contest for flit; RSP on BL event=0x50,umask=8 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn0.bl_wb uncore interconnect VN0 message lost contest for flit; WB on BL event=0x50,umask=0x10 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_collision_vn1.ad_req uncore interconnect VN1 message lost contest for flit; REQ on AD event=0x51,umask=1 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_collision_vn1.ad_rsp uncore interconnect VN1 message lost contest for flit; RSP on AD event=0x51,umask=4 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn1.ad_snp uncore interconnect VN1 message lost contest for flit; SNP on AD event=0x51,umask=2 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_collision_vn1.bl_ncb uncore interconnect VN1 message lost contest for flit; NCB on BL event=0x51,umask=0x20 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_collision_vn1.bl_ncs uncore interconnect VN1 message lost contest for flit; NCS on BL event=0x51,umask=0x40 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_collision_vn1.bl_rsp uncore interconnect VN1 message lost contest for flit; RSP on BL event=0x51,umask=8 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn1.bl_wb uncore interconnect VN1 message lost contest for flit; WB on BL event=0x51,umask=0x10 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_crd_misc.any_bgf_fifo uncore interconnect Miscellaneous Credit Events; Any In BGF FIFO event=0x60,umask=1 01 Indication that at least one packet (flit) is in the bgf (fifo only) unc_m3upi_rxc_crd_misc.any_bgf_path uncore interconnect Miscellaneous Credit Events; Any in BGF Path event=0x60,umask=2 01 Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo) unc_m3upi_rxc_crd_misc.no_d2k_for_arb uncore interconnect Miscellaneous Credit Events; No D2K For Arb event=0x60,umask=4 01 VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits unc_m3upi_rxc_crd_occ.d2k_crd uncore interconnect Credit Occupancy; D2K Credits event=0x61,umask=0x10 01 D2K completion fifo credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.flits_in_fifo uncore interconnect Credit Occupancy; Packets in BGF FIFO event=0x61,umask=2 01 Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo unc_m3upi_rxc_crd_occ.flits_in_path uncore interconnect Credit Occupancy; Packets in BGF Path event=0x61,umask=4 01 Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo) unc_m3upi_rxc_crd_occ.p1p_fifo uncore interconnect Credit Occupancy event=0x61,umask=0x40 01 count of bl messages in pump-1-pending state, in completion fifo only unc_m3upi_rxc_crd_occ.p1p_total uncore interconnect Credit Occupancy event=0x61,umask=0x20 01 count of bl messages in pump-1-pending state, in marker table and in fifo unc_m3upi_rxc_crd_occ.txq_crd uncore interconnect Credit Occupancy; Transmit Credits event=0x61,umask=8 01 Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.vna_in_use uncore interconnect Credit Occupancy; VNA In Use event=0x61,umask=1 01 Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles unc_m3upi_rxc_cycles_ne_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD event=0x43,umask=1 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD event=0x43,umask=4 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD event=0x43,umask=2 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL event=0x43,umask=0x20 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL event=0x43,umask=0x40 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL event=0x43,umask=8 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL event=0x43,umask=0x10 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_cycles_ne_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD event=0x44,umask=1 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD event=0x44,umask=4 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD event=0x44,umask=2 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL event=0x44,umask=0x20 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL event=0x44,umask=0x40 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL event=0x44,umask=8 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL event=0x44,umask=0x10 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_flits_data_not_sent.all uncore interconnect Data Flit Not Sent; All event=0x57,umask=1 01 Data flit is ready for transmission but could not be sent unc_m3upi_rxc_flits_data_not_sent.no_bgf uncore interconnect Data Flit Not Sent; No BGF Credits event=0x57,umask=2 01 Data flit is ready for transmission but could not be sent unc_m3upi_rxc_flits_data_not_sent.no_txq uncore interconnect Data Flit Not Sent; No TxQ Credits event=0x57,umask=4 01 Data flit is ready for transmission but could not be sent unc_m3upi_rxc_flits_gen_bl.p0_wait uncore interconnect Generating BL Data Flit Sequence; Wait on Pump 0 event=0x59,umask=1 01 generating bl data flit sequence; waiting for data pump 0 unc_m3upi_rxc_flits_gen_bl.p1p_at_limit uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x10 01 pump-1-pending logic is at capacity (pending table plus completion fifo at limit) unc_m3upi_rxc_flits_gen_bl.p1p_busy uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=8 01 pump-1-pending logic is tracking at least one message unc_m3upi_rxc_flits_gen_bl.p1p_fifo_full uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x40 01 pump-1-pending completion fifo is full unc_m3upi_rxc_flits_gen_bl.p1p_hold_p0 uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x20 01 pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage unc_m3upi_rxc_flits_gen_bl.p1p_to_limbo uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=4 01 a bl message finished but is in limbo and moved to pump-1-pending logic unc_m3upi_rxc_flits_gen_bl.p1_wait uncore interconnect Generating BL Data Flit Sequence; Wait on Pump 1 event=0x59,umask=2 01 generating bl data flit sequence; waiting for data pump 1 unc_m3upi_rxc_flits_misc uncore interconnect UNC_M3UPI_RxC_FLITS_MISC event=0x5a 01 unc_m3upi_rxc_flits_sent.1_msg uncore interconnect Sent Header Flit; One Message event=0x56,umask=1 01 One message in flit; VNA or non-VNA flit unc_m3upi_rxc_flits_sent.1_msg_vnx uncore interconnect Sent Header Flit; One Message in non-VNA event=0x56,umask=8 01 One message in flit; non-VNA flit unc_m3upi_rxc_flits_sent.2_msgs uncore interconnect Sent Header Flit; Two Messages event=0x56,umask=2 01 Two messages in flit; VNA flit unc_m3upi_rxc_flits_sent.3_msgs uncore interconnect Sent Header Flit; Three Messages event=0x56,umask=4 01 Three messages in flit; VNA flit unc_m3upi_rxc_flits_sent.slots_1 uncore interconnect Sent Header Flit event=0x56,umask=0x10 01 unc_m3upi_rxc_flits_sent.slots_2 uncore interconnect Sent Header Flit event=0x56,umask=0x20 01 unc_m3upi_rxc_flits_sent.slots_3 uncore interconnect Sent Header Flit event=0x56,umask=0x40 01 unc_m3upi_rxc_flits_slot_bl.all uncore interconnect Slotting BL Message Into Header Flit; All event=0x58,umask=1 01 unc_m3upi_rxc_flits_slot_bl.need_data uncore interconnect Slotting BL Message Into Header Flit; Needs Data Flit event=0x58,umask=2 01 BL message requires data flit sequence unc_m3upi_rxc_flits_slot_bl.p0_wait uncore interconnect Slotting BL Message Into Header Flit; Wait on Pump 0 event=0x58,umask=4 01 Waiting for header pump 0 unc_m3upi_rxc_flits_slot_bl.p1_not_req uncore interconnect Slotting BL Message Into Header Flit; Don't Need Pump 1 event=0x58,umask=0x10 01 Header pump 1 is not required for flit unc_m3upi_rxc_flits_slot_bl.p1_not_req_but_bubble uncore interconnect Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble event=0x58,umask=0x20 01 Header pump 1 is not required for flit but flit transmission delayed unc_m3upi_rxc_flits_slot_bl.p1_not_req_not_avail uncore interconnect Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail event=0x58,umask=0x40 01 Header pump 1 is not required for flit and not available unc_m3upi_rxc_flits_slot_bl.p1_wait uncore interconnect Slotting BL Message Into Header Flit; Wait on Pump 1 event=0x58,umask=8 01 Waiting for header pump 1 unc_m3upi_rxc_flit_gen_hdr1.accum uncore interconnect Flit Gen - Header 1; Accumulate event=0x53,umask=1 01 Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles unc_m3upi_rxc_flit_gen_hdr1.accum_read uncore interconnect Flit Gen - Header 1; Accumulate Ready event=0x53,umask=2 01 Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit unc_m3upi_rxc_flit_gen_hdr1.accum_wasted uncore interconnect Flit Gen - Header 1; Accumulate Wasted event=0x53,umask=4 01 Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted unc_m3upi_rxc_flit_gen_hdr1.ahead_blocked uncore interconnect Flit Gen - Header 1; Run-Ahead - Blocked event=0x53,umask=8 01 Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked unc_m3upi_rxc_flit_gen_hdr1.ahead_msg uncore interconnect Flit Gen - Header 1; Run-Ahead - Message event=0x53,umask=0x10 01 Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit unc_m3upi_rxc_flit_gen_hdr1.par uncore interconnect Flit Gen - Header 1; Parallel Ok event=0x53,umask=0x20 01 Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr1.par_flit uncore interconnect Flit Gen - Header 1; Parallel Flit Finished event=0x53,umask=0x80 01 Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr1.par_msg uncore interconnect Flit Gen - Header 1; Parallel Message event=0x53,umask=0x40 01 Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.rmstall uncore interconnect Flit Gen - Header 2; Rate-matching Stall event=0x54,umask=1 01 Events related to Header Flit Generation - Set 2; Rate-matching stall injected unc_m3upi_rxc_flit_gen_hdr2.rmstall_nomsg uncore interconnect Flit Gen - Header 2; Rate-matching Stall - No Message event=0x54,umask=2 01 Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle unc_m3upi_rxc_flit_not_sent.all uncore interconnect Header Not Sent; All event=0x55,umask=1 01 header flit is ready for transmission but could not be sent unc_m3upi_rxc_flit_not_sent.no_bgf_crd uncore interconnect Header Not Sent; No BGF Credits event=0x55,umask=2 01 header flit is ready for transmission but could not be sent; No BGF credits available unc_m3upi_rxc_flit_not_sent.no_bgf_no_msg uncore interconnect Header Not Sent; No BGF Credits + No Extra Message Slotted event=0x55,umask=8 01 header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit unc_m3upi_rxc_flit_not_sent.no_txq_crd uncore interconnect Header Not Sent; No TxQ Credits event=0x55,umask=4 01 header flit is ready for transmission but could not be sent; No TxQ credits available unc_m3upi_rxc_flit_not_sent.no_txq_no_msg uncore interconnect Header Not Sent; No TxQ Credits + No Extra Message Slotted event=0x55,umask=0x10 01 header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit unc_m3upi_rxc_flit_not_sent.one_taken uncore interconnect Header Not Sent; Sent - One Slot Taken event=0x55,umask=0x20 01 header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free) unc_m3upi_rxc_flit_not_sent.three_taken uncore interconnect Header Not Sent; Sent - Three Slots Taken event=0x55,umask=0x80 01 header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free) unc_m3upi_rxc_flit_not_sent.two_taken uncore interconnect Header Not Sent; Sent - Two Slots Taken event=0x55,umask=0x40 01 header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free) unc_m3upi_rxc_held.cant_slot_ad uncore interconnect Message Held; Can't Slot AD event=0x52,umask=0x40 01 some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.cant_slot_bl uncore interconnect Message Held; Can't Slot BL event=0x52,umask=0x80 01 some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_ad_lost uncore interconnect Message Held; Parallel AD Lost event=0x52,umask=0x10 01 some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_attempt uncore interconnect Message Held; Parallel Attempt event=0x52,umask=4 01 ad and bl messages attempted to slot into the same flit in parallel unc_m3upi_rxc_held.parallel_bl_lost uncore interconnect Message Held; Parallel BL Lost event=0x52,umask=0x20 01 some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_success uncore interconnect Message Held; Parallel Success event=0x52,umask=8 01 ad and bl messages were actually slotted into the same flit in parallel unc_m3upi_rxc_held.vn0 uncore interconnect Message Held; VN0 event=0x52,umask=1 01 vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit unc_m3upi_rxc_held.vn1 uncore interconnect Message Held; VN1 event=0x52,umask=2 01 vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit unc_m3upi_rxc_inserts_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; REQ on AD event=0x41,umask=1 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; RSP on AD event=0x41,umask=4 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; SNP on AD event=0x41,umask=2 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; NCB on BL event=0x41,umask=0x20 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; NCS on BL event=0x41,umask=0x40 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; RSP on BL event=0x41,umask=8 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; WB on BL event=0x41,umask=0x10 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_inserts_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; REQ on AD event=0x42,umask=1 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; RSP on AD event=0x42,umask=4 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; SNP on AD event=0x42,umask=2 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; NCB on BL event=0x42,umask=0x20 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; NCS on BL event=0x42,umask=0x40 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; RSP on BL event=0x42,umask=8 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; WB on BL event=0x42,umask=0x10 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD event=0x45,umask=1 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD event=0x45,umask=4 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD event=0x45,umask=2 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL event=0x45,umask=0x20 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL event=0x45,umask=0x40 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL event=0x45,umask=8 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; WB on BL event=0x45,umask=0x10 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD event=0x46,umask=1 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD event=0x46,umask=4 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD event=0x46,umask=2 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL event=0x46,umask=0x20 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL event=0x46,umask=0x40 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL event=0x46,umask=8 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; WB on BL event=0x46,umask=0x10 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_packing_miss_vn0.ad_req uncore interconnect VN0 message can't slot into flit; REQ on AD event=0x4e,umask=1 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn0.ad_rsp uncore interconnect VN0 message can't slot into flit; RSP on AD event=0x4e,umask=4 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.ad_snp uncore interconnect VN0 message can't slot into flit; SNP on AD event=0x4e,umask=2 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn0.bl_ncb uncore interconnect VN0 message can't slot into flit; NCB on BL event=0x4e,umask=0x20 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn0.bl_ncs uncore interconnect VN0 message can't slot into flit; NCS on BL event=0x4e,umask=0x40 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn0.bl_rsp uncore interconnect VN0 message can't slot into flit; RSP on BL event=0x4e,umask=8 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.bl_wb uncore interconnect VN0 message can't slot into flit; WB on BL event=0x4e,umask=0x10 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_packing_miss_vn1.ad_req uncore interconnect VN1 message can't slot into flit; REQ on AD event=0x4f,umask=1 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn1.ad_rsp uncore interconnect VN1 message can't slot into flit; RSP on AD event=0x4f,umask=4 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.ad_snp uncore interconnect VN1 message can't slot into flit; SNP on AD event=0x4f,umask=2 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn1.bl_ncb uncore interconnect VN1 message can't slot into flit; NCB on BL event=0x4f,umask=0x20 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn1.bl_ncs uncore interconnect VN1 message can't slot into flit; NCS on BL event=0x4f,umask=0x40 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn1.bl_rsp uncore interconnect VN1 message can't slot into flit; RSP on BL event=0x4f,umask=8 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.bl_wb uncore interconnect VN1 message can't slot into flit; WB on BL event=0x4f,umask=0x10 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_smi3_pftch.arb_lost uncore interconnect SMI3 Prefetch Messages; Lost Arbitration event=0x62,umask=2 01 unc_m3upi_rxc_smi3_pftch.arrived uncore interconnect SMI3 Prefetch Messages; Arrived event=0x62,umask=1 01 unc_m3upi_rxc_smi3_pftch.drop_old uncore interconnect SMI3 Prefetch Messages; Dropped - Old event=0x62,umask=8 01 unc_m3upi_rxc_smi3_pftch.drop_wrap uncore interconnect SMI3 Prefetch Messages; Dropped - Wrap event=0x62,umask=0x10 01 Dropped because it was overwritten by new message while prefetch queue was full unc_m3upi_rxc_smi3_pftch.slotted uncore interconnect SMI3 Prefetch Messages; Slotted event=0x62,umask=4 01 unc_m3upi_rxc_vna_crd.any_in_use uncore interconnect Remote VNA Credits; Any In Use event=0x5b,umask=0x20 01 At least one remote vna credit is in use unc_m3upi_rxc_vna_crd.corrected uncore interconnect Remote VNA Credits; Corrected event=0x5b,umask=2 01 Number of remote vna credits corrected (local return) per cycle unc_m3upi_rxc_vna_crd.lt1 uncore interconnect Remote VNA Credits; Level < 1 event=0x5b,umask=4 01 Remote vna credit level is less than 1 (i.e. no vna credits available) unc_m3upi_rxc_vna_crd.lt4 uncore interconnect Remote VNA Credits; Level < 4 event=0x5b,umask=8 01 Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna unc_m3upi_rxc_vna_crd.lt5 uncore interconnect Remote VNA Credits; Level < 5 event=0x5b,umask=0x10 01 Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible unc_m3upi_rxc_vna_crd.used uncore interconnect Remote VNA Credits; Used event=0x5b,umask=1 01 Number of remote vna credits consumed per cycle unc_m3upi_rxr_busy_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb4,umask=1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb4,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb4,umask=4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb4,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_bypass.ad_bnc uncore interconnect Transgress Ingress Bypass; AD - Bounce event=0xb2,umask=1 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass; AD - Credit event=0xb2,umask=0x10 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ak_bnc uncore interconnect Transgress Ingress Bypass; AK - Bounce event=0xb2,umask=2 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_bnc uncore interconnect Transgress Ingress Bypass; BL - Bounce event=0xb2,umask=4 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass; BL - Credit event=0xb2,umask=0x40 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.iv_bnc uncore interconnect Transgress Ingress Bypass; IV - Bounce event=0xb2,umask=8 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_crd_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb3,umask=1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb3,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ak_bnc uncore interconnect Transgress Injection Starvation; AK - Bounce event=0xb3,umask=2 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb3,umask=4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb3,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation; IFV - Credit event=0xb3,umask=0x80 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.iv_bnc uncore interconnect Transgress Injection Starvation; IV - Bounce event=0xb3,umask=8 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_inserts.ad_bnc uncore interconnect Transgress Ingress Allocations; AD - Bounce event=0xb1,umask=1 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations; AD - Credit event=0xb1,umask=0x10 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ak_bnc uncore interconnect Transgress Ingress Allocations; AK - Bounce event=0xb1,umask=2 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_bnc uncore interconnect Transgress Ingress Allocations; BL - Bounce event=0xb1,umask=4 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations; BL - Credit event=0xb1,umask=0x40 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.iv_bnc uncore interconnect Transgress Ingress Allocations; IV - Bounce event=0xb1,umask=8 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_bnc uncore interconnect Transgress Ingress Occupancy; AD - Bounce event=0xb0,umask=1 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy; AD - Credit event=0xb0,umask=0x10 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ak_bnc uncore interconnect Transgress Ingress Occupancy; AK - Bounce event=0xb0,umask=2 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_bnc uncore interconnect Transgress Ingress Occupancy; BL - Bounce event=0xb0,umask=4 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy; BL - Credit event=0xb0,umask=0x40 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.iv_bnc uncore interconnect Transgress Ingress Occupancy; IV - Bounce event=0xb0,umask=8 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 0 event=0xd0,umask=1 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 1 event=0xd0,umask=2 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 2 event=0xd0,umask=4 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 3 event=0xd0,umask=8 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 4 event=0xd0,umask=0x10 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 5 event=0xd0,umask=0x20 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 0 event=0xd2,umask=1 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 1 event=0xd2,umask=2 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 2 event=0xd2,umask=4 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 3 event=0xd2,umask=8 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 4 event=0xd2,umask=0x10 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 5 event=0xd2,umask=0x20 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 0 event=0xd4,umask=1 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 1 event=0xd4,umask=2 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 2 event=0xd4,umask=4 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 3 event=0xd4,umask=8 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 4 event=0xd4,umask=0x10 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 5 event=0xd4,umask=0x20 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 0 event=0xd6,umask=1 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 1 event=0xd6,umask=2 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 2 event=0xd6,umask=4 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 3 event=0xd6,umask=8 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 4 event=0xd6,umask=0x10 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 5 event=0xd6,umask=0x20 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_txc_ad_arb_fail.vn0_req uncore interconnect Failed ARB for AD; VN0 REQ Messages event=0x30,umask=1 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_rsp uncore interconnect Failed ARB for AD; VN0 RSP Messages event=0x30,umask=4 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_snp uncore interconnect Failed ARB for AD; VN0 SNP Messages event=0x30,umask=2 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_wb uncore interconnect Failed ARB for AD; VN0 WB Messages event=0x30,umask=8 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_req uncore interconnect Failed ARB for AD; VN1 REQ Messages event=0x30,umask=0x10 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_rsp uncore interconnect Failed ARB for AD; VN1 RSP Messages event=0x30,umask=0x40 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_snp uncore interconnect Failed ARB for AD; VN1 SNP Messages event=0x30,umask=0x20 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_wb uncore interconnect Failed ARB for AD; VN1 WB Messages event=0x30,umask=0x80 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_flq_bypass.ad_slot0 uncore interconnect AD FlowQ Bypass event=0x2c,umask=1 01 Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot1 uncore interconnect AD FlowQ Bypass event=0x2c,umask=2 01 Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot2 uncore interconnect AD FlowQ Bypass event=0x2c,umask=4 01 Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.bl_early_rsp uncore interconnect AD FlowQ Bypass event=0x2c,umask=8 01 Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_cycles_ne.vn0_req uncore interconnect AD Flow Q Not Empty; VN0 REQ Messages event=0x27,umask=1 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_rsp uncore interconnect AD Flow Q Not Empty; VN0 RSP Messages event=0x27,umask=4 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_snp uncore interconnect AD Flow Q Not Empty; VN0 SNP Messages event=0x27,umask=2 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_wb uncore interconnect AD Flow Q Not Empty; VN0 WB Messages event=0x27,umask=8 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_req uncore interconnect AD Flow Q Not Empty; VN1 REQ Messages event=0x27,umask=0x10 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_rsp uncore interconnect AD Flow Q Not Empty; VN1 RSP Messages event=0x27,umask=0x40 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_snp uncore interconnect AD Flow Q Not Empty; VN1 SNP Messages event=0x27,umask=0x20 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_wb uncore interconnect AD Flow Q Not Empty; VN1 WB Messages event=0x27,umask=0x80 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_inserts.vn0_req uncore interconnect AD Flow Q Inserts; VN0 REQ Messages event=0x2d,umask=1 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_rsp uncore interconnect AD Flow Q Inserts; VN0 RSP Messages event=0x2d,umask=4 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_snp uncore interconnect AD Flow Q Inserts; VN0 SNP Messages event=0x2d,umask=2 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_wb uncore interconnect AD Flow Q Inserts; VN0 WB Messages event=0x2d,umask=8 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_req uncore interconnect AD Flow Q Inserts; VN1 REQ Messages event=0x2d,umask=0x10 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_rsp uncore interconnect AD Flow Q Inserts; VN1 RSP Messages event=0x2d,umask=0x40 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_snp uncore interconnect AD Flow Q Inserts; VN1 SNP Messages event=0x2d,umask=0x20 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_occupancy.vn0_req uncore interconnect AD Flow Q Occupancy; VN0 REQ Messages event=0x1c,umask=1 01 unc_m3upi_txc_ad_flq_occupancy.vn0_rsp uncore interconnect AD Flow Q Occupancy; VN0 RSP Messages event=0x1c,umask=4 01 unc_m3upi_txc_ad_flq_occupancy.vn0_snp uncore interconnect AD Flow Q Occupancy; VN0 SNP Messages event=0x1c,umask=2 01 unc_m3upi_txc_ad_flq_occupancy.vn0_wb uncore interconnect AD Flow Q Occupancy; VN0 WB Messages event=0x1c,umask=8 01 unc_m3upi_txc_ad_flq_occupancy.vn1_req uncore interconnect AD Flow Q Occupancy; VN1 REQ Messages event=0x1c,umask=0x10 01 unc_m3upi_txc_ad_flq_occupancy.vn1_rsp uncore interconnect AD Flow Q Occupancy; VN1 RSP Messages event=0x1c,umask=0x40 01 unc_m3upi_txc_ad_flq_occupancy.vn1_snp uncore interconnect AD Flow Q Occupancy; VN1 SNP Messages event=0x1c,umask=0x20 01 unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_cha uncore interconnect Number of Snoop Targets; CHA on VN0 event=0x3c,umask=4 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_non_idle uncore interconnect Number of Snoop Targets; Non Idle cycles on VN0 event=0x3c,umask=0x40 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_peer_upi0 uncore interconnect Number of Snoop Targets; Peer UPI0 on VN0 event=0x3c,umask=1 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0 unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_peer_upi1 uncore interconnect Number of Snoop Targets; Peer UPI1 on VN0 event=0x3c,umask=2 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1 unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_cha uncore interconnect Number of Snoop Targets; CHA on VN1 event=0x3c,umask=0x20 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_non_idle uncore interconnect Number of Snoop Targets; Non Idle cycles on VN1 event=0x3c,umask=0x80 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_peer_upi0 uncore interconnect Number of Snoop Targets; Peer UPI0 on VN1 event=0x3c,umask=8 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0 unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_peer_upi1 uncore interconnect Number of Snoop Targets; Peer UPI1 on VN1 event=0x3c,umask=0x10 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1 unc_m3upi_txc_ad_snpf_grp2_vn1.vn0_snpfp_nonsnp uncore interconnect Snoop Arbitration; FlowQ Won event=0x3d,umask=1 01 Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0 unc_m3upi_txc_ad_snpf_grp2_vn1.vn0_snpfp_vn2snp uncore interconnect Snoop Arbitration; FlowQ SnpF Won event=0x3d,umask=4 01 Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1 unc_m3upi_txc_ad_snpf_grp2_vn1.vn1_snpfp_nonsnp uncore interconnect Snoop Arbitration; FlowQ Won event=0x3d,umask=2 01 Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1 unc_m3upi_txc_ad_snpf_grp2_vn1.vn1_snpfp_vn0snp uncore interconnect Snoop Arbitration; FlowQ SnpF Won event=0x3d,umask=8 01 Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0 unc_m3upi_txc_ad_spec_arb_crd_avail.vn0_req uncore interconnect Speculative ARB for AD - Credit Available; VN0 REQ Messages event=0x34,umask=1 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn0_snp uncore interconnect Speculative ARB for AD - Credit Available; VN0 SNP Messages event=0x34,umask=2 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn0_wb uncore interconnect Speculative ARB for AD - Credit Available; VN0 WB Messages event=0x34,umask=8 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn1_req uncore interconnect Speculative ARB for AD - Credit Available; VN1 REQ Messages event=0x34,umask=0x10 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn1_snp uncore interconnect Speculative ARB for AD - Credit Available; VN1 SNP Messages event=0x34,umask=0x20 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn1_wb uncore interconnect Speculative ARB for AD - Credit Available; VN1 WB Messages event=0x34,umask=0x80 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_new_msg.vn0_req uncore interconnect Speculative ARB for AD - New Message; VN0 REQ Messages event=0x33,umask=1 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn0_snp uncore interconnect Speculative ARB for AD - New Message; VN0 SNP Messages event=0x33,umask=2 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn0_wb uncore interconnect Speculative ARB for AD - New Message; VN0 WB Messages event=0x33,umask=8 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn1_req uncore interconnect Speculative ARB for AD - New Message; VN1 REQ Messages event=0x33,umask=0x10 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn1_snp uncore interconnect Speculative ARB for AD - New Message; VN1 SNP Messages event=0x33,umask=0x20 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn1_wb uncore interconnect Speculative ARB for AD - New Message; VN1 WB Messages event=0x33,umask=0x80 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_req uncore interconnect Speculative ARB for AD - No Credit; VN0 REQ Messages event=0x32,umask=1 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_rsp uncore interconnect Speculative ARB for AD - No Credit; VN0 RSP Messages event=0x32,umask=4 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_snp uncore interconnect Speculative ARB for AD - No Credit; VN0 SNP Messages event=0x32,umask=2 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_wb uncore interconnect Speculative ARB for AD - No Credit; VN0 WB Messages event=0x32,umask=8 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_req uncore interconnect Speculative ARB for AD - No Credit; VN1 REQ Messages event=0x32,umask=0x10 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_rsp uncore interconnect Speculative ARB for AD - No Credit; VN1 RSP Messages event=0x32,umask=0x40 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_snp uncore interconnect Speculative ARB for AD - No Credit; VN1 SNP Messages event=0x32,umask=0x20 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_wb uncore interconnect Speculative ARB for AD - No Credit; VN1 WB Messages event=0x32,umask=0x80 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ak_flq_inserts uncore interconnect AK Flow Q Inserts event=0x2f 01 unc_m3upi_txc_ak_flq_occupancy uncore interconnect AK Flow Q Occupancy event=0x1e 01 unc_m3upi_txc_bl_arb_fail.vn0_ncb uncore interconnect Failed ARB for BL; VN0 NCB Messages event=0x35,umask=4 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_ncs uncore interconnect Failed ARB for BL; VN0 NCS Messages event=0x35,umask=8 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_rsp uncore interconnect Failed ARB for BL; VN0 RSP Messages event=0x35,umask=1 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_wb uncore interconnect Failed ARB for BL; VN0 WB Messages event=0x35,umask=2 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncb uncore interconnect Failed ARB for BL; VN1 NCS Messages event=0x35,umask=0x40 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncs uncore interconnect Failed ARB for BL; VN1 NCB Messages event=0x35,umask=0x80 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_rsp uncore interconnect Failed ARB for BL; VN1 RSP Messages event=0x35,umask=0x10 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_wb uncore interconnect Failed ARB for BL; VN1 WB Messages event=0x35,umask=0x20 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_flq_cycles_ne.vn0_req uncore interconnect BL Flow Q Not Empty; VN0 REQ Messages event=0x28,umask=1 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_rsp uncore interconnect BL Flow Q Not Empty; VN0 RSP Messages event=0x28,umask=4 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_snp uncore interconnect BL Flow Q Not Empty; VN0 SNP Messages event=0x28,umask=2 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_wb uncore interconnect BL Flow Q Not Empty; VN0 WB Messages event=0x28,umask=8 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_req uncore interconnect BL Flow Q Not Empty; VN1 REQ Messages event=0x28,umask=0x10 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_rsp uncore interconnect BL Flow Q Not Empty; VN1 RSP Messages event=0x28,umask=0x40 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_snp uncore interconnect BL Flow Q Not Empty; VN1 SNP Messages event=0x28,umask=0x20 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_wb uncore interconnect BL Flow Q Not Empty; VN1 WB Messages event=0x28,umask=0x80 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_inserts.vn0_ncb uncore interconnect BL Flow Q Inserts; VN0 RSP Messages event=0x2e,umask=1 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_ncs uncore interconnect BL Flow Q Inserts; VN0 WB Messages event=0x2e,umask=2 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_rsp uncore interconnect BL Flow Q Inserts; VN0 NCS Messages event=0x2e,umask=8 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_wb uncore interconnect BL Flow Q Inserts; VN0 NCB Messages event=0x2e,umask=4 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncb uncore interconnect BL Flow Q Inserts; VN1 RSP Messages event=0x2e,umask=0x10 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncs uncore interconnect BL Flow Q Inserts; VN1 WB Messages event=0x2e,umask=0x20 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_rsp uncore interconnect BL Flow Q Inserts; VN1_NCB Messages event=0x2e,umask=0x80 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_wb uncore interconnect BL Flow Q Inserts; VN1_NCS Messages event=0x2e,umask=0x40 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_occupancy.vn0_ncb uncore interconnect BL Flow Q Occupancy; VN0 NCB Messages event=0x1d,umask=4 01 unc_m3upi_txc_bl_flq_occupancy.vn0_ncs uncore interconnect BL Flow Q Occupancy; VN0 NCS Messages event=0x1d,umask=8 01 unc_m3upi_txc_bl_flq_occupancy.vn0_rsp uncore interconnect BL Flow Q Occupancy; VN0 RSP Messages event=0x1d,umask=1 01 unc_m3upi_txc_bl_flq_occupancy.vn0_wb uncore interconnect BL Flow Q Occupancy; VN0 WB Messages event=0x1d,umask=2 01 unc_m3upi_txc_bl_flq_occupancy.vn1_ncb uncore interconnect BL Flow Q Occupancy; VN1_NCS Messages event=0x1d,umask=0x40 01 unc_m3upi_txc_bl_flq_occupancy.vn1_ncs uncore interconnect BL Flow Q Occupancy; VN1_NCB Messages event=0x1d,umask=0x80 01 unc_m3upi_txc_bl_flq_occupancy.vn1_rsp uncore interconnect BL Flow Q Occupancy; VN1 RSP Messages event=0x1d,umask=0x10 01 unc_m3upi_txc_bl_flq_occupancy.vn1_wb uncore interconnect BL Flow Q Occupancy; VN1 WB Messages event=0x1d,umask=0x20 01 unc_m3upi_txc_bl_spec_arb_new_msg.vn0_ncb uncore interconnect Speculative ARB for BL - New Message; VN0 WB Messages event=0x38,umask=2 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn0_ncs uncore interconnect Speculative ARB for BL - New Message; VN0 NCS Messages event=0x38,umask=8 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn0_wb uncore interconnect Speculative ARB for BL - New Message; VN0 WB Messages event=0x38,umask=1 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn1_ncb uncore interconnect Speculative ARB for BL - New Message; VN1 WB Messages event=0x38,umask=0x20 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn1_ncs uncore interconnect Speculative ARB for BL - New Message; VN1 NCB Messages event=0x38,umask=0x80 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn1_wb uncore interconnect Speculative ARB for BL - New Message; VN1 RSP Messages event=0x38,umask=0x10 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_ncb uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 NCB Messages event=0x37,umask=4 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_ncs uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 NCS Messages event=0x37,umask=8 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_rsp uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 RSP Messages event=0x37,umask=1 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_wb uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 WB Messages event=0x37,umask=2 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_ncb uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 NCS Messages event=0x37,umask=0x40 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_ncs uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 NCB Messages event=0x37,umask=0x80 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_rsp uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 RSP Messages event=0x37,umask=0x10 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_wb uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 WB Messages event=0x37,umask=0x20 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txr_horz_ads_used.ad_bnc uncore interconnect CMS Horizontal ADS Used; AD - Bounce event=0x9d,umask=1 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used; AD - Credit event=0x9d,umask=0x10 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.ak_bnc uncore interconnect CMS Horizontal ADS Used; AK - Bounce event=0x9d,umask=2 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_bnc uncore interconnect CMS Horizontal ADS Used; BL - Bounce event=0x9d,umask=4 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used; BL - Credit event=0x9d,umask=0x40 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_bnc uncore interconnect CMS Horizontal Bypass Used; AD - Bounce event=0x9f,umask=1 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used; AD - Credit event=0x9f,umask=0x10 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ak_bnc uncore interconnect CMS Horizontal Bypass Used; AK - Bounce event=0x9f,umask=2 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_bnc uncore interconnect CMS Horizontal Bypass Used; BL - Bounce event=0x9f,umask=4 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used; BL - Credit event=0x9f,umask=0x40 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.iv_bnc uncore interconnect CMS Horizontal Bypass Used; IV - Bounce event=0x9f,umask=8 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_cycles_full.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Bounce event=0x96,umask=1 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Credit event=0x96,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AK - Bounce event=0x96,umask=2 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Bounce event=0x96,umask=4 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Credit event=0x96,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; IV - Bounce event=0x96,umask=8 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce event=0x97,umask=1 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit event=0x97,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce event=0x97,umask=2 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce event=0x97,umask=4 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit event=0x97,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce event=0x97,umask=8 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_bnc uncore interconnect CMS Horizontal Egress Inserts; AD - Bounce event=0x95,umask=1 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts; AD - Credit event=0x95,umask=0x10 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ak_bnc uncore interconnect CMS Horizontal Egress Inserts; AK - Bounce event=0x95,umask=2 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_bnc uncore interconnect CMS Horizontal Egress Inserts; BL - Bounce event=0x95,umask=4 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts; BL - Credit event=0x95,umask=0x40 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.iv_bnc uncore interconnect CMS Horizontal Egress Inserts; IV - Bounce event=0x95,umask=8 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_nack.ad_bnc uncore interconnect CMS Horizontal Egress NACKs; AD - Bounce event=0x99,umask=1 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs; AD - Credit event=0x99,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ak_bnc uncore interconnect CMS Horizontal Egress NACKs; AK - Bounce event=0x99,umask=2 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_bnc uncore interconnect CMS Horizontal Egress NACKs; BL - Bounce event=0x99,umask=4 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs; BL - Credit event=0x99,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.iv_bnc uncore interconnect CMS Horizontal Egress NACKs; IV - Bounce event=0x99,umask=8 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_occupancy.ad_bnc uncore interconnect CMS Horizontal Egress Occupancy; AD - Bounce event=0x94,umask=1 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy; AD - Credit event=0x94,umask=0x10 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ak_bnc uncore interconnect CMS Horizontal Egress Occupancy; AK - Bounce event=0x94,umask=2 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_bnc uncore interconnect CMS Horizontal Egress Occupancy; BL - Bounce event=0x94,umask=4 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy; BL - Credit event=0x94,umask=0x40 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.iv_bnc uncore interconnect CMS Horizontal Egress Occupancy; IV - Bounce event=0x94,umask=8 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_starved.ad_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AD - Bounce event=0x9b,umask=1 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.ak_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AK - Bounce event=0x9b,umask=2 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.bl_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; BL - Bounce event=0x9b,umask=4 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.iv_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; IV - Bounce event=0x9b,umask=8 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9c,umask=1 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9c,umask=0x10 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9c,umask=2 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9c,umask=0x20 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9c,umask=4 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9c,umask=0x40 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9e,umask=1 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9e,umask=0x10 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9e,umask=2 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9e,umask=0x20 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9e,umask=4 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9e,umask=0x40 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.iv uncore interconnect CMS Vertical ADS Used; IV event=0x9e,umask=8 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_cycles_full.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0 event=0x92,umask=1 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_full.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1 event=0x92,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_full.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0 event=0x92,umask=2 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_full.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1 event=0x92,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_full.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0 event=0x92,umask=4 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_full.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1 event=0x92,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_full.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Full; IV event=0x92,umask=8 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_cycles_ne.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0 event=0x93,umask=1 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_ne.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1 event=0x93,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_ne.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0 event=0x93,umask=2 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_ne.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1 event=0x93,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_ne.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0 event=0x93,umask=4 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_ne.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1 event=0x93,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_ne.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; IV event=0x93,umask=8 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_inserts.ad_ag0 uncore interconnect CMS Vert Egress Allocations; AD - Agent 0 event=0x91,umask=1 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_inserts.ad_ag1 uncore interconnect CMS Vert Egress Allocations; AD - Agent 1 event=0x91,umask=0x10 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_inserts.ak_ag0 uncore interconnect CMS Vert Egress Allocations; AK - Agent 0 event=0x91,umask=2 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_inserts.ak_ag1 uncore interconnect CMS Vert Egress Allocations; AK - Agent 1 event=0x91,umask=0x20 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_inserts.bl_ag0 uncore interconnect CMS Vert Egress Allocations; BL - Agent 0 event=0x91,umask=4 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_inserts.bl_ag1 uncore interconnect CMS Vert Egress Allocations; BL - Agent 1 event=0x91,umask=0x40 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_inserts.iv uncore interconnect CMS Vert Egress Allocations; IV event=0x91,umask=8 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_nack.ad_ag0 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 0 event=0x98,umask=1 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.ad_ag1 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 1 event=0x98,umask=0x10 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.ak_ag0 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 0 event=0x98,umask=2 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.ak_ag1 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 1 event=0x98,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.bl_ag0 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 0 event=0x98,umask=4 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.bl_ag1 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 1 event=0x98,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.iv uncore interconnect CMS Vertical Egress NACKs; IV event=0x98,umask=8 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_occupancy.ad_ag0 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 0 event=0x90,umask=1 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_occupancy.ad_ag1 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 1 event=0x90,umask=0x10 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_occupancy.ak_ag0 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 0 event=0x90,umask=2 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_occupancy.ak_ag1 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 1 event=0x90,umask=0x20 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_occupancy.bl_ag0 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 0 event=0x90,umask=4 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_occupancy.bl_ag1 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 1 event=0x90,umask=0x40 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_occupancy.iv uncore interconnect CMS Vert Egress Occupancy; IV event=0x90,umask=8 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_starved.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 0 event=0x9a,umask=1 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 1 event=0x9a,umask=0x10 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 0 event=0x9a,umask=2 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 1 event=0x9a,umask=0x20 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 0 event=0x9a,umask=4 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 1 event=0x9a,umask=0x40 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.iv uncore interconnect CMS Vertical Egress Injection Starvation; IV event=0x9a,umask=8 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_upi_peer_ad_credits_empty.vn0_req uncore interconnect UPI0 AD Credits Empty; VN0 REQ Messages event=0x20,umask=2 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_rsp uncore interconnect UPI0 AD Credits Empty; VN0 RSP Messages event=0x20,umask=8 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_snp uncore interconnect UPI0 AD Credits Empty; VN0 SNP Messages event=0x20,umask=4 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_req uncore interconnect UPI0 AD Credits Empty; VN1 REQ Messages event=0x20,umask=0x10 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_rsp uncore interconnect UPI0 AD Credits Empty; VN1 RSP Messages event=0x20,umask=0x40 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_snp uncore interconnect UPI0 AD Credits Empty; VN1 SNP Messages event=0x20,umask=0x20 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vna uncore interconnect UPI0 AD Credits Empty; VNA event=0x20,umask=1 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_bl_credits_empty.vn0_ncs_ncb uncore interconnect UPI0 BL Credits Empty; VN0 RSP Messages event=0x21,umask=4 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_rsp uncore interconnect UPI0 BL Credits Empty; VN0 REQ Messages event=0x21,umask=2 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_wb uncore interconnect UPI0 BL Credits Empty; VN0 SNP Messages event=0x21,umask=8 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_ncs_ncb uncore interconnect UPI0 BL Credits Empty; VN1 RSP Messages event=0x21,umask=0x20 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_rsp uncore interconnect UPI0 BL Credits Empty; VN1 REQ Messages event=0x21,umask=0x10 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_wb uncore interconnect UPI0 BL Credits Empty; VN1 SNP Messages event=0x21,umask=0x40 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vna uncore interconnect UPI0 BL Credits Empty; VNA event=0x21,umask=1 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_prefetch_spawn uncore interconnect Prefetches generated by the flow control queue of the M3UPI unit event=0x29 01 Count cases where flow control queue that sits between the Intel(R) Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller) unc_m3upi_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use; Down and Even event=0xa6,umask=4 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use; Down and Odd event=0xa6,umask=8 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use; Up and Even event=0xa6,umask=1 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use; Up and Odd event=0xa6,umask=2 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use; Down and Even event=0xa8,umask=4 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use; Down and Odd event=0xa8,umask=8 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use; Up and Even event=0xa8,umask=1 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use; Up and Odd event=0xa8,umask=2 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use; Down and Even event=0xaa,umask=4 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use; Down and Odd event=0xaa,umask=8 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use; Up and Even event=0xaa,umask=1 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use; Up and Odd event=0xaa,umask=2 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use; Down event=0xac,umask=4 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use; Up event=0xac,umask=1 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vn0_credits_used.ncb uncore interconnect VN0 Credit Used; WB on BL event=0x5c,umask=0x10 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_credits_used.ncs uncore interconnect VN0 Credit Used; NCB on BL event=0x5c,umask=0x20 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn0_credits_used.req uncore interconnect VN0 Credit Used; REQ on AD event=0x5c,umask=1 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_credits_used.rsp uncore interconnect VN0 Credit Used; RSP on AD event=0x5c,umask=4 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_credits_used.snp uncore interconnect VN0 Credit Used; SNP on AD event=0x5c,umask=2 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn0_credits_used.wb uncore interconnect VN0 Credit Used; RSP on BL event=0x5c,umask=8 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.ncb uncore interconnect VN0 No Credits; WB on BL event=0x5e,umask=0x10 01 Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_no_credits.ncs uncore interconnect VN0 No Credits; NCB on BL event=0x5e,umask=0x20 01 Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn0_no_credits.req uncore interconnect VN0 No Credits; REQ on AD event=0x5e,umask=1 01 Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_no_credits.rsp uncore interconnect VN0 No Credits; RSP on AD event=0x5e,umask=4 01 Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.snp uncore interconnect VN0 No Credits; SNP on AD event=0x5e,umask=2 01 Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn0_no_credits.wb uncore interconnect VN0 No Credits; RSP on BL event=0x5e,umask=8 01 Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.ncb uncore interconnect VN1 Credit Used; WB on BL event=0x5d,umask=0x10 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_credits_used.ncs uncore interconnect VN1 Credit Used; NCB on BL event=0x5d,umask=0x20 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn1_credits_used.req uncore interconnect VN1 Credit Used; REQ on AD event=0x5d,umask=1 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_credits_used.rsp uncore interconnect VN1 Credit Used; RSP on AD event=0x5d,umask=4 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.snp uncore interconnect VN1 Credit Used; SNP on AD event=0x5d,umask=2 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn1_credits_used.wb uncore interconnect VN1 Credit Used; RSP on BL event=0x5d,umask=8 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.ncb uncore interconnect VN1 No Credits; WB on BL event=0x5f,umask=0x10 01 Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_no_credits.ncs uncore interconnect VN1 No Credits; NCB on BL event=0x5f,umask=0x20 01 Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn1_no_credits.req uncore interconnect VN1 No Credits; REQ on AD event=0x5f,umask=1 01 Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_no_credits.rsp uncore interconnect VN1 No Credits; RSP on AD event=0x5f,umask=4 01 Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.snp uncore interconnect VN1 No Credits; SNP on AD event=0x5f,umask=2 01 Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn1_no_credits.wb uncore interconnect VN1 No Credits; RSP on BL event=0x5f,umask=8 01 Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_nounit_txc_bl.drs_upi uncore interconnect This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI event=0x40,umask=4 11 uncore_upi unc_upi_clockticks uncore interconnect Clocks of the Intel(R) Ultra Path Interconnect (UPI) event=1 01 Counts clockticks of the fixed frequency clock controlling the Intel(R) Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz unc_upi_direct_attempts.d2c uncore interconnect Data Response packets that go direct to core event=0x12,umask=1 01 Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA unc_upi_direct_attempts.d2k uncore interconnect This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U event=0x12,umask=2 11 unc_upi_direct_attempts.d2u uncore interconnect Data Response packets that go direct to Intel(R) UPI event=0x12,umask=2 01 Counts Data Response (DRS) packets that attempted to go direct to Intel(R) Ultra Path Interconnect (UPI) bypassing the CHA unc_upi_flowq_no_vna_crd.ad_vna_eq0 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0 event=0x18,umask=1 01 unc_upi_flowq_no_vna_crd.ad_vna_eq1 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1 event=0x18,umask=2 01 unc_upi_flowq_no_vna_crd.ad_vna_eq2 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2 event=0x18,umask=4 01 unc_upi_flowq_no_vna_crd.ak_vna_eq0 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0 event=0x18,umask=0x10 01 unc_upi_flowq_no_vna_crd.ak_vna_eq1 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1 event=0x18,umask=0x20 01 unc_upi_flowq_no_vna_crd.ak_vna_eq2 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2 event=0x18,umask=0x40 01 unc_upi_flowq_no_vna_crd.ak_vna_eq3 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3 event=0x18,umask=0x80 01 unc_upi_flowq_no_vna_crd.bl_vna_eq0 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0 event=0x18,umask=8 01 unc_upi_l1_power_cycles uncore interconnect Cycles Intel(R) UPI is in L1 power mode (shutdown) event=0x21 01 Counts cycles when the Intel(R) Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown unc_upi_m3_byp_blocked.bgf_crd uncore interconnect UNC_UPI_M3_BYP_BLOCKED.BGF_CRD event=0x14,umask=8 01 unc_upi_m3_byp_blocked.flowq_ad_vna_le2 uncore interconnect UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2 event=0x14,umask=1 01 unc_upi_m3_byp_blocked.flowq_ak_vna_le3 uncore interconnect UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3 event=0x14,umask=4 01 unc_upi_m3_byp_blocked.flowq_bl_vna_eq0 uncore interconnect UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0 event=0x14,umask=2 01 unc_upi_m3_byp_blocked.gv_block uncore interconnect UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK event=0x14,umask=0x10 01 unc_upi_m3_crd_return_blocked uncore interconnect UNC_UPI_M3_CRD_RETURN_BLOCKED event=0x16 01 unc_upi_m3_rxq_blocked.bgf_crd uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD event=0x15,umask=0x20 01 unc_upi_m3_rxq_blocked.flowq_ad_vna_btw_2_thresh uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH event=0x15,umask=2 01 unc_upi_m3_rxq_blocked.flowq_ad_vna_le2 uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2 event=0x15,umask=1 01 unc_upi_m3_rxq_blocked.flowq_ak_vna_le3 uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3 event=0x15,umask=0x10 01 unc_upi_m3_rxq_blocked.flowq_bl_vna_btw_0_thresh uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH event=0x15,umask=8 01 unc_upi_m3_rxq_blocked.flowq_bl_vna_eq0 uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0 event=0x15,umask=4 01 unc_upi_m3_rxq_blocked.gv_block uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK event=0x15,umask=0x40 01 unc_upi_phy_init_cycles uncore interconnect Cycles where phy is not in L0, L0c, L0p, L1 event=0x20 01 unc_upi_power_l1_nack uncore interconnect L1 Req Nack event=0x23 01 Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_power_l1_req uncore interconnect L1 Req (same as L1 Ack) event=0x22 01 Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_req_slot2_from_m3.ack uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.ACK event=0x46,umask=8 01 unc_upi_req_slot2_from_m3.vn0 uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.VN0 event=0x46,umask=2 01 unc_upi_req_slot2_from_m3.vn1 uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.VN1 event=0x46,umask=4 01 unc_upi_req_slot2_from_m3.vna uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.VNA event=0x46,umask=1 01 unc_upi_rxl0p_power_cycles uncore interconnect Cycles the Rx of the Intel(R) UPI is in L0p power mode event=0x25 01 Counts cycles when the receive side (Rx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power unc_upi_rxl0_power_cycles uncore interconnect Cycles in L0. Receive side event=0x24 01 Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_upi_rxl_basic_hdr_match.ncb uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Bypass event=5,umask=0xe 01 Match Message Class - NCB unc_upi_rxl_basic_hdr_match.ncb_opc uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Bypass event=5,umask=0x10e 01 Match Message Class - NCB unc_upi_rxl_basic_hdr_match.ncs uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Standard event=5,umask=0xf 01 Match Message Class - NCS unc_upi_rxl_basic_hdr_match.ncs_opc uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Standard event=5,umask=0x10f 01 Match Message Class - NCS unc_upi_rxl_basic_hdr_match.req uncore interconnect Matches on Receive path of a UPI Port; Request event=5,umask=8 01 REQ Message Class unc_upi_rxl_basic_hdr_match.req_opc uncore interconnect Matches on Receive path of a UPI Port; Request Opcode event=5,umask=0x108 01 Match REQ Opcodes - Specified in Umask[7:4] unc_upi_rxl_basic_hdr_match.rspcnflt uncore interconnect Matches on Receive path of a UPI Port; Response - Conflict event=5,umask=0x1aa 01 unc_upi_rxl_basic_hdr_match.rspi uncore interconnect Matches on Receive path of a UPI Port; Response - Invalid event=5,umask=0x12a 01 unc_upi_rxl_basic_hdr_match.rsp_data uncore interconnect Matches on Receive path of a UPI Port; Response - Data event=5,umask=0xc 01 Match Message Class -WB unc_upi_rxl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Receive path of a UPI Port; Response - Data event=5,umask=0x10c 01 Match Message Class -WB unc_upi_rxl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Receive path of a UPI Port; Response - No Data event=5,umask=0xa 01 Match Message Class - RSP unc_upi_rxl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Receive path of a UPI Port; Response - No Data event=5,umask=0x10a 01 Match Message Class - RSP unc_upi_rxl_basic_hdr_match.snp uncore interconnect Matches on Receive path of a UPI Port; Snoop event=5,umask=9 01 SNP Message Class unc_upi_rxl_basic_hdr_match.snp_opc uncore interconnect Matches on Receive path of a UPI Port; Snoop Opcode event=5,umask=0x109 01 Match SNP Opcodes - Specified in Umask[7:4] unc_upi_rxl_basic_hdr_match.wb uncore interconnect Matches on Receive path of a UPI Port; Writeback event=5,umask=0xd 01 Match Message Class -WB unc_upi_rxl_basic_hdr_match.wb_opc uncore interconnect Matches on Receive path of a UPI Port; Writeback event=5,umask=0x10d 01 Match Message Class -WB unc_upi_rxl_bypassed.slot0 uncore interconnect FLITs received which bypassed the Slot0 Receive Buffer event=0x31,umask=1 01 Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot1 uncore interconnect FLITs received which bypassed the Slot0 Receive Buffer event=0x31,umask=2 01 Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot2 uncore interconnect FLITs received which bypassed the Slot0 Receive Buffer event=0x31,umask=4 01 Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_credits_consumed_vn0 uncore interconnect VN0 Credit Consumed event=0x39 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_credits_consumed_vn1 uncore interconnect VN1 Credit Consumed event=0x3a 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_credits_consumed_vna uncore interconnect VNA Credit Consumed event=0x38 01 Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_flits.all_data uncore interconnect Valid data FLITs received from any slot event=3,umask=0xf 01 Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit unc_upi_rxl_flits.all_null uncore interconnect Null FLITs received from any slot event=3,umask=0x27 01 Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit unc_upi_rxl_flits.data uncore interconnect Valid Flits Received; Data event=3,umask=8 01 Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received; Idle event=3,umask=0x47 01 Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.llcrd uncore interconnect Valid Flits Received; LLCRD Not Empty event=3,umask=0x10 01 Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_rxl_flits.llctrl uncore interconnect Valid Flits Received; LLCTRL event=3,umask=0x40 01 Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages unc_upi_rxl_flits.non_data uncore interconnect Protocol header and credit FLITs received from any slot event=3,umask=0x97 01 Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit unc_upi_rxl_flits.null uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL event=3,umask=0x20 11 unc_upi_rxl_flits.prothdr uncore interconnect Valid Flits Received; Protocol Header event=3,umask=0x80 01 Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_rxl_flits.prot_hdr uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR event=3,umask=0x80 11 unc_upi_rxl_flits.slot0 uncore interconnect Valid Flits Received; Slot 0 event=3,umask=1 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot1 uncore interconnect Valid Flits Received; Slot 1 event=3,umask=2 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot2 uncore interconnect Valid Flits Received; Slot 2 event=3,umask=4 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count unc_upi_rxl_hdr_match.ncb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB event=5,umask=0xc 11 unc_upi_rxl_hdr_match.ncs uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS event=5,umask=0xd 11 unc_upi_rxl_hdr_match.req uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ event=5,umask=8 11 unc_upi_rxl_hdr_match.rsp uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA event=5,umask=0xa 11 unc_upi_rxl_hdr_match.snp uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP event=5,umask=9 11 unc_upi_rxl_hdr_match.wb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB event=5,umask=0xb 11 unc_upi_rxl_inserts.slot0 uncore interconnect RxQ Flit Buffer Allocations; Slot 0 event=0x30,umask=1 01 Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot1 uncore interconnect RxQ Flit Buffer Allocations; Slot 1 event=0x30,umask=2 01 Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot2 uncore interconnect RxQ Flit Buffer Allocations; Slot 2 event=0x30,umask=4 01 Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_occupancy.slot0 uncore interconnect RxQ Occupancy - All Packets; Slot 0 event=0x32,umask=1 01 Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot1 uncore interconnect RxQ Occupancy - All Packets; Slot 1 event=0x32,umask=2 01 Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot2 uncore interconnect RxQ Occupancy - All Packets; Slot 2 event=0x32,umask=4 01 Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_slot_bypass.s0_rxq1 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1 event=0x33,umask=1 01 unc_upi_rxl_slot_bypass.s0_rxq2 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2 event=0x33,umask=2 01 unc_upi_rxl_slot_bypass.s1_rxq0 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0 event=0x33,umask=4 01 unc_upi_rxl_slot_bypass.s1_rxq2 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2 event=0x33,umask=8 01 unc_upi_rxl_slot_bypass.s2_rxq0 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0 event=0x33,umask=0x10 01 unc_upi_rxl_slot_bypass.s2_rxq1 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1 event=0x33,umask=0x20 01 unc_upi_txl0p_clk_active.cfg_ctl uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL event=0x2a,umask=1 01 unc_upi_txl0p_clk_active.dfx uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.DFX event=0x2a,umask=0x40 01 unc_upi_txl0p_clk_active.retry uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RETRY event=0x2a,umask=0x20 01 unc_upi_txl0p_clk_active.rxq uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RXQ event=0x2a,umask=2 01 unc_upi_txl0p_clk_active.rxq_bypass uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS event=0x2a,umask=4 01 unc_upi_txl0p_clk_active.rxq_cred uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED event=0x2a,umask=8 01 unc_upi_txl0p_clk_active.spare uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.SPARE event=0x2a,umask=0x80 01 unc_upi_txl0p_clk_active.txq uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.TXQ event=0x2a,umask=0x10 01 unc_upi_txl0p_power_cycles uncore interconnect Cycles in which the Tx of the Intel(R) Ultra Path Interconnect (UPI) is in L0p power mode event=0x27 01 Counts cycles when the transmit side (Tx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power unc_upi_txl0p_power_cycles_ll_enter uncore interconnect UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER event=0x28 01 unc_upi_txl0p_power_cycles_m3_exit uncore interconnect UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT event=0x29 01 unc_upi_txl0_power_cycles uncore interconnect Cycles in L0. Transmit side event=0x26 01 Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_upi_txl_basic_hdr_match.ncb uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Bypass event=4,umask=0xe 01 Match Message Class - NCB unc_upi_txl_basic_hdr_match.ncb_opc uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Bypass event=4,umask=0x10e 01 Match Message Class - NCB unc_upi_txl_basic_hdr_match.ncs uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Standard event=4,umask=0xf 01 Match Message Class - NCS unc_upi_txl_basic_hdr_match.ncs_opc uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Standard event=4,umask=0x10f 01 Match Message Class - NCS unc_upi_txl_basic_hdr_match.req uncore interconnect Matches on Transmit path of a UPI Port; Request event=4,umask=8 01 REQ Message Class unc_upi_txl_basic_hdr_match.req_opc uncore interconnect Matches on Transmit path of a UPI Port; Request Opcode event=4,umask=0x108 01 Match REQ Opcodes - Specified in Umask[7:4] unc_upi_txl_basic_hdr_match.rspcnflt uncore interconnect Matches on Transmit path of a UPI Port; Response - Conflict event=4,umask=0x1aa 01 unc_upi_txl_basic_hdr_match.rspi uncore interconnect Matches on Transmit path of a UPI Port; Response - Invalid event=4,umask=0x12a 01 unc_upi_txl_basic_hdr_match.rsp_data uncore interconnect Matches on Transmit path of a UPI Port; Response - Data event=4,umask=0xc 01 Match Message Class -WB unc_upi_txl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Transmit path of a UPI Port; Response - Data event=4,umask=0x10c 01 Match Message Class -WB unc_upi_txl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Transmit path of a UPI Port; Response - No Data event=4,umask=0xa 01 Match Message Class - RSP unc_upi_txl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Transmit path of a UPI Port; Response - No Data event=4,umask=0x10a 01 Match Message Class - RSP unc_upi_txl_basic_hdr_match.snp uncore interconnect Matches on Transmit path of a UPI Port; Snoop event=4,umask=9 01 SNP Message Class unc_upi_txl_basic_hdr_match.snp_opc uncore interconnect Matches on Transmit path of a UPI Port; Snoop Opcode event=4,umask=0x109 01 Match SNP Opcodes - Specified in Umask[7:4] unc_upi_txl_basic_hdr_match.wb uncore interconnect Matches on Transmit path of a UPI Port; Writeback event=4,umask=0xd 01 Match Message Class -WB unc_upi_txl_basic_hdr_match.wb_opc uncore interconnect Matches on Transmit path of a UPI Port; Writeback event=4,umask=0x10d 01 Match Message Class -WB unc_upi_txl_bypassed uncore interconnect FLITs that bypassed the TxL Buffer event=0x41 01 Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel(R) Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link unc_upi_txl_flits.all_data uncore interconnect Valid data FLITs transmitted via any slot event=2,umask=0xf 01 Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit unc_upi_txl_flits.all_null uncore interconnect Null FLITs transmitted from any slot event=2,umask=0x27 01 Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel(R) Ulra Path Interconnect (UPI) slots on this UPI unit unc_upi_txl_flits.data uncore interconnect Valid Flits Sent; Data event=2,umask=8 01 Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_txl_flits.idle uncore interconnect Idle FLITs transmitted event=2,umask=0x47 01 Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs unc_upi_txl_flits.llcrd uncore interconnect Valid Flits Sent; LLCRD Not Empty event=2,umask=0x10 01 Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_txl_flits.llctrl uncore interconnect Valid Flits Sent; LLCTRL event=2,umask=0x40 01 Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages unc_upi_txl_flits.non_data uncore interconnect Protocol header and credit FLITs transmitted across any slot event=2,umask=0x97 01 Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit unc_upi_txl_flits.null uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL event=2,umask=0x20 11 unc_upi_txl_flits.prothdr uncore interconnect Valid Flits Sent; Protocol Header event=2,umask=0x80 01 Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_txl_flits.prot_hdr uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR event=2,umask=0x80 11 unc_upi_txl_flits.slot0 uncore interconnect Valid Flits Sent; Slot 0 event=2,umask=1 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot1 uncore interconnect Valid Flits Sent; Slot 1 event=2,umask=2 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot2 uncore interconnect Valid Flits Sent; Slot 2 event=2,umask=4 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count unc_upi_txl_hdr_match.data_hdr uncore interconnect This event is deprecated event=4 11 unc_upi_txl_hdr_match.dual_slot_hdr uncore interconnect This event is deprecated event=4 11 unc_upi_txl_hdr_match.loc uncore interconnect This event is deprecated event=4 11 unc_upi_txl_hdr_match.ncb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB event=4,umask=0xe 11 unc_upi_txl_hdr_match.ncs uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS event=4,umask=0xf 11 unc_upi_txl_hdr_match.non_data_hdr uncore interconnect This event is deprecated event=4 11 unc_upi_txl_hdr_match.rem uncore interconnect This event is deprecated event=4 11 unc_upi_txl_hdr_match.req uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ event=4,umask=8 11 unc_upi_txl_hdr_match.rsp_data uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA event=4,umask=0xc 11 unc_upi_txl_hdr_match.rsp_nodata uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA event=4,umask=0xa 11 unc_upi_txl_hdr_match.sgl_slot_hdr uncore interconnect This event is deprecated event=4 11 unc_upi_txl_hdr_match.snp uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP event=4,umask=9 11 unc_upi_txl_hdr_match.wb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB event=4,umask=0xc 11 unc_upi_txl_inserts uncore interconnect Tx Flit Buffer Allocations event=0x40 01 Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_txl_occupancy uncore interconnect Tx Flit Buffer Occupancy event=0x42 01 Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ unc_upi_vna_credit_return_blocked_vn01 uncore interconnect UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01 event=0x45 01 unc_upi_vna_credit_return_occupancy uncore interconnect VNA Credits Pending Return - Occupancy event=0x44 01 Number of VNA credits in the Rx side that are waitng to be returned back across the link unc_u_event_msg.doorbell_rcvd uncore interconnect Message Received event=0x42,umask=8 01 Virtual Logical Wire (legacy) message were received from Uncore unc_u_event_msg.int_prio uncore interconnect Message Received event=0x42,umask=0x10 01 Virtual Logical Wire (legacy) message were received from Uncore unc_u_event_msg.ipi_rcvd uncore interconnect Message Received; IPI event=0x42,umask=4 01 Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts unc_u_event_msg.msi_rcvd uncore interconnect Message Received; MSI event=0x42,umask=2 01 Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only) unc_u_event_msg.vlw_rcvd uncore interconnect Message Received; VLW event=0x42,umask=1 01 Virtual Logical Wire (legacy) message were received from Uncore unc_u_lock_cycles uncore interconnect IDI Lock/SplitLock Cycles event=0x44 01 Number of times an IDI Lock/SplitLock sequence was started unc_u_phold_cycles.assert_to_ack uncore interconnect Cycles PHOLD Assert to Ack; Assert to ACK event=0x45,umask=1 01 PHOLD cycles unc_u_racu_drng.pftch_buf_empty uncore interconnect UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY event=0x4c,umask=4 01 unc_u_racu_drng.rdrand uncore interconnect UNC_U_RACU_DRNG.RDRAND event=0x4c,umask=1 01 unc_u_racu_drng.rdseed uncore interconnect UNC_U_RACU_DRNG.RDSEED event=0x4c,umask=2 01 upi_data_bandwidth_tx uncore interconnect UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data event=2,umask=0xf 017.11E-06Bytes Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit uncore_iio llc_misses.pcie_read uncore io PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 event=0x83,ch_mask=1,fc_mask=7,umask=4,ch_mask=0x1f 014Bytes Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus llc_misses.pcie_write uncore io PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 event=0x83,ch_mask=1,fc_mask=7,umask=1,ch_mask=0x1f 014Bytes Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_clockticks uncore io Clockticks of the IIO Traffic Controller event=1 01 Counts clockticks of the 1GHz traffic controller clock in the IIO unit unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIe Completion Buffer Inserts of completions with data: Part 0-3 event=0xc2,ch_mask=0xf,fc_mask=4,umask=3 01 unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIe Completion Buffer Inserts of completions with data: Part 0 event=0xc2,ch_mask=1,fc_mask=4,umask=3 01 unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIe Completion Buffer Inserts of completions with data: Part 1 event=0xc2,ch_mask=2,fc_mask=4,umask=3 01 unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIe Completion Buffer Inserts of completions with data: Part 2 event=0xc2,ch_mask=4,fc_mask=4,umask=3 01 unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIe Completion Buffer Inserts of completions with data: Part 3 event=0xc2,ch_mask=8,fc_mask=4,umask=3 01 unc_iio_comp_buf_inserts.port0 uncore io PCIe Completion Buffer Inserts; Port 0 event=0xc2,ch_mask=1,fc_mask=7,umask=4 01 unc_iio_comp_buf_inserts.port1 uncore io PCIe Completion Buffer Inserts; Port 1 event=0xc2,ch_mask=2,fc_mask=7,umask=4 01 unc_iio_comp_buf_inserts.port2 uncore io PCIe Completion Buffer Inserts; Port 2 event=0xc2,ch_mask=4,fc_mask=7,umask=4 01 unc_iio_comp_buf_inserts.port3 uncore io PCIe Completion Buffer Inserts; Port 3 event=0xc2,ch_mask=8,fc_mask=7,umask=4 01 unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io PCIe Completion Buffer occupancy of completions with data: Part 0-3 event=0xd5,fc_mask=4,umask=0xf 01 unc_iio_comp_buf_occupancy.cmpd.part0 uncore io PCIe Completion Buffer occupancy of completions with data: Part 0 event=0xd5,fc_mask=4,umask=1 01 unc_iio_comp_buf_occupancy.cmpd.part1 uncore io PCIe Completion Buffer occupancy of completions with data: Part 1 event=0xd5,fc_mask=4,umask=2 01 unc_iio_comp_buf_occupancy.cmpd.part2 uncore io PCIe Completion Buffer occupancy of completions with data: Part 2 event=0xd5,fc_mask=4,umask=4 01 unc_iio_comp_buf_occupancy.cmpd.part3 uncore io PCIe Completion Buffer occupancy of completions with data: Part 3 event=0xd5,fc_mask=4,umask=8 01 unc_iio_data_req_by_cpu.cfg_read.part0 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=1,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_read.part1 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=2,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_read.part2 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=4,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_read.part3 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=8,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_read.vtd0 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.cfg_read.vtd1 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.cfg_write.part0 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=1,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_write.part1 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=2,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_write.part2 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=4,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_write.part3 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=8,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_write.vtd0 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.cfg_write.vtd1 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.io_read.part0 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=1,fc_mask=7,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_read.part1 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=2,fc_mask=7,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_read.part2 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=4,fc_mask=7,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_read.part3 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=8,fc_mask=7,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_read.vtd0 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.io_read.vtd1 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.io_write.part0 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=1,fc_mask=7,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_write.part1 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=2,fc_mask=7,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_write.part2 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=4,fc_mask=7,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_write.part3 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=8,fc_mask=7,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_write.vtd0 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.io_write.vtd1 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.mem_read.part0 uncore io Read request for 4 bytes made by the CPU to IIO Part0 event=0xc0,ch_mask=1,fc_mask=7,umask=4 01 Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part1 uncore io Read request for 4 bytes made by the CPU to IIO Part1 event=0xc0,ch_mask=2,fc_mask=7,umask=4 01 Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part2 uncore io Read request for 4 bytes made by the CPU to IIO Part2 event=0xc0,ch_mask=4,fc_mask=7,umask=4 01 Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part3 uncore io Read request for 4 bytes made by the CPU to IIO Part3 event=0xc0,ch_mask=8,fc_mask=7,umask=4 01 Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.vtd0 uncore io Data requested by the CPU; Core reading from Card's MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=4 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.mem_read.vtd1 uncore io Data requested by the CPU; Core reading from Card's MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=4 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.mem_write.part0 uncore io Write request of 4 bytes made to IIO Part0 by the CPU event=0xc0,ch_mask=1,fc_mask=7,umask=1 01 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part1 uncore io Write request of 4 bytes made to IIO Part1 by the CPU event=0xc0,ch_mask=2,fc_mask=7,umask=1 01 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part2 uncore io Write request of 4 bytes made to IIO Part2 by the CPU event=0xc0,ch_mask=4,fc_mask=7,umask=1 01 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part3 uncore io Write request of 4 bytes made to IIO Part3 by the CPU event=0xc0,ch_mask=8,fc_mask=7,umask=1 01 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.vtd0 uncore io Data requested by the CPU; Core writing to Card's MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=1 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.mem_write.vtd1 uncore io Data requested by the CPU; Core writing to Card's MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=1 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.peer_read.part0 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=1,fc_mask=7,umask=8 01 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part1 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1 event=0xc0,ch_mask=2,fc_mask=7,umask=8 01 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part2 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2 event=0xc0,ch_mask=4,fc_mask=7,umask=8 01 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part3 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3 event=0xc0,ch_mask=8,fc_mask=7,umask=8 01 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.vtd0 uncore io Data requested by the CPU; Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=8 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.peer_read.vtd1 uncore io Data requested by the CPU; Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=8 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=1,fc_mask=7,umask=2 01 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit event=0xc0,ch_mask=2,fc_mask=7,umask=2 01 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit event=0xc0,ch_mask=4,fc_mask=7,umask=2 01 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit event=0xc0,ch_mask=8,fc_mask=7,umask=2 01 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.vtd0 uncore io Data requested by the CPU; Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=2 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.peer_write.vtd1 uncore io Data requested by the CPU; Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=2 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_of_cpu.atomic.part0 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=1,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.atomic.part1 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=2,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.atomic.part2 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=4,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.atomic.part3 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=8,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.atomic.vtd0 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.atomic.vtd1 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.atomiccmp.part0 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=1,fc_mask=7,umask=0x20 01 Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.atomiccmp.part1 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=2,fc_mask=7,umask=0x20 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.atomiccmp.part2 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=4,fc_mask=7,umask=0x20 01 Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.atomiccmp.part3 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=8,fc_mask=7,umask=0x20 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_read.part0 uncore io PCI Express bandwidth reading at IIO, part 0 event=0x83,ch_mask=1,fc_mask=7,umask=4 01 Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.part1 uncore io PCI Express bandwidth reading at IIO, part 1 event=0x83,ch_mask=2,fc_mask=7,umask=4 01 Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.part2 uncore io PCI Express bandwidth reading at IIO, part 2 event=0x83,ch_mask=4,fc_mask=7,umask=4 01 Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.part3 uncore io PCI Express bandwidth reading at IIO, part 3 event=0x83,ch_mask=8,fc_mask=7,umask=4 01 Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.vtd0 uncore io Data requested of the CPU; Card reading from DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=4 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.mem_read.vtd1 uncore io Data requested of the CPU; Card reading from DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=4 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.mem_write.part0 uncore io PCI Express bandwidth writing at IIO, part 0 event=0x83,ch_mask=1,fc_mask=7,umask=1 01 Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.part1 uncore io PCI Express bandwidth writing at IIO, part 1 event=0x83,ch_mask=2,fc_mask=7,umask=1 01 Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.part2 uncore io PCI Express bandwidth writing at IIO, part 2 event=0x83,ch_mask=4,fc_mask=7,umask=1 01 Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.part3 uncore io PCI Express bandwidth writing at IIO, part 3 event=0x83,ch_mask=8,fc_mask=7,umask=1 01 Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.vtd0 uncore io Data requested of the CPU; Card writing to DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=1 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.mem_write.vtd1 uncore io Data requested of the CPU; Card writing to DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=1 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.msg.part0 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=1,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.msg.part1 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=2,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.msg.part2 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=4,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.msg.part3 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=8,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.msg.vtd0 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=0x10,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.msg.vtd1 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=0x20,fc_mask=7,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.peer_read.part0 uncore io Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=1,fc_mask=7,umask=8 01 Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part1 uncore io Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target event=0x83,ch_mask=2,fc_mask=7,umask=8 01 Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part2 uncore io Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target event=0x83,ch_mask=4,fc_mask=7,umask=8 01 Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part3 uncore io Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target event=0x83,ch_mask=8,fc_mask=7,umask=8 01 Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.vtd0 uncore io Data requested of the CPU; Card reading from another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=8 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.peer_read.vtd1 uncore io Data requested of the CPU; Card reading from another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=8 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=1,fc_mask=7,umask=2 01 Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=2,fc_mask=7,umask=2 01 Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=4,fc_mask=7,umask=2 01 Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=8,fc_mask=7,umask=2 01 Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.vtd0 uncore io Data requested of the CPU; Card writing to another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=2 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.peer_write.vtd1 uncore io Data requested of the CPU; Card writing to another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=2 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_link_num_corr_err uncore io Num Link Correctable Errors event=0xf 01 unc_iio_link_num_retries uncore io Num Link Retries event=0xe 01 unc_iio_mask_match uncore io Number packets that passed the Mask/Match Filter event=0x21 01 unc_iio_mask_match_and.bus0 uncore io AND Mask/match for debug bus; Non-PCIE bus event=2,umask=1 01 Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_bus1 uncore io AND Mask/match for debug bus; Non-PCIE bus and PCIE bus event=2,umask=8 01 Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_not_bus1 uncore io AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus) event=2,umask=4 01 Asserted if all bits specified by mask match unc_iio_mask_match_and.bus1 uncore io AND Mask/match for debug bus; PCIE bus event=2,umask=2 01 Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_bus1 uncore io AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus event=2,umask=0x10 01 Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_not_bus1 uncore io AND Mask/match for debug bus event=2,umask=0x20 01 Asserted if all bits specified by mask match unc_iio_mask_match_or.bus0 uncore io OR Mask/match for debug bus; Non-PCIE bus event=3,umask=1 01 Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_bus1 uncore io OR Mask/match for debug bus; Non-PCIE bus and PCIE bus event=3,umask=8 01 Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_not_bus1 uncore io OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus) event=3,umask=4 01 Asserted if any bits specified by mask match unc_iio_mask_match_or.bus1 uncore io OR Mask/match for debug bus; PCIE bus event=3,umask=2 01 Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_bus1 uncore io OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus event=3,umask=0x10 01 Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_not_bus1 uncore io OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus) event=3,umask=0x20 01 Asserted if any bits specified by mask match unc_iio_nothing uncore io Counting disabled event=0 01 unc_iio_payload_bytes_in.atomic.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_in.atomic.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_in.atomic.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_in.atomic.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_in.atomic.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_in.atomic.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_in.atomiccmp.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=0x20 11 unc_iio_payload_bytes_in.atomiccmp.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=0x20 11 unc_iio_payload_bytes_in.atomiccmp.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=0x20 11 unc_iio_payload_bytes_in.atomiccmp.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=0x20 11 unc_iio_payload_bytes_in.mem_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=4 11 unc_iio_payload_bytes_in.mem_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=4 11 unc_iio_payload_bytes_in.mem_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=4 11 unc_iio_payload_bytes_in.mem_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=4 11 unc_iio_payload_bytes_in.mem_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=4 11 unc_iio_payload_bytes_in.mem_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=4 11 unc_iio_payload_bytes_in.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=1 11 unc_iio_payload_bytes_in.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=1 11 unc_iio_payload_bytes_in.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=1 11 unc_iio_payload_bytes_in.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=1 11 unc_iio_payload_bytes_in.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=1 11 unc_iio_payload_bytes_in.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=1 11 unc_iio_payload_bytes_in.msg.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_in.msg.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_in.msg.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_in.msg.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_in.msg.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_in.msg.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_in.peer_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=8 11 unc_iio_payload_bytes_in.peer_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=8 11 unc_iio_payload_bytes_in.peer_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=8 11 unc_iio_payload_bytes_in.peer_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=8 11 unc_iio_payload_bytes_in.peer_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=8 11 unc_iio_payload_bytes_in.peer_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=8 11 unc_iio_payload_bytes_in.peer_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=2 11 unc_iio_payload_bytes_in.peer_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=2 11 unc_iio_payload_bytes_in.peer_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=2 11 unc_iio_payload_bytes_in.peer_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=2 11 unc_iio_payload_bytes_in.peer_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=2 11 unc_iio_payload_bytes_in.peer_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=2 11 unc_iio_payload_bytes_out.cfg_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_out.cfg_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_out.cfg_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_out.cfg_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_out.cfg_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_out.cfg_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x10 11 unc_iio_payload_bytes_out.io_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=0x80 11 unc_iio_payload_bytes_out.io_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=0x80 11 unc_iio_payload_bytes_out.io_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=0x80 11 unc_iio_payload_bytes_out.io_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=0x80 11 unc_iio_payload_bytes_out.io_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x80 11 unc_iio_payload_bytes_out.io_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x80 11 unc_iio_payload_bytes_out.io_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=0x20 11 unc_iio_payload_bytes_out.io_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=0x20 11 unc_iio_payload_bytes_out.io_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=0x20 11 unc_iio_payload_bytes_out.io_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=0x20 11 unc_iio_payload_bytes_out.io_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x20 11 unc_iio_payload_bytes_out.io_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x20 11 unc_iio_payload_bytes_out.mem_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=4 11 unc_iio_payload_bytes_out.mem_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=4 11 unc_iio_payload_bytes_out.mem_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=4 11 unc_iio_payload_bytes_out.mem_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=4 11 unc_iio_payload_bytes_out.mem_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=4 11 unc_iio_payload_bytes_out.mem_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=4 11 unc_iio_payload_bytes_out.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=1 11 unc_iio_payload_bytes_out.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=1 11 unc_iio_payload_bytes_out.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=1 11 unc_iio_payload_bytes_out.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=1 11 unc_iio_payload_bytes_out.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=1 11 unc_iio_payload_bytes_out.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=1 11 unc_iio_payload_bytes_out.peer_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=8 11 unc_iio_payload_bytes_out.peer_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=8 11 unc_iio_payload_bytes_out.peer_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=8 11 unc_iio_payload_bytes_out.peer_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=8 11 unc_iio_payload_bytes_out.peer_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=8 11 unc_iio_payload_bytes_out.peer_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=8 11 unc_iio_payload_bytes_out.peer_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=2 11 unc_iio_payload_bytes_out.peer_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=2 11 unc_iio_payload_bytes_out.peer_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=2 11 unc_iio_payload_bytes_out.peer_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=2 11 unc_iio_payload_bytes_out.peer_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=2 11 unc_iio_payload_bytes_out.peer_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=2 11 unc_iio_symbol_times uncore io Symbol Times on Link event=0x82 01 Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS unc_iio_txn_in.atomic.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=0x10 11 unc_iio_txn_in.atomic.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=0x10 11 unc_iio_txn_in.atomic.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=0x10 11 unc_iio_txn_in.atomic.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=0x10 11 unc_iio_txn_in.atomic.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=7,umask=0x10 11 unc_iio_txn_in.atomic.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=7,umask=0x10 11 unc_iio_txn_in.atomiccmp.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=0x20 11 unc_iio_txn_in.atomiccmp.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=0x20 11 unc_iio_txn_in.atomiccmp.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=0x20 11 unc_iio_txn_in.atomiccmp.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=0x20 11 unc_iio_txn_in.mem_read.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=4 11 unc_iio_txn_in.mem_read.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=4 11 unc_iio_txn_in.mem_read.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=4 11 unc_iio_txn_in.mem_read.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=4 11 unc_iio_txn_in.mem_read.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=7,umask=4 11 unc_iio_txn_in.mem_read.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=7,umask=4 11 unc_iio_txn_in.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 event=0x84,ch_mask=1,fc_mask=7,umask=1 11 unc_iio_txn_in.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 event=0x84,ch_mask=2,fc_mask=7,umask=1 11 unc_iio_txn_in.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 event=0x84,ch_mask=4,fc_mask=7,umask=1 11 unc_iio_txn_in.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 event=0x84,ch_mask=8,fc_mask=7,umask=1 11 unc_iio_txn_in.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0 event=0x84,ch_mask=0x10,fc_mask=7,umask=1 11 unc_iio_txn_in.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1 event=0x84,ch_mask=0x20,fc_mask=7,umask=1 11 unc_iio_txn_in.msg.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=0x40 11 unc_iio_txn_in.msg.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=0x40 11 unc_iio_txn_in.msg.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=0x40 11 unc_iio_txn_in.msg.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=0x40 11 unc_iio_txn_in.msg.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=7,umask=0x40 11 unc_iio_txn_in.msg.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=7,umask=0x40 11 unc_iio_txn_in.peer_read.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=8 11 unc_iio_txn_in.peer_read.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=8 11 unc_iio_txn_in.peer_read.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=8 11 unc_iio_txn_in.peer_read.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=8 11 unc_iio_txn_in.peer_read.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=7,umask=8 11 unc_iio_txn_in.peer_read.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=7,umask=8 11 unc_iio_txn_in.peer_write.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=2 11 unc_iio_txn_in.peer_write.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=2 11 unc_iio_txn_in.peer_write.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=2 11 unc_iio_txn_in.peer_write.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=2 11 unc_iio_txn_in.peer_write.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=7,umask=2 11 unc_iio_txn_in.peer_write.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=7,umask=2 11 unc_iio_txn_out.cfg_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=0x40 11 unc_iio_txn_out.cfg_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=0x40 11 unc_iio_txn_out.cfg_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=0x40 11 unc_iio_txn_out.cfg_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=0x40 11 unc_iio_txn_out.cfg_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x40 11 unc_iio_txn_out.cfg_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x40 11 unc_iio_txn_out.cfg_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=0x10 11 unc_iio_txn_out.cfg_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=0x10 11 unc_iio_txn_out.cfg_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=0x10 11 unc_iio_txn_out.cfg_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=0x10 11 unc_iio_txn_out.cfg_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x10 11 unc_iio_txn_out.io_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=0x80 11 unc_iio_txn_out.io_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=0x80 11 unc_iio_txn_out.io_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=0x80 11 unc_iio_txn_out.io_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=0x80 11 unc_iio_txn_out.io_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x80 11 unc_iio_txn_out.io_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x80 11 unc_iio_txn_out.io_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=0x20 11 unc_iio_txn_out.io_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=0x20 11 unc_iio_txn_out.io_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=0x20 11 unc_iio_txn_out.io_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=0x20 11 unc_iio_txn_out.io_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x20 11 unc_iio_txn_out.io_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x20 11 unc_iio_txn_out.mem_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=4 11 unc_iio_txn_out.mem_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=4 11 unc_iio_txn_out.mem_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=4 11 unc_iio_txn_out.mem_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=4 11 unc_iio_txn_out.mem_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=4 11 unc_iio_txn_out.mem_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=4 11 unc_iio_txn_out.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=1 11 unc_iio_txn_out.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=1 11 unc_iio_txn_out.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=1 11 unc_iio_txn_out.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=1 11 unc_iio_txn_out.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=1 11 unc_iio_txn_out.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=1 11 unc_iio_txn_out.peer_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=8 11 unc_iio_txn_out.peer_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=8 11 unc_iio_txn_out.peer_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=8 11 unc_iio_txn_out.peer_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=8 11 unc_iio_txn_out.peer_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=8 11 unc_iio_txn_out.peer_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=8 11 unc_iio_txn_out.peer_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=2 11 unc_iio_txn_out.peer_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=2 11 unc_iio_txn_out.peer_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=2 11 unc_iio_txn_out.peer_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=2 11 unc_iio_txn_out.peer_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=2 11 unc_iio_txn_out.peer_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=2 11 unc_iio_txn_req_by_cpu.cfg_read.part0 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=1,fc_mask=7,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_read.part1 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=2,fc_mask=7,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_read.part2 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=4,fc_mask=7,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_read.part3 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=8,fc_mask=7,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_read.vtd0 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.cfg_read.vtd1 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.cfg_write.part0 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=1,fc_mask=7,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_write.part1 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=2,fc_mask=7,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_write.part2 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=4,fc_mask=7,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_write.part3 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=8,fc_mask=7,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_write.vtd0 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.cfg_write.vtd1 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.io_read.part0 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=1,fc_mask=7,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_read.part1 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=2,fc_mask=7,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_read.part2 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=4,fc_mask=7,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_read.part3 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=8,fc_mask=7,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_read.vtd0 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.io_read.vtd1 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.io_write.part0 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=1,fc_mask=7,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_write.part1 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=2,fc_mask=7,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_write.part2 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=4,fc_mask=7,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_write.part3 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=8,fc_mask=7,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_write.vtd0 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.io_write.vtd1 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part0 event=0xc1,ch_mask=1,fc_mask=7,umask=4 01 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part1 event=0xc1,ch_mask=2,fc_mask=7,umask=4 01 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part2 event=0xc1,ch_mask=4,fc_mask=7,umask=4 01 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part3 event=0xc1,ch_mask=8,fc_mask=7,umask=4 01 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.vtd0 uncore io Number Transactions requested by the CPU; Core reading from Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=4 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.mem_read.vtd1 uncore io Number Transactions requested by the CPU; Core reading from Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=4 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU event=0xc1,ch_mask=1,fc_mask=7,umask=1 01 Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU event=0xc1,ch_mask=2,fc_mask=7,umask=1 01 Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU event=0xc1,ch_mask=4,fc_mask=7,umask=1 01 Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU event=0xc1,ch_mask=8,fc_mask=7,umask=1 01 Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.vtd0 uncore io Number Transactions requested by the CPU; Core writing to Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=1 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.mem_write.vtd1 uncore io Number Transactions requested by the CPU; Core writing to Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=1 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.peer_read.part0 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0 event=0xc1,ch_mask=1,fc_mask=7,umask=8 01 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part1 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1 event=0xc1,ch_mask=2,fc_mask=7,umask=8 01 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part2 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2 event=0xc1,ch_mask=4,fc_mask=7,umask=8 01 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part3 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3 event=0xc1,ch_mask=8,fc_mask=7,umask=8 01 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.vtd0 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x10,fc_mask=7,umask=8 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.peer_read.vtd1 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x20,fc_mask=7,umask=8 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.peer_write.part0 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit event=0xc1,ch_mask=1,fc_mask=7,umask=2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part1 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit event=0xc1,ch_mask=2,fc_mask=7,umask=2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part2 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit event=0xc1,ch_mask=4,fc_mask=7,umask=2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part3 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit event=0xc1,ch_mask=8,fc_mask=7,umask=2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.vtd0 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x10,fc_mask=7,umask=2 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.peer_write.vtd1 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x20,fc_mask=7,umask=2 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_of_cpu.atomic.part0 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=1,fc_mask=7,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.atomic.part1 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=2,fc_mask=7,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.atomic.part2 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=4,fc_mask=7,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.atomic.part3 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=8,fc_mask=7,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.atomic.vtd0 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.atomic.vtd1 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.atomiccmp.part0 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=1,fc_mask=7,umask=0x20 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.atomiccmp.part1 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=2,fc_mask=7,umask=0x20 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.atomiccmp.part2 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=4,fc_mask=7,umask=0x20 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.atomiccmp.part3 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=8,fc_mask=7,umask=0x20 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=1,fc_mask=7,umask=4 01 Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is made by IIO Part1 to Memory event=0x84,ch_mask=2,fc_mask=7,umask=4 01 Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=4,fc_mask=7,umask=4 01 Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=8,fc_mask=7,umask=4 01 Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.vtd0 uncore io Number Transactions requested of the CPU; Card reading from DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=4 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.mem_read.vtd1 uncore io Number Transactions requested of the CPU; Card reading from DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=4 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=1,fc_mask=7,umask=1 01 Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made by IIO Part1 to Memory event=0x84,ch_mask=2,fc_mask=7,umask=1 01 Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=4,fc_mask=7,umask=1 01 Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=8,fc_mask=7,umask=1 01 Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.vtd0 uncore io Number Transactions requested of the CPU; Card writing to DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=1 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.mem_write.vtd1 uncore io Number Transactions requested of the CPU; Card writing to DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=1 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.msg.part0 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=1,fc_mask=7,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.msg.part1 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=2,fc_mask=7,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.msg.part2 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=4,fc_mask=7,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.msg.part3 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=8,fc_mask=7,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.msg.vtd0 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=0x10,fc_mask=7,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.msg.vtd1 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=0x20,fc_mask=7,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.peer_read.part0 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target event=0x84,ch_mask=1,fc_mask=7,umask=8 01 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part1 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target event=0x84,ch_mask=2,fc_mask=7,umask=8 01 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part2 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target event=0x84,ch_mask=4,fc_mask=7,umask=8 01 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part3 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target event=0x84,ch_mask=8,fc_mask=7,umask=8 01 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.vtd0 uncore io Number Transactions requested of the CPU; Card reading from another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=8 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.peer_read.vtd1 uncore io Number Transactions requested of the CPU; Card reading from another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=8 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.peer_write.part0 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target event=0x84,ch_mask=1,fc_mask=7,umask=2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part1 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target event=0x84,ch_mask=2,fc_mask=7,umask=2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part2 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target event=0x84,ch_mask=4,fc_mask=7,umask=2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part3 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target event=0x84,ch_mask=8,fc_mask=7,umask=2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.vtd0 uncore io Number Transactions requested of the CPU; Card writing to another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=2 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.peer_write.vtd1 uncore io Number Transactions requested of the CPU; Card writing to another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=2 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_vtd_access.ctxt_miss uncore io VTd Access; context cache miss event=0x41,umask=2 01 unc_iio_vtd_access.l1_miss uncore io VTd Access; L1 miss event=0x41,umask=4 01 unc_iio_vtd_access.l2_miss uncore io VTd Access; L2 miss event=0x41,umask=8 01 unc_iio_vtd_access.l3_miss uncore io VTd Access; L3 miss event=0x41,umask=0x10 01 unc_iio_vtd_access.l4_page_hit uncore io VTd Access; Vtd hit event=0x41,umask=1 01 unc_iio_vtd_access.tlb1_miss uncore io VTd Access; TLB miss event=0x41,umask=0x80 01 unc_iio_vtd_access.tlb_full uncore io VTd Access; TLB is full event=0x41,umask=0x40 01 unc_iio_vtd_access.tlb_miss uncore io VTd Access; TLB miss event=0x41,umask=0x20 01 unc_iio_vtd_occupancy uncore io VTd Occupancy event=0x40 01 llc_misses.mem_read uncore memory read requests to memory controller. Derived from unc_m_cas_count.rd event=4,umask=3 0164Bytes Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read. This event includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not llc_misses.mem_write uncore memory write requests to memory controller. Derived from unc_m_cas_count.wr event=4,umask=0xc 0164Bytes Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_act_count.byp uncore memory DRAM Activate Count; Activate due to Bypass event=1,umask=8 01 Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.wr uncore memory DRAM Page Activate commands sent due to a write request event=1,umask=2 01 Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command unc_m_cas_count.all uncore memory All DRAM CAS Commands issued event=4,umask=0xf 01 Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.rd uncore memory All DRAM Read CAS Commands issued (including underfills) event=4,umask=3 01 Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read. This event includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.rd_isoch uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode event=4,umask=0x40 01 unc_m_cas_count.rd_reg uncore memory All DRAM Read CAS Commands issued (does not include underfills) event=4,umask=1 01 Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.rd_rmm uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM event=4,umask=0x20 01 unc_m_cas_count.rd_underfill uncore memory DRAM Underfill Read CAS Commands issued event=4,umask=2 01 Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request) unc_m_cas_count.rd_wmm uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM event=4,umask=0x10 01 unc_m_cas_count.wr uncore memory All DRAM Write CAS commands issued event=4,umask=0xc 01 Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.wr_isoch uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode event=4,umask=0x80 01 unc_m_cas_count.wr_rmm uncore memory DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode event=4,umask=8 01 Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode unc_m_cas_count.wr_wmm uncore memory DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode event=4,umask=4 01 Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode unc_m_clockticks uncore memory Memory controller clock ticks event=0 01 Counts clockticks of the fixed frequency clock of the memory controller using one of the programmable counters unc_m_clockticks_f uncore memory Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter event=0xff 01 unc_m_majmode2.dram_cyc uncore memory UNC_M_MAJMODE2.DRAM_CYC event=0xed,umask=2 01 unc_m_majmode2.dram_enter uncore memory UNC_M_MAJMODE2.DRAM_ENTER event=0xed,umask=8 01 unc_m_majmode2.pmm_cyc uncore memory Major Mode 2 : Cycles in PMM major mode event=0xed,umask=1 01 unc_m_majmode2.pmm_enter uncore memory Major Mode 2 : Entered PMM major mode event=0xed,umask=4 01 unc_m_pmm_bandwidth.read uncore memory Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts event=0xe3 016.103515625E-5MB/sec unc_m_pmm_bandwidth.total uncore memory Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts event=0xe3 016.103515625E-5MB/sec unc_m_pmm_bandwidth.write uncore memory Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts event=0xe7 016.103515625E-5MB/sec unc_m_pmm_cmd1.all uncore memory All commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=1 01 unc_m_pmm_cmd1.misc uncore memory Misc Commands (error, flow ACKs) event=0xea,umask=0x80 01 unc_m_pmm_cmd1.misc_gnt uncore memory Misc GNTs event=0xea,umask=0x40 01 unc_m_pmm_cmd1.rd uncore memory Regular reads(RPQ) commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=2 01 All Reads - RPQ or Ufill unc_m_pmm_cmd1.rpq_gnts uncore memory RPQ GNTs event=0xea,umask=0x10 01 unc_m_pmm_cmd1.ufill_rd uncore memory Underfill read commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=8 01 Underfill reads unc_m_pmm_cmd1.wpq_gnts uncore memory Underfill GNTs event=0xea,umask=0x20 01 unc_m_pmm_cmd1.wr uncore memory Write commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=4 01 Writes unc_m_pmm_cmd2.nodata_exp uncore memory Expected No data packet (ERID matched NDP encoding) event=0xeb,umask=2 01 unc_m_pmm_cmd2.nodata_unexp uncore memory Unexpected No data packet (ERID matched a Read, but data was a NDP) event=0xeb,umask=4 01 unc_m_pmm_cmd2.opp_rd uncore memory Opportunistic Reads event=0xeb,umask=1 01 unc_m_pmm_cmd2.pmm_ecc_error uncore memory PMM ECC Errors event=0xeb,umask=0x20 01 unc_m_pmm_cmd2.pmm_erid_error uncore memory PMM ERID detectable parity error event=0xeb,umask=0x40 01 unc_m_pmm_cmd2.reqs_slot0 uncore memory Read Requests - Slot 0 event=0xeb,umask=8 01 unc_m_pmm_cmd2.reqs_slot1 uncore memory Read Requests - Slot 1 event=0xeb,umask=0x10 01 unc_m_pmm_majmode1.partial_wr_cyc uncore memory PMM Major Mode; Cycles PMM is in Partial Write Major Mode event=0xec,umask=4 01 unc_m_pmm_majmode1.partial_wr_enter uncore memory PMM Major Mode event=0xec,umask=0x20 01 unc_m_pmm_majmode1.partial_wr_exit uncore memory PMM Major Mode event=0xec,umask=0x40 01 unc_m_pmm_majmode1.rd_cyc uncore memory PMM Major Mode; Cycles PMM is in Read Major Mode event=0xec,umask=1 01 unc_m_pmm_majmode1.wr_cyc uncore memory PMM Major Mode; Cycles PMM is in Write Major Mode event=0xec,umask=2 01 unc_m_pmm_read_latency uncore memory Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all event=0xe0,umask=1 016000000000ns unc_m_pmm_rpq_cycles_full uncore memory PMM Read Queue Cycles Full event=0xe2 01 unc_m_pmm_rpq_cycles_ne uncore memory PMM Read Queue Cycles Not Empty event=0xe1 01 unc_m_pmm_rpq_inserts uncore memory Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory event=0xe3 01 unc_m_pmm_rpq_occupancy.all uncore memory Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory event=0xe0,umask=1 01 unc_m_pmm_rpq_occupancy.gnt_wait uncore memory PMM Occupancy event=0xe0,umask=4 01 unc_m_pmm_wpq_cycles_full uncore memory PMM Write Queue Cycles Full event=0xe6 01 unc_m_pmm_wpq_cycles_ne uncore memory PMM Write Queue Cycles Not Empty event=0xe5 01 unc_m_pmm_wpq_inserts uncore memory Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory event=0xe7 01 unc_m_pmm_wpq_occupancy.all uncore memory Write Pending Queue Occupancy of all write requests for Intel(R) Optane(TM) DC persistent memory event=0xe4,umask=1 01 unc_m_pmm_wpq_occupancy.cas uncore memory PMM Occupancy event=0xe4,umask=2 01 unc_m_pmm_wpq_occupancy.pwr uncore memory PMM Occupancy event=0xe4,umask=4 01 unc_m_pmm_wpq_pcommit uncore memory UNC_M_PMM_WPQ_PCOMMIT event=0xe8 01 unc_m_pmm_wpq_pcommit_cyc uncore memory UNC_M_PMM_WPQ_PCOMMIT_CYC event=0xe9 01 unc_m_power_channel_ppd uncore memory Cycles where DRAM ranks are in power down (CKE) mode+C37 event=0x85 01 Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of unc_m_power_self_refresh uncore memory Cycles Memory is in self refresh power mode event=0x43 01 Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_pre_count.page_miss uncore memory Pre-charges due to page misses event=2,umask=1 01 Counts the number of explicit DRAM Precharge commands sent on this channel as a result of a DRAM page miss. This does not include the implicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include Precharge commands sent as a result of a page close counter expiration unc_m_pre_count.rd uncore memory Pre-charge for reads event=2,umask=4 01 Counts the number of explicit DRAM Precharge commands issued on a per channel basis due to a read, so as to close the previous DRAM page, before opening the requested page unc_m_pre_count.wr uncore memory Pre-charge for writes event=2,umask=8 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_rd_cas_rank0.allbanks uncore memory RD_CAS Access to Rank 0; All Banks event=0xb0,umask=0x10 01 unc_m_rd_cas_rank0.bank0 uncore memory RD_CAS Access to Rank 0; Bank 0 event=0xb0 01 unc_m_rd_cas_rank0.bank1 uncore memory RD_CAS Access to Rank 0; Bank 1 event=0xb0,umask=1 01 unc_m_rd_cas_rank0.bank10 uncore memory RD_CAS Access to Rank 0; Bank 10 event=0xb0,umask=0xa 01 unc_m_rd_cas_rank0.bank11 uncore memory RD_CAS Access to Rank 0; Bank 11 event=0xb0,umask=0xb 01 unc_m_rd_cas_rank0.bank12 uncore memory RD_CAS Access to Rank 0; Bank 12 event=0xb0,umask=0xc 01 unc_m_rd_cas_rank0.bank13 uncore memory RD_CAS Access to Rank 0; Bank 13 event=0xb0,umask=0xd 01 unc_m_rd_cas_rank0.bank14 uncore memory RD_CAS Access to Rank 0; Bank 14 event=0xb0,umask=0xe 01 unc_m_rd_cas_rank0.bank15 uncore memory RD_CAS Access to Rank 0; Bank 15 event=0xb0,umask=0xf 01 unc_m_rd_cas_rank0.bank2 uncore memory RD_CAS Access to Rank 0; Bank 2 event=0xb0,umask=2 01 unc_m_rd_cas_rank0.bank3 uncore memory RD_CAS Access to Rank 0; Bank 3 event=0xb0,umask=3 01 unc_m_rd_cas_rank0.bank4 uncore memory RD_CAS Access to Rank 0; Bank 4 event=0xb0,umask=4 01 unc_m_rd_cas_rank0.bank5 uncore memory RD_CAS Access to Rank 0; Bank 5 event=0xb0,umask=5 01 unc_m_rd_cas_rank0.bank6 uncore memory RD_CAS Access to Rank 0; Bank 6 event=0xb0,umask=6 01 unc_m_rd_cas_rank0.bank7 uncore memory RD_CAS Access to Rank 0; Bank 7 event=0xb0,umask=7 01 unc_m_rd_cas_rank0.bank8 uncore memory RD_CAS Access to Rank 0; Bank 8 event=0xb0,umask=8 01 unc_m_rd_cas_rank0.bank9 uncore memory RD_CAS Access to Rank 0; Bank 9 event=0xb0,umask=9 01 unc_m_rd_cas_rank0.bankg0 uncore memory RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb0,umask=0x11 01 unc_m_rd_cas_rank0.bankg1 uncore memory RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb0,umask=0x12 01 unc_m_rd_cas_rank0.bankg2 uncore memory RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb0,umask=0x13 01 unc_m_rd_cas_rank0.bankg3 uncore memory RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb0,umask=0x14 01 unc_m_rd_cas_rank1.allbanks uncore memory RD_CAS Access to Rank 1; All Banks event=0xb1,umask=0x10 01 unc_m_rd_cas_rank1.bank0 uncore memory RD_CAS Access to Rank 1; Bank 0 event=0xb1 01 unc_m_rd_cas_rank1.bank1 uncore memory RD_CAS Access to Rank 1; Bank 1 event=0xb1,umask=1 01 unc_m_rd_cas_rank1.bank10 uncore memory RD_CAS Access to Rank 1; Bank 10 event=0xb1,umask=0xa 01 unc_m_rd_cas_rank1.bank11 uncore memory RD_CAS Access to Rank 1; Bank 11 event=0xb1,umask=0xb 01 unc_m_rd_cas_rank1.bank12 uncore memory RD_CAS Access to Rank 1; Bank 12 event=0xb1,umask=0xc 01 unc_m_rd_cas_rank1.bank13 uncore memory RD_CAS Access to Rank 1; Bank 13 event=0xb1,umask=0xd 01 unc_m_rd_cas_rank1.bank14 uncore memory RD_CAS Access to Rank 1; Bank 14 event=0xb1,umask=0xe 01 unc_m_rd_cas_rank1.bank15 uncore memory RD_CAS Access to Rank 1; Bank 15 event=0xb1,umask=0xf 01 unc_m_rd_cas_rank1.bank2 uncore memory RD_CAS Access to Rank 1; Bank 2 event=0xb1,umask=2 01 unc_m_rd_cas_rank1.bank3 uncore memory RD_CAS Access to Rank 1; Bank 3 event=0xb1,umask=3 01 unc_m_rd_cas_rank1.bank4 uncore memory RD_CAS Access to Rank 1; Bank 4 event=0xb1,umask=4 01 unc_m_rd_cas_rank1.bank5 uncore memory RD_CAS Access to Rank 1; Bank 5 event=0xb1,umask=5 01 unc_m_rd_cas_rank1.bank6 uncore memory RD_CAS Access to Rank 1; Bank 6 event=0xb1,umask=6 01 unc_m_rd_cas_rank1.bank7 uncore memory RD_CAS Access to Rank 1; Bank 7 event=0xb1,umask=7 01 unc_m_rd_cas_rank1.bank8 uncore memory RD_CAS Access to Rank 1; Bank 8 event=0xb1,umask=8 01 unc_m_rd_cas_rank1.bank9 uncore memory RD_CAS Access to Rank 1; Bank 9 event=0xb1,umask=9 01 unc_m_rd_cas_rank1.bankg0 uncore memory RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb1,umask=0x11 01 unc_m_rd_cas_rank1.bankg1 uncore memory RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb1,umask=0x12 01 unc_m_rd_cas_rank1.bankg2 uncore memory RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb1,umask=0x13 01 unc_m_rd_cas_rank1.bankg3 uncore memory RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb1,umask=0x14 01 unc_m_rd_cas_rank2.allbanks uncore memory RD_CAS Access to Rank 2; All Banks event=0xb2,umask=0x10 01 unc_m_rd_cas_rank2.bank0 uncore memory RD_CAS Access to Rank 2; Bank 0 event=0xb2 01 unc_m_rd_cas_rank2.bank1 uncore memory RD_CAS Access to Rank 2; Bank 1 event=0xb2,umask=1 01 unc_m_rd_cas_rank2.bank10 uncore memory RD_CAS Access to Rank 2; Bank 10 event=0xb2,umask=0xa 01 unc_m_rd_cas_rank2.bank11 uncore memory RD_CAS Access to Rank 2; Bank 11 event=0xb2,umask=0xb 01 unc_m_rd_cas_rank2.bank12 uncore memory RD_CAS Access to Rank 2; Bank 12 event=0xb2,umask=0xc 01 unc_m_rd_cas_rank2.bank13 uncore memory RD_CAS Access to Rank 2; Bank 13 event=0xb2,umask=0xd 01 unc_m_rd_cas_rank2.bank14 uncore memory RD_CAS Access to Rank 2; Bank 14 event=0xb2,umask=0xe 01 unc_m_rd_cas_rank2.bank15 uncore memory RD_CAS Access to Rank 2; Bank 15 event=0xb2,umask=0xf 01 unc_m_rd_cas_rank2.bank2 uncore memory RD_CAS Access to Rank 2; Bank 2 event=0xb2,umask=2 01 unc_m_rd_cas_rank2.bank3 uncore memory RD_CAS Access to Rank 2; Bank 3 event=0xb2,umask=3 01 unc_m_rd_cas_rank2.bank4 uncore memory RD_CAS Access to Rank 2; Bank 4 event=0xb2,umask=4 01 unc_m_rd_cas_rank2.bank5 uncore memory RD_CAS Access to Rank 2; Bank 5 event=0xb2,umask=5 01 unc_m_rd_cas_rank2.bank6 uncore memory RD_CAS Access to Rank 2; Bank 6 event=0xb2,umask=6 01 unc_m_rd_cas_rank2.bank7 uncore memory RD_CAS Access to Rank 2; Bank 7 event=0xb2,umask=7 01 unc_m_rd_cas_rank2.bank8 uncore memory RD_CAS Access to Rank 2; Bank 8 event=0xb2,umask=8 01 unc_m_rd_cas_rank2.bank9 uncore memory RD_CAS Access to Rank 2; Bank 9 event=0xb2,umask=9 01 unc_m_rd_cas_rank2.bankg0 uncore memory RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3) event=0xb2,umask=0x11 01 unc_m_rd_cas_rank2.bankg1 uncore memory RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7) event=0xb2,umask=0x12 01 unc_m_rd_cas_rank2.bankg2 uncore memory RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11) event=0xb2,umask=0x13 01 unc_m_rd_cas_rank2.bankg3 uncore memory RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15) event=0xb2,umask=0x14 01 unc_m_rd_cas_rank3.allbanks uncore memory RD_CAS Access to Rank 3; All Banks event=0xb3,umask=0x10 01 unc_m_rd_cas_rank3.bank0 uncore memory RD_CAS Access to Rank 3; Bank 0 event=0xb3 01 unc_m_rd_cas_rank3.bank1 uncore memory RD_CAS Access to Rank 3; Bank 1 event=0xb3,umask=1 01 unc_m_rd_cas_rank3.bank10 uncore memory RD_CAS Access to Rank 3; Bank 10 event=0xb3,umask=0xa 01 unc_m_rd_cas_rank3.bank11 uncore memory RD_CAS Access to Rank 3; Bank 11 event=0xb3,umask=0xb 01 unc_m_rd_cas_rank3.bank12 uncore memory RD_CAS Access to Rank 3; Bank 12 event=0xb3,umask=0xc 01 unc_m_rd_cas_rank3.bank13 uncore memory RD_CAS Access to Rank 3; Bank 13 event=0xb3,umask=0xd 01 unc_m_rd_cas_rank3.bank14 uncore memory RD_CAS Access to Rank 3; Bank 14 event=0xb3,umask=0xe 01 unc_m_rd_cas_rank3.bank15 uncore memory RD_CAS Access to Rank 3; Bank 15 event=0xb3,umask=0xf 01 unc_m_rd_cas_rank3.bank2 uncore memory RD_CAS Access to Rank 3; Bank 2 event=0xb3,umask=2 01 unc_m_rd_cas_rank3.bank3 uncore memory RD_CAS Access to Rank 3; Bank 3 event=0xb3,umask=3 01 unc_m_rd_cas_rank3.bank4 uncore memory RD_CAS Access to Rank 3; Bank 4 event=0xb3,umask=4 01 unc_m_rd_cas_rank3.bank5 uncore memory RD_CAS Access to Rank 3; Bank 5 event=0xb3,umask=5 01 unc_m_rd_cas_rank3.bank6 uncore memory RD_CAS Access to Rank 3; Bank 6 event=0xb3,umask=6 01 unc_m_rd_cas_rank3.bank7 uncore memory RD_CAS Access to Rank 3; Bank 7 event=0xb3,umask=7 01 unc_m_rd_cas_rank3.bank8 uncore memory RD_CAS Access to Rank 3; Bank 8 event=0xb3,umask=8 01 unc_m_rd_cas_rank3.bank9 uncore memory RD_CAS Access to Rank 3; Bank 9 event=0xb3,umask=9 01 unc_m_rd_cas_rank3.bankg0 uncore memory RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3) event=0xb3,umask=0x11 01 unc_m_rd_cas_rank3.bankg1 uncore memory RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7) event=0xb3,umask=0x12 01 unc_m_rd_cas_rank3.bankg2 uncore memory RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11) event=0xb3,umask=0x13 01 unc_m_rd_cas_rank3.bankg3 uncore memory RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15) event=0xb3,umask=0x14 01 unc_m_rd_cas_rank4.allbanks uncore memory RD_CAS Access to Rank 4; All Banks event=0xb4,umask=0x10 01 unc_m_rd_cas_rank4.bank0 uncore memory RD_CAS Access to Rank 4; Bank 0 event=0xb4 01 unc_m_rd_cas_rank4.bank1 uncore memory RD_CAS Access to Rank 4; Bank 1 event=0xb4,umask=1 01 unc_m_rd_cas_rank4.bank10 uncore memory RD_CAS Access to Rank 4; Bank 10 event=0xb4,umask=0xa 01 unc_m_rd_cas_rank4.bank11 uncore memory RD_CAS Access to Rank 4; Bank 11 event=0xb4,umask=0xb 01 unc_m_rd_cas_rank4.bank12 uncore memory RD_CAS Access to Rank 4; Bank 12 event=0xb4,umask=0xc 01 unc_m_rd_cas_rank4.bank13 uncore memory RD_CAS Access to Rank 4; Bank 13 event=0xb4,umask=0xd 01 unc_m_rd_cas_rank4.bank14 uncore memory RD_CAS Access to Rank 4; Bank 14 event=0xb4,umask=0xe 01 unc_m_rd_cas_rank4.bank15 uncore memory RD_CAS Access to Rank 4; Bank 15 event=0xb4,umask=0xf 01 unc_m_rd_cas_rank4.bank2 uncore memory RD_CAS Access to Rank 4; Bank 2 event=0xb4,umask=2 01 unc_m_rd_cas_rank4.bank3 uncore memory RD_CAS Access to Rank 4; Bank 3 event=0xb4,umask=3 01 unc_m_rd_cas_rank4.bank4 uncore memory RD_CAS Access to Rank 4; Bank 4 event=0xb4,umask=4 01 unc_m_rd_cas_rank4.bank5 uncore memory RD_CAS Access to Rank 4; Bank 5 event=0xb4,umask=5 01 unc_m_rd_cas_rank4.bank6 uncore memory RD_CAS Access to Rank 4; Bank 6 event=0xb4,umask=6 01 unc_m_rd_cas_rank4.bank7 uncore memory RD_CAS Access to Rank 4; Bank 7 event=0xb4,umask=7 01 unc_m_rd_cas_rank4.bank8 uncore memory RD_CAS Access to Rank 4; Bank 8 event=0xb4,umask=8 01 unc_m_rd_cas_rank4.bank9 uncore memory RD_CAS Access to Rank 4; Bank 9 event=0xb4,umask=9 01 unc_m_rd_cas_rank4.bankg0 uncore memory RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xb4,umask=0x11 01 unc_m_rd_cas_rank4.bankg1 uncore memory RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xb4,umask=0x12 01 unc_m_rd_cas_rank4.bankg2 uncore memory RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xb4,umask=0x13 01 unc_m_rd_cas_rank4.bankg3 uncore memory RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xb4,umask=0x14 01 unc_m_rd_cas_rank5.allbanks uncore memory RD_CAS Access to Rank 5; All Banks event=0xb5,umask=0x10 01 unc_m_rd_cas_rank5.bank0 uncore memory RD_CAS Access to Rank 5; Bank 0 event=0xb5 01 unc_m_rd_cas_rank5.bank1 uncore memory RD_CAS Access to Rank 5; Bank 1 event=0xb5,umask=1 01 unc_m_rd_cas_rank5.bank10 uncore memory RD_CAS Access to Rank 5; Bank 10 event=0xb5,umask=0xa 01 unc_m_rd_cas_rank5.bank11 uncore memory RD_CAS Access to Rank 5; Bank 11 event=0xb5,umask=0xb 01 unc_m_rd_cas_rank5.bank12 uncore memory RD_CAS Access to Rank 5; Bank 12 event=0xb5,umask=0xc 01 unc_m_rd_cas_rank5.bank13 uncore memory RD_CAS Access to Rank 5; Bank 13 event=0xb5,umask=0xd 01 unc_m_rd_cas_rank5.bank14 uncore memory RD_CAS Access to Rank 5; Bank 14 event=0xb5,umask=0xe 01 unc_m_rd_cas_rank5.bank15 uncore memory RD_CAS Access to Rank 5; Bank 15 event=0xb5,umask=0xf 01 unc_m_rd_cas_rank5.bank2 uncore memory RD_CAS Access to Rank 5; Bank 2 event=0xb5,umask=2 01 unc_m_rd_cas_rank5.bank3 uncore memory RD_CAS Access to Rank 5; Bank 3 event=0xb5,umask=3 01 unc_m_rd_cas_rank5.bank4 uncore memory RD_CAS Access to Rank 5; Bank 4 event=0xb5,umask=4 01 unc_m_rd_cas_rank5.bank5 uncore memory RD_CAS Access to Rank 5; Bank 5 event=0xb5,umask=5 01 unc_m_rd_cas_rank5.bank6 uncore memory RD_CAS Access to Rank 5; Bank 6 event=0xb5,umask=6 01 unc_m_rd_cas_rank5.bank7 uncore memory RD_CAS Access to Rank 5; Bank 7 event=0xb5,umask=7 01 unc_m_rd_cas_rank5.bank8 uncore memory RD_CAS Access to Rank 5; Bank 8 event=0xb5,umask=8 01 unc_m_rd_cas_rank5.bank9 uncore memory RD_CAS Access to Rank 5; Bank 9 event=0xb5,umask=9 01 unc_m_rd_cas_rank5.bankg0 uncore memory RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xb5,umask=0x11 01 unc_m_rd_cas_rank5.bankg1 uncore memory RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xb5,umask=0x12 01 unc_m_rd_cas_rank5.bankg2 uncore memory RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xb5,umask=0x13 01 unc_m_rd_cas_rank5.bankg3 uncore memory RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xb5,umask=0x14 01 unc_m_rd_cas_rank6.allbanks uncore memory RD_CAS Access to Rank 6; All Banks event=0xb6,umask=0x10 01 unc_m_rd_cas_rank6.bank0 uncore memory RD_CAS Access to Rank 6; Bank 0 event=0xb6 01 unc_m_rd_cas_rank6.bank1 uncore memory RD_CAS Access to Rank 6; Bank 1 event=0xb6,umask=1 01 unc_m_rd_cas_rank6.bank10 uncore memory RD_CAS Access to Rank 6; Bank 10 event=0xb6,umask=0xa 01 unc_m_rd_cas_rank6.bank11 uncore memory RD_CAS Access to Rank 6; Bank 11 event=0xb6,umask=0xb 01 unc_m_rd_cas_rank6.bank12 uncore memory RD_CAS Access to Rank 6; Bank 12 event=0xb6,umask=0xc 01 unc_m_rd_cas_rank6.bank13 uncore memory RD_CAS Access to Rank 6; Bank 13 event=0xb6,umask=0xd 01 unc_m_rd_cas_rank6.bank14 uncore memory RD_CAS Access to Rank 6; Bank 14 event=0xb6,umask=0xe 01 unc_m_rd_cas_rank6.bank15 uncore memory RD_CAS Access to Rank 6; Bank 15 event=0xb6,umask=0xf 01 unc_m_rd_cas_rank6.bank2 uncore memory RD_CAS Access to Rank 6; Bank 2 event=0xb6,umask=2 01 unc_m_rd_cas_rank6.bank3 uncore memory RD_CAS Access to Rank 6; Bank 3 event=0xb6,umask=3 01 unc_m_rd_cas_rank6.bank4 uncore memory RD_CAS Access to Rank 6; Bank 4 event=0xb6,umask=4 01 unc_m_rd_cas_rank6.bank5 uncore memory RD_CAS Access to Rank 6; Bank 5 event=0xb6,umask=5 01 unc_m_rd_cas_rank6.bank6 uncore memory RD_CAS Access to Rank 6; Bank 6 event=0xb6,umask=6 01 unc_m_rd_cas_rank6.bank7 uncore memory RD_CAS Access to Rank 6; Bank 7 event=0xb6,umask=7 01 unc_m_rd_cas_rank6.bank8 uncore memory RD_CAS Access to Rank 6; Bank 8 event=0xb6,umask=8 01 unc_m_rd_cas_rank6.bank9 uncore memory RD_CAS Access to Rank 6; Bank 9 event=0xb6,umask=9 01 unc_m_rd_cas_rank6.bankg0 uncore memory RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xb6,umask=0x11 01 unc_m_rd_cas_rank6.bankg1 uncore memory RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xb6,umask=0x12 01 unc_m_rd_cas_rank6.bankg2 uncore memory RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xb6,umask=0x13 01 unc_m_rd_cas_rank6.bankg3 uncore memory RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xb6,umask=0x14 01 unc_m_rd_cas_rank7.allbanks uncore memory RD_CAS Access to Rank 7; All Banks event=0xb7,umask=0x10 01 unc_m_rd_cas_rank7.bank0 uncore memory RD_CAS Access to Rank 7; Bank 0 event=0xb7 01 unc_m_rd_cas_rank7.bank1 uncore memory RD_CAS Access to Rank 7; Bank 1 event=0xb7,umask=1 01 unc_m_rd_cas_rank7.bank10 uncore memory RD_CAS Access to Rank 7; Bank 10 event=0xb7,umask=0xa 01 unc_m_rd_cas_rank7.bank11 uncore memory RD_CAS Access to Rank 7; Bank 11 event=0xb7,umask=0xb 01 unc_m_rd_cas_rank7.bank12 uncore memory RD_CAS Access to Rank 7; Bank 12 event=0xb7,umask=0xc 01 unc_m_rd_cas_rank7.bank13 uncore memory RD_CAS Access to Rank 7; Bank 13 event=0xb7,umask=0xd 01 unc_m_rd_cas_rank7.bank14 uncore memory RD_CAS Access to Rank 7; Bank 14 event=0xb7,umask=0xe 01 unc_m_rd_cas_rank7.bank15 uncore memory RD_CAS Access to Rank 7; Bank 15 event=0xb7,umask=0xf 01 unc_m_rd_cas_rank7.bank2 uncore memory RD_CAS Access to Rank 7; Bank 2 event=0xb7,umask=2 01 unc_m_rd_cas_rank7.bank3 uncore memory RD_CAS Access to Rank 7; Bank 3 event=0xb7,umask=3 01 unc_m_rd_cas_rank7.bank4 uncore memory RD_CAS Access to Rank 7; Bank 4 event=0xb7,umask=4 01 unc_m_rd_cas_rank7.bank5 uncore memory RD_CAS Access to Rank 7; Bank 5 event=0xb7,umask=5 01 unc_m_rd_cas_rank7.bank6 uncore memory RD_CAS Access to Rank 7; Bank 6 event=0xb7,umask=6 01 unc_m_rd_cas_rank7.bank7 uncore memory RD_CAS Access to Rank 7; Bank 7 event=0xb7,umask=7 01 unc_m_rd_cas_rank7.bank8 uncore memory RD_CAS Access to Rank 7; Bank 8 event=0xb7,umask=8 01 unc_m_rd_cas_rank7.bank9 uncore memory RD_CAS Access to Rank 7; Bank 9 event=0xb7,umask=9 01 unc_m_rd_cas_rank7.bankg0 uncore memory RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xb7,umask=0x11 01 unc_m_rd_cas_rank7.bankg1 uncore memory RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xb7,umask=0x12 01 unc_m_rd_cas_rank7.bankg2 uncore memory RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xb7,umask=0x13 01 unc_m_rd_cas_rank7.bankg3 uncore memory RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xb7,umask=0x14 01 unc_m_rpq_cycles_full uncore memory Read Pending Queue Full Cycles event=0x12 01 Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries unc_m_rpq_inserts uncore memory Read Pending Queue Allocations event=0x10 01 Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ unc_m_rpq_occupancy uncore memory Read Pending Queue Occupancy event=0x80 01 Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory unc_m_sb_accesses.fm_rd_cmps uncore memory Scoreboard Accesses; Write Accepts event=0xd2,umask=0x40 01 unc_m_sb_accesses.fm_wr_cmps uncore memory Scoreboard Accesses; Write Rejects event=0xd2,umask=0x80 01 unc_m_sb_accesses.nm_rd_cmps uncore memory Scoreboard Accesses; FM read completions event=0xd2,umask=0x10 01 unc_m_sb_accesses.nm_wr_cmps uncore memory Scoreboard Accesses; FM write completions event=0xd2,umask=0x20 01 unc_m_sb_accesses.rd_accepts uncore memory Scoreboard Accesses; Read Accepts event=0xd2,umask=1 01 unc_m_sb_accesses.rd_rejects uncore memory Scoreboard Accesses; Read Rejects event=0xd2,umask=2 01 unc_m_sb_accesses.wr_accepts uncore memory Scoreboard Accesses; NM read completions event=0xd2,umask=4 01 unc_m_sb_accesses.wr_rejects uncore memory Scoreboard Accesses; NM write completions event=0xd2,umask=8 01 unc_m_sb_canary.alloc uncore memory Alloc event=0xd9,umask=1 01 unc_m_sb_canary.dealloc uncore memory Dealloc event=0xd9,umask=2 01 unc_m_sb_canary.fmrd_starved uncore memory Far Mem Read Starved event=0xd9,umask=0x40 01 unc_m_sb_canary.fmwr_starved uncore memory Far Mem Write Starved event=0xd9,umask=0x80 01 unc_m_sb_canary.nmrd_starved uncore memory Near Mem Read Starved event=0xd9,umask=0x10 01 unc_m_sb_canary.nmwr_starved uncore memory Near Mem Write Starved event=0xd9,umask=0x20 01 unc_m_sb_canary.rej uncore memory Reject event=0xd9,umask=4 01 unc_m_sb_canary.vld uncore memory Valid event=0xd9,umask=8 01 unc_m_sb_cycles_full uncore memory Scoreboard Cycles Full event=0xd1 01 unc_m_sb_cycles_ne uncore memory Scoreboard Cycles Not-Empty event=0xd0 01 unc_m_sb_inserts.block_rds uncore memory Scoreboard Inserts; Block region reads event=0xd6,umask=0x10 01 unc_m_sb_inserts.block_wrs uncore memory Scoreboard Inserts; Block region writes event=0xd6,umask=0x20 01 unc_m_sb_inserts.dealloc uncore memory Scoreboard Inserts; Dealloc all commands (for error flows) event=0xd6,umask=0x40 01 unc_m_sb_inserts.patrol uncore memory Scoreboard Inserts; Patrol inserts event=0xd6,umask=0x80 01 unc_m_sb_inserts.pmm_rds uncore memory Scoreboard Inserts; Persistent Mem reads event=0xd6,umask=4 01 unc_m_sb_inserts.pmm_wrs uncore memory Scoreboard Inserts; Persistent Mem writes event=0xd6,umask=8 01 unc_m_sb_inserts.rds uncore memory Scoreboard Inserts; Reads event=0xd6,umask=1 01 unc_m_sb_inserts.wrs uncore memory Scoreboard Inserts; Writes event=0xd6,umask=2 01 unc_m_sb_occupancy.block_rds uncore memory Scoreboard Occupancy; Block region reads event=0xd5,umask=0x20 01 unc_m_sb_occupancy.block_wrs uncore memory Scoreboard Occupancy; Block region writes event=0xd5,umask=0x40 01 unc_m_sb_occupancy.patrol uncore memory Scoreboard Occupancy; Patrol event=0xd5,umask=0x80 01 unc_m_sb_occupancy.pmm_rds uncore memory Scoreboard Occupancy; Persistent Mem reads event=0xd5,umask=4 01 unc_m_sb_occupancy.pmm_wrs uncore memory Scoreboard Occupancy; Persistent Mem writes event=0xd5,umask=8 01 unc_m_sb_occupancy.rds uncore memory Scoreboard Occupancy; Reads event=0xd5,umask=1 01 unc_m_sb_occupancy.wrs uncore memory Scoreboard Occupancy; Writes event=0xd5,umask=2 01 unc_m_sb_reject.fm_addr_cnflt uncore memory Number of Scoreboard Requests Rejected; FM requests rejected due to full address conflict event=0xd4,umask=2 01 unc_m_sb_reject.nm_set_cnflt uncore memory Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict event=0xd4,umask=1 01 unc_m_sb_reject.patrol_set_cnflt uncore memory Number of Scoreboard Requests Rejected; Patrol requests rejected due to set conflict event=0xd4,umask=4 01 unc_m_sb_strv_alloc.fmrd_clr uncore memory Far Mem Read - Clear event=0xd7,umask=0x20 01 unc_m_sb_strv_alloc.fmrd_set uncore memory Far Mem Read - Set event=0xd7,umask=2 01 unc_m_sb_strv_alloc.fmwr_clr uncore memory Far Mem Write - Clear event=0xd7,umask=0x80 01 unc_m_sb_strv_alloc.fmwr_set uncore memory Far Mem Write - Set event=0xd7,umask=8 01 unc_m_sb_strv_alloc.nmrd_clr uncore memory Near Mem Read - Clear event=0xd7,umask=0x10 01 unc_m_sb_strv_alloc.nmrd_set uncore memory Near Mem Read - Set event=0xd7,umask=1 01 unc_m_sb_strv_alloc.nmwr_clr uncore memory Near Mem Write - Clear event=0xd7,umask=0x40 01 unc_m_sb_strv_alloc.nmwr_set uncore memory Near Mem Write - Set event=0xd7,umask=4 01 unc_m_sb_strv_occ.fmrd uncore memory Far Mem Read event=0xd8,umask=2 01 unc_m_sb_strv_occ.fmwr uncore memory Far Mem Write event=0xd8,umask=8 01 unc_m_sb_strv_occ.nmrd uncore memory Near Mem Read event=0xd8,umask=1 01 unc_m_sb_strv_occ.nmwr uncore memory Near Mem Write event=0xd8,umask=4 01 unc_m_sb_tagged.ddr4_cmp uncore memory UNC_M_SB_TAGGED.DDR4_CMP event=0xdd,umask=8 01 unc_m_sb_tagged.new uncore memory UNC_M_SB_TAGGED.NEW event=0xdd,umask=1 01 unc_m_sb_tagged.occ uncore memory UNC_M_SB_TAGGED.OCC event=0xdd,umask=0x80 01 unc_m_sb_tagged.pmm0_cmp uncore memory UNC_M_SB_TAGGED.PMM0_CMP event=0xdd,umask=0x10 01 unc_m_sb_tagged.pmm1_cmp uncore memory UNC_M_SB_TAGGED.PMM1_CMP event=0xdd,umask=0x20 01 unc_m_sb_tagged.pmm2_cmp uncore memory UNC_M_SB_TAGGED.PMM2_CMP event=0xdd,umask=0x40 01 unc_m_sb_tagged.rd_hit uncore memory UNC_M_SB_TAGGED.RD_HIT event=0xdd,umask=2 01 unc_m_sb_tagged.rd_miss uncore memory UNC_M_SB_TAGGED.RD_MISS event=0xdd,umask=4 01 unc_m_tagchk.hit uncore memory All hits to Near Memory(DRAM cache) in Memory Mode event=0xd3,umask=1 01 Tag Check; Hit unc_m_tagchk.miss_clean uncore memory All Clean line misses to Near Memory(DRAM cache) in Memory Mode event=0xd3,umask=2 01 Tag Check; Clean unc_m_tagchk.miss_dirty uncore memory All dirty line misses to Near Memory(DRAM cache) in Memory Mode event=0xd3,umask=4 01 Tag Check; Dirty unc_m_wpq_cycles_full uncore memory Write Pending Queue Full Cycles event=0x22 01 Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_ne uncore memory Write Pending Queue Not Empty event=0x21 01 Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_inserts uncore memory Write Pending Queue Allocations event=0x20 01 Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC unc_m_wpq_occupancy uncore memory Write Pending Queue Occupancy event=0x81 01 Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_m_wr_cas_rank0.allbanks uncore memory WR_CAS Access to Rank 0; All Banks event=0xb8,umask=0x10 01 unc_m_wr_cas_rank0.bank0 uncore memory WR_CAS Access to Rank 0; Bank 0 event=0xb8 01 unc_m_wr_cas_rank0.bank1 uncore memory WR_CAS Access to Rank 0; Bank 1 event=0xb8,umask=1 01 unc_m_wr_cas_rank0.bank10 uncore memory WR_CAS Access to Rank 0; Bank 10 event=0xb8,umask=0xa 01 unc_m_wr_cas_rank0.bank11 uncore memory WR_CAS Access to Rank 0; Bank 11 event=0xb8,umask=0xb 01 unc_m_wr_cas_rank0.bank12 uncore memory WR_CAS Access to Rank 0; Bank 12 event=0xb8,umask=0xc 01 unc_m_wr_cas_rank0.bank13 uncore memory WR_CAS Access to Rank 0; Bank 13 event=0xb8,umask=0xd 01 unc_m_wr_cas_rank0.bank14 uncore memory WR_CAS Access to Rank 0; Bank 14 event=0xb8,umask=0xe 01 unc_m_wr_cas_rank0.bank15 uncore memory WR_CAS Access to Rank 0; Bank 15 event=0xb8,umask=0xf 01 unc_m_wr_cas_rank0.bank2 uncore memory WR_CAS Access to Rank 0; Bank 2 event=0xb8,umask=2 01 unc_m_wr_cas_rank0.bank3 uncore memory WR_CAS Access to Rank 0; Bank 3 event=0xb8,umask=3 01 unc_m_wr_cas_rank0.bank4 uncore memory WR_CAS Access to Rank 0; Bank 4 event=0xb8,umask=4 01 unc_m_wr_cas_rank0.bank5 uncore memory WR_CAS Access to Rank 0; Bank 5 event=0xb8,umask=5 01 unc_m_wr_cas_rank0.bank6 uncore memory WR_CAS Access to Rank 0; Bank 6 event=0xb8,umask=6 01 unc_m_wr_cas_rank0.bank7 uncore memory WR_CAS Access to Rank 0; Bank 7 event=0xb8,umask=7 01 unc_m_wr_cas_rank0.bank8 uncore memory WR_CAS Access to Rank 0; Bank 8 event=0xb8,umask=8 01 unc_m_wr_cas_rank0.bank9 uncore memory WR_CAS Access to Rank 0; Bank 9 event=0xb8,umask=9 01 unc_m_wr_cas_rank0.bankg0 uncore memory WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb8,umask=0x11 01 unc_m_wr_cas_rank0.bankg1 uncore memory WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb8,umask=0x12 01 unc_m_wr_cas_rank0.bankg2 uncore memory WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb8,umask=0x13 01 unc_m_wr_cas_rank0.bankg3 uncore memory WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb8,umask=0x14 01 unc_m_wr_cas_rank1.allbanks uncore memory WR_CAS Access to Rank 1; All Banks event=0xb9,umask=0x10 01 unc_m_wr_cas_rank1.bank0 uncore memory WR_CAS Access to Rank 1; Bank 0 event=0xb9 01 unc_m_wr_cas_rank1.bank1 uncore memory WR_CAS Access to Rank 1; Bank 1 event=0xb9,umask=1 01 unc_m_wr_cas_rank1.bank10 uncore memory WR_CAS Access to Rank 1; Bank 10 event=0xb9,umask=0xa 01 unc_m_wr_cas_rank1.bank11 uncore memory WR_CAS Access to Rank 1; Bank 11 event=0xb9,umask=0xb 01 unc_m_wr_cas_rank1.bank12 uncore memory WR_CAS Access to Rank 1; Bank 12 event=0xb9,umask=0xc 01 unc_m_wr_cas_rank1.bank13 uncore memory WR_CAS Access to Rank 1; Bank 13 event=0xb9,umask=0xd 01 unc_m_wr_cas_rank1.bank14 uncore memory WR_CAS Access to Rank 1; Bank 14 event=0xb9,umask=0xe 01 unc_m_wr_cas_rank1.bank15 uncore memory WR_CAS Access to Rank 1; Bank 15 event=0xb9,umask=0xf 01 unc_m_wr_cas_rank1.bank2 uncore memory WR_CAS Access to Rank 1; Bank 2 event=0xb9,umask=2 01 unc_m_wr_cas_rank1.bank3 uncore memory WR_CAS Access to Rank 1; Bank 3 event=0xb9,umask=3 01 unc_m_wr_cas_rank1.bank4 uncore memory WR_CAS Access to Rank 1; Bank 4 event=0xb9,umask=4 01 unc_m_wr_cas_rank1.bank5 uncore memory WR_CAS Access to Rank 1; Bank 5 event=0xb9,umask=5 01 unc_m_wr_cas_rank1.bank6 uncore memory WR_CAS Access to Rank 1; Bank 6 event=0xb9,umask=6 01 unc_m_wr_cas_rank1.bank7 uncore memory WR_CAS Access to Rank 1; Bank 7 event=0xb9,umask=7 01 unc_m_wr_cas_rank1.bank8 uncore memory WR_CAS Access to Rank 1; Bank 8 event=0xb9,umask=8 01 unc_m_wr_cas_rank1.bank9 uncore memory WR_CAS Access to Rank 1; Bank 9 event=0xb9,umask=9 01 unc_m_wr_cas_rank1.bankg0 uncore memory WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb9,umask=0x11 01 unc_m_wr_cas_rank1.bankg1 uncore memory WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb9,umask=0x12 01 unc_m_wr_cas_rank1.bankg2 uncore memory WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb9,umask=0x13 01 unc_m_wr_cas_rank1.bankg3 uncore memory WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb9,umask=0x14 01 unc_m_wr_cas_rank2.allbanks uncore memory WR_CAS Access to Rank 2; All Banks event=0xba,umask=0x10 01 unc_m_wr_cas_rank2.bank0 uncore memory WR_CAS Access to Rank 2; Bank 0 event=0xba 01 unc_m_wr_cas_rank2.bank1 uncore memory WR_CAS Access to Rank 2; Bank 1 event=0xba,umask=1 01 unc_m_wr_cas_rank2.bank10 uncore memory WR_CAS Access to Rank 2; Bank 10 event=0xba,umask=0xa 01 unc_m_wr_cas_rank2.bank11 uncore memory WR_CAS Access to Rank 2; Bank 11 event=0xba,umask=0xb 01 unc_m_wr_cas_rank2.bank12 uncore memory WR_CAS Access to Rank 2; Bank 12 event=0xba,umask=0xc 01 unc_m_wr_cas_rank2.bank13 uncore memory WR_CAS Access to Rank 2; Bank 13 event=0xba,umask=0xd 01 unc_m_wr_cas_rank2.bank14 uncore memory WR_CAS Access to Rank 2; Bank 14 event=0xba,umask=0xe 01 unc_m_wr_cas_rank2.bank15 uncore memory WR_CAS Access to Rank 2; Bank 15 event=0xba,umask=0xf 01 unc_m_wr_cas_rank2.bank2 uncore memory WR_CAS Access to Rank 2; Bank 2 event=0xba,umask=2 01 unc_m_wr_cas_rank2.bank3 uncore memory WR_CAS Access to Rank 2; Bank 3 event=0xba,umask=3 01 unc_m_wr_cas_rank2.bank4 uncore memory WR_CAS Access to Rank 2; Bank 4 event=0xba,umask=4 01 unc_m_wr_cas_rank2.bank5 uncore memory WR_CAS Access to Rank 2; Bank 5 event=0xba,umask=5 01 unc_m_wr_cas_rank2.bank6 uncore memory WR_CAS Access to Rank 2; Bank 6 event=0xba,umask=6 01 unc_m_wr_cas_rank2.bank7 uncore memory WR_CAS Access to Rank 2; Bank 7 event=0xba,umask=7 01 unc_m_wr_cas_rank2.bank8 uncore memory WR_CAS Access to Rank 2; Bank 8 event=0xba,umask=8 01 unc_m_wr_cas_rank2.bank9 uncore memory WR_CAS Access to Rank 2; Bank 9 event=0xba,umask=9 01 unc_m_wr_cas_rank2.bankg0 uncore memory WR_CAS Access to Rank 2; Bank Group 0 (Banks 0-3) event=0xba,umask=0x11 01 unc_m_wr_cas_rank2.bankg1 uncore memory WR_CAS Access to Rank 2; Bank Group 1 (Banks 4-7) event=0xba,umask=0x12 01 unc_m_wr_cas_rank2.bankg2 uncore memory WR_CAS Access to Rank 2; Bank Group 2 (Banks 8-11) event=0xba,umask=0x13 01 unc_m_wr_cas_rank2.bankg3 uncore memory WR_CAS Access to Rank 2; Bank Group 3 (Banks 12-15) event=0xba,umask=0x14 01 unc_m_wr_cas_rank3.allbanks uncore memory WR_CAS Access to Rank 3; All Banks event=0xbb,umask=0x10 01 unc_m_wr_cas_rank3.bank0 uncore memory WR_CAS Access to Rank 3; Bank 0 event=0xbb 01 unc_m_wr_cas_rank3.bank1 uncore memory WR_CAS Access to Rank 3; Bank 1 event=0xbb,umask=1 01 unc_m_wr_cas_rank3.bank10 uncore memory WR_CAS Access to Rank 3; Bank 10 event=0xbb,umask=0xa 01 unc_m_wr_cas_rank3.bank11 uncore memory WR_CAS Access to Rank 3; Bank 11 event=0xbb,umask=0xb 01 unc_m_wr_cas_rank3.bank12 uncore memory WR_CAS Access to Rank 3; Bank 12 event=0xbb,umask=0xc 01 unc_m_wr_cas_rank3.bank13 uncore memory WR_CAS Access to Rank 3; Bank 13 event=0xbb,umask=0xd 01 unc_m_wr_cas_rank3.bank14 uncore memory WR_CAS Access to Rank 3; Bank 14 event=0xbb,umask=0xe 01 unc_m_wr_cas_rank3.bank15 uncore memory WR_CAS Access to Rank 3; Bank 15 event=0xbb,umask=0xf 01 unc_m_wr_cas_rank3.bank2 uncore memory WR_CAS Access to Rank 3; Bank 2 event=0xbb,umask=2 01 unc_m_wr_cas_rank3.bank3 uncore memory WR_CAS Access to Rank 3; Bank 3 event=0xbb,umask=3 01 unc_m_wr_cas_rank3.bank4 uncore memory WR_CAS Access to Rank 3; Bank 4 event=0xbb,umask=4 01 unc_m_wr_cas_rank3.bank5 uncore memory WR_CAS Access to Rank 3; Bank 5 event=0xbb,umask=5 01 unc_m_wr_cas_rank3.bank6 uncore memory WR_CAS Access to Rank 3; Bank 6 event=0xbb,umask=6 01 unc_m_wr_cas_rank3.bank7 uncore memory WR_CAS Access to Rank 3; Bank 7 event=0xbb,umask=7 01 unc_m_wr_cas_rank3.bank8 uncore memory WR_CAS Access to Rank 3; Bank 8 event=0xbb,umask=8 01 unc_m_wr_cas_rank3.bank9 uncore memory WR_CAS Access to Rank 3; Bank 9 event=0xbb,umask=9 01 unc_m_wr_cas_rank3.bankg0 uncore memory WR_CAS Access to Rank 3; Bank Group 0 (Banks 0-3) event=0xbb,umask=0x11 01 unc_m_wr_cas_rank3.bankg1 uncore memory WR_CAS Access to Rank 3; Bank Group 1 (Banks 4-7) event=0xbb,umask=0x12 01 unc_m_wr_cas_rank3.bankg2 uncore memory WR_CAS Access to Rank 3; Bank Group 2 (Banks 8-11) event=0xbb,umask=0x13 01 unc_m_wr_cas_rank3.bankg3 uncore memory WR_CAS Access to Rank 3; Bank Group 3 (Banks 12-15) event=0xbb,umask=0x14 01 unc_m_wr_cas_rank4.allbanks uncore memory WR_CAS Access to Rank 4; All Banks event=0xbc,umask=0x10 01 unc_m_wr_cas_rank4.bank0 uncore memory WR_CAS Access to Rank 4; Bank 0 event=0xbc 01 unc_m_wr_cas_rank4.bank1 uncore memory WR_CAS Access to Rank 4; Bank 1 event=0xbc,umask=1 01 unc_m_wr_cas_rank4.bank10 uncore memory WR_CAS Access to Rank 4; Bank 10 event=0xbc,umask=0xa 01 unc_m_wr_cas_rank4.bank11 uncore memory WR_CAS Access to Rank 4; Bank 11 event=0xbc,umask=0xb 01 unc_m_wr_cas_rank4.bank12 uncore memory WR_CAS Access to Rank 4; Bank 12 event=0xbc,umask=0xc 01 unc_m_wr_cas_rank4.bank13 uncore memory WR_CAS Access to Rank 4; Bank 13 event=0xbc,umask=0xd 01 unc_m_wr_cas_rank4.bank14 uncore memory WR_CAS Access to Rank 4; Bank 14 event=0xbc,umask=0xe 01 unc_m_wr_cas_rank4.bank15 uncore memory WR_CAS Access to Rank 4; Bank 15 event=0xbc,umask=0xf 01 unc_m_wr_cas_rank4.bank2 uncore memory WR_CAS Access to Rank 4; Bank 2 event=0xbc,umask=2 01 unc_m_wr_cas_rank4.bank3 uncore memory WR_CAS Access to Rank 4; Bank 3 event=0xbc,umask=3 01 unc_m_wr_cas_rank4.bank4 uncore memory WR_CAS Access to Rank 4; Bank 4 event=0xbc,umask=4 01 unc_m_wr_cas_rank4.bank5 uncore memory WR_CAS Access to Rank 4; Bank 5 event=0xbc,umask=5 01 unc_m_wr_cas_rank4.bank6 uncore memory WR_CAS Access to Rank 4; Bank 6 event=0xbc,umask=6 01 unc_m_wr_cas_rank4.bank7 uncore memory WR_CAS Access to Rank 4; Bank 7 event=0xbc,umask=7 01 unc_m_wr_cas_rank4.bank8 uncore memory WR_CAS Access to Rank 4; Bank 8 event=0xbc,umask=8 01 unc_m_wr_cas_rank4.bank9 uncore memory WR_CAS Access to Rank 4; Bank 9 event=0xbc,umask=9 01 unc_m_wr_cas_rank4.bankg0 uncore memory WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xbc,umask=0x11 01 unc_m_wr_cas_rank4.bankg1 uncore memory WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xbc,umask=0x12 01 unc_m_wr_cas_rank4.bankg2 uncore memory WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xbc,umask=0x13 01 unc_m_wr_cas_rank4.bankg3 uncore memory WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xbc,umask=0x14 01 unc_m_wr_cas_rank5.allbanks uncore memory WR_CAS Access to Rank 5; All Banks event=0xbd,umask=0x10 01 unc_m_wr_cas_rank5.bank0 uncore memory WR_CAS Access to Rank 5; Bank 0 event=0xbd 01 unc_m_wr_cas_rank5.bank1 uncore memory WR_CAS Access to Rank 5; Bank 1 event=0xbd,umask=1 01 unc_m_wr_cas_rank5.bank10 uncore memory WR_CAS Access to Rank 5; Bank 10 event=0xbd,umask=0xa 01 unc_m_wr_cas_rank5.bank11 uncore memory WR_CAS Access to Rank 5; Bank 11 event=0xbd,umask=0xb 01 unc_m_wr_cas_rank5.bank12 uncore memory WR_CAS Access to Rank 5; Bank 12 event=0xbd,umask=0xc 01 unc_m_wr_cas_rank5.bank13 uncore memory WR_CAS Access to Rank 5; Bank 13 event=0xbd,umask=0xd 01 unc_m_wr_cas_rank5.bank14 uncore memory WR_CAS Access to Rank 5; Bank 14 event=0xbd,umask=0xe 01 unc_m_wr_cas_rank5.bank15 uncore memory WR_CAS Access to Rank 5; Bank 15 event=0xbd,umask=0xf 01 unc_m_wr_cas_rank5.bank2 uncore memory WR_CAS Access to Rank 5; Bank 2 event=0xbd,umask=2 01 unc_m_wr_cas_rank5.bank3 uncore memory WR_CAS Access to Rank 5; Bank 3 event=0xbd,umask=3 01 unc_m_wr_cas_rank5.bank4 uncore memory WR_CAS Access to Rank 5; Bank 4 event=0xbd,umask=4 01 unc_m_wr_cas_rank5.bank5 uncore memory WR_CAS Access to Rank 5; Bank 5 event=0xbd,umask=5 01 unc_m_wr_cas_rank5.bank6 uncore memory WR_CAS Access to Rank 5; Bank 6 event=0xbd,umask=6 01 unc_m_wr_cas_rank5.bank7 uncore memory WR_CAS Access to Rank 5; Bank 7 event=0xbd,umask=7 01 unc_m_wr_cas_rank5.bank8 uncore memory WR_CAS Access to Rank 5; Bank 8 event=0xbd,umask=8 01 unc_m_wr_cas_rank5.bank9 uncore memory WR_CAS Access to Rank 5; Bank 9 event=0xbd,umask=9 01 unc_m_wr_cas_rank5.bankg0 uncore memory WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xbd,umask=0x11 01 unc_m_wr_cas_rank5.bankg1 uncore memory WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xbd,umask=0x12 01 unc_m_wr_cas_rank5.bankg2 uncore memory WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xbd,umask=0x13 01 unc_m_wr_cas_rank5.bankg3 uncore memory WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xbd,umask=0x14 01 unc_m_wr_cas_rank6.allbanks uncore memory WR_CAS Access to Rank 6; All Banks event=0xbe,umask=0x10 01 unc_m_wr_cas_rank6.bank0 uncore memory WR_CAS Access to Rank 6; Bank 0 event=0xbe 01 unc_m_wr_cas_rank6.bank1 uncore memory WR_CAS Access to Rank 6; Bank 1 event=0xbe,umask=1 01 unc_m_wr_cas_rank6.bank10 uncore memory WR_CAS Access to Rank 6; Bank 10 event=0xbe,umask=0xa 01 unc_m_wr_cas_rank6.bank11 uncore memory WR_CAS Access to Rank 6; Bank 11 event=0xbe,umask=0xb 01 unc_m_wr_cas_rank6.bank12 uncore memory WR_CAS Access to Rank 6; Bank 12 event=0xbe,umask=0xc 01 unc_m_wr_cas_rank6.bank13 uncore memory WR_CAS Access to Rank 6; Bank 13 event=0xbe,umask=0xd 01 unc_m_wr_cas_rank6.bank14 uncore memory WR_CAS Access to Rank 6; Bank 14 event=0xbe,umask=0xe 01 unc_m_wr_cas_rank6.bank15 uncore memory WR_CAS Access to Rank 6; Bank 15 event=0xbe,umask=0xf 01 unc_m_wr_cas_rank6.bank2 uncore memory WR_CAS Access to Rank 6; Bank 2 event=0xbe,umask=2 01 unc_m_wr_cas_rank6.bank3 uncore memory WR_CAS Access to Rank 6; Bank 3 event=0xbe,umask=3 01 unc_m_wr_cas_rank6.bank4 uncore memory WR_CAS Access to Rank 6; Bank 4 event=0xbe,umask=4 01 unc_m_wr_cas_rank6.bank5 uncore memory WR_CAS Access to Rank 6; Bank 5 event=0xbe,umask=5 01 unc_m_wr_cas_rank6.bank6 uncore memory WR_CAS Access to Rank 6; Bank 6 event=0xbe,umask=6 01 unc_m_wr_cas_rank6.bank7 uncore memory WR_CAS Access to Rank 6; Bank 7 event=0xbe,umask=7 01 unc_m_wr_cas_rank6.bank8 uncore memory WR_CAS Access to Rank 6; Bank 8 event=0xbe,umask=8 01 unc_m_wr_cas_rank6.bank9 uncore memory WR_CAS Access to Rank 6; Bank 9 event=0xbe,umask=9 01 unc_m_wr_cas_rank6.bankg0 uncore memory WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xbe,umask=0x11 01 unc_m_wr_cas_rank6.bankg1 uncore memory WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xbe,umask=0x12 01 unc_m_wr_cas_rank6.bankg2 uncore memory WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xbe,umask=0x13 01 unc_m_wr_cas_rank6.bankg3 uncore memory WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xbe,umask=0x14 01 unc_m_wr_cas_rank7.allbanks uncore memory WR_CAS Access to Rank 7; All Banks event=0xbf,umask=0x10 01 unc_m_wr_cas_rank7.bank0 uncore memory WR_CAS Access to Rank 7; Bank 0 event=0xbf 01 unc_m_wr_cas_rank7.bank1 uncore memory WR_CAS Access to Rank 7; Bank 1 event=0xbf,umask=1 01 unc_m_wr_cas_rank7.bank10 uncore memory WR_CAS Access to Rank 7; Bank 10 event=0xbf,umask=0xa 01 unc_m_wr_cas_rank7.bank11 uncore memory WR_CAS Access to Rank 7; Bank 11 event=0xbf,umask=0xb 01 unc_m_wr_cas_rank7.bank12 uncore memory WR_CAS Access to Rank 7; Bank 12 event=0xbf,umask=0xc 01 unc_m_wr_cas_rank7.bank13 uncore memory WR_CAS Access to Rank 7; Bank 13 event=0xbf,umask=0xd 01 unc_m_wr_cas_rank7.bank14 uncore memory WR_CAS Access to Rank 7; Bank 14 event=0xbf,umask=0xe 01 unc_m_wr_cas_rank7.bank15 uncore memory WR_CAS Access to Rank 7; Bank 15 event=0xbf,umask=0xf 01 unc_m_wr_cas_rank7.bank2 uncore memory WR_CAS Access to Rank 7; Bank 2 event=0xbf,umask=2 01 unc_m_wr_cas_rank7.bank3 uncore memory WR_CAS Access to Rank 7; Bank 3 event=0xbf,umask=3 01 unc_m_wr_cas_rank7.bank4 uncore memory WR_CAS Access to Rank 7; Bank 4 event=0xbf,umask=4 01 unc_m_wr_cas_rank7.bank5 uncore memory WR_CAS Access to Rank 7; Bank 5 event=0xbf,umask=5 01 unc_m_wr_cas_rank7.bank6 uncore memory WR_CAS Access to Rank 7; Bank 6 event=0xbf,umask=6 01 unc_m_wr_cas_rank7.bank7 uncore memory WR_CAS Access to Rank 7; Bank 7 event=0xbf,umask=7 01 unc_m_wr_cas_rank7.bank8 uncore memory WR_CAS Access to Rank 7; Bank 8 event=0xbf,umask=8 01 unc_m_wr_cas_rank7.bank9 uncore memory WR_CAS Access to Rank 7; Bank 9 event=0xbf,umask=9 01 unc_m_wr_cas_rank7.bankg0 uncore memory WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xbf,umask=0x11 01 unc_m_wr_cas_rank7.bankg1 uncore memory WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xbf,umask=0x12 01 unc_m_wr_cas_rank7.bankg2 uncore memory WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xbf,umask=0x13 01 unc_m_wr_cas_rank7.bankg3 uncore memory WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xbf,umask=0x14 01 unc_p_core_transition_cycles uncore power UNC_P_CORE_TRANSITION_CYCLES event=0x60 01 unc_p_demotions uncore power UNC_P_DEMOTIONS event=0x30 01 unc_p_fivr_ps_ps0_cycles uncore power Phase Shed 0 Cycles event=0x75 01 Cycles spent in phase-shedding power state 0 unc_p_fivr_ps_ps1_cycles uncore power Phase Shed 1 Cycles event=0x76 01 Cycles spent in phase-shedding power state 1 unc_p_fivr_ps_ps2_cycles uncore power Phase Shed 2 Cycles event=0x77 01 Cycles spent in phase-shedding power state 2 unc_p_fivr_ps_ps3_cycles uncore power Phase Shed 3 Cycles event=0x78 01 Cycles spent in phase-shedding power state 3 unc_p_mcp_prochot_cycles uncore power UNC_P_MCP_PROCHOT_CYCLES event=6 01 unc_p_pmax_throttled_cycles uncore power UNC_P_PMAX_THROTTLED_CYCLES event=7 01 unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C-State; C0 and C1 event=0x80,umask=0x40 01 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C-State; C3 event=0x80,umask=0x80 01 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C-State; C6 and C7 event=0x80,umask=0xc0 01 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_vr_hot_cycles uncore power VR Hot event=0x42 01 dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks event=8,period=100003,umask=1 00 Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed dtlb_load_misses.stlb_hit virtual memory Loads that miss the DTLB and hit the STLB event=8,period=2000003,umask=0x20 00 Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) dtlb_load_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake event=8,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load dtlb_load_misses.walk_completed virtual memory Load miss in all TLB levels causes a page walk that completes. (All page sizes) event=8,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_1g virtual memory Page walk completed due to a demand data load to a 1G page event=8,period=2000003,umask=8 00 Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand data load to a 2M/4M page event=8,period=2000003,umask=4 00 Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_4k virtual memory Page walk completed due to a demand data load to a 4K page event=8,period=2000003,umask=2 00 Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake event=8,period=2000003,umask=0x10 00 Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks event=0x49,period=100003,umask=1 00 Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed dtlb_store_misses.stlb_hit virtual memory Stores that miss the DTLB and hit the STLB event=0x49,period=100003,umask=0x20 00 Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) dtlb_store_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake event=0x49,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store dtlb_store_misses.walk_completed virtual memory Store misses in all TLB levels causes a page walk that completes. (All page sizes) event=0x49,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_1g virtual memory Page walk completed due to a demand data store to a 1G page event=0x49,period=100003,umask=8 00 Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand data store to a 2M/4M page event=0x49,period=100003,umask=4 00 Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_4k virtual memory Page walk completed due to a demand data store to a 4K page event=0x49,period=100003,umask=2 00 Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake event=0x49,period=2000003,umask=0x10 00 Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture ept.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type event=0x4f,period=2000003,umask=0x10 00 Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=1 00 Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=1 00 Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed itlb_misses.stlb_hit virtual memory Instruction fetch requests that miss the ITLB and hit the STLB event=0x85,period=100003,umask=0x20 00 itlb_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake event=0x85,cmask=1,period=100003,umask=0x10 00 Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture itlb_misses.walk_completed virtual memory Code miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x85,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_1g virtual memory Code miss in all TLB levels causes a page walk that completes. (1G) event=0x85,period=100003,umask=8 00 Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) event=0x85,period=100003,umask=4 00 Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) event=0x85,period=100003,umask=2 00 Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake event=0x85,period=100003,umask=0x10 00 Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=1 00 Counts the number of DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20 00 Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.) core_reject_l2q.any cache Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition event=0x31,period=200003 00 Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis dl1.dirty_eviction cache Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches event=0x51,period=200003,umask=1 00 Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back l2_reject_xq.any cache Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition event=0x30,period=200003 00 Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims) l2_request.all cache Counts the total number of L2 Cache accesses. Counts on a per core basis event=0x24,period=200003 00 Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis l2_request.hit cache Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis event=0x24,period=200003,umask=2 00 Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis l2_request.miss cache Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis event=0x24,period=200003,umask=1 00 Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis l2_request.rejects cache Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis event=0x24,period=200003,umask=4 00 Counts the number of L2 Cache accesses that miss the L2 and get BBL reject short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis longest_lat_cache.miss cache Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis event=0x2e,period=200003,umask=0x41 00 Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis longest_lat_cache.reference cache Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis event=0x2e,period=200003,umask=0x4f 00 Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis mem_bound_stalls.store_buffer_full cache Counts the number of cycles the core is stalled due to a store buffer being full event=0x34,period=200003,umask=0x40 00 mem_load_uops_retired.hitm cache Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x20 00 mem_load_uops_retired.l1_hit cache Counts the number of load uops retired that hit in the L1 data cache Supports address when precise (Precise event) event=0xd1,period=200003,umask=1 00 mem_load_uops_retired.l1_miss cache Counts the number of load uops retired that miss in the L1 data cache Supports address when precise (Precise event) event=0xd1,period=200003,umask=8 00 mem_load_uops_retired.l2_miss cache Counts the number of load uops retired that miss in the L2 cache Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x10 00 mem_uops_retired.all cache Counts the number of memory uops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x83 00 Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) Supports address when precise (Precise event) mem_uops_retired.split cache Counts the number of memory uops retired that were splits Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x43 00 mem_uops_retired.split_stores cache Counts the number of retired split store uops Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x42 00 ocr.all_code_rd.l3_hit cache Counts all code reads that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0044 00 ocr.all_code_rd.l3_hit.snoop_hitm cache Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0044 00 ocr.all_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0044 00 ocr.all_code_rd.l3_hit.snoop_hit_with_fwd cache Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0044 00 ocr.all_code_rd.l3_hit.snoop_miss cache Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0044 00 ocr.all_code_rd.l3_hit.snoop_not_needed cache Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0044 00 ocr.corewb_m.l3_hit cache Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3001F803C0000 00 ocr.demand_code_rd.l3_hit cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0004 00 ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004 00 ocr.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004 00 ocr.demand_code_rd.l3_hit.snoop_hit_with_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0004 00 ocr.demand_code_rd.l3_hit.snoop_miss cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0004 00 ocr.demand_code_rd.l3_hit.snoop_not_needed cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004 00 ocr.demand_data_and_l1pf_rd.l3_hit cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0001 00 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hitm cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 00 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hit_no_fwd cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 00 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hit_with_fwd cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001 00 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_miss cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001 00 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_not_needed cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001 00 ocr.demand_data_rd.l3_hit cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0001 10 ocr.demand_data_rd.l3_hit.snoop_hitm cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 10 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 10 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001 10 ocr.demand_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001 10 ocr.demand_data_rd.l3_hit.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001 10 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0002 00 ocr.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002 00 ocr.demand_rfo.l3_hit.snoop_hit_with_fwd cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0002 00 ocr.demand_rfo.l3_hit.snoop_miss cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0002 00 ocr.demand_rfo.l3_hit.snoop_not_needed cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002 00 ocr.full_streaming_wr.l3_hit cache Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x801F803C0000 00 ocr.hwpf_l1d_and_swpf.l3_hit.snoop_hitm cache Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0400 00 ocr.hwpf_l2_code_rd.l3_hit cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0040 00 ocr.hwpf_l2_code_rd.l3_hit.snoop_hitm cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0040 00 ocr.hwpf_l2_code_rd.l3_hit.snoop_hit_no_fwd cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0040 00 ocr.hwpf_l2_code_rd.l3_hit.snoop_hit_with_fwd cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0040 00 ocr.hwpf_l2_code_rd.l3_hit.snoop_miss cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0040 00 ocr.hwpf_l2_code_rd.l3_hit.snoop_not_needed cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0040 00 ocr.hwpf_l2_data_rd.l3_hit cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_hitm cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_no_fwd cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_miss cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_not_needed cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010 00 ocr.hwpf_l2_rfo.l3_hit cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_hitm cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_hit_no_fwd cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_hit_with_fwd cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_miss cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_not_needed cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020 00 ocr.l1wb_m.l3_hit cache Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1001F803C0000 00 ocr.l2wb_m.l3_hit cache Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2001F803C0000 00 ocr.partial_streaming_wr.l3_hit cache Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x401F803C0000 00 ocr.reads_to_core.l3_hit cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0477 00 ocr.reads_to_core.l3_hit.snoop_hitm cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0477 00 ocr.reads_to_core.l3_hit.snoop_hit_no_fwd cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0477 00 ocr.reads_to_core.l3_hit.snoop_hit_with_fwd cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0477 00 ocr.reads_to_core.l3_hit.snoop_miss cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0477 00 ocr.reads_to_core.l3_hit.snoop_not_needed cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0477 00 ocr.streaming_wr.l3_hit cache Counts streaming stores that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0800 00 ocr.uc_rd.l3_hit cache Counts uncached memory reads that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x101F803C0000 00 ocr.uc_rd.l3_hit.snoop_hitm cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x1010003C0000 00 ocr.uc_rd.l3_hit.snoop_hit_no_fwd cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x1004003C0000 00 ocr.uc_rd.l3_hit.snoop_hit_with_fwd cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x1008003C0000 00 ocr.uc_rd.l3_hit.snoop_miss cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x1002003C0000 00 ocr.uc_rd.l3_hit.snoop_not_needed cache Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1001003C0000 00 ocr.uc_wr.l3_hit cache Counts uncached memory writes that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x201F803C0000 00 cycles_div_busy.fpdiv floating point Counts the number of cycles the floating point divider is busy event=0xcd,period=200003,umask=2 00 Counts the number of cycles the floating point divider is busy. Does not imply a stall waiting for the divider baclears.any frontend Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches event=0xe6,period=200003,umask=1 00 Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches baclears.cond frontend Counts the number of BACLEARS due to a conditional jump event=0xe6,period=200003,umask=0x10 00 baclears.indirect frontend Counts the number of BACLEARS due to an indirect branch event=0xe6,period=200003,umask=2 00 baclears.return frontend Counts the number of BACLEARS due to a return branch event=0xe6,period=200003,umask=8 00 baclears.uncond frontend Counts the number of BACLEARS due to a direct, unconditional jump event=0xe6,period=200003,umask=4 00 decode_restriction.predecode_wrong frontend Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction event=0xe9,period=200003,umask=1 00 icache.hit frontend Counts the number of instruction cache hits event=0x80,period=200003,umask=1 00 Counts the number of requests that hit in the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line misalign_mem_ref.load_page_split memory Counts the number of misaligned load uops that are 4K page splits (Precise event) event=0x13,period=200003,umask=2 00 misalign_mem_ref.store_page_split memory Counts the number of misaligned store uops that are 4K page splits (Precise event) event=0x13,period=200003,umask=4 00 ocr.all_code_rd.l3_miss memory Counts all code reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000044 00 ocr.all_code_rd.l3_miss_local memory Counts all code reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000044 00 ocr.corewb_m.l3_miss memory Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3002184000000 00 ocr.corewb_m.l3_miss_local memory Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3002184000000 00 ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000004 00 ocr.demand_code_rd.l3_miss_local memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000004 00 ocr.demand_data_and_l1pf_rd.l3_miss memory Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000001 00 ocr.demand_data_and_l1pf_rd.l3_miss_local memory Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000001 00 ocr.demand_data_rd.l3_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000001 10 ocr.demand_data_rd.l3_miss_local memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000001 10 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000002 00 ocr.demand_rfo.l3_miss_local memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000002 00 ocr.full_streaming_wr.l3_miss memory Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x802184000000 00 ocr.full_streaming_wr.l3_miss_local memory Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x802184000000 00 ocr.hwpf_l2_code_rd.l3_miss memory Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000040 00 ocr.hwpf_l2_code_rd.l3_miss_local memory Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000040 00 ocr.hwpf_l2_data_rd.l3_miss memory Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000010 00 ocr.hwpf_l2_data_rd.l3_miss_local memory Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000010 00 ocr.hwpf_l2_rfo.l3_miss memory Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000020 00 ocr.hwpf_l2_rfo.l3_miss_local memory Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000020 00 ocr.l1wb_m.l3_miss memory Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1002184000000 00 ocr.l1wb_m.l3_miss_local memory Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1002184000000 00 ocr.l2wb_m.l3_miss memory Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2002184000000 00 ocr.l2wb_m.l3_miss_local memory Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2002184000000 00 ocr.other.l3_miss memory Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184008000 00 ocr.other.l3_miss_local memory Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184008000 00 ocr.partial_streaming_wr.l3_miss memory Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x402184000000 00 ocr.partial_streaming_wr.l3_miss_local memory Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x402184000000 00 ocr.prefetches.l3_miss memory Counts all hardware and software prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000470 00 ocr.reads_to_core.l3_miss memory Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000477 00 ocr.reads_to_core.l3_miss_local memory Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000477 00 ocr.streaming_wr.l3_miss memory Counts streaming stores that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000800 00 ocr.streaming_wr.l3_miss_local memory Counts streaming stores that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000800 00 ocr.uc_rd.l3_miss memory Counts uncached memory reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x102184000000 00 ocr.uc_rd.l3_miss_local memory Counts uncached memory reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x102184000000 00 ocr.uc_wr.l3_miss memory Counts uncached memory writes that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x202184000000 00 ocr.uc_wr.l3_miss_local memory Counts uncached memory writes that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x202184000000 00 bus_lock.all other This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS event=0x63,edge=1,period=200003 10 bus_lock.block_cycles other Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores event=0x63,period=200003,umask=2 00 Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis bus_lock.cycles_other_block other This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES event=0x63,period=200003,umask=2 10 bus_lock.cycles_self_block other This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES event=0x63,period=200003,umask=1 10 bus_lock.lock_cycles other Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued event=0x63,period=200003,umask=1 00 Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis bus_lock.self_locks other Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks event=0x63,edge=1,period=200003 00 Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis c0_stalls.load_dram_hit other This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT event=0x34,period=200003,umask=4 10 c0_stalls.load_l2_hit other This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT event=0x34,period=200003,umask=1 10 c0_stalls.load_llc_hit other This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT event=0x34,period=200003,umask=2 10 hw_interrupts.masked other Counts the number of core cycles during which interrupts are masked (disabled) event=0xcb,period=200003,umask=2 00 Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not hw_interrupts.pending_and_masked other Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled) event=0xcb,period=200003,umask=4 00 Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR) because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important hw_interrupts.received other Counts the number of hardware interrupts received by the processor event=0xcb,period=203,umask=1 00 ocr.all_code_rd.any_response other Counts all code reads that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10044 00 ocr.all_code_rd.dram other Counts all code reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000044 00 ocr.all_code_rd.local_dram other Counts all code reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000044 00 ocr.all_code_rd.outstanding other Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000044 00 ocr.corewb_m.any_response other Counts modified writebacks from L1 cache and L2 cache that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x3000000010000 00 ocr.corewb_m.outstanding other Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8003000000000000 00 ocr.demand_code_rd.any_response other Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10004 00 ocr.demand_code_rd.dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000004 00 ocr.demand_code_rd.local_dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000004 00 ocr.demand_data_and_l1pf_rd.any_response other Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10001 00 ocr.demand_data_and_l1pf_rd.dram other Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001 00 ocr.demand_data_and_l1pf_rd.local_dram other Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001 00 ocr.demand_data_and_l1pf_rd.outstanding other Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000001 00 ocr.demand_data_rd.any_response other This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10001 10 ocr.demand_data_rd.dram other This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001 10 ocr.demand_data_rd.local_dram other This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001 10 ocr.demand_data_rd.outstanding other This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000001 10 ocr.demand_rfo.dram other Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000002 00 ocr.demand_rfo.local_dram other Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000002 00 ocr.demand_rfo.outstanding other Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000002 00 ocr.full_streaming_wr.any_response other Counts streaming stores which modify a full 64 byte cacheline that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x800000010000 00 ocr.hwpf_l1d_and_swpf.any_response other Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10400 00 ocr.hwpf_l2_code_rd.any_response other Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10040 00 ocr.hwpf_l2_code_rd.dram other Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000040 00 ocr.hwpf_l2_code_rd.local_dram other Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000040 00 ocr.hwpf_l2_code_rd.outstanding other Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000040 00 ocr.hwpf_l2_data_rd.any_response other Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10010 00 ocr.hwpf_l2_data_rd.dram other Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000010 00 ocr.hwpf_l2_data_rd.local_dram other Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000010 00 ocr.hwpf_l2_rfo.any_response other Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10020 00 ocr.hwpf_l2_rfo.dram other Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000020 00 ocr.hwpf_l2_rfo.local_dram other Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000020 00 ocr.hwpf_l2_rfo.outstanding other Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000020 00 ocr.l1wb_m.any_response other Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x1000000010000 00 ocr.l2wb_m.any_response other Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x2000000010000 00 ocr.other.any_response other Counts miscellaneous requests, such as I/O accesses, that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x18000 00 ocr.partial_streaming_wr.any_response other Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x400000010000 00 ocr.prefetches.any_response other Counts all hardware and software prefetches that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10470 00 ocr.reads_to_core.any_response other Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10477 00 ocr.reads_to_core.dram other Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000477 00 ocr.reads_to_core.local_dram other Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000477 00 ocr.reads_to_core.outstanding other Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000477 00 ocr.uc_rd.any_response other Counts uncached memory reads that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x100000010000 00 ocr.uc_rd.dram other Counts uncached memory reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x100184000000 00 ocr.uc_rd.local_dram other Counts uncached memory reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x100184000000 00 ocr.uc_rd.outstanding other Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000100000000000 00 ocr.uc_wr.any_response other Counts uncached memory writes that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x200000010000 00 br_inst_retired.call pipeline Counts the number of near CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf9 00 br_inst_retired.ind_call pipeline Counts the number of near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfb 00 br_inst_retired.jcc pipeline Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches (Precise event) event=0xc4,period=200003,umask=0x7e 00 br_inst_retired.non_return_ind pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xeb 00 br_inst_retired.return pipeline Counts the number of near RET branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf7 00 br_inst_retired.taken_jcc pipeline Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfe 00 br_misp_retired.ind_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfb 00 br_misp_retired.jcc pipeline Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc5,period=200003,umask=0x7e 00 br_misp_retired.non_return_ind pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xeb 00 br_misp_retired.taken_jcc pipeline Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfe 00 btclear.any pipeline Counts the total number of BTCLEARS event=0xe8,period=200003 00 Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch cpu_clk_unhalted.ref pipeline Counts the number of unhalted reference clock cycles at TSC frequency event=0x0,umask=0x03,period=2000003 00 Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2 cycles_div_busy.any pipeline This event is deprecated event=0xcd,period=2000003 10 cycles_div_busy.idiv pipeline Counts the number of cycles the integer divider is busy event=0xcd,period=200003,umask=1 00 Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider ld_blocks.4k_alias pipeline Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check (Precise event) event=3,period=1000003,umask=4 00 ld_blocks.all pipeline Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks) (Precise event) event=3,period=1000003,umask=0x10 00 ld_blocks.store_forward pipeline Counts the number of retired loads that are blocked because its address partially overlapped with an older store (Precise event) event=3,period=1000003,umask=2 00 machine_clears.any pipeline Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist event=0xc3,period=20003 00 topdown_bad_speculation.all pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0x73,period=1000003,umask=6 00 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear topdown_bad_speculation.machine_clears pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation event=0x73,period=1000003,umask=2 00 topdown_bad_speculation.monuke pipeline This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE event=0x73,period=1000003,umask=2 10 topdown_be_bound.store_buffer pipeline This event is deprecated event=0x74,period=1000003,umask=4 10 dtlb_load_misses.pde_cache_miss virtual memory Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache event=8,period=200003,umask=0x80 00 dtlb_load_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB event=8,period=200003,umask=0x20 00 dtlb_load_misses.walk_completed_1g virtual memory Counts the number of page walks completed due to load DTLB misses to a 1G page event=8,period=200003,umask=8 00 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault dtlb_load_misses.walk_completed_2m_4m virtual memory Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page event=8,period=200003,umask=4 00 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault dtlb_load_misses.walk_completed_4k virtual memory Counts the number of page walks completed due to load DTLB misses to a 4K page event=8,period=200003,umask=2 00 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault dtlb_load_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle event=8,period=200003,umask=0x10 00 Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals dtlb_store_misses.pde_cache_miss virtual memory Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache event=0x49,period=2000003,umask=0x80 00 dtlb_store_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB event=0x49,period=2000003,umask=0x20 00 dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to any page size event=0x49,period=200003,umask=0xe 00 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault dtlb_store_misses.walk_completed_1g virtual memory Counts the number of page walks completed due to store DTLB misses to a 1G page event=0x49,period=200003,umask=8 00 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault dtlb_store_misses.walk_completed_2m_4m virtual memory Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page event=0x49,period=2000003,umask=4 00 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault dtlb_store_misses.walk_completed_4k virtual memory Counts the number of page walks completed due to store DTLB misses to a 4K page event=0x49,period=2000003,umask=2 00 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault dtlb_store_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle event=0x49,period=200003,umask=0x10 00 Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals ept.epde_hit virtual memory Counts the number of Extended Page Directory Entry hits event=0x4f,period=2000003,umask=1 00 Counts the number of Extended Page Directory Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.epde_miss virtual memory Counts the number of Extended Page Directory Entry misses event=0x4f,period=2000003,umask=2 00 Counts the number Extended Page Directory Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.epdpe_hit virtual memory Counts the number of Extended Page Directory Pointer Entry hits event=0x4f,period=2000003,umask=4 00 Counts the number Extended Page Directory Pointer Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.epdpe_miss virtual memory Counts the number of Extended Page Directory Pointer Entry misses event=0x4f,period=2000003,umask=8 00 Counts the number Extended Page Directory Pointer Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.walk_pending virtual memory Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle event=0x4f,period=200003,umask=0x10 00 Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches itlb.fills virtual memory Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB event=0x81,period=200003,umask=4 00 Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB itlb_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB event=0x85,period=2000003,umask=0x20 00 itlb_misses.walk_completed_1g virtual memory Counts the number of page walks completed due to instruction fetch misses to a 1G page event=0x85,period=200003,umask=8 00 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault itlb_misses.walk_completed_2m_4m virtual memory Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page event=0x85,period=2000003,umask=4 00 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault itlb_misses.walk_completed_4k virtual memory Counts the number of page walks completed due to instruction fetch misses to a 4K page event=0x85,period=2000003,umask=2 00 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault itlb_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle event=0x85,period=200003,umask=0x10 00 Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk) ld_blocks.dtlb_miss virtual memory Counts the number of retired loads that are blocked due to a first level TLB miss (Precise event) event=3,period=1000003,umask=8 00 mem_uops_retired.dtlb_miss virtual memory Counts the number of memory uops retired that missed in the second level TLB Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x13 00 mem_uops_retired.dtlb_miss_loads virtual memory Counts the number of load uops retired that miss in the second Level TLB Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x11 00 mem_uops_retired.dtlb_miss_stores virtual memory Counts the number of store uops retired that miss in the second level TLB Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x12 00 l2_lines_out.non_silent cache Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill event=0x26,period=200003,umask=2 00 Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 l2_lines_out.silent cache Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill event=0x26,period=200003,umask=1 00 Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event l2_rqsts.all_demand_references cache Demand requests to L2 cache event=0x24,period=200003,umask=0xe7 00 Counts demand requests to L2 cache mem_load_l3_miss_retired.remote_dram cache MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM Supports address when precise (Precise event) event=0xd3,period=1000003,umask=2 00 mem_load_l3_miss_retired.remote_fwd cache Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise (Precise event) event=0xd3,period=100007,umask=8 00 Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_hitm cache MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM Supports address when precise (Precise event) event=0xd3,period=1000003,umask=4 00 ocr.demand_code_rd.l3_hit cache Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x3F803C0004 00 ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C0004 00 ocr.demand_code_rd.snc_cache.hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x1008000004 00 ocr.demand_code_rd.snc_cache.hit_with_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x808000004 00 ocr.demand_data_rd.l3_hit cache Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x3F803C0001 00 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data event=0x2a,period=100003,umask=1,offcore_rsp=0x4003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x8003C0001 00 ocr.demand_data_rd.remote_cache.snoop_hitm cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x1030000001 00 ocr.demand_data_rd.remote_cache.snoop_hit_with_fwd cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x830000001 00 ocr.demand_data_rd.snc_cache.hitm cache Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x1008000001 00 ocr.demand_data_rd.snc_cache.hit_with_fwd cache Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x808000001 00 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x3F803C0002 00 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C0002 00 ocr.demand_rfo.snc_cache.hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x1008000002 00 ocr.demand_rfo.snc_cache.hit_with_fwd cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x808000002 00 ocr.hwpf_l3.l3_hit cache Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x80082380 00 ocr.reads_to_core.l3_hit cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x3F003C4477 00 ocr.reads_to_core.l3_hit.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C4477 00 ocr.reads_to_core.l3_hit.snoop_hit_no_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data event=0x2a,period=100003,umask=1,offcore_rsp=0x4003C4477 00 ocr.reads_to_core.l3_hit.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x8003C4477 00 ocr.reads_to_core.remote_cache.snoop_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified) event=0x2a,period=100003,umask=1,offcore_rsp=0x1830004477 00 ocr.reads_to_core.remote_cache.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x1030004477 00 ocr.reads_to_core.remote_cache.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x830004477 00 ocr.reads_to_core.snc_cache.hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x1008004477 00 ocr.reads_to_core.snc_cache.hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x808004477 00 ocr.rfo_to_core.l3_hit_m cache Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter event=0x2a,period=100003,umask=1,offcore_rsp=0x1F80040022 00 ocr.streaming_wr.l3_hit cache Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x80080800 00 offcore_requests_outstanding.all_data_rd cache This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD event=0x20,period=1000003,umask=8 10 offcore_requests_outstanding.cycles_with_data_rd cache OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD event=0x20,cmask=1,period=1000003,umask=8 00 offcore_requests_outstanding.cycles_with_demand_rfo cache OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO event=0x20,cmask=1,period=1000003,umask=4 00 offcore_requests_outstanding.data_rd cache OFFCORE_REQUESTS_OUTSTANDING.DATA_RD event=0x20,period=1000003,umask=8 00 fp_arith_inst_retired.512b_packed_double floating point Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x40 00 Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_single floating point Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x80 00 Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.8_flops floating point Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x60 00 Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired2.128b_packed_half floating point FP_ARITH_INST_RETIRED2.128B_PACKED_HALF event=0xcf,period=100003,umask=4 00 fp_arith_inst_retired2.256b_packed_half floating point FP_ARITH_INST_RETIRED2.256B_PACKED_HALF event=0xcf,period=100003,umask=8 00 fp_arith_inst_retired2.512b_packed_half floating point FP_ARITH_INST_RETIRED2.512B_PACKED_HALF event=0xcf,period=100003,umask=0x10 00 fp_arith_inst_retired2.complex_scalar_half floating point FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF event=0xcf,period=100003,umask=2 00 fp_arith_inst_retired2.scalar floating point Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex event=0xcf,period=100003,umask=3 00 FP_ARITH_INST_RETIRED2.SCALAR fp_arith_inst_retired2.scalar_half floating point FP_ARITH_INST_RETIRED2.SCALAR_HALF event=0xcf,period=100003,umask=1 00 fp_arith_inst_retired2.vector floating point Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired event=0xcf,period=100003,umask=0x1c 00 FP_ARITH_INST_RETIRED2.VECTOR ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3FBFC00004 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3FBFC00001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3F3FC00002 00 ocr.hwpf_l3.l3_miss memory Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x94002380 00 ocr.hwpf_l3.l3_miss_local memory Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0x2a,period=100003,umask=1,offcore_rsp=0x84002380 00 ocr.reads_to_core.l3_miss memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3F3FC04477 00 ocr.reads_to_core.l3_miss_local memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0x2a,period=100003,umask=1,offcore_rsp=0x3F04C04477 00 ocr.reads_to_core.l3_miss_local_socket memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x70CC04477 00 ocr.streaming_wr.l3_miss memory Counts streaming stores that missed the local socket's L1, L2, and L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x94000800 00 ocr.streaming_wr.l3_miss_local memory Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0x2a,period=100003,umask=1,offcore_rsp=0x84000800 00 rtm_retired.aborted memory Number of times an RTM execution aborted (Precise event) event=0xc9,period=100003,umask=4 00 Counts the number of times RTM abort was triggered (Precise event) rtm_retired.aborted_events memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=100003,umask=0x80 00 Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) rtm_retired.aborted_mem memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=100003,umask=8 00 Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) rtm_retired.aborted_memtype memory Number of times an RTM execution aborted due to incompatible memory type event=0xc9,period=100003,umask=0x40 00 Counts the number of times an RTM execution aborted due to incompatible memory type rtm_retired.aborted_unfriendly memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=100003,umask=0x20 00 Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions rtm_retired.commit memory Number of times an RTM execution successfully committed event=0xc9,period=100003,umask=2 00 Counts the number of times RTM commit succeeded rtm_retired.start memory Number of times an RTM execution started event=0xc9,period=100003,umask=1 00 Counts the number of times we entered an RTM region. Does not count nested transactions tx_mem.abort_capacity_read memory Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads event=0x54,period=100003,umask=0x80 00 Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads tx_mem.abort_capacity_write memory Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes event=0x54,period=100003,umask=2 00 Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes tx_mem.abort_conflict memory Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address event=0x54,period=100003,umask=1 00 Counts the number of times a TSX line had a cache conflict exe.amx_busy other Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation event=0xb7,period=2000003,umask=2 00 ocr.demand_code_rd.any_response other Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10004 00 ocr.demand_code_rd.dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x73C000004 00 ocr.demand_code_rd.local_dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x104000004 00 ocr.demand_code_rd.snc_dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x708000004 00 ocr.demand_data_rd.dram other Counts demand data reads that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x73C000001 00 ocr.demand_data_rd.local_dram other Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x104000001 00 ocr.demand_data_rd.remote_dram other Counts demand data reads that were supplied by DRAM attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x730000001 00 ocr.demand_data_rd.snc_dram other Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x708000001 00 ocr.demand_rfo.any_response other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x3F3FFC0002 00 ocr.demand_rfo.dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x73C000002 00 ocr.demand_rfo.local_dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x104000002 00 ocr.demand_rfo.snc_dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x708000002 00 ocr.hwpf_l1d.any_response other Counts data load hardware prefetch requests to the L1 data cache that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10400 00 ocr.hwpf_l2.any_response other Counts hardware prefetches (which bring data to L2) that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10070 00 ocr.hwpf_l3.any_response other Counts hardware prefetches to the L3 only that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x12380 00 ocr.hwpf_l3.remote other Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket event=0x2a,period=100003,umask=1,offcore_rsp=0x90002380 00 ocr.modified_write.any_response other Counts writebacks of modified cachelines and streaming stores that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10808 00 ocr.reads_to_core.any_response other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x3F3FFC4477 00 ocr.reads_to_core.dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x73C004477 00 ocr.reads_to_core.local_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x104004477 00 ocr.reads_to_core.local_socket_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x70C004477 00 ocr.reads_to_core.remote other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket event=0x2a,period=100003,umask=1,offcore_rsp=0x3F33004477 00 ocr.reads_to_core.remote_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x730004477 00 ocr.reads_to_core.remote_memory other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x733004477 00 ocr.reads_to_core.snc_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x708004477 00 ocr.write_estimate.memory other Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) event=0x2a,period=100003,umask=1,offcore_rsp=0xFBFF80822 00 int_misc.mba_stalls pipeline INT_MISC.MBA_STALLS event=0xad,period=1000003,umask=0x20 00 uops_executed.core pipeline Number of uops executed on the core event=0xb1,period=2000003,umask=2 00 Counts the number of uops executed from any thread unc_cha_bypass_cha_imc.intermediate uncore cache CHA to iMC Bypass : Intermediate bypass Taken event=0x57,umask=2 01 CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass unc_cha_bypass_cha_imc.not_taken uncore cache CHA to iMC Bypass : Not Taken event=0x57,umask=4 01 CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted unc_cha_bypass_cha_imc.taken uncore cache CHA to iMC Bypass : Taken event=0x57,umask=1 01 CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass unc_cha_clockticks uncore cache CHA Clockticks event=1 01 Number of CHA clock cycles while the event is enabled unc_cha_core_snp.any_gtone uncore cache Core Cross Snoops Issued : Any Cycle with Multiple Snoops event=0x33,umask=0xf2 01 Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.any_one uncore cache Core Cross Snoops Issued : Any Single Snoop event=0x33,umask=0xf1 01 Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_gtone uncore cache Core Cross Snoops Issued : Multiple Core Requests event=0x33,umask=0x42 01 Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_one uncore cache Core Cross Snoops Issued : Single Core Requests event=0x33,umask=0x41 01 Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_gtone uncore cache Core Cross Snoops Issued : Multiple Eviction event=0x33,umask=0x82 01 Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_one uncore cache Core Cross Snoops Issued : Single Eviction event=0x33,umask=0x81 01 Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_gtone uncore cache Core Cross Snoops Issued : Multiple External Snoops event=0x33,umask=0x22 01 Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_one uncore cache Core Cross Snoops Issued : Single External Snoops event=0x33,umask=0x21 01 Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.remote_gtone uncore cache Core Cross Snoops Issued : Multiple Snoop Targets from Remote event=0x33,umask=0x12 01 Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.remote_one uncore cache Core Cross Snoops Issued : Single Snoop Target from Remote event=0x33,umask=0x11 01 Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_direct_go.ha_suppress_drd uncore cache Direct GO event=0x6e,umask=4 01 unc_cha_direct_go.ha_suppress_no_d2c uncore cache Direct GO event=0x6e,umask=2 01 unc_cha_direct_go.ha_tor_dealloc uncore cache Direct GO event=0x6e,umask=1 01 unc_cha_direct_go_opc.extcmp uncore cache Direct GO event=0x6d,umask=1 01 unc_cha_direct_go_opc.fast_go uncore cache Direct GO event=0x6d,umask=0x10 01 unc_cha_direct_go_opc.fast_go_pull uncore cache Direct GO event=0x6d,umask=0x20 01 unc_cha_direct_go_opc.go uncore cache Direct GO event=0x6d,umask=4 01 unc_cha_direct_go_opc.go_pull uncore cache Direct GO event=0x6d,umask=8 01 unc_cha_direct_go_opc.idle_due_suppress uncore cache Direct GO event=0x6d,umask=0x80 01 unc_cha_direct_go_opc.nop uncore cache Direct GO event=0x6d,umask=0x40 01 unc_cha_direct_go_opc.pull uncore cache Direct GO event=0x6d,umask=2 01 unc_cha_egress_ordering.iv_snoopgo_dn uncore cache Egress Blocking due to Ordering requirements : Down event=0xba,umask=4 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_egress_ordering.iv_snoopgo_up uncore cache Egress Blocking due to Ordering requirements : Up event=0xba,umask=1 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_hitme_hit.shared_ownreq uncore cache Counts Number of Hits in HitMe Cache : Shared hit and op is RdInvOwn, RdInv, Inv* event=0x5f,umask=4 01 unc_cha_hitme_hit.wbmtoe uncore cache Counts Number of Hits in HitMe Cache : op is WbMtoE event=0x5f,umask=8 01 unc_cha_hitme_hit.wbmtoi_or_s uncore cache Counts Number of Hits in HitMe Cache : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5f,umask=0x10 01 unc_cha_hitme_lookup.read uncore cache Counts Number of times HitMe Cache is accessed : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv* event=0x5e,umask=1 01 unc_cha_hitme_lookup.write uncore cache Counts Number of times HitMe Cache is accessed : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5e,umask=2 01 unc_cha_hitme_miss.notshared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : No SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x40 01 unc_cha_hitme_miss.read_or_inv uncore cache Counts Number of Misses in HitMe Cache : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv* event=0x60,umask=0x80 01 unc_cha_hitme_miss.shared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x20 01 unc_cha_hitme_update.deallocate uncore cache Counts the number of Allocate/Update to HitMe Cache : Deallocate HitME$ on Reads without RspFwdI* event=0x61,umask=0x10 01 unc_cha_hitme_update.deallocate_rspfwdi_loc uncore cache Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request event=0x61,umask=1 01 Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry unc_cha_hitme_update.rdinvown uncore cache Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI* event=0x61,umask=8 01 unc_cha_hitme_update.rspfwdi_rem uncore cache Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request event=0x61,umask=2 01 Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request unc_cha_hitme_update.shared uncore cache Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed event=0x61,umask=4 01 unc_cha_imc_reads_count.priority uncore cache HA to iMC Reads Issued : ISOCH event=0x59,umask=2 01 HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads unc_cha_imc_writes_count.full_priority uncore cache CHA to iMC Full Line Writes Issued : ISOCH Full Line event=0x5b,umask=4 01 CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller unc_cha_imc_writes_count.partial uncore cache CHA to iMC Full Line Writes Issued : Partial Non-ISOCH event=0x5b,umask=2 01 CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller unc_cha_imc_writes_count.partial_priority uncore cache CHA to iMC Full Line Writes Issued : ISOCH Partial event=0x5b,umask=8 01 CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller unc_cha_llc_lookup.all uncore cache Cache and Snoop Filter Lookups; Any Request event=0x34,umask=0x1fffff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_cha_llc_lookup.all_remote uncore cache Cache Lookups : All transactions from Remote Agents event=0x34,umask=0x17e0ff 01 Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.any_f uncore cache Cache Lookups : All Requests event=0x34 01 Cache Lookups : All Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch unc_cha_llc_lookup.code uncore cache Cache Lookups : CRd Requests event=0x34,umask=0x1bd0ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.code_read_f uncore cache Cache Lookups : CRd Requests event=0x34 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.corepref_or_dmnd_local_f uncore cache Cache Lookups : Local non-prefetch requests event=0x34 01 Cache Lookups : Local non-prefetch requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, not including prefetch unc_cha_llc_lookup.data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Request event=0x34,umask=0x1bc1ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_all uncore cache Cache Lookups : Data Reads event=0x34,umask=0x1fc1ff 01 Cache Lookups : Data Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.data_read_f uncore cache Cache Lookups : Data Read Request event=0x34 01 Cache Lookups : Data Read Request : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Read transactions unc_cha_llc_lookup.data_read_local uncore cache Cache Lookups : Demand Data Reads, Core and LLC prefetches event=0x34,umask=0x841ff 01 Cache Lookups : Demand Data Reads, Core and LLC prefetches : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.data_read_miss uncore cache Cache Lookups : Data Read Misses event=0x34,umask=0x1fc101 01 Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.e uncore cache Cache Lookups : E State event=0x34,umask=0x20 01 Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Exclusive State unc_cha_llc_lookup.f uncore cache Cache Lookups : F State event=0x34,umask=0x80 01 Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Forward State unc_cha_llc_lookup.flush_inv uncore cache Cache Lookups : Flush or Invalidate Requests event=0x34,umask=0x1a44ff 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.flush_or_inv_f uncore cache Cache Lookups : Flush event=0x34 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.i uncore cache Cache Lookups : I State event=0x34,umask=1 01 Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Miss unc_cha_llc_lookup.llcpref_local_f uncore cache Cache Lookups : Local LLC prefetch requests (from LLC) event=0x34 01 Cache Lookups : Local LLC prefetch requests (from LLC) : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC unc_cha_llc_lookup.locally_homed_address uncore cache Cache Lookups : Transactions homed locally event=0x34,umask=0xbdfff 01 Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.local_code uncore cache Cache Lookups : CRd Requests that come from the local socket (usually the core) event=0x34,umask=0x19d0ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.local_data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core) event=0x34,umask=0x19c1ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_dmnd_code uncore cache Cache Lookups : Demand CRd Requests that come from the local socket (usually the core) event=0x34,umask=0x1850ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.local_dmnd_data_rd uncore cache Cache and Snoop Filter Lookups; Demand Data Reads that come from the local socket (usually the core) event=0x34,umask=0x1841ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_dmnd_rfo uncore cache Cache Lookups : Demand RFO Requests that come from the local socket (usually the core) event=0x34,umask=0x1848ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.local_f uncore cache Cache Lookups : Transactions homed locally event=0x34 01 Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.local_flush_inv uncore cache Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core) event=0x34,umask=0x1844ff 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.local_llc_pf uncore cache Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core) event=0x34,umask=0x189dff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf uncore cache Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core) event=0x34,umask=0x199dff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf_code uncore cache Cache Lookups : CRd Prefetches that come from the local socket (usually the core) event=0x34,umask=0x1910ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.local_pf_data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core) event=0x34,umask=0x1981ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf_rfo uncore cache Cache Lookups : RFO Prefetches that come from the local socket (usually the core) event=0x34,umask=0x1908ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.local_rfo uncore cache Cache Lookups : RFO Requests that come from the local socket (usually the core) event=0x34,umask=0x19c8ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.m uncore cache Cache Lookups : M State event=0x34,umask=0x40 01 Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Modified State unc_cha_llc_lookup.miss_all uncore cache Cache Lookups : All Misses event=0x34,umask=0x1fe001 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.other_req_f uncore cache Cache Lookups : Write Requests event=0x34 01 Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.pref_or_dmnd_remote_f uncore cache Cache Lookups : Remote non-snoop requests event=0x34 01 Cache Lookups : Remote non-snoop requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Remote non-snoop transactions to the LLC unc_cha_llc_lookup.remotely_homed_address uncore cache Cache Lookups : Transactions homed remotely event=0x34,umask=0x15dfff 01 Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_code uncore cache Cache Lookups : CRd Requests that come from a Remote socket event=0x34,umask=0x1a10ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.remote_data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket event=0x34,umask=0x1a01ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.remote_f uncore cache Cache Lookups : Transactions homed remotely event=0x34 01 Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_flush_inv uncore cache Cache Lookups : Flush or Invalidate requests that come from a Remote socket event=0x34,umask=0x1a04ff 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.remote_other uncore cache Cache Lookups : Filters Requests for those that write info into the cache that come from a remote socket event=0x34,umask=0x1a02ff 01 Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.remote_rfo uncore cache Cache Lookups : RFO Requests that come from a Remote socket event=0x34,umask=0x1a08ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.remote_snoop_f uncore cache Cache Lookups : Remote snoop requests event=0x34 01 Cache Lookups : Remote snoop requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Remote snoop transactions to the LLC unc_cha_llc_lookup.remote_snp uncore cache Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket event=0x34,umask=0x1c19ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_cha_llc_lookup.rfo uncore cache Cache Lookups : RFO Requests event=0x34,umask=0x1bc8ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.rfo_f uncore cache Cache Lookups : RFO Request Filter event=0x34 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.rfo_local uncore cache Cache Lookups : Locally HOMed RFOs - Demand and Prefetches event=0x34,umask=0x9c8ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.s uncore cache Cache Lookups : S State event=0x34,umask=0x10 01 Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Shared State unc_cha_llc_lookup.sf_e uncore cache Cache Lookups : SnoopFilter - E State event=0x34,umask=4 01 Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit Exclusive State unc_cha_llc_lookup.sf_h uncore cache Cache Lookups : SnoopFilter - H State event=0x34,umask=8 01 Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit HitMe State unc_cha_llc_lookup.sf_s uncore cache Cache Lookups : SnoopFilter - S State event=0x34,umask=2 01 Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit Shared State unc_cha_llc_lookup.write_local uncore cache Cache Lookups : Writes event=0x34,umask=0x842ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Requests that install or change a line in the LLC. Examples: Writebacks from Core L2's and UPI. Prefetches into the LLC unc_cha_llc_lookup.write_remote uncore cache Cache Lookups : Remote Writes event=0x34,umask=0x17c2ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_victims.e_state uncore cache Lines Victimized : Lines in E state event=0x37,umask=2 01 Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.ia uncore cache Lines Victimized : IA traffic event=0x37,umask=0x20 01 Lines Victimized : IA traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.io uncore cache Lines Victimized : IO traffic event=0x37,umask=0x10 01 Lines Victimized : IO traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.io_e uncore cache All LLC lines in E state that are victimized on a fill from an IO device event=0x37,umask=0x12 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.io_fs uncore cache All LLC lines in F or S state that are victimized on a fill from an IO device event=0x37,umask=0x1c 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.io_m uncore cache All LLC lines in M state that are victimized on a fill from an IO device event=0x37,umask=0x11 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.io_mesf uncore cache All LLC lines in any state that are victimized on a fill from an IO device event=0x37,umask=0x1f 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_all uncore cache Lines Victimized; Local - All Lines event=0x37,umask=0x200f 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_e uncore cache Lines Victimized event=0x37,umask=0x2002 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_m uncore cache Lines Victimized event=0x37,umask=0x2001 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_only uncore cache Lines Victimized : Local Only event=0x37 01 Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_s uncore cache Lines Victimized event=0x37,umask=0x2004 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.m_state uncore cache Lines Victimized : Lines in M state event=0x37,umask=1 01 Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_all uncore cache Lines Victimized; Remote - All Lines event=0x37,umask=0x800f 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_e uncore cache Lines Victimized event=0x37,umask=0x8002 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_m uncore cache Lines Victimized event=0x37,umask=0x8001 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_only uncore cache Lines Victimized : Remote Only event=0x37 01 Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_s uncore cache Lines Victimized event=0x37,umask=0x8004 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.s_state uncore cache Lines Victimized : Lines in S State event=0x37,umask=4 01 Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_e uncore cache All LLC lines in E state that are victimized on a fill event=0x37,umask=2 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_m uncore cache All LLC lines in M state that are victimized on a fill event=0x37,umask=1 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_s uncore cache All LLC lines in S state that are victimized on a fill event=0x37,umask=4 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_misc.cv0_pref_miss uncore cache Cbo Misc : CV0 Prefetch Miss event=0x39,umask=0x20 01 Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo unc_cha_misc.cv0_pref_vic uncore cache Cbo Misc : CV0 Prefetch Victim event=0x39,umask=0x10 01 Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo unc_cha_misc.rspi_was_fse uncore cache Cbo Misc : Silent Snoop Eviction event=0x39,umask=1 01 Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings unc_cha_misc.wc_aliasing uncore cache Cbo Misc : Write Combining Aliasing event=0x39,umask=2 01 Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing unc_cha_osb.local_invitoe uncore cache OSB Snoop Broadcast : Local InvItoE event=0x55,umask=1 01 OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.local_read uncore cache OSB Snoop Broadcast : Local Rd event=0x55,umask=2 01 OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.off_pwrheuristic uncore cache OSB Snoop Broadcast : Off event=0x55,umask=0x20 01 OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.remote_read uncore cache OSB Snoop Broadcast : Remote Rd event=0x55,umask=4 01 OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.remote_readinvitoe uncore cache OSB Snoop Broadcast : Remote Rd InvItoE event=0x55,umask=8 01 OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.rfo_hits_snp_bcast uncore cache OSB Snoop Broadcast : RFO HitS Snoop Broadcast event=0x55,umask=0x10 01 OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_pmm_memmode_nm_invitox.local uncore cache UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL event=0x65,umask=1 01 unc_cha_pmm_memmode_nm_invitox.remote uncore cache UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE event=0x65,umask=2 01 unc_cha_pmm_memmode_nm_invitox.setconflict uncore cache UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT event=0x65,umask=4 01 unc_cha_pmm_memmode_nm_setconflicts.llc uncore cache Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in SF/LLC event=0x64,umask=2 01 Near Memory evictions due to another read to the same Near Memory set in the LLC unc_cha_pmm_memmode_nm_setconflicts.sf uncore cache Memory Mode related events; Counts the number of times CHA saw a Near memory set conflict in SF/LLC event=0x64,umask=1 01 Near Memory evictions due to another read to the same Near Memory set in the SF unc_cha_pmm_memmode_nm_setconflicts.tor uncore cache Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in TOR event=0x64,umask=4 01 No Reject in the CHA due to a pending read to the same Near Memory set in the TOR unc_cha_pmm_memmode_nm_setconflicts2.iodc uncore cache UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC event=0x70,umask=1 01 unc_cha_pmm_memmode_nm_setconflicts2.memwr uncore cache UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR event=0x70,umask=2 01 unc_cha_pmm_memmode_nm_setconflicts2.memwrni uncore cache UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI event=0x70,umask=4 01 unc_cha_pmm_qos.ddr4_fast_insert uncore cache UNC_CHA_PMM_QOS.DDR4_FAST_INSERT event=0x66,umask=2 01 unc_cha_pmm_qos.rej_irq uncore cache UNC_CHA_PMM_QOS.REJ_IRQ event=0x66,umask=8 01 unc_cha_pmm_qos.slowtorq_skip uncore cache UNC_CHA_PMM_QOS.SLOWTORQ_SKIP event=0x66,umask=0x40 01 unc_cha_pmm_qos.slow_insert uncore cache UNC_CHA_PMM_QOS.SLOW_INSERT event=0x66,umask=1 01 unc_cha_pmm_qos.throttle uncore cache UNC_CHA_PMM_QOS.THROTTLE event=0x66,umask=4 01 unc_cha_pmm_qos.throttle_irq uncore cache UNC_CHA_PMM_QOS.THROTTLE_IRQ event=0x66,umask=0x20 01 unc_cha_pmm_qos.throttle_prq uncore cache UNC_CHA_PMM_QOS.THROTTLE_PRQ event=0x66,umask=0x10 01 unc_cha_pmm_qos_occupancy.ddr_fast_fifo uncore cache UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO event=0x67,umask=2 01 : count # of FAST TOR Request inserted to ha_tor_req_fifo unc_cha_pmm_qos_occupancy.ddr_slow_fifo uncore cache Number of SLOW TOR Request inserted to ha_pmm_tor_req_fifo event=0x67,umask=1 01 unc_cha_read_no_credits.mc0 uncore cache CHA iMC CHNx READ Credits Empty : MC0 event=0x58,umask=1 01 CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only unc_cha_read_no_credits.mc1 uncore cache CHA iMC CHNx READ Credits Empty : MC1 event=0x58,umask=2 01 CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only unc_cha_read_no_credits.mc2 uncore cache CHA iMC CHNx READ Credits Empty : MC2 event=0x58,umask=4 01 CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only unc_cha_read_no_credits.mc3 uncore cache CHA iMC CHNx READ Credits Empty : MC3 event=0x58,umask=8 01 CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only unc_cha_read_no_credits.mc4 uncore cache CHA iMC CHNx READ Credits Empty : MC4 event=0x58,umask=0x10 01 CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only unc_cha_read_no_credits.mc5 uncore cache CHA iMC CHNx READ Credits Empty : MC5 event=0x58,umask=0x20 01 CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only unc_cha_requests.invitoe uncore cache Requests for exclusive ownership of a cache line without receiving data event=0x50,umask=0x30 01 Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_remote uncore cache Remote requests for exclusive ownership of a cache line without receiving data event=0x50,umask=0x20 01 Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.reads uncore cache Read requests made into the CHA event=0x50,umask=3 01 Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.writes uncore cache Write requests made into the CHA event=0x50,umask=0xc 01 Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_rxc_inserts.ipq uncore cache Ingress (from CMS) Allocations : IPQ event=0x13,umask=4 01 Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq uncore cache Ingress (from CMS) Allocations : IRQ event=0x13,umask=1 01 Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq_rej uncore cache Ingress (from CMS) Allocations : IRQ Rejected event=0x13,umask=2 01 Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq uncore cache Ingress (from CMS) Allocations : PRQ event=0x13,umask=0x10 01 Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq_rej uncore cache Ingress (from CMS) Allocations : PRQ event=0x13,umask=0x20 01 Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.rrq uncore cache Ingress (from CMS) Allocations : RRQ event=0x13,umask=0x40 01 Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.wbq uncore cache Ingress (from CMS) Allocations : WBQ event=0x13,umask=0x80 01 Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_ipq0_reject.ad_req_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 event=0x22,umask=1 01 IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request unc_cha_rxc_ipq0_reject.ad_rsp_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 event=0x22,umask=2 01 IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response unc_cha_rxc_ipq0_reject.ak_non_upi uncore cache IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request event=0x22,umask=0x40 01 IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message unc_cha_rxc_ipq0_reject.bl_ncb_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 event=0x22,umask=0x10 01 IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB unc_cha_rxc_ipq0_reject.bl_ncs_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 event=0x22,umask=0x20 01 IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS unc_cha_rxc_ipq0_reject.bl_rsp_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 event=0x22,umask=4 01 IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response unc_cha_rxc_ipq0_reject.bl_wb_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 event=0x22,umask=8 01 IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback unc_cha_rxc_ipq0_reject.iv_non_upi uncore cache IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request event=0x22,umask=0x80 01 IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message unc_cha_rxc_ipq1_reject.allow_snp uncore cache IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop event=0x23,umask=0x40 01 unc_cha_rxc_ipq1_reject.any0 uncore cache IPQ Requests (from CMS) Rejected - Set 1 : ANY0 event=0x23,umask=1 01 IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true unc_cha_rxc_ipq1_reject.ha uncore cache IPQ Requests (from CMS) Rejected - Set 1 : HA event=0x23,umask=2 01 unc_cha_rxc_ipq1_reject.llc_or_sf_way uncore cache IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way event=0x23,umask=0x20 01 IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject unc_cha_rxc_ipq1_reject.llc_victim uncore cache IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim event=0x23,umask=4 01 unc_cha_rxc_ipq1_reject.pa_match uncore cache IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match event=0x23,umask=0x80 01 IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected unc_cha_rxc_ipq1_reject.sf_victim uncore cache IPQ Requests (from CMS) Rejected - Set 1 : SF Victim event=0x23,umask=8 01 IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim unc_cha_rxc_ipq1_reject.victim uncore cache IPQ Requests (from CMS) Rejected - Set 1 : Victim event=0x23,umask=0x10 01 unc_cha_rxc_irq0_reject.ad_req_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 event=0x18,umask=1 01 IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request unc_cha_rxc_irq0_reject.ad_rsp_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 event=0x18,umask=2 01 IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response unc_cha_rxc_irq0_reject.ak_non_upi uncore cache IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request event=0x18,umask=0x40 01 IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message unc_cha_rxc_irq0_reject.bl_ncb_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 event=0x18,umask=0x10 01 IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB unc_cha_rxc_irq0_reject.bl_ncs_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 event=0x18,umask=0x20 01 IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS unc_cha_rxc_irq0_reject.bl_rsp_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 event=0x18,umask=4 01 IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response unc_cha_rxc_irq0_reject.bl_wb_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 event=0x18,umask=8 01 IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback unc_cha_rxc_irq0_reject.iv_non_upi uncore cache IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request event=0x18,umask=0x80 01 IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message unc_cha_rxc_irq1_reject.allow_snp uncore cache IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop event=0x19,umask=0x40 01 unc_cha_rxc_irq1_reject.any0 uncore cache IRQ Requests (from CMS) Rejected - Set 1 : ANY0 event=0x19,umask=1 01 IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true unc_cha_rxc_irq1_reject.ha uncore cache IRQ Requests (from CMS) Rejected - Set 1 : HA event=0x19,umask=2 01 unc_cha_rxc_irq1_reject.llc_or_sf_way uncore cache IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way event=0x19,umask=0x20 01 IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject unc_cha_rxc_irq1_reject.llc_victim uncore cache IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim event=0x19,umask=4 01 unc_cha_rxc_irq1_reject.sf_victim uncore cache IRQ Requests (from CMS) Rejected - Set 1 : SF Victim event=0x19,umask=8 01 IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim unc_cha_rxc_irq1_reject.victim uncore cache IRQ Requests (from CMS) Rejected - Set 1 : Victim event=0x19,umask=0x10 01 unc_cha_rxc_ismq0_reject.ad_req_vn0 uncore cache ISMQ Rejects - Set 0 : AD REQ on VN0 event=0x24,umask=1 01 ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request unc_cha_rxc_ismq0_reject.ad_rsp_vn0 uncore cache ISMQ Rejects - Set 0 : AD RSP on VN0 event=0x24,umask=2 01 ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response unc_cha_rxc_ismq0_reject.ak_non_upi uncore cache ISMQ Rejects - Set 0 : Non UPI AK Request event=0x24,umask=0x40 01 ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message unc_cha_rxc_ismq0_reject.bl_ncb_vn0 uncore cache ISMQ Rejects - Set 0 : BL NCB on VN0 event=0x24,umask=0x10 01 ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB unc_cha_rxc_ismq0_reject.bl_ncs_vn0 uncore cache ISMQ Rejects - Set 0 : BL NCS on VN0 event=0x24,umask=0x20 01 ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS unc_cha_rxc_ismq0_reject.bl_rsp_vn0 uncore cache ISMQ Rejects - Set 0 : BL RSP on VN0 event=0x24,umask=4 01 ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response unc_cha_rxc_ismq0_reject.bl_wb_vn0 uncore cache ISMQ Rejects - Set 0 : BL WB on VN0 event=0x24,umask=8 01 ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback unc_cha_rxc_ismq0_reject.iv_non_upi uncore cache ISMQ Rejects - Set 0 : Non UPI IV Request event=0x24,umask=0x80 01 ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message unc_cha_rxc_ismq0_retry.ad_req_vn0 uncore cache ISMQ Retries - Set 0 : AD REQ on VN0 event=0x2c,umask=1 01 ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request unc_cha_rxc_ismq0_retry.ad_rsp_vn0 uncore cache ISMQ Retries - Set 0 : AD RSP on VN0 event=0x2c,umask=2 01 ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response unc_cha_rxc_ismq0_retry.ak_non_upi uncore cache ISMQ Retries - Set 0 : Non UPI AK Request event=0x2c,umask=0x40 01 ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message unc_cha_rxc_ismq0_retry.bl_ncb_vn0 uncore cache ISMQ Retries - Set 0 : BL NCB on VN0 event=0x2c,umask=0x10 01 ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB unc_cha_rxc_ismq0_retry.bl_ncs_vn0 uncore cache ISMQ Retries - Set 0 : BL NCS on VN0 event=0x2c,umask=0x20 01 ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS unc_cha_rxc_ismq0_retry.bl_rsp_vn0 uncore cache ISMQ Retries - Set 0 : BL RSP on VN0 event=0x2c,umask=4 01 ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response unc_cha_rxc_ismq0_retry.bl_wb_vn0 uncore cache ISMQ Retries - Set 0 : BL WB on VN0 event=0x2c,umask=8 01 ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback unc_cha_rxc_ismq0_retry.iv_non_upi uncore cache ISMQ Retries - Set 0 : Non UPI IV Request event=0x2c,umask=0x80 01 ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message unc_cha_rxc_ismq1_reject.any0 uncore cache ISMQ Rejects - Set 1 : ANY0 event=0x25,umask=1 01 ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true unc_cha_rxc_ismq1_reject.ha uncore cache ISMQ Rejects - Set 1 : HA event=0x25,umask=2 01 ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_retry.any0 uncore cache ISMQ Retries - Set 1 : ANY0 event=0x2d,umask=1 01 ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true unc_cha_rxc_ismq1_retry.ha uncore cache ISMQ Retries - Set 1 : HA event=0x2d,umask=2 01 ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_occupancy.ipq uncore cache Ingress (from CMS) Occupancy : IPQ event=0x11,umask=4 01 Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.rrq uncore cache Ingress (from CMS) Occupancy : RRQ event=0x11,umask=0x40 01 Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.wbq uncore cache Ingress (from CMS) Occupancy : WBQ event=0x11,umask=0x80 01 Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_other0_retry.ad_req_vn0 uncore cache Other Retries - Set 0 : AD REQ on VN0 event=0x2e,umask=1 01 Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request unc_cha_rxc_other0_retry.ad_rsp_vn0 uncore cache Other Retries - Set 0 : AD RSP on VN0 event=0x2e,umask=2 01 Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response unc_cha_rxc_other0_retry.ak_non_upi uncore cache Other Retries - Set 0 : Non UPI AK Request event=0x2e,umask=0x40 01 Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message unc_cha_rxc_other0_retry.bl_ncb_vn0 uncore cache Other Retries - Set 0 : BL NCB on VN0 event=0x2e,umask=0x10 01 Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB unc_cha_rxc_other0_retry.bl_ncs_vn0 uncore cache Other Retries - Set 0 : BL NCS on VN0 event=0x2e,umask=0x20 01 Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS unc_cha_rxc_other0_retry.bl_rsp_vn0 uncore cache Other Retries - Set 0 : BL RSP on VN0 event=0x2e,umask=4 01 Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response unc_cha_rxc_other0_retry.bl_wb_vn0 uncore cache Other Retries - Set 0 : BL WB on VN0 event=0x2e,umask=8 01 Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback unc_cha_rxc_other0_retry.iv_non_upi uncore cache Other Retries - Set 0 : Non UPI IV Request event=0x2e,umask=0x80 01 Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message unc_cha_rxc_other1_retry.allow_snp uncore cache Other Retries - Set 1 : Allow Snoop event=0x2f,umask=0x40 01 Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.any0 uncore cache Other Retries - Set 1 : ANY0 event=0x2f,umask=1 01 Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true unc_cha_rxc_other1_retry.ha uncore cache Other Retries - Set 1 : HA event=0x2f,umask=2 01 Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.llc_or_sf_way uncore cache Other Retries - Set 1 : LLC OR SF Way event=0x2f,umask=0x20 01 Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject unc_cha_rxc_other1_retry.llc_victim uncore cache Other Retries - Set 1 : LLC Victim event=0x2f,umask=4 01 Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.pa_match uncore cache Other Retries - Set 1 : PhyAddr Match event=0x2f,umask=0x80 01 Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected unc_cha_rxc_other1_retry.sf_victim uncore cache Other Retries - Set 1 : SF Victim event=0x2f,umask=8 01 Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim unc_cha_rxc_other1_retry.victim uncore cache Other Retries - Set 1 : Victim event=0x2f,umask=0x10 01 Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_prq0_reject.ad_req_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 event=0x20,umask=1 01 PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request unc_cha_rxc_prq0_reject.ad_rsp_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 event=0x20,umask=2 01 PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response unc_cha_rxc_prq0_reject.ak_non_upi uncore cache PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request event=0x20,umask=0x40 01 PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message unc_cha_rxc_prq0_reject.bl_ncb_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 event=0x20,umask=0x10 01 PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB unc_cha_rxc_prq0_reject.bl_ncs_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 event=0x20,umask=0x20 01 PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS unc_cha_rxc_prq0_reject.bl_rsp_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 event=0x20,umask=4 01 PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response unc_cha_rxc_prq0_reject.bl_wb_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 event=0x20,umask=8 01 PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback unc_cha_rxc_prq0_reject.iv_non_upi uncore cache PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request event=0x20,umask=0x80 01 PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message unc_cha_rxc_prq1_reject.allow_snp uncore cache PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop event=0x21,umask=0x40 01 unc_cha_rxc_prq1_reject.any0 uncore cache PRQ Requests (from CMS) Rejected - Set 1 : ANY0 event=0x21,umask=1 01 PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true unc_cha_rxc_prq1_reject.ha uncore cache PRQ Requests (from CMS) Rejected - Set 1 : HA event=0x21,umask=2 01 unc_cha_rxc_prq1_reject.llc_or_sf_way uncore cache PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way event=0x21,umask=0x20 01 PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject unc_cha_rxc_prq1_reject.llc_victim uncore cache PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim event=0x21,umask=4 01 unc_cha_rxc_prq1_reject.pa_match uncore cache PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match event=0x21,umask=0x80 01 PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected unc_cha_rxc_prq1_reject.sf_victim uncore cache PRQ Requests (from CMS) Rejected - Set 1 : SF Victim event=0x21,umask=8 01 PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim unc_cha_rxc_prq1_reject.victim uncore cache PRQ Requests (from CMS) Rejected - Set 1 : Victim event=0x21,umask=0x10 01 unc_cha_rxc_req_q0_retry.ad_req_vn0 uncore cache Request Queue Retries - Set 0 : AD REQ on VN0 event=0x2a,umask=1 01 Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request unc_cha_rxc_req_q0_retry.ad_rsp_vn0 uncore cache Request Queue Retries - Set 0 : AD RSP on VN0 event=0x2a,umask=2 01 Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response unc_cha_rxc_req_q0_retry.ak_non_upi uncore cache Request Queue Retries - Set 0 : Non UPI AK Request event=0x2a,umask=0x40 01 Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message unc_cha_rxc_req_q0_retry.bl_ncb_vn0 uncore cache Request Queue Retries - Set 0 : BL NCB on VN0 event=0x2a,umask=0x10 01 Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB unc_cha_rxc_req_q0_retry.bl_ncs_vn0 uncore cache Request Queue Retries - Set 0 : BL NCS on VN0 event=0x2a,umask=0x20 01 Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS unc_cha_rxc_req_q0_retry.bl_rsp_vn0 uncore cache Request Queue Retries - Set 0 : BL RSP on VN0 event=0x2a,umask=4 01 Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response unc_cha_rxc_req_q0_retry.bl_wb_vn0 uncore cache Request Queue Retries - Set 0 : BL WB on VN0 event=0x2a,umask=8 01 Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback unc_cha_rxc_req_q0_retry.iv_non_upi uncore cache Request Queue Retries - Set 0 : Non UPI IV Request event=0x2a,umask=0x80 01 Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message unc_cha_rxc_req_q1_retry.allow_snp uncore cache Request Queue Retries - Set 1 : Allow Snoop event=0x2b,umask=0x40 01 Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.any0 uncore cache Request Queue Retries - Set 1 : ANY0 event=0x2b,umask=1 01 Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true unc_cha_rxc_req_q1_retry.ha uncore cache Request Queue Retries - Set 1 : HA event=0x2b,umask=2 01 Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.llc_or_sf_way uncore cache Request Queue Retries - Set 1 : LLC OR SF Way event=0x2b,umask=0x20 01 Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject unc_cha_rxc_req_q1_retry.llc_victim uncore cache Request Queue Retries - Set 1 : LLC Victim event=0x2b,umask=4 01 Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.pa_match uncore cache Request Queue Retries - Set 1 : PhyAddr Match event=0x2b,umask=0x80 01 Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected unc_cha_rxc_req_q1_retry.sf_victim uncore cache Request Queue Retries - Set 1 : SF Victim event=0x2b,umask=8 01 Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim unc_cha_rxc_req_q1_retry.victim uncore cache Request Queue Retries - Set 1 : Victim event=0x2b,umask=0x10 01 Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_rrq0_reject.ad_req_vn0 uncore cache RRQ Rejects - Set 0 : AD REQ on VN0 event=0x26,umask=1 01 RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request unc_cha_rxc_rrq0_reject.ad_rsp_vn0 uncore cache RRQ Rejects - Set 0 : AD RSP on VN0 event=0x26,umask=2 01 RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response unc_cha_rxc_rrq0_reject.ak_non_upi uncore cache RRQ Rejects - Set 0 : Non UPI AK Request event=0x26,umask=0x40 01 RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message unc_cha_rxc_rrq0_reject.bl_ncb_vn0 uncore cache RRQ Rejects - Set 0 : BL NCB on VN0 event=0x26,umask=0x10 01 RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB unc_cha_rxc_rrq0_reject.bl_ncs_vn0 uncore cache RRQ Rejects - Set 0 : BL NCS on VN0 event=0x26,umask=0x20 01 RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS unc_cha_rxc_rrq0_reject.bl_rsp_vn0 uncore cache RRQ Rejects - Set 0 : BL RSP on VN0 event=0x26,umask=4 01 RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response unc_cha_rxc_rrq0_reject.bl_wb_vn0 uncore cache RRQ Rejects - Set 0 : BL WB on VN0 event=0x26,umask=8 01 RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback unc_cha_rxc_rrq0_reject.iv_non_upi uncore cache RRQ Rejects - Set 0 : Non UPI IV Request event=0x26,umask=0x80 01 RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message unc_cha_rxc_rrq1_reject.allow_snp uncore cache RRQ Rejects - Set 1 : Allow Snoop event=0x27,umask=0x40 01 RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.any0 uncore cache RRQ Rejects - Set 1 : ANY0 event=0x27,umask=1 01 RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true unc_cha_rxc_rrq1_reject.ha uncore cache RRQ Rejects - Set 1 : HA event=0x27,umask=2 01 RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.llc_or_sf_way uncore cache RRQ Rejects - Set 1 : LLC OR SF Way event=0x27,umask=0x20 01 RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject unc_cha_rxc_rrq1_reject.llc_victim uncore cache RRQ Rejects - Set 1 : LLC Victim event=0x27,umask=4 01 RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.pa_match uncore cache RRQ Rejects - Set 1 : PhyAddr Match event=0x27,umask=0x80 01 RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected unc_cha_rxc_rrq1_reject.sf_victim uncore cache RRQ Rejects - Set 1 : SF Victim event=0x27,umask=8 01 RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim unc_cha_rxc_rrq1_reject.victim uncore cache RRQ Rejects - Set 1 : Victim event=0x27,umask=0x10 01 RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_wbq0_reject.ad_req_vn0 uncore cache WBQ Rejects - Set 0 : AD REQ on VN0 event=0x28,umask=1 01 WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request unc_cha_rxc_wbq0_reject.ad_rsp_vn0 uncore cache WBQ Rejects - Set 0 : AD RSP on VN0 event=0x28,umask=2 01 WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response unc_cha_rxc_wbq0_reject.ak_non_upi uncore cache WBQ Rejects - Set 0 : Non UPI AK Request event=0x28,umask=0x40 01 WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message unc_cha_rxc_wbq0_reject.bl_ncb_vn0 uncore cache WBQ Rejects - Set 0 : BL NCB on VN0 event=0x28,umask=0x10 01 WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB unc_cha_rxc_wbq0_reject.bl_ncs_vn0 uncore cache WBQ Rejects - Set 0 : BL NCS on VN0 event=0x28,umask=0x20 01 WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS unc_cha_rxc_wbq0_reject.bl_rsp_vn0 uncore cache WBQ Rejects - Set 0 : BL RSP on VN0 event=0x28,umask=4 01 WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response unc_cha_rxc_wbq0_reject.bl_wb_vn0 uncore cache WBQ Rejects - Set 0 : BL WB on VN0 event=0x28,umask=8 01 WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback unc_cha_rxc_wbq0_reject.iv_non_upi uncore cache WBQ Rejects - Set 0 : Non UPI IV Request event=0x28,umask=0x80 01 WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message unc_cha_rxc_wbq1_reject.allow_snp uncore cache WBQ Rejects - Set 1 : Allow Snoop event=0x29,umask=0x40 01 WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.any0 uncore cache WBQ Rejects - Set 1 : ANY0 event=0x29,umask=1 01 WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true unc_cha_rxc_wbq1_reject.ha uncore cache WBQ Rejects - Set 1 : HA event=0x29,umask=2 01 WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.llc_or_sf_way uncore cache WBQ Rejects - Set 1 : LLC OR SF Way event=0x29,umask=0x20 01 WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject unc_cha_rxc_wbq1_reject.llc_victim uncore cache WBQ Rejects - Set 1 : LLC Victim event=0x29,umask=4 01 WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.pa_match uncore cache WBQ Rejects - Set 1 : PhyAddr Match event=0x29,umask=0x80 01 WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected unc_cha_rxc_wbq1_reject.sf_victim uncore cache WBQ Rejects - Set 1 : SF Victim event=0x29,umask=8 01 WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim unc_cha_rxc_wbq1_reject.victim uncore cache WBQ Rejects - Set 1 : Victim event=0x29,umask=0x10 01 WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_snoops_sent.all uncore cache Snoops Sent : All event=0x51,umask=1 01 Snoops Sent : All : Counts the number of snoops issued by the HA unc_cha_snoops_sent.bcst_local uncore cache Snoops Sent : Broadcast snoop for Local Requests event=0x51,umask=0x10 01 Snoops Sent : Broadcast snoop for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.bcst_remote uncore cache Snoops Sent : Broadcast snoops for Remote Requests event=0x51,umask=0x20 01 Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets unc_cha_snoops_sent.direct_local uncore cache Snoops Sent : Directed snoops for Local Requests event=0x51,umask=0x40 01 Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.direct_remote uncore cache Snoops Sent : Directed snoops for Remote Requests event=0x51,umask=0x80 01 Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets unc_cha_snoops_sent.local uncore cache Snoops Sent : Broadcast or directed Snoops sent for Local Requests event=0x51,umask=4 01 Snoops Sent : Broadcast or directed Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket unc_cha_snoops_sent.remote uncore cache Snoops Sent : Broadcast or directed Snoops sent for Remote Requests event=0x51,umask=8 01 Snoops Sent : Broadcast or directed Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket unc_cha_snoop_resp.rspcnflct uncore cache Snoop Responses Received : RSPCNFLCT* event=0x5c,umask=0x40 01 Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI unc_cha_snoop_resp.rspfwd uncore cache Snoop Responses Received : RspFwd event=0x5c,umask=0x80 01 Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp.rspfwdwb uncore cache Snoop Responses Received : Rsp*Fwd*WB event=0x5c,umask=0x20 01 Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_cha_snoop_resp.rsps uncore cache RspS Snoop Responses Received event=0x5c,umask=2 01 Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_cha_snoop_resp.rspwb uncore cache Snoop Responses Received : Rsp*WB event=0x5c,umask=0x10 01 Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership unc_cha_snoop_resp_local.rspcnflct uncore cache Snoop Responses Received Local : RspCnflct event=0x5d,umask=0x40 01 Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI unc_cha_snoop_resp_local.rspfwd uncore cache Snoop Responses Received Local : RspFwd event=0x5d,umask=0x80 01 Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp_local.rspfwdwb uncore cache Snoop Responses Received Local : Rsp*FWD*WB event=0x5d,umask=0x20 01 Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_cha_snoop_resp_local.rspi uncore cache Snoop Responses Received Local : RspI event=0x5d,umask=1 01 Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_cha_snoop_resp_local.rspifwd uncore cache Snoop Responses Received Local : RspIFwd event=0x5d,umask=4 01 Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE unc_cha_snoop_resp_local.rsps uncore cache Snoop Responses Received Local : RspS event=0x5d,umask=2 01 Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_cha_snoop_resp_local.rspsfwd uncore cache Snoop Responses Received Local : RspSFwd event=0x5d,umask=8 01 Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state unc_cha_snoop_resp_local.rspwb uncore cache Snoop Responses Received Local : Rsp*WB event=0x5d,umask=0x10 01 Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership unc_cha_snoop_rsp_misc.mtoi_rspdatam uncore cache Misc Snoop Responses Received : MtoI RspIDataM event=0x6b,umask=2 01 unc_cha_snoop_rsp_misc.mtoi_rspifwdm uncore cache Misc Snoop Responses Received : MtoI RspIFwdM event=0x6b,umask=1 01 unc_cha_snoop_rsp_misc.pulldataptl_hitllc uncore cache Misc Snoop Responses Received : Pull Data Partial - Hit LLC event=0x6b,umask=0x20 01 unc_cha_snoop_rsp_misc.pulldataptl_hitsf uncore cache Misc Snoop Responses Received : Pull Data Partial - Hit SF event=0x6b,umask=0x10 01 unc_cha_snoop_rsp_misc.rspifwdmptl_hitllc uncore cache Misc Snoop Responses Received : RspIFwdPtl Hit LLC event=0x6b,umask=8 01 unc_cha_snoop_rsp_misc.rspifwdmptl_hitsf uncore cache Misc Snoop Responses Received : RspIFwdPtl Hit SF event=0x6b,umask=4 01 unc_cha_tor_inserts.all uncore cache TOR Inserts : All event=0x35,umask=0xc001ffff 01 TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ddr uncore cache TOR Inserts : DDR Access event=0x35 01 TOR Inserts : DDR Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.evict uncore cache TOR Inserts : SF/LLC Evictions event=0x35,umask=2 01 TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.hit uncore cache TOR Inserts : Just Hits event=0x35 01 TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ia uncore cache TOR Inserts; All from Local IA event=0x35,umask=0xc001ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from IA Cores unc_cha_tor_inserts.ia_clflush uncore cache TOR Inserts;CLFlush from Local IA event=0x35,umask=0xc8c7ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlush events that are initiated from the Core unc_cha_tor_inserts.ia_clflushopt uncore cache TOR Inserts;CLFlushOpt from Local IA event=0x35,umask=0xc8d7ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlushOpt events that are initiated from the Core unc_cha_tor_inserts.ia_crd uncore cache TOR Inserts; CRd from local IA event=0x35,umask=0xc80fff01 01 TOR Inserts; Code read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_crd_pref uncore cache TOR Inserts; CRd Pref from local IA event=0x35,umask=0xc88fff01 01 TOR Inserts; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd uncore cache TOR Inserts; DRd from local IA event=0x35,umask=0xc817ff01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drdpte uncore cache TOR Inserts : DRd PTEs issued by iA Cores event=0x35,umask=0xc837ff01 01 TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_opt uncore cache TOR Inserts; DRd Opt from local IA event=0x35,umask=0xc827ff01 01 TOR Inserts; Data read opt from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd_opt_pref uncore cache TOR Inserts; DRd Opt Pref from local IA event=0x35,umask=0xc8a7ff01 01 TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd_pref uncore cache TOR Inserts; DRd Pref from local IA event=0x35,umask=0xc897ff01 01 TOR Inserts; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_hit uncore cache TOR Inserts; Hits from Local IA event=0x35,umask=0xc001fd01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ia_hit_crd uncore cache TOR Inserts; CRd hits from local IA event=0x35,umask=0xc80ffd01 01 TOR Inserts; Code read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_crd_pref uncore cache TOR Inserts; CRd Pref hits from local IA event=0x35,umask=0xc88ffd01 01 TOR Inserts; Code read prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_cxl_acc uncore cache All requests issued from IA cores to CXL accelerator memory regions that hit the LLC event=0x35,umask=0x10c0018101 01 unc_cha_tor_inserts.ia_hit_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL event=0x35,umask=0x10c0008101 01 unc_cha_tor_inserts.ia_hit_drd uncore cache TOR Inserts; DRd hits from local IA event=0x35,umask=0xc817fd01 01 TOR Inserts; Data read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_drdpte uncore cache TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC event=0x35,umask=0xc837fd01 01 TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_opt uncore cache TOR Inserts; DRd Opt hits from local IA event=0x35,umask=0xc827fd01 01 TOR Inserts; Data read opt from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_drd_opt_pref uncore cache TOR Inserts; DRd Opt Pref hits from local IA event=0x35,umask=0xc8a7fd01 01 TOR Inserts; Data read opt prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_drd_pref uncore cache TOR Inserts; DRd Pref hits from local IA event=0x35,umask=0xc897fd01 01 TOR Inserts; Data read prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Hit LLC event=0x35,umask=0xcc47fd01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcode uncore cache TOR Inserts; LLCPrefCode hits from local IA event=0x35,umask=0xcccffd01 01 TOR Inserts; Last level cache prefetch code read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_llcprefdata uncore cache TOR Inserts; LLCPrefData hits from local IA event=0x35,umask=0xccd7fd01 01 TOR Inserts; Last level cache prefetch data read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache TOR Inserts; LLCPrefRFO hits from local IA event=0x35,umask=0xccc7fd01 01 TOR Inserts; Last level cache prefetch read for ownership from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_rfo uncore cache TOR Inserts; RFO hits from local IA event=0x35,umask=0xc807fd01 01 TOR Inserts; Read for ownership from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_rfo_pref uncore cache TOR Inserts; RFO Pref hits from local IA event=0x35,umask=0xc887fd01 01 TOR Inserts; Read for ownership prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_itom uncore cache TOR Inserts;ItoM from Local IA event=0x35,umask=0xcc47ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; ItoM events that are initiated from the Core unc_cha_tor_inserts.ia_itomcachenear uncore cache TOR Inserts : ItoMCacheNears issued by iA Cores event=0x35,umask=0xcd47ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefcode uncore cache TOR Inserts; LLCPrefCode from local IA event=0x35,umask=0xcccfff01 01 TOR Inserts; Last level cache prefetch code read from local IA unc_cha_tor_inserts.ia_llcprefdata uncore cache TOR Inserts; LLCPrefData from local IA event=0x35,umask=0xccd7ff01 01 TOR Inserts; Last level cache prefetch data read from local IA unc_cha_tor_inserts.ia_llcprefrfo uncore cache TOR Inserts; LLCPrefRFO from local IA event=0x35,umask=0xccc7ff01 01 TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss uncore cache TOR Inserts; misses from Local IA event=0x35,umask=0xc001fe01 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd uncore cache TOR Inserts for CRd misses from local IA event=0x35,umask=0xc80ffe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd unc_cha_tor_inserts.ia_miss_crdmorph_cxl_acc uncore cache CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c80b8201 01 unc_cha_tor_inserts.ia_miss_crd_local uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc80efe01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref uncore cache TOR Inserts; CRd Pref misses from local IA event=0x35,umask=0xc88ffe01 01 TOR Inserts; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_crd_pref_local uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc88efe01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref_remote uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc88f7e01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_remote uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc80f7e01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_cxl_acc uncore cache All requests issued from IA cores to CXL accelerator memory regions that miss the LLC event=0x35,umask=0x10c0018201 01 unc_cha_tor_inserts.ia_miss_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL event=0x35,umask=0x10c0008201 01 unc_cha_tor_inserts.ia_miss_drd uncore cache TOR Inserts for DRd misses from local IA event=0x35,umask=0xc817fe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd unc_cha_tor_inserts.ia_miss_drdmorph_cxl_acc uncore cache DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8138201 01 unc_cha_tor_inserts.ia_miss_drdpte uncore cache TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC event=0x35,umask=0xc837fe01 01 TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_cxl_acc uncore cache DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card event=0x35,umask=0x10c8178201 01 unc_cha_tor_inserts.ia_miss_drd_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL event=0x35,umask=0x10c8168201 01 unc_cha_tor_inserts.ia_miss_drd_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_EXP_LOCAL event=0x35,umask=0x20c8168201 01 unc_cha_tor_inserts.ia_miss_drd_ddr uncore cache TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8178601 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory unc_cha_tor_inserts.ia_miss_drd_local uncore cache TOR Inserts for DRd misses from local IA targeting local memory event=0x35,umask=0xc816fe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory unc_cha_tor_inserts.ia_miss_drd_local_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_opt uncore cache TOR Inserts; DRd Opt misses from local IA event=0x35,umask=0xc827fe01 01 TOR Inserts; Data read opt from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_opt_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_LOCAL event=0x35,umask=0x10c8268201 01 unc_cha_tor_inserts.ia_miss_drd_opt_pref uncore cache TOR Inserts; DRd Opt Pref misses from local IA event=0x35,umask=0xc8a7fe01 01 TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_opt_pref_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL event=0x35,umask=0x10c8a68201 01 unc_cha_tor_inserts.ia_miss_drd_pmm uncore cache TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8178a01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory unc_cha_tor_inserts.ia_miss_drd_pref uncore cache TOR Inserts for DRd Pref misses from local IA event=0x35,umask=0xc897fe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF unc_cha_tor_inserts.ia_miss_drd_pref_cxl_acc uncore cache L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8978201 01 unc_cha_tor_inserts.ia_miss_drd_pref_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_LOCAL event=0x35,umask=0x10c8968201 01 unc_cha_tor_inserts.ia_miss_drd_pref_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_EXP_LOCAL event=0x35,umask=0x20c8968201 01 unc_cha_tor_inserts.ia_miss_drd_pref_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8978601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local uncore cache TOR Inserts for DRd Pref misses from local IA targeting local memory event=0x35,umask=0xc896fe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory unc_cha_tor_inserts.ia_miss_drd_pref_local_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8978a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote uncore cache TOR Inserts for DRd Pref misses from local IA targeting remote memory event=0x35,umask=0xc8977e01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory unc_cha_tor_inserts.ia_miss_drd_pref_remote_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote uncore cache TOR Inserts for DRd misses from local IA targeting remote memory event=0x35,umask=0xc8177e01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory unc_cha_tor_inserts.ia_miss_drd_remote_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Missed LLC event=0x35,umask=0xcc47fe01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefcode uncore cache TOR Inserts; LLCPrefCode misses from local IA event=0x35,umask=0xcccffe01 01 TOR Inserts; Last level cache prefetch code read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_llcprefcode_cxl_acc uncore cache LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10cccf8201 01 unc_cha_tor_inserts.ia_miss_llcprefdata uncore cache TOR Inserts; LLCPrefData misses from local IA event=0x35,umask=0xccd7fe01 01 TOR Inserts; Last level cache prefetch data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_llcprefdata_cxl_acc uncore cache LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10ccd78201 01 unc_cha_tor_inserts.ia_miss_llcprefdata_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL event=0x35,umask=0x10ccd68201 01 unc_cha_tor_inserts.ia_miss_llcprefdata_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_EXP_LOCAL event=0x35,umask=0x20ccd68201 01 unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache TOR Inserts; LLCPrefRFO misses from local IA event=0x35,umask=0xccc7fe01 01 TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_llcprefrfo_cxl_acc uncore cache L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8878201 01 unc_cha_tor_inserts.ia_miss_llcprefrfo_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL event=0x35,umask=0x10c8868201 01 unc_cha_tor_inserts.ia_miss_llcprefrfo_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_EXP_LOCAL event=0x35,umask=0x20c8868201 01 unc_cha_tor_inserts.ia_miss_local_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc8668601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc8668a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc86e8601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc86e8a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc8670601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x35,umask=0xc8670a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo uncore cache TOR Inserts; RFO misses from local IA event=0x35,umask=0xc807fe01 01 TOR Inserts; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfomorph_cxl_acc uncore cache RFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8038201 01 unc_cha_tor_inserts.ia_miss_rfo_cxl_acc uncore cache RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8078201 01 unc_cha_tor_inserts.ia_miss_rfo_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL event=0x35,umask=0x10c8068201 01 unc_cha_tor_inserts.ia_miss_rfo_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_EXP_LOCAL event=0x35,umask=0x20c8068201 01 unc_cha_tor_inserts.ia_miss_rfo_local uncore cache TOR Inserts RFO misses from local IA event=0x35,umask=0xc806fe01 01 TOR Inserts; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_pref uncore cache TOR Inserts; RFO pref misses from local IA event=0x35,umask=0xc887fe01 01 TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_pref_cxl_acc uncore cache LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10ccc78201 01 unc_cha_tor_inserts.ia_miss_rfo_pref_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_LOCAL event=0x35,umask=0x10ccc68201 01 unc_cha_tor_inserts.ia_miss_rfo_pref_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_EXP_LOCAL event=0x35,umask=0x20ccc68201 01 unc_cha_tor_inserts.ia_miss_rfo_pref_local uncore cache TOR Inserts; RFO prefetch misses from local IA event=0x35,umask=0xc886fe01 01 TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_pref_remote uncore cache TOR Inserts; RFO prefetch misses from local IA event=0x35,umask=0xc8877e01 01 TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_remote uncore cache TOR Inserts; RFO misses from local IA event=0x35,umask=0xc8077e01 01 TOR Inserts Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_ucrdf uncore cache TOR Inserts : UCRdFs issued by iA Cores that Missed LLC event=0x35,umask=0xc877de01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores that Missed the LLC event=0x35,umask=0xc86ffe01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores that Missed the LLC event=0x35,umask=0xc867fe01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc8678601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc8678a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc86f8601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc86f8a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wil uncore cache TOR Inserts : WiLs issued by iA Cores that Missed LLC event=0x35,umask=0xc87fde01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_rfo uncore cache TOR Inserts; RFO from local IA event=0x35,umask=0xc807ff01 01 TOR Inserts; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_rfo_pref uncore cache TOR Inserts; RFO pref from local IA event=0x35,umask=0xc887ff01 01 TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_specitom uncore cache TOR Inserts;SpecItoM from Local IA event=0x35,umask=0xcc57ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; SpecItoM events that are initiated from the Core unc_cha_tor_inserts.ia_wbeftoe uncore cache TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc3fff01 01 WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbeftoi uncore cache TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc37ff01 01 WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbmtoe uncore cache TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc2fff01 01 WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbmtoi uncore cache TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs event=0x35,umask=0xcc27ff01 01 WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbstoi uncore cache TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc67ff01 01 WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores event=0x35,umask=0xc86fff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores event=0x35,umask=0xc867ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io uncore cache TOR Inserts; All from local IO event=0x35,umask=0xc001ff04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_clflush uncore cache TOR Inserts : CLFlushes issued by IO Devices event=0x35,umask=0xc8c3ff04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit uncore cache TOR Inserts; Hits from local IO event=0x35,umask=0xc001fd04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_itom uncore cache TOR Inserts; ItoM hits from local IO event=0x35,umask=0xcc43fd04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_itomcachenear uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC event=0x35,umask=0xcd43fd04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_pcirdcur uncore cache TOR Inserts; RdCur and FsRdCur hits from local IO event=0x35,umask=0xc8f3fd04 01 TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_rfo uncore cache TOR Inserts; RFO hits from local IO event=0x35,umask=0xc803fd04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom uncore cache TOR Inserts for ItoM from local IO event=0x35,umask=0xcc43ff04 01 Inserts into the TOR from local IO with the opcode ItoM unc_cha_tor_inserts.io_itomcachenear uncore cache TOR Inserts for ItoMCacheNears from IO devices event=0x35,umask=0xcd43ff04 01 Inserts into the TOR from local IO devices with the opcode ItoMCacheNears. This event indicates a partial write request unc_cha_tor_inserts.io_itomcachenear_local uncore cache ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xcd42ff04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear_remote uncore cache ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xcd437f04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom_local uncore cache ItoM (write) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xcc42ff04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom_remote uncore cache ItoM (write) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xcc437f04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss uncore cache TOR Inserts; Misses from local IO event=0x35,umask=0xc001fe04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_itom uncore cache TOR Inserts : ItoM, indicating a full cacheline write request, from IO Devices that missed the LLC event=0x35,umask=0xcc43fe04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_itomcachenear uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC event=0x35,umask=0xcd43fe04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_pcirdcur uncore cache TOR Inserts; RdCur and FsRdCur requests from local IO that miss LLC event=0x35,umask=0xc8f3fe04 01 TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_rfo uncore cache TOR Inserts; RFO misses from local IO event=0x35,umask=0xc803fe04 01 TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur uncore cache TOR Inserts for RdCur from local IO event=0x35,umask=0xc8f3ff04 01 Inserts into the TOR from local IO with the opcode RdCur unc_cha_tor_inserts.io_pcirdcur_local uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xc8f2ff04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur_remote uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xc8f37f04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_rfo uncore cache TOR Inserts; RFO from local IO event=0x35,umask=0xc803ff04 01 TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_wbmtoi uncore cache TOR Inserts : WbMtoIs issued by IO Devices event=0x35,umask=0xcc23ff04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ipq uncore cache TOR Inserts : IPQ event=0x35,umask=8 01 TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.irq_ia uncore cache TOR Inserts : IRQ - iA event=0x35,umask=1 01 TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From an iA Core unc_cha_tor_inserts.irq_non_ia uncore cache TOR Inserts : IRQ - Non iA event=0x35,umask=0x10 01 TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.isoc uncore cache TOR Inserts : Just ISOC event=0x35 01 TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.local_tgt uncore cache TOR Inserts : Just Local Targets event=0x35 01 TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.loc_all uncore cache TOR Inserts : All from Local iA and IO event=0x35,umask=0xc000ff05 01 TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests unc_cha_tor_inserts.loc_ia uncore cache TOR Inserts : All from Local iA event=0x35,umask=0xc000ff01 01 TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests from iA Cores unc_cha_tor_inserts.loc_io uncore cache TOR Inserts : All from Local IO event=0x35,umask=0xc000ff04 01 TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally generated IO traffic unc_cha_tor_inserts.match_opc uncore cache TOR Inserts : Match the Opcode in b[29:19] of the extended umask field event=0x35 01 TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.miss uncore cache TOR Inserts : Just Misses event=0x35 01 TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.mmcfg uncore cache TOR Inserts : MMCFG Access event=0x35 01 TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.mmio uncore cache TOR Inserts : MMIO Access event=0x35 01 TOR Inserts : MMIO Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.nearmem uncore cache TOR Inserts : Just NearMem event=0x35 01 TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.noncoh uncore cache TOR Inserts : Just NonCoherent event=0x35 01 TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.not_nearmem uncore cache TOR Inserts : Just NotNearMem event=0x35 01 TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.pmm uncore cache TOR Inserts : PMM Access event=0x35 01 TOR Inserts : PM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.premorph_opc uncore cache TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x35 01 TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.prq_iosf uncore cache TOR Inserts : PRQ - IOSF event=0x35,umask=4 01 TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From a PCIe Device unc_cha_tor_inserts.prq_non_iosf uncore cache TOR Inserts : PRQ - Non IOSF event=0x35,umask=0x20 01 TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.remote_tgt uncore cache TOR Inserts : Just Remote Targets event=0x35 01 TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.rem_all uncore cache TOR Inserts : All from Remote event=0x35,umask=0xc001ffc8 01 TOR Inserts : All from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All remote requests (e.g. snoops, writebacks) that came from remote sockets unc_cha_tor_inserts.rem_snps uncore cache TOR Inserts : All Snoops from Remote event=0x35,umask=0xc001ff08 01 TOR Inserts : All Snoops from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All snoops to this LLC that came from remote sockets unc_cha_tor_inserts.rrq uncore cache TOR Inserts : RRQ event=0x35,umask=0x40 01 TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.rrq_miss_invxtom_cxl_exp_local uncore cache TOR Inserts for INVXTOM opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x35,umask=0x20e87e8240 01 unc_cha_tor_inserts.rrq_miss_rdcode_cxl_exp_local uncore cache TOR Inserts for RDCODE opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x35,umask=0x20e80e8240 01 unc_cha_tor_inserts.rrq_miss_rdcur_cxl_exp_local uncore cache TOR Inserts for RDCUR opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x35,umask=0x20e8068240 01 unc_cha_tor_inserts.rrq_miss_rddata_cxl_exp_local uncore cache TOR Inserts for RDDATA opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x35,umask=0x20e8168240 01 unc_cha_tor_inserts.rrq_miss_rdinvown_opt_cxl_exp_local uncore cache TOR Inserts for RDINVOWN_OPT opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x35,umask=0x20e8268240 01 unc_cha_tor_inserts.snps_from_rem uncore cache TOR Inserts; All Snoops from Remote event=0x35,umask=0xc001ff08 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets unc_cha_tor_inserts.wbq uncore cache TOR Inserts : WBQ event=0x35,umask=0x80 01 TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_occupancy.all uncore cache TOR Occupancy : All event=0x36,umask=0xc001ffff 01 TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.ddr uncore cache TOR Occupancy : DDR Access event=0x36 01 TOR Occupancy : DDR Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent unc_cha_tor_occupancy.evict uncore cache TOR Occupancy : SF/LLC Evictions event=0x36,umask=2 01 TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_occupancy.hit uncore cache TOR Occupancy : Just Hits event=0x36 01 TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.ia uncore cache TOR Occupancy; All from local IA event=0x36,umask=0xc001ff01 01 TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_clflush uncore cache TOR Occupancy : CLFlushes issued by iA Cores event=0x36,umask=0xc8c7ff01 01 TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_clflushopt uncore cache TOR Occupancy : CLFlushOpts issued by iA Cores event=0x36,umask=0xc8d7ff01 01 TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_crd uncore cache TOR Occupancy; CRd from local IA event=0x36,umask=0xc80fff01 01 TOR Occupancy; Code read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_crd_pref uncore cache TOR Occupancy; CRd Pref from local IA event=0x36,umask=0xc88fff01 01 TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd uncore cache TOR Occupancy; DRd from local IA event=0x36,umask=0xc817ff01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk event=0x36,umask=0xc837ff01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_opt uncore cache TOR Occupancy; DRd Opt from local IA event=0x36,umask=0xc827ff01 01 TOR Occupancy; Data read opt from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd_opt_pref uncore cache TOR Occupancy; DRd Opt Pref from local IA event=0x36,umask=0xc8a7ff01 01 TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd_pref uncore cache TOR Occupancy; DRd Pref from local IA event=0x36,umask=0xc897ff01 01 TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy; Hits from local IA event=0x36,umask=0xc001fd01 01 TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy; CRd hits from local IA event=0x36,umask=0xc80ffd01 01 TOR Occupancy; Code read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_crd_pref uncore cache TOR Occupancy; CRd Pref hits from local IA event=0x36,umask=0xc88ffd01 01 TOR Occupancy; Code read prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_cxl_acc uncore cache TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC event=0x36,umask=0x10c0018101 01 unc_cha_tor_occupancy.ia_hit_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL event=0x36,umask=0x10c0008101 01 unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy; DRd hits from local IA event=0x36,umask=0xc817fd01 01 TOR Occupancy; Data read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC event=0x36,umask=0xc837fd01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_opt uncore cache TOR Occupancy; DRd Opt hits from local IA event=0x36,umask=0xc827fd01 01 TOR Occupancy; Data read opt from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_drd_opt_pref uncore cache TOR Occupancy; DRd Opt Pref hits from local IA event=0x36,umask=0xc8a7fd01 01 TOR Occupancy; Data read opt prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_drd_pref uncore cache TOR Occupancy; DRd Pref hits from local IA event=0x36,umask=0xc897fd01 01 TOR Occupancy; Data read prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_itom uncore cache TOR Occupancy : ItoMs issued by iA Cores that Hit LLC event=0x36,umask=0xcc47fd01 01 TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefcode uncore cache TOR Occupancy; LLCPrefCode hits from local IA event=0x36,umask=0xcccffd01 01 TOR Occupancy; Last level cache prefetch code read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_llcprefdata uncore cache TOR Occupancy; LLCPrefData hits from local IA event=0x36,umask=0xccd7fd01 01 TOR Occupancy; Last level cache prefetch data read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy; LLCPrefRFO hits from local IA event=0x36,umask=0xccc7fd01 01 TOR Occupancy; Last level cache prefetch read for ownership from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy; RFO hits from local IA event=0x36,umask=0xc807fd01 01 TOR Occupancy; Read for ownership from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_rfo_pref uncore cache TOR Occupancy; RFO Pref hits from local IA event=0x36,umask=0xc887fd01 01 TOR Occupancy; Read for ownership prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_itom uncore cache TOR Occupancy : ItoMs issued by iA Cores event=0x36,umask=0xcc47ff01 01 TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears issued by iA Cores event=0x36,umask=0xcd47ff01 01 TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefcode uncore cache TOR Occupancy; LLCPrefCode from local IA event=0x36,umask=0xcccfff01 01 TOR Occupancy; Last level cache prefetch data read from local IA unc_cha_tor_occupancy.ia_llcprefdata uncore cache TOR Occupancy; LLCPrefData from local IA event=0x36,umask=0xccd7ff01 01 TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_llcprefrfo uncore cache TOR Occupancy; LLCPrefRFO from local IA event=0x36,umask=0xccc7ff01 01 TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy; Misses from Local IA event=0x36,umask=0xc001fe01 01 TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy; CRd misses from local IA event=0x36,umask=0xc80ffe01 01 TOR Occupancy; Code read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_crdmorph_cxl_acc uncore cache TOR Occupancy for CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c80b8201 01 unc_cha_tor_occupancy.ia_miss_crd_local uncore cache TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc80efe01 01 TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_pref uncore cache TOR Occupancy; CRd Pref misses from local IA event=0x36,umask=0xc88ffe01 01 TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_crd_pref_local uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc88efe01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_pref_remote uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc88f7e01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_remote uncore cache TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc80f7e01 01 TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_cxl_acc uncore cache TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC event=0x36,umask=0x10c0018201 01 unc_cha_tor_occupancy.ia_miss_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL event=0x36,umask=0x10c0008201 01 unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy for DRd misses from local IA event=0x36,umask=0xc817fe01 01 Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd unc_cha_tor_occupancy.ia_miss_drdmorph_cxl_acc uncore cache TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8138201 01 unc_cha_tor_occupancy.ia_miss_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC event=0x36,umask=0xc837fe01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_cxl_acc uncore cache TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card event=0x36,umask=0x10c8178201 01 unc_cha_tor_occupancy.ia_miss_drd_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOCAL event=0x36,umask=0x10c8168201 01 unc_cha_tor_occupancy.ia_miss_drd_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_EXP_LOCAL event=0x36,umask=0x20c8168201 01 unc_cha_tor_occupancy.ia_miss_drd_ddr uncore cache TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8178601 01 Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory unc_cha_tor_occupancy.ia_miss_drd_local uncore cache TOR Occupancy for DRd misses from local IA targeting local memory event=0x36,umask=0xc816fe01 01 Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory unc_cha_tor_occupancy.ia_miss_drd_local_ddr uncore cache TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8168601 01 TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_local_pmm uncore cache TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8168a01 01 TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_opt uncore cache TOR Occupancy; DRd Opt misses from local IA event=0x36,umask=0xc827fe01 01 TOR Occupancy; Data read opt from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_opt_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC_LOCAL event=0x36,umask=0x10c8268201 01 unc_cha_tor_occupancy.ia_miss_drd_opt_pref uncore cache TOR Occupancy; DRd Opt Pref misses from local IA event=0x36,umask=0xc8a7fe01 01 TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_opt_pref_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL event=0x36,umask=0x10c8a68201 01 unc_cha_tor_occupancy.ia_miss_drd_pmm uncore cache TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8178a01 01 Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory unc_cha_tor_occupancy.ia_miss_drd_pref uncore cache TOR Occupancy; DRd Pref misses from local IA event=0x36,umask=0xc897fe01 01 TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_cxl_acc uncore cache TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8978201 01 unc_cha_tor_occupancy.ia_miss_drd_pref_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC_LOCAL event=0x36,umask=0x10c8968201 01 unc_cha_tor_occupancy.ia_miss_drd_pref_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_EXP_LOCAL event=0x36,umask=0x20c8968201 01 unc_cha_tor_occupancy.ia_miss_drd_pref_ddr uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8978601 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_local uncore cache TOR Occupancy; DRd Pref misses from local IA event=0x36,umask=0xc896fe01 01 TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_local_ddr uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8968601 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_local_pmm uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8968a01 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_pmm uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8978a01 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_remote uncore cache TOR Occupancy; DRd Pref misses from local IA event=0x36,umask=0xc8977e01 01 TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_remote_ddr uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8970601 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_remote_pmm uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8970a01 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_remote uncore cache TOR Occupancy for DRd misses from local IA targeting remote memory event=0x36,umask=0xc8177e01 01 Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory unc_cha_tor_occupancy.ia_miss_drd_remote_ddr uncore cache TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8170601 01 TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_remote_pmm uncore cache TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8170a01 01 TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_itom uncore cache TOR Occupancy : ItoMs issued by iA Cores that Missed LLC event=0x36,umask=0xcc47fe01 01 TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefcode uncore cache TOR Occupancy; LLCPrefCode misses from local IA event=0x36,umask=0xcccffe01 01 TOR Occupancy; Last level cache prefetch code read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefcode_cxl_acc uncore cache TOR Occupancy for LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10cccf8201 01 unc_cha_tor_occupancy.ia_miss_llcprefdata uncore cache TOR Occupancy; LLCPrefData misses from local IA event=0x36,umask=0xccd7fe01 01 TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefdata_cxl_acc uncore cache TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10ccd78201 01 unc_cha_tor_occupancy.ia_miss_llcprefdata_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL event=0x36,umask=0x10ccd68201 01 unc_cha_tor_occupancy.ia_miss_llcprefdata_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_EXP_LOCAL event=0x36,umask=0x20ccd68201 01 unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy; LLCPrefRFO misses from local IA event=0x36,umask=0xccc7fe01 01 TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefrfo_cxl_acc uncore cache TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8878201 01 unc_cha_tor_occupancy.ia_miss_llcprefrfo_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL event=0x36,umask=0x10c8868201 01 unc_cha_tor_occupancy.ia_miss_llcprefrfo_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_EXP_LOCAL event=0x36,umask=0x20c8868201 01 unc_cha_tor_occupancy.ia_miss_local_wcilf_ddr uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x36,umask=0xc8668601 01 TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_local_wcilf_pmm uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x36,umask=0xc8668a01 01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_local_wcil_ddr uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x36,umask=0xc86e8601 01 TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_local_wcil_pmm uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x36,umask=0xc86e8a01 01 TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcilf_ddr uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x36,umask=0xc8670601 01 TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcilf_pmm uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x36,umask=0xc8670a01 01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcil_ddr uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x36,umask=0xc86f0601 01 TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcil_pmm uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x36,umask=0xc86f0a01 01 TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy; RFO misses from local IA event=0x36,umask=0xc807fe01 01 TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfomorph_cxl_acc uncore cache TOR Occupancy for RFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8038201 01 unc_cha_tor_occupancy.ia_miss_rfo_cxl_acc uncore cache TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8078201 01 unc_cha_tor_occupancy.ia_miss_rfo_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOCAL event=0x36,umask=0x10c8068201 01 unc_cha_tor_occupancy.ia_miss_rfo_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_EXP_LOCAL event=0x36,umask=0x20c8068201 01 unc_cha_tor_occupancy.ia_miss_rfo_local uncore cache TOR Occupancy; RFO misses from local IA event=0x36,umask=0xc806fe01 01 TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_pref uncore cache TOR Occupancy; RFO prefetch misses from local IA event=0x36,umask=0xc887fe01 01 TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_pref_cxl_acc uncore cache TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10ccc78201 01 unc_cha_tor_occupancy.ia_miss_rfo_pref_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC_LOCAL event=0x36,umask=0x10ccc68201 01 unc_cha_tor_occupancy.ia_miss_rfo_pref_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_EXP_LOCAL event=0x36,umask=0x20ccc68201 01 unc_cha_tor_occupancy.ia_miss_rfo_pref_local uncore cache TOR Occupancy; RFO prefetch misses from local IA event=0x36,umask=0xc886fe01 01 TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_pref_remote uncore cache TOR Occupancy; RFO prefetch misses from local IA event=0x36,umask=0xc8877e01 01 TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_remote uncore cache TOR Occupancy; RFO misses from local IA event=0x36,umask=0xc8077e01 01 TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_ucrdf uncore cache TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC event=0x36,umask=0xc877de01 01 TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcil uncore cache TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC event=0x36,umask=0xc86ffe01 01 TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcilf uncore cache TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC event=0x36,umask=0xc867fe01 01 TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcilf_ddr uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC event=0x36,umask=0xc8678601 01 TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcilf_pmm uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC event=0x36,umask=0xc8678a01 01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcil_ddr uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC event=0x36,umask=0xc86f8601 01 TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcil_pmm uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC event=0x36,umask=0xc86f8a01 01 TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wil uncore cache TOR Occupancy : WiLs issued by iA Cores that Missed LLC event=0x36,umask=0xc87fde01 01 TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_rfo uncore cache TOR Occupancy; RFO from local IA event=0x36,umask=0xc807ff01 01 TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_rfo_pref uncore cache TOR Occupancy; RFO prefetch from local IA event=0x36,umask=0xc887ff01 01 TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_specitom uncore cache TOR Occupancy : SpecItoMs issued by iA Cores event=0x36,umask=0xcc57ff01 01 TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_wbmtoi uncore cache TOR Occupancy : WbMtoIs issued by iA Cores event=0x36,umask=0xcc27ff01 01 TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_wcil uncore cache TOR Occupancy : WCiLs issued by iA Cores event=0x36,umask=0xc86fff01 01 TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_wcilf uncore cache TOR Occupancy : WCiLF issued by iA Cores event=0x36,umask=0xc867ff01 01 TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io uncore cache TOR Occupancy; All from local IO event=0x36,umask=0xc001ff04 01 TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_clflush uncore cache TOR Occupancy : CLFlushes issued by IO Devices event=0x36,umask=0xc8c3ff04 01 TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy; Hits from local IO event=0x36,umask=0xc001fd04 01 TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_itom uncore cache TOR Occupancy; ITOM hits from local IO event=0x36,umask=0xcc43fd04 01 TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC event=0x36,umask=0xcd43fd04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_pcirdcur uncore cache TOR Occupancy; RdCur and FsRdCur hits from local IO event=0x36,umask=0xc8f3fd04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_rfo uncore cache TOR Occupancy; RFO hits from local IO event=0x36,umask=0xc803fd04 01 TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_itom uncore cache TOR Occupancy; ITOM from local IO event=0x36,umask=0xcc43ff04 01 TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices event=0x36,umask=0xcd43ff04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy; Misses from local IO event=0x36,umask=0xc001fe04 01 TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy; ITOM misses from local IO event=0x36,umask=0xcc43fe04 01 TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC event=0x36,umask=0xcd43fe04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itomcachenear_local uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC and targets local memory event=0x36,umask=0xcd42fe04 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itomcachenear_remote uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC and targets remote memory event=0x36,umask=0xcd437e04 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itom_local uncore cache TOR Occupancy; ITOM misses from local IO and targets local memory event=0x36,umask=0xcc42fe04 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itom_remote uncore cache TOR Occupancy; ITOM misses from local IO and targets remote memory event=0x36,umask=0xcc437e04 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_pcirdcur uncore cache TOR Occupancy; RdCur and FsRdCur misses from local IO event=0x36,umask=0xc8f3fe04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_pcirdcur_local uncore cache TOR Occupancy; RdCur and FsRdCur misses from local IO and targets local memory event=0x36,umask=0xc8f2fe04 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_pcirdcur_remote uncore cache TOR Occupancy; RdCur and FsRdCur misses from local IO and targets remote memory event=0x36,umask=0xc8f37e04 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy; RFO misses from local IO event=0x36,umask=0xc803fe04 01 TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_pcirdcur uncore cache TOR Occupancy; RdCur and FsRdCur from local IO event=0x36,umask=0xc8f3ff04 01 TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_rfo uncore cache TOR Occupancy; ItoM from local IO event=0x36,umask=0xc803ff04 01 TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_wbmtoi uncore cache TOR Occupancy : WbMtoIs issued by IO Devices event=0x36,umask=0xcc23ff04 01 TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ipq uncore cache TOR Occupancy : IPQ event=0x36,umask=8 01 TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.irq_ia uncore cache TOR Occupancy : IRQ - iA event=0x36,umask=1 01 TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From an iA Core unc_cha_tor_occupancy.irq_non_ia uncore cache TOR Occupancy : IRQ - Non iA event=0x36,umask=0x10 01 TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.isoc uncore cache TOR Occupancy : Just ISOC event=0x36 01 TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.local_tgt uncore cache TOR Occupancy : Just Local Targets event=0x36 01 TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.loc_all uncore cache TOR Occupancy : All from Local iA and IO event=0x36,umask=0xc000ff05 01 TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests unc_cha_tor_occupancy.loc_ia uncore cache TOR Occupancy : All from Local iA event=0x36,umask=0xc000ff01 01 TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests from iA Cores unc_cha_tor_occupancy.loc_io uncore cache TOR Occupancy : All from Local IO event=0x36,umask=0xc000ff04 01 TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally generated IO traffic unc_cha_tor_occupancy.match_opc uncore cache TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field event=0x36 01 TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.miss uncore cache TOR Occupancy : Just Misses event=0x36 01 TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.mmcfg uncore cache TOR Occupancy : MMCFG Access event=0x36 01 TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.mmio uncore cache TOR Occupancy : MMIO Access event=0x36 01 TOR Occupancy : MMIO Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.nearmem uncore cache TOR Occupancy : Just NearMem event=0x36 01 TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.noncoh uncore cache TOR Occupancy : Just NonCoherent event=0x36 01 TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.not_nearmem uncore cache TOR Occupancy : Just NotNearMem event=0x36 01 TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.pmm uncore cache TOR Occupancy : PMM Access event=0x36 01 TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent unc_cha_tor_occupancy.premorph_opc uncore cache TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x36 01 TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.prq uncore cache TOR Occupancy : PRQ - IOSF event=0x36,umask=4 01 TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From a PCIe Device unc_cha_tor_occupancy.prq_non_iosf uncore cache TOR Occupancy : PRQ - Non IOSF event=0x36,umask=0x20 01 TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.remote_tgt uncore cache TOR Occupancy : Just Remote Targets event=0x36 01 TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.rem_all uncore cache TOR Occupancy : All from Remote event=0x36,umask=0xc001ffc8 01 TOR Occupancy : All from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All remote requests (e.g. snoops, writebacks) that came from remote sockets unc_cha_tor_occupancy.rem_snps uncore cache TOR Occupancy : All Snoops from Remote event=0x36,umask=0xc001ff08 01 TOR Occupancy : All Snoops from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All snoops to this LLC that came from remote sockets unc_cha_tor_occupancy.rrq uncore cache TOR Occupancy : RRQ event=0x36,umask=0x40 01 TOR Occupancy : RRQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.rrq_miss_invxtom_cxl_exp_local uncore cache TOR Occupancy for INVXTOM opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x36,umask=0x20e87e8240 01 unc_cha_tor_occupancy.rrq_miss_rdcode_cxl_exp_local uncore cache TOR Occupancy for RDCODE opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x36,umask=0x20e80e8240 01 unc_cha_tor_occupancy.rrq_miss_rdcur_cxl_exp_local uncore cache TOR Occupancy for RDCUR opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x36,umask=0x20e8068240 01 unc_cha_tor_occupancy.rrq_miss_rddata_cxl_exp_local uncore cache TOR Occupancy for RDDATA opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x36,umask=0x20e8168240 01 unc_cha_tor_occupancy.rrq_miss_rdinvown_opt_cxl_exp_local uncore cache TOR Occupancy for RDINVOWN_OPT opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x36,umask=0x20e8268240 01 unc_cha_tor_occupancy.snps_from_rem uncore cache TOR Occupancy; All Snoops from Remote event=0x36,umask=0xc001ff08 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets unc_cha_tor_occupancy.wbq uncore cache TOR Occupancy : WBQ event=0x36,umask=0x80 01 TOR Occupancy : WBQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_wb_push_mtoi.llc uncore cache WbPushMtoI : Pushed to LLC event=0x56,umask=1 01 WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC unc_cha_wb_push_mtoi.mem uncore cache WbPushMtoI : Pushed to Memory event=0x56,umask=2 01 WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM) unc_cha_write_no_credits.mc0 uncore cache CHA iMC CHNx WRITE Credits Empty : MC0 event=0x5a,umask=1 01 CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only unc_cha_write_no_credits.mc1 uncore cache CHA iMC CHNx WRITE Credits Empty : MC1 event=0x5a,umask=2 01 CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only unc_cha_write_no_credits.mc2 uncore cache CHA iMC CHNx WRITE Credits Empty : MC2 event=0x5a,umask=4 01 CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only unc_cha_write_no_credits.mc3 uncore cache CHA iMC CHNx WRITE Credits Empty : MC3 event=0x5a,umask=8 01 CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only unc_cha_write_no_credits.mc4 uncore cache CHA iMC CHNx WRITE Credits Empty : MC4 event=0x5a,umask=0x10 01 CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only unc_cha_write_no_credits.mc5 uncore cache CHA iMC CHNx WRITE Credits Empty : MC5 event=0x5a,umask=0x20 01 CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only unc_cha_xpt_pref.drop0_conflict uncore cache XPT Prefetches : Dropped (on 0?) - Conflict event=0x6f,umask=8 01 XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention unc_cha_xpt_pref.drop0_nocrd uncore cache XPT Prefetches : Dropped (on 0?) - No Credits event=0x6f,umask=4 01 XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits unc_cha_xpt_pref.drop1_conflict uncore cache XPT Prefetches : Dropped (on 1?) - Conflict event=0x6f,umask=0x80 01 XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention unc_cha_xpt_pref.drop1_nocrd uncore cache XPT Prefetches : Dropped (on 1?) - No Credits event=0x6f,umask=0x40 01 XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits unc_cha_xpt_pref.sent0 uncore cache XPT Prefetches : Sent (on 0?) event=0x6f,umask=1 01 XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent unc_cha_xpt_pref.sent1 uncore cache XPT Prefetches : Sent (on 1?) event=0x6f,umask=0x10 01 XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent uncore_cxlcm unc_cxlcm_clockticks uncore cxl Counts the number of lfclk ticks event=1,umask=2 01 unc_cxlcm_rxc_agf_inserts.cache_data uncore cxl Number of Allocation to Mem Rxx AGF 0 event=0x43,umask=8 01 unc_cxlcm_rxc_agf_inserts.cache_req0 uncore cxl Number of Allocation to Cache Req AGF0 event=0x43,umask=1 01 unc_cxlcm_rxc_agf_inserts.cache_req1 uncore cxl Number of Allocation to Cache Rsp AGF event=0x43,umask=2 01 unc_cxlcm_rxc_agf_inserts.cache_rsp0 uncore cxl Number of Allocation to Cache Data AGF event=0x43,umask=4 01 unc_cxlcm_rxc_agf_inserts.cache_rsp1 uncore cxl Number of Allocation to Cache Rsp AGF event=0x43,umask=0x40 01 unc_cxlcm_rxc_agf_inserts.mem_data uncore cxl Number of Allocation to Cache Req AGF 1 event=0x43,umask=0x20 01 unc_cxlcm_rxc_agf_inserts.mem_req uncore cxl Number of Allocation to Mem Data AGF event=0x43,umask=0x10 01 unc_cxlcm_rxc_flits.ak_hdr uncore cxl Count the number of Flits with AK set event=0x4b,umask=0x10 01 unc_cxlcm_rxc_flits.be_hdr uncore cxl Count the number of Flits with BE set event=0x4b,umask=0x20 01 unc_cxlcm_rxc_flits.ctrl uncore cxl Count the number of control flits received event=0x4b,umask=4 01 unc_cxlcm_rxc_flits.no_hdr uncore cxl Count the number of Headerless flits received event=0x4b,umask=8 01 unc_cxlcm_rxc_flits.prot uncore cxl Count the number of protocol flits received event=0x4b,umask=2 01 unc_cxlcm_rxc_flits.sz_hdr uncore cxl Count the number of Flits with SZ set event=0x4b,umask=0x40 01 unc_cxlcm_rxc_flits.valid uncore cxl Count the number of flits received event=0x4b,umask=1 01 unc_cxlcm_rxc_flits.valid_msg uncore cxl Count the number of valid messages in the flit event=0x4b,umask=0x80 01 unc_cxlcm_rxc_misc.crc_errors uncore cxl Count the number of CRC errors detected event=0x40,umask=8 01 unc_cxlcm_rxc_misc.init uncore cxl Count the number of Init flits sent event=0x40,umask=4 01 unc_cxlcm_rxc_misc.llcrd uncore cxl Count the number of LLCRD flits sent event=0x40,umask=1 01 unc_cxlcm_rxc_misc.retry uncore cxl Count the number of Retry flits sent event=0x40,umask=2 01 unc_cxlcm_rxc_pack_buf_full.cache_data uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=4 01 unc_cxlcm_rxc_pack_buf_full.cache_req uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=1 01 unc_cxlcm_rxc_pack_buf_full.cache_rsp uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=2 01 unc_cxlcm_rxc_pack_buf_full.mem_data uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=0x10 01 unc_cxlcm_rxc_pack_buf_full.mem_req uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=8 01 unc_cxlcm_rxc_pack_buf_inserts.cache_data uncore cxl Number of Allocation to Cache Data Packing buffer event=0x41,umask=4 01 unc_cxlcm_rxc_pack_buf_inserts.cache_req uncore cxl Number of Allocation to Cache Req Packing buffer event=0x41,umask=1 01 unc_cxlcm_rxc_pack_buf_inserts.cache_rsp uncore cxl Number of Allocation to Cache Rsp Packing buffer event=0x41,umask=2 01 unc_cxlcm_rxc_pack_buf_inserts.mem_data uncore cxl Number of Allocation to Mem Data Packing buffer event=0x41,umask=0x10 01 unc_cxlcm_rxc_pack_buf_inserts.mem_req uncore cxl Number of Allocation to Mem Rxx Packing buffer event=0x41,umask=8 01 unc_cxlcm_rxc_pack_buf_ne.cache_data uncore cxl Number of cycles of Not Empty for Cache Data Packing buffer event=0x42,umask=4 01 unc_cxlcm_rxc_pack_buf_ne.cache_req uncore cxl Number of cycles of Not Empty for Cache Req Packing buffer event=0x42,umask=1 01 unc_cxlcm_rxc_pack_buf_ne.cache_rsp uncore cxl Number of cycles of Not Empty for Cache Rsp Packing buffer event=0x42,umask=2 01 unc_cxlcm_rxc_pack_buf_ne.mem_data uncore cxl Number of cycles of Not Empty for Mem Data Packing buffer event=0x42,umask=0x10 01 unc_cxlcm_rxc_pack_buf_ne.mem_req uncore cxl Number of cycles of Not Empty for Mem Rxx Packing buffer event=0x42,umask=8 01 unc_cxlcm_txc_flits.ak_hdr uncore cxl Count the number of Flits with AK set event=5,umask=0x10 01 unc_cxlcm_txc_flits.be_hdr uncore cxl Count the number of Flits with BE set event=5,umask=0x20 01 unc_cxlcm_txc_flits.ctrl uncore cxl Count the number of control flits packed event=5,umask=4 01 unc_cxlcm_txc_flits.no_hdr uncore cxl Count the number of Headerless flits packed event=5,umask=8 01 unc_cxlcm_txc_flits.prot uncore cxl Count the number of protocol flits packed event=5,umask=2 01 unc_cxlcm_txc_flits.sz_hdr uncore cxl Count the number of Flits with SZ set event=5,umask=0x40 01 unc_cxlcm_txc_flits.valid uncore cxl Count the number of flits packed event=5,umask=1 01 unc_cxlcm_txc_pack_buf_inserts.cache_data uncore cxl Number of Allocation to Cache Data Packing buffer event=2,umask=4 01 unc_cxlcm_txc_pack_buf_inserts.cache_req0 uncore cxl Number of Allocation to Cache Req Packing buffer event=2,umask=1 01 unc_cxlcm_txc_pack_buf_inserts.cache_req1 uncore cxl Number of Allocation to Cache Rsp1 Packing buffer event=2,umask=0x40 01 unc_cxlcm_txc_pack_buf_inserts.cache_rsp0 uncore cxl Number of Allocation to Cache Rsp0 Packing buffer event=2,umask=2 01 unc_cxlcm_txc_pack_buf_inserts.cache_rsp1 uncore cxl Number of Allocation to Cache Req Packing buffer event=2,umask=0x20 01 unc_cxlcm_txc_pack_buf_inserts.mem_data uncore cxl Number of Allocation to Mem Data Packing buffer event=2,umask=0x10 01 unc_cxlcm_txc_pack_buf_inserts.mem_req uncore cxl Number of Allocation to Mem Rxx Packing buffer event=2,umask=8 01 uncore_cxldp unc_cxldp_clockticks uncore cxl Counts the number of uclk ticks event=1,umask=1 01 unc_cxldp_txc_agf_inserts.m2s_data uncore cxl Number of Allocation to M2S Data AGF event=2,umask=0x20 01 unc_cxldp_txc_agf_inserts.m2s_req uncore cxl Number of Allocation to M2S Req AGF event=2,umask=0x10 01 unc_cxldp_txc_agf_inserts.u2c_data uncore cxl Number of Allocation to U2C Data AGF event=2,umask=8 01 unc_cxldp_txc_agf_inserts.u2c_req uncore cxl Number of Allocation to U2C Req AGF event=2,umask=1 01 unc_cxldp_txc_agf_inserts.u2c_rsp0 uncore cxl Number of Allocation to U2C Rsp AGF 0 event=2,umask=2 01 unc_cxldp_txc_agf_inserts.u2c_rsp1 uncore cxl Number of Allocation to U2C Rsp AGF 1 event=2,umask=4 01 unc_i_cache_total_occupancy.mem uncore interconnect Total IRP occupancy of inbound read and write requests to coherent memory event=0xf,umask=4 01 Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy unc_i_clockticks uncore interconnect IRP Clockticks event=1 01 Number of IRP clock cycles while the event is enabled unc_i_faf_inserts uncore interconnect FAF - request insert from TC event=0x18 01 unc_i_faf_occupancy uncore interconnect FAF occupancy event=0x19 01 unc_i_irp_all.evicts uncore interconnect : All Inserts Outbound (BL, AK, Snoops) event=0x20,umask=4 01 unc_i_irp_all.inbound_inserts uncore interconnect : All Inserts Inbound (p2p + faf + cset) event=0x20,umask=1 01 unc_i_irp_all.outbound_inserts uncore interconnect : All Inserts Outbound (BL, AK, Snoops) event=0x20,umask=2 01 unc_i_misc0.2nd_atomic_insert uncore interconnect Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary event=0x1e,umask=0x10 01 unc_i_misc0.2nd_rd_insert uncore interconnect Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary event=0x1e,umask=4 01 unc_i_misc0.2nd_wr_insert uncore interconnect Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary event=0x1e,umask=8 01 unc_i_misc0.fast_rej uncore interconnect Counts Timeouts - Set 0 : Fastpath Rejects event=0x1e,umask=2 01 unc_i_misc0.fast_req uncore interconnect Counts Timeouts - Set 0 : Fastpath Requests event=0x1e,umask=1 01 unc_i_misc0.fast_xfer uncore interconnect Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary event=0x1e,umask=0x20 01 unc_i_misc0.pf_ack_hint uncore interconnect Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary event=0x1e,umask=0x40 01 unc_i_misc0.slowpath_fwpf_no_prf uncore interconnect Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch event=0x1e,umask=0x80 01 unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1 : Lost Forward event=0x1f,umask=0x10 01 Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed unc_i_misc1.sec_rcvd_invld uncore interconnect Misc Events - Set 1 : Received Invalid event=0x1f,umask=0x20 01 Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state unc_i_misc1.sec_rcvd_vld uncore interconnect Misc Events - Set 1 : Received Valid event=0x1f,umask=0x40 01 Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_e uncore interconnect Misc Events - Set 1 : Slow Transfer of E Line event=0x1f,umask=4 01 Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_i uncore interconnect Misc Events - Set 1 : Slow Transfer of I Line event=0x1f,umask=1 01 Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_m uncore interconnect Misc Events - Set 1 : Slow Transfer of M Line event=0x1f,umask=8 01 Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_s uncore interconnect Misc Events - Set 1 : Slow Transfer of S Line event=0x1f,umask=2 01 Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state unc_i_snoop_resp.hit_es uncore interconnect Snoop Responses : Hit E or S event=0x12,umask=4 01 unc_i_snoop_resp.hit_i uncore interconnect Snoop Responses : Hit I event=0x12,umask=2 01 unc_i_snoop_resp.hit_m uncore interconnect Snoop Responses : Hit M event=0x12,umask=8 01 unc_i_snoop_resp.miss uncore interconnect Snoop Responses : Miss event=0x12,umask=1 01 unc_i_snoop_resp.snpcode uncore interconnect Snoop Responses : SnpCode event=0x12,umask=0x10 01 unc_i_snoop_resp.snpdata uncore interconnect Snoop Responses : SnpData event=0x12,umask=0x20 01 unc_i_snoop_resp.snpinv uncore interconnect Snoop Responses : SnpInv event=0x12,umask=0x40 01 unc_i_txr2_ad01_stall_credit_cycles uncore interconnect UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES event=0x1c 01 : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0AD1 both. Stalls on both AD0 and AD1 will count as 2 unc_i_txr2_ad0_stall_credit_cycles uncore interconnect No AD0 Egress Credits Stalls event=0x1a 01 No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available unc_i_txr2_ad1_stall_credit_cycles uncore interconnect No AD1 Egress Credits Stalls event=0x1b 01 No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available unc_i_txr2_bl_stall_credit_cycles uncore interconnect No BL Egress Credit Stalls event=0x1d 01 No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available unc_i_txs_data_inserts_ncb uncore interconnect Outbound Read Requests event=0xd 01 Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices) unc_i_txs_data_inserts_ncs uncore interconnect Outbound Read Requests event=0xe 01 Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices) unc_i_txs_request_occupancy uncore interconnect Outbound Request Queue Occupancy event=0xc 01 Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests unc_m2m_clockticks uncore interconnect M2M Clockticks event=1 01 Clockticks of the mesh to memory (M2M) unc_m2m_direct2core_not_taken_dirstate uncore interconnect Cycles when direct to core mode (which bypasses the CHA) was disabled event=0x17,umask=7 01 unc_m2m_direct2core_not_taken_dirstate.non_cisgress uncore interconnect Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress event=0x17,umask=2 01 Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress : Counts the number of time non cisgress D2C was not honoured by egress due to directory state constraints unc_m2m_direct2core_not_taken_notforked uncore interconnect Counts the time when FM didn't do d2c for fill reads (cross tile case) event=0x4a 01 unc_m2m_direct2core_txn_override uncore interconnect Number of reads in which direct to core transaction were overridden event=0x18,umask=3 01 unc_m2m_direct2core_txn_override.cisgress uncore interconnect Number of reads in which direct to core transaction was overridden : Cisgress event=0x18,umask=2 01 unc_m2m_direct2core_txn_override.pmm_hit uncore interconnect Number of reads in which direct to core transaction was overridden : 2LM Hit? event=0x18,umask=1 01 unc_m2m_direct2upitxn_override.pmm_hit uncore interconnect Number of times a direct to UPI transaction was overridden event=0x1c,umask=1 01 Number of times a direct to UPI transaction was overridden. : Counts the number of times D2K wasn't honored even though the incoming request had d2k set unc_m2m_direct2upi_not_taken_credits uncore interconnect Number of reads in which direct to Intel UPI transactions were overridden event=0x1b,umask=7 01 unc_m2m_direct2upi_not_taken_dirstate uncore interconnect Cycles when direct to Intel UPI was disabled event=0x1a,umask=7 01 unc_m2m_direct2upi_not_taken_dirstate.cisgress uncore interconnect Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored event=0x1a,umask=4 01 Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored : Counts cisgress d2K that was not honored due to directory constraints unc_m2m_direct2upi_not_taken_dirstate.egress uncore interconnect Cycles when Direct2UPI was Disabled : Egress Ignored D2U event=0x1a,umask=1 01 Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints unc_m2m_direct2upi_not_taken_dirstate.non_cisgress uncore interconnect Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored event=0x1a,umask=2 01 Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored : Counts non cisgress d2K that was not honored due to directory constraints unc_m2m_direct2upi_taken uncore interconnect Messages sent direct to the Intel UPI event=0x19,umask=7 01 Counts the number of times egress did D2K (Direct to KTI) unc_m2m_direct2upi_txn_override uncore interconnect Number of reads that a message sent direct2 Intel UPI was overridden event=0x1c,umask=3 01 unc_m2m_direct2upi_txn_override.cisgress uncore interconnect Number of times a direct to UPI transaction was overridden event=0x1c,umask=2 01 unc_m2m_directory_hit.clean_a uncore interconnect Directory Hit : On NonDirty Line in A State event=0x1d,umask=0x80 01 unc_m2m_directory_hit.clean_i uncore interconnect Directory Hit : On NonDirty Line in I State event=0x1d,umask=0x10 01 unc_m2m_directory_hit.clean_p uncore interconnect Directory Hit : On NonDirty Line in L State event=0x1d,umask=0x40 01 unc_m2m_directory_hit.clean_s uncore interconnect Directory Hit : On NonDirty Line in S State event=0x1d,umask=0x20 01 unc_m2m_directory_hit.dirty_a uncore interconnect Directory Hit : On Dirty Line in A State event=0x1d,umask=8 01 unc_m2m_directory_hit.dirty_i uncore interconnect Directory Hit : On Dirty Line in I State event=0x1d,umask=1 01 unc_m2m_directory_hit.dirty_p uncore interconnect Directory Hit : On Dirty Line in L State event=0x1d,umask=4 01 unc_m2m_directory_hit.dirty_s uncore interconnect Directory Hit : On Dirty Line in S State event=0x1d,umask=2 01 unc_m2m_directory_lookup.any uncore interconnect Multi-socket cacheline Directory lookups (any state found) event=0x20,umask=1 01 Counts the number of hit data returns to egress with any directory to non persistent memory unc_m2m_directory_lookup.state_a uncore interconnect Multi-socket cacheline Directory lookups (cacheline found in A state) event=0x20,umask=8 01 Counts the number of hit data returns to egress with directory A to non persistent memory unc_m2m_directory_lookup.state_i uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in I state) event=0x20,umask=2 01 Counts the number of hit data returns to egress with directory I to non persistent memory unc_m2m_directory_lookup.state_s uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in S state) event=0x20,umask=4 01 Counts the number of hit data returns to egress with directory S to non persistent memory unc_m2m_directory_miss.clean_a uncore interconnect Directory Miss : On NonDirty Line in A State event=0x1e,umask=0x80 01 unc_m2m_directory_miss.clean_i uncore interconnect Directory Miss : On NonDirty Line in I State event=0x1e,umask=0x10 01 unc_m2m_directory_miss.clean_p uncore interconnect Directory Miss : On NonDirty Line in L State event=0x1e,umask=0x40 01 unc_m2m_directory_miss.clean_s uncore interconnect Directory Miss : On NonDirty Line in S State event=0x1e,umask=0x20 01 unc_m2m_directory_miss.dirty_a uncore interconnect Directory Miss : On Dirty Line in A State event=0x1e,umask=8 01 unc_m2m_directory_miss.dirty_i uncore interconnect Directory Miss : On Dirty Line in I State event=0x1e,umask=1 01 unc_m2m_directory_miss.dirty_p uncore interconnect Directory Miss : On Dirty Line in L State event=0x1e,umask=4 01 unc_m2m_directory_miss.dirty_s uncore interconnect Directory Miss : On Dirty Line in S State event=0x1e,umask=2 01 unc_m2m_directory_update.a2i uncore interconnect Multi-socket cacheline Directory update from A to I event=0x21,umask=0x320 01 unc_m2m_directory_update.a2s uncore interconnect Multi-socket cacheline Directory update from A to S event=0x21,umask=0x340 01 unc_m2m_directory_update.any uncore interconnect Multi-socket cacheline Directory update from/to Any state event=0x21,umask=0x301 01 unc_m2m_directory_update.a_to_i_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x120 01 Counts 1lm or 2lm hit data returns that would result in directory update from A to I to non persistent memory (DRAM or HBM) unc_m2m_directory_update.a_to_i_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x220 01 Counts 2lm miss data returns that would result in directory update from A to I to non persistent memory (DRAM or HBM) unc_m2m_directory_update.a_to_s_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x140 01 Counts 1lm or 2lm hit data returns that would result in directory update from A to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.a_to_s_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x240 01 Counts 2lm miss data returns that would result in directory update from A to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x101 01 Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i2a uncore interconnect Multi-socket cacheline Directory update from I to A event=0x21,umask=0x304 01 unc_m2m_directory_update.i2s uncore interconnect Multi-socket cacheline Directory update from I to S event=0x21,umask=0x302 01 unc_m2m_directory_update.i_to_a_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x104 01 Counts 1lm or 2lm hit data returns that would result in directory update from I to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i_to_a_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x204 01 Counts 2lm miss data returns that would result in directory update from I to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i_to_s_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x102 01 Counts 1lm or 2lm hit data returns that would result in directory update from I to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i_to_s_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x202 01 Counts 2lm miss data returns that would result in directory update from I to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x201 01 Counts any 2lm miss data return that would result in directory update to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s2a uncore interconnect Multi-socket cacheline Directory update from S to A event=0x21,umask=0x310 01 unc_m2m_directory_update.s2i uncore interconnect Multi-socket cacheline Directory update from S to I event=0x21,umask=0x308 01 unc_m2m_directory_update.s_to_a_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x110 01 Counts 1lm or 2lm hit data returns that would result in directory update from S to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s_to_a_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x210 01 Counts 2lm miss data returns that would result in directory update from S to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s_to_i_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x108 01 Counts 1lm or 2lm hit data returns that would result in directory update from S to I to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s_to_i_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x208 01 Counts 2lm miss data returns that would result in directory update from S to I to non persistent memory (DRAM or HBM) unc_m2m_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements : Down event=0xba,umask=0x80000004 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements : Up event=0xba,umask=0x80000001 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_igr_starve_winner.mask7 uncore interconnect Count when Starve Glocab counter is at 7 event=0x44,umask=0x80 01 unc_m2m_imc_reads.all uncore interconnect Reads to iMC issued event=0x24,umask=0x304 01 unc_m2m_imc_reads.ch0.to_nm1lm uncore interconnect UNC_M2M_IMC_READS.CH0.TO_NM1LM event=0x24,umask=0x108 01 unc_m2m_imc_reads.ch0.to_nmcache uncore interconnect UNC_M2M_IMC_READS.CH0.TO_NMCache event=0x24,umask=0x110 01 unc_m2m_imc_reads.ch0_all uncore interconnect UNC_M2M_IMC_READS.CH0_ALL event=0x24,umask=0x104 01 unc_m2m_imc_reads.ch0_from_tgr uncore interconnect UNC_M2M_IMC_READS.CH0_FROM_TGR event=0x24,umask=0x140 01 unc_m2m_imc_reads.ch0_isoch uncore interconnect UNC_M2M_IMC_READS.CH0_ISOCH event=0x24,umask=0x102 01 unc_m2m_imc_reads.ch0_normal uncore interconnect UNC_M2M_IMC_READS.CH0_NORMAL event=0x24,umask=0x101 01 unc_m2m_imc_reads.ch0_to_ddr_as_cache uncore interconnect UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE event=0x24,umask=0x110 01 unc_m2m_imc_reads.ch0_to_ddr_as_mem uncore interconnect UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM event=0x24,umask=0x108 01 unc_m2m_imc_reads.ch0_to_pmm uncore interconnect UNC_M2M_IMC_READS.CH0_TO_PMM event=0x24,umask=0x120 01 unc_m2m_imc_reads.ch1.to_nm1lm uncore interconnect UNC_M2M_IMC_READS.CH1.TO_NM1LM event=0x24,umask=0x208 01 unc_m2m_imc_reads.ch1.to_nmcache uncore interconnect UNC_M2M_IMC_READS.CH1.TO_NMCache event=0x24,umask=0x210 01 unc_m2m_imc_reads.ch1_all uncore interconnect UNC_M2M_IMC_READS.CH1_ALL event=0x24,umask=0x204 01 unc_m2m_imc_reads.ch1_from_tgr uncore interconnect UNC_M2M_IMC_READS.CH1_FROM_TGR event=0x24,umask=0x240 01 unc_m2m_imc_reads.ch1_isoch uncore interconnect UNC_M2M_IMC_READS.CH1_ISOCH event=0x24,umask=0x202 01 unc_m2m_imc_reads.ch1_normal uncore interconnect UNC_M2M_IMC_READS.CH1_NORMAL event=0x24,umask=0x201 01 unc_m2m_imc_reads.ch1_to_ddr_as_cache uncore interconnect UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE event=0x24,umask=0x210 01 unc_m2m_imc_reads.ch1_to_ddr_as_mem uncore interconnect UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM event=0x24,umask=0x208 01 unc_m2m_imc_reads.ch1_to_pmm uncore interconnect UNC_M2M_IMC_READS.CH1_TO_PMM event=0x24,umask=0x220 01 unc_m2m_imc_reads.from_tgr uncore interconnect UNC_M2M_IMC_READS.FROM_TGR event=0x24,umask=0x340 01 unc_m2m_imc_reads.isoch uncore interconnect UNC_M2M_IMC_READS.ISOCH event=0x24,umask=0x302 01 unc_m2m_imc_reads.normal uncore interconnect UNC_M2M_IMC_READS.NORMAL event=0x24,umask=0x301 01 unc_m2m_imc_reads.to_ddr_as_cache uncore interconnect UNC_M2M_IMC_READS.TO_DDR_AS_CACHE event=0x24,umask=0x310 01 unc_m2m_imc_reads.to_ddr_as_mem uncore interconnect UNC_M2M_IMC_READS.TO_DDR_AS_MEM event=0x24,umask=0x308 01 unc_m2m_imc_reads.to_nm1lm uncore interconnect UNC_M2M_IMC_READS.TO_NM1LM event=0x24,umask=0x308 01 unc_m2m_imc_reads.to_nmcache uncore interconnect UNC_M2M_IMC_READS.TO_NMCACHE event=0x24,umask=0x310 01 unc_m2m_imc_reads.to_pmm uncore interconnect UNC_M2M_IMC_READS.TO_PMM event=0x24,umask=0x320 01 unc_m2m_imc_writes.all uncore interconnect All Writes - All Channels event=0x25,umask=0x1810 01 unc_m2m_imc_writes.ch0.ni uncore interconnect Non-Inclusive - Ch0 event=0x25 01 unc_m2m_imc_writes.ch0_all uncore interconnect UNC_M2M_IMC_WRITES.CH0_ALL event=0x25,umask=0x810 01 unc_m2m_imc_writes.ch0_from_tgr uncore interconnect From TGR - Ch0 event=0x25 01 unc_m2m_imc_writes.ch0_full uncore interconnect UNC_M2M_IMC_WRITES.CH0_FULL event=0x25,umask=0x801 01 unc_m2m_imc_writes.ch0_full_isoch uncore interconnect UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH event=0x25,umask=0x804 01 unc_m2m_imc_writes.ch0_ni uncore interconnect Non-Inclusive - Ch0 event=0x25 01 unc_m2m_imc_writes.ch0_ni_miss uncore interconnect Non-Inclusive Miss - Ch0 event=0x25 01 unc_m2m_imc_writes.ch0_partial uncore interconnect UNC_M2M_IMC_WRITES.CH0_PARTIAL event=0x25,umask=0x802 01 unc_m2m_imc_writes.ch0_partial_isoch uncore interconnect UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH event=0x25,umask=0x808 01 unc_m2m_imc_writes.ch0_to_ddr_as_cache uncore interconnect DDR, acting as Cache - Ch0 event=0x25,umask=0x840 01 unc_m2m_imc_writes.ch0_to_ddr_as_mem uncore interconnect UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM event=0x25,umask=0x820 01 unc_m2m_imc_writes.ch0_to_pmm uncore interconnect PMM - Ch0 event=0x25,umask=0x880 01 PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.ch1.ni uncore interconnect Non-Inclusive - Ch1 event=0x25 01 unc_m2m_imc_writes.ch1_all uncore interconnect All Writes - Ch1 event=0x25,umask=0x1010 01 unc_m2m_imc_writes.ch1_from_tgr uncore interconnect From TGR - Ch1 event=0x25 01 unc_m2m_imc_writes.ch1_full uncore interconnect Full Line Non-ISOCH - Ch1 event=0x25,umask=0x1001 01 unc_m2m_imc_writes.ch1_full_isoch uncore interconnect ISOCH Full Line - Ch1 event=0x25,umask=0x1004 01 unc_m2m_imc_writes.ch1_ni uncore interconnect Non-Inclusive - Ch1 event=0x25 01 unc_m2m_imc_writes.ch1_ni_miss uncore interconnect Non-Inclusive Miss - Ch1 event=0x25 01 unc_m2m_imc_writes.ch1_partial uncore interconnect Partial Non-ISOCH - Ch1 event=0x25,umask=0x1002 01 unc_m2m_imc_writes.ch1_partial_isoch uncore interconnect ISOCH Partial - Ch1 event=0x25,umask=0x1008 01 unc_m2m_imc_writes.ch1_to_ddr_as_cache uncore interconnect DDR, acting as Cache - Ch1 event=0x25,umask=0x1040 01 unc_m2m_imc_writes.ch1_to_ddr_as_mem uncore interconnect DDR - Ch1 event=0x25,umask=0x1020 01 unc_m2m_imc_writes.ch1_to_pmm uncore interconnect PMM - Ch1 event=0x25,umask=0x1080 01 PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.from_tgr uncore interconnect From TGR - All Channels event=0x25 01 unc_m2m_imc_writes.full uncore interconnect Full Non-ISOCH - All Channels event=0x25,umask=0x1801 01 unc_m2m_imc_writes.full_isoch uncore interconnect ISOCH Full Line - All Channels event=0x25,umask=0x1804 01 unc_m2m_imc_writes.ni uncore interconnect Non-Inclusive - All Channels event=0x25 01 unc_m2m_imc_writes.ni_miss uncore interconnect Non-Inclusive Miss - All Channels event=0x25 01 unc_m2m_imc_writes.partial uncore interconnect Partial Non-ISOCH - All Channels event=0x25,umask=0x1802 01 unc_m2m_imc_writes.partial_isoch uncore interconnect ISOCH Partial - All Channels event=0x25,umask=0x1808 01 unc_m2m_imc_writes.to_ddr_as_cache uncore interconnect DDR, acting as Cache - All Channels event=0x25,umask=0x1840 01 unc_m2m_imc_writes.to_ddr_as_mem uncore interconnect DDR - All Channels event=0x25,umask=0x1820 01 unc_m2m_imc_writes.to_pmm uncore interconnect PMM - All Channels event=0x25,umask=0x1880 01 unc_m2m_prefcam_cis_drops uncore interconnect UNC_M2M_PREFCAM_CIS_DROPS event=0x5c 01 unc_m2m_prefcam_demand_drops.ch0_upi uncore interconnect Data Prefetches Dropped event=0x58,umask=2 01 unc_m2m_prefcam_demand_drops.ch0_xpt uncore interconnect Data Prefetches Dropped event=0x58,umask=1 01 unc_m2m_prefcam_demand_drops.ch1_upi uncore interconnect Data Prefetches Dropped event=0x58,umask=8 01 unc_m2m_prefcam_demand_drops.ch1_xpt uncore interconnect Data Prefetches Dropped event=0x58,umask=4 01 unc_m2m_prefcam_demand_drops.upi_allch uncore interconnect Data Prefetches Dropped : UPI - All Channels event=0x58,umask=0xa 01 unc_m2m_prefcam_demand_drops.xpt_allch uncore interconnect Data Prefetches Dropped event=0x58,umask=5 01 unc_m2m_prefcam_demand_merge.upi_allch uncore interconnect : UPI - All Channels event=0x5d,umask=0xa 01 unc_m2m_prefcam_demand_merge.xpt_allch uncore interconnect : XPT - All Channels event=0x5d,umask=5 01 unc_m2m_prefcam_demand_no_merge.rd_merged uncore interconnect Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x40 01 unc_m2m_prefcam_demand_no_merge.wr_merged uncore interconnect Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x20 01 unc_m2m_prefcam_demand_no_merge.wr_squashed uncore interconnect Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x10 01 unc_m2m_prefcam_inserts.ch0_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 0 event=0x56,umask=2 01 unc_m2m_prefcam_inserts.ch0_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 0 event=0x56,umask=1 01 unc_m2m_prefcam_inserts.ch1_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 1 event=0x56,umask=8 01 unc_m2m_prefcam_inserts.ch1_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 1 event=0x56,umask=4 01 unc_m2m_prefcam_inserts.upi_allch uncore interconnect Prefetch CAM Inserts : UPI - All Channels event=0x56,umask=0xa 01 unc_m2m_prefcam_inserts.xpt_allch uncore interconnect Prefetch CAM Inserts : XPT - All Channels event=0x56,umask=5 01 Prefetch CAM Inserts : XPT -All Channels unc_m2m_prefcam_occupancy.allch uncore interconnect Prefetch CAM Occupancy : All Channels event=0x54,umask=3 01 unc_m2m_prefcam_occupancy.ch0 uncore interconnect Prefetch CAM Occupancy : Channel 0 event=0x54,umask=1 01 unc_m2m_prefcam_occupancy.ch1 uncore interconnect Prefetch CAM Occupancy : Channel 1 event=0x54,umask=2 01 unc_m2m_prefcam_resp_miss.allch uncore interconnect All Channels event=0x5f,umask=3 01 unc_m2m_prefcam_resp_miss.ch0 uncore interconnect : Channel 0 event=0x5f,umask=1 01 unc_m2m_prefcam_resp_miss.ch1 uncore interconnect : Channel 1 event=0x5f,umask=2 01 unc_m2m_prefcam_rxc_deallocs.1lm_posted uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED event=0x62,umask=2 01 unc_m2m_prefcam_rxc_deallocs.cis uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS event=0x62,umask=8 01 unc_m2m_prefcam_rxc_deallocs.pmm_memmode_accept uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT event=0x62,umask=4 01 unc_m2m_prefcam_rxc_deallocs.squashed uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED event=0x62,umask=1 01 unc_m2m_prefcam_rxc_occupancy uncore interconnect AD Ingress (from CMS) Occupancy - Prefetches event=0x60 01 unc_m2m_rxc_ad_inserts uncore interconnect AD Ingress (from CMS) : AD Ingress (from CMS) Allocations event=2,umask=1 01 unc_m2m_rxc_ad_occupancy uncore interconnect AD Ingress (from CMS) Occupancy event=3 01 unc_m2m_tag_hit.nm_rd_hit_clean uncore interconnect Clean NearMem Read Hit event=0x1f,umask=1 01 Counts clean full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_rd_hit_dirty uncore interconnect Dirty NearMem Read Hit event=0x1f,umask=2 01 Counts dirty full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_ufill_hit_clean uncore interconnect Tag Hit : Clean NearMem Underfill Hit event=0x1f,umask=4 01 Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write unc_m2m_tag_hit.nm_ufill_hit_dirty uncore interconnect Tag Hit : Dirty NearMem Underfill Hit event=0x1f,umask=8 01 Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write unc_m2m_tag_miss uncore interconnect UNC_M2M_TAG_MISS event=0x4b,umask=3 01 unc_m2m_tgr_ad_credits uncore interconnect Number AD Ingress Credits event=0x2e 01 unc_m2m_tgr_bl_credits uncore interconnect Number BL Ingress Credits event=0x2f 01 unc_m2m_tracker_inserts.ch0 uncore interconnect Tracker Inserts : Channel 0 event=0x32,umask=0x104 01 unc_m2m_tracker_inserts.ch1 uncore interconnect Tracker Inserts : Channel 1 event=0x32,umask=0x204 01 unc_m2m_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy : Channel 0 event=0x33,umask=1 01 unc_m2m_tracker_occupancy.ch1 uncore interconnect Tracker Occupancy : Channel 1 event=0x33,umask=2 01 unc_m2m_wpq_flush.ch0 uncore interconnect WPQ Flush : Channel 0 event=0x42,umask=1 01 unc_m2m_wpq_flush.ch1 uncore interconnect WPQ Flush : Channel 1 event=0x42,umask=2 01 unc_m2m_wpq_no_reg_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0 event=0x37,umask=1 01 unc_m2m_wpq_no_reg_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1 event=0x37,umask=2 01 unc_m2m_wpq_no_spec_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 0 event=0x38,umask=1 01 unc_m2m_wpq_no_spec_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 1 event=0x38,umask=2 01 unc_m2m_wr_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts : Channel 0 event=0x40,umask=1 01 unc_m2m_wr_tracker_inserts.ch1 uncore interconnect Write Tracker Inserts : Channel 1 event=0x40,umask=2 01 unc_m2m_wr_tracker_ne.ch0 uncore interconnect Write Tracker Cycles Not Empty : Channel 0 event=0x35,umask=1 01 unc_m2m_wr_tracker_ne.ch1 uncore interconnect Write Tracker Cycles Not Empty : Channel 1 event=0x35,umask=2 01 unc_m2m_wr_tracker_ne.mirr uncore interconnect Write Tracker Cycles Not Empty : Mirror event=0x35,umask=4 01 unc_m2m_wr_tracker_ne.mirr_nontgr uncore interconnect Write Tracker Cycles Not Empty event=0x35,umask=8 01 unc_m2m_wr_tracker_ne.mirr_pwr uncore interconnect Write Tracker Cycles Not Empty event=0x35,umask=0x10 01 unc_m2m_wr_tracker_nonposted_inserts.ch0 uncore interconnect Write Tracker Non-Posted Inserts : Channel 0 event=0x4d,umask=1 01 unc_m2m_wr_tracker_nonposted_inserts.ch1 uncore interconnect Write Tracker Non-Posted Inserts : Channel 1 event=0x4d,umask=2 01 unc_m2m_wr_tracker_nonposted_occupancy.ch0 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 0 event=0x4c,umask=1 01 unc_m2m_wr_tracker_nonposted_occupancy.ch1 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 1 event=0x4c,umask=2 01 unc_m2m_wr_tracker_posted_inserts.ch0 uncore interconnect Write Tracker Posted Inserts : Channel 0 event=0x48,umask=1 01 unc_m2m_wr_tracker_posted_inserts.ch1 uncore interconnect Write Tracker Posted Inserts : Channel 1 event=0x48,umask=2 01 unc_m2m_wr_tracker_posted_occupancy.ch0 uncore interconnect Write Tracker Posted Occupancy : Channel 0 event=0x47,umask=1 01 unc_m2m_wr_tracker_posted_occupancy.ch1 uncore interconnect Write Tracker Posted Occupancy : Channel 1 event=0x47,umask=2 01 unc_m3upi_cha_ad_credits_empty.req uncore interconnect CBox AD Credits Empty : Requests event=0x22,umask=4 01 CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.snp uncore interconnect CBox AD Credits Empty : Snoops event=0x22,umask=8 01 CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.vna uncore interconnect CBox AD Credits Empty : VNA Messages event=0x22,umask=1 01 CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.wb uncore interconnect CBox AD Credits Empty : Writebacks event=0x22,umask=2 01 CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_clockticks uncore interconnect M3UPI Clockticks event=1 01 Number of M2UPI clock cycles while the event is enabled unc_m3upi_cms_clockticks uncore interconnect M3UPI CMS Clockticks event=0xc0 01 unc_m3upi_d2c_sent uncore interconnect D2C Sent event=0x2b 01 D2C Sent : Count cases BL sends direct to core unc_m3upi_d2u_sent uncore interconnect D2U Sent event=0x2a 01 D2U Sent : Cases where SMI3 sends D2U command unc_m3upi_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements : Down event=0xba,umask=4 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements : Up event=0xba,umask=1 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_m2_bl_credits_empty.iio1_ncb uncore interconnect M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) event=0x23,umask=1 01 M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio2_ncb uncore interconnect M2 BL Credits Empty : IIO2 event=0x23,umask=2 01 M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio3_ncb uncore interconnect M2 BL Credits Empty : IIO3 event=0x23,umask=4 01 M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio4_ncb uncore interconnect M2 BL Credits Empty : IIO4 event=0x23,umask=8 01 M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio5_ncb uncore interconnect M2 BL Credits Empty : IIO5 event=0x23,umask=0x10 01 M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs uncore interconnect M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together event=0x23,umask=0x40 01 M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs_sel uncore interconnect M2 BL Credits Empty : Selected M2p BL NCS credits event=0x23,umask=0x80 01 M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ubox_ncb uncore interconnect M2 BL Credits Empty : IIO5 event=0x23,umask=0x20 01 M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2 unc_m3upi_multi_slot_rcvd.ad_slot0 uncore interconnect Multi Slot Flit Received : AD - Slot 0 event=0x3e,umask=1 01 Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot1 uncore interconnect Multi Slot Flit Received : AD - Slot 1 event=0x3e,umask=2 01 Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot2 uncore interconnect Multi Slot Flit Received : AD - Slot 2 event=0x3e,umask=4 01 Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot0 uncore interconnect Multi Slot Flit Received : AK - Slot 0 event=0x3e,umask=0x10 01 Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot2 uncore interconnect Multi Slot Flit Received : AK - Slot 2 event=0x3e,umask=0x20 01 Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.bl_slot0 uncore interconnect Multi Slot Flit Received : BL - Slot 0 event=0x3e,umask=8 01 Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_rxc_arb_lost_vn0.ad_req uncore interconnect Lost Arb for VN0 : REQ on AD event=0x4b,umask=1 01 Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn0.ad_rsp uncore interconnect Lost Arb for VN0 : RSP on AD event=0x4b,umask=4 01 Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.ad_snp uncore interconnect Lost Arb for VN0 : SNP on AD event=0x4b,umask=2 01 Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn0.bl_ncb uncore interconnect Lost Arb for VN0 : NCB on BL event=0x4b,umask=0x20 01 Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn0.bl_ncs uncore interconnect Lost Arb for VN0 : NCS on BL event=0x4b,umask=0x40 01 Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn0.bl_rsp uncore interconnect Lost Arb for VN0 : RSP on BL event=0x4b,umask=8 01 Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.bl_wb uncore interconnect Lost Arb for VN0 : WB on BL event=0x4b,umask=0x10 01 Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_lost_vn1.ad_req uncore interconnect Lost Arb for VN1 : REQ on AD event=0x4c,umask=1 01 Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn1.ad_rsp uncore interconnect Lost Arb for VN1 : RSP on AD event=0x4c,umask=4 01 Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.ad_snp uncore interconnect Lost Arb for VN1 : SNP on AD event=0x4c,umask=2 01 Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn1.bl_ncb uncore interconnect Lost Arb for VN1 : NCB on BL event=0x4c,umask=0x20 01 Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn1.bl_ncs uncore interconnect Lost Arb for VN1 : NCS on BL event=0x4c,umask=0x40 01 Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn1.bl_rsp uncore interconnect Lost Arb for VN1 : RSP on BL event=0x4c,umask=8 01 Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.bl_wb uncore interconnect Lost Arb for VN1 : WB on BL event=0x4c,umask=0x10 01 Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_misc.adbl_parallel_win_vn0 uncore interconnect Arb Miscellaneous : AD, BL Parallel Win VN0 event=0x4d,umask=0x10 01 Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel unc_m3upi_rxc_arb_misc.adbl_parallel_win_vn1 uncore interconnect Arb Miscellaneous : AD, BL Parallel Win VN1 event=0x4d,umask=0x20 01 Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel unc_m3upi_rxc_arb_misc.all_parallel_win uncore interconnect Arb Miscellaneous : Max Parallel Win event=0x4d,umask=0x80 01 Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners) unc_m3upi_rxc_arb_misc.no_prog_ad_vn0 uncore interconnect Arb Miscellaneous : No Progress on Pending AD VN0 event=0x4d,umask=1 01 Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_ad_vn1 uncore interconnect Arb Miscellaneous : No Progress on Pending AD VN1 event=0x4d,umask=2 01 Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn0 uncore interconnect Arb Miscellaneous : No Progress on Pending BL VN0 event=0x4d,umask=4 01 Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn1 uncore interconnect Arb Miscellaneous : No Progress on Pending BL VN1 event=0x4d,umask=8 01 Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.vn01_parallel_win uncore interconnect Arb Miscellaneous : VN0, VN1 Parallel Win event=0x4d,umask=0x40 01 Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side) unc_m3upi_rxc_arb_nocrd_vn0.ad_req uncore interconnect No Credits to Arb for VN0 : REQ on AD event=0x47,umask=1 01 No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocrd_vn0.ad_rsp uncore interconnect No Credits to Arb for VN0 : RSP on AD event=0x47,umask=4 01 No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn0.ad_snp uncore interconnect No Credits to Arb for VN0 : SNP on AD event=0x47,umask=2 01 No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocrd_vn0.bl_ncb uncore interconnect No Credits to Arb for VN0 : NCB on BL event=0x47,umask=0x20 01 No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_nocrd_vn0.bl_ncs uncore interconnect No Credits to Arb for VN0 : NCS on BL event=0x47,umask=0x40 01 No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocrd_vn0.bl_rsp uncore interconnect No Credits to Arb for VN0 : RSP on BL event=0x47,umask=8 01 No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn0.bl_wb uncore interconnect No Credits to Arb for VN0 : WB on BL event=0x47,umask=0x10 01 No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_nocrd_vn1.ad_req uncore interconnect No Credits to Arb for VN1 : REQ on AD event=0x48,umask=1 01 No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocrd_vn1.ad_rsp uncore interconnect No Credits to Arb for VN1 : RSP on AD event=0x48,umask=4 01 No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn1.ad_snp uncore interconnect No Credits to Arb for VN1 : SNP on AD event=0x48,umask=2 01 No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocrd_vn1.bl_ncb uncore interconnect No Credits to Arb for VN1 : NCB on BL event=0x48,umask=0x20 01 No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_nocrd_vn1.bl_ncs uncore interconnect No Credits to Arb for VN1 : NCS on BL event=0x48,umask=0x40 01 No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocrd_vn1.bl_rsp uncore interconnect No Credits to Arb for VN1 : RSP on BL event=0x48,umask=8 01 No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn1.bl_wb uncore interconnect No Credits to Arb for VN1 : WB on BL event=0x48,umask=0x10 01 No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_noreq_vn0.ad_req uncore interconnect Can't Arb for VN0 : REQ on AD event=0x49,umask=1 01 Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noreq_vn0.ad_rsp uncore interconnect Can't Arb for VN0 : RSP on AD event=0x49,umask=4 01 Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn0.ad_snp uncore interconnect Can't Arb for VN0 : SNP on AD event=0x49,umask=2 01 Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_noreq_vn0.bl_ncb uncore interconnect Can't Arb for VN0 : NCB on BL event=0x49,umask=0x20 01 Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_noreq_vn0.bl_ncs uncore interconnect Can't Arb for VN0 : NCS on BL event=0x49,umask=0x40 01 Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noreq_vn0.bl_rsp uncore interconnect Can't Arb for VN0 : RSP on BL event=0x49,umask=8 01 Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn0.bl_wb uncore interconnect Can't Arb for VN0 : WB on BL event=0x49,umask=0x10 01 Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_noreq_vn1.ad_req uncore interconnect Can't Arb for VN1 : REQ on AD event=0x4a,umask=1 01 Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noreq_vn1.ad_rsp uncore interconnect Can't Arb for VN1 : RSP on AD event=0x4a,umask=4 01 Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn1.ad_snp uncore interconnect Can't Arb for VN1 : SNP on AD event=0x4a,umask=2 01 Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_noreq_vn1.bl_ncb uncore interconnect Can't Arb for VN1 : NCB on BL event=0x4a,umask=0x20 01 Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_noreq_vn1.bl_ncs uncore interconnect Can't Arb for VN1 : NCS on BL event=0x4a,umask=0x40 01 Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noreq_vn1.bl_rsp uncore interconnect Can't Arb for VN1 : RSP on BL event=0x4a,umask=8 01 Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn1.bl_wb uncore interconnect Can't Arb for VN1 : WB on BL event=0x4a,umask=0x10 01 Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_bypassed.ad_s0_bl_arb uncore interconnect Ingress Queue Bypasses : AD to Slot 0 on BL Arb event=0x40,umask=2 01 Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration unc_m3upi_rxc_bypassed.ad_s0_idle uncore interconnect Ingress Queue Bypasses : AD to Slot 0 on Idle event=0x40,umask=1 01 Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle unc_m3upi_rxc_bypassed.ad_s1_bl_slot uncore interconnect Ingress Queue Bypasses : AD + BL to Slot 1 event=0x40,umask=4 01 Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit unc_m3upi_rxc_bypassed.ad_s2_bl_slot uncore interconnect Ingress Queue Bypasses : AD + BL to Slot 2 event=0x40,umask=8 01 Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit unc_m3upi_rxc_crd_misc.any_bgf_fifo uncore interconnect Miscellaneous Credit Events : Any In BGF FIFO event=0x5f,umask=1 01 Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only) unc_m3upi_rxc_crd_misc.any_bgf_path uncore interconnect Miscellaneous Credit Events : Any in BGF Path event=0x5f,umask=2 01 Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo) unc_m3upi_rxc_crd_misc.lt1_for_d2k uncore interconnect Miscellaneous Credit Events event=0x5f,umask=0x10 01 Miscellaneous Credit Events : d2k credit count is less than 1 unc_m3upi_rxc_crd_misc.lt2_for_d2k uncore interconnect Miscellaneous Credit Events event=0x5f,umask=0x20 01 Miscellaneous Credit Events : d2k credit count is less than 2 unc_m3upi_rxc_crd_misc.vn0_no_d2k_for_arb uncore interconnect Miscellaneous Credit Events : No D2K For Arb event=0x5f,umask=4 01 Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit unc_m3upi_rxc_crd_misc.vn1_no_d2k_for_arb uncore interconnect Miscellaneous Credit Events event=0x5f,umask=8 01 Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits unc_m3upi_rxc_crd_occ.consumed uncore interconnect Credit Occupancy : Credits Consumed event=0x60,umask=0x80 01 Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle unc_m3upi_rxc_crd_occ.d2k_crd uncore interconnect Credit Occupancy : D2K Credits event=0x60,umask=0x10 01 Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.flits_in_fifo uncore interconnect Credit Occupancy : Packets in BGF FIFO event=0x60,umask=2 01 Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo unc_m3upi_rxc_crd_occ.flits_in_path uncore interconnect Credit Occupancy : Packets in BGF Path event=0x60,umask=4 01 Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo) unc_m3upi_rxc_crd_occ.p1p_fifo uncore interconnect Credit Occupancy event=0x60,umask=0x40 01 Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only unc_m3upi_rxc_crd_occ.p1p_total uncore interconnect Credit Occupancy event=0x60,umask=0x20 01 Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo unc_m3upi_rxc_crd_occ.txq_crd uncore interconnect Credit Occupancy : Transmit Credits event=0x60,umask=8 01 Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.vna_in_use uncore interconnect Credit Occupancy : VNA In Use event=0x60,umask=1 01 Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles unc_m3upi_rxc_cycles_ne_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD event=0x43,umask=1 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD event=0x43,umask=4 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD event=0x43,umask=2 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL event=0x43,umask=0x20 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL event=0x43,umask=0x40 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL event=0x43,umask=8 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL event=0x43,umask=0x10 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_data_flits_not_sent.all uncore interconnect Data Flit Not Sent : All event=0x55,umask=1 01 Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection unc_m3upi_rxc_data_flits_not_sent.no_bgf uncore interconnect Data Flit Not Sent : No BGF Credits event=0x55,umask=8 01 Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent unc_m3upi_rxc_data_flits_not_sent.no_txq uncore interconnect Data Flit Not Sent : No TxQ Credits event=0x55,umask=0x10 01 Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent unc_m3upi_rxc_data_flits_not_sent.tsv_hi uncore interconnect Data Flit Not Sent : TSV High event=0x55,umask=2 01 Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high unc_m3upi_rxc_data_flits_not_sent.valid_for_flit uncore interconnect Data Flit Not Sent : Cycle valid for Flit event=0x55,umask=4 01 Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission unc_m3upi_rxc_flits_gen_bl.p0_wait uncore interconnect Generating BL Data Flit Sequence : Wait on Pump 0 event=0x57,umask=1 01 Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0 unc_m3upi_rxc_flits_gen_bl.p1p_at_limit uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x10 01 Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit) unc_m3upi_rxc_flits_gen_bl.p1p_busy uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=8 01 Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message unc_m3upi_rxc_flits_gen_bl.p1p_fifo_full uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x40 01 Generating BL Data Flit Sequence : pump-1-pending completion fifo is full unc_m3upi_rxc_flits_gen_bl.p1p_hold_p0 uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x20 01 Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage unc_m3upi_rxc_flits_gen_bl.p1p_to_limbo uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=4 01 Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic unc_m3upi_rxc_flits_gen_bl.p1_wait uncore interconnect Generating BL Data Flit Sequence : Wait on Pump 1 event=0x57,umask=2 01 Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1 unc_m3upi_rxc_flits_misc.s2req_in_holdoff uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF event=0x58,umask=4 01 : slot 2 request naturally serviced during hold-off period unc_m3upi_rxc_flits_misc.s2req_in_service uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE event=0x58,umask=8 01 : slot 2 request forcibly serviced during service window unc_m3upi_rxc_flits_misc.s2req_received uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED event=0x58,umask=1 01 : slot 2 request received from link layer while idle (with no slot 2 request active immediately prior) unc_m3upi_rxc_flits_misc.s2req_withdrawn uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN event=0x58,umask=2 01 : slot 2 request withdrawn during hold-off period or service window unc_m3upi_rxc_flits_slot_bl.all uncore interconnect Slotting BL Message Into Header Flit : All event=0x56,umask=1 01 unc_m3upi_rxc_flits_slot_bl.need_data uncore interconnect Slotting BL Message Into Header Flit : Needs Data Flit event=0x56,umask=2 01 Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence unc_m3upi_rxc_flits_slot_bl.p0_wait uncore interconnect Slotting BL Message Into Header Flit : Wait on Pump 0 event=0x56,umask=4 01 Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0 unc_m3upi_rxc_flits_slot_bl.p1_not_req uncore interconnect Slotting BL Message Into Header Flit : Don't Need Pump 1 event=0x56,umask=0x10 01 Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit unc_m3upi_rxc_flits_slot_bl.p1_not_req_but_bubble uncore interconnect Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble event=0x56,umask=0x20 01 Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed unc_m3upi_rxc_flits_slot_bl.p1_not_req_not_avail uncore interconnect Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail event=0x56,umask=0x40 01 Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available unc_m3upi_rxc_flits_slot_bl.p1_wait uncore interconnect Slotting BL Message Into Header Flit : Wait on Pump 1 event=0x56,umask=8 01 Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1 unc_m3upi_rxc_flit_gen_hdr1.accum uncore interconnect Flit Gen - Header 1 : Accumulate event=0x51,umask=1 01 Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles unc_m3upi_rxc_flit_gen_hdr1.accum_read uncore interconnect Flit Gen - Header 1 : Accumulate Ready event=0x51,umask=2 01 Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit unc_m3upi_rxc_flit_gen_hdr1.accum_wasted uncore interconnect Flit Gen - Header 1 : Accumulate Wasted event=0x51,umask=4 01 Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted unc_m3upi_rxc_flit_gen_hdr1.ahead_blocked uncore interconnect Flit Gen - Header 1 : Run-Ahead - Blocked event=0x51,umask=8 01 Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked unc_m3upi_rxc_flit_gen_hdr1.ahead_msg1_after uncore interconnect Flit Gen - Header 1 event=0x51,umask=0x80 01 Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted unc_m3upi_rxc_flit_gen_hdr1.ahead_msg1_during uncore interconnect Flit Gen - Header 1 : Run-Ahead - Message event=0x51,umask=0x10 01 Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead unc_m3upi_rxc_flit_gen_hdr1.ahead_msg2_after uncore interconnect Flit Gen - Header 1 event=0x51,umask=0x20 01 Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success unc_m3upi_rxc_flit_gen_hdr1.ahead_msg2_sent uncore interconnect Flit Gen - Header 1 event=0x51,umask=0x40 01 Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success unc_m3upi_rxc_flit_gen_hdr2.par uncore interconnect Flit Gen - Header 2 : Parallel Ok event=0x52,umask=4 01 Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.par_flit uncore interconnect Flit Gen - Header 2 : Parallel Flit Finished event=0x52,umask=0x10 01 Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.par_msg uncore interconnect Flit Gen - Header 2 : Parallel Message event=0x52,umask=8 01 Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.rmstall uncore interconnect Flit Gen - Header 2 : Rate-matching Stall event=0x52,umask=1 01 Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected unc_m3upi_rxc_flit_gen_hdr2.rmstall_nomsg uncore interconnect Flit Gen - Header 2 : Rate-matching Stall - No Message event=0x52,umask=2 01 Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle unc_m3upi_rxc_hdr_flits_sent.1_msg uncore interconnect Sent Header Flit : One Message event=0x54,umask=1 01 Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit unc_m3upi_rxc_hdr_flits_sent.1_msg_vnx uncore interconnect Sent Header Flit : One Message in non-VNA event=0x54,umask=8 01 Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit unc_m3upi_rxc_hdr_flits_sent.2_msgs uncore interconnect Sent Header Flit : Two Messages event=0x54,umask=2 01 Sent Header Flit : Two Messages : Two messages in flit; VNA flit unc_m3upi_rxc_hdr_flits_sent.3_msgs uncore interconnect Sent Header Flit : Three Messages event=0x54,umask=4 01 Sent Header Flit : Three Messages : Three messages in flit; VNA flit unc_m3upi_rxc_hdr_flits_sent.slots_1 uncore interconnect Sent Header Flit : One Slot Taken event=0x54,umask=0x10 01 unc_m3upi_rxc_hdr_flits_sent.slots_2 uncore interconnect Sent Header Flit : Two Slots Taken event=0x54,umask=0x20 01 unc_m3upi_rxc_hdr_flits_sent.slots_3 uncore interconnect Sent Header Flit : All Slots Taken event=0x54,umask=0x40 01 unc_m3upi_rxc_hdr_flit_not_sent.all uncore interconnect Header Not Sent : All event=0x53,umask=1 01 Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection unc_m3upi_rxc_hdr_flit_not_sent.no_bgf_crd uncore interconnect Header Not Sent : No BGF Credits event=0x53,umask=8 01 Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available unc_m3upi_rxc_hdr_flit_not_sent.no_bgf_no_msg uncore interconnect Header Not Sent : No BGF Credits + No Extra Message Slotted event=0x53,umask=0x20 01 Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit unc_m3upi_rxc_hdr_flit_not_sent.no_txq_crd uncore interconnect Header Not Sent : No TxQ Credits event=0x53,umask=0x10 01 Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available unc_m3upi_rxc_hdr_flit_not_sent.no_txq_no_msg uncore interconnect Header Not Sent : No TxQ Credits + No Extra Message Slotted event=0x53,umask=0x40 01 Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit unc_m3upi_rxc_hdr_flit_not_sent.tsv_hi uncore interconnect Header Not Sent : TSV High event=0x53,umask=2 01 Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high unc_m3upi_rxc_hdr_flit_not_sent.valid_for_flit uncore interconnect Header Not Sent : Cycle valid for Flit event=0x53,umask=4 01 Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission unc_m3upi_rxc_held.cant_slot_ad uncore interconnect Message Held : Can't Slot AD event=0x50,umask=0x10 01 Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.cant_slot_bl uncore interconnect Message Held : Can't Slot BL event=0x50,umask=0x20 01 Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_attempt uncore interconnect Message Held : Parallel Attempt event=0x50,umask=4 01 Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel unc_m3upi_rxc_held.parallel_success uncore interconnect Message Held : Parallel Success event=0x50,umask=8 01 Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in parallel unc_m3upi_rxc_held.vn0 uncore interconnect Message Held : VN0 event=0x50,umask=1 01 Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit unc_m3upi_rxc_held.vn1 uncore interconnect Message Held : VN1 event=0x50,umask=2 01 Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit unc_m3upi_rxc_packing_miss_vn0.ad_req uncore interconnect VN0 message can't slot into flit : REQ on AD event=0x4e,umask=1 01 VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn0.ad_rsp uncore interconnect VN0 message can't slot into flit : RSP on AD event=0x4e,umask=4 01 VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.ad_snp uncore interconnect VN0 message can't slot into flit : SNP on AD event=0x4e,umask=2 01 VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn0.bl_ncb uncore interconnect VN0 message can't slot into flit : NCB on BL event=0x4e,umask=0x20 01 VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn0.bl_ncs uncore interconnect VN0 message can't slot into flit : NCS on BL event=0x4e,umask=0x40 01 VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn0.bl_rsp uncore interconnect VN0 message can't slot into flit : RSP on BL event=0x4e,umask=8 01 VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.bl_wb uncore interconnect VN0 message can't slot into flit : WB on BL event=0x4e,umask=0x10 01 VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_packing_miss_vn1.ad_req uncore interconnect VN1 message can't slot into flit : REQ on AD event=0x4f,umask=1 01 VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn1.ad_rsp uncore interconnect VN1 message can't slot into flit : RSP on AD event=0x4f,umask=4 01 VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.ad_snp uncore interconnect VN1 message can't slot into flit : SNP on AD event=0x4f,umask=2 01 VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn1.bl_ncb uncore interconnect VN1 message can't slot into flit : NCB on BL event=0x4f,umask=0x20 01 VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn1.bl_ncs uncore interconnect VN1 message can't slot into flit : NCS on BL event=0x4f,umask=0x40 01 VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn1.bl_rsp uncore interconnect VN1 message can't slot into flit : RSP on BL event=0x4f,umask=8 01 VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.bl_wb uncore interconnect VN1 message can't slot into flit : WB on BL event=0x4f,umask=0x10 01 VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_vna_crd.any_in_use uncore interconnect Remote VNA Credits : Any In Use event=0x5a,umask=0x20 01 Remote VNA Credits : Any In Use : At least one remote vna credit is in use unc_m3upi_rxc_vna_crd.corrected uncore interconnect Remote VNA Credits : Corrected event=0x5a,umask=1 01 Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle unc_m3upi_rxc_vna_crd.lt1 uncore interconnect Remote VNA Credits : Level < 1 event=0x5a,umask=2 01 Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available) unc_m3upi_rxc_vna_crd.lt10 uncore interconnect Remote VNA Credits : Level < 10 event=0x5a,umask=0x10 01 Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible unc_m3upi_rxc_vna_crd.lt4 uncore interconnect Remote VNA Credits : Level < 4 event=0x5a,umask=4 01 Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna unc_m3upi_rxc_vna_crd.lt5 uncore interconnect Remote VNA Credits : Level < 5 event=0x5a,umask=8 01 Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible unc_m3upi_rxc_vna_crd_misc.req_adbl_alloc_l5 uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5 event=0x59,umask=2 01 : remote vna credit count was less than 5 and allocation to ad or bl messages was required unc_m3upi_rxc_vna_crd_misc.req_vn01_alloc_lt10 uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10 event=0x59,umask=1 01 : remote vna credit count was less than 10 and allocation to vn0 or vn1 was required unc_m3upi_rxc_vna_crd_misc.vn0_just_ad uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD event=0x59,umask=0x10 01 : on vn0, remote vna credits were allocated only to ad messages, not to bl unc_m3upi_rxc_vna_crd_misc.vn0_just_bl uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL event=0x59,umask=0x20 01 : on vn0, remote vna credits were allocated only to bl messages, not to ad unc_m3upi_rxc_vna_crd_misc.vn0_only uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY event=0x59,umask=4 01 : remote vna credits were allocated only to vn0, not to vn1 unc_m3upi_rxc_vna_crd_misc.vn1_just_ad uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD event=0x59,umask=0x40 01 : on vn1, remote vna credits were allocated only to ad messages, not to bl unc_m3upi_rxc_vna_crd_misc.vn1_just_bl uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL event=0x59,umask=0x80 01 : on vn1, remote vna credits were allocated only to bl messages, not to ad unc_m3upi_rxc_vna_crd_misc.vn1_only uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY event=0x59,umask=8 01 : remote vna credits were allocated only to vn1, not to vn0 unc_m3upi_txc_ad_arb_fail.vn0_req uncore interconnect Failed ARB for AD : VN0 REQ Messages event=0x30,umask=1 01 Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_rsp uncore interconnect Failed ARB for AD : VN0 RSP Messages event=0x30,umask=4 01 Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_snp uncore interconnect Failed ARB for AD : VN0 SNP Messages event=0x30,umask=2 01 Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_wb uncore interconnect Failed ARB for AD : VN0 WB Messages event=0x30,umask=8 01 Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_req uncore interconnect Failed ARB for AD : VN1 REQ Messages event=0x30,umask=0x10 01 Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_rsp uncore interconnect Failed ARB for AD : VN1 RSP Messages event=0x30,umask=0x40 01 Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_snp uncore interconnect Failed ARB for AD : VN1 SNP Messages event=0x30,umask=0x20 01 Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_wb uncore interconnect Failed ARB for AD : VN1 WB Messages event=0x30,umask=0x80 01 Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_flq_bypass uncore interconnect AD FlowQ Bypass event=0x2c 01 Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot0 uncore interconnect AD FlowQ Bypass event=0x2c,umask=1 01 AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot1 uncore interconnect AD FlowQ Bypass event=0x2c,umask=2 01 AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot2 uncore interconnect AD FlowQ Bypass event=0x2c,umask=4 01 AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.bl_early_rsp uncore interconnect AD FlowQ Bypass event=0x2c,umask=8 01 AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_cycles_ne.vn0_req uncore interconnect AD Flow Q Not Empty : VN0 REQ Messages event=0x27,umask=1 01 AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_rsp uncore interconnect AD Flow Q Not Empty : VN0 RSP Messages event=0x27,umask=4 01 AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_snp uncore interconnect AD Flow Q Not Empty : VN0 SNP Messages event=0x27,umask=2 01 AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_wb uncore interconnect AD Flow Q Not Empty : VN0 WB Messages event=0x27,umask=8 01 AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_req uncore interconnect AD Flow Q Not Empty : VN1 REQ Messages event=0x27,umask=0x10 01 AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_rsp uncore interconnect AD Flow Q Not Empty : VN1 RSP Messages event=0x27,umask=0x40 01 AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_snp uncore interconnect AD Flow Q Not Empty : VN1 SNP Messages event=0x27,umask=0x20 01 AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_wb uncore interconnect AD Flow Q Not Empty : VN1 WB Messages event=0x27,umask=0x80 01 AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_inserts.vn0_req uncore interconnect AD Flow Q Inserts : VN0 REQ Messages event=0x2d,umask=1 01 AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_rsp uncore interconnect AD Flow Q Inserts : VN0 RSP Messages event=0x2d,umask=4 01 AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_snp uncore interconnect AD Flow Q Inserts : VN0 SNP Messages event=0x2d,umask=2 01 AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_wb uncore interconnect AD Flow Q Inserts : VN0 WB Messages event=0x2d,umask=8 01 AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_req uncore interconnect AD Flow Q Inserts : VN1 REQ Messages event=0x2d,umask=0x10 01 AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_rsp uncore interconnect AD Flow Q Inserts : VN1 RSP Messages event=0x2d,umask=0x40 01 AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_snp uncore interconnect AD Flow Q Inserts : VN1 SNP Messages event=0x2d,umask=0x20 01 AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_occupancy.vn0_req uncore interconnect AD Flow Q Occupancy : VN0 REQ Messages event=0x1c,umask=1 01 unc_m3upi_txc_ad_flq_occupancy.vn0_rsp uncore interconnect AD Flow Q Occupancy : VN0 RSP Messages event=0x1c,umask=4 01 unc_m3upi_txc_ad_flq_occupancy.vn0_snp uncore interconnect AD Flow Q Occupancy : VN0 SNP Messages event=0x1c,umask=2 01 unc_m3upi_txc_ad_flq_occupancy.vn0_wb uncore interconnect AD Flow Q Occupancy : VN0 WB Messages event=0x1c,umask=8 01 unc_m3upi_txc_ad_flq_occupancy.vn1_req uncore interconnect AD Flow Q Occupancy : VN1 REQ Messages event=0x1c,umask=0x10 01 unc_m3upi_txc_ad_flq_occupancy.vn1_rsp uncore interconnect AD Flow Q Occupancy : VN1 RSP Messages event=0x1c,umask=0x40 01 unc_m3upi_txc_ad_flq_occupancy.vn1_snp uncore interconnect AD Flow Q Occupancy : VN1 SNP Messages event=0x1c,umask=0x20 01 unc_m3upi_txc_bl_arb_fail.vn0_ncb uncore interconnect Failed ARB for BL : VN0 NCB Messages event=0x35,umask=4 01 Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_ncs uncore interconnect Failed ARB for BL : VN0 NCS Messages event=0x35,umask=8 01 Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_rsp uncore interconnect Failed ARB for BL : VN0 RSP Messages event=0x35,umask=1 01 Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_wb uncore interconnect Failed ARB for BL : VN0 WB Messages event=0x35,umask=2 01 Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncb uncore interconnect Failed ARB for BL : VN1 NCS Messages event=0x35,umask=0x40 01 Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncs uncore interconnect Failed ARB for BL : VN1 NCB Messages event=0x35,umask=0x80 01 Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_rsp uncore interconnect Failed ARB for BL : VN1 RSP Messages event=0x35,umask=0x10 01 Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_wb uncore interconnect Failed ARB for BL : VN1 WB Messages event=0x35,umask=0x20 01 Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_flq_cycles_ne.vn0_req uncore interconnect BL Flow Q Not Empty : VN0 REQ Messages event=0x28,umask=1 01 BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_rsp uncore interconnect BL Flow Q Not Empty : VN0 RSP Messages event=0x28,umask=4 01 BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_snp uncore interconnect BL Flow Q Not Empty : VN0 SNP Messages event=0x28,umask=2 01 BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_wb uncore interconnect BL Flow Q Not Empty : VN0 WB Messages event=0x28,umask=8 01 BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_req uncore interconnect BL Flow Q Not Empty : VN1 REQ Messages event=0x28,umask=0x10 01 BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_rsp uncore interconnect BL Flow Q Not Empty : VN1 RSP Messages event=0x28,umask=0x40 01 BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_snp uncore interconnect BL Flow Q Not Empty : VN1 SNP Messages event=0x28,umask=0x20 01 BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_wb uncore interconnect BL Flow Q Not Empty : VN1 WB Messages event=0x28,umask=0x80 01 BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_inserts.vn0_ncb uncore interconnect BL Flow Q Inserts : VN0 RSP Messages event=0x2e,umask=1 01 BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_ncs uncore interconnect BL Flow Q Inserts : VN0 WB Messages event=0x2e,umask=2 01 BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_rsp uncore interconnect BL Flow Q Inserts : VN0 NCS Messages event=0x2e,umask=8 01 BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_wb uncore interconnect BL Flow Q Inserts : VN0 NCB Messages event=0x2e,umask=4 01 BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncb uncore interconnect BL Flow Q Inserts : VN1 RSP Messages event=0x2e,umask=0x10 01 BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncs uncore interconnect BL Flow Q Inserts : VN1 WB Messages event=0x2e,umask=0x20 01 BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_rsp uncore interconnect BL Flow Q Inserts : VN1_NCB Messages event=0x2e,umask=0x80 01 BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_wb uncore interconnect BL Flow Q Inserts : VN1_NCS Messages event=0x2e,umask=0x40 01 BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_occupancy.vn0_ncb uncore interconnect BL Flow Q Occupancy : VN0 NCB Messages event=0x1d,umask=4 01 unc_m3upi_txc_bl_flq_occupancy.vn0_ncs uncore interconnect BL Flow Q Occupancy : VN0 NCS Messages event=0x1d,umask=8 01 unc_m3upi_txc_bl_flq_occupancy.vn0_rsp uncore interconnect BL Flow Q Occupancy : VN0 RSP Messages event=0x1d,umask=1 01 unc_m3upi_txc_bl_flq_occupancy.vn0_wb uncore interconnect BL Flow Q Occupancy : VN0 WB Messages event=0x1d,umask=2 01 unc_m3upi_txc_bl_flq_occupancy.vn1_ncb uncore interconnect BL Flow Q Occupancy : VN1_NCS Messages event=0x1d,umask=0x40 01 unc_m3upi_txc_bl_flq_occupancy.vn1_ncs uncore interconnect BL Flow Q Occupancy : VN1_NCB Messages event=0x1d,umask=0x80 01 unc_m3upi_txc_bl_flq_occupancy.vn1_rsp uncore interconnect BL Flow Q Occupancy : VN1 RSP Messages event=0x1d,umask=0x10 01 unc_m3upi_txc_bl_flq_occupancy.vn1_wb uncore interconnect BL Flow Q Occupancy : VN1 WB Messages event=0x1d,umask=0x20 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn0_local uncore interconnect BL Flow Q Occupancy : VN0 RSP Messages event=0x1f,umask=1 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn0_through uncore interconnect BL Flow Q Occupancy : VN0 WB Messages event=0x1f,umask=2 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn0_wrpull uncore interconnect BL Flow Q Occupancy : VN0 NCB Messages event=0x1f,umask=4 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn1_local uncore interconnect BL Flow Q Occupancy : VN1 RSP Messages event=0x1f,umask=0x10 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn1_through uncore interconnect BL Flow Q Occupancy : VN1 WB Messages event=0x1f,umask=0x20 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn1_wrpull uncore interconnect BL Flow Q Occupancy : VN1_NCS Messages event=0x1f,umask=0x40 01 unc_m3upi_upi_peer_ad_credits_empty.vn0_req uncore interconnect UPI0 AD Credits Empty : VN0 REQ Messages event=0x20,umask=2 01 UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_rsp uncore interconnect UPI0 AD Credits Empty : VN0 RSP Messages event=0x20,umask=8 01 UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_snp uncore interconnect UPI0 AD Credits Empty : VN0 SNP Messages event=0x20,umask=4 01 UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_req uncore interconnect UPI0 AD Credits Empty : VN1 REQ Messages event=0x20,umask=0x10 01 UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_rsp uncore interconnect UPI0 AD Credits Empty : VN1 RSP Messages event=0x20,umask=0x40 01 UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_snp uncore interconnect UPI0 AD Credits Empty : VN1 SNP Messages event=0x20,umask=0x20 01 UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vna uncore interconnect UPI0 AD Credits Empty : VNA event=0x20,umask=1 01 UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_bl_credits_empty.vn0_ncs_ncb uncore interconnect UPI0 BL Credits Empty : VN0 RSP Messages event=0x21,umask=4 01 UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_rsp uncore interconnect UPI0 BL Credits Empty : VN0 REQ Messages event=0x21,umask=2 01 UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_wb uncore interconnect UPI0 BL Credits Empty : VN0 SNP Messages event=0x21,umask=8 01 UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_ncs_ncb uncore interconnect UPI0 BL Credits Empty : VN1 RSP Messages event=0x21,umask=0x20 01 UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_rsp uncore interconnect UPI0 BL Credits Empty : VN1 REQ Messages event=0x21,umask=0x10 01 UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_wb uncore interconnect UPI0 BL Credits Empty : VN1 SNP Messages event=0x21,umask=0x40 01 UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vna uncore interconnect UPI0 BL Credits Empty : VNA event=0x21,umask=1 01 UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_prefetch_spawn uncore interconnect FlowQ Generated Prefetch event=0x29 01 FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target unc_m3upi_vn0_credits_used.ncb uncore interconnect VN0 Credit Used : WB on BL event=0x5b,umask=0x10 01 VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_credits_used.ncs uncore interconnect VN0 Credit Used : NCB on BL event=0x5b,umask=0x20 01 VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn0_credits_used.req uncore interconnect VN0 Credit Used : REQ on AD event=0x5b,umask=1 01 VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_credits_used.rsp uncore interconnect VN0 Credit Used : RSP on AD event=0x5b,umask=4 01 VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_credits_used.snp uncore interconnect VN0 Credit Used : SNP on AD event=0x5b,umask=2 01 VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn0_credits_used.wb uncore interconnect VN0 Credit Used : RSP on BL event=0x5b,umask=8 01 VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.ncb uncore interconnect VN0 No Credits : WB on BL event=0x5d,umask=0x10 01 VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_no_credits.ncs uncore interconnect VN0 No Credits : NCB on BL event=0x5d,umask=0x20 01 VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn0_no_credits.req uncore interconnect VN0 No Credits : REQ on AD event=0x5d,umask=1 01 VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_no_credits.rsp uncore interconnect VN0 No Credits : RSP on AD event=0x5d,umask=4 01 VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.snp uncore interconnect VN0 No Credits : SNP on AD event=0x5d,umask=2 01 VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn0_no_credits.wb uncore interconnect VN0 No Credits : RSP on BL event=0x5d,umask=8 01 VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.ncb uncore interconnect VN1 Credit Used : WB on BL event=0x5c,umask=0x10 01 VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_credits_used.ncs uncore interconnect VN1 Credit Used : NCB on BL event=0x5c,umask=0x20 01 VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn1_credits_used.req uncore interconnect VN1 Credit Used : REQ on AD event=0x5c,umask=1 01 VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_credits_used.rsp uncore interconnect VN1 Credit Used : RSP on AD event=0x5c,umask=4 01 VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.snp uncore interconnect VN1 Credit Used : SNP on AD event=0x5c,umask=2 01 VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn1_credits_used.wb uncore interconnect VN1 Credit Used : RSP on BL event=0x5c,umask=8 01 VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.ncb uncore interconnect VN1 No Credits : WB on BL event=0x5e,umask=0x10 01 VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_no_credits.ncs uncore interconnect VN1 No Credits : NCB on BL event=0x5e,umask=0x20 01 VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn1_no_credits.req uncore interconnect VN1 No Credits : REQ on AD event=0x5e,umask=1 01 VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_no_credits.rsp uncore interconnect VN1 No Credits : RSP on AD event=0x5e,umask=4 01 VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.snp uncore interconnect VN1 No Credits : SNP on AD event=0x5e,umask=2 01 VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn1_no_credits.wb uncore interconnect VN1 No Credits : RSP on BL event=0x5e,umask=8 01 VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_wb_occ_compare.bothnonzero_rt_eq_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0 event=0x7e,umask=0x82 01 unc_m3upi_wb_occ_compare.bothnonzero_rt_eq_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1 event=0x7e,umask=0xa0 01 unc_m3upi_wb_occ_compare.bothnonzero_rt_gt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0 event=0x7e,umask=0x81 01 unc_m3upi_wb_occ_compare.bothnonzero_rt_gt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1 event=0x7e,umask=0x90 01 unc_m3upi_wb_occ_compare.bothnonzero_rt_lt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0 event=0x7e,umask=0x84 01 unc_m3upi_wb_occ_compare.bothnonzero_rt_lt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1 event=0x7e,umask=0xc0 01 unc_m3upi_wb_occ_compare.rt_eq_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0 event=0x7e,umask=2 01 unc_m3upi_wb_occ_compare.rt_eq_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1 event=0x7e,umask=0x20 01 unc_m3upi_wb_occ_compare.rt_gt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0 event=0x7e,umask=1 01 unc_m3upi_wb_occ_compare.rt_gt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1 event=0x7e,umask=0x10 01 unc_m3upi_wb_occ_compare.rt_lt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0 event=0x7e,umask=4 01 unc_m3upi_wb_occ_compare.rt_lt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1 event=0x7e,umask=0x40 01 unc_m3upi_wb_pending.localdest_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.LOCALDEST_VN0 event=0x7d,umask=1 01 unc_m3upi_wb_pending.localdest_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.LOCALDEST_VN1 event=0x7d,umask=0x10 01 unc_m3upi_wb_pending.local_and_rt_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0 event=0x7d,umask=4 01 unc_m3upi_wb_pending.local_and_rt_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1 event=0x7d,umask=0x40 01 unc_m3upi_wb_pending.routethru_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0 event=0x7d,umask=2 01 unc_m3upi_wb_pending.routethru_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1 event=0x7d,umask=0x20 01 unc_m3upi_wb_pending.waiting4pull_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0 event=0x7d,umask=8 01 unc_m3upi_wb_pending.waiting4pull_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1 event=0x7d,umask=0x80 01 unc_m3upi_xpt_pftch.arb uncore interconnect UNC_M3UPI_XPT_PFTCH.ARB event=0x61,umask=4 01 : xpt prefetch message is making arbitration request unc_m3upi_xpt_pftch.arrived uncore interconnect UNC_M3UPI_XPT_PFTCH.ARRIVED event=0x61,umask=1 01 : xpt prefetch message arrived in ingress pipeline unc_m3upi_xpt_pftch.bypass uncore interconnect UNC_M3UPI_XPT_PFTCH.BYPASS event=0x61,umask=2 01 : xpt prefetch message took bypass path unc_m3upi_xpt_pftch.flitted uncore interconnect UNC_M3UPI_XPT_PFTCH.FLITTED event=0x61,umask=0x10 01 : xpt prefetch message was slotted into flit (non bypass) unc_m3upi_xpt_pftch.lost_arb uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_ARB event=0x61,umask=8 01 : xpt prefetch message lost arbitration unc_m3upi_xpt_pftch.lost_old uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_OLD event=0x61,umask=0x20 01 : xpt prefetch message was dropped because it became too old unc_m3upi_xpt_pftch.lost_qfull uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_QFULL event=0x61,umask=0x40 01 : xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full uncore_mdf unc_mdf_crs_txr_inserts.ad_bnc uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD Bounceable) event=0x47,umask=1 01 AD Bounceable : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.ad_crd uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD credited) event=0x47,umask=2 01 AD credited : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.ak uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AK) event=0x47,umask=0x10 01 AK : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.akc uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AKC) event=0x47,umask=0x40 01 AKC : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.bl_bnc uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL Bounceable) event=0x47,umask=4 01 BL Bounceable : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.bl_crd uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL credited) event=0x47,umask=8 01 BL credited : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.iv uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (IV) event=0x47,umask=0x20 01 IV : Number of allocations into the CRS Egress unc_mdf_crs_txr_v_bounces.ad uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AD) event=0x4b,umask=1 01 AD : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.ak uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AK) event=0x4b,umask=4 01 AK : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.akc uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AKC) event=0x4b,umask=0x10 01 AKC : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.bl uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (BL) event=0x4b,umask=2 01 BL : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.iv uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (IV) event=0x4b,umask=8 01 IV : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_fast_asserted.ad_bnc uncore interconnect Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold event=0x15,umask=1 01 AD bnc : Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold unc_mdf_fast_asserted.bl_crd uncore interconnect Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold event=0x15,umask=2 01 BL bnc : Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold unc_upi_clockticks uncore interconnect UPI Clockticks event=1 01 Number of UPI LL clock cycles while the event is enabled unc_upi_direct_attempts.d2c uncore interconnect Direct packet attempts : D2C event=0x12,umask=1 01 Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_upi_direct_attempts.d2k uncore interconnect Direct packet attempts : D2K event=0x12,umask=2 01 Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_upi_l1_power_cycles uncore interconnect Cycles in L1 event=0x21 01 Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode unc_upi_power_l1_nack uncore interconnect L1 Req Nack event=0x23 01 L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_power_l1_req uncore interconnect L1 Req (same as L1 Ack) event=0x22 01 L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_rxl0p_power_cycles uncore interconnect Cycles in L0p event=0x25 01 Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_upi_rxl0_power_cycles uncore interconnect Cycles in L0 event=0x24 01 Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_upi_rxl_any_flits.data uncore interconnect UNC_UPI_RxL_ANY_FLITS.DATA event=0x4b,umask=8 01 unc_upi_rxl_any_flits.llcrd uncore interconnect UNC_UPI_RxL_ANY_FLITS.LLCRD event=0x4b,umask=0x10 01 unc_upi_rxl_any_flits.llctrl uncore interconnect UNC_UPI_RxL_ANY_FLITS.LLCTRL event=0x4b,umask=0x40 01 unc_upi_rxl_any_flits.null uncore interconnect UNC_UPI_RxL_ANY_FLITS.NULL event=0x4b,umask=0x20 01 unc_upi_rxl_any_flits.prothdr uncore interconnect UNC_UPI_RxL_ANY_FLITS.PROTHDR event=0x4b,umask=0x80 01 unc_upi_rxl_any_flits.slot0 uncore interconnect UNC_UPI_RxL_ANY_FLITS.SLOT0 event=0x4b,umask=1 01 unc_upi_rxl_any_flits.slot1 uncore interconnect UNC_UPI_RxL_ANY_FLITS.SLOT1 event=0x4b,umask=2 01 unc_upi_rxl_any_flits.slot2 uncore interconnect UNC_UPI_RxL_ANY_FLITS.SLOT2 event=0x4b,umask=4 01 unc_upi_rxl_basic_hdr_match.ncb uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Bypass event=5,umask=0xe 01 Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.ncb_opc uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode event=5,umask=0x10e 01 Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.ncs uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Standard event=5,umask=0xf 01 Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.ncs_opc uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode event=5,umask=0x10f 01 Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_bypassed.slot0 uncore interconnect RxQ Flit Buffer Bypassed : Slot 0 event=0x31,umask=1 01 RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot1 uncore interconnect RxQ Flit Buffer Bypassed : Slot 1 event=0x31,umask=2 01 RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot2 uncore interconnect RxQ Flit Buffer Bypassed : Slot 2 event=0x31,umask=4 01 RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_crc_errors uncore interconnect CRC Errors Detected event=0xb 01 CRC Errors Detected : Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_upi_rxl_crc_llr_req_transmit uncore interconnect LLR Requests Sent event=8 01 LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs. unc_upi_rxl_credits_consumed_vn0 uncore interconnect VN0 Credit Consumed event=0x39 01 VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_credits_consumed_vn1 uncore interconnect VN1 Credit Consumed event=0x3a 01 VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_flits.all_data uncore interconnect Valid Flits Received : All Data event=3,umask=0xf 01 Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.all_null uncore interconnect Null FLITs received from any slot event=3,umask=0x27 01 unc_upi_rxl_flits.data uncore interconnect Valid Flits Received : Data event=3,umask=8 01 Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received : Idle event=3,umask=0x47 01 Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.llcrd uncore interconnect Valid Flits Received : LLCRD Not Empty event=3,umask=0x10 01 Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_rxl_flits.llctrl uncore interconnect Valid Flits Received : LLCTRL event=3,umask=0x40 01 Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages unc_upi_rxl_flits.non_data uncore interconnect Valid Flits Received : All Non Data event=3,umask=0x97 01 Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.null uncore interconnect Valid Flits Received : Slot NULL or LLCRD Empty event=3,umask=0x20 01 Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2 unc_upi_rxl_flits.prothdr uncore interconnect Valid Flits Received : Protocol Header event=3,umask=0x80 01 Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_rxl_flits.slot0 uncore interconnect Valid Flits Received : Slot 0 event=3,umask=1 01 Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot1 uncore interconnect Valid Flits Received : Slot 1 event=3,umask=2 01 Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot2 uncore interconnect Valid Flits Received : Slot 2 event=3,umask=4 01 Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count unc_upi_rxl_inserts.slot0 uncore interconnect RxQ Flit Buffer Allocations : Slot 0 event=0x30,umask=1 01 RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot1 uncore interconnect RxQ Flit Buffer Allocations : Slot 1 event=0x30,umask=2 01 RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot2 uncore interconnect RxQ Flit Buffer Allocations : Slot 2 event=0x30,umask=4 01 RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_occupancy.slot0 uncore interconnect RxQ Occupancy - All Packets : Slot 0 event=0x32,umask=1 01 RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot1 uncore interconnect RxQ Occupancy - All Packets : Slot 1 event=0x32,umask=2 01 RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot2 uncore interconnect RxQ Occupancy - All Packets : Slot 2 event=0x32,umask=4 01 RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_txl0p_power_cycles uncore interconnect Cycles in L0p event=0x27 01 Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_upi_txl0_power_cycles uncore interconnect Cycles in L0 event=0x26 01 Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_upi_txl_any_flits.data uncore interconnect UNC_UPI_TxL_ANY_FLITS.DATA event=0x4a,umask=8 01 unc_upi_txl_any_flits.llcrd uncore interconnect UNC_UPI_TxL_ANY_FLITS.LLCRD event=0x4a,umask=0x10 01 unc_upi_txl_any_flits.llctrl uncore interconnect UNC_UPI_TxL_ANY_FLITS.LLCTRL event=0x4a,umask=0x40 01 unc_upi_txl_any_flits.null uncore interconnect UNC_UPI_TxL_ANY_FLITS.NULL event=0x4a,umask=0x20 01 unc_upi_txl_any_flits.prothdr uncore interconnect UNC_UPI_TxL_ANY_FLITS.PROTHDR event=0x4a,umask=0x80 01 unc_upi_txl_any_flits.slot0 uncore interconnect UNC_UPI_TxL_ANY_FLITS.SLOT0 event=0x4a,umask=1 01 unc_upi_txl_any_flits.slot1 uncore interconnect UNC_UPI_TxL_ANY_FLITS.SLOT1 event=0x4a,umask=2 01 unc_upi_txl_any_flits.slot2 uncore interconnect UNC_UPI_TxL_ANY_FLITS.SLOT2 event=0x4a,umask=4 01 unc_upi_txl_basic_hdr_match.ncb uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Bypass event=4,umask=0xe 01 Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.ncb_opc uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode event=4,umask=0x10e 01 Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.ncs uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Standard event=4,umask=0xf 01 Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.ncs_opc uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode event=4,umask=0x10f 01 Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_bypassed uncore interconnect Tx Flit Buffer Bypassed event=0x41 01 Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link unc_upi_txl_flits.all_data uncore interconnect Valid Flits Sent : All Data event=2,umask=0xf 01 Valid Flits Sent : All Data : Counts number of data flits across this UPI link unc_upi_txl_flits.all_llcrd uncore interconnect Valid Flits Sent : All LLCRD Not Empty event=2,umask=0x17 01 Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.all_llctrl uncore interconnect Valid Flits Sent : All LLCTRL event=2,umask=0x47 01 Valid Flits Sent : All LLCTRL : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.all_null uncore interconnect All Null Flits event=2,umask=0x27 01 unc_upi_txl_flits.all_prothdr uncore interconnect Valid Flits Sent : All Protocol Header event=2,umask=0x87 01 Valid Flits Sent : All ProtDDR : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.data uncore interconnect Valid Flits Sent : Data event=2,umask=8 01 Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_txl_flits.idle uncore interconnect Valid Flits Sent : Idle event=2,umask=0x47 01 Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.llcrd uncore interconnect Valid Flits Sent : LLCRD Not Empty event=2,umask=0x10 01 Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_txl_flits.llctrl uncore interconnect Valid Flits Sent : LLCTRL event=2,umask=0x40 01 Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages unc_upi_txl_flits.non_data uncore interconnect Valid Flits Sent : All Non Data event=2,umask=0x97 01 Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.null uncore interconnect Valid Flits Sent : Slot NULL or LLCRD Empty event=2,umask=0x20 01 Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2 unc_upi_txl_flits.prothdr uncore interconnect Valid Flits Sent : Protocol Header event=2,umask=0x80 01 Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_txl_flits.slot0 uncore interconnect Valid Flits Sent : Slot 0 event=2,umask=1 01 Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot1 uncore interconnect Valid Flits Sent : Slot 1 event=2,umask=2 01 Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot2 uncore interconnect Valid Flits Sent : Slot 2 event=2,umask=4 01 Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count unc_upi_txl_inserts uncore interconnect Tx Flit Buffer Allocations event=0x40 01 Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_txl_occupancy uncore interconnect Tx Flit Buffer Occupancy event=0x42 01 Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ unc_upi_vna_credit_return_occupancy uncore interconnect VNA Credits Pending Return - Occupancy event=0x44 01 VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link unc_u_event_msg.doorbell_rcvd uncore interconnect Message Received : Doorbell event=0x42,umask=8 01 unc_u_event_msg.int_prio uncore interconnect Message Received : Interrupt event=0x42,umask=0x10 01 Message Received : Interrupt : Interrupts unc_u_event_msg.ipi_rcvd uncore interconnect Message Received : IPI event=0x42,umask=4 01 Message Received : IPI : Inter Processor Interrupts unc_u_event_msg.msi_rcvd uncore interconnect Message Received : MSI event=0x42,umask=2 01 Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only) unc_u_event_msg.vlw_rcvd uncore interconnect Message Received : VLW event=0x42,umask=1 01 Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore unc_u_m2u_misc1.rxc_cycles_ne_cbo_ncb uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB event=0x4d,umask=1 01 unc_u_m2u_misc1.rxc_cycles_ne_cbo_ncs uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS event=0x4d,umask=2 01 unc_u_m2u_misc1.rxc_cycles_ne_upi_ncb uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB event=0x4d,umask=4 01 unc_u_m2u_misc1.rxc_cycles_ne_upi_ncs uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS event=0x4d,umask=8 01 unc_u_m2u_misc1.txc_cycles_crd_ovf_cbo_ncb uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB event=0x4d,umask=0x10 01 unc_u_m2u_misc1.txc_cycles_crd_ovf_cbo_ncs uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS event=0x4d,umask=0x20 01 unc_u_m2u_misc1.txc_cycles_crd_ovf_upi_ncb uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB event=0x4d,umask=0x40 01 unc_u_m2u_misc1.txc_cycles_crd_ovf_upi_ncs uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS event=0x4d,umask=0x80 01 unc_u_m2u_misc2.rxc_cycles_empty_bl uncore interconnect UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL event=0x4e,umask=2 01 unc_u_m2u_misc2.rxc_cycles_full_bl uncore interconnect UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL event=0x4e,umask=1 01 unc_u_m2u_misc2.txc_cycles_crd_ovf_vn0_ncb uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB event=0x4e,umask=4 01 unc_u_m2u_misc2.txc_cycles_crd_ovf_vn0_ncs uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS event=0x4e,umask=8 01 unc_u_m2u_misc2.txc_cycles_empty_ak uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK event=0x4e,umask=0x20 01 unc_u_m2u_misc2.txc_cycles_empty_akc uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC event=0x4e,umask=0x40 01 unc_u_m2u_misc2.txc_cycles_empty_bl uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL event=0x4e,umask=0x10 01 unc_u_m2u_misc2.txc_cycles_full_bl uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL event=0x4e,umask=0x80 01 unc_u_m2u_misc3.txc_cycles_full_ak uncore interconnect UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK event=0x4f,umask=1 01 unc_u_m2u_misc3.txc_cycles_full_akc uncore interconnect UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC event=0x4f,umask=2 01 unc_u_phold_cycles.assert_to_ack uncore interconnect Cycles PHOLD Assert to Ack : Assert to ACK event=0x45,umask=1 01 Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles unc_u_racu_requests uncore interconnect RACU Request event=0x46 01 RACU Request : Number outstanding register requests within message channel tracker uncore_iio_free_running unc_iio_bandwidth_in.part0_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x20 01 unc_iio_bandwidth_in.part1_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x21 01 unc_iio_bandwidth_in.part2_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x22 01 unc_iio_bandwidth_in.part3_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x23 01 unc_iio_bandwidth_in.part4_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x24 01 unc_iio_bandwidth_in.part5_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x25 01 unc_iio_bandwidth_in.part6_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x26 01 unc_iio_bandwidth_in.part7_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x27 01 unc_iio_bandwidth_out.part0_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x30 01 unc_iio_bandwidth_out.part1_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x31 01 unc_iio_bandwidth_out.part2_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x32 01 unc_iio_bandwidth_out.part3_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x33 01 unc_iio_bandwidth_out.part4_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x34 01 unc_iio_bandwidth_out.part5_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x35 01 unc_iio_bandwidth_out.part6_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x36 01 unc_iio_bandwidth_out.part7_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x37 01 unc_iio_clockticks uncore io IIO Clockticks event=1 01 Number of IIO clock cycles while the event is enabled unc_iio_clockticks_freerun uncore io Free running counter that increments for IIO clocktick event=0xff,umask=0x10 01 unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIe Completion Buffer Inserts of completions with data: Part 0-7 event=0xc2,ch_mask=0xff,fc_mask=7,umask=4 01 PCIe Completion Buffer Inserts of completions with data : Part 0-7 unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIe Completion Buffer Inserts of completions with data: Part 0 event=0xc2,ch_mask=1,fc_mask=7,umask=0x7001004 01 PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIe Completion Buffer Inserts of completions with data: Part 1 event=0xc2,ch_mask=2,fc_mask=7,umask=0x7002004 01 PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIe Completion Buffer Inserts of completions with data: Part 2 event=0xc2,ch_mask=4,fc_mask=7,umask=0x7004004 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIe Completion Buffer Inserts of completions with data: Part 3 event=0xc2,ch_mask=8,fc_mask=7,umask=0x7008004 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 unc_iio_comp_buf_inserts.cmpd.part4 uncore io PCIe Completion Buffer Inserts of completions with data: Part 4 event=0xc2,ch_mask=0x10,fc_mask=7,umask=0x7010004 01 PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 unc_iio_comp_buf_inserts.cmpd.part5 uncore io PCIe Completion Buffer Inserts of completions with data: Part 5 event=0xc2,ch_mask=0x20,fc_mask=7,umask=0x7020004 01 PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 unc_iio_comp_buf_inserts.cmpd.part6 uncore io PCIe Completion Buffer Inserts of completions with data: Part 6 event=0xc2,ch_mask=0x40,fc_mask=7,umask=0x7040004 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 unc_iio_comp_buf_inserts.cmpd.part7 uncore io PCIe Completion Buffer Inserts of completions with data: Part 7 event=0xc2,ch_mask=0x80,fc_mask=7,umask=0x7080004 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS event=0xd5,fc_mask=7,umask=0xff 01 unc_iio_comp_buf_occupancy.cmpd.part0 uncore io PCIe Completion Buffer Occupancy : Part 0 event=0xd5,fc_mask=7,umask=0x7000001 01 x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_occupancy.cmpd.part1 uncore io PCIe Completion Buffer Occupancy : Part 1 event=0xd5,fc_mask=7,umask=0x7000002 01 x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part2 uncore io PCIe Completion Buffer Occupancy : Part 2 event=0xd5,fc_mask=7,umask=0x7000004 01 x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part3 uncore io PCIe Completion Buffer Occupancy : Part 3 event=0xd5,fc_mask=7,umask=0x7000008 01 x4 card is plugged in to slot 3 unc_iio_comp_buf_occupancy.cmpd.part4 uncore io PCIe Completion Buffer Occupancy : Part 4 event=0xd5,fc_mask=7,umask=0x7000010 01 x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_occupancy.cmpd.part5 uncore io PCIe Completion Buffer Occupancy : Part 5 event=0xd5,fc_mask=7,umask=0x7000020 01 x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part6 uncore io PCIe Completion Buffer Occupancy : Part 6 event=0xd5,fc_mask=7,umask=0x7000040 01 x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part7 uncore io PCIe Completion Buffer Occupancy : Part 7 event=0xd5,fc_mask=7,umask=0x7000080 01 x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_read.all_parts uncore io Read request for 4 bytes made by the CPU to IIO Part0-7 event=0xc0,ch_mask=0xff,fc_mask=7,umask=4 01 unc_iio_data_req_by_cpu.mem_read.part0 uncore io Read request for 4 bytes made by the CPU to IIO Part0 event=0xc0,ch_mask=1,fc_mask=7,umask=0x7001004 01 Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_read.part1 uncore io Read request for 4 bytes made by the CPU to IIO Part1 event=0xc0,ch_mask=2,fc_mask=7,umask=0x7002004 01 Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part2 uncore io Read request for 4 bytes made by the CPU to IIO Part2 event=0xc0,ch_mask=4,fc_mask=7,umask=0x7004004 01 Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part3 uncore io Read request for 4 bytes made by the CPU to IIO Part3 event=0xc0,ch_mask=8,fc_mask=7,umask=0x7008004 01 Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_read.part4 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x7010004 01 Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_read.part5 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x7020004 01 Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part6 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x7040004 01 Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part7 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x7080004 01 Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_write.all_parts uncore io Write request of 4 bytes made to IIO Part0-7 by the CPU event=0xc0,ch_mask=0xff,fc_mask=7,umask=1 01 unc_iio_data_req_by_cpu.mem_write.iommu0 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x100,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.mem_write.iommu1 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x200,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.mem_write.part0 uncore io Write request of 4 bytes made to IIO Part0 by the CPU event=0xc0,ch_mask=1,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_write.part1 uncore io Write request of 4 bytes made to IIO Part1 by the CPU event=0xc0,ch_mask=2,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part2 uncore io Write request of 4 bytes made to IIO Part2 by the CPU event=0xc0,ch_mask=4,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part3 uncore io Write request of 4 bytes made to IIO Part3 by the CPU event=0xc0,ch_mask=8,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_write.part4 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_write.part5 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part6 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part7 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_read.part0 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=1,fc_mask=7,umask=0x7001008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_read.part1 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=2,fc_mask=7,umask=0x7002008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part2 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=4,fc_mask=7,umask=0x7004008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part3 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=8,fc_mask=7,umask=0x7008008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_read.part4 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x7010008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_read.part5 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x7020008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part6 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x7040008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part7 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x7080008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=1,fc_mask=7,umask=0x7001002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=2,fc_mask=7,umask=0x7002002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=4,fc_mask=7,umask=0x7004002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=8,fc_mask=7,umask=0x7008002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_write.part4 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x7010002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_write.part5 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x7020002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part6 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x7040002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part7 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x7080002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.cmpd.all_parts uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0xff,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.cmpd.part0 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=1,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.cmpd.part1 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=2,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.cmpd.part2 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=4,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.cmpd.part3 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=8,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.cmpd.part4 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x10,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.cmpd.part5 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x20,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.cmpd.part6 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x40,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.cmpd.part7 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x80,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.mem_read.all_parts uncore io Read request for 4 bytes made by IIO Part0-7 to Memory event=0x83,ch_mask=0xff,fc_mask=7,umask=4 01 unc_iio_data_req_of_cpu.mem_read.part0 uncore io Read request for 4 bytes made by IIO Part0 to Memory event=0x83,ch_mask=1,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part1 uncore io Read request for 4 bytes made by IIO Part1 to Memory event=0x83,ch_mask=2,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part2 uncore io Read request for 4 bytes made by IIO Part2 to Memory event=0x83,ch_mask=4,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part3 uncore io Read request for 4 bytes made by IIO Part3 to Memory event=0x83,ch_mask=8,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_read.part4 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part5 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part6 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part7 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.all_parts uncore io Write request of 4 bytes made by IIO Part0-7 to Memory event=0x83,ch_mask=0xff,fc_mask=7,umask=1 01 unc_iio_data_req_of_cpu.mem_write.part0 uncore io Write request of 4 bytes made by IIO Part0 to Memory event=0x83,ch_mask=1,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part1 uncore io Write request of 4 bytes made by IIO Part1 to Memory event=0x83,ch_mask=2,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part2 uncore io Write request of 4 bytes made by IIO Part2 to Memory event=0x83,ch_mask=4,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part3 uncore io Write request of 4 bytes made by IIO Part3 to Memory event=0x83,ch_mask=8,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.part4 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part5 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part6 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part7 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=1,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=2,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=4,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=8,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_write.part4 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_write.part5 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part6 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part7 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_inbound_arb_req.data uncore io Incoming arbitration requests : Passing data to be written event=0x86,ch_mask=0xff,fc_mask=7,umask=0x70ff020 01 Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_req.final_rd_wr uncore io Incoming arbitration requests : Issuing final read or write of line event=0x86,ch_mask=0xff,fc_mask=7,umask=8 01 Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.iommu_hit uncore io Incoming arbitration requests : Processing response from IOMMU event=0x86,ch_mask=0xff,fc_mask=7,umask=2 01 Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.iommu_req uncore io Incoming arbitration requests : Issuing to IOMMU event=0x86,ch_mask=0xff,fc_mask=7,umask=1 01 Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.req_own uncore io Incoming arbitration requests : Request Ownership event=0x86,ch_mask=0xff,fc_mask=7,umask=0x70ff004 01 Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_req.wr uncore io Incoming arbitration requests : Writing line event=0x86,ch_mask=0xff,fc_mask=7,umask=0x70ff010 01 Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.data uncore io Incoming arbitration requests granted : Passing data to be written event=0x87,ch_mask=0xff,fc_mask=7,umask=0x70ff020 01 Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.final_rd_wr uncore io Incoming arbitration requests granted : Issuing final read or write of line event=0x87,ch_mask=0xff,fc_mask=7,umask=0x70ff008 01 Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.iommu_hit uncore io Incoming arbitration requests granted : Processing response from IOMMU event=0x87,ch_mask=0xff,fc_mask=7,umask=0x70ff002 01 Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.iommu_req uncore io Incoming arbitration requests granted : Issuing to IOMMU event=0x87,ch_mask=0xff,fc_mask=7,umask=0x70ff001 01 Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.req_own uncore io Incoming arbitration requests granted : Request Ownership event=0x87,ch_mask=0xff,fc_mask=7,umask=0x70ff004 01 Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.wr uncore io Incoming arbitration requests granted : Writing line event=0x87,ch_mask=0xff,fc_mask=7,umask=0x70ff010 01 Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_iommu0.1g_hits uncore io : IOTLB Hits to a 1G Page event=0x40,umask=0x10 01 : IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB unc_iio_iommu0.2m_hits uncore io : IOTLB Hits to a 2M Page event=0x40,umask=8 01 : IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB unc_iio_iommu0.4k_hits uncore io : IOTLB Hits to a 4K Page event=0x40,umask=4 01 : IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB unc_iio_iommu0.ctxt_cache_hits uncore io : Context cache hits event=0x40,umask=0x80 01 : Context cache hits : Counts each time a first look up of the transaction hits the RCC unc_iio_iommu0.ctxt_cache_lookups uncore io : Context cache lookups event=0x40,umask=0x40 01 : Context cache lookups : Counts each time a transaction looks up root context cache unc_iio_iommu0.first_lookups uncore io : IOTLB lookups first event=0x40,umask=1 01 : IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB unc_iio_iommu0.misses uncore io IOTLB Fills (same as IOTLB miss) event=0x40,umask=0x20 01 IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB unc_iio_iommu1.num_mem_accesses uncore io : IOMMU memory access event=0x41,umask=0xc0 01 : IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel unc_iio_iommu1.pwc_1g_hits uncore io : PWC Hit to a 2M page event=0x41,umask=4 01 : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.pwc_256t_hits uncore io : PWT Hit to a 256T page event=0x41,umask=0x10 01 : PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level unc_iio_iommu1.pwc_2m_hits uncore io : PWC Hit to a 4K page event=0x41,umask=2 01 : PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level unc_iio_iommu1.pwc_512g_hits uncore io : PWC Hit to a 1G page event=0x41,umask=8 01 : PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level unc_iio_iommu1.pwc_cache_fills uncore io : PageWalk cache fill event=0x41,umask=0x20 01 : PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted unc_iio_iommu1.pwt_cache_lookups uncore io : PageWalk cache lookup event=0x41,umask=1 01 : PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache unc_iio_iommu1.slpwc_1g_hits uncore io : PWC Hit to a 2M page event=0x41,umask=4 01 : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.slpwc_256t_hits uncore io : PWC Hit to a 2M page event=0x41,umask=0x10 01 : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.slpwc_512g_hits uncore io : PWC Hit to a 1G page event=0x41,umask=8 01 : PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level unc_iio_iommu3.pwt_occupancy_msb uncore io : Global IOTLB invalidation cycles event=0x43,umask=1 01 : Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation unc_iio_mask_match_and.bus0 uncore io AND Mask/match for debug bus : Non-PCIE bus event=2,umask=1 01 AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_bus1 uncore io AND Mask/match for debug bus : Non-PCIE bus and PCIE bus event=2,umask=8 01 AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_not_bus1 uncore io AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) event=2,umask=4 01 AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus1 uncore io AND Mask/match for debug bus : PCIE bus event=2,umask=2 01 AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_bus1 uncore io AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus event=2,umask=0x10 01 AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_not_bus1 uncore io AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) event=2,umask=0x20 01 AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match unc_iio_mask_match_or.bus0 uncore io OR Mask/match for debug bus : Non-PCIE bus event=3,umask=1 01 OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_bus1 uncore io OR Mask/match for debug bus : Non-PCIE bus and PCIE bus event=3,umask=8 01 OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_not_bus1 uncore io OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) event=3,umask=4 01 OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus1 uncore io OR Mask/match for debug bus : PCIE bus event=3,umask=2 01 OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_bus1 uncore io OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus event=3,umask=0x10 01 OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_not_bus1 uncore io OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) event=3,umask=0x20 01 OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match unc_iio_num_req_of_cpu.commit.all uncore io Number requests PCIe makes of the main die : All event=0x85,ch_mask=0xfff,fc_mask=7,umask=1 01 Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU unc_iio_num_req_of_cpu_by_tgt.abort uncore io Num requests sent by PCIe - by target : Abort event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x80 01 unc_iio_num_req_of_cpu_by_tgt.confined_p2p uncore io Num requests sent by PCIe - by target : Confined P2P event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x40 01 unc_iio_num_req_of_cpu_by_tgt.loc_p2p uncore io Num requests sent by PCIe - by target : Local P2P event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x20 01 unc_iio_num_req_of_cpu_by_tgt.mcast uncore io Num requests sent by PCIe - by target : Multi-cast event=0x8e,ch_mask=0xff,fc_mask=7,umask=2 01 unc_iio_num_req_of_cpu_by_tgt.mem uncore io Num requests sent by PCIe - by target : Memory event=0x8e,ch_mask=0xff,fc_mask=7,umask=8 01 unc_iio_num_req_of_cpu_by_tgt.msgb uncore io Num requests sent by PCIe - by target : MsgB event=0x8e,ch_mask=0xff,fc_mask=7,umask=1 01 unc_iio_num_req_of_cpu_by_tgt.rem_p2p uncore io Num requests sent by PCIe - by target : Remote P2P event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x10 01 unc_iio_num_req_of_cpu_by_tgt.ubox uncore io Num requests sent by PCIe - by target : Ubox event=0x8e,ch_mask=0xff,fc_mask=7,umask=4 01 unc_iio_num_tgt_matched_req_of_cpu uncore io ITC address map 1 event=0x8f 01 UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU unc_iio_outbound_cl_reqs_issued.to_io uncore io Outbound cacheline requests issued : 64B requests issued to device event=0xd0,ch_mask=0xff,fc_mask=7,umask=8 01 Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line unc_iio_outbound_tlp_reqs_issued.to_io uncore io Outbound TLP (transaction layer packet) requests issued : To device event=0xd1,ch_mask=0xff,fc_mask=7,umask=8 01 Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer unc_iio_pwt_occupancy uncore io PWT occupancy. Does not include 9th bit of occupancy (will undercount if PWT is greater than 255 per cycle) event=0x42,umask=0xff 01 PWT occupancy : Indicates how many page walks are outstanding at any point in time unc_iio_req_from_pcie_cl_cmpl.data uncore io Request Ownership : PCIe Request complete event=0x91,ch_mask=0xff,fc_mask=7,umask=0x70ff020 01 Request Ownership : PCIe Request complete : Only for posted requests : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cl_cmpl.final_rd_wr uncore io Request Ownership : Writing line event=0x91,ch_mask=0xff,fc_mask=7,umask=0x70ff008 01 Request Ownership : Writing line : Only for posted requests : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.req_own uncore io Request Ownership : Issuing final read or write of line event=0x91,ch_mask=0xff,fc_mask=7,umask=0x70ff004 01 Request Ownership : Issuing final read or write of line : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.wr uncore io Request Ownership : Passing data to be written event=0x91,ch_mask=0xff,fc_mask=7,umask=0x70ff010 01 Request Ownership : Passing data to be written : Only for posted requests : Only for posted requests unc_iio_req_from_pcie_cmpl.final_rd_wr uncore io Processing response from IOMMU : Passing data to be written event=0x92,ch_mask=0xff,fc_mask=7,umask=0x70ff008 01 Processing response from IOMMU : Passing data to be written : Only for posted requests unc_iio_req_from_pcie_cmpl.iommu_hit uncore io Processing response from IOMMU : Issuing final read or write of line event=0x92,ch_mask=0xff,fc_mask=7,umask=0x70ff002 01 unc_iio_req_from_pcie_cmpl.iommu_req uncore io Processing response from IOMMU : Request Ownership event=0x92,ch_mask=0xff,fc_mask=7,umask=0x70ff001 01 Processing response from IOMMU : Request Ownership : Only for posted requests unc_iio_req_from_pcie_cmpl.req_own uncore io Processing response from IOMMU : Writing line event=0x92,ch_mask=0xff,fc_mask=7,umask=0x70ff004 01 Processing response from IOMMU : Writing line : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.data uncore io PCIe Request - pass complete : Passing data to be written event=0x90,ch_mask=0xff,fc_mask=7,umask=0x70ff020 01 PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.final_rd_wr uncore io PCIe Request - pass complete : Issuing final read or write of line event=0x90,ch_mask=0xff,fc_mask=7,umask=8 01 PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state unc_iio_req_from_pcie_pass_cmpl.req_own uncore io PCIe Request - pass complete : Request Ownership event=0x90,ch_mask=0xff,fc_mask=7,umask=0x70ff004 01 PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.wr uncore io PCIe Request - pass complete : Writing line event=0x90,ch_mask=0xff,fc_mask=7,umask=0x70ff010 01 PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part0 event=0xc1,ch_mask=1,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part1 event=0xc1,ch_mask=2,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part2 event=0xc1,ch_mask=4,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part3 event=0xc1,ch_mask=8,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU event=0xc1,ch_mask=1,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU event=0xc1,ch_mask=2,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU event=0xc1,ch_mask=4,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU event=0xc1,ch_mask=8,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_write.part0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=1,fc_mask=7,umask=0x7001002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.peer_write.part1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=2,fc_mask=7,umask=0x7002002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.peer_write.part2 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=4,fc_mask=7,umask=0x7004002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.peer_write.part3 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=8,fc_mask=7,umask=0x7008002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_write.part4 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x7010002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.peer_write.part5 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x7020002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.peer_write.part6 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x7040002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.peer_write.part7 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x7080002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.cmpd.part0 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=1,fc_mask=7,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.cmpd.part1 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=2,fc_mask=7,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.cmpd.part2 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=4,fc_mask=7,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.cmpd.part3 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=8,fc_mask=7,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.cmpd.part4 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x10,fc_mask=7,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.cmpd.part5 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x20,fc_mask=7,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.cmpd.part6 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x40,fc_mask=7,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.cmpd.part7 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x80,fc_mask=7,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=1,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is made by IIO Part1 to Memory event=0x84,ch_mask=2,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=4,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=8,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_read.part4 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_read.part5 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part6 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part7 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=1,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made by IIO Part1 to Memory event=0x84,ch_mask=2,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=4,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=8,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_write.part4 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_write.part5 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part6 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part7 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.peer_write.part0 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=1,fc_mask=7,umask=2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.peer_write.part1 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=2,fc_mask=7,umask=2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.peer_write.part2 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=4,fc_mask=7,umask=2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.peer_write.part3 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=8,fc_mask=7,umask=2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.peer_write.part4 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.peer_write.part5 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.peer_write.part6 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x40,fc_mask=7,umask=2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.peer_write.part7 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x80,fc_mask=7,umask=2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 uncore_m2pcie unc_m2p_clockticks uncore io M2P Clockticks event=1 01 Number of M2P clock cycles while the event is enabled unc_m2p_cms_clockticks uncore io CMS Clockticks event=0xc0 01 unc_m2p_egress_ordering.iv_snoopgo_dn uncore io Egress Blocking due to Ordering requirements : Down event=0xba,umask=4 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2p_egress_ordering.iv_snoopgo_up uncore io Egress Blocking due to Ordering requirements : Up event=0xba,umask=1 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2p_iio_credits_acquired.drs_0 uncore io M2PCIe IIO Credit Acquired : DRS event=0x33,umask=1 01 M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_acquired.drs_1 uncore io M2PCIe IIO Credit Acquired : DRS event=0x33,umask=2 01 M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_acquired.ncb_0 uncore io M2PCIe IIO Credit Acquired : NCB event=0x33,umask=4 01 M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_acquired.ncb_1 uncore io M2PCIe IIO Credit Acquired : NCB event=0x33,umask=8 01 M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_acquired.ncs_0 uncore io M2PCIe IIO Credit Acquired : NCS event=0x33,umask=0x10 01 M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class unc_m2p_iio_credits_acquired.ncs_1 uncore io M2PCIe IIO Credit Acquired : NCS event=0x33,umask=0x20 01 M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class unc_m2p_iio_credits_reject.drs uncore io M2PCIe IIO Failed to Acquire a Credit : DRS event=0x34,umask=8 01 M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class unc_m2p_iio_credits_reject.ncb uncore io M2PCIe IIO Failed to Acquire a Credit : NCB event=0x34,umask=0x10 01 M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class unc_m2p_iio_credits_reject.ncs uncore io M2PCIe IIO Failed to Acquire a Credit : NCS event=0x34,umask=0x20 01 M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class unc_m2p_iio_credits_used.drs_0 uncore io M2PCIe IIO Credits in Use : DRS to CMS Port 0 event=0x32,umask=1 01 M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_used.drs_1 uncore io M2PCIe IIO Credits in Use : DRS to CMS Port 1 event=0x32,umask=2 01 M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_used.ncb_0 uncore io M2PCIe IIO Credits in Use : NCB to CMS Port 0 event=0x32,umask=4 01 M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_used.ncb_1 uncore io M2PCIe IIO Credits in Use : NCB to CMS Port 1 event=0x32,umask=8 01 M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_used.ncs_0 uncore io M2PCIe IIO Credits in Use : NCS to CMS Port 0 event=0x32,umask=0x10 01 M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class unc_m2p_iio_credits_used.ncs_1 uncore io M2PCIe IIO Credits in Use : NCS to CMS Port 1 event=0x32,umask=0x20 01 M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class unc_m2p_local_ded_p2p_crd_taken_0.m2iosf0_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB event=0x46,umask=1 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf0_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS event=0x46,umask=2 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf1_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB event=0x46,umask=4 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf1_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS event=0x46,umask=8 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf2_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB event=0x46,umask=0x10 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf2_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS event=0x46,umask=0x20 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf3_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB event=0x46,umask=0x40 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf3_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS event=0x46,umask=0x80 01 unc_m2p_local_ded_p2p_crd_taken_1.m2iosf4_ncb uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB event=0x47,umask=1 01 unc_m2p_local_ded_p2p_crd_taken_1.m2iosf4_ncs uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS event=0x47,umask=2 01 unc_m2p_local_ded_p2p_crd_taken_1.m2iosf5_ncb uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB event=0x47,umask=4 01 unc_m2p_local_ded_p2p_crd_taken_1.m2iosf5_ncs uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS event=0x47,umask=8 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf0_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB event=0x19,umask=1 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf0_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS event=0x19,umask=2 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf1_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB event=0x19,umask=4 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf1_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS event=0x19,umask=8 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf2_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB event=0x19,umask=0x10 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf2_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS event=0x19,umask=0x20 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB event=0x19,umask=0x40 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS event=0x19,umask=0x80 01 unc_m2p_local_p2p_ded_returned_1.ms2iosf4_ncb uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB event=0x1a,umask=1 01 unc_m2p_local_p2p_ded_returned_1.ms2iosf4_ncs uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS event=0x1a,umask=2 01 unc_m2p_local_p2p_ded_returned_1.ms2iosf5_ncb uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB event=0x1a,umask=4 01 unc_m2p_local_p2p_ded_returned_1.ms2iosf5_ncs uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS event=0x1a,umask=8 01 unc_m2p_local_p2p_shar_returned.agent_0 uncore io Local P2P Shared Credits Returned : Agent0 event=0x17,umask=1 01 unc_m2p_local_p2p_shar_returned.agent_1 uncore io Local P2P Shared Credits Returned : Agent1 event=0x17,umask=2 01 unc_m2p_local_p2p_shar_returned.agent_2 uncore io Local P2P Shared Credits Returned : Agent2 event=0x17,umask=4 01 unc_m2p_local_shar_p2p_crd_returned.agent_0 uncore io Local Shared P2P Credit Returned to credit ring : Agent0 event=0x44,umask=1 01 unc_m2p_local_shar_p2p_crd_returned.agent_1 uncore io Local Shared P2P Credit Returned to credit ring : Agent1 event=0x44,umask=2 01 unc_m2p_local_shar_p2p_crd_returned.agent_2 uncore io Local Shared P2P Credit Returned to credit ring : Agent2 event=0x44,umask=4 01 unc_m2p_local_shar_p2p_crd_returned.agent_3 uncore io Local Shared P2P Credit Returned to credit ring : Agent3 event=0x44,umask=8 01 unc_m2p_local_shar_p2p_crd_returned.agent_4 uncore io Local Shared P2P Credit Returned to credit ring : Agent4 event=0x44,umask=0x10 01 unc_m2p_local_shar_p2p_crd_returned.agent_5 uncore io Local Shared P2P Credit Returned to credit ring : Agent5 event=0x44,umask=0x20 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf0_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB event=0x40,umask=1 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf0_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS event=0x40,umask=2 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf1_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB event=0x40,umask=4 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf1_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS event=0x40,umask=8 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf2_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB event=0x40,umask=0x10 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf2_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS event=0x40,umask=0x20 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf3_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB event=0x40,umask=0x40 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf3_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS event=0x40,umask=0x80 01 unc_m2p_local_shar_p2p_crd_taken_1.m2iosf4_ncb uncore io Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB event=0x41,umask=1 01 unc_m2p_local_shar_p2p_crd_taken_1.m2iosf4_ncs uncore io Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS event=0x41,umask=2 01 unc_m2p_local_shar_p2p_crd_taken_1.m2iosf5_ncb uncore io Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB event=0x41,umask=4 01 unc_m2p_local_shar_p2p_crd_taken_1.m2iosf5_ncs uncore io Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS event=0x41,umask=8 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf0_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB event=0x4a,umask=1 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf0_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS event=0x4a,umask=2 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf1_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB event=0x4a,umask=4 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf1_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS event=0x4a,umask=8 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf2_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB event=0x4a,umask=0x10 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf2_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS event=0x4a,umask=0x20 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf3_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB event=0x4a,umask=0x40 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf3_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS event=0x4a,umask=0x80 01 unc_m2p_local_shar_p2p_crd_wait_1.m2iosf4_ncb uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB event=0x4b,umask=1 01 unc_m2p_local_shar_p2p_crd_wait_1.m2iosf4_ncs uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS event=0x4b,umask=2 01 unc_m2p_local_shar_p2p_crd_wait_1.m2iosf5_ncb uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB event=0x4b,umask=4 01 unc_m2p_local_shar_p2p_crd_wait_1.m2iosf5_ncs uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS event=0x4b,umask=8 01 unc_m2p_p2p_crd_occupancy.all uncore io P2P Credit Occupancy : All event=0x14,umask=0x10 01 unc_m2p_p2p_crd_occupancy.local_ncb uncore io P2P Credit Occupancy : Local NCB event=0x14,umask=1 01 unc_m2p_p2p_crd_occupancy.local_ncs uncore io P2P Credit Occupancy : Local NCS event=0x14,umask=2 01 unc_m2p_p2p_crd_occupancy.remote_ncb uncore io P2P Credit Occupancy : Remote NCB event=0x14,umask=4 01 unc_m2p_p2p_crd_occupancy.remote_ncs uncore io P2P Credit Occupancy : Remote NCS event=0x14,umask=8 01 unc_m2p_p2p_ded_received.all uncore io Dedicated Credits Received : All event=0x16,umask=0x10 01 unc_m2p_p2p_ded_received.local_ncb uncore io Dedicated Credits Received : Local NCB event=0x16,umask=1 01 unc_m2p_p2p_ded_received.local_ncs uncore io Dedicated Credits Received : Local NCS event=0x16,umask=2 01 unc_m2p_p2p_ded_received.remote_ncb uncore io Dedicated Credits Received : Remote NCB event=0x16,umask=4 01 unc_m2p_p2p_ded_received.remote_ncs uncore io Dedicated Credits Received : Remote NCS event=0x16,umask=8 01 unc_m2p_p2p_shar_received.all uncore io Shared Credits Received : All event=0x15,umask=0x10 01 unc_m2p_p2p_shar_received.local_ncb uncore io Shared Credits Received : Local NCB event=0x15,umask=1 01 unc_m2p_p2p_shar_received.local_ncs uncore io Shared Credits Received : Local NCS event=0x15,umask=2 01 unc_m2p_p2p_shar_received.remote_ncb uncore io Shared Credits Received : Remote NCB event=0x15,umask=4 01 unc_m2p_p2p_shar_received.remote_ncs uncore io Shared Credits Received : Remote NCS event=0x15,umask=8 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi0_drs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS event=0x48,umask=1 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi0_ncb uncore io Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB event=0x48,umask=2 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi0_ncs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS event=0x48,umask=4 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi1_drs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS event=0x48,umask=8 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi1_ncb uncore io Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB event=0x48,umask=0x10 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi1_ncs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS event=0x48,umask=0x20 01 unc_m2p_remote_ded_p2p_crd_taken_1.upi2_drs uncore io Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS event=0x49,umask=1 01 unc_m2p_remote_ded_p2p_crd_taken_1.upi2_ncb uncore io Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB event=0x49,umask=2 01 unc_m2p_remote_ded_p2p_crd_taken_1.upi2_ncs uncore io Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS event=0x49,umask=4 01 unc_m2p_remote_p2p_ded_returned.upi0_ncb uncore io Remote P2P Dedicated Credits Returned : UPI0 - NCB event=0x1b,umask=1 01 unc_m2p_remote_p2p_ded_returned.upi0_ncs uncore io Remote P2P Dedicated Credits Returned : UPI0 - NCS event=0x1b,umask=2 01 unc_m2p_remote_p2p_ded_returned.upi1_ncb uncore io Remote P2P Dedicated Credits Returned : UPI1 - NCB event=0x1b,umask=4 01 unc_m2p_remote_p2p_ded_returned.upi1_ncs uncore io Remote P2P Dedicated Credits Returned : UPI1 - NCS event=0x1b,umask=8 01 unc_m2p_remote_p2p_ded_returned.upi2_ncb uncore io Remote P2P Dedicated Credits Returned : UPI2 - NCB event=0x1b,umask=0x10 01 unc_m2p_remote_p2p_ded_returned.upi2_ncs uncore io Remote P2P Dedicated Credits Returned : UPI2 - NCS event=0x1b,umask=0x20 01 unc_m2p_remote_p2p_shar_returned.agent_0 uncore io Remote P2P Shared Credits Returned : Agent0 event=0x18,umask=1 01 unc_m2p_remote_p2p_shar_returned.agent_1 uncore io Remote P2P Shared Credits Returned : Agent1 event=0x18,umask=2 01 unc_m2p_remote_p2p_shar_returned.agent_2 uncore io Remote P2P Shared Credits Returned : Agent2 event=0x18,umask=4 01 unc_m2p_remote_shar_p2p_crd_returned.agent_0 uncore io Remote Shared P2P Credit Returned to credit ring : Agent0 event=0x45,umask=1 01 unc_m2p_remote_shar_p2p_crd_returned.agent_1 uncore io Remote Shared P2P Credit Returned to credit ring : Agent1 event=0x45,umask=2 01 unc_m2p_remote_shar_p2p_crd_returned.agent_2 uncore io Remote Shared P2P Credit Returned to credit ring : Agent2 event=0x45,umask=4 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi0_drs uncore io Remote Shared P2P Credit Taken - 0 : UPI0 - DRS event=0x42,umask=1 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi0_ncb uncore io Remote Shared P2P Credit Taken - 0 : UPI0 - NCB event=0x42,umask=2 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi0_ncs uncore io Remote Shared P2P Credit Taken - 0 : UPI0 - NCS event=0x42,umask=4 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi1_drs uncore io Remote Shared P2P Credit Taken - 0 : UPI1 - DRS event=0x42,umask=8 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi1_ncb uncore io Remote Shared P2P Credit Taken - 0 : UPI1 - NCB event=0x42,umask=0x10 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi1_ncs uncore io Remote Shared P2P Credit Taken - 0 : UPI1 - NCS event=0x42,umask=0x20 01 unc_m2p_remote_shar_p2p_crd_taken_1.upi2_drs uncore io Remote Shared P2P Credit Taken - 1 : UPI2 - DRS event=0x43,umask=1 01 unc_m2p_remote_shar_p2p_crd_taken_1.upi2_ncb uncore io Remote Shared P2P Credit Taken - 1 : UPI2 - NCB event=0x43,umask=2 01 unc_m2p_remote_shar_p2p_crd_taken_1.upi2_ncs uncore io Remote Shared P2P Credit Taken - 1 : UPI2 - NCS event=0x43,umask=4 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi0_drs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS event=0x4c,umask=1 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi0_ncb uncore io Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB event=0x4c,umask=2 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi0_ncs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS event=0x4c,umask=4 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi1_drs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS event=0x4c,umask=8 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi1_ncb uncore io Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB event=0x4c,umask=0x10 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi1_ncs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS event=0x4c,umask=0x20 01 unc_m2p_remote_shar_p2p_crd_wait_1.upi2_drs uncore io Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS event=0x4d,umask=1 01 unc_m2p_remote_shar_p2p_crd_wait_1.upi2_ncb uncore io Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB event=0x4d,umask=2 01 unc_m2p_remote_shar_p2p_crd_wait_1.upi2_ncs uncore io Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS event=0x4d,umask=4 01 unc_m2p_rxc_cycles_ne.all uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x80 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.cha_idi uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=1 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.cha_ncb uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=2 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.cha_ncs uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=4 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.iio_ncb uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x20 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.iio_ncs uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x40 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.upi_ncb uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=8 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.upi_ncs uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x10 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_inserts.all uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x80 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.cha_idi uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=1 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.cha_ncb uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=2 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.cha_ncs uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=4 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.iio_ncb uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x20 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.iio_ncs uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x40 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.upi_ncb uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=8 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.upi_ncs uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x10 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_txc_credits.pmm uncore io UNC_M2P_TxC_CREDITS.PMM event=0x2d,umask=2 01 unc_m2p_txc_credits.prq uncore io UNC_M2P_TxC_CREDITS.PRQ event=0x2d,umask=1 01 unc_m2p_txc_cycles_full.pmm_block_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x80 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.pmm_block_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=8 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_ne.pmm_distress_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x80 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.pmm_distress_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=8 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters uncore_m2hbm unc_m2hbm_clockticks uncore memory Cycles - at UCLK event=1 01 unc_m2hbm_cms_clockticks uncore memory CMS Clockticks event=0xc0 01 unc_m2hbm_direct2core_not_taken_dirstate uncore memory Cycles when direct to core mode (which bypasses the CHA) was disabled event=0x17,umask=7 01 unc_m2hbm_direct2core_not_taken_dirstate.non_cisgress uncore memory Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress event=0x17,umask=2 01 Counts the number of time non cisgress D2C was not honoured by egress due to directory state constraints unc_m2hbm_direct2core_not_taken_notforked uncore memory Counts the time when FM didn't do d2c for fill reads (cross tile case) event=0x4a 01 unc_m2hbm_direct2core_txn_override uncore memory Number of reads in which direct to core transaction were overridden event=0x18,umask=3 01 unc_m2hbm_direct2core_txn_override.cisgress uncore memory Number of reads in which direct to core transaction was overridden : Cisgress event=0x18,umask=2 01 unc_m2hbm_direct2upi_not_taken_credits uncore memory Number of reads in which direct to Intel UPI transactions were overridden event=0x1b,umask=7 01 unc_m2hbm_direct2upi_not_taken_dirstate uncore memory Cycles when direct to Intel UPI was disabled event=0x1a,umask=7 01 unc_m2hbm_direct2upi_not_taken_dirstate.cisgress uncore memory Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored event=0x1a,umask=4 01 Counts cisgress d2K that was not honored due to directory constraints unc_m2hbm_direct2upi_not_taken_dirstate.egress uncore memory Cycles when Direct2UPI was Disabled : Egress Ignored D2U event=0x1a,umask=1 01 Counts the number of time D2K was not honoured by egress due to directory state constraints unc_m2hbm_direct2upi_not_taken_dirstate.non_cisgress uncore memory Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored event=0x1a,umask=2 01 Counts non cisgress d2K that was not honored due to directory constraints unc_m2hbm_direct2upi_txn_override uncore memory Number of reads that a message sent direct2 Intel UPI was overridden event=0x1c,umask=3 01 unc_m2hbm_direct2upi_txn_override.cisgress uncore memory Number of times a direct to UPI transaction was overridden event=0x1c,umask=2 01 unc_m2hbm_directory_hit.clean_a uncore memory Directory Hit : On NonDirty Line in A State event=0x1d,umask=0x80 01 unc_m2hbm_directory_hit.clean_i uncore memory Directory Hit : On NonDirty Line in I State event=0x1d,umask=0x10 01 unc_m2hbm_directory_hit.clean_p uncore memory Directory Hit : On NonDirty Line in L State event=0x1d,umask=0x40 01 unc_m2hbm_directory_hit.clean_s uncore memory Directory Hit : On NonDirty Line in S State event=0x1d,umask=0x20 01 unc_m2hbm_directory_hit.dirty_a uncore memory Directory Hit : On Dirty Line in A State event=0x1d,umask=8 01 unc_m2hbm_directory_hit.dirty_i uncore memory Directory Hit : On Dirty Line in I State event=0x1d,umask=1 01 unc_m2hbm_directory_hit.dirty_p uncore memory Directory Hit : On Dirty Line in L State event=0x1d,umask=4 01 unc_m2hbm_directory_hit.dirty_s uncore memory Directory Hit : On Dirty Line in S State event=0x1d,umask=2 01 unc_m2hbm_directory_lookup.any uncore memory Multi-socket cacheline Directory lookups (any state found) event=0x20,umask=1 01 Counts the number of hit data returns to egress with any directory to non persistent memory unc_m2hbm_directory_lookup.state_a uncore memory Multi-socket cacheline Directory lookups (cacheline found in A state) event=0x20,umask=8 01 Counts the number of hit data returns to egress with directory A to non persistent memory unc_m2hbm_directory_lookup.state_i uncore memory Multi-socket cacheline Directory lookup (cacheline found in I state) event=0x20,umask=2 01 Counts the number of hit data returns to egress with directory I to non persistent memory unc_m2hbm_directory_lookup.state_s uncore memory Multi-socket cacheline Directory lookup (cacheline found in S state) event=0x20,umask=4 01 Counts the number of hit data returns to egress with directory S to non persistent memory unc_m2hbm_directory_miss.clean_a uncore memory Directory Miss : On NonDirty Line in A State event=0x1e,umask=0x80 01 unc_m2hbm_directory_miss.clean_i uncore memory Directory Miss : On NonDirty Line in I State event=0x1e,umask=0x10 01 unc_m2hbm_directory_miss.clean_p uncore memory Directory Miss : On NonDirty Line in L State event=0x1e,umask=0x40 01 unc_m2hbm_directory_miss.clean_s uncore memory Directory Miss : On NonDirty Line in S State event=0x1e,umask=0x20 01 unc_m2hbm_directory_miss.dirty_a uncore memory Directory Miss : On Dirty Line in A State event=0x1e,umask=8 01 unc_m2hbm_directory_miss.dirty_i uncore memory Directory Miss : On Dirty Line in I State event=0x1e,umask=1 01 unc_m2hbm_directory_miss.dirty_p uncore memory Directory Miss : On Dirty Line in L State event=0x1e,umask=4 01 unc_m2hbm_directory_miss.dirty_s uncore memory Directory Miss : On Dirty Line in S State event=0x1e,umask=2 01 unc_m2hbm_directory_update.a2i uncore memory Multi-socket cacheline Directory update from A to I event=0x21,umask=0x320 01 unc_m2hbm_directory_update.a2s uncore memory Multi-socket cacheline Directory update from A to S event=0x21,umask=0x340 01 unc_m2hbm_directory_update.any uncore memory Multi-socket cacheline Directory update from/to Any state event=0x21,umask=0x301 01 unc_m2hbm_directory_update.a_to_i_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x120 01 Counts 1lm or 2lm hit data returns that would result in directory update from A to I to non persistent memory unc_m2hbm_directory_update.a_to_i_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x220 01 Counts 2lm miss data returns that would result in directory update from A to I to non persistent memory unc_m2hbm_directory_update.a_to_s_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x140 01 Counts 1lm or 2lm hit data returns that would result in directory update from A to S to non persistent memory unc_m2hbm_directory_update.a_to_s_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x240 01 Counts 2lm miss data returns that would result in directory update from A to S to non persistent memory unc_m2hbm_directory_update.hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x101 01 Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory unc_m2hbm_directory_update.i2a uncore memory Multi-socket cacheline Directory update from I to A event=0x21,umask=0x304 01 unc_m2hbm_directory_update.i2s uncore memory Multi-socket cacheline Directory update from I to S event=0x21,umask=0x302 01 unc_m2hbm_directory_update.i_to_a_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x104 01 Counts 1lm or 2lm hit data returns that would result in directory update from I to A to non persistent memory unc_m2hbm_directory_update.i_to_a_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x204 01 Counts 2lm miss data returns that would result in directory update from I to A to non persistent memory unc_m2hbm_directory_update.i_to_s_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x102 01 Counts 1lm or 2lm hit data returns that would result in directory update from I to S to non persistent memory unc_m2hbm_directory_update.i_to_s_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x202 01 Counts 2lm miss data returns that would result in directory update from I to S to non persistent memory unc_m2hbm_directory_update.miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x201 01 Counts any 2lm miss data return that would result in directory update to non persistent memory unc_m2hbm_directory_update.s2a uncore memory Multi-socket cacheline Directory update from S to A event=0x21,umask=0x310 01 unc_m2hbm_directory_update.s2i uncore memory Multi-socket cacheline Directory update from S to I event=0x21,umask=0x308 01 unc_m2hbm_directory_update.s_to_a_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x110 01 Counts 1lm or 2lm hit data returns that would result in directory update from S to A to non persistent memory unc_m2hbm_directory_update.s_to_a_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x210 01 Counts 2lm miss data returns that would result in directory update from S to A to non persistent memory unc_m2hbm_directory_update.s_to_i_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x108 01 Counts 1lm or 2lm hit data returns that would result in directory update from S to I to non persistent memory unc_m2hbm_directory_update.s_to_i_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x208 01 Counts 2lm miss data returns that would result in directory update from S to I to non persistent memory unc_m2hbm_distress.ad uncore memory Count distress signalled on AkAd cmp message event=0x67,umask=0x20 01 unc_m2hbm_distress.all uncore memory Count distress signalled on any packet type event=0x67,umask=1 01 unc_m2hbm_distress.bl_cmp uncore memory Count distress signalled on Bl Cmp message event=0x67,umask=0x40 01 unc_m2hbm_distress.crosstile_nmwr uncore memory Count distress signalled on NM fill write message event=0x67,umask=0x10 01 unc_m2hbm_distress.d2cha uncore memory Count distress signalled on D2Cha message event=0x67,umask=8 01 unc_m2hbm_distress.d2core uncore memory Count distress signalled on D2c message event=0x67,umask=2 01 unc_m2hbm_distress.d2upi uncore memory Count distress signalled on D2k message event=0x67,umask=4 01 unc_m2hbm_egress_ordering.iv_snoopgo_dn uncore memory Egress Blocking due to Ordering requirements : Down event=0xba,umask=0x80000004 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2hbm_egress_ordering.iv_snoopgo_up uncore memory Egress Blocking due to Ordering requirements : Up event=0xba,umask=0x80000001 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2hbm_igr_starve_winner.mask7 uncore memory Count when Starve Glocab counter is at 7 event=0x44,umask=0x80 01 unc_m2hbm_imc_reads.all uncore memory Reads to iMC issued event=0x24,umask=0x304 01 unc_m2hbm_imc_reads.ch0.all uncore memory UNC_M2HBM_IMC_READS.CH0.ALL event=0x24,umask=0x104 01 unc_m2hbm_imc_reads.ch0.normal uncore memory UNC_M2HBM_IMC_READS.CH0.NORMAL event=0x24,umask=0x101 01 unc_m2hbm_imc_reads.ch0_all uncore memory UNC_M2HBM_IMC_READS.CH0_ALL event=0x24,umask=0x104 01 unc_m2hbm_imc_reads.ch0_from_tgr uncore memory UNC_M2HBM_IMC_READS.CH0_FROM_TGR event=0x24,umask=0x140 01 unc_m2hbm_imc_reads.ch0_isoch uncore memory Critical Priority - Ch0 event=0x24,umask=0x102 01 unc_m2hbm_imc_reads.ch0_normal uncore memory UNC_M2HBM_IMC_READS.CH0_NORMAL event=0x24,umask=0x101 01 unc_m2hbm_imc_reads.ch1.all uncore memory UNC_M2HBM_IMC_READS.CH1.ALL event=0x24,umask=0x204 01 unc_m2hbm_imc_reads.ch1.normal uncore memory UNC_M2HBM_IMC_READS.CH1.NORMAL event=0x24,umask=0x201 01 unc_m2hbm_imc_reads.ch1_all uncore memory UNC_M2HBM_IMC_READS.CH1_ALL event=0x24,umask=0x204 01 unc_m2hbm_imc_reads.ch1_from_tgr uncore memory From TGR - Ch1 event=0x24,umask=0x240 01 unc_m2hbm_imc_reads.ch1_isoch uncore memory Critical Priority - Ch1 event=0x24,umask=0x202 01 unc_m2hbm_imc_reads.ch1_normal uncore memory UNC_M2HBM_IMC_READS.CH1_NORMAL event=0x24,umask=0x201 01 unc_m2hbm_imc_reads.from_tgr uncore memory From TGR - All Channels event=0x24,umask=0x340 01 unc_m2hbm_imc_reads.isoch uncore memory Critical Priority - All Channels event=0x24,umask=0x302 01 unc_m2hbm_imc_reads.normal uncore memory UNC_M2HBM_IMC_READS.NORMAL event=0x24,umask=0x301 01 unc_m2hbm_imc_writes.all uncore memory All Writes - All Channels event=0x25,umask=0x1810 01 unc_m2hbm_imc_writes.ch0.all uncore memory UNC_M2HBM_IMC_WRITES.CH0.ALL event=0x25,umask=0x810 01 unc_m2hbm_imc_writes.ch0.full uncore memory UNC_M2HBM_IMC_WRITES.CH0.FULL event=0x25,umask=0x801 01 unc_m2hbm_imc_writes.ch0.partial uncore memory UNC_M2HBM_IMC_WRITES.CH0.PARTIAL event=0x25,umask=0x802 01 unc_m2hbm_imc_writes.ch0_all uncore memory UNC_M2HBM_IMC_WRITES.CH0_ALL event=0x25,umask=0x810 01 unc_m2hbm_imc_writes.ch0_from_tgr uncore memory From TGR - Ch0 event=0x25 01 unc_m2hbm_imc_writes.ch0_full uncore memory UNC_M2HBM_IMC_WRITES.CH0_FULL event=0x25,umask=0x801 01 unc_m2hbm_imc_writes.ch0_full_isoch uncore memory ISOCH Full Line - Ch0 event=0x25,umask=0x804 01 unc_m2hbm_imc_writes.ch0_ni uncore memory Non-Inclusive - Ch0 event=0x25 01 unc_m2hbm_imc_writes.ch0_ni_miss uncore memory Non-Inclusive Miss - Ch0 event=0x25 01 unc_m2hbm_imc_writes.ch0_partial uncore memory UNC_M2HBM_IMC_WRITES.CH0_PARTIAL event=0x25,umask=0x802 01 unc_m2hbm_imc_writes.ch0_partial_isoch uncore memory ISOCH Partial - Ch0 event=0x25,umask=0x808 01 unc_m2hbm_imc_writes.ch1.all uncore memory All Writes - Ch1 event=0x25,umask=0x1010 01 unc_m2hbm_imc_writes.ch1.full uncore memory Full Line Non-ISOCH - Ch1 event=0x25,umask=0x1001 01 unc_m2hbm_imc_writes.ch1.partial uncore memory Partial Non-ISOCH - Ch1 event=0x25,umask=0x1002 01 unc_m2hbm_imc_writes.ch1_all uncore memory All Writes - Ch1 event=0x25,umask=0x1010 01 unc_m2hbm_imc_writes.ch1_from_tgr uncore memory From TGR - Ch1 event=0x25 01 unc_m2hbm_imc_writes.ch1_full uncore memory Full Line Non-ISOCH - Ch1 event=0x25,umask=0x1001 01 unc_m2hbm_imc_writes.ch1_full_isoch uncore memory ISOCH Full Line - Ch1 event=0x25,umask=0x1004 01 unc_m2hbm_imc_writes.ch1_ni uncore memory Non-Inclusive - Ch1 event=0x25 01 unc_m2hbm_imc_writes.ch1_ni_miss uncore memory Non-Inclusive Miss - Ch1 event=0x25 01 unc_m2hbm_imc_writes.ch1_partial uncore memory Partial Non-ISOCH - Ch1 event=0x25,umask=0x1002 01 unc_m2hbm_imc_writes.ch1_partial_isoch uncore memory ISOCH Partial - Ch1 event=0x25,umask=0x1008 01 unc_m2hbm_imc_writes.from_tgr uncore memory From TGR - All Channels event=0x25 01 unc_m2hbm_imc_writes.full uncore memory Full Non-ISOCH - All Channels event=0x25,umask=0x1801 01 unc_m2hbm_imc_writes.full_isoch uncore memory ISOCH Full Line - All Channels event=0x25,umask=0x1804 01 unc_m2hbm_imc_writes.ni uncore memory Non-Inclusive - All Channels event=0x25 01 unc_m2hbm_imc_writes.ni_miss uncore memory Non-Inclusive Miss - All Channels event=0x25 01 unc_m2hbm_imc_writes.partial uncore memory Partial Non-ISOCH - All Channels event=0x25,umask=0x1802 01 unc_m2hbm_imc_writes.partial_isoch uncore memory ISOCH Partial - All Channels event=0x25,umask=0x1808 01 unc_m2hbm_prefcam_cis_drops uncore memory UNC_M2HBM_PREFCAM_CIS_DROPS event=0x5c 01 unc_m2hbm_prefcam_demand_drops.ch0_upi uncore memory Data Prefetches Dropped event=0x58,umask=2 01 unc_m2hbm_prefcam_demand_drops.ch0_xpt uncore memory Data Prefetches Dropped event=0x58,umask=1 01 unc_m2hbm_prefcam_demand_drops.ch1_upi uncore memory Data Prefetches Dropped event=0x58,umask=8 01 unc_m2hbm_prefcam_demand_drops.ch1_xpt uncore memory Data Prefetches Dropped event=0x58,umask=4 01 unc_m2hbm_prefcam_demand_drops.upi_allch uncore memory Data Prefetches Dropped : UPI - All Channels event=0x58,umask=0xa 01 unc_m2hbm_prefcam_demand_drops.xpt_allch uncore memory Data Prefetches Dropped event=0x58,umask=5 01 unc_m2hbm_prefcam_demand_merge.upi_allch uncore memory : UPI - All Channels event=0x5d,umask=0xa 01 unc_m2hbm_prefcam_demand_merge.xpt_allch uncore memory : XPT - All Channels event=0x5d,umask=5 01 unc_m2hbm_prefcam_demand_no_merge.rd_merged uncore memory Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x40 01 unc_m2hbm_prefcam_demand_no_merge.wr_merged uncore memory Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x20 01 unc_m2hbm_prefcam_demand_no_merge.wr_squashed uncore memory Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x10 01 unc_m2hbm_prefcam_inserts.ch0_upi uncore memory Prefetch CAM Inserts : UPI - Ch 0 event=0x56,umask=2 01 unc_m2hbm_prefcam_inserts.ch0_xpt uncore memory Prefetch CAM Inserts : XPT - Ch 0 event=0x56,umask=1 01 unc_m2hbm_prefcam_inserts.ch1_upi uncore memory Prefetch CAM Inserts : UPI - Ch 1 event=0x56,umask=8 01 unc_m2hbm_prefcam_inserts.ch1_xpt uncore memory Prefetch CAM Inserts : XPT - Ch 1 event=0x56,umask=4 01 unc_m2hbm_prefcam_inserts.upi_allch uncore memory Prefetch CAM Inserts : UPI - All Channels event=0x56,umask=0xa 01 unc_m2hbm_prefcam_inserts.xpt_allch uncore memory Prefetch CAM Inserts : XPT - All Channels event=0x56,umask=5 01 Prefetch CAM Inserts : XPT -All Channels unc_m2hbm_prefcam_occupancy.allch uncore memory Prefetch CAM Occupancy : All Channels event=0x54,umask=3 01 unc_m2hbm_prefcam_occupancy.ch0 uncore memory Prefetch CAM Occupancy : Channel 0 event=0x54,umask=1 01 unc_m2hbm_prefcam_occupancy.ch1 uncore memory Prefetch CAM Occupancy : Channel 1 event=0x54,umask=2 01 unc_m2hbm_prefcam_resp_miss.allch uncore memory All Channels event=0x5f,umask=3 01 unc_m2hbm_prefcam_resp_miss.ch0 uncore memory : Channel 0 event=0x5f,umask=1 01 unc_m2hbm_prefcam_resp_miss.ch1 uncore memory : Channel 1 event=0x5f,umask=2 01 unc_m2hbm_prefcam_rxc_deallocs.1lm_posted uncore memory UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED event=0x62,umask=2 01 unc_m2hbm_prefcam_rxc_deallocs.cis uncore memory UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS event=0x62,umask=8 01 unc_m2hbm_prefcam_rxc_deallocs.squashed uncore memory UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED event=0x62,umask=1 01 unc_m2hbm_prefcam_rxc_occupancy uncore memory UNC_M2HBM_PREFCAM_RxC_OCCUPANCY event=0x60 01 unc_m2hbm_rxc_ad.inserts uncore memory AD Ingress (from CMS) : AD Ingress (from CMS) Allocations event=2,umask=1 01 unc_m2hbm_rxc_ad_inserts uncore memory AD Ingress (from CMS) : AD Ingress (from CMS) Allocations event=2,umask=1 01 unc_m2hbm_rxc_ad_occupancy uncore memory AD Ingress (from CMS) Occupancy event=3 01 unc_m2hbm_rxc_bl.inserts uncore memory BL Ingress (from CMS) : BL Ingress (from CMS) Allocations event=4,umask=1 01 Counts anytime a BL packet is added to Ingress unc_m2hbm_rxc_bl_inserts uncore memory BL Ingress (from CMS) : BL Ingress (from CMS) Allocations event=4,umask=1 01 Counts anytime a BL packet is added to Ingress unc_m2hbm_rxc_bl_occupancy uncore memory BL Ingress (from CMS) Occupancy event=5 01 unc_m2hbm_tgr_ad_credits uncore memory Number AD Ingress Credits event=0x2e 01 unc_m2hbm_tgr_bl_credits uncore memory Number BL Ingress Credits event=0x2f 01 unc_m2hbm_tracker_inserts.ch0 uncore memory Tracker Inserts : Channel 0 event=0x32,umask=0x104 01 unc_m2hbm_tracker_inserts.ch1 uncore memory Tracker Inserts : Channel 1 event=0x32,umask=0x204 01 unc_m2hbm_tracker_occupancy.ch0 uncore memory Tracker Occupancy : Channel 0 event=0x33,umask=1 01 unc_m2hbm_tracker_occupancy.ch1 uncore memory Tracker Occupancy : Channel 1 event=0x33,umask=2 01 unc_m2hbm_txc_ad.inserts uncore memory AD Egress (to CMS) : AD Egress (to CMS) Allocations event=6,umask=1 01 Counts anytime a AD packet is added to Egress unc_m2hbm_txc_ad_inserts uncore memory AD Egress (to CMS) : AD Egress (to CMS) Allocations event=6,umask=1 01 Counts anytime a AD packet is added to Egress unc_m2hbm_txc_ad_occupancy uncore memory AD Egress (to CMS) Occupancy event=7 01 unc_m2hbm_txc_bl.inserts_cms0 uncore memory BL Egress (to CMS) : Inserts - CMS0 - Near Side event=0xe,umask=0x101 01 Counts the number of BL transactions to CMS add port 0 unc_m2hbm_txc_bl.inserts_cms1 uncore memory BL Egress (to CMS) : Inserts - CMS1 - Far Side event=0xe,umask=0x201 01 Counts the number of BL transactions to CMS add port 1 unc_m2hbm_txc_bl_occupancy.all uncore memory BL Egress (to CMS) Occupancy : All event=0xf,umask=3 01 unc_m2hbm_txc_bl_occupancy.cms0 uncore memory BL Egress (to CMS) Occupancy : Common Mesh Stop - Near Side event=0xf,umask=1 01 unc_m2hbm_txc_bl_occupancy.cms1 uncore memory BL Egress (to CMS) Occupancy : Common Mesh Stop - Far Side event=0xf,umask=2 01 unc_m2hbm_wpq_flush.ch0 uncore memory WPQ Flush : Channel 0 event=0x42,umask=1 01 unc_m2hbm_wpq_flush.ch1 uncore memory WPQ Flush : Channel 1 event=0x42,umask=2 01 unc_m2hbm_wpq_no_reg_crd.chn0 uncore memory M2M and iMC WPQ Cycles w/Credits - Regular : Channel 0 event=0x37,umask=1 01 unc_m2hbm_wpq_no_reg_crd.chn1 uncore memory M2M and iMC WPQ Cycles w/Credits - Regular : Channel 1 event=0x37,umask=2 01 unc_m2hbm_wpq_no_spec_crd.chn0 uncore memory M2M and iMC WPQ Cycles w/Credits - Special : Channel 0 event=0x38,umask=1 01 unc_m2hbm_wpq_no_spec_crd.chn1 uncore memory M2M and iMC WPQ Cycles w/Credits - Special : Channel 1 event=0x38,umask=2 01 unc_m2hbm_wr_tracker_inserts.ch0 uncore memory Write Tracker Inserts : Channel 0 event=0x40,umask=1 01 unc_m2hbm_wr_tracker_inserts.ch1 uncore memory Write Tracker Inserts : Channel 1 event=0x40,umask=2 01 unc_m2hbm_wr_tracker_nonposted_inserts.ch0 uncore memory Write Tracker Non-Posted Inserts : Channel 0 event=0x4d,umask=1 01 unc_m2hbm_wr_tracker_nonposted_inserts.ch1 uncore memory Write Tracker Non-Posted Inserts : Channel 1 event=0x4d,umask=2 01 unc_m2hbm_wr_tracker_nonposted_occupancy.ch0 uncore memory Write Tracker Non-Posted Occupancy : Channel 0 event=0x4c,umask=1 01 unc_m2hbm_wr_tracker_nonposted_occupancy.ch1 uncore memory Write Tracker Non-Posted Occupancy : Channel 1 event=0x4c,umask=2 01 unc_m2hbm_wr_tracker_posted_inserts.ch0 uncore memory Write Tracker Posted Inserts : Channel 0 event=0x48,umask=1 01 unc_m2hbm_wr_tracker_posted_inserts.ch1 uncore memory Write Tracker Posted Inserts : Channel 1 event=0x48,umask=2 01 unc_m2hbm_wr_tracker_posted_occupancy.ch0 uncore memory Write Tracker Posted Occupancy : Channel 0 event=0x47,umask=1 01 unc_m2hbm_wr_tracker_posted_occupancy.ch1 uncore memory Write Tracker Posted Occupancy : Channel 1 event=0x47,umask=2 01 uncore_mchbm unc_mchbm_act_count.all uncore memory Activate due to read, write, underfill, or bypass event=2,umask=0xff 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.rd uncore memory Activate due to read event=2,umask=0x11 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.rd_pch0 uncore memory HBM Activate Count : Activate due to Read in PCH0 event=2,umask=1 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.rd_pch1 uncore memory HBM Activate Count : Activate due to Read in PCH1 event=2,umask=0x10 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.ufill uncore memory HBM Activate Count : Underfill Read transaction on Page Empty or Page Miss event=2,umask=0x44 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.ufill_pch0 uncore memory HBM Activate Count event=2,umask=4 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.ufill_pch1 uncore memory HBM Activate Count event=2,umask=0x40 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.wr uncore memory Activate due to write event=2,umask=0x22 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.wr_pch0 uncore memory HBM Activate Count : Activate due to Write in PCH0 event=2,umask=2 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.wr_pch1 uncore memory HBM Activate Count : Activate due to Write in PCH1 event=2,umask=0x20 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_cas_count.all uncore memory All CAS commands issued event=5,umask=0xff 01 unc_mchbm_cas_count.pch0 uncore memory Pseudo Channel 0 event=5,umask=0x40 01 HBM RD_CAS and WR_CAS Commands unc_mchbm_cas_count.pch1 uncore memory Pseudo Channel 1 event=5,umask=0x80 01 HBM RD_CAS and WR_CAS Commands unc_mchbm_cas_count.rd uncore memory Read CAS commands issued (regular and underfill) event=5,umask=0xcf 01 unc_mchbm_cas_count.rd_pre_reg uncore memory Regular read CAS commands with precharge event=5,umask=0xc2 01 unc_mchbm_cas_count.rd_pre_underfill uncore memory Underfill read CAS commands with precharge event=5,umask=0xc8 01 unc_mchbm_cas_count.rd_reg uncore memory Regular read CAS commands issued (does not include underfills) event=5,umask=0xc1 01 unc_mchbm_cas_count.rd_underfill uncore memory Underfill read CAS commands issued event=5,umask=0xc4 01 unc_mchbm_cas_count.wr uncore memory Write CAS commands issued event=5,umask=0xf0 01 unc_mchbm_cas_count.wr_nonpre uncore memory HBM RD_CAS and WR_CAS Commands. : HBM WR_CAS commands w/o auto-pre event=5,umask=0xd0 01 unc_mchbm_cas_count.wr_pre uncore memory Write CAS commands with precharge event=5,umask=0xe0 01 unc_mchbm_cas_issued_req_len.pch0 uncore memory Pseudo Channel 0 event=6,umask=0x40 01 unc_mchbm_cas_issued_req_len.pch1 uncore memory Pseudo Channel 1 event=6,umask=0x80 01 unc_mchbm_cas_issued_req_len.rd_32b uncore memory Read CAS Command in Interleaved Mode (32B) event=6,umask=0xc8 01 unc_mchbm_cas_issued_req_len.rd_64b uncore memory Read CAS Command in Regular Mode (64B) in Pseudochannel 0 event=6,umask=0xc1 01 unc_mchbm_cas_issued_req_len.rd_ufill_32b uncore memory Underfill Read CAS Command in Interleaved Mode (32B) event=6,umask=0xd0 01 unc_mchbm_cas_issued_req_len.rd_ufill_64b uncore memory Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1 event=6,umask=0xc2 01 unc_mchbm_cas_issued_req_len.wr_32b uncore memory Write CAS Command in Interleaved Mode (32B) event=6,umask=0xe0 01 unc_mchbm_cas_issued_req_len.wr_64b uncore memory Write CAS Command in Regular Mode (64B) in Pseudochannel 0 event=6,umask=0xc4 01 unc_mchbm_clockticks uncore memory IMC Clockticks at DCLK frequency event=1,umask=1 01 unc_mchbm_hbm_preall.pch0 uncore memory HBM Precharge All Commands event=0x44,umask=1 01 Counts the number of times that the precharge all command was sent unc_mchbm_hbm_preall.pch1 uncore memory HBM Precharge All Commands event=0x44,umask=2 01 Counts the number of times that the precharge all command was sent unc_mchbm_hbm_pre_all uncore memory All Precharge Commands event=0x44,umask=3 01 Precharge All Commands: Counts the number of times that the precharge all command was sent unc_mchbm_hclockticks uncore memory IMC Clockticks at HCLK frequency event=1 01 unc_mchbm_pre_count.all uncore memory All precharge events event=3,umask=0xff 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.pgt uncore memory Precharge from MC page table event=3,umask=0x88 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.pgt_pch0 uncore memory HBM Precharge commands. : Precharges from Page Table event=3,umask=8 01 Counts the number of HBM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY unc_mchbm_pre_count.pgt_pch1 uncore memory HBM Precharge commands event=3,umask=0x80 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.rd uncore memory Precharge due to read on page miss event=3,umask=0x11 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.rd_pch0 uncore memory HBM Precharge commands. : Precharge due to read event=3,umask=1 01 Counts the number of HBM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_mchbm_pre_count.rd_pch1 uncore memory HBM Precharge commands event=3,umask=0x10 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.ufill uncore memory HBM Precharge commands event=3,umask=0x44 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.ufill_pch0 uncore memory HBM Precharge commands event=3,umask=4 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.ufill_pch1 uncore memory HBM Precharge commands event=3,umask=0x40 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.wr uncore memory Precharge due to write on page miss event=3,umask=0x22 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.wr_pch0 uncore memory HBM Precharge commands. : Precharge due to write event=3,umask=2 01 Counts the number of HBM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_mchbm_pre_count.wr_pch1 uncore memory HBM Precharge commands event=3,umask=0x20 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_rdb_full uncore memory Counts the number of cycles where the read buffer has greater than UMASK elements. NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR) event=0x19 01 unc_mchbm_rdb_inserts uncore memory Counts the number of inserts into the read buffer event=0x17,umask=3 01 unc_mchbm_rdb_inserts.pch0 uncore memory Read Data Buffer Inserts event=0x17,umask=1 01 unc_mchbm_rdb_inserts.pch1 uncore memory Read Data Buffer Inserts event=0x17,umask=2 01 unc_mchbm_rdb_occupancy uncore memory Counts the number of elements in the read buffer per cycle event=0x1a 01 unc_mchbm_rpq_inserts.pch0 uncore memory Read Pending Queue Allocations event=0x10,umask=1 01 Read Pending Queue Allocations: Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_mchbm_rpq_inserts.pch1 uncore memory Read Pending Queue Allocations event=0x10,umask=2 01 Read Pending Queue Allocations: Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_mchbm_rpq_occupancy_pch0 uncore memory Read Pending Queue Occupancy event=0x80 01 Read Pending Queue Occupancy: Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_mchbm_rpq_occupancy_pch1 uncore memory Read Pending Queue Occupancy event=0x81 01 Read Pending Queue Occupancy: Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_mchbm_wpq_inserts.pch0 uncore memory Write Pending Queue Allocations event=0x20,umask=1 01 Write Pending Queue Allocations: Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_mchbm_wpq_inserts.pch1 uncore memory Write Pending Queue Allocations event=0x20,umask=2 01 Write Pending Queue Allocations: Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_mchbm_wpq_occupancy_pch0 uncore memory Write Pending Queue Occupancy event=0x82 01 Write Pending Queue Occupancy: Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to memory. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_mchbm_wpq_occupancy_pch1 uncore memory Write Pending Queue Occupancy event=0x83 01 Write Pending Queue Occupancy: Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to memory. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_mchbm_wpq_read_hit uncore memory Write Pending Queue CAM Match event=0x23 01 Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_read_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x23,umask=1 01 Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_read_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x23,umask=2 01 Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_write_hit uncore memory Write Pending Queue CAM Match event=0x24 01 Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_write_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x24,umask=1 01 Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_write_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x24,umask=2 01 Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_act_count.all uncore memory Activate due to read, write, underfill, or bypass event=2,umask=0xff 01 DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_cas_count.all uncore memory All DRAM CAS commands issued event=5,umask=0xff 01 DRAM RD_CAS and WR_CAS Commands. : All DRAM Read and Write actions : DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM CAS commands issued on this channel unc_m_cas_count.pch0 uncore memory DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 event=5,umask=0x40 01 DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.pch1 uncore memory DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 event=5,umask=0x80 01 DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd uncore memory All DRAM read CAS commands issued (including underfills) event=5,umask=0xcf 01 DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel. This includes underfills unc_m_cas_count.rd_pre_reg uncore memory DRAM RD_CAS and WR_CAS Commands event=5,umask=0xc2 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd_pre_underfill uncore memory DRAM RD_CAS and WR_CAS Commands event=5,umask=0xc8 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd_reg uncore memory All DRAM read CAS commands issued (does not include underfills) event=5,umask=0xc1 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_underfill uncore memory DRAM underfill read CAS commands issued event=5,umask=0xc4 01 DRAM RD_CAS and WR_CAS Commands. : Underfill Read Issued : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.wr uncore memory All DRAM write CAS commands issued event=5,umask=0xf0 01 DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel unc_m_cas_count.wr_nonpre uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre event=5,umask=0xd0 01 DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.wr_pre uncore memory DRAM RD_CAS and WR_CAS Commands event=5,umask=0xe0 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_issued_req_len.pch0 uncore memory Pseudo Channel 0 event=6,umask=0x40 01 unc_m_cas_issued_req_len.pch1 uncore memory Pseudo Channel 1 event=6,umask=0x80 01 unc_m_cas_issued_req_len.rd_32b uncore memory Read CAS Command in Interleaved Mode (32B) event=6,umask=0xc8 01 unc_m_cas_issued_req_len.rd_64b uncore memory Read CAS Command in Regular Mode (64B) in Pseudochannel 0 event=6,umask=0xc1 01 unc_m_cas_issued_req_len.rd_ufill_32b uncore memory Underfill Read CAS Command in Interleaved Mode (32B) event=6,umask=0xd0 01 unc_m_cas_issued_req_len.rd_ufill_64b uncore memory Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1 event=6,umask=0xc2 01 unc_m_cas_issued_req_len.wr_32b uncore memory Write CAS Command in Interleaved Mode (32B) event=6,umask=0xe0 01 unc_m_cas_issued_req_len.wr_64b uncore memory Write CAS Command in Regular Mode (64B) in Pseudochannel 0 event=6,umask=0xc4 01 unc_m_clockticks uncore memory IMC Clockticks at DCLK frequency event=1,umask=1 01 Number of DRAM DCLK clock cycles while the event is enabled unc_m_dram_pre_all uncore memory DRAM Precharge All Commands event=0x44,umask=3 01 DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent unc_m_hclockticks uncore memory IMC Clockticks at HCLK frequency event=1 01 Number of DRAM HCLK clock cycles while the event is enabled unc_m_pcls.rd uncore memory UNC_M_PCLS.RD event=0xa0,umask=5 01 unc_m_pcls.total uncore memory UNC_M_PCLS.TOTAL event=0xa0,umask=0xf 01 unc_m_pcls.wr uncore memory UNC_M_PCLS.WR event=0xa0,umask=0xa 01 unc_m_pmm_rpq_inserts uncore memory PMM Read Pending Queue inserts event=0xe3 01 Counts number of read requests allocated in the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.all_sch0 uncore memory PMM Read Pending Queue occupancy event=0xe0,umask=1 01 Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.all_sch1 uncore memory PMM Read Pending Queue occupancy event=0xe0,umask=2 01 Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.gnt_wait_sch0 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x10 01 PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.gnt_wait_sch1 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x20 01 PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.no_gnt_sch0 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=4 01 Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.no_gnt_sch1 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=8 01 Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_wpq_cycles_ne uncore memory PMM (for IXP) Write Queue Cycles Not Empty event=0xe5 01 unc_m_pmm_wpq_inserts uncore memory PMM Write Pending Queue inserts event=0xe7 01 Counts number of write requests allocated in the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.all uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=3 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM unc_m_pmm_wpq_occupancy.all_sch0 uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=1 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.all_sch1 uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=2 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.cas uncore memory PMM (for IXP) Write Pending Queue Occupancy event=0xe4,umask=0xc 01 PMM (for IXP) Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP DIMM unc_m_pmm_wpq_occupancy.pwr uncore memory PMM (for IXP) Write Pending Queue Occupancy event=0xe4,umask=0x30 01 PMM (for IXP) Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP DIMM unc_m_power_channel_ppd uncore memory Channel PPD Cycles event=0x85 01 Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of unc_m_power_cke_cycles.low_0 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=1 01 CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.low_1 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=2 01 CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.low_2 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=4 01 CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.low_3 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=8 01 CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_crit_throttle_cycles.slot0 uncore memory Throttle Cycles for Rank 0 event=0x86,umask=1 01 Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID unc_m_power_crit_throttle_cycles.slot1 uncore memory Throttle Cycles for Rank 0 event=0x86,umask=2 01 Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_self_refresh uncore memory Clock-Enabled Self-Refresh event=0x43 01 Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_pre_count.all uncore memory Precharge due to read, write, underfill, or PGT event=3,umask=0xff 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.pgt uncore memory DRAM Precharge commands event=3,umask=0x88 01 DRAM Precharge commands. Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.pgt_pch0 uncore memory DRAM Precharge commands. : Precharges from Page Table event=3,umask=8 01 DRAM Precharge commands. : Precharges from Page Table : Counts the number of DRAM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY unc_m_pre_count.pgt_pch1 uncore memory DRAM Precharge commands event=3,umask=0x80 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.rd uncore memory Precharge due to read on page miss event=3,umask=0x11 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.rd_pch0 uncore memory DRAM Precharge commands. : Precharge due to read event=3,umask=1 01 DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_m_pre_count.rd_pch1 uncore memory DRAM Precharge commands event=3,umask=0x10 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.ufill uncore memory DRAM Precharge commands event=3,umask=0x44 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.ufill_pch0 uncore memory DRAM Precharge commands event=3,umask=4 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.ufill_pch1 uncore memory DRAM Precharge commands event=3,umask=0x40 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.wr uncore memory Precharge due to write on page miss event=3,umask=0x22 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.wr_pch0 uncore memory DRAM Precharge commands. : Precharge due to write event=3,umask=2 01 DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_m_pre_count.wr_pch1 uncore memory DRAM Precharge commands event=3,umask=0x20 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_rdb_full uncore memory Counts the number of cycles where the read buffer has greater than UMASK elements. This includes reads to both DDR and PMEM. NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR) event=0x19 01 unc_m_rdb_inserts uncore memory Counts the number of inserts into the read buffer destined for DDR. Does not count reads destined for PMEM event=0x17,umask=3 01 unc_m_rdb_inserts.pch0 uncore memory Read Data Buffer Inserts event=0x17,umask=1 01 unc_m_rdb_inserts.pch1 uncore memory Read Data Buffer Inserts event=0x17,umask=2 01 unc_m_rdb_ne uncore memory Counts the number of cycles where there's at least one element in the read buffer. This includes reads to both DDR and PMEM event=0x18,umask=3 01 unc_m_rdb_ne.pch0 uncore memory Read Data Buffer Not Empty event=0x18,umask=1 01 unc_m_rdb_ne.pch1 uncore memory Read Data Buffer Not Empty event=0x18,umask=2 01 unc_m_rdb_not_empty uncore memory Counts the number of cycles where there's at least one element in the read buffer. This includes reads to both DDR and PMEM event=0x18,umask=3 01 unc_m_rdb_occupancy uncore memory Counts the number of elements in the read buffer, including reads to both DDR and PMEM event=0x1a 01 unc_m_rpq_inserts.pch0 uncore memory Read Pending Queue Allocations event=0x10,umask=1 01 Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_m_rpq_inserts.pch1 uncore memory Read Pending Queue Allocations event=0x10,umask=2 01 Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_m_rpq_occupancy_pch0 uncore memory Read Pending Queue Occupancy event=0x80 01 Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_m_rpq_occupancy_pch1 uncore memory Read Pending Queue Occupancy event=0x81 01 Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_m_sb_accesses.accepts uncore memory Scoreboard accepts event=0xd2,umask=5 01 unc_m_sb_accesses.fm_rd_cmps uncore memory Scoreboard Accesses : Write Accepts event=0xd2,umask=0x40 01 unc_m_sb_accesses.fm_wr_cmps uncore memory Scoreboard Accesses : Write Rejects event=0xd2,umask=0x80 01 unc_m_sb_accesses.nm_rd_cmps uncore memory Scoreboard Accesses : FM read completions event=0xd2,umask=0x10 01 unc_m_sb_accesses.nm_wr_cmps uncore memory Scoreboard Accesses : FM write completions event=0xd2,umask=0x20 01 unc_m_sb_accesses.rd_accepts uncore memory Scoreboard Accesses : Read Accepts event=0xd2,umask=1 01 unc_m_sb_accesses.rd_rejects uncore memory Scoreboard Accesses : Read Rejects event=0xd2,umask=2 01 unc_m_sb_accesses.rejects uncore memory Scoreboard rejects event=0xd2,umask=0xa 01 unc_m_sb_accesses.wr_accepts uncore memory Scoreboard Accesses : NM read completions event=0xd2,umask=4 01 unc_m_sb_accesses.wr_rejects uncore memory Scoreboard Accesses : NM write completions event=0xd2,umask=8 01 unc_m_sb_canary.alloc uncore memory : Alloc event=0xd9,umask=1 01 unc_m_sb_canary.dealloc uncore memory : Dealloc event=0xd9,umask=2 01 unc_m_sb_canary.fm_rd_starved uncore memory : Near Mem Write Starved event=0xd9,umask=0x20 01 unc_m_sb_canary.fm_tgr_wr_starved uncore memory : Far Mem Write Starved event=0xd9,umask=0x80 01 unc_m_sb_canary.fm_wr_starved uncore memory : Far Mem Read Starved event=0xd9,umask=0x40 01 unc_m_sb_canary.nm_rd_starved uncore memory : Valid event=0xd9,umask=8 01 unc_m_sb_canary.nm_wr_starved uncore memory : Near Mem Read Starved event=0xd9,umask=0x10 01 unc_m_sb_canary.vld uncore memory : Reject event=0xd9,umask=4 01 unc_m_sb_inserts.block_rds uncore memory Scoreboard Inserts : Block region reads event=0xd6,umask=0x10 01 unc_m_sb_inserts.block_wrs uncore memory Scoreboard Inserts : Block region writes event=0xd6,umask=0x20 01 unc_m_sb_inserts.pmm_rds uncore memory Scoreboard Inserts : Persistent Mem reads event=0xd6,umask=4 01 unc_m_sb_inserts.pmm_wrs uncore memory Scoreboard Inserts : Persistent Mem writes event=0xd6,umask=8 01 unc_m_sb_inserts.rds uncore memory Scoreboard Inserts : Reads event=0xd6,umask=1 01 unc_m_sb_inserts.wrs uncore memory Scoreboard Inserts : Writes event=0xd6,umask=2 01 unc_m_sb_occupancy.block_rds uncore memory Scoreboard Occupancy : Block region reads event=0xd5,umask=0x20 01 unc_m_sb_occupancy.block_wrs uncore memory Scoreboard Occupancy : Block region writes event=0xd5,umask=0x40 01 unc_m_sb_occupancy.pmm_rds uncore memory Scoreboard Occupancy : Persistent Mem reads event=0xd5,umask=4 01 unc_m_sb_occupancy.pmm_wrs uncore memory Scoreboard Occupancy : Persistent Mem writes event=0xd5,umask=8 01 unc_m_sb_occupancy.rds uncore memory Scoreboard Occupancy : Reads event=0xd5,umask=1 01 unc_m_sb_pref_inserts.all uncore memory Scoreboard Prefetch Inserts : All event=0xda,umask=1 01 unc_m_sb_pref_inserts.ddr uncore memory Scoreboard Prefetch Inserts : DDR4 event=0xda,umask=2 01 unc_m_sb_pref_inserts.pmm uncore memory Scoreboard Prefetch Inserts : PMM event=0xda,umask=4 01 unc_m_sb_pref_occupancy.all uncore memory Scoreboard Prefetch Occupancy : All event=0xdb,umask=1 01 unc_m_sb_pref_occupancy.ddr uncore memory Scoreboard Prefetch Occupancy : DDR4 event=0xdb,umask=2 01 unc_m_sb_pref_occupancy.pmm uncore memory Scoreboard Prefetch Occupancy : Persistent Mem event=0xdb,umask=4 01 unc_m_sb_reject.canary uncore memory Number of Scoreboard Requests Rejected event=0xd4,umask=8 01 unc_m_sb_reject.ddr_early_cmp uncore memory Number of Scoreboard Requests Rejected event=0xd4,umask=0x20 01 unc_m_sb_reject.fm_addr_cnflt uncore memory Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict event=0xd4,umask=2 01 unc_m_sb_reject.nm_set_cnflt uncore memory Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict event=0xd4,umask=1 01 unc_m_sb_reject.patrol_set_cnflt uncore memory Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict event=0xd4,umask=4 01 unc_m_sb_strv_alloc.fm_rd uncore memory : Far Mem Read - Set event=0xd7,umask=2 01 unc_m_sb_strv_alloc.fm_tgr uncore memory : Near Mem Read - Clear event=0xd7,umask=0x10 01 unc_m_sb_strv_alloc.fm_wr uncore memory : Far Mem Write - Set event=0xd7,umask=8 01 unc_m_sb_strv_alloc.nm_rd uncore memory : Near Mem Read - Set event=0xd7,umask=1 01 unc_m_sb_strv_alloc.nm_wr uncore memory : Near Mem Write - Set event=0xd7,umask=4 01 unc_m_sb_strv_dealloc.fm_rd uncore memory : Far Mem Read - Set event=0xde,umask=2 01 unc_m_sb_strv_dealloc.fm_tgr uncore memory : Near Mem Read - Clear event=0xde,umask=0x10 01 unc_m_sb_strv_dealloc.fm_wr uncore memory : Far Mem Write - Set event=0xde,umask=8 01 unc_m_sb_strv_dealloc.nm_rd uncore memory : Near Mem Read - Set event=0xde,umask=1 01 unc_m_sb_strv_dealloc.nm_wr uncore memory : Near Mem Write - Set event=0xde,umask=4 01 unc_m_sb_strv_occ.fm_rd uncore memory : Far Mem Read event=0xd8,umask=2 01 unc_m_sb_strv_occ.fm_tgr uncore memory : Near Mem Read - Clear event=0xd8,umask=0x10 01 unc_m_sb_strv_occ.fm_wr uncore memory : Far Mem Write event=0xd8,umask=8 01 unc_m_sb_strv_occ.nm_rd uncore memory : Near Mem Read event=0xd8,umask=1 01 unc_m_sb_strv_occ.nm_wr uncore memory : Near Mem Write event=0xd8,umask=4 01 unc_m_tagchk.hit uncore memory 2LM Tag check hit in near memory cache (DDR4) event=0xd3,umask=1 01 unc_m_tagchk.miss_clean uncore memory 2LM Tag check miss, no data at this line event=0xd3,umask=2 01 unc_m_tagchk.miss_dirty uncore memory 2LM Tag check miss, existing data may be evicted to PMM event=0xd3,umask=4 01 unc_m_tagchk.nm_rd_hit uncore memory 2LM Tag check hit due to memory read event=0xd3,umask=8 01 unc_m_tagchk.nm_wr_hit uncore memory 2LM Tag check hit due to memory write event=0xd3,umask=0x10 01 unc_m_wpq_inserts.pch0 uncore memory Write Pending Queue Allocations event=0x20,umask=1 01 Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_m_wpq_inserts.pch1 uncore memory Write Pending Queue Allocations event=0x20,umask=2 01 Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_m_wpq_occupancy_pch0 uncore memory Write Pending Queue Occupancy event=0x82 01 Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_m_wpq_occupancy_pch1 uncore memory Write Pending Queue Occupancy event=0x83 01 Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_p_clockticks uncore power PCU PCLK Clockticks event=1 01 Number of PCU PCLK Clock cycles while the event is enabled unc_p_fivr_ps_ps0_cycles uncore power Phase Shed 0 Cycles event=0x75 01 Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0 unc_p_fivr_ps_ps1_cycles uncore power Phase Shed 1 Cycles event=0x76 01 Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1 unc_p_fivr_ps_ps2_cycles uncore power Phase Shed 2 Cycles event=0x77 01 Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2 unc_p_fivr_ps_ps3_cycles uncore power Phase Shed 3 Cycles event=0x78 01 Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3 unc_p_freq_clip_avx256 uncore power AVX256 Frequency Clipping event=0x49 01 unc_p_freq_clip_avx512 uncore power AVX512 Frequency Clipping event=0x4a 01 unc_p_freq_max_limit_thermal_cycles uncore power Thermal Strongest Upper Limit Cycles event=4 01 Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring unc_p_freq_max_power_cycles uncore power Power Strongest Upper Limit Cycles event=5 01 Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=0x73 01 IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0x74 01 Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_memory_phase_shedding_cycles uncore power Memory Phase Shedding Cycles event=0x2f 01 Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency unc_p_pkg_residency_c0_cycles uncore power Package C State Residency - C0 event=0x2a 01 Package C State Residency - C0 : Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c2e_cycles uncore power Package C State Residency - C2E event=0x2b 01 Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c6_cycles uncore power Package C State Residency - C6 event=0x2d 01 Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times unc_p_pmax_throttled_cycles uncore power UNC_P_PMAX_THROTTLED_CYCLES event=6 01 unc_p_power_state_occupancy_cores_c0 uncore power Number of cores in C0 event=0x35 01 Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy_cores_c3 uncore power Number of cores in C3 event=0x36 01 Number of cores in C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy_cores_c6 uncore power Number of cores in C6 event=0x37 01 Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_prochot_external_cycles uncore power External Prochot event=0xa 01 External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip unc_p_prochot_internal_cycles uncore power Internal Prochot event=9 01 Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0x72 01 Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores core_reject_l2q.all cache Requests rejected by the L2Q event=0x31,period=200003 00 Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops dl1.dirty_eviction cache L1 Cache evictions for dirty data event=0x51,period=200003,umask=1 00 Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback fetch_stall.icache_fill_pending_cycles cache Cycles code-fetch stalled due to an outstanding ICache miss event=0x86,period=200003,umask=2 00 Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy l2_reject_xq.all cache Requests rejected by the XQ event=0x30,period=200003 00 Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims longest_lat_cache.miss cache L2 cache request misses event=0x2e,period=200003,umask=0x41 00 Counts memory requests originating from the core that miss in the L2 cache longest_lat_cache.reference cache L2 cache requests event=0x2e,period=200003,umask=0x4f 00 Counts memory requests originating from the core that reference a cache line in the L2 cache mem_load_uops_retired.dram_hit cache Loads retired that came from DRAM (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x80 00 Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response Supports address when precise (Must be precise) mem_load_uops_retired.hitm cache Memory uop retired where cross core or cross module HITM occurred (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x20 00 Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks Supports address when precise (Must be precise) mem_load_uops_retired.l1_hit cache Load uops retired that hit L1 data cache (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=1 00 Counts load uops retired that hit the L1 data cache Supports address when precise (Must be precise) mem_load_uops_retired.l1_miss cache Load uops retired that missed L1 data cache (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=8 00 Counts load uops retired that miss the L1 data cache Supports address when precise (Must be precise) mem_load_uops_retired.l2_hit cache Load uops retired that hit L2 (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=2 00 Counts load uops retired that hit in the L2 cache Supports address when precise (Must be precise) mem_load_uops_retired.l2_miss cache Load uops retired that missed L2 (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x10 00 Counts load uops retired that miss in the L2 cache Supports address when precise (Must be precise) mem_load_uops_retired.wcb_hit cache Loads retired that hit WCB (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x40 00 Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs Supports address when precise (Must be precise) mem_uops_retired.all cache Memory uops retired (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x83 00 Counts the number of memory uops retired that is either a loads or a store or both Supports address when precise (Must be precise) mem_uops_retired.all_loads cache Load uops retired (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x81 00 Counts the number of load uops retired Supports address when precise (Must be precise) mem_uops_retired.all_stores cache Store uops retired (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x82 00 Counts the number of store uops retired Supports address when precise (Must be precise) mem_uops_retired.lock_loads cache Locked load uops retired (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x21 00 Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks Supports address when precise (Must be precise) mem_uops_retired.split cache Memory uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x43 00 Counts memory uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) mem_uops_retired.split_loads cache Load uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x41 00 Counts load uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) mem_uops_retired.split_stores cache Stores uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x42 00 Counts store uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) offcore_response cache Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=1 00 offcore_response.any_data_rd.l2_hit cache Counts data reads (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000043091 00 Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.any cache Counts data reads (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600003091 00 Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hitm_other_core cache Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000003091 00 Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400003091 00 Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200003091 00 Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_hit cache Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000043010 00 Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.any cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600003010 00 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hitm_other_core cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000003010 00 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400003010 00 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200003010 00 Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_hit cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x00000432b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.any cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x36000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hitm_other_core cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x10000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hit_other_core_no_fwd cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x04000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x02000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.any_response cache Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000018000 00 Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_hit cache Counts requests to the uncore subsystem that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000048000 00 Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hitm_other_core cache Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000008000 00 Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hit_other_core_no_fwd cache Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400008000 00 Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_needed cache Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200008000 00 Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_hit cache Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040022 00 Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.any cache Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hit_other_core_no_fwd cache Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.any_response cache Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010400 00 Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_hit cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.any cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hitm_other_core cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hit_other_core_no_fwd cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_needed cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_hit cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.any cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwd cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.outstanding cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_hit cache Counts demand cacheable data reads of full cache lines that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040001 00 Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.any cache Counts demand cacheable data reads of full cache lines that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000001 00 Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hitm_other_core cache Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000001 00 Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwd cache Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000001 00 Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000001 00 Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.outstanding cache Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000001 00 Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_hit cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.any cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hitm_other_core cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwd cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.outstanding cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_hit cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.any cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hitm_other_core cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hit_other_core_no_fwd cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_reads.l2_miss.any cache Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000080 00 Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_hit cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000044000 00 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.any cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600004000 00 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.hitm_other_core cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000004000 00 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.hit_other_core_no_fwd cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400004000 00 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200004000 00 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_writes.l2_miss.any cache Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000100 00 Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_hit cache Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000042000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.any cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_hit cache Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.any cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_hit cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.any cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwd cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_hit cache Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000044800 00 Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.any cache Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600004800 00 Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_hit cache Counts data cache lines requests by software prefetch instructions that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000041000 00 Counts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.any cache Counts data cache lines requests by software prefetch instructions that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600001000 00 Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hitm_other_core cache Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000001000 00 Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hit_other_core_no_fwd cache Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400001000 00 Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200001000 00 Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) cycles_div_busy.fpdiv floating point Cycles the FP divide unit is busy event=0xcd,period=200003,umask=2 00 Counts core cycles the floating point divide unit is busy machine_clears.fp_assist floating point Machine clears due to FP assists event=0xc3,period=200003,umask=4 00 Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result uops_retired.fpdiv floating point Floating point divide uops retired. (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=8 00 Counts the number of floating point divide uops retired (Must be precise) baclears.all frontend BACLEARs asserted for any branch type event=0xe6,period=200003,umask=1 00 Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns baclears.cond frontend BACLEARs asserted for conditional branch event=0xe6,period=200003,umask=0x10 00 Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches baclears.return frontend BACLEARs asserted for return branch event=0xe6,period=200003,umask=8 00 Counts BACLEARS on return instructions decode_restriction.predecode_wrong frontend Decode restrictions due to predicting wrong instruction length event=0xe9,period=200003,umask=1 00 Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect icache.accesses frontend References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture event=0x80,period=200003,umask=3 00 Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line. This event counts differently than Intel processors based on Silvermont microarchitecture icache.hit frontend References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture event=0x80,period=200003,umask=1 00 Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture icache.misses frontend References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture event=0x80,period=200003,umask=2 00 Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture ms_decoded.ms_entry frontend MS decode starts event=0xe7,period=200003,umask=1 00 Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear machine_clears.memory_ordering memory Machine clears due to memory ordering issue event=0xc3,period=200003,umask=2 00 Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data misalign_mem_ref.load_page_split memory Load uops that split a page (Precise event capable) (Must be precise) event=0x13,period=200003,umask=2 00 Counts when a memory load of a uop spans a page boundary (a split) is retired (Must be precise) misalign_mem_ref.store_page_split memory Store uops that split a page (Precise event capable) (Must be precise) event=0x13,period=200003,umask=4 00 Counts when a memory store of a uop spans a page boundary (a split) is retired (Must be precise) fetch_stall.all other Cycles code-fetch stalled due to any reason event=0x86,period=200003 00 Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events fetch_stall.itlb_fill_pending_cycles other Cycles code-fetch stalled due to an outstanding ITLB miss event=0x86,period=200003,umask=1 00 Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation hw_interrupts.masked other Cycles hardware interrupts are masked event=0xcb,period=200003,umask=2 00 Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not hw_interrupts.pending_and_masked other Cycles pending interrupts are masked event=0xcb,period=200003,umask=4 00 Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0) hw_interrupts.received other Hardware interrupts received event=0xcb,period=203,umask=1 00 Counts hardware interrupts received by the processor br_inst_retired.all_branches pipeline Retired branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003 00 Counts branch instructions retired for all branch types. This is an architectural performance event (Must be precise) br_inst_retired.all_taken_branches pipeline Retired taken branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0x80 00 Counts the number of taken branch instructions retired (Must be precise) br_inst_retired.call pipeline Retired near call instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xf9 00 Counts near CALL branch instructions retired (Must be precise) br_inst_retired.far_branch pipeline Retired far branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xbf 00 Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return (Must be precise) br_inst_retired.ind_call pipeline Retired near indirect call instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xfb 00 Counts near indirect CALL branch instructions retired (Must be precise) br_inst_retired.jcc pipeline Retired conditional branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0x7e 00 Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken (Must be precise) br_inst_retired.non_return_ind pipeline Retired instructions of near indirect Jmp or call (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xeb 00 Counts near indirect call or near indirect jmp branch instructions retired (Must be precise) br_inst_retired.rel_call pipeline Retired near relative call instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xfd 00 Counts near relative CALL branch instructions retired (Must be precise) br_inst_retired.return pipeline Retired near return instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xf7 00 Counts near return branch instructions retired (Must be precise) br_inst_retired.taken_jcc pipeline Retired conditional branch instructions that were taken (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xfe 00 Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken (Must be precise) br_misp_retired.all_branches pipeline Retired mispredicted branch instructions (Precise event capable) (Must be precise) event=0xc5,period=200003 00 Counts mispredicted branch instructions retired including all branch types (Must be precise) br_misp_retired.ind_call pipeline Retired mispredicted near indirect call instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xfb 00 Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted (Must be precise) br_misp_retired.jcc pipeline Retired mispredicted conditional branch instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0x7e 00 Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition) (Must be precise) br_misp_retired.non_return_ind pipeline Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xeb 00 Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise) br_misp_retired.return pipeline Retired mispredicted near return instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xf7 00 Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted (Must be precise) br_misp_retired.taken_jcc pipeline Retired mispredicted conditional branch instructions that were taken (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xfe 00 Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken (Must be precise) cpu_clk_unhalted.core pipeline Core cycles when core is not halted (Fixed event) event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event cpu_clk_unhalted.core_p pipeline Core cycles when core is not halted event=0x3c,period=2000003 00 Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003 00 Reference cycles when core is not halted. This event uses a programmable general purpose performance counter cpu_clk_unhalted.ref_tsc pipeline Reference cycles when core is not halted (Fixed event) event=0,period=2000003,umask=3 00 Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event cycles_div_busy.all pipeline Cycles a divider is busy event=0xcd,period=2000003 00 Counts core cycles if either divide unit is busy cycles_div_busy.idiv pipeline Cycles the integer divide unit is busy event=0xcd,period=200003,umask=1 00 Counts core cycles the integer divide unit is busy inst_retired.any pipeline Instructions retired (Fixed event) event=0xc0,period=2000003 00 Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event inst_retired.any_p pipeline Instructions retired (Precise event capable) (Must be precise) event=0xc0,period=2000003 00 Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time (Must be precise) issue_slots_not_consumed.any pipeline Unfilled issue slots per cycle event=0xca,period=200003 00 Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY) issue_slots_not_consumed.recovery pipeline Unfilled issue slots per cycle to recover event=0xca,period=200003,umask=2 00 Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue issue_slots_not_consumed.resource_full pipeline Unfilled issue slots per cycle because of a full resource in the backend event=0xca,period=200003,umask=1 00 Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count ld_blocks.4k_alias pipeline Loads blocked because address has 4k partial address false dependence (Precise event capable) (Must be precise) event=3,period=200003,umask=4 00 Counts loads that block because their address modulo 4K matches a pending store (Must be precise) ld_blocks.all_block pipeline Loads blocked (Precise event capable) (Must be precise) event=3,period=200003,umask=0x10 00 Counts anytime a load that retires is blocked for any reason (Must be precise) ld_blocks.data_unknown pipeline Loads blocked due to store data not ready (Precise event capable) (Must be precise) event=3,period=200003,umask=1 00 Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available (Must be precise) ld_blocks.store_forward pipeline Loads blocked due to store forward restriction (Precise event capable) (Must be precise) event=3,period=200003,umask=2 00 Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted (Must be precise) ld_blocks.utlb_miss pipeline Loads blocked because address in not in the UTLB (Precise event capable) (Must be precise) event=3,period=200003,umask=8 00 Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB) (Must be precise) machine_clears.all pipeline All machine clears event=0xc3,period=200003 00 Counts machine clears for any reason machine_clears.disambiguation pipeline Machine clears due to memory disambiguation event=0xc3,period=200003,umask=8 00 Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=200003,umask=1 00 Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors uops_issued.any pipeline Uops issued to the back end per cycle event=0xe,period=200003 00 Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear uops_not_delivered.any pipeline Uops requested but not-delivered to the back-end per cycle event=0x9c,period=200003 00 This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue uops_retired.any pipeline Uops retired (Precise event capable) (Must be precise) event=0xc2,period=2000003 00 Counts uops which retired (Must be precise) uops_retired.idiv pipeline Integer divide uops retired. (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=0x10 00 Counts the number of integer divide uops retired (Must be precise) uops_retired.ms pipeline MS uops retired (Precise event capable) (Must be precise) event=0xc2,period=2000003,umask=1 00 Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist (Must be precise) itlb.miss virtual memory ITLB misses event=0x81,period=200003,umask=4 00 Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB mem_uops_retired.dtlb_miss virtual memory Memory uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x13 00 Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss Supports address when precise (Must be precise) mem_uops_retired.dtlb_miss_loads virtual memory Load uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x11 00 Counts load uops retired that caused a DTLB miss Supports address when precise (Must be precise) mem_uops_retired.dtlb_miss_stores virtual memory Store uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x12 00 Counts store uops retired that caused a DTLB miss Supports address when precise (Must be precise) page_walks.cycles virtual memory Duration of page-walks in cycles event=5,period=200003,umask=3 00 Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch page_walks.d_side_cycles virtual memory Duration of D-side page-walks in cycles event=5,period=200003,umask=1 00 Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress page_walks.i_side_cycles virtual memory Duration of I-side pagewalks in cycles event=5,period=200003,umask=2 00 Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress core_reject_l2q.all cache Requests rejected by the L2Q event=0x31,period=200003 00 Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops dl1.replacement cache L1 Cache evictions for dirty data event=0x51,period=200003,umask=1 00 Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback offcore_response.any_data_rd.any_response cache Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000013091 00 Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_hit cache Counts data reads (demand & prefetch) hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000043091 00 Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hitm_other_core cache Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000003091 00 Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200003091 00 Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.outstanding cache Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000003091 00 Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.any_response cache Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000013010 00 Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_hit cache Counts data reads generated by L1 or L2 prefetchers hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000043010 00 Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hitm_other_core cache Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000003010 00 Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200003010 00 Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.outstanding cache Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000003010 00 Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.any_response cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x00000132b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_hit cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x00000432b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hitm_other_core cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x10000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x02000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.outstanding cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x40000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.any_response cache Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000018000 00 Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_hit cache Counts requests to the uncore subsystem hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000048000 00 Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hitm_other_core cache Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000008000 00 Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_needed cache Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200008000 00 Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.outstanding cache Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000008000 00 Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.any_response cache Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010022 00 Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_hit cache Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040022 00 Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.outstanding cache Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.any_response cache Counts bus lock and split lock requests have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010400 00 Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_hit cache Counts bus lock and split lock requests hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040400 00 Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_miss.hitm_other_core cache Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000400 00 Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_miss.snoop_miss_or_no_snoop_needed cache Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000400 00 Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.outstanding cache Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000400 00 Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.any_response cache Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_hit cache Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hitm_other_core cache Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_needed cache Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.outstanding cache Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.any_response cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_hit cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.hitm_other_core cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.outstanding cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.any_response cache Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010001 00 Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_hit cache Counts demand cacheable data reads of full cache lines hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040001 00 Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hitm_other_core cache Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000001 00 Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000001 00 Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.outstanding cache Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000001 00 Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.any_response cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_hit cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hitm_other_core cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.outstanding cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.any_response cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_hit cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hitm_other_core cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.outstanding cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.any_response cache Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000012000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_hit cache Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000042000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core cache Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.outstanding cache Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.any_response cache Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_hit cache Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core cache Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.outstanding cache Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.any_response cache Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_hit cache Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.outstanding cache Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.any_response cache Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000014800 00 Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_hit cache Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000044800 00 Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.hitm_other_core cache Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000004800 00 Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200004800 00 Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.outstanding cache Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000004800 00 Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.any_response cache Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000011000 00 Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_hit cache Counts data cache lines requests by software prefetch instructions hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000041000 00 Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hitm_other_core cache Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000001000 00 Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200001000 00 Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.outstanding cache Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000001000 00 Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) machine_clears.fp_assist floating point Machine clears due to FP assists event=0xc3,period=20003,umask=4 00 Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result uops_retired.fpdiv floating point Floating point divide uops retired (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=8 00 Counts the number of floating point divide uops retired (Must be precise) machine_clears.memory_ordering memory Machine clears due to memory ordering issue event=0xc3,period=20003,umask=2 00 Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data fetch_stall.itlb_fill_pending_cycles other Cycles the code-fetch stalls and an ITLB miss is outstanding event=0x86,period=200003,umask=1 00 Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation br_misp_retired.non_return_ind pipeline Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xeb 00 Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise) cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003 00 Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter inst_retired.any pipeline Instructions retired (Fixed event) (Must be precise) event=0xc0,period=2000003 00 Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event (Must be precise) inst_retired.prec_dist pipeline Instructions retired - using Reduced Skid PEBS feature (Must be precise) event=0xc0,period=2000003 00 Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired (Must be precise) machine_clears.all pipeline All machine clears event=0xc3,period=20003 00 Counts machine clears for any reason machine_clears.disambiguation pipeline Machine clears due to memory disambiguation event=0xc3,period=20003,umask=8 00 Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address machine_clears.page_fault pipeline Machines clear due to a page fault event=0xc3,period=20003,umask=0x20 00 Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=20003,umask=1 00 Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors uops_retired.idiv pipeline Integer divide uops retired (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=0x10 00 Counts the number of integer divide uops retired (Must be precise) dtlb_load_misses.walk_completed_1gb virtual memory Page walk completed due to a demand load to a 1GB page event=8,period=200003,umask=8 00 Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault dtlb_load_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand load to a 2M or 4M page event=8,period=200003,umask=4 00 Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault dtlb_load_misses.walk_completed_4k virtual memory Page walk completed due to a demand load to a 4K page event=8,period=200003,umask=2 00 Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault dtlb_load_misses.walk_pending virtual memory Page walks outstanding due to a demand load every cycle event=8,period=200003,umask=0x10 00 Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks dtlb_store_misses.walk_completed_1gb virtual memory Page walk completed due to a demand data store to a 1GB page event=0x49,period=2000003,umask=8 00 Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand data store to a 2M or 4M page event=0x49,period=2000003,umask=4 00 Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault dtlb_store_misses.walk_completed_4k virtual memory Page walk completed due to a demand data store to a 4K page event=0x49,period=2000003,umask=2 00 Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault dtlb_store_misses.walk_pending virtual memory Page walks outstanding due to a demand data store every cycle event=0x49,period=200003,umask=0x10 00 Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks ept.walk_pending virtual memory Page walks outstanding due to walking the EPT every cycle event=0x4f,period=200003,umask=0x10 00 Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by number of walks itlb_misses.walk_completed_1gb virtual memory Page walk completed due to an instruction fetch in a 1GB page event=0x85,period=2000003,umask=8 00 Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault itlb_misses.walk_completed_2m_4m virtual memory Page walk completed due to an instruction fetch in a 2M or 4M page event=0x85,period=2000003,umask=4 00 Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault itlb_misses.walk_completed_4k virtual memory Page walk completed due to an instruction fetch in a 4K page event=0x85,period=2000003,umask=2 00 Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault itlb_misses.walk_pending virtual memory Page walks outstanding due to an instruction fetch every cycle event=0x85,period=200003,umask=0x10 00 Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks tlb_flushes.stlb_any virtual memory STLB flushes event=0xbd,period=20003,umask=0x20 00 Counts STLB flushes. The TLBs are flushed on instructions like INVLPG and MOV to CR3 mem_bound_stalls_ifetch.all cache Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss event=0x35,period=1000003,umask=0x7f 00 mem_bound_stalls_ifetch.l2_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache event=0x35,period=1000003,umask=1 00 Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache mem_bound_stalls_ifetch.llc_hit cache Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which hit in the LLC event=0x35,period=1000003,umask=6 00 mem_bound_stalls_ifetch.llc_miss cache Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches event=0x35,period=1000003,umask=0x78 00 mem_bound_stalls_load.all cache Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss event=0x34,period=1000003,umask=0x7f 00 mem_bound_stalls_load.l2_hit cache Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache event=0x34,period=1000003,umask=1 00 Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache mem_bound_stalls_load.llc_hit cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC event=0x34,period=1000003,umask=6 00 mem_bound_stalls_load.llc_miss cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches event=0x34,period=1000003,umask=0x78 00 mem_load_uops_l3_miss_retired.local_dram cache Counts the number of load ops retired that miss the L3 cache and hit in DRAM event=0xd3,period=1000003,umask=1 00 mem_load_uops_retired.l1_hit cache Counts the number of load ops retired that hit the L1 data cache event=0xd1,period=200003,umask=1 00 mem_load_uops_retired.l1_miss cache Counts the number of load ops retired that miss in the L1 data cache event=0xd1,period=200003,umask=0x40 00 mem_load_uops_retired.l2_hit cache Counts the number of load ops retired that hit in the L2 cache event=0xd1,period=200003,umask=2 00 mem_load_uops_retired.l2_miss cache Counts the number of load ops retired that miss in the L2 cache event=0xd1,period=200003,umask=0x80 00 mem_load_uops_retired.l3_hit cache Counts the number of load ops retired that hit in the L3 cache event=0xd1,period=200003,umask=0x1c 00 mem_load_uops_retired.wcb_hit cache Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate event=0xd1,period=200003,umask=0x20 00 mem_uops_retired.all_loads cache Counts the number of load ops retired Supports address when precise event=0xd0,period=200003,umask=0x81 00 mem_uops_retired.all_stores cache Counts the number of store ops retired Supports address when precise event=0xd0,period=200003,umask=0x82 00 mem_uops_retired.load_latency_gt_1024 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x400 00 mem_uops_retired.load_latency_gt_128 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x80 00 mem_uops_retired.load_latency_gt_16 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x10 00 mem_uops_retired.load_latency_gt_2048 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x800 00 mem_uops_retired.load_latency_gt_256 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x100 00 mem_uops_retired.load_latency_gt_32 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x20 00 mem_uops_retired.load_latency_gt_4 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x4 00 mem_uops_retired.load_latency_gt_512 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x200 00 mem_uops_retired.load_latency_gt_64 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x40 00 mem_uops_retired.load_latency_gt_8 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x8 00 mem_uops_retired.lock_loads cache Counts the number of load uops retired that performed one or more locks Supports address when precise event=0xd0,period=200003,umask=0x21 00 mem_uops_retired.split cache Counts the number of memory uops retired that were splits Supports address when precise event=0xd0,period=200003,umask=0x43 00 mem_uops_retired.split_loads cache Counts the number of retired split load uops Supports address when precise event=0xd0,period=200003,umask=0x41 00 mem_uops_retired.split_stores cache Counts the number of retired split store uops Supports address when precise event=0xd0,period=200003,umask=0x42 00 mem_uops_retired.store_latency cache Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES Supports address when precise event=0xd0,period=1000003,umask=6 00 topdown_fe_bound.icache cache Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss event=0x71,period=1000003,umask=0x20 00 arith.fpdiv_active floating point Counts the number of cycles when any of the floating point dividers are active event=0xcd,cmask=1,period=1000003,umask=2 00 fp_flops_retired.all floating point Counts the number of all types of floating point operations per uop with all default weighting event=0xc8,period=1000003,umask=3 00 fp_flops_retired.dp floating point This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64] event=0xc8,period=1000003,umask=1 10 fp_flops_retired.fp32 floating point Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP] event=0xc8,period=1000003,umask=2 00 fp_flops_retired.fp64 floating point Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP] event=0xc8,period=1000003,umask=1 00 fp_flops_retired.sp floating point This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32] event=0xc8,period=1000003,umask=2 10 fp_inst_retired.128b_dp floating point Counts the total number of floating point retired instructions event=0xc7,period=1000003,umask=8 00 fp_inst_retired.128b_sp floating point Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations event=0xc7,period=1000003,umask=4 00 fp_inst_retired.256b_dp floating point Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point event=0xc7,period=1000003,umask=0x20 00 fp_inst_retired.32b_sp floating point Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point event=0xc7,period=1000003,umask=1 00 fp_inst_retired.64b_dp floating point Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point event=0xc7,period=1000003,umask=2 00 uops_retired.fpdiv floating point Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt) event=0xc2,period=2000003,umask=8 00 frontend_retired.itlb_miss frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss event=0xc6,period=1000003,umask=0x10 00 icache.accesses frontend Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump event=0x80,period=200003,umask=3 00 icache.misses frontend Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. - event=0x80,period=200003,umask=2 00 misalign_mem_ref.load_page_split memory Counts misaligned loads that are 4K page splits event=0x13,period=200003,umask=2 00 misalign_mem_ref.store_page_split memory Counts misaligned stores that are 4K page splits event=0x13,period=200003,umask=4 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00002 00 lbr_inserts.any other This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS] event=0xe4,period=1000003,umask=1 10 serialization.c01_ms_scb other Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state event=0x75,period=200003,umask=4 00 arith.div_active pipeline Counts the number of cycles when any of the dividers are active event=0xcd,cmask=1,period=1000003,umask=3 00 br_inst_retired.all_branches pipeline Counts the total number of branch instructions retired for all branch types event=0xc4,period=200003 00 Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for br_inst_retired.cond pipeline Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches event=0xc4,period=200003,umask=0x7e 00 br_inst_retired.cond_taken pipeline Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired event=0xc4,period=200003,umask=0xfe 00 br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return event=0xc4,period=200003,umask=0xbf 00 br_inst_retired.indirect pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired event=0xc4,period=200003,umask=0xeb 00 br_inst_retired.indirect_call pipeline Counts the number of near indirect CALL branch instructions retired event=0xc4,period=200003,umask=0xfb 00 br_inst_retired.ind_call pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL event=0xc4,period=200003,umask=0xfb 10 br_inst_retired.near_call pipeline Counts the number of near CALL branch instructions retired event=0xc4,period=200003,umask=0xf9 00 br_inst_retired.near_return pipeline Counts the number of near RET branch instructions retired event=0xc4,period=200003,umask=0xf7 00 br_misp_retired.all_branches pipeline Counts the total number of mispredicted branch instructions retired for all branch types event=0xc5,period=200003 00 Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path br_misp_retired.cond pipeline Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired event=0xc5,period=200003,umask=0x7e 00 br_misp_retired.cond_taken pipeline Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired event=0xc5,period=200003,umask=0xfe 00 br_misp_retired.indirect pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired event=0xc5,period=200003,umask=0xeb 00 br_misp_retired.indirect_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired event=0xc5,period=200003,umask=0xfb 00 br_misp_retired.near_taken pipeline Counts the number of mispredicted near taken branch instructions retired event=0xc5,period=200003,umask=0x80 00 br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired event=0xc5,period=200003,umask=0xf7 00 cpu_clk_unhalted.core pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 cpu_clk_unhalted.core_p pipeline Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P] event=0x3c,period=2000003 00 cpu_clk_unhalted.ref_tsc pipeline Fixed Counter: Counts the number of unhalted reference clock cycles event=0,period=2000003,umask=3 00 cpu_clk_unhalted.thread pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P] event=0x3c,period=2000003 00 inst_retired.any pipeline Fixed Counter: Counts the number of instructions retired (Precise event) event=0xc0,period=2000003 00 inst_retired.any_p pipeline Counts the number of instructions retired event=0xc0,period=2000003 00 ld_blocks.address_alias pipeline Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check event=3,period=1000003,umask=4 00 ld_blocks.data_unknown pipeline Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready event=3,period=1000003,umask=1 00 ld_blocks.store_forward pipeline Counts the number of retired loads that are blocked because its address partially overlapped with an older store event=3,period=1000003,umask=2 00 misc_retired.lbr_inserts pipeline Counts the number of Last Branch Record (LBR) entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY] event=0xe4,period=1000003,umask=1 00 topdown_bad_speculation.all pipeline Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P] event=0x73,period=1000003 00 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P] topdown_bad_speculation.all_p pipeline Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL] event=0x73,period=1000003 00 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL] topdown_bad_speculation.fastnuke pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes event=0x73,period=1000003,umask=2 00 topdown_bad_speculation.mispredict pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict event=0x73,period=1000003,umask=4 00 topdown_be_bound.all pipeline Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P] event=0x74,period=1000003 00 topdown_be_bound.alloc_restrictions pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions event=0x74,period=1000003,umask=1 00 topdown_be_bound.all_p pipeline Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL] event=0x74,period=1000003 00 topdown_be_bound.mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block event=0x74,period=1000003,umask=2 00 topdown_be_bound.non_mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. ) event=0x74,period=1000003,umask=8 00 topdown_be_bound.register pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST) event=0x74,period=1000003,umask=0x20 00 topdown_be_bound.reorder_buffer pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full event=0x74,period=1000003,umask=0x40 00 topdown_be_bound.serialization pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb event=0x74,period=1000003,umask=0x10 00 topdown_fe_bound.all pipeline Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL_P] event=0x71,period=1000003 00 topdown_fe_bound.all_p pipeline Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL] event=0x71,period=1000003 00 topdown_fe_bound.branch_detect pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear event=0x71,period=1000003,umask=2 00 topdown_fe_bound.branch_resteer pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear event=0x71,period=1000003,umask=0x40 00 topdown_fe_bound.cisc pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to ms event=0x71,period=1000003,umask=1 00 topdown_fe_bound.decode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall event=0x71,period=1000003,umask=8 00 topdown_fe_bound.frontend_latency pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses event=0x71,period=1000003,umask=0x72 00 topdown_fe_bound.itlb pipeline This event is deprecated. [This event is alias to TOPDOWN_FE_BOUND.ITLB_MISS] event=0x71,period=1000003,umask=0x10 10 topdown_fe_bound.itlb_miss pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss [This event is alias to TOPDOWN_FE_BOUND.ITLB] event=0x71,period=1000003,umask=0x10 00 topdown_fe_bound.other pipeline Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall event=0x71,period=1000003,umask=0x80 00 topdown_fe_bound.predecode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong event=0x71,period=1000003,umask=4 00 topdown_retiring.all pipeline Counts the number of consumed retirement slots. [This event is alias to TOPDOWN_RETIRING.ALL_P] event=0x72,period=1000003 00 topdown_retiring.all_p pipeline Counts the number of consumed retirement slots. [This event is alias to TOPDOWN_RETIRING.ALL] event=0x72,period=1000003 00 uops_issued.any pipeline Counts the number of uops issued by the front end every cycle event=0xe,period=1000003 00 Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued uops_retired.all pipeline Counts the total number of uops retired event=0xc2,period=2000003 00 uops_retired.idiv pipeline Counts the number of integer divide uops retired event=0xc2,period=2000003,umask=0x10 00 uops_retired.ms pipeline Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows event=0xc2,period=2000003,umask=1 00 uops_retired.x87 pipeline Counts the number of x87 uops retired, includes those in ms flows event=0xc2,period=2000003,umask=2 00 uncore_chacms unc_chacms_clockticks uncore cache Clockticks for CMS units attached to CHA event=1 01 unc_cha_clockticks uncore cache Number of CHA clock cycles while the event is enabled event=1 01 Clockticks of the uncore caching and home agent (CHA) unc_cha_distress_asserted.dpt_any uncore cache Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering) event=0x59,umask=3 01 unc_cha_distress_asserted.dpt_irq uncore cache Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering) event=0x59,umask=1 01 unc_cha_distress_asserted.dpt_tor uncore cache Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering) event=0x59,umask=2 01 unc_cha_imc_writes_count.full uncore cache Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels event=0x5b,umask=1 01 unc_cha_imc_writes_count.full_priority uncore cache CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller event=0x5b,umask=4 01 unc_cha_imc_writes_count.partial uncore cache CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller event=0x5b,umask=2 01 unc_cha_imc_writes_count.partial_priority uncore cache CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller event=0x5b,umask=8 01 unc_cha_llc_lookup.code uncore cache Cache Lookups: CRd Requests event=0x34,umask=0x1bd0ff 01 Cache Lookups : CRd Requests unc_cha_llc_lookup.data_rd uncore cache Cache Lookups: Read Requests and Read Prefetches event=0x34,umask=0x1bc1ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_all uncore cache Cache Lookups: Read Requests, Read Prefetches, and Snoops event=0x34,umask=0x1fc1ff 01 Cache Lookups : Data Reads unc_cha_llc_lookup.data_read_local uncore cache Cache Lookups: Read Requests to Locally Homed Memory event=0x34,umask=0x841ff 01 Cache Lookups : Demand Data Reads, Core and LLC prefetches unc_cha_llc_lookup.data_read_miss uncore cache Cache Lookups: Read Requests, Read Prefetches, and Snoops which miss the Cache event=0x34,umask=0x1fc101 01 Cache Lookups : Data Read Misses unc_cha_llc_lookup.locally_homed_address uncore cache Cache Lookups: All Requests to Locally Homed Memory event=0x34,umask=0xbdfff 01 Cache Lookups : Transactions homed locally unc_cha_llc_lookup.local_code uncore cache Cache Lookups: Code Read Requests and Code Read Prefetches to Locally Homed Memory event=0x34,umask=0x19d0ff 01 Cache Lookups : CRd Requests unc_cha_llc_lookup.local_data_rd uncore cache Cache Lookups: Read Requests and Read Prefetches to Locally Homed Memory event=0x34,umask=0x19c1ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_dmnd_code uncore cache Cache Lookups: Code Read Requests to Locally Homed Memory event=0x34,umask=0x1850ff 01 Cache Lookups : CRd Requests unc_cha_llc_lookup.local_dmnd_data_rd uncore cache Cache Lookups: Read Requests to Locally Homed Memory event=0x34,umask=0x1841ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_dmnd_rfo uncore cache Cache Lookups: RFO Requests to Locally Homed Memory event=0x34,umask=0x1848ff 01 Cache Lookups : RFO Requests unc_cha_llc_lookup.local_llc_pf uncore cache Cache Lookups: LLC Prefetch Requests to Locally Homed Memory event=0x34,umask=0x189dff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf uncore cache Cache Lookups: All Prefetches to Locally Homed Memory event=0x34,umask=0x199dff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf_code uncore cache Cache Lookups: Code Prefetches to Locally Homed Memory event=0x34,umask=0x1910ff 01 Cache Lookups : CRd Requests unc_cha_llc_lookup.local_pf_data_rd uncore cache Cache Lookups: Read Prefetches to Locally Homed Memory event=0x34,umask=0x1981ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf_rfo uncore cache Cache Lookups: RFO Prefetches to Locally Homed Memory event=0x34,umask=0x1908ff 01 Cache Lookups : RFO Requests unc_cha_llc_lookup.local_rfo uncore cache Cache Lookups: RFO Requests and RFO Prefetches to Locally Homed Memory event=0x34,umask=0x19c8ff 01 Cache Lookups : RFO Requests unc_cha_llc_lookup.rfo uncore cache Cache Lookups: All RFO and RFO Prefetches event=0x34,umask=0x1bc8ff 01 Cache Lookups : All RFOs - Demand and Prefetches unc_cha_llc_lookup.rfo_local uncore cache Cache Lookups: RFO Requests and RFO Prefetches to Locally Homed Memory event=0x34,umask=0x9c8ff 01 Cache Lookups : Locally HOMed RFOs - Demand and Prefetches unc_cha_llc_lookup.write_local uncore cache Cache Lookups: Writes to Locally Homed Memory (includes writebacks from L1/L2) event=0x34,umask=0x842ff 01 Cache Lookups : Writes unc_cha_llc_victims.all uncore cache Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0xf 01 Lines Victimized : All Lines Victimized unc_cha_llc_victims.ia uncore cache Lines Victimized : IA traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x20 01 unc_cha_llc_victims.io uncore cache Lines Victimized : IO traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x10 01 unc_cha_llc_victims.local_all uncore cache Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x200f 01 Lines Victimized : Local - All Lines unc_cha_llc_victims.local_e uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x2002 01 Lines Victimized : Local - Lines in E State unc_cha_llc_victims.local_f uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x2008 01 Lines Victimized : Local - Lines in F State unc_cha_llc_victims.local_m uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x2001 01 Lines Victimized : Local - Lines in M State unc_cha_llc_victims.local_s uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x2004 01 Lines Victimized : Local - Lines in S State unc_cha_llc_victims.total_e uncore cache Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=2 01 Lines Victimized : Lines in E state unc_cha_llc_victims.total_m uncore cache Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=1 01 Lines Victimized : Lines in M state unc_cha_llc_victims.total_s uncore cache Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=4 01 Lines Victimized : Lines in S State unc_cha_misc.rfo_hit_s uncore cache Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state event=0x39,umask=8 01 Cbo Misc : RFO HitS unc_cha_osb.local_invitoe uncore cache OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB event=0x55,umask=1 01 unc_cha_osb.local_read uncore cache OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB event=0x55,umask=2 01 unc_cha_osb.off_pwrheuristic uncore cache OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB event=0x55,umask=0x20 01 unc_cha_osb.rfo_hits_snp_bcast uncore cache OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB event=0x55,umask=0x10 01 unc_cha_requests.invitoe uncore cache Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA event=0x50,umask=0x30 01 HA Read and Write Requests : InvalItoE unc_cha_requests.invitoe_local uncore cache Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA event=0x50,umask=0x10 01 unc_cha_requests.reads uncore cache Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) event=0x50,umask=3 01 HA Read and Write Requests : Reads unc_cha_requests.reads_local uncore cache Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) event=0x50,umask=1 01 unc_cha_requests.writes uncore cache Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc event=0x50,umask=0xc 01 HA Read and Write Requests : Writes unc_cha_requests.writes_local uncore cache Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc event=0x50,umask=4 01 unc_cha_tor_inserts.all uncore cache All TOR Inserts event=0x35,umask=0xc001ffff 01 TOR Inserts : All unc_cha_tor_inserts.ia uncore cache All locally initiated requests from IA Cores event=0x35,umask=0xc001ff01 01 TOR Inserts : All requests from iA Cores unc_cha_tor_inserts.ia_clflush uncore cache CLFlush events that are initiated from the Core event=0x35,umask=0xc8c7ff01 01 TOR Inserts : CLFlushes issued by iA Cores unc_cha_tor_inserts.ia_clflushopt uncore cache CLFlushOpt events that are initiated from the Core event=0x35,umask=0xc8d7ff01 01 TOR Inserts : CLFlushOpts issued by iA Cores unc_cha_tor_inserts.ia_crd uncore cache Code read from local IA that miss the cache event=0x35,umask=0xc80fff01 01 TOR Inserts : CRDs issued by iA Cores unc_cha_tor_inserts.ia_crd_pref uncore cache Code read prefetch from local IA that miss the cache event=0x35,umask=0xc88fff01 01 TOR Inserts; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd_opt uncore cache Data read opt from local IA that miss the cache event=0x35,umask=0xc827ff01 01 TOR Inserts : DRd_Opts issued by iA Cores unc_cha_tor_inserts.ia_drd_opt_pref uncore cache Data read opt prefetch from local IA that miss the cache event=0x35,umask=0xc8a7ff01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores unc_cha_tor_inserts.ia_hit uncore cache All locally initiated requests from IA Cores which hit the cache event=0x35,umask=0xc001fd01 01 TOR Inserts : All requests from iA Cores that Hit the LLC unc_cha_tor_inserts.ia_hit_crd uncore cache Code read from local IA that hit the cache event=0x35,umask=0xc80ffd01 01 TOR Inserts : CRds issued by iA Cores that Hit the LLC unc_cha_tor_inserts.ia_hit_crd_pref uncore cache Code read prefetch from local IA that hit the cache event=0x35,umask=0xc88ffd01 01 TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_drd_opt uncore cache Data read opt from local IA that hit the cache event=0x35,umask=0xc827fd01 01 TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_drd_opt_pref uncore cache Data read opt prefetch from local IA that hit the cache event=0x35,umask=0xc8a7fd01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_itom uncore cache ItoM requests from local IA cores that hit the cache event=0x35,umask=0xcc47fd01 01 TOR Inserts : ItoMs issued by iA Cores that Hit LLC unc_cha_tor_inserts.ia_hit_llcprefcode uncore cache Last level cache prefetch code read from local IA that hit the cache event=0x35,umask=0xcccffd01 01 TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_llcprefdata uncore cache Last level cache prefetch data read from local IA that hit the cache event=0x35,umask=0xccd7fd01 01 TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache Last level cache prefetch read for ownership from local IA that hit the cache event=0x35,umask=0xccc7fd01 01 TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_rfo uncore cache Read for ownership from local IA that hit the cache event=0x35,umask=0xc807fd01 01 TOR Inserts : RFOs issued by iA Cores that Hit the LLC unc_cha_tor_inserts.ia_hit_rfo_pref uncore cache Read for ownership prefetch from local IA that hit the cache event=0x35,umask=0xc887fd01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC unc_cha_tor_inserts.ia_itom uncore cache ItoM events that are initiated from the Core event=0x35,umask=0xcc47ff01 01 TOR Inserts : ItoMs issued by iA Cores unc_cha_tor_inserts.ia_itomcachenear uncore cache ItoMCacheNear requests from local IA cores event=0x35,umask=0xcd47ff01 01 TOR Inserts : ItoMCacheNears issued by iA Cores unc_cha_tor_inserts.ia_llcprefcode uncore cache Last level cache prefetch code read from local IA event=0x35,umask=0xcccfff01 01 TOR Inserts : LLCPrefCode issued by iA Cores unc_cha_tor_inserts.ia_llcprefdata uncore cache Last level cache prefetch data read from local IA event=0x35,umask=0xccd7ff01 01 TOR Inserts : LLCPrefData issued by iA Cores unc_cha_tor_inserts.ia_llcprefrfo uncore cache Last level cache prefetch read for ownership from local IA that miss the cache event=0x35,umask=0xccc7ff01 01 TOR Inserts : LLCPrefRFO issued by iA Cores unc_cha_tor_inserts.ia_miss uncore cache All locally initiated requests from IA Cores which miss the cache event=0x35,umask=0xc001fe01 01 TOR Inserts : All requests from iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_crd uncore cache Code read from local IA that miss the cache event=0x35,umask=0xc80ffe01 01 TOR Inserts : CRds issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_crd_local uncore cache CRDs from local IA cores to locally homed memory event=0x35,umask=0xc80efe01 01 TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_crd_pref uncore cache Code read prefetch from local IA that miss the cache event=0x35,umask=0xc88ffe01 01 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_crd_pref_local uncore cache CRD Prefetches from local IA cores to locally homed memory event=0x35,umask=0xc88efe01 01 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_opt uncore cache Data read opt from local IA that miss the cache event=0x35,umask=0xc827fe01 01 TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_drd_opt_local uncore cache Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd_Opt, and which target local memory event=0x35,umask=0xc826fe01 01 TOR Inserts : DRd_Opt issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_opt_pref uncore cache Data read opt prefetch from local IA that miss the cache event=0x35,umask=0xc8a7fe01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_drd_opt_pref_local uncore cache Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target local memory event=0x35,umask=0xc8a6fe01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_itom uncore cache ItoM requests from local IA cores that miss the cache event=0x35,umask=0xcc47fe01 01 TOR Inserts : ItoMs issued by iA Cores that Missed LLC unc_cha_tor_inserts.ia_miss_llcprefcode uncore cache Last level cache prefetch code read from local IA that miss the cache event=0x35,umask=0xcccffe01 01 TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_llcprefdata uncore cache Last level cache prefetch data read from local IA that miss the cache event=0x35,umask=0xccd7fe01 01 TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache Last level cache prefetch read for ownership from local IA that miss the cache event=0x35,umask=0xccc7fe01 01 TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_local_wcilf_ddr uncore cache WCILF requests from local IA cores to locally homed DDR addresses that miss the cache event=0x35,umask=0xc8668601 01 TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_local_wcil_ddr uncore cache WCIL requests from local IA cores to locally homed DDR addresses that miss the cache event=0x35,umask=0xc86e8601 01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_rfo uncore cache Read for ownership from local IA that miss the cache event=0x35,umask=0xc807fe01 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_rfo_local uncore cache Read for ownership from local IA that miss the cache event=0x35,umask=0xc806fe01 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_rfo_pref uncore cache Read for ownership prefetch from local IA that miss the cache event=0x35,umask=0xc887fe01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_rfo_pref_local uncore cache Read for ownership prefetch from local IA that miss the cache event=0x35,umask=0xc886fe01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_ucrdf uncore cache UCRDF requests from local IA cores that miss the cache event=0x35,umask=0xc877de01 01 TOR Inserts : UCRdFs issued by iA Cores that Missed LLC unc_cha_tor_inserts.ia_miss_wcil uncore cache WCIL requests from a local IA core that miss the cache event=0x35,umask=0xc86ffe01 01 TOR Inserts : WCiLs issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_wcilf uncore cache WCILF requests from local IA core that miss the cache event=0x35,umask=0xc867fe01 01 TOR Inserts : WCiLF issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_wcilf_ddr uncore cache WCILF requests from local IA cores to DDR homed addresses which miss the cache event=0x35,umask=0xc8678601 01 TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC unc_cha_tor_inserts.ia_miss_wcil_ddr uncore cache WCIL requests from local IA cores to DDR homed addresses which miss the cache event=0x35,umask=0xc86f8601 01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC unc_cha_tor_inserts.ia_miss_wil uncore cache WIL requests from local IA cores that miss the cache event=0x35,umask=0xc87fde01 01 TOR Inserts : WiLs issued by iA Cores that Missed LLC unc_cha_tor_inserts.ia_rfo uncore cache Read for ownership from local IA that miss the cache event=0x35,umask=0xc807ff01 01 TOR Inserts : RFOs issued by iA Cores unc_cha_tor_inserts.ia_rfo_pref uncore cache Read for ownership prefetch from local IA that miss the cache event=0x35,umask=0xc887ff01 01 TOR Inserts : RFO_Prefs issued by iA Cores unc_cha_tor_inserts.ia_specitom uncore cache SpecItoM events that are initiated from the Core event=0x35,umask=0xcc57ff01 01 TOR Inserts : SpecItoMs issued by iA Cores unc_cha_tor_inserts.ia_wbeftoe uncore cache WbEFtoEs issued by iA Cores. (Non Modified Write Backs) event=0x35,umask=0xcc3fff01 01 TOR Inserts : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_inserts.ia_wbeftoi uncore cache WbEFtoIs issued by iA Cores . (Non Modified Write Backs) event=0x35,umask=0xcc37ff01 01 TOR Inserts : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_inserts.ia_wbmtoe uncore cache WbMtoEs issued by iA Cores . (Modified Write Backs) event=0x35,umask=0xcc2fff01 01 TOR Inserts : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_inserts.ia_wbmtoi uncore cache WbMtoI requests from local IA cores event=0x35,umask=0xcc27ff01 01 TOR Inserts : WbMtoIs issued by iA Cores unc_cha_tor_inserts.ia_wbstoi uncore cache WbStoIs issued by iA Cores . (Non Modified Write Backs) event=0x35,umask=0xcc67ff01 01 TOR Inserts : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_inserts.ia_wcil uncore cache WCIL requests from a local IA core event=0x35,umask=0xc86fff01 01 TOR Inserts : WCiLs issued by iA Cores unc_cha_tor_inserts.ia_wcilf uncore cache WCILF requests from local IA core event=0x35,umask=0xc867ff01 01 TOR Inserts : WCiLF issued by iA Cores unc_cha_tor_inserts.io uncore cache All TOR inserts from local IO devices event=0x35,umask=0xc001ff04 01 TOR Inserts : All requests from IO Devices unc_cha_tor_inserts.io_clflush uncore cache CLFlush requests from IO devices event=0x35,umask=0xc8c3ff04 01 TOR Inserts : CLFlushes issued by IO Devices unc_cha_tor_inserts.io_hit uncore cache All TOR inserts from local IO devices which hit the cache event=0x35,umask=0xc001fd04 01 TOR Inserts : All requests from IO Devices that hit the LLC unc_cha_tor_inserts.io_hit_itom uncore cache ItoMs from local IO devices which hit the cache event=0x35,umask=0xcc43fd04 01 TOR Inserts : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_inserts.io_hit_itomcachenear uncore cache ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC event=0x35,umask=0xcd43fd04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC unc_cha_tor_inserts.io_hit_pcirdcur uncore cache PCIRDCURs issued by IO devices which hit the LLC event=0x35,umask=0xc8f3fd04 01 TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC unc_cha_tor_inserts.io_hit_rfo uncore cache RFOs from local IO devices which hit the cache event=0x35,umask=0xc803fd04 01 TOR Inserts : RFOs issued by IO Devices that hit the LLC unc_cha_tor_inserts.io_itom uncore cache All TOR ItoM inserts from local IO devices event=0x35,umask=0xcc43ff04 01 TOR Inserts : ItoMs issued by IO Devices unc_cha_tor_inserts.io_itomcachenear uncore cache ItoMCacheNears, indicating a partial write request, from IO Devices event=0x35,umask=0xcd43ff04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices unc_cha_tor_inserts.io_miss uncore cache All TOR inserts from local IO devices which miss the cache event=0x35,umask=0xc001fe04 01 TOR Inserts : All requests from IO Devices that missed the LLC unc_cha_tor_inserts.io_miss_itom uncore cache All TOR ItoM inserts from local IO devices which miss the cache event=0x35,umask=0xcc43fe04 01 TOR Inserts : ItoMs issued by IO Devices that missed the LLC unc_cha_tor_inserts.io_miss_itomcachenear uncore cache ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC event=0x35,umask=0xcd43fe04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC unc_cha_tor_inserts.io_miss_pcirdcur uncore cache PCIRDCURs issued by IO devices which miss the LLC event=0x35,umask=0xc8f3fe04 01 TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC unc_cha_tor_inserts.io_miss_rfo uncore cache All TOR RFO inserts from local IO devices which miss the cache event=0x35,umask=0xc803fe04 01 TOR Inserts : RFOs issued by IO Devices that missed the LLC unc_cha_tor_inserts.io_pcirdcur uncore cache PCIRDCURs issued by IO devices event=0x35,umask=0xc8f3ff04 01 TOR Inserts : PCIRdCurs issued by IO Devices unc_cha_tor_inserts.io_rfo uncore cache RFOs from local IO devices event=0x35,umask=0xc803ff04 01 TOR Inserts : RFOs issued by IO Devices unc_cha_tor_inserts.io_wbmtoi uncore cache WBMtoI requests from IO devices event=0x35,umask=0xcc23ff04 01 TOR Inserts : WbMtoIs issued by IO Devices unc_cha_tor_inserts.llc_or_sf_evictions uncore cache TOR Inserts for SF or LLC Evictions event=0x35,umask=0xc001ff02 01 TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.loc_all uncore cache All locally initiated requests event=0x35,umask=0xc000ff05 01 TOR Inserts : All from Local iA and IO unc_cha_tor_inserts.loc_ia uncore cache All from Local iA event=0x35,umask=0xc000ff01 01 TOR Inserts : All from Local iA unc_cha_tor_inserts.loc_io uncore cache All from Local IO event=0x35,umask=0xc000ff04 01 TOR Inserts : All from Local IO unc_cha_tor_occupancy.all uncore cache Occupancy for all TOR entries event=0x36,umask=0xc001ffff 01 TOR Occupancy : All unc_cha_tor_occupancy.ia uncore cache TOR Occupancy for All locally initiated requests from IA Cores event=0x36,umask=0xc001ff01 01 TOR Occupancy : All requests from iA Cores unc_cha_tor_occupancy.ia_clflush uncore cache TOR Occupancy for CLFlush events that are initiated from the Core event=0x36,umask=0xc8c7ff01 01 TOR Occupancy : CLFlushes issued by iA Cores unc_cha_tor_occupancy.ia_clflushopt uncore cache TOR Occupancy for CLFlushOpt events that are initiated from the Core event=0x36,umask=0xc8d7ff01 01 TOR Occupancy : CLFlushOpts issued by iA Cores unc_cha_tor_occupancy.ia_crd uncore cache TOR Occupancy for Code read from local IA that miss the cache event=0x36,umask=0xc80fff01 01 TOR Occupancy : CRDs issued by iA Cores unc_cha_tor_occupancy.ia_crd_pref uncore cache TOR Occupancy for Code read prefetch from local IA that miss the cache event=0x36,umask=0xc88fff01 01 TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd_opt uncore cache TOR Occupancy for Data read opt from local IA that miss the cache event=0x36,umask=0xc827ff01 01 TOR Occupancy : DRd_Opts issued by iA Cores unc_cha_tor_occupancy.ia_drd_opt_pref uncore cache TOR Occupancy for Data read opt prefetch from local IA that miss the cache event=0x36,umask=0xc8a7ff01 01 TOR Occupancy : DRd_Opt_Prefs issued by iA Cores unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy for All locally initiated requests from IA Cores which hit the cache event=0x36,umask=0xc001fd01 01 TOR Occupancy : All requests from iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy for Code read from local IA that hit the cache event=0x36,umask=0xc80ffd01 01 TOR Occupancy : CRds issued by iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_hit_crd_pref uncore cache TOR Occupancy for Code read prefetch from local IA that hit the cache event=0x36,umask=0xc88ffd01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_drd_opt uncore cache TOR Occupancy for Data read opt from local IA that hit the cache event=0x36,umask=0xc827fd01 01 TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_drd_opt_pref uncore cache TOR Occupancy for Data read opt prefetch from local IA that hit the cache event=0x36,umask=0xc8a7fd01 01 TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_itom uncore cache TOR Occupancy for ItoM requests from local IA cores that hit the cache event=0x36,umask=0xcc47fd01 01 TOR Occupancy : ItoMs issued by iA Cores that Hit LLC unc_cha_tor_occupancy.ia_hit_llcprefcode uncore cache TOR Occupancy for Last level cache prefetch code read from local IA that hit the cache event=0x36,umask=0xcccffd01 01 TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_llcprefdata uncore cache TOR Occupancy for Last level cache prefetch data read from local IA that hit the cache event=0x36,umask=0xccd7fd01 01 TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy for Last level cache prefetch read for ownership from local IA that hit the cache event=0x36,umask=0xccc7fd01 01 TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy for Read for ownership from local IA that hit the cache event=0x36,umask=0xc807fd01 01 TOR Occupancy : RFOs issued by iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_hit_rfo_pref uncore cache TOR Occupancy for Read for ownership prefetch from local IA that hit the cache event=0x36,umask=0xc887fd01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_itom uncore cache TOR Occupancy for ItoM events that are initiated from the Core event=0x36,umask=0xcc47ff01 01 TOR Occupancy : ItoMs issued by iA Cores unc_cha_tor_occupancy.ia_itomcachenear uncore cache TOR Occupancy for ItoMCacheNear requests from local IA cores event=0x36,umask=0xcd47ff01 01 TOR Occupancy : ItoMCacheNears issued by iA Cores unc_cha_tor_occupancy.ia_llcprefcode uncore cache TOR Occupancy for Last level cache prefetch code read from local IA event=0x36,umask=0xcccfff01 01 TOR Occupancy : LLCPrefCode issued by iA Cores unc_cha_tor_occupancy.ia_llcprefdata uncore cache TOR Occupancy for Last level cache prefetch data read from local IA event=0x36,umask=0xccd7ff01 01 TOR Occupancy : LLCPrefData issued by iA Cores unc_cha_tor_occupancy.ia_llcprefrfo uncore cache TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache event=0x36,umask=0xccc7ff01 01 TOR Occupancy : LLCPrefRFO issued by iA Cores unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy for All locally initiated requests from IA Cores which miss the cache event=0x36,umask=0xc001fe01 01 TOR Occupancy : All requests from iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy for Code read from local IA that miss the cache event=0x36,umask=0xc80ffe01 01 TOR Occupancy : CRds issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_crd_local uncore cache TOR Occupancy for CRDs from local IA cores to locally homed memory event=0x36,umask=0xc80efe01 01 TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_crd_pref uncore cache TOR Occupancy for Code read prefetch from local IA that miss the cache event=0x36,umask=0xc88ffe01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_crd_pref_local uncore cache TOR Occupancy for CRD Prefetches from local IA cores to locally homed memory event=0x36,umask=0xc88efe01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_opt uncore cache TOR Occupancy for Data read opt from local IA that miss the cache event=0x36,umask=0xc827fe01 01 TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC unc_cha_tor_occupancy.ia_miss_drd_opt_pref uncore cache TOR Occupancy for Data read opt prefetch from local IA that miss the cache event=0x36,umask=0xc8a7fe01 01 TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC unc_cha_tor_occupancy.ia_miss_itom uncore cache TOR Occupancy for ItoM requests from local IA cores that miss the cache event=0x36,umask=0xcc47fe01 01 TOR Occupancy : ItoMs issued by iA Cores that Missed LLC unc_cha_tor_occupancy.ia_miss_llcprefcode uncore cache TOR Occupancy for Last level cache prefetch code read from local IA that miss the cache event=0x36,umask=0xcccffe01 01 TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC unc_cha_tor_occupancy.ia_miss_llcprefdata uncore cache TOR Occupancy for Last level cache prefetch data read from local IA that miss the cache event=0x36,umask=0xccd7fe01 01 TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache event=0x36,umask=0xccc7fe01 01 TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC unc_cha_tor_occupancy.ia_miss_local_wcilf_ddr uncore cache TOR Occupancy for WCILF requests from local IA cores to locally homed DDR addresses that miss the cache event=0x36,umask=0xc8668601 01 TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_local_wcil_ddr uncore cache TOR Occupancy for WCIL requests from local IA cores to locally homed DDR addresses that miss the cache event=0x36,umask=0xc86e8601 01 TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy for Read for ownership from local IA that miss the cache event=0x36,umask=0xc807fe01 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_rfo_local uncore cache TOR Occupancy for Read for ownership from local IA that miss the cache event=0x36,umask=0xc806fe01 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_rfo_pref uncore cache TOR Occupancy for Read for ownership prefetch from local IA that miss the cache event=0x36,umask=0xc887fe01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_rfo_pref_local uncore cache TOR Occupancy for Read for ownership prefetch from local IA that miss the cache event=0x36,umask=0xc886fe01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_ucrdf uncore cache TOR Occupancy for UCRDF requests from local IA cores that miss the cache event=0x36,umask=0xc877de01 01 TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC unc_cha_tor_occupancy.ia_miss_wcil uncore cache TOR Occupancy for WCIL requests from a local IA core that miss the cache event=0x36,umask=0xc86ffe01 01 TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_wcilf uncore cache TOR Occupancy for WCILF requests from local IA core that miss the cache event=0x36,umask=0xc867fe01 01 TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_wcilf_ddr uncore cache TOR Occupancy for WCILF requests from local IA cores to DDR homed addresses which miss the cache event=0x36,umask=0xc8678601 01 TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC unc_cha_tor_occupancy.ia_miss_wcil_ddr uncore cache TOR Occupancy for WCIL requests from local IA cores to DDR homed addresses which miss the cache event=0x36,umask=0xc86f8601 01 TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC unc_cha_tor_occupancy.ia_miss_wil uncore cache TOR Occupancy for WIL requests from local IA cores that miss the cache event=0x36,umask=0xc87fde01 01 TOR Occupancy : WiLs issued by iA Cores that Missed LLC unc_cha_tor_occupancy.ia_rfo uncore cache TOR Occupancy for Read for ownership from local IA that miss the cache event=0x36,umask=0xc807ff01 01 TOR Occupancy : RFOs issued by iA Cores unc_cha_tor_occupancy.ia_rfo_pref uncore cache TOR Occupancy for Read for ownership prefetch from local IA that miss the cache event=0x36,umask=0xc887ff01 01 TOR Occupancy : RFO_Prefs issued by iA Cores unc_cha_tor_occupancy.ia_specitom uncore cache TOR Occupancy for SpecItoM events that are initiated from the Core event=0x36,umask=0xcc57ff01 01 TOR Occupancy : SpecItoMs issued by iA Cores unc_cha_tor_occupancy.ia_wbmtoi uncore cache TOR Occupancy for WbMtoI requests from local IA cores event=0x36,umask=0xcc27ff01 01 TOR Occupancy : WbMtoIs issued by iA Cores unc_cha_tor_occupancy.ia_wcil uncore cache TOR Occupancy for WCIL requests from a local IA core event=0x36,umask=0xc86fff01 01 TOR Occupancy : WCiLs issued by iA Cores unc_cha_tor_occupancy.ia_wcilf uncore cache TOR Occupancy for WCILF requests from local IA core event=0x36,umask=0xc867ff01 01 TOR Occupancy : WCiLF issued by iA Cores unc_cha_tor_occupancy.io uncore cache TOR Occupancy for All TOR inserts from local IO devices event=0x36,umask=0xc001ff04 01 TOR Occupancy : All requests from IO Devices unc_cha_tor_occupancy.io_clflush uncore cache TOR Occupancy for CLFlush requests from IO devices event=0x36,umask=0xc8c3ff04 01 TOR Occupancy : CLFlushes issued by IO Devices unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy for All TOR inserts from local IO devices which hit the cache event=0x36,umask=0xc001fd04 01 TOR Occupancy : All requests from IO Devices that hit the LLC unc_cha_tor_occupancy.io_hit_itom uncore cache TOR Occupancy for ItoMs from local IO devices which hit the cache event=0x36,umask=0xcc43fd04 01 TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_occupancy.io_hit_itomcachenear uncore cache TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC event=0x36,umask=0xcd43fd04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC unc_cha_tor_occupancy.io_hit_pcirdcur uncore cache TOR Occupancy for PCIRDCURs issued by IO devices which hit the LLC event=0x36,umask=0xc8f3fd04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC unc_cha_tor_occupancy.io_hit_rfo uncore cache TOR Occupancy for RFOs from local IO devices which hit the cache event=0x36,umask=0xc803fd04 01 TOR Occupancy : RFOs issued by IO Devices that hit the LLC unc_cha_tor_occupancy.io_itom uncore cache TOR Occupancy for All TOR ItoM inserts from local IO devices event=0x36,umask=0xcc43ff04 01 TOR Occupancy : ItoMs issued by IO Devices unc_cha_tor_occupancy.io_itomcachenear uncore cache TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices event=0x36,umask=0xcd43ff04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy for All TOR inserts from local IO devices which miss the cache event=0x36,umask=0xc001fe04 01 TOR Occupancy : All requests from IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy for All TOR ItoM inserts from local IO devices which miss the cache event=0x36,umask=0xcc43fe04 01 TOR Occupancy : ItoMs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_itomcachenear uncore cache TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC event=0x36,umask=0xcd43fe04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_pcirdcur uncore cache TOR Occupancy for PCIRDCURs issued by IO devices which miss the LLC event=0x36,umask=0xc8f3fe04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy for All TOR RFO inserts from local IO devices which miss the cache event=0x36,umask=0xc803fe04 01 TOR Occupancy : RFOs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_pcirdcur uncore cache TOR Occupancy for PCIRDCURs issued by IO devices event=0x36,umask=0xc8f3ff04 01 TOR Occupancy : PCIRdCurs issued by IO Devices unc_cha_tor_occupancy.io_rfo uncore cache TOR Occupancy for RFOs from local IO devices event=0x36,umask=0xc803ff04 01 TOR Occupancy : RFOs issued by IO Devices unc_cha_tor_occupancy.io_wbmtoi uncore cache TOR Occupancy for WBMtoI requests from IO devices event=0x36,umask=0xcc23ff04 01 TOR Occupancy : WbMtoIs issued by IO Devices unc_cha_tor_occupancy.loc_all uncore cache TOR Occupancy for All locally initiated requests event=0x36,umask=0xc000ff05 01 TOR Occupancy : All from Local iA and IO unc_cha_tor_occupancy.loc_ia uncore cache TOR Occupancy for All from Local iA event=0x36,umask=0xc000ff01 01 TOR Occupancy : All from Local iA unc_cha_tor_occupancy.loc_io uncore cache TOR Occupancy for All from Local IO event=0x36,umask=0xc000ff04 01 TOR Occupancy : All from Local IO uncore_b2cmi unc_b2cmi_clockticks uncore interconnect Clockticks of the mesh to memory (B2CMI) event=1 01 unc_b2cmi_direct2core_taken uncore interconnect Counts the number of times B2CMI egress did D2C (direct to core) event=0x16,umask=1 01 unc_b2cmi_direct2core_txn_override uncore interconnect Counts the number of times D2C wasn't honoured even though the incoming request had d2c set for non cisgress txn event=0x18,umask=1 01 unc_b2cmi_imc_reads.all uncore interconnect Counts any read event=0x24,umask=0x104 01 unc_b2cmi_imc_reads.normal uncore interconnect Counts normal reads issue to CMI event=0x24,umask=0x101 01 unc_b2cmi_imc_reads.to_ddr_as_mem uncore interconnect Counts reads to 1lm non persistent memory regions event=0x24,umask=0x108 01 unc_b2cmi_imc_writes.all uncore interconnect All Writes - All Channels event=0x25,umask=0x110 01 unc_b2cmi_imc_writes.full uncore interconnect Full Non-ISOCH - All Channels event=0x25,umask=0x101 01 unc_b2cmi_imc_writes.partial uncore interconnect Partial Non-ISOCH - All Channels event=0x25,umask=0x102 01 unc_b2cmi_imc_writes.to_ddr_as_mem uncore interconnect DDR - All Channels event=0x25,umask=0x120 01 unc_b2cmi_prefcam_inserts.ch0_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 0 event=0x56,umask=1 01 unc_b2cmi_prefcam_inserts.xpt_allch uncore interconnect Prefetch CAM Inserts : XPT -All Channels event=0x56,umask=1 01 Prefetch CAM Inserts : XPT - All Channels unc_b2cmi_prefcam_occupancy.ch0 uncore interconnect Prefetch CAM Occupancy : Channel 0 event=0x54,umask=1 01 unc_b2cmi_tracker_inserts.ch0 uncore interconnect Tracker Inserts : Channel 0 event=0x32,umask=0x104 01 unc_b2cmi_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy : Channel 0 event=0x33,umask=1 01 unc_b2cmi_wr_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts : Channel 0 event=0x40,umask=1 01 unc_i_cache_total_occupancy.mem uncore interconnect Total Write Cache Occupancy : Mem event=0xf,umask=4 01 unc_i_clockticks uncore interconnect IRP Clockticks event=1 01 unc_i_faf_inserts uncore interconnect Inbound read requests received by the IRP and inserted into the FAF queue event=0x18 01 unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed event=0x1f,umask=0x10 01 unc_i_transactions.wr_pref uncore interconnect Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh event=0x11,umask=8 01 unc_iio_clockticks uncore io IIO Clockticks event=1 01 unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=0xff,fc_mask=7,umask=0x70ff004 01 unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=1,fc_mask=7,umask=0x7001004 01 unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=2,fc_mask=7,umask=0x7002004 01 unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=4,fc_mask=7,umask=0x7004004 01 unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=8,fc_mask=7,umask=0x7008004 01 unc_iio_comp_buf_inserts.cmpd.part4 uncore io PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=0x10,fc_mask=7,umask=0x7010004 01 unc_iio_comp_buf_inserts.cmpd.part5 uncore io PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=0x20,fc_mask=7,umask=0x7020004 01 unc_iio_comp_buf_inserts.cmpd.part6 uncore io PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=0x40,fc_mask=7,umask=0x7040004 01 unc_iio_comp_buf_inserts.cmpd.part7 uncore io PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=0x80,fc_mask=7,umask=0x7080004 01 unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=0xff,fc_mask=7,umask=0x70ff0ff 01 unc_iio_comp_buf_occupancy.cmpd.part0 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=1,fc_mask=7,umask=0x7001001 01 unc_iio_comp_buf_occupancy.cmpd.part1 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=2,fc_mask=7,umask=0x7002002 01 unc_iio_comp_buf_occupancy.cmpd.part2 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=4,fc_mask=7,umask=0x7004004 01 unc_iio_comp_buf_occupancy.cmpd.part3 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=8,fc_mask=7,umask=0x7008008 01 unc_iio_comp_buf_occupancy.cmpd.part4 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=0x10,fc_mask=7,umask=0x7010010 01 unc_iio_comp_buf_occupancy.cmpd.part5 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=0x20,fc_mask=7,umask=0x7020020 01 unc_iio_comp_buf_occupancy.cmpd.part6 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=0x40,fc_mask=7,umask=0x7040040 01 unc_iio_comp_buf_occupancy.cmpd.part7 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=0x80,fc_mask=7,umask=0x7080080 01 unc_iio_data_req_by_cpu.mem_read.all_parts uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0xff,fc_mask=7,umask=0x70ff004 01 unc_iio_data_req_by_cpu.mem_read.part0 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=1,fc_mask=7,umask=0x7001004 01 unc_iio_data_req_by_cpu.mem_read.part1 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=2,fc_mask=7,umask=0x7002004 01 unc_iio_data_req_by_cpu.mem_read.part2 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=4,fc_mask=7,umask=0x7004004 01 unc_iio_data_req_by_cpu.mem_read.part3 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=8,fc_mask=7,umask=0x7008004 01 unc_iio_data_req_by_cpu.mem_read.part4 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x7010004 01 unc_iio_data_req_by_cpu.mem_read.part5 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x7020004 01 unc_iio_data_req_by_cpu.mem_read.part6 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x7040004 01 unc_iio_data_req_by_cpu.mem_read.part7 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x7080004 01 unc_iio_data_req_by_cpu.mem_write.all_parts uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0xff,fc_mask=7,umask=0x70ff001 01 unc_iio_data_req_by_cpu.mem_write.part0 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=1,fc_mask=7,umask=0x7001001 01 unc_iio_data_req_by_cpu.mem_write.part1 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=2,fc_mask=7,umask=0x7002001 01 unc_iio_data_req_by_cpu.mem_write.part2 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=4,fc_mask=7,umask=0x7004001 01 unc_iio_data_req_by_cpu.mem_write.part3 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=8,fc_mask=7,umask=0x7008001 01 unc_iio_data_req_by_cpu.mem_write.part4 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x7010001 01 unc_iio_data_req_by_cpu.mem_write.part5 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x7020001 01 unc_iio_data_req_by_cpu.mem_write.part6 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x7040001 01 unc_iio_data_req_by_cpu.mem_write.part7 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x7080001 01 unc_iio_data_req_of_cpu.mem_read.part0 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=1,fc_mask=7,umask=0x7001004 01 unc_iio_data_req_of_cpu.mem_read.part1 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=2,fc_mask=7,umask=0x7002004 01 unc_iio_data_req_of_cpu.mem_read.part2 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=4,fc_mask=7,umask=0x7004004 01 unc_iio_data_req_of_cpu.mem_read.part3 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=8,fc_mask=7,umask=0x7008004 01 unc_iio_data_req_of_cpu.mem_read.part4 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=0x7010004 01 unc_iio_data_req_of_cpu.mem_read.part5 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=0x7020004 01 unc_iio_data_req_of_cpu.mem_read.part6 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=0x7040004 01 unc_iio_data_req_of_cpu.mem_read.part7 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=0x7080004 01 unc_iio_data_req_of_cpu.mem_write.part0 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=1,fc_mask=7,umask=0x7001001 01 unc_iio_data_req_of_cpu.mem_write.part1 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=2,fc_mask=7,umask=0x7002001 01 unc_iio_data_req_of_cpu.mem_write.part2 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=4,fc_mask=7,umask=0x7004001 01 unc_iio_data_req_of_cpu.mem_write.part3 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=8,fc_mask=7,umask=0x7008001 01 unc_iio_data_req_of_cpu.mem_write.part4 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=0x7010001 01 unc_iio_data_req_of_cpu.mem_write.part5 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=0x7020001 01 unc_iio_data_req_of_cpu.mem_write.part6 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=0x7040001 01 unc_iio_data_req_of_cpu.mem_write.part7 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=0x7080001 01 unc_iio_data_req_of_cpu.peer_write.part0 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=1,fc_mask=7,umask=0x7001002 01 unc_iio_data_req_of_cpu.peer_write.part1 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=2,fc_mask=7,umask=0x7002002 01 unc_iio_data_req_of_cpu.peer_write.part2 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=4,fc_mask=7,umask=0x7004002 01 unc_iio_data_req_of_cpu.peer_write.part3 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=8,fc_mask=7,umask=0x7008002 01 unc_iio_data_req_of_cpu.peer_write.part4 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=0x7010002 01 unc_iio_data_req_of_cpu.peer_write.part5 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=0x7020002 01 unc_iio_data_req_of_cpu.peer_write.part6 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=7,umask=0x7040002 01 unc_iio_data_req_of_cpu.peer_write.part7 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=7,umask=0x7080002 01 unc_iio_iommu0.1g_hits uncore io IOTLB Hits to a 1G Page event=0x40,umask=0x10 01 unc_iio_iommu0.2m_hits uncore io IOTLB Hits to a 2M Page event=0x40,umask=8 01 unc_iio_iommu0.4k_hits uncore io IOTLB Hits to a 4K Page event=0x40,umask=4 01 unc_iio_iommu0.ctxt_cache_hits uncore io Context cache hits event=0x40,umask=0x80 01 unc_iio_iommu0.ctxt_cache_lookups uncore io Context cache lookups event=0x40,umask=0x40 01 unc_iio_iommu0.first_lookups uncore io IOTLB lookups first event=0x40,umask=1 01 unc_iio_iommu0.misses uncore io IOTLB Fills (same as IOTLB miss) event=0x40,umask=0x20 01 unc_iio_iommu1.num_mem_accesses uncore io IOMMU memory access (both low and high priority) event=0x41,umask=0xc0 01 unc_iio_iommu1.slpwc_1g_hits uncore io Second Level Page Walk Cache Hit to a 1G page event=0x41,umask=4 01 unc_iio_iommu1.slpwc_256t_hits uncore io Second Level Page Walk Cache Hit to a 256T page event=0x41,umask=0x10 01 unc_iio_iommu1.slpwc_512g_hits uncore io Second Level Page Walk Cache Hit to a 512G page event=0x41,umask=8 01 unc_iio_num_req_of_cpu_by_tgt.abort uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x70ff080 01 unc_iio_num_req_of_cpu_by_tgt.confined_p2p uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x70ff040 01 unc_iio_num_req_of_cpu_by_tgt.loc_p2p uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x70ff020 01 unc_iio_num_req_of_cpu_by_tgt.mcast uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x70ff002 01 unc_iio_num_req_of_cpu_by_tgt.mem uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x70ff008 01 unc_iio_num_req_of_cpu_by_tgt.msgb uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x70ff001 01 unc_iio_num_req_of_cpu_by_tgt.ubox uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x70ff004 01 unc_iio_pwt_occupancy uncore io All 9 bits of Page Walk Tracker Occupancy event=0x42 01 unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=1,fc_mask=7,umask=0x7001004 01 unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=2,fc_mask=7,umask=0x7002004 01 unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=4,fc_mask=7,umask=0x7004004 01 unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=8,fc_mask=7,umask=0x7008004 01 unc_iio_txn_req_by_cpu.mem_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x7010004 01 unc_iio_txn_req_by_cpu.mem_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x7020004 01 unc_iio_txn_req_by_cpu.mem_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x7040004 01 unc_iio_txn_req_by_cpu.mem_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x7080004 01 unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=1,fc_mask=7,umask=0x7001001 01 unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=2,fc_mask=7,umask=0x7002001 01 unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=4,fc_mask=7,umask=0x7004001 01 unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=8,fc_mask=7,umask=0x7008001 01 unc_iio_txn_req_by_cpu.mem_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x7010001 01 unc_iio_txn_req_by_cpu.mem_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x7020001 01 unc_iio_txn_req_by_cpu.mem_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x7040001 01 unc_iio_txn_req_by_cpu.mem_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x7080001 01 unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=1,fc_mask=7,umask=0x7001004 01 unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=2,fc_mask=7,umask=0x7002004 01 unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=4,fc_mask=7,umask=0x7004004 01 unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=8,fc_mask=7,umask=0x7008004 01 unc_iio_txn_req_of_cpu.mem_read.part4 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=0x7010004 01 unc_iio_txn_req_of_cpu.mem_read.part5 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=0x7020004 01 unc_iio_txn_req_of_cpu.mem_read.part6 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=0x7040004 01 unc_iio_txn_req_of_cpu.mem_read.part7 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=0x7080004 01 unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=1,fc_mask=7,umask=0x7001001 01 unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=2,fc_mask=7,umask=0x7002001 01 unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=4,fc_mask=7,umask=0x7004001 01 unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=8,fc_mask=7,umask=0x7008001 01 unc_iio_txn_req_of_cpu.mem_write.part4 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=0x7010001 01 unc_iio_txn_req_of_cpu.mem_write.part5 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=0x7020001 01 unc_iio_txn_req_of_cpu.mem_write.part6 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=0x7040001 01 unc_iio_txn_req_of_cpu.mem_write.part7 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=0x7080001 01 unc_iio_txn_req_of_cpu.peer_write.part0 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=1,fc_mask=7,umask=0x7001002 01 unc_iio_txn_req_of_cpu.peer_write.part1 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=2,fc_mask=7,umask=0x7002002 01 unc_iio_txn_req_of_cpu.peer_write.part2 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=4,fc_mask=7,umask=0x7004002 01 unc_iio_txn_req_of_cpu.peer_write.part3 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=8,fc_mask=7,umask=0x7008002 01 unc_iio_txn_req_of_cpu.peer_write.part4 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=0x7010002 01 unc_iio_txn_req_of_cpu.peer_write.part5 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=0x7020002 01 unc_iio_txn_req_of_cpu.peer_write.part6 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x40,fc_mask=7,umask=0x7040002 01 unc_iio_txn_req_of_cpu.peer_write.part7 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x80,fc_mask=7,umask=0x7080002 01 unc_m_act_count.all uncore memory DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates event=2,umask=0xf7 01 unc_m_act_count.rd uncore memory DRAM Activate Count : Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates event=2,umask=0xf1 01 unc_m_act_count.ufill uncore memory DRAM Activate Count : Underfill Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates event=2,umask=0xf4 01 unc_m_act_count.wr uncore memory DRAM Activate Count : Write transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates event=2,umask=0xf2 01 unc_m_cas_count_sch0.all uncore memory CAS count for SubChannel 0, all CAS operations event=5,umask=0xff 01 unc_m_cas_count_sch0.rd uncore memory CAS count for SubChannel 0, all reads event=5,umask=0xcf 01 unc_m_cas_count_sch0.rd_reg uncore memory CAS count for SubChannel 0 regular reads event=5,umask=0xc1 01 unc_m_cas_count_sch0.rd_underfill uncore memory CAS count for SubChannel 0 underfill reads event=5,umask=0xc4 01 unc_m_cas_count_sch0.wr uncore memory CAS count for SubChannel 0, all writes event=5,umask=0xf0 01 unc_m_cas_count_sch0.wr_nonpre uncore memory CAS count for SubChannel 0 regular writes event=5,umask=0xd0 01 unc_m_cas_count_sch0.wr_pre uncore memory CAS count for SubChannel 0 auto-precharge writes event=5,umask=0xe0 01 unc_m_cas_count_sch1.all uncore memory CAS count for SubChannel 1, all CAS operations event=6,umask=0xff 01 unc_m_cas_count_sch1.rd uncore memory CAS count for SubChannel 1, all reads event=6,umask=0xcf 01 unc_m_cas_count_sch1.rd_reg uncore memory CAS count for SubChannel 1 regular reads event=6,umask=0xc1 01 unc_m_cas_count_sch1.rd_underfill uncore memory CAS count for SubChannel 1 underfill reads event=6,umask=0xc4 01 unc_m_cas_count_sch1.wr uncore memory CAS count for SubChannel 1, all writes event=6,umask=0xf0 01 unc_m_cas_count_sch1.wr_nonpre uncore memory CAS count for SubChannel 1 regular writes event=6,umask=0xd0 01 unc_m_cas_count_sch1.wr_pre uncore memory CAS count for SubChannel 1 auto-precharge writes event=6,umask=0xe0 01 unc_m_clockticks uncore memory Number of DRAM DCLK clock cycles while the event is enabled event=1,umask=1 01 DRAM Clockticks unc_m_hclockticks uncore memory Number of DRAM HCLK clock cycles while the event is enabled event=1 01 DRAM Clockticks unc_m_pre_count.all uncore memory DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel event=3,umask=0xff 01 unc_m_pre_count.pgt uncore memory DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel event=3,umask=0xf8 01 unc_m_pre_count.rd uncore memory DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel event=3,umask=0xf1 01 unc_m_pre_count.ufill uncore memory DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel event=3,umask=0xf4 01 unc_m_pre_count.wr uncore memory DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel event=3,umask=0xf2 01 unc_m_rdb_inserts.sch0 uncore memory Read buffer inserts on subchannel 0 event=0x17,umask=0x40 01 unc_m_rdb_inserts.sch1 uncore memory Read buffer inserts on subchannel 1 event=0x17,umask=0x80 01 unc_m_rdb_occupancy_sch0 uncore memory Read buffer occupancy on subchannel 0 event=0x1a 01 unc_m_rdb_occupancy_sch1 uncore memory Read buffer occupancy on subchannel 1 event=0x1b 01 unc_m_rpq_inserts.pch0 uncore memory Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests event=0x10,umask=0x50 01 unc_m_rpq_inserts.pch1 uncore memory Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests event=0x10,umask=0xa0 01 unc_m_rpq_inserts.sch0_pch0 uncore memory Read Pending Queue inserts for subchannel 0, pseudochannel 0 event=0x10,umask=0x10 01 unc_m_rpq_inserts.sch0_pch1 uncore memory Read Pending Queue inserts for subchannel 0, pseudochannel 1 event=0x10,umask=0x20 01 unc_m_rpq_inserts.sch1_pch0 uncore memory Read Pending Queue inserts for subchannel 1, pseudochannel 0 event=0x10,umask=0x40 01 unc_m_rpq_inserts.sch1_pch1 uncore memory Read Pending Queue inserts for subchannel 1, pseudochannel 1 event=0x10,umask=0x80 01 unc_m_rpq_occupancy_sch0_pch0 uncore memory Read pending queue occupancy for subchannel 0, pseudochannel 0 event=0x80 01 unc_m_rpq_occupancy_sch0_pch1 uncore memory Read pending queue occupancy for subchannel 0, pseudochannel 1 event=0x81 01 unc_m_rpq_occupancy_sch1_pch0 uncore memory Read pending queue occupancy for subchannel 1, pseudochannel 0 event=0x82 01 unc_m_rpq_occupancy_sch1_pch1 uncore memory Read pending queue occupancy for subchannel 1, pseudochannel 1 event=0x83 01 unc_m_wpq_inserts.pch0 uncore memory Write Pending Queue Allocations event=0x22,umask=0x50 01 unc_m_wpq_inserts.pch1 uncore memory Write Pending Queue Allocations event=0x22,umask=0xa0 01 unc_m_wpq_inserts.sch0_pch0 uncore memory Write Pending Queue inserts for subchannel 0, pseudochannel 0 event=0x22,umask=0x10 01 unc_m_wpq_inserts.sch0_pch1 uncore memory Write Pending Queue inserts for subchannel 0, pseudochannel 1 event=0x22,umask=0x20 01 unc_m_wpq_inserts.sch1_pch0 uncore memory Write Pending Queue inserts for subchannel 1, pseudochannel 0 event=0x22,umask=0x40 01 unc_m_wpq_inserts.sch1_pch1 uncore memory Write Pending Queue inserts for subchannel 1, pseudochannel 1 event=0x22,umask=0x80 01 unc_m_wpq_occupancy_sch0_pch0 uncore memory Write pending queue occupancy for subchannel 0, pseudochannel 0 event=0x84 01 unc_m_wpq_occupancy_sch0_pch1 uncore memory Write pending queue occupancy for subchannel 0, pseudochannel 1 event=0x85 01 unc_m_wpq_occupancy_sch1_pch0 uncore memory Write pending queue occupancy for subchannel 1, pseudochannel 0 event=0x86 01 unc_m_wpq_occupancy_sch1_pch1 uncore memory Write pending queue occupancy for subchannel 1, pseudochannel 1 event=0x87 01 unc_p_clockticks uncore power PCU Clockticks event=1 01 PCU Clockticks: The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time dtlb_load_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB event=8,period=200003,umask=0x20 00 dtlb_load_misses.walk_completed virtual memory Counts the number of page walks completed due to load DTLB misses event=8,period=200003,umask=0xe 00 dtlb_load_misses.walk_pending virtual memory Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle event=8,period=200003,umask=0x10 00 Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals dtlb_store_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB event=0x49,period=2000003,umask=0x20 00 dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to a 1G page event=0x49,period=2000003,umask=0xe 00 dtlb_store_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle event=0x49,period=200003,umask=0x10 00 Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals itlb_misses.walk_pending virtual memory Counts the number of page walks outstanding for iside in PMH every cycle event=0x85,period=200003,umask=0x10 00 Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks l2_request.hit cache All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT] event=0x24,period=200003,umask=0xdf 00 Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT] l2_request.miss cache Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MISS] event=0x24,period=200003,umask=0x3f 00 Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS] l2_rqsts.hit cache All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT] event=0x24,period=200003,umask=0xdf 00 Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT] l2_rqsts.miss cache Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS] event=0x24,period=200003,umask=0x3f 00 Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS] mem_inst_retired.stlb_hit_loads cache Retired load instructions that hit the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=9 00 Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB) Supports address when precise (Precise event) mem_inst_retired.stlb_hit_stores cache Retired store instructions that hit the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0xa 00 Number of retired store instructions that hit in the 2nd-level TLB (STLB) Supports address when precise (Precise event) offcore_requests.all_requests cache Any memory transaction that reached the SQ event=0x21,period=100003,umask=0x80 00 Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc. offcore_requests.demand_code_rd cache Cacheable and Non-Cacheable code read requests event=0x21,period=100003,umask=2 00 Counts both cacheable and Non-Cacheable code read requests offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x20,cmask=1,period=1000003,umask=8 00 Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore event=0x20,cmask=1,period=1000003,umask=4 00 Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_rfo cache Store Read transactions pending for off-core. Highly correlated event=0x20,period=1000003,umask=4 00 Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion arith.fpdiv_active floating point This event counts the cycles the floating point divider is busy event=0xb0,cmask=1,period=1000003,umask=1 00 frontend_retired.any_ant frontend Retired ANT branches (Precise event) event=0xc6,period=100007,umask=3,frontend=0x9 00 Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted) (Precise event) frontend_retired.any_dsb_miss frontend Retired Instructions who experienced DSB miss (Precise event) event=0xc6,period=100007,umask=3,frontend=0x1 00 Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event) frontend_retired.dsb_miss frontend Retired Instructions who experienced a critical DSB miss (Precise event) event=0xc6,period=100007,umask=3,frontend=0x11 00 Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss (Precise event) frontend_retired.itlb_miss frontend Retired Instructions who experienced iTLB true miss (Precise event) event=0xc6,period=100007,umask=3,frontend=0x14 00 Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event) frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss (Precise event) event=0xc6,period=100007,umask=3,frontend=0x12 00 Counts retired Instructions who experienced Instruction L1 Cache true miss (Precise event) frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss (Precise event) event=0xc6,period=100007,umask=3,frontend=0x13 00 Counts retired Instructions who experienced Instruction L2 Cache true miss (Precise event) frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle (Precise event) event=0xc6,period=100007,umask=3,frontend=0x600106 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=3,frontend=0x608006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=3,frontend=0x601006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_2 frontend Retired instructions after front-end starvation of at least 2 cycles (Precise event) event=0xc6,period=100007,umask=3,frontend=0x600206 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=3,frontend=0x610006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_2_bubbles_ge_1 frontend Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=3,frontend=0x100206 00 Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event) frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=3,frontend=0x602006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=3,frontend=0x600406 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=3,frontend=0x620006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=3,frontend=0x604006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=3,frontend=0x600806 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.late_swpf frontend I-Cache miss too close to Code Prefetch Instruction (Precise event) event=0xc6,period=100007,umask=3,frontend=0x9 00 Number of Instruction Cache demand miss in shadow of an on-going i-fetch cache-line triggered by PREFETCHIT0/1 instructions (Precise event) frontend_retired.misp_ant frontend Mispredicted Retired ANT branches (Precise event) event=0xc6,period=100007,umask=2,frontend=0x9 00 ANT retired branches that got just mispredicted (Precise event) frontend_retired.ms_flows frontend FRONTEND_RETIRED.MS_FLOWS (Precise event) event=0xc6,period=100007,umask=3,frontend=0x8 00 frontend_retired.stlb_miss frontend Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event) event=0xc6,period=100007,umask=3,frontend=0x15 00 Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event) frontend_retired.unknown_branch frontend FRONTEND_RETIRED.UNKNOWN_BRANCH (Precise event) event=0xc6,period=100007,umask=3,frontend=0x17 00 idq.ms_uops frontend Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=1000003,umask=0x20 00 Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ idq_bubbles.core frontend This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations event=0x9c,period=1000003,umask=1 00 This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. The count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method idq_uops_not_delivered.core frontend Uops not delivered by IDQ when backend of the machine is not stalled event=0x9c,period=1000003,umask=1 00 Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle cycle_activity.cycles_l3_miss memory Cycles while L3 cache miss demand load is outstanding event=0xa3,cmask=2,period=1000003,umask=2 00 mem_trans_retired.load_latency_gt_2048 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles Supports address when precise (Must be precise) event=0xcd,period=23,umask=1,ldlat=0x800 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd memory Cycles where data return is pending for a Demand Data Read request who miss L3 cache event=0x20,cmask=1,period=1000003,umask=0x10 00 Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ rs.empty_resource other Cycles when RS was empty and a resource allocation stall is asserted event=0xa5,period=1000003,umask=1 00 br_misp_retired.all_branches_cost pipeline All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x44 00 br_misp_retired.cond_cost pipeline Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x51 00 br_misp_retired.cond_ntaken_cost pipeline Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x50 00 br_misp_retired.cond_taken_cost pipeline Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x41 00 br_misp_retired.indirect_call_cost pipeline Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x42 00 br_misp_retired.indirect_cost pipeline Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=100003,umask=0xc0 00 br_misp_retired.near_taken_cost pipeline Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x60 00 br_misp_retired.ret_cost pipeline Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=100007,umask=0x48 00 inst_retired.nop pipeline Retired NOP instructions (Precise event) event=0xc0,period=2000003,umask=2 00 Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions (Precise event) topdown.backend_bound_slots pipeline This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions event=0xa4,period=10000003,umask=2 00 This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method uops_decoded.dec0_uops pipeline Number of non dec-by-all uops decoded by decoder event=0x76,period=1000003,umask=1 00 This event counts the number of not dec-by-all uops decoded by decoder 0 uops_retired.slots pipeline This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric event=0xc2,period=2000003,umask=2 00 This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method unc_chacms_clockticks uncore cache Clockticks for CMS units attached to CHA event=1 01 UNC_CHACMS_CLOCKTICKS unc_cha_dir_lookup.no_snp uncore cache Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed event=0x53,umask=2 01 unc_cha_dir_lookup.snp uncore cache Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed event=0x53,umask=1 01 unc_cha_dir_update.ha uncore cache Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines event=0x54,umask=1 01 unc_cha_dir_update.tor uncore cache Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines event=0x54,umask=2 01 unc_cha_llc_lookup.all_remote uncore cache Cache Lookups: All Requests to Remotely Homed Memory event=0x34,umask=0x17e0ff 01 Cache Lookups : All transactions from Remote Agents unc_cha_llc_lookup.remotely_homed_address uncore cache Cache Lookups: All Requests to Remotely Homed Memory event=0x34,umask=0x15dfff 01 Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_code uncore cache Cache Lookups: Code Read/Prefetch Requests from a Remote Socket event=0x34,umask=0x1a10ff 01 Cache Lookups : CRd Requests unc_cha_llc_lookup.remote_data_rd uncore cache Cache Lookups: Data Read/Prefetch Requests from a Remote Socket event=0x34,umask=0x1a01ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.remote_rfo uncore cache Cache Lookups: RFO Requests/Prefetches from a Remote Socket event=0x34,umask=0x1a08ff 01 Cache Lookups : RFO Requests unc_cha_llc_lookup.remote_snp uncore cache Cache Lookups: Snoop Requests from a Remote Socket event=0x34,umask=0x1c19ff 01 Counts the number of times the LLC was accessed unc_cha_llc_lookup.write_remote uncore cache Cache Lookups: Writes to Remotely Homed Memory (includes writebacks from L1/L2) event=0x34,umask=0x17c2ff 01 Cache Lookups : Remote Writes unc_cha_llc_victims.remote_all uncore cache Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x800f 01 Lines Victimized : Remote - All Lines unc_cha_llc_victims.remote_e uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x8002 01 Lines Victimized : Remote - Lines in E State unc_cha_llc_victims.remote_m uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x8001 01 Lines Victimized : Remote - Lines in M State unc_cha_llc_victims.remote_s uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in event=0x37,umask=0x8004 01 Lines Victimized : Remote - Lines in S State unc_cha_osb.remote_read uncore cache OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB event=0x55,umask=4 01 unc_cha_remote_sf.alloc_exclusive uncore cache UNC_CHA_REMOTE_SF.ALLOC_EXCLUSIVE event=0x69,umask=0x10 01 unc_cha_remote_sf.alloc_shared uncore cache UNC_CHA_REMOTE_SF.ALLOC_SHARED event=0x69,umask=8 01 unc_cha_remote_sf.dealloc_evctcln uncore cache UNC_CHA_REMOTE_SF.DEALLOC_EVCTCLN event=0x69,umask=0x40 01 unc_cha_remote_sf.dirbacked_only uncore cache UNC_CHA_REMOTE_SF.DIRBACKED_ONLY event=0x69 01 unc_cha_remote_sf.hit_exclusive uncore cache UNC_CHA_REMOTE_SF.HIT_EXCLUSIVE event=0x69,umask=2 01 unc_cha_remote_sf.hit_shared uncore cache UNC_CHA_REMOTE_SF.HIT_SHARED event=0x69,umask=1 01 unc_cha_remote_sf.inclusive_only uncore cache UNC_CHA_REMOTE_SF.INCLUSIVE_ONLY event=0x69 01 unc_cha_remote_sf.miss uncore cache UNC_CHA_REMOTE_SF.MISS event=0x69,umask=4 01 unc_cha_remote_sf.update_exclusive uncore cache UNC_CHA_REMOTE_SF.UPDATE_EXCLUSIVE event=0x69 01 unc_cha_remote_sf.update_shared uncore cache UNC_CHA_REMOTE_SF.UPDATE_SHARED event=0x69,umask=0x80 01 unc_cha_remote_sf.victim_exclusive uncore cache UNC_CHA_REMOTE_SF.VICTIM_EXCLUSIVE event=0x69 01 unc_cha_remote_sf.victim_shared uncore cache UNC_CHA_REMOTE_SF.VICTIM_SHARED event=0x69 01 unc_cha_requests.invitoe_remote uncore cache Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA event=0x50,umask=0x20 01 unc_cha_requests.reads_remote uncore cache Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) event=0x50,umask=2 01 unc_cha_requests.writes_remote uncore cache Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc) event=0x50,umask=8 01 unc_cha_tor_inserts.cxl_hit_clflush uncore cache CLFlush transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c8c7fd20 01 unc_cha_tor_inserts.cxl_hit_fsrdcur uncore cache FsRdCur transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c8effd20 01 unc_cha_tor_inserts.cxl_hit_fsrdcurptl uncore cache FsRdCurPtl transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c9effd20 01 unc_cha_tor_inserts.cxl_hit_itom uncore cache ItoM transactions from a CXL device which hit in the L3 event=0x35,umask=0x78cc47fd20 01 unc_cha_tor_inserts.cxl_hit_itomwr uncore cache ItoMWr transactions from a CXL device which hit in the L3 event=0x35,umask=0x78cc4ffd20 01 unc_cha_tor_inserts.cxl_hit_mempushwr uncore cache MemPushWr transactions from a CXL device which hit in the L3 event=0x35,umask=0x78cc6ffd20 01 unc_cha_tor_inserts.cxl_hit_wcil uncore cache WCiL transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c86ffd20 01 unc_cha_tor_inserts.cxl_hit_wcilf uncore cache WcilF transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c867fd20 01 unc_cha_tor_inserts.cxl_hit_wil uncore cache WiL transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c87ffd20 01 unc_cha_tor_inserts.cxl_miss_clflush uncore cache CLFlush transactions from a CXL device which miss the L3 event=0x35,umask=0x78c8c7fe20 01 unc_cha_tor_inserts.cxl_miss_fsrdcur uncore cache FsRdCur transactions from a CXL device which miss the L3 event=0x35,umask=0x78c8effe20 01 unc_cha_tor_inserts.cxl_miss_fsrdcurptl uncore cache FsRdCurPtl transactions from a CXL device which miss the L3 event=0x35,umask=0x78c9effe20 01 unc_cha_tor_inserts.cxl_miss_itom uncore cache ItoM transactions from a CXL device which miss the L3 event=0x35,umask=0x78cc47fe20 01 unc_cha_tor_inserts.cxl_miss_itomwr uncore cache ItoMWr transactions from a CXL device which miss the L3 event=0x35,umask=0x78cc4ffe20 01 unc_cha_tor_inserts.cxl_miss_mempushwr uncore cache MemPushWr transactions from a CXL device which miss the L3 event=0x35,umask=0x78cc6ffe20 01 unc_cha_tor_inserts.cxl_miss_wcil uncore cache WCiL transactions from a CXL device which miss the L3 event=0x35,umask=0x78c86ffe20 01 unc_cha_tor_inserts.cxl_miss_wcilf uncore cache WcilF transactions from a CXL device which miss the L3 event=0x35,umask=0x78c867fe20 01 unc_cha_tor_inserts.cxl_miss_wil uncore cache WiL transactions from a CXL device which miss the L3 event=0x35,umask=0x78c87ffe20 01 unc_cha_tor_inserts.ia_drd uncore cache Data read from local IA that miss the cache event=0x35,umask=0xc817ff01 01 TOR Inserts : DRds issued by iA Cores unc_cha_tor_inserts.ia_drdpte uncore cache DRd PTEs issued by iA Cores due to a page walk event=0x35,umask=0xc837ff01 01 TOR Inserts : DRdPte issued by iA Cores due to a page walk unc_cha_tor_inserts.ia_drd_pref uncore cache Data read prefetch from local IA that miss the cache event=0x35,umask=0xc897ff01 01 TOR Inserts : DRd_Prefs issued by iA Cores unc_cha_tor_inserts.ia_hit_drd uncore cache Data read from local IA that hit the cache event=0x35,umask=0xc817fd01 01 TOR Inserts : DRds issued by iA Cores that Hit the LLC unc_cha_tor_inserts.ia_hit_drdpte uncore cache DRd PTEs issued by iA Cores due to page walks that hit the LLC event=0x35,umask=0xc837fd01 01 TOR Inserts : DRdPte issued by iA Cores due to a page walk that hit the LLC unc_cha_tor_inserts.ia_hit_drd_pref uncore cache Data read prefetch from local IA that hit the cache event=0x35,umask=0xc897fd01 01 TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC unc_cha_tor_inserts.ia_miss_crd_pref_remote uncore cache CRD Prefetches from local IA cores to remotely homed memory event=0x35,umask=0xc88f7e01 01 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_crd_remote uncore cache CRDs from local IA cores to remotely homed memory event=0x35,umask=0xc80f7e01 01 TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_drd uncore cache Data read from local IA that miss the cache event=0x35,umask=0xc817fe01 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_drdpte uncore cache DRd PTEs issued by iA Cores due to a page walk that missed the LLC event=0x35,umask=0xc837fe01 01 TOR Inserts : DRdPte issued by iA Cores due to a page walk that missed the LLC unc_cha_tor_inserts.ia_miss_drd_cxl_acc uncore cache DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card event=0x35,umask=0x10c8178201 01 DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card unc_cha_tor_inserts.ia_miss_drd_ddr uncore cache DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8178601 01 TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC unc_cha_tor_inserts.ia_miss_drd_local uncore cache Data read from local IA that miss the cache event=0x35,umask=0xc816fe01 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_local_ddr uncore cache DRds from local IA cores to locally homed DDR addresses that miss the cache event=0x35,umask=0xc8168601 01 TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_local_pmm uncore cache DRds from local IA cores to locally homed PMM addresses that miss the cache event=0x35,umask=0xc8168a01 01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_pmm uncore cache DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8178a01 01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC unc_cha_tor_inserts.ia_miss_drd_pref uncore cache Data read prefetch from local IA that miss the cache event=0x35,umask=0xc897fe01 01 TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_drd_pref_ddr uncore cache DRd Prefetches from local IA cores to DDR addresses that miss the cache event=0x35,umask=0xc8978601 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC unc_cha_tor_inserts.ia_miss_drd_pref_local uncore cache Data read prefetch from local IA that miss the cache event=0x35,umask=0xc896fe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory unc_cha_tor_inserts.ia_miss_drd_pref_local_ddr uncore cache DRd Prefetches from local IA cores to locally homed DDR addresses that miss the cache event=0x35,umask=0xc8968601 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_pref_local_pmm uncore cache DRd Prefetches from local IA cores to locally homed PMM addresses that miss the cache event=0x35,umask=0xc8968a01 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_pref_pmm uncore cache DRd Prefetches from local IA cores to PMM addresses that miss the cache event=0x35,umask=0xc8978a01 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC unc_cha_tor_inserts.ia_miss_drd_pref_remote uncore cache Data read prefetch from local IA that miss the cache event=0x35,umask=0xc8977e01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory unc_cha_tor_inserts.ia_miss_drd_pref_remote_ddr uncore cache DRd Prefetches from local IA cores to remotely homed DDR addresses that miss the cache event=0x35,umask=0xc8970601 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_drd_pref_remote_pmm uncore cache DRd Prefetches from local IA cores to remotely homed PMM addresses that miss the cache event=0x35,umask=0xc8970a01 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_drd_remote uncore cache Data read from local IA that miss the cache event=0x35,umask=0xc8177e01 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_drd_remote_ddr uncore cache DRds from local IA cores to remotely homed DDR addresses that miss the cache event=0x35,umask=0xc8170601 01 TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_drd_remote_pmm uncore cache DRds from local IA cores to remotely homed PMM addresses that miss the cache event=0x35,umask=0xc8170a01 01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_local_wcilf_pmm uncore cache WCILF requests from local IA cores to locally homed PMM addresses which miss the cache event=0x35,umask=0xc8668a01 01 TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_local_wcil_pmm uncore cache WCIL requests from local IA cores to locally homed PMM addresses which miss the cache event=0x35,umask=0xc86e8a01 01 TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_remote_wcilf_ddr uncore cache WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache event=0x35,umask=0xc8670601 01 TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_remote_wcilf_pmm uncore cache WCILF requests from local IA cores to remotely homed PMM addresses which miss the cache event=0x35,umask=0xc8670a01 01 TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_remote_wcil_ddr uncore cache WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache event=0x35,umask=0xc86f0601 01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_remote_wcil_pmm uncore cache WCIL requests from local IA cores to remotely homed PMM addresses which miss the cache event=0x35,umask=0xc86f0a01 01 TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_rfo_pref_remote uncore cache Read for ownership prefetch from local IA that miss the cache event=0x35,umask=0xc8877e01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_rfo_remote uncore cache Read for ownership from local IA that miss the cache event=0x35,umask=0xc8077e01 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_wcilf_pmm uncore cache WCILF requests from local IA cores to PMM homed addresses which miss the cache event=0x35,umask=0xc8678a01 01 TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC unc_cha_tor_inserts.ia_miss_wcil_pmm uncore cache WCIL requests from a local IA core to PMM homed addresses that miss the cache event=0x35,umask=0xc86f8a01 01 TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC unc_cha_tor_inserts.io_itomcachenear_local uncore cache ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xcd42ff04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on the local socket unc_cha_tor_inserts.io_itomcachenear_remote uncore cache ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xcd437f04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on a remote socket unc_cha_tor_inserts.io_itom_local uncore cache ItoM (write) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xcc42ff04 01 TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on the local socket unc_cha_tor_inserts.io_itom_remote uncore cache ItoM (write) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xcc437f04 01 TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on a remote socket unc_cha_tor_inserts.io_pcirdcur_local uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xc8f2ff04 01 TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on the local socket unc_cha_tor_inserts.io_pcirdcur_remote uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xc8f37f04 01 TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on a remote socket unc_cha_tor_inserts.rem_all uncore cache All remote requests (e.g. snoops, writebacks) that came from remote sockets event=0x35,umask=0xc001ffc8 01 TOR Inserts : All Remote Requests unc_cha_tor_inserts.rem_snps uncore cache All snoops to this LLC that came from remote sockets event=0x35,umask=0xc001ff08 01 TOR Inserts : All Snoops from Remote unc_cha_tor_occupancy.cxl_hit_clflush uncore cache TOR Occupancy for CLFlush transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c8c7fd20 01 unc_cha_tor_occupancy.cxl_hit_fsrdcur uncore cache TOR Occupancy for FsRdCur transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c8effd20 01 unc_cha_tor_occupancy.cxl_hit_fsrdcurptl uncore cache TOR Occupancy for FsRdCurPtl transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c9effd20 01 unc_cha_tor_occupancy.cxl_hit_itom uncore cache TOR Occupancy for ItoM transactions from a CXL device which hit in the L3 event=0x36,umask=0x78cc47fd20 01 unc_cha_tor_occupancy.cxl_hit_itomwr uncore cache TOR Occupancy for ItoMWr transactions from a CXL device which hit in the L3 event=0x36,umask=0x78cc4ffd20 01 unc_cha_tor_occupancy.cxl_hit_mempushwr uncore cache TOR Occupancy for MemPushWr transactions from a CXL device which hit in the L3 event=0x36,umask=0x78cc6ffd20 01 unc_cha_tor_occupancy.cxl_hit_wcil uncore cache TOR Occupancy for WCiL transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c86ffd20 01 unc_cha_tor_occupancy.cxl_hit_wcilf uncore cache TOR Occupancy for WcilF transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c867fd20 01 unc_cha_tor_occupancy.cxl_hit_wil uncore cache TOR Occupancy for WiL transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c87ffd20 01 unc_cha_tor_occupancy.cxl_miss_clflush uncore cache TOR Occupancy for CLFlush transactions from a CXL device which miss the L3 event=0x36,umask=0x78c8c7fe20 01 unc_cha_tor_occupancy.cxl_miss_fsrdcur uncore cache TOR Occupancy for FsRdCur transactions from a CXL device which miss the L3 event=0x36,umask=0x78c8effe20 01 unc_cha_tor_occupancy.cxl_miss_fsrdcurptl uncore cache TOR Occupancy for FsRdCurPtl transactions from a CXL device which miss the L3 event=0x36,umask=0x78c9effe20 01 unc_cha_tor_occupancy.cxl_miss_itom uncore cache TOR Occupancy for ItoM transactions from a CXL device which miss the L3 event=0x36,umask=0x78cc47fe20 01 unc_cha_tor_occupancy.cxl_miss_itomwr uncore cache TOR Occupancy for ItoMWr transactions from a CXL device which miss the L3 event=0x36,umask=0x78cc4ffe20 01 unc_cha_tor_occupancy.cxl_miss_mempushwr uncore cache TOR Occupancy for MemPushWr transactions from a CXL device which miss the L3 event=0x36,umask=0x78cc6ffe20 01 unc_cha_tor_occupancy.cxl_miss_wcil uncore cache TOR Occupancy for WCiL transactions from a CXL device which miss the L3 event=0x36,umask=0x78c86ffe20 01 unc_cha_tor_occupancy.cxl_miss_wcilf uncore cache TOR Occupancy for WcilF transactions from a CXL device which miss the L3 event=0x36,umask=0x78c867fe20 01 unc_cha_tor_occupancy.cxl_miss_wil uncore cache TOR Occupancy for WiL transactions from a CXL device which miss the L3 event=0x36,umask=0x78c87ffe20 01 unc_cha_tor_occupancy.ia_drd uncore cache TOR Occupancy for Data read from local IA that miss the cache event=0x36,umask=0xc817ff01 01 TOR Occupancy : DRds issued by iA Cores unc_cha_tor_occupancy.ia_drdpte uncore cache TOR Occupancy for DRd PTEs issued by iA Cores due to a page walk event=0x36,umask=0xc837ff01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk unc_cha_tor_occupancy.ia_drd_pref uncore cache TOR Occupancy for Data read prefetch from local IA that miss the cache event=0x36,umask=0xc897ff01 01 TOR Occupancy : DRd_Prefs issued by iA Cores unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy for Data read from local IA that hit the cache event=0x36,umask=0xc817fd01 01 TOR Occupancy : DRds issued by iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_hit_drdpte uncore cache TOR Occupancy for DRd PTEs issued by iA Cores due to page walks that hit the LLC event=0x36,umask=0xc837fd01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC unc_cha_tor_occupancy.ia_hit_drd_pref uncore cache TOR Occupancy for Data read prefetch from local IA that hit the cache event=0x36,umask=0xc897fd01 01 TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_miss_crd_pref_remote uncore cache TOR Occupancy for CRD Prefetches from local IA cores to remotely homed memory event=0x36,umask=0xc88f7e01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_crd_remote uncore cache TOR Occupancy for CRDs from local IA cores to remotely homed memory event=0x36,umask=0xc80f7e01 01 TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy for Data read from local IA that miss the cache event=0x36,umask=0xc817fe01 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_drdpte uncore cache TOR Occupancy for DRd PTEs issued by iA Cores due to a page walk that missed the LLC event=0x36,umask=0xc837fe01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC unc_cha_tor_occupancy.ia_miss_drd_ddr uncore cache TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8178601 01 TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC unc_cha_tor_occupancy.ia_miss_drd_local uncore cache TOR Occupancy for Data read from local IA that miss the cache event=0x36,umask=0xc816fe01 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_local_ddr uncore cache TOR Occupancy for DRds from local IA cores to locally homed DDR addresses that miss the cache event=0x36,umask=0xc8168601 01 TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_local_pmm uncore cache TOR Occupancy for DRds from local IA cores to locally homed PMM addresses that miss the cache event=0x36,umask=0xc8168a01 01 TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_pmm uncore cache TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8178a01 01 TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC unc_cha_tor_occupancy.ia_miss_drd_pref uncore cache TOR Occupancy for Data read prefetch from local IA that miss the cache event=0x36,umask=0xc897fe01 01 TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_drd_pref_ddr uncore cache TOR Occupancy for DRd Prefetches from local IA cores to DDR addresses that miss the cache event=0x36,umask=0xc8978601 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC unc_cha_tor_occupancy.ia_miss_drd_pref_local uncore cache TOR Occupancy for Data read prefetch from local IA that miss the cache event=0x36,umask=0xc896fe01 01 TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_local_ddr uncore cache TOR Occupancy for DRd Prefetches from local IA cores to locally homed DDR addresses that miss the cache event=0x36,umask=0xc8968601 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_pref_local_pmm uncore cache TOR Occupancy for DRd Prefetches from local IA cores to locally homed PMM addresses that miss the cache event=0x36,umask=0xc8968a01 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_pref_pmm uncore cache TOR Occupancy for DRd Prefetches from local IA cores to PMM addresses that miss the cache event=0x36,umask=0xc8978a01 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC unc_cha_tor_occupancy.ia_miss_drd_pref_remote uncore cache TOR Occupancy for Data read prefetch from local IA that miss the cache event=0x36,umask=0xc8977e01 01 TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_remote_ddr uncore cache TOR Occupancy for DRd Prefetches from local IA cores to remotely homed DDR addresses that miss the cache event=0x36,umask=0xc8970601 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_drd_pref_remote_pmm uncore cache TOR Occupancy for DRd Prefetches from local IA cores to remotely homed PMM addresses that miss the cache event=0x36,umask=0xc8970a01 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_drd_remote uncore cache TOR Occupancy for Data read from local IA that miss the cache event=0x36,umask=0xc8177e01 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_drd_remote_ddr uncore cache TOR Occupancy for DRds from local IA cores to remotely homed DDR addresses that miss the cache event=0x36,umask=0xc8170601 01 TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_drd_remote_pmm uncore cache TOR Occupancy for DRds from local IA cores to remotely homed PMM addresses that miss the cache event=0x36,umask=0xc8170a01 01 TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_local_wcilf_pmm uncore cache TOR Occupancy for WCILF requests from local IA cores to locally homed PMM addresses which miss the cache event=0x36,umask=0xc8668a01 01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_local_wcil_pmm uncore cache TOR Occupancy for WCIL requests from local IA cores to locally homed PMM addresses which miss the cache event=0x36,umask=0xc86e8a01 01 TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_remote_wcilf_ddr uncore cache TOR Occupancy for WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache event=0x36,umask=0xc8670601 01 TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_remote_wcilf_pmm uncore cache TOR Occupancy for WCILF requests from local IA cores to remotely homed PMM addresses which miss the cache event=0x36,umask=0xc8670a01 01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_remote_wcil_ddr uncore cache TOR Occupancy for WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache event=0x36,umask=0xc86f0601 01 TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_remote_wcil_pmm uncore cache TOR Occupancy for WCIL requests from local IA cores to remotely homed PMM addresses which miss the cache event=0x36,umask=0xc86f0a01 01 TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_rfo_pref_remote uncore cache TOR Occupancy for Read for ownership prefetch from local IA that miss the cache event=0x36,umask=0xc8877e01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_rfo_remote uncore cache TOR Occupancy for Read for ownership from local IA that miss the cache event=0x36,umask=0xc8077e01 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_wcilf_pmm uncore cache TOR Occupancy for WCILF requests from local IA cores to PMM homed addresses which miss the cache event=0x36,umask=0xc8678a01 01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC unc_cha_tor_occupancy.ia_miss_wcil_pmm uncore cache TOR Occupancy for WCIL requests from a local IA core to PMM homed addresses that miss the cache event=0x36,umask=0xc86f8a01 01 TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC unc_cha_tor_occupancy.io_miss_itomcachenear_local uncore cache TOR Occupancy for ItoMCacheNear transactions from an IO device on the local socket that miss the cache event=0x36,umask=0xcd42fe04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_itomcachenear_remote uncore cache TOR Occupancy for ItoMCacheNear transactions from an IO device on a remote socket that miss the cache event=0x36,umask=0xcd437e04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_itom_local uncore cache TOR Occupancy for ItoM transactions from an IO device on the local socket that miss the cache event=0x36,umask=0xcc42fe04 01 TOR Occupancy : ItoMs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_itom_remote uncore cache TOR Occupancy for ItoM transactions from an IO device on a remote socket that miss the cache event=0x36,umask=0xcc437e04 01 TOR Occupancy : ItoMs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_pcirdcur_local uncore cache TOR Occupancy for PCIRDCUR transactions from an IO device on the local socket that miss the cache event=0x36,umask=0xc8f2fe04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_pcirdcur_remote uncore cache TOR Occupancy for PCIRDCUR transactions from an IO device on a remote socket that miss the cache event=0x36,umask=0xc8f37e04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.rem_all uncore cache TOR Occupancy for All remote requests (e.g. snoops, writebacks) that came from remote sockets event=0x36,umask=0xc001ffc8 01 TOR Occupancy : All Remote Requests unc_cha_tor_occupancy.rem_snps uncore cache TOR Occupancy for All snoops to this LLC that came from remote sockets event=0x36,umask=0xc001ff08 01 TOR Occupancy : All Snoops from Remote uncore_b2cxl unc_b2cxl_clockticks uncore cxl B2CXL Clockticks event=1 01 unc_b2cmi_direct2core_not_taken_dirstate uncore interconnect Counts the number of time D2C was not honoured by egress due to directory state constraints event=0x17,umask=1 01 unc_b2cmi_direct2upi_not_taken_credits uncore interconnect Counts the number of d2k wasn't done due to credit constraints event=0x1b,umask=1 01 unc_b2cmi_direct2upi_not_taken_credits.egress uncore interconnect Direct to UPI Transactions - Ignored due to lack of credits : All : Counts the number of d2k wasn't done due to credit constraints event=0x1b,umask=1 01 unc_b2cmi_direct2upi_not_taken_dirstate uncore interconnect Counts the number of time D2K was not honoured by egress due to directory state constraints event=0x1a,umask=1 01 unc_b2cmi_direct2upi_not_taken_dirstate.egress uncore interconnect Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints event=0x1a,umask=1 01 unc_b2cmi_direct2upi_taken uncore interconnect Counts the number of times egress did D2K (Direct to KTI) event=0x19,umask=1 01 unc_b2cmi_direct2upi_txn_override uncore interconnect Counts the number of times D2K wasn't honoured even though the incoming request had d2k set for non cisgress txn event=0x1c,umask=1 01 unc_b2cmi_directory_hit.clean uncore interconnect Directory Hit Clean event=0x1d,umask=0x38 01 unc_b2cmi_directory_hit.clean_a uncore interconnect Directory Hit : On NonDirty Line in A State event=0x1d,umask=0x20 01 unc_b2cmi_directory_hit.clean_i uncore interconnect Directory Hit : On NonDirty Line in I State event=0x1d,umask=8 01 unc_b2cmi_directory_hit.clean_s uncore interconnect Directory Hit : On NonDirty Line in S State event=0x1d,umask=0x10 01 unc_b2cmi_directory_hit.dirty uncore interconnect Directory Hit Dirty (modified) event=0x1d,umask=7 01 unc_b2cmi_directory_hit.dirty_a uncore interconnect Directory Hit : On Dirty Line in A State event=0x1d,umask=4 01 unc_b2cmi_directory_hit.dirty_i uncore interconnect Directory Hit : On Dirty Line in I State event=0x1d,umask=1 01 unc_b2cmi_directory_hit.dirty_s uncore interconnect Directory Hit : On Dirty Line in S State event=0x1d,umask=2 01 unc_b2cmi_directory_lookup.any uncore interconnect Counts the number of 1lm or 2lm hit read data returns to egress with any directory to non persistent memory event=0x20,umask=1 01 unc_b2cmi_directory_lookup.state_a uncore interconnect Counts the number of 1lm or 2lm hit read data returns to egress with directory A to non persistent memory event=0x20,umask=8 01 unc_b2cmi_directory_lookup.state_i uncore interconnect Counts the number of 1lm or 2lm hit read data returns to egress with directory I to non persistent memory event=0x20,umask=2 01 unc_b2cmi_directory_lookup.state_s uncore interconnect Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory event=0x20,umask=4 01 Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory unc_b2cmi_directory_miss.clean uncore interconnect Directory Miss Clean event=0x1e,umask=0x38 01 unc_b2cmi_directory_miss.clean_a uncore interconnect Directory Miss : On NonDirty Line in A State event=0x1e,umask=0x20 01 unc_b2cmi_directory_miss.clean_i uncore interconnect Directory Miss : On NonDirty Line in I State event=0x1e,umask=8 01 unc_b2cmi_directory_miss.clean_s uncore interconnect Directory Miss : On NonDirty Line in S State event=0x1e,umask=0x10 01 unc_b2cmi_directory_miss.dirty uncore interconnect Directory Miss Dirty (modified) event=0x1e,umask=7 01 unc_b2cmi_directory_miss.dirty_a uncore interconnect Directory Miss : On Dirty Line in A State event=0x1e,umask=4 01 unc_b2cmi_directory_miss.dirty_i uncore interconnect Directory Miss : On Dirty Line in I State event=0x1e,umask=1 01 unc_b2cmi_directory_miss.dirty_s uncore interconnect Directory Miss : On Dirty Line in S State event=0x1e,umask=2 01 unc_b2cmi_directory_update.a2i uncore interconnect Any A2I Transition event=0x21,umask=0x320 01 unc_b2cmi_directory_update.a2s uncore interconnect Any A2S Transition event=0x21,umask=0x340 01 unc_b2cmi_directory_update.any uncore interconnect Counts cisgress directory updates event=0x21,umask=0x301 01 unc_b2cmi_directory_update.hit_any uncore interconnect Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory (DRAM) event=0x21,umask=0x101 01 unc_b2cmi_directory_update.hit_x2a uncore interconnect Directory update in near memory to the A state event=0x21,umask=0x114 01 unc_b2cmi_directory_update.hit_x2i uncore interconnect Directory update in near memory to the I state event=0x21,umask=0x128 01 unc_b2cmi_directory_update.hit_x2s uncore interconnect Directory update in near memory to the S state event=0x21,umask=0x142 01 unc_b2cmi_directory_update.i2a uncore interconnect Any I2A Transition event=0x21,umask=0x304 01 unc_b2cmi_directory_update.i2s uncore interconnect Any I2S Transition event=0x21,umask=0x302 01 unc_b2cmi_directory_update.miss_x2a uncore interconnect Directory update in far memory to the A state event=0x21,umask=0x214 01 unc_b2cmi_directory_update.miss_x2i uncore interconnect Directory update in far memory to the I state event=0x21,umask=0x228 01 unc_b2cmi_directory_update.miss_x2s uncore interconnect Directory update in far memory to the S state event=0x21,umask=0x242 01 unc_b2cmi_directory_update.s2a uncore interconnect Any S2A Transition event=0x21,umask=0x310 01 unc_b2cmi_directory_update.s2i uncore interconnect Any S2I Transition event=0x21,umask=0x308 01 unc_b2cmi_directory_update.x2a uncore interconnect Directory update to the A state event=0x21,umask=0x314 01 unc_b2cmi_directory_update.x2i uncore interconnect Directory update to the I state event=0x21,umask=0x328 01 unc_b2cmi_directory_update.x2s uncore interconnect Directory update to the S state event=0x21,umask=0x342 01 unc_b2cmi_imc_reads.to_ddr_as_cache uncore interconnect Count reads to NM region event=0x24,umask=0x110 01 unc_b2cmi_imc_writes.ni uncore interconnect Non-Inclusive - All Channels event=0x25 01 unc_b2cmi_imc_writes.ni_miss uncore interconnect Non-Inclusive Miss - All Channels event=0x25 01 unc_b2cmi_imc_writes.to_ddr_as_cache uncore interconnect DDR, acting as Cache - All Channels event=0x25,umask=0x140 01 unc_b2cmi_prefcam_inserts.ch0_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 0 event=0x56,umask=2 01 unc_b2cmi_prefcam_inserts.upi_allch uncore interconnect Prefetch CAM Inserts : UPI - All Channels event=0x56,umask=2 01 unc_b2cmi_tag_hit.all uncore interconnect Counts the 2lm reads and WRNI which were a hit event=0x1f,umask=0xf 01 unc_b2cmi_tag_hit.rd_clean uncore interconnect Counts the 2lm reads which were a hit clean event=0x1f,umask=1 01 unc_b2cmi_tag_hit.rd_dirty uncore interconnect Counts the 2lm reads which were a hit dirty event=0x1f,umask=2 01 unc_b2cmi_tag_hit.wr_clean uncore interconnect Counts the 2lm WRNI which were a hit clean event=0x1f,umask=4 01 unc_b2cmi_tag_hit.wr_dirty uncore interconnect Counts the 2lm WRNI which were a hit dirty event=0x1f,umask=8 01 unc_b2cmi_tag_miss.clean uncore interconnect Counts the 2lm second way read miss for a WrNI event=0x4b,umask=5 01 unc_b2cmi_tag_miss.dirty uncore interconnect Counts the 2lm second way read miss for a WrNI event=0x4b,umask=0xa 01 unc_b2cmi_tag_miss.rd_2way uncore interconnect Counts the 2lm second way read miss for a Rd event=0x4b,umask=0x10 01 unc_b2cmi_tag_miss.rd_clean uncore interconnect Counts the 2lm reads which were a miss and the cache line is unmodified event=0x4b,umask=1 01 unc_b2cmi_tag_miss.rd_dirty uncore interconnect Counts the 2lm reads which were a miss and the cache line is modified event=0x4b,umask=2 01 unc_b2cmi_tag_miss.wr_2way uncore interconnect Counts the 2lm second way read miss for a WrNI event=0x4b,umask=0x20 01 unc_b2cmi_tag_miss.wr_clean uncore interconnect Counts the 2lm WRNI which were a miss and the cache line is unmodified event=0x4b,umask=4 01 unc_b2cmi_tag_miss.wr_dirty uncore interconnect Counts the 2lm WRNI which were a miss and the cache line is modified event=0x4b,umask=8 01 uncore_b2hot unc_b2hot_clockticks uncore interconnect UNC_B2HOT_CLOCKTICKS event=1,umask=1 01 Clockticks for the B2HOT unit uncore_b2upi unc_b2upi_clockticks uncore interconnect Number of uclks in domain event=1 01 unc_mdf_clockticks uncore interconnect MDF Clockticks event=1 01 unc_mdf_rxr_bypass.ad_bnc uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=1 01 unc_mdf_rxr_bypass.ad_crd uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=0x10 01 unc_mdf_rxr_bypass.ak uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=2 01 unc_mdf_rxr_bypass.bl_bnc uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=4 01 unc_mdf_rxr_bypass.bl_crd uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=0x20 01 unc_mdf_rxr_bypass.iv uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=8 01 unc_mdf_rxr_inserts.ad_bnc uncore interconnect Number of allocations into the Ingress used to queue up requests from the mesh (AD_BNC) event=0x12,umask=1 01 unc_mdf_rxr_inserts.ad_crd uncore interconnect Number of allocations into the Ingress used to queue up requests from the mesh (AD) event=0x12,umask=0x10 01 unc_mdf_rxr_inserts.ak uncore interconnect Number of allocations into the Ingress used to queue up requests from the mesh (AK) event=0x12,umask=2 01 unc_mdf_rxr_inserts.bl_bnc uncore interconnect Number of allocations into the Ingress used to queue up requests from the mesh (BL_BNC) event=0x12,umask=4 01 unc_mdf_rxr_inserts.bl_crd uncore interconnect Number of allocations into the Ingress used to queue up requests from the mesh (BL_CRD) event=0x12,umask=0x20 01 unc_mdf_rxr_inserts.iv uncore interconnect Number of allocations into the Ingress used to queue up requests from the mesh (IV) event=0x12,umask=8 01 unc_mdf_rxr_occupancy.ad_bnc uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=1 01 unc_mdf_rxr_occupancy.ad_crd uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=0x10 01 unc_mdf_rxr_occupancy.ak uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=2 01 unc_mdf_rxr_occupancy.bl_bnc uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=4 01 unc_mdf_rxr_occupancy.bl_crd uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=0x20 01 unc_mdf_rxr_occupancy.iv uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=8 01 unc_mdf_txr_bypass.ad_bnc uncore interconnect Egress bypasses for for AD_BNC event=0x1e,umask=1 01 unc_mdf_txr_bypass.ad_crd uncore interconnect Egress bypasses for for AD_CRD event=0x1e,umask=0x10 01 unc_mdf_txr_bypass.ak uncore interconnect Egress bypasses for for AK event=0x1e,umask=2 01 unc_mdf_txr_bypass.bl_bnc uncore interconnect Egress bypasses for for BL_BNC event=0x1e,umask=4 01 unc_mdf_txr_bypass.bl_crd uncore interconnect Egress bypasses for for BL_CRD event=0x1e,umask=0x20 01 unc_mdf_txr_bypass.iv uncore interconnect Egress bypasses for for IV event=0x1e,umask=8 01 unc_mdf_txr_inserts.ad_bnc uncore interconnect Number of egress inserts for for AD_BNC event=0x1c,umask=1 01 unc_mdf_txr_inserts.ad_crd uncore interconnect Number of egress inserts for for AD_CRD event=0x1c,umask=0x10 01 unc_mdf_txr_inserts.ak uncore interconnect Number of egress inserts for for AK event=0x1c,umask=2 01 unc_mdf_txr_inserts.bl_bnc uncore interconnect Number of egress inserts for for BL_BNC event=0x1c,umask=4 01 unc_mdf_txr_inserts.bl_crd uncore interconnect Number of egress inserts for for BL_CRD event=0x1c,umask=0x20 01 unc_mdf_txr_inserts.iv uncore interconnect Number of egress inserts for for IV event=0x1c,umask=8 01 unc_mdf_txr_occupancy.ad_bnc uncore interconnect Egress occupancy for for AD_BNC event=0x1d,umask=1 01 unc_mdf_txr_occupancy.ad_crd uncore interconnect Egress occupancy for for AD_CRD event=0x1d,umask=0x10 01 unc_mdf_txr_occupancy.ak uncore interconnect Egress occupancy for for AK event=0x1d,umask=2 01 unc_mdf_txr_occupancy.bl_bnc uncore interconnect Egress occupancy for for BL_BNC event=0x1d,umask=4 01 unc_mdf_txr_occupancy.bl_crd uncore interconnect Egress occupancy for for BL_CRD event=0x1d,umask=0x20 01 unc_mdf_txr_occupancy.iv uncore interconnect Egress occupancy for for IV event=0x1d,umask=8 01 unc_upi_clockticks uncore interconnect Number of UPI LL clock cycles while the event is enabled event=1 01 Number of kfclks unc_upi_l1_power_cycles uncore interconnect Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode event=0x21 01 unc_upi_rxl_basic_hdr_match.ncb uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Bypass event=5,umask=0xe 01 unc_upi_rxl_basic_hdr_match.ncb_opc uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode event=5,umask=0x10e 01 unc_upi_rxl_basic_hdr_match.ncs uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Standard event=5,umask=0xf 01 unc_upi_rxl_basic_hdr_match.ncs_opc uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode event=5,umask=0x10f 01 unc_upi_rxl_basic_hdr_match.req uncore interconnect Matches on Receive path of a UPI Port : Request event=5,umask=8 01 unc_upi_rxl_basic_hdr_match.req_opc uncore interconnect Matches on Receive path of a UPI Port : Request, Match Opcode event=5,umask=0x108 01 unc_upi_rxl_basic_hdr_match.rspcnflt uncore interconnect Matches on Receive path of a UPI Port : Response - Conflict event=5,umask=0x1aa 01 unc_upi_rxl_basic_hdr_match.rspi uncore interconnect Matches on Receive path of a UPI Port : Response - Invalid event=5,umask=0x12a 01 unc_upi_rxl_basic_hdr_match.rsp_data uncore interconnect Matches on Receive path of a UPI Port : Response - Data event=5,umask=0xc 01 unc_upi_rxl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Receive path of a UPI Port : Response - Data, Match Opcode event=5,umask=0x10c 01 unc_upi_rxl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Receive path of a UPI Port : Response - No Data event=5,umask=0xa 01 unc_upi_rxl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Receive path of a UPI Port : Response - No Data, Match Opcode event=5,umask=0x10a 01 unc_upi_rxl_basic_hdr_match.snp uncore interconnect Matches on Receive path of a UPI Port : Snoop event=5,umask=9 01 unc_upi_rxl_basic_hdr_match.snp_opc uncore interconnect Matches on Receive path of a UPI Port : Snoop, Match Opcode event=5,umask=0x109 01 unc_upi_rxl_basic_hdr_match.wb uncore interconnect Matches on Receive path of a UPI Port : Writeback event=5,umask=0xd 01 unc_upi_rxl_basic_hdr_match.wb_opc uncore interconnect Matches on Receive path of a UPI Port : Writeback, Match Opcode event=5,umask=0x10d 01 unc_upi_rxl_flits.all_data uncore interconnect Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c) event=3,umask=0xf 01 unc_upi_rxl_flits.all_null uncore interconnect Null FLITs received from any slot event=3,umask=0x27 01 Valid Flits Received : Null FLITs received from any slot unc_upi_rxl_flits.data uncore interconnect Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. event=3,umask=8 01 unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c) event=3,umask=0x47 01 unc_upi_rxl_flits.llcrd uncore interconnect Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 event=3,umask=0x10 01 unc_upi_rxl_flits.llctrl uncore interconnect Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages event=3,umask=0x40 01 unc_upi_rxl_flits.non_data uncore interconnect Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c) event=3,umask=0x97 01 unc_upi_rxl_flits.null uncore interconnect Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2 event=3,umask=0x20 01 unc_upi_rxl_flits.prothdr uncore interconnect Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) event=3,umask=0x80 01 unc_upi_rxl_flits.slot0 uncore interconnect Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count event=3,umask=1 01 unc_upi_rxl_flits.slot1 uncore interconnect Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count event=3,umask=2 01 unc_upi_rxl_flits.slot2 uncore interconnect Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count event=3,umask=4 01 unc_upi_rxl_inserts.slot0 uncore interconnect RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime event=0x30,umask=1 01 unc_upi_rxl_inserts.slot1 uncore interconnect RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime event=0x30,umask=2 01 unc_upi_rxl_inserts.slot2 uncore interconnect RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime event=0x30,umask=4 01 unc_upi_rxl_occupancy.slot0 uncore interconnect RxQ Occupancy - All Packets : Slot 0 event=0x32,umask=1 01 unc_upi_rxl_occupancy.slot1 uncore interconnect RxQ Occupancy - All Packets : Slot 1 event=0x32,umask=2 01 unc_upi_rxl_occupancy.slot2 uncore interconnect RxQ Occupancy - All Packets : Slot 2 event=0x32,umask=4 01 unc_upi_txl_basic_hdr_match.ncb uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Bypass event=4,umask=0xe 01 unc_upi_txl_basic_hdr_match.ncb_opc uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode event=4,umask=0x10e 01 unc_upi_txl_basic_hdr_match.ncs uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Standard event=4,umask=0xf 01 unc_upi_txl_basic_hdr_match.ncs_opc uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode event=4,umask=0x10f 01 unc_upi_txl_basic_hdr_match.req uncore interconnect Matches on Transmit path of a UPI Port : Request event=4,umask=8 01 unc_upi_txl_basic_hdr_match.req_opc uncore interconnect Matches on Transmit path of a UPI Port : Request, Match Opcode event=4,umask=0x108 01 unc_upi_txl_basic_hdr_match.rspcnflt uncore interconnect Matches on Transmit path of a UPI Port : Response - Conflict event=4,umask=0x1aa 01 unc_upi_txl_basic_hdr_match.rspi uncore interconnect Matches on Transmit path of a UPI Port : Response - Invalid event=4,umask=0x12a 01 unc_upi_txl_basic_hdr_match.rsp_data uncore interconnect Matches on Transmit path of a UPI Port : Response - Data event=4,umask=0xc 01 unc_upi_txl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Transmit path of a UPI Port : Response - Data, Match Opcode event=4,umask=0x10c 01 unc_upi_txl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Transmit path of a UPI Port : Response - No Data event=4,umask=0xa 01 unc_upi_txl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode event=4,umask=0x10a 01 unc_upi_txl_basic_hdr_match.snp uncore interconnect Matches on Transmit path of a UPI Port : Snoop event=4,umask=9 01 unc_upi_txl_basic_hdr_match.snp_opc uncore interconnect Matches on Transmit path of a UPI Port : Snoop, Match Opcode event=4,umask=0x109 01 unc_upi_txl_basic_hdr_match.wb uncore interconnect Matches on Transmit path of a UPI Port : Writeback event=4,umask=0xd 01 unc_upi_txl_basic_hdr_match.wb_opc uncore interconnect Matches on Transmit path of a UPI Port : Writeback, Match Opcode event=4,umask=0x10d 01 unc_upi_txl_flits.all_data uncore interconnect Valid Flits Sent : All Data : Counts number of data flits across this UPI link event=2,umask=0xf 01 unc_upi_txl_flits.all_null uncore interconnect All Null Flits event=2,umask=0x27 01 Valid Flits Sent : Idle unc_upi_txl_flits.data uncore interconnect Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. event=2,umask=8 01 unc_upi_txl_flits.idle uncore interconnect Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c) event=2,umask=0x47 01 unc_upi_txl_flits.llcrd uncore interconnect Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 event=2,umask=0x10 01 unc_upi_txl_flits.llctrl uncore interconnect Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages event=2,umask=0x40 01 unc_upi_txl_flits.non_data uncore interconnect Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c) event=2,umask=0x97 01 Valid Flits Sent : Null FLITs transmitted to any slot unc_upi_txl_flits.null uncore interconnect Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2 event=2,umask=0x20 01 unc_upi_txl_flits.prothdr uncore interconnect Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) event=2,umask=0x80 01 unc_upi_txl_flits.slot0 uncore interconnect Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count event=2,umask=1 01 unc_upi_txl_flits.slot1 uncore interconnect Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count event=2,umask=2 01 unc_upi_txl_flits.slot2 uncore interconnect Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count event=2,umask=4 01 unc_upi_txl_inserts uncore interconnect Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime event=0x40 01 unc_upi_txl_occupancy uncore interconnect Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ event=0x42 01 unc_iio_data_req_by_cpu.peer_read.all_parts uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0xff,fc_mask=7,umask=0x70ff008 01 unc_iio_data_req_by_cpu.peer_write.all_parts uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0xff,fc_mask=7,umask=0x70ff002 01 unc_iio_data_req_of_cpu.mem_read.all_parts uncore io Counts once for every 4 bytes read from this card to memory. This event does include reads to IO event=0x83,ch_mask=0xff,fc_mask=7,umask=0x70ff004 01 unc_iio_data_req_of_cpu.mem_write.all_parts uncore io Counts once for every 4 bytes written from this card to memory. This event does include writes to IO event=0x83,ch_mask=0xff,fc_mask=7,umask=0x70ff001 01 unc_iio_data_req_of_cpu.peer_read.part0 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=1,fc_mask=7,umask=0x7001008 01 unc_iio_data_req_of_cpu.peer_read.part1 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=2,fc_mask=7,umask=0x7002008 01 unc_iio_data_req_of_cpu.peer_read.part2 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=4,fc_mask=7,umask=0x7004008 01 unc_iio_data_req_of_cpu.peer_read.part3 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=8,fc_mask=7,umask=0x7008008 01 unc_iio_data_req_of_cpu.peer_read.part4 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=0x7010008 01 unc_iio_data_req_of_cpu.peer_read.part5 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=0x7020008 01 unc_iio_data_req_of_cpu.peer_read.part6 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=7,umask=0x7040008 01 unc_iio_data_req_of_cpu.peer_read.part7 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=7,umask=0x7080008 01 unc_iio_data_req_of_cpu.peer_write.all_parts uncore io Counts once for every 4 bytes written from this card to a peer device's IO space event=0x83,ch_mask=0xff,fc_mask=7,umask=0x70ff002 01 unc_iio_iommu0.all_lookups uncore io IOTLB lookups all event=0x40,umask=2 01 unc_iio_iommu1.num_mem_accesses_high uncore io IOMMU high priority memory access event=0x41,umask=0x80 01 unc_iio_iommu1.num_mem_accesses_low uncore io IOMMU low priority memory access event=0x41,umask=0x40 01 unc_iio_iommu1.slpwc_2m_hits uncore io Second Level Page Walk Cache Hit to a 2M page event=0x41,umask=2 01 unc_iio_iommu1.slpwc_cache_fills uncore io Second Level Page Walk Cache fill event=0x41,umask=0x20 01 unc_iio_iommu1.slpwc_cache_lookups uncore io Second Level Page Walk Cache lookup event=0x41,umask=1 01 unc_iio_iommu3.cyc_pwt_full uncore io Cycles PWT full event=0x43,umask=2 01 unc_iio_iommu3.int_cache_hits uncore io Interrupt Entry cache hit event=0x43,umask=0x80 01 unc_iio_iommu3.int_cache_lookups uncore io Interrupt Entry cache lookup event=0x43,umask=0x40 01 unc_iio_iommu3.num_inval_ctxt_cache uncore io Context Cache invalidation events event=0x43,umask=8 01 unc_iio_iommu3.num_inval_int_cache uncore io Interrupt Entry Cache invalidation events event=0x43,umask=0x20 01 unc_iio_iommu3.num_inval_iotlb uncore io IOTLB invalidation events event=0x43,umask=4 01 unc_iio_iommu3.num_inval_pasid_cache uncore io PASID Cache invalidation events event=0x43,umask=0x10 01 unc_iio_num_oustanding_req_from_cpu.to_io uncore io Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing event=0xc5,ch_mask=0xff,fc_mask=7,umask=0x70ff008 01 unc_iio_num_outstanding_req_of_cpu.data uncore io Passing data to be written event=0x88,ch_mask=0xff,fc_mask=7,umask=0x700f020 01 unc_iio_num_outstanding_req_of_cpu.final_rd_wr uncore io Issuing final read or write of line event=0x88,ch_mask=0xff,fc_mask=7,umask=0x700f008 01 unc_iio_num_outstanding_req_of_cpu.iommu_hit uncore io Processing response from IOMMU event=0x88,ch_mask=0xff,fc_mask=7,umask=0x700f002 01 unc_iio_num_outstanding_req_of_cpu.iommu_req uncore io Issuing to IOMMU event=0x88,ch_mask=0xff,fc_mask=7,umask=0x700f001 01 unc_iio_num_outstanding_req_of_cpu.req_own uncore io Request Ownership event=0x88,ch_mask=0xff,fc_mask=7,umask=0x700f004 01 unc_iio_num_outstanding_req_of_cpu.wr uncore io Writing line event=0x88,ch_mask=0xff,fc_mask=7,umask=0x700f010 01 unc_iio_num_req_of_cpu_by_tgt.rem_p2p uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x70ff010 01 unc_iio_txn_req_by_cpu.mem_read.all_parts uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0xff,fc_mask=7,umask=0x70ff004 01 unc_iio_txn_req_by_cpu.mem_write.all_parts uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0xff,fc_mask=7,umask=0x70ff001 01 unc_iio_txn_req_by_cpu.peer_read.all_parts uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0xff,fc_mask=7,umask=0x70ff008 01 unc_iio_txn_req_by_cpu.peer_write.all_parts uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0xff,fc_mask=7,umask=0x70ff002 01 unc_iio_txn_req_of_cpu.peer_read.part0 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=1,fc_mask=7,umask=0x7001008 01 unc_iio_txn_req_of_cpu.peer_read.part1 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=2,fc_mask=7,umask=0x7002008 01 unc_iio_txn_req_of_cpu.peer_read.part2 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=4,fc_mask=7,umask=0x7004008 01 unc_iio_txn_req_of_cpu.peer_read.part3 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=8,fc_mask=7,umask=0x7008008 01 unc_iio_txn_req_of_cpu.peer_read.part4 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=0x7010008 01 unc_iio_txn_req_of_cpu.peer_read.part5 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=0x7020008 01 unc_iio_txn_req_of_cpu.peer_read.part6 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x40,fc_mask=7,umask=0x7040008 01 unc_iio_txn_req_of_cpu.peer_read.part7 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x80,fc_mask=7,umask=0x7080008 01 l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=1 00 This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache l1d_pend_miss.pending cache L1D miss outstanding duration in cycles event=0x48,period=2000003,umask=1 00 Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=2000003,umask=1 00 l1d_pend_miss.request_fb_full cache Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e event=0x48,period=2000003,umask=2 00 l2_demand_rqsts.wb_hit cache Not rejected writebacks that hit L2 cache event=0x27,period=200003,umask=0x50 00 Not rejected writebacks that hit L2 cache l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=7 00 This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss l2_lines_in.e cache L2 cache lines in E state filling L2 event=0xf1,period=100003,umask=4 00 L2 cache lines in E state filling L2 l2_lines_in.i cache L2 cache lines in I state filling L2 event=0xf1,period=100003,umask=1 00 L2 cache lines in I state filling L2 l2_lines_in.s cache L2 cache lines in S state filling L2 event=0xf1,period=100003,umask=2 00 L2 cache lines in S state filling L2 l2_lines_out.demand_clean cache Clean L2 cache lines evicted by demand event=0xf2,period=100003,umask=5 00 Clean L2 cache lines evicted by demand l2_lines_out.demand_dirty cache Dirty L2 cache lines evicted by demand event=0xf2,period=100003,umask=6 00 Dirty L2 cache lines evicted by demand l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0xe4 00 Counts all L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read requests Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xe1 00 Counts any demand and L1 HW prefetch data load requests to L2 Spec update: HSD78, HSM80 l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0x27 00 Demand requests that miss L2 cache Spec update: HSD78, HSM80 l2_rqsts.all_demand_references cache Demand requests to L2 cache Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xe7 00 Demand requests to L2 cache Spec update: HSD78, HSM80 l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xf8 00 Counts all L2 HW prefetcher requests l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xe2 00 Counts all L2 store RFO requests l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0xc4 00 Number of instruction fetches that hit the L2 cache l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x24 00 Number of instruction fetches that missed the L2 cache l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xc1 00 Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache Spec update: HSD78, HSM80 l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2, no rejects Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0x21 00 Demand data read requests that missed L2, no rejects Spec update: HSD78, HSM80 l2_rqsts.l2_pf_hit cache L2 prefetch requests that hit L2 cache event=0x24,period=200003,umask=0xd0 00 Counts all L2 HW prefetcher requests that hit L2 l2_rqsts.l2_pf_miss cache L2 prefetch requests that miss L2 cache event=0x24,period=200003,umask=0x30 00 Counts all L2 HW prefetcher requests that missed L2 l2_rqsts.miss cache All requests that miss L2 cache Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0x3f 00 All requests that missed L2 Spec update: HSD78, HSM80 l2_rqsts.references cache All L2 requests Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xff 00 All requests to L2 cache Spec update: HSD78, HSM80 l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0xc2 00 Counts the number of store RFO requests that hit the L2 cache l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x22 00 Counts the number of store RFO requests that miss the L2 cache l2_trans.all_pf cache L2 or L3 HW prefetches that access L2 cache event=0xf0,period=200003,umask=8 00 Any MLC or L3 HW prefetch accessing L2, including rejects l2_trans.all_requests cache Transactions accessing L2 pipe event=0xf0,period=200003,umask=0x80 00 Transactions accessing L2 pipe l2_trans.code_rd cache L2 cache accesses when fetching instructions event=0xf0,period=200003,umask=4 00 L2 cache accesses when fetching instructions l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=1 00 Demand data read requests that access L2 cache l2_trans.l1d_wb cache L1D writebacks that access L2 cache event=0xf0,period=200003,umask=0x10 00 L1D writebacks that access L2 cache l2_trans.l2_fill cache L2 fill requests that access L2 cache event=0xf0,period=200003,umask=0x20 00 L2 fill requests that access L2 cache l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40 00 L2 writebacks that access L2 cache l2_trans.rfo cache RFO requests that access L2 cache event=0xf0,period=200003,umask=2 00 RFO requests that access L2 cache lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x63,period=2000003,umask=2 00 Cycles in which the L1D is locked longest_lat_cache.miss cache Core-originated cacheable demand requests missed L3 event=0x2e,period=100003,umask=0x41 00 This event counts each cache miss condition for references to the last level cache longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to L3 event=0x2e,period=100003,umask=0x4f 00 This event counts requests originating from the core that reference a cache line in the last level cache mem_load_uops_l3_hit_retired.xsnp_hit cache Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=20011,umask=2 00 mem_load_uops_l3_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared L3 Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=20011,umask=4 00 mem_load_uops_l3_hit_retired.xsnp_miss cache Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=20011,umask=1 00 mem_load_uops_l3_hit_retired.xsnp_none cache Retired load uops which data sources were hits in L3 without snoops required Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=100003,umask=8 00 mem_load_uops_l3_miss_retired.local_dram cache Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) event=0xd3,period=100003,umask=1 00 This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise. Spec update: HSM30 (Precise event) event=0xd1,period=100003,umask=0x40 00 mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd1,period=2000003,umask=1 00 mem_load_uops_retired.l1_miss cache Retired load uops misses in L1 cache as data sources Supports address when precise. Spec update: HSM30 (Precise event) event=0xd1,period=100003,umask=8 00 Retired load uops missed L1 cache as data sources Supports address when precise. Spec update: HSM30 (Precise event) mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources Supports address when precise. Spec update: HSD76, HSD29, HSM30 (Precise event) event=0xd1,period=100003,umask=2 00 mem_load_uops_retired.l2_miss cache Miss in mid-level (L2) cache. Excludes Unknown data-source Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd1,period=50021,umask=0x10 00 Retired load uops missed L2. Unknown data source excluded Supports address when precise. Spec update: HSD29, HSM30 (Precise event) mem_load_uops_retired.l3_hit cache Retired load uops which data sources were data hits in L3 without snoops required Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd1,period=50021,umask=4 00 Retired load uops with L3 cache hits as data sources Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) mem_load_uops_retired.l3_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd1,period=100003,umask=0x20 00 Retired load uops missed L3. Excludes unknown data source Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) mem_uops_retired.all_loads cache Retired load uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=2000003,umask=0x81 00 Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW Supports address when precise. Spec update: HSD29, HSM30 (Precise event) mem_uops_retired.all_stores cache Retired store uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=2000003,umask=0x82 00 Counts all retired store uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access Supports address when precise. Spec update: HSD76, HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x21 00 mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x41 00 mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x42 00 mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x11 00 mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x12 00 offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=8 00 Data read requests sent to uncore (demand and prefetch) offcore_requests.demand_code_rd cache Cacheable and noncacheable code read requests event=0xb0,period=100003,umask=2 00 Demand code read requests sent to uncore offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore Spec update: HSD78, HSM80 event=0xb0,period=100003,umask=1 00 Demand data read requests sent to uncore Spec update: HSD78, HSM80 offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=4 00 Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM offcore_requests_buffer.sq_full cache Offcore requests buffer cannot take more entries for this thread core event=0xb2,period=2000003,umask=1 00 offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61, HSM63 event=0x60,period=2000003,umask=8 00 Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61, HSM63 offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61, HSM63 event=0x60,cmask=1,period=2000003,umask=8 00 offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 event=0x60,cmask=1,period=2000003,umask=1 00 offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: HSD62, HSD61, HSM63 event=0x60,cmask=1,period=2000003,umask=4 00 offcore_requests_outstanding.demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: HSD62, HSD61, HSM63 event=0x60,period=2000003,umask=2 00 Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61, HSM63 offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 event=0x60,period=2000003,umask=1 00 Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 event=0x60,cmask=6,period=2000003,umask=1 00 offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61, HSM63 event=0x60,period=2000003,umask=4 00 Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61, HSM63 offcore_response.all_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0244 00 offcore_response.all_data_rd.l3_hit.hitm_other_core cache Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0091 00 offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0091 00 offcore_response.all_reads.l3_hit.hitm_other_core cache hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C07F7 00 offcore_response.all_reads.l3_hit.hit_other_core_no_fwd cache hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C07F7 00 offcore_response.all_requests.l3_hit.any_response cache Counts all requests hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C8FFF 00 offcore_response.all_rfo.l3_hit.hitm_other_core cache Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122 00 offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122 00 offcore_response.demand_code_rd.l3_hit.hitm_other_core cache Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004 00 offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004 00 offcore_response.demand_data_rd.l3_hit.hitm_other_core cache Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 00 offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd cache Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 00 offcore_response.demand_rfo.l3_hit.hitm_other_core cache Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002 00 offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002 00 offcore_response.pf_l2_code_rd.l3_hit.any_response cache Counts all prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0040 00 offcore_response.pf_l2_data_rd.l3_hit.any_response cache Counts prefetch (that bring data to L2) data reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010 00 offcore_response.pf_l2_rfo.l3_hit.any_response cache Counts all prefetch (that bring data to L2) RFOs hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020 00 offcore_response.pf_l3_code_rd.l3_hit.any_response cache Counts prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0200 00 offcore_response.pf_l3_data_rd.l3_hit.any_response cache Counts all prefetch (that bring data to LLC only) data reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080 00 offcore_response.pf_l3_rfo.l3_hit.any_response cache Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100 00 sq_misc.split_lock cache Split locks in SQ event=0xf4,period=100003,umask=0x10 00 avx_insts.all floating point Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX event=0xc6,period=2000003,umask=7 00 Note that a whole rep string only counts AVX_INST.ALL once fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e 00 Cycles with any input/output SSE* or FP assists fp_assist.simd_input floating point Number of SIMD FP assists due to input values event=0xca,period=100003,umask=0x10 00 Number of SIMD FP assists due to input values fp_assist.simd_output floating point Number of SIMD FP assists due to Output values event=0xca,period=100003,umask=8 00 Number of SIMD FP assists due to output values fp_assist.x87_input floating point Number of X87 assists due to input value event=0xca,period=100003,umask=4 00 Number of X87 FP assists due to input values fp_assist.x87_output floating point Number of X87 assists due to output value event=0xca,period=100003,umask=2 00 Number of X87 FP assists due to output values move_elimination.simd_eliminated floating point Number of SIMD Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=2 00 Number of SIMD move elimination candidate uops that were eliminated move_elimination.simd_not_eliminated floating point Number of SIMD Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=8 00 Number of SIMD move elimination candidate uops that were not eliminated other_assists.avx_to_sse floating point Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: HSD56, HSM57 event=0xc1,period=100003,umask=8 00 other_assists.sse_to_avx floating point Number of transitions from SSE to AVX-256 when penalty applicable Spec update: HSD56, HSM57 event=0xc1,period=100003,umask=0x10 00 baclears.any frontend Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end event=0xe6,period=100003,umask=0x1f 00 Number of front end re-steers due to BPU misprediction dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=2 00 icache.hit frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches event=0x80,period=2000003,umask=1 00 icache.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction-cache miss event=0x80,period=2000003,umask=4 00 icache.ifetch_stall frontend Cycles where a code fetch is stalled due to L1 instruction-cache miss event=0x80,period=2000003,umask=4 00 icache.misses frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses event=0x80,period=200003,umask=2 00 This event counts Instruction Cache (ICACHE) misses idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x18 00 Counts cycles DSB is delivered four uops. Set Cmask = 4 idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x18 00 Counts cycles DSB is delivered at least one uops. Set Cmask = 1 idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24 00 Counts cycles MITE is delivered four uops. Set Cmask = 4 idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24 00 Counts cycles MITE is delivered at least one uop. Set Cmask = 1 idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=8 00 idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=8 00 Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles idq.empty frontend Instruction Decode Queue (IDQ) empty cycles Spec update: HSD135 event=0x79,period=2000003,umask=2 00 Counts cycles the IDQ is empty Spec update: HSD135 idq.mite_all_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x3c 00 Number of uops delivered to IDQ from any path idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=4 00 idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=4 00 Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10 00 idq.ms_dsb_occur frontend Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,edge=1,period=2000003,umask=0x10 00 idq.ms_dsb_uops frontend Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x10 00 Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20 00 Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30 00 This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled Spec update: HSD135 event=0x9c,period=2000003,umask=1 00 This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis Spec update: HSD135 idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Spec update: HSD135 event=0x9c,cmask=4,period=2000003,umask=1 00 This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis Spec update: HSD135 idq_uops_not_delivered.cycles_fe_was_ok frontend Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE Spec update: HSD135 event=0x9c,cmask=1,inv=1,period=2000003,umask=1 00 idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Spec update: HSD135 event=0x9c,cmask=3,period=2000003,umask=1 00 idq_uops_not_delivered.cycles_le_2_uop_deliv.core frontend Cycles with less than 2 uops delivered by the front end Spec update: HSD135 event=0x9c,cmask=2,period=2000003,umask=1 00 idq_uops_not_delivered.cycles_le_3_uop_deliv.core frontend Cycles with less than 3 uops delivered by the front end Spec update: HSD135 event=0x9c,cmask=1,period=2000003,umask=1 00 hle_retired.aborted memory Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event) event=0xc8,period=2000003,umask=4 00 hle_retired.aborted_misc1 memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=2000003,umask=8 00 hle_retired.aborted_misc2 memory Number of times an HLE execution aborted due to uncommon conditions event=0xc8,period=2000003,umask=0x10 00 hle_retired.aborted_misc3 memory Number of times an HLE execution aborted due to HLE-unfriendly instructions event=0xc8,period=2000003,umask=0x20 00 hle_retired.aborted_misc4 memory Number of times an HLE execution aborted due to incompatible memory type Spec update: HSD65 event=0xc8,period=2000003,umask=0x40 00 hle_retired.aborted_misc5 memory Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) event=0xc8,period=2000003,umask=0x80 00 Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) hle_retired.commit memory Number of times an HLE execution successfully committed event=0xc8,period=2000003,umask=2 00 hle_retired.start memory Number of times an HLE execution started event=0xc8,period=2000003,umask=1 00 machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=2 00 This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently mem_trans_retired.load_latency_gt_128 memory Randomly selected loads with latency value being above 128 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=1009,umask=1,ldlat=0x80 00 mem_trans_retired.load_latency_gt_16 memory Randomly selected loads with latency value being above 16 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=20011,umask=1,ldlat=0x10 00 mem_trans_retired.load_latency_gt_256 memory Randomly selected loads with latency value being above 256 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=503,umask=1,ldlat=0x100 00 mem_trans_retired.load_latency_gt_32 memory Randomly selected loads with latency value being above 32 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x20 00 mem_trans_retired.load_latency_gt_4 memory Randomly selected loads with latency value being above 4 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x4 00 mem_trans_retired.load_latency_gt_512 memory Randomly selected loads with latency value being above 512 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=101,umask=1,ldlat=0x200 00 mem_trans_retired.load_latency_gt_64 memory Randomly selected loads with latency value being above 64 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=2003,umask=1,ldlat=0x40 00 mem_trans_retired.load_latency_gt_8 memory Randomly selected loads with latency value being above 8 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=50021,umask=1,ldlat=0x8 00 misalign_mem_ref.loads memory Speculative cache line split load uops dispatched to L1 cache event=5,period=2000003,umask=1 00 Speculative cache-line split load uops dispatched to L1D misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=5,period=2000003,umask=2 00 Speculative cache-line split store-address uops dispatched to L1D offcore_response.all_code_rd.l3_miss.any_response memory Counts all demand & prefetch code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00244 00 offcore_response.all_code_rd.l3_miss.local_dram memory Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400244 00 offcore_response.all_data_rd.l3_miss.any_response memory Counts all demand & prefetch data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00091 00 offcore_response.all_data_rd.l3_miss.local_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400091 00 offcore_response.all_reads.l3_miss.any_response memory miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC007F7 00 offcore_response.all_reads.l3_miss.local_dram memory miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x1004007F7 00 offcore_response.all_requests.l3_miss.any_response memory Counts all requests miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC08FFF 00 offcore_response.all_rfo.l3_miss.any_response memory Counts all demand & prefetch RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00122 00 offcore_response.all_rfo.l3_miss.local_dram memory Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400122 00 offcore_response.demand_code_rd.l3_miss.any_response memory Counts all demand code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00004 00 offcore_response.demand_code_rd.l3_miss.local_dram memory Counts all demand code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400004 00 offcore_response.demand_data_rd.l3_miss.any_response memory Counts demand data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00001 00 offcore_response.demand_data_rd.l3_miss.local_dram memory Counts demand data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400001 00 offcore_response.demand_rfo.l3_miss.any_response memory Counts all demand data writes (RFOs) miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00002 00 offcore_response.demand_rfo.l3_miss.local_dram memory Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400002 00 offcore_response.pf_l2_code_rd.l3_miss.any_response memory Counts all prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00040 00 offcore_response.pf_l2_data_rd.l3_miss.any_response memory Counts prefetch (that bring data to L2) data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00010 00 offcore_response.pf_l2_rfo.l3_miss.any_response memory Counts all prefetch (that bring data to L2) RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00020 00 offcore_response.pf_l3_code_rd.l3_miss.any_response memory Counts prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00200 00 offcore_response.pf_l3_data_rd.l3_miss.any_response memory Counts all prefetch (that bring data to LLC only) data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00080 00 offcore_response.pf_l3_rfo.l3_miss.any_response memory Counts all prefetch (that bring data to LLC only) RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00100 00 rtm_retired.aborted memory Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Must be precise) event=0xc9,period=2000003,umask=4 00 rtm_retired.aborted_misc1 memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=2000003,umask=8 00 Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) rtm_retired.aborted_misc2 memory Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc9,period=2000003,umask=0x10 00 rtm_retired.aborted_misc3 memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=2000003,umask=0x20 00 rtm_retired.aborted_misc4 memory Number of times an RTM execution aborted due to incompatible memory type Spec update: HSD65 event=0xc9,period=2000003,umask=0x40 00 rtm_retired.aborted_misc5 memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=2000003,umask=0x80 00 Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) rtm_retired.commit memory Number of times an RTM execution successfully committed event=0xc9,period=2000003,umask=2 00 rtm_retired.start memory Number of times an RTM execution started event=0xc9,period=2000003,umask=1 00 tx_exec.misc2 memory Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region event=0x5d,period=2000003,umask=2 00 tx_exec.misc3 memory Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded event=0x5d,period=2000003,umask=4 00 tx_exec.misc4 memory Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region event=0x5d,period=2000003,umask=8 00 tx_mem.abort_capacity_write memory Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes event=0x54,period=2000003,umask=2 00 tx_mem.abort_conflict memory Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address event=0x54,period=2000003,umask=1 00 tx_mem.abort_hle_elision_buffer_mismatch memory Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer event=0x54,period=2000003,umask=0x10 00 tx_mem.abort_hle_elision_buffer_not_empty memory Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero event=0x54,period=2000003,umask=8 00 tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer event=0x54,period=2000003,umask=0x20 00 tx_mem.abort_hle_store_to_elided_lock memory Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer event=0x54,period=2000003,umask=4 00 tx_mem.hle_elision_buffer_full memory Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero event=0x54,period=2000003,umask=0x40 00 cpl_cycles.ring0 other Unhalted core cycles when the thread is in ring 0 event=0x5c,period=2000003,umask=1 00 Unhalted core cycles when the thread is in ring 0 cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100003,umask=1 00 cpl_cycles.ring123 other Unhalted core cycles when thread is in rings 1, 2, or 3 event=0x5c,period=2000003,umask=2 00 Unhalted core cycles when the thread is not in ring 0 lock_cycles.split_lock_uc_lock_duration other Cycles when L1 and L2 are locked due to UC or split lock event=0x63,period=2000003,umask=1 00 Cycles in which the L1D and L2 are locked, due to a UC lock or split lock arith.divider_uops pipeline Any uop executed by the Divider. (This includes all divide uops, sqrt, ...) event=0x14,period=2000003,umask=2 00 br_inst_exec.all_branches pipeline Speculative and retired branches event=0x88,period=200003,umask=0xff 00 Counts all near executed branches (not necessarily retired) br_inst_exec.all_conditional pipeline Speculative and retired macro-conditional branches event=0x88,period=200003,umask=0xc1 00 br_inst_exec.all_direct_jmp pipeline Speculative and retired macro-unconditional branches excluding calls and indirects event=0x88,period=200003,umask=0xc2 00 br_inst_exec.all_direct_near_call pipeline Speculative and retired direct near calls event=0x88,period=200003,umask=0xd0 00 br_inst_exec.all_indirect_jump_non_call_ret pipeline Speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0xc4 00 br_inst_exec.all_indirect_near_return pipeline Speculative and retired indirect return branches event=0x88,period=200003,umask=0xc8 00 br_inst_exec.nontaken_conditional pipeline Not taken macro-conditional branches event=0x88,period=200003,umask=0x41 00 br_inst_exec.taken_conditional pipeline Taken speculative and retired macro-conditional branches event=0x88,period=200003,umask=0x81 00 br_inst_exec.taken_direct_jump pipeline Taken speculative and retired macro-conditional branch instructions excluding calls and indirects event=0x88,period=200003,umask=0x82 00 br_inst_exec.taken_direct_near_call pipeline Taken speculative and retired direct near calls event=0x88,period=200003,umask=0x90 00 br_inst_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0x84 00 br_inst_exec.taken_indirect_near_call pipeline Taken speculative and retired indirect calls event=0x88,period=200003,umask=0xa0 00 br_inst_exec.taken_indirect_near_return pipeline Taken speculative and retired indirect branches with return mnemonic event=0x88,period=200003,umask=0x88 00 br_inst_retired.all_branches pipeline All (macro) branch instructions retired event=0xc4,period=400009 00 Branch instructions at retirement br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired (Must be precise) event=0xc4,period=400009,umask=4 00 br_inst_retired.conditional pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=1 00 Counts the number of conditional branch instructions retired (Precise event) br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100003,umask=0x40 00 Number of far branches retired br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100003,umask=2 00 br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) event=0xc4,period=100003,umask=2 00 br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100003,umask=8 00 Counts the number of near return instructions retired (Precise event) br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20 00 Number of near taken branches retired (Precise event) br_inst_retired.not_taken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10 00 Counts the number of not taken branch instructions retired br_misp_exec.all_branches pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xff 00 Counts all near executed branches (not necessarily retired) br_misp_exec.all_conditional pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xc1 00 br_misp_exec.all_indirect_jump_non_call_ret pipeline Mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0xc4 00 br_misp_exec.nontaken_conditional pipeline Not taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x41 00 br_misp_exec.taken_conditional pipeline Taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x81 00 br_misp_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0x84 00 br_misp_exec.taken_return_near pipeline Taken speculative and retired mispredicted indirect branches with return mnemonic event=0x89,period=200003,umask=0x88 00 br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009 00 Mispredicted branch instructions at retirement br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired (Must be precise) event=0xc5,period=400009,umask=4 00 This event counts all mispredicted branch instructions retired. This is a precise event (Must be precise) br_misp_retired.conditional pipeline Mispredicted conditional branch instructions retired (Precise event) event=0xc5,period=400009,umask=1 00 br_misp_retired.near_taken pipeline number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20 00 Number of near branch instructions retired that were taken but mispredicted (Precise event) cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=1 00 Increments at the frequency of XCLK (100 MHz) when not halted cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=100003,umask=1 00 Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3 00 This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=1 00 Reference cycles when the thread is unhalted. (counts at 100 MHz rate) cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=100003,umask=1 00 Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003 00 This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state event=0x3c,period=2000003 00 Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling cycle_activity.cycles_l1d_pending pipeline Cycles with pending L1 cache miss loads event=0xa3,cmask=8,period=2000003,umask=8 00 Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle cycle_activity.cycles_l2_pending pipeline Cycles with pending L2 cache miss loads Spec update: HSD78, HSM63, HSM80 event=0xa3,cmask=1,period=2000003,umask=1 00 Cycles with pending L2 miss loads. Set Cmask=2 to count cycle Spec update: HSD78, HSM63, HSM80 cycle_activity.cycles_ldm_pending pipeline Cycles with pending memory loads event=0xa3,cmask=2,period=2000003,umask=2 00 Cycles with pending memory loads. Set Cmask=2 to count cycle cycle_activity.cycles_no_execute pipeline This event increments by 1 for every cycle where there was no execute for this thread event=0xa3,cmask=4,period=2000003,umask=4 00 This event counts cycles during which no instructions were executed in the execution stage of the pipeline cycle_activity.stalls_l1d_pending pipeline Execution stalls due to L1 data cache misses event=0xa3,cmask=12,period=2000003,umask=0xc 00 Execution stalls due to L1 data cache miss loads. Set Cmask=0CH cycle_activity.stalls_l2_pending pipeline Execution stalls due to L2 cache misses Spec update: HSM63, HSM80 event=0xa3,cmask=5,period=2000003,umask=5 00 Number of loads missed L2 Spec update: HSM63, HSM80 cycle_activity.stalls_ldm_pending pipeline Execution stalls due to memory subsystem event=0xa3,cmask=6,period=2000003,umask=6 00 This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data) ild_stall.iq_full pipeline Stall cycles because IQ is full event=0x87,period=2000003,umask=4 00 Stall cycles due to IQ is full ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction event=0x87,period=2000003,umask=1 00 This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP) inst_retired.any pipeline Instructions retired from execution Spec update: HSD140, HSD143 event=0xc0,period=2000003 00 This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions Spec update: HSD140, HSD143 inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event Spec update: HSD11, HSD140 event=0xc0,period=2000003 00 Number of instructions at retirement Spec update: HSD11, HSD140 inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: HSD140 (Must be precise) event=0xc0,period=2000003,umask=1 00 Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: HSD140 (Must be precise) inst_retired.x87 pipeline FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling event=0xc0,period=2000003,umask=2 00 This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) event=0xd,cmask=1,period=2000003,umask=3 00 This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc int_misc.recovery_cycles_any pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) event=0xd,any=1,cmask=1,period=2000003,umask=3 00 Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) ld_blocks.store_forward pipeline loads blocked by overlapping with store buffer that cannot be forwarded event=3,period=100003,umask=2 00 This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=7,period=100003,umask=1 00 Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact load_hit_pre.hw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for hardware prefetch event=0x4c,period=100003,umask=2 00 Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch load_hit_pre.sw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for software prefetch event=0x4c,period=100003,umask=1 00 Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=1 00 Number of uops delivered by the LSD machine_clears.cycles pipeline Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes event=0xc3,period=2000003,umask=1 00 machine_clears.maskmov pipeline This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 event=0xc3,period=100003,umask=0x20 00 machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=4 00 This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently move_elimination.int_eliminated pipeline Number of integer Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=1 00 Number of integer move elimination candidate uops that were eliminated move_elimination.int_not_eliminated pipeline Number of integer Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=4 00 Number of integer move elimination candidate uops that were not eliminated other_assists.any_wb_assist pipeline Number of times any microcode assist is invoked by HW upon uop writeback event=0xc1,period=100003,umask=0x40 00 Number of microcode assists invoked by HW upon uop writeback resource_stalls.any pipeline Resource-related stall cycles Spec update: HSD135 event=0xa2,period=2000003,umask=1 00 Cycles allocation is stalled due to resource related reason Spec update: HSD135 resource_stalls.rob pipeline Cycles stalled due to re-order buffer full event=0xa2,period=2000003,umask=0x10 00 resource_stalls.rs pipeline Cycles stalled due to no eligible RS entry available event=0xa2,period=2000003,umask=4 00 resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=8 00 This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available rob_misc_events.lbr_inserts pipeline Count cases of saving new LBR event=0xcc,period=2000003,umask=0x20 00 Count cases of saving new LBR records by hardware rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=1 00 This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end uops_dispatched_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=1 00 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=2 00 uops_dispatched_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=4 00 uops_dispatched_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=8 00 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10 00 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20 00 uops_dispatched_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40 00 uops_dispatched_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80 00 uops_executed.core pipeline Number of uops executed on the core Spec update: HSD30, HSM31 event=0xb1,period=2000003,umask=2 00 Counts total number of uops to be executed per-core each cycle Spec update: HSD30, HSM31 uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 event=0xb1,cmask=1,period=2000003,umask=2 00 uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 event=0xb1,cmask=2,period=2000003,umask=2 00 uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 event=0xb1,cmask=3,period=2000003,umask=2 00 uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 event=0xb1,cmask=4,period=2000003,umask=2 00 uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core Spec update: HSD30, HSM31 event=0xb1,inv=1,period=2000003,umask=2 00 uops_executed.cycles_ge_1_uop_exec pipeline Cycles where at least 1 uop was executed per-thread Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=1,period=2000003,umask=1 00 This events counts the cycles where at least one uop was executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 uops_executed.cycles_ge_2_uops_exec pipeline Cycles where at least 2 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=2,period=2000003,umask=1 00 This events counts the cycles where at least two uop were executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 uops_executed.cycles_ge_3_uops_exec pipeline Cycles where at least 3 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=3,period=2000003,umask=1 00 This events counts the cycles where at least three uop were executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 uops_executed.cycles_ge_4_uops_exec pipeline Cycles where at least 4 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=4,period=2000003,umask=1 00 uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=1,inv=1,period=2000003,umask=1 00 uops_executed_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=1 00 Cycles which a uop is dispatched on port 0 in this thread uops_executed_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=2 00 Cycles which a uop is dispatched on port 1 in this thread uops_executed_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=4 00 Cycles which a uop is dispatched on port 2 in this thread uops_executed_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=8 00 Cycles which a uop is dispatched on port 3 in this thread uops_executed_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10 00 Cycles which a uop is dispatched on port 4 in this thread uops_executed_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20 00 Cycles which a uop is dispatched on port 5 in this thread uops_executed_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40 00 Cycles which a uop is dispatched on port 6 in this thread uops_executed_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80 00 Cycles which a uop is dispatched on port 7 in this thread uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=1 00 This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops uops_issued.core_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads event=0xe,any=1,cmask=1,inv=1,period=2000003,umask=1 00 uops_issued.flags_merge pipeline Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch event=0xe,period=2000003,umask=0x10 00 Number of flags-merge uops allocated. Such uops add delay uops_issued.single_mul pipeline Number of Multiply packed/scalar single precision uops allocated event=0xe,period=2000003,umask=0x40 00 Number of multiply packed/scalar single precision uops allocated uops_issued.slow_lea pipeline Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not event=0xe,period=2000003,umask=0x20 00 Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=1 00 uops_retired.all pipeline Actually retired uops (Precise event) event=0xc2,period=2000003,umask=1 00 Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles (Precise event) uops_retired.core_stall_cycles pipeline Cycles without actually retired uops event=0xc2,any=1,cmask=1,inv=1,period=2000003,umask=1 00 uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=2 00 This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle (Precise event) uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=1 00 uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=16,inv=1,period=2000003,umask=1 00 unc_cbo_cache_lookup.any_es uncore cache L3 Lookup any request that access cache and found line in E or S-state event=0x34,umask=0x86 01 unc_cbo_cache_lookup.any_i uncore cache L3 Lookup any request that access cache and found line in I-state event=0x34,umask=0x88 01 unc_cbo_cache_lookup.any_m uncore cache L3 Lookup any request that access cache and found line in M-state event=0x34,umask=0x81 01 unc_cbo_cache_lookup.any_mesi uncore cache L3 Lookup any request that access cache and found line in MESI-state event=0x34,umask=0x8f 01 unc_cbo_cache_lookup.extsnp_es uncore cache L3 Lookup external snoop request that access cache and found line in E or S-state event=0x34,umask=0x46 01 unc_cbo_cache_lookup.extsnp_i uncore cache L3 Lookup external snoop request that access cache and found line in I-state event=0x34,umask=0x48 01 unc_cbo_cache_lookup.extsnp_m uncore cache L3 Lookup external snoop request that access cache and found line in M-state event=0x34,umask=0x41 01 unc_cbo_cache_lookup.extsnp_mesi uncore cache L3 Lookup external snoop request that access cache and found line in MESI-state event=0x34,umask=0x4f 01 unc_cbo_cache_lookup.read_es uncore cache L3 Lookup read request that access cache and found line in E or S-state event=0x34,umask=0x16 01 unc_cbo_cache_lookup.read_i uncore cache L3 Lookup read request that access cache and found line in I-state event=0x34,umask=0x18 01 unc_cbo_cache_lookup.read_m uncore cache L3 Lookup read request that access cache and found line in M-state event=0x34,umask=0x11 01 unc_cbo_cache_lookup.read_mesi uncore cache L3 Lookup read request that access cache and found line in any MESI-state event=0x34,umask=0x1f 01 unc_cbo_cache_lookup.write_es uncore cache L3 Lookup write request that access cache and found line in E or S-state event=0x34,umask=0x26 01 unc_cbo_cache_lookup.write_i uncore cache L3 Lookup write request that access cache and found line in I-state event=0x34,umask=0x28 01 unc_cbo_cache_lookup.write_m uncore cache L3 Lookup write request that access cache and found line in M-state event=0x34,umask=0x21 01 unc_cbo_cache_lookup.write_mesi uncore cache L3 Lookup write request that access cache and found line in MESI-state event=0x34,umask=0x2f 01 unc_cbo_xsnp_response.hitm_eviction uncore cache A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core event=0x22,umask=0x88 01 unc_cbo_xsnp_response.hitm_external uncore cache An external snoop hits a modified line in some processor core event=0x22,umask=0x28 01 unc_cbo_xsnp_response.hit_eviction uncore cache A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core event=0x22,umask=0x84 01 unc_cbo_xsnp_response.hit_external uncore cache An external snoop hits a non-modified line in some processor core event=0x22,umask=0x24 01 unc_cbo_xsnp_response.miss_external uncore cache An external snoop misses in some processor core event=0x22,umask=0x21 01 unc_clock.socket uncore cache This 48-bit fixed counter counts the UCLK cycles event=0xff 01 unc_arb_coh_trk_occupancy.all uncore interconnect Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory) event=0x83,umask=1 01 Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory) unc_arb_trk_occupancy.cycles_with_any_request uncore interconnect Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC event=0x80,cmask=1,umask=1 01 dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks event=8,period=100003,umask=1 00 Misses in all TLB levels that cause a page walk of any page size dtlb_load_misses.pde_cache_miss virtual memory DTLB demand load misses with low part of linear-to-physical address translation missed event=8,period=100003,umask=0x80 00 DTLB demand load misses with low part of linear-to-physical address translation missed dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=8,period=2000003,umask=0x60 00 Number of cache load STLB hits. No page walk dtlb_load_misses.stlb_hit_2m virtual memory Load misses that miss the DTLB and hit the STLB (2M) event=8,period=2000003,umask=0x40 00 This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks dtlb_load_misses.stlb_hit_4k virtual memory Load misses that miss the DTLB and hit the STLB (4K) event=8,period=2000003,umask=0x20 00 This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks dtlb_load_misses.walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size event=8,period=100003,umask=0xe 00 Completed page walks in any TLB of any page size due to demand load misses dtlb_load_misses.walk_completed_1g virtual memory Load miss in all TLB levels causes a page walk that completes. (1G) event=8,period=2000003,umask=8 00 dtlb_load_misses.walk_completed_2m_4m virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) event=8,period=2000003,umask=4 00 Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels dtlb_load_misses.walk_completed_4k virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) event=8,period=2000003,umask=2 00 Completed page walks due to demand load misses that caused 4K page walks in any TLB levels dtlb_load_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=8,period=2000003,umask=0x10 00 This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks event=0x49,period=100003,umask=1 00 Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G) dtlb_store_misses.pde_cache_miss virtual memory DTLB store misses with low part of linear-to-physical address translation missed event=0x49,period=100003,umask=0x80 00 DTLB store misses with low part of linear-to-physical address translation missed dtlb_store_misses.stlb_hit virtual memory Store operations that miss the first TLB level but hit the second and do not cause page walks event=0x49,period=100003,umask=0x60 00 Store operations that miss the first TLB level but hit the second and do not cause page walks dtlb_store_misses.stlb_hit_2m virtual memory Store misses that miss the DTLB and hit the STLB (2M) event=0x49,period=100003,umask=0x40 00 This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks dtlb_store_misses.stlb_hit_4k virtual memory Store misses that miss the DTLB and hit the STLB (4K) event=0x49,period=100003,umask=0x20 00 This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks event=0x49,period=100003,umask=0xe 00 Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G) dtlb_store_misses.walk_completed_1g virtual memory Store misses in all DTLB levels that cause completed page walks. (1G) event=0x49,period=100003,umask=8 00 dtlb_store_misses.walk_completed_2m_4m virtual memory Store misses in all DTLB levels that cause completed page walks (2M/4M) event=0x49,period=100003,umask=4 00 Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure dtlb_store_misses.walk_completed_4k virtual memory Store miss in all TLB levels causes a page walk that completes. (4K) event=0x49,period=100003,umask=2 00 Completed page walks due to store misses in one or more TLB levels of 4K page structure dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x49,period=100003,umask=0x10 00 This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses ept.walk_cycles virtual memory Cycle count for an Extended Page table walk event=0x4f,period=2000003,umask=0x10 00 itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100003,umask=1 00 Counts the number of ITLB flushes, includes 4k/2M/4M pages itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=1 00 Misses in ITLB that causes a page walk of any page size itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x60 00 ITLB misses that hit STLB. No page walk itlb_misses.stlb_hit_2m virtual memory Code misses that miss the DTLB and hit the STLB (2M) event=0x85,period=100003,umask=0x40 00 ITLB misses that hit STLB (2M) itlb_misses.stlb_hit_4k virtual memory Core misses that miss the DTLB and hit the STLB (4K) event=0x85,period=100003,umask=0x20 00 ITLB misses that hit STLB (4K) itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks event=0x85,period=100003,umask=0xe 00 Completed page walks in ITLB of any page size itlb_misses.walk_completed_1g virtual memory Store miss in all TLB levels causes a page walk that completes. (1G) event=0x85,period=100003,umask=8 00 itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) event=0x85,period=100003,umask=4 00 Completed page walks due to misses in ITLB 2M/4M page entries itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) event=0x85,period=100003,umask=2 00 Completed page walks due to misses in ITLB 4K page entries itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x85,period=100003,umask=0x10 00 This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses page_walker_loads.dtlb_l1 virtual memory Number of DTLB page walker hits in the L1+FB event=0xbc,period=2000003,umask=0x11 00 Number of DTLB page walker loads that hit in the L1+FB page_walker_loads.dtlb_l2 virtual memory Number of DTLB page walker hits in the L2 event=0xbc,period=2000003,umask=0x12 00 Number of DTLB page walker loads that hit in the L2 page_walker_loads.dtlb_l3 virtual memory Number of DTLB page walker hits in the L3 + XSNP Spec update: HSD25 event=0xbc,period=2000003,umask=0x14 00 Number of DTLB page walker loads that hit in the L3 Spec update: HSD25 page_walker_loads.dtlb_memory virtual memory Number of DTLB page walker hits in Memory Spec update: HSD25 event=0xbc,period=2000003,umask=0x18 00 Number of DTLB page walker loads from memory Spec update: HSD25 page_walker_loads.ept_dtlb_l1 virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB event=0xbc,period=2000003,umask=0x41 00 page_walker_loads.ept_dtlb_l2 virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in the L2 event=0xbc,period=2000003,umask=0x42 00 page_walker_loads.ept_dtlb_l3 virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in the L3 event=0xbc,period=2000003,umask=0x44 00 page_walker_loads.ept_dtlb_memory virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in memory event=0xbc,period=2000003,umask=0x48 00 page_walker_loads.ept_itlb_l1 virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB event=0xbc,period=2000003,umask=0x81 00 page_walker_loads.ept_itlb_l2 virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in the L2 event=0xbc,period=2000003,umask=0x82 00 page_walker_loads.ept_itlb_l3 virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in the L2 event=0xbc,period=2000003,umask=0x84 00 page_walker_loads.ept_itlb_memory virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in memory event=0xbc,period=2000003,umask=0x88 00 page_walker_loads.itlb_l1 virtual memory Number of ITLB page walker hits in the L1+FB event=0xbc,period=2000003,umask=0x21 00 Number of ITLB page walker loads that hit in the L1+FB page_walker_loads.itlb_l2 virtual memory Number of ITLB page walker hits in the L2 event=0xbc,period=2000003,umask=0x22 00 Number of ITLB page walker loads that hit in the L2 page_walker_loads.itlb_l3 virtual memory Number of ITLB page walker hits in the L3 + XSNP Spec update: HSD25 event=0xbc,period=2000003,umask=0x24 00 Number of ITLB page walker loads that hit in the L3 Spec update: HSD25 page_walker_loads.itlb_memory virtual memory Number of ITLB page walker hits in Memory Spec update: HSD25 event=0xbc,period=2000003,umask=0x28 00 Number of ITLB page walker loads from memory Spec update: HSD25 tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100003,umask=1 00 DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100003,umask=0x20 00 Count number of STLB flush attempts mem_load_uops_l3_miss_retired.remote_dram cache Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd3,period=100003,umask=4 00 mem_load_uops_l3_miss_retired.remote_fwd cache Retired load uop whose Data Source was: forwarded from remote cache Supports address when precise. Spec update: HSM30 (Precise event) event=0xd3,period=100003,umask=0x20 00 mem_load_uops_l3_miss_retired.remote_hitm cache Retired load uop whose Data Source was: Remote cache HITM Supports address when precise. Spec update: HSM30 (Precise event) event=0xd3,period=100003,umask=0x10 00 offcore_response.demand_code_rd.llc_hit.hitm_other_core cache Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004 00 offcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwd cache Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004 00 offcore_response.demand_data_rd.llc_hit.hitm_other_core cache Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 00 offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwd cache Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 00 offcore_response.demand_rfo.llc_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002 00 offcore_response.pf_l2_code_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0040 00 offcore_response.pf_l2_data_rd.llc_hit.any_response cache Counts prefetch (that bring data to L2) data reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010 00 offcore_response.pf_l2_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to L2) RFOs hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020 00 offcore_response.pf_llc_data_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) data reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080 00 offcore_response.all_code_rd.llc_miss.local_dram memory Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400244 00 offcore_response.all_data_rd.llc_miss.local_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400091 00 offcore_response.all_data_rd.llc_miss.remote_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63F800091 00 offcore_response.all_data_rd.llc_miss.remote_hit_forward memory Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00091 00 offcore_response.all_reads.llc_miss.local_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x6004007F7 00 offcore_response.all_reads.llc_miss.remote_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63F8007F7 00 offcore_response.all_reads.llc_miss.remote_hit_forward memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC007F7 00 offcore_response.all_rfo.llc_miss.local_dram memory Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400122 00 offcore_response.demand_code_rd.llc_miss.any_response memory Counts all demand code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00004 00 offcore_response.demand_code_rd.llc_miss.local_dram memory Counts all demand code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400004 00 offcore_response.demand_data_rd.llc_miss.any_response memory Counts demand data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00001 00 offcore_response.demand_data_rd.llc_miss.local_dram memory Counts demand data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400001 00 offcore_response.demand_rfo.llc_miss.local_dram memory Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400002 00 offcore_response.pf_l2_code_rd.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00040 00 offcore_response.pf_l2_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to L2) data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00010 00 offcore_response.pf_l2_rfo.llc_miss.any_response memory Counts all prefetch (that bring data to L2) RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00020 00 offcore_response.pf_llc_data_rd.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00080 00 rtm_retired.aborted memory Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise event) event=0xc9,period=2000003,umask=4 00 unc_c_llc_victims.s_state uncore cache Lines in S State event=0x37,umask=4 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_ring_ad_used.all uncore cache AD Ring In Use; All event=0x1b,umask=0xf 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down uncore cache AD Ring In Use; Down event=0x1b,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_even uncore cache AD Ring In Use; Down and Even event=0x1b,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ad_used.down_odd uncore cache AD Ring In Use; Down and Odd event=0x1b,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ad_used.up uncore cache AD Ring In Use; Up event=0x1b,umask=3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_even uncore cache AD Ring In Use; Up and Even event=0x1b,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ad_used.up_odd uncore cache AD Ring In Use; Up and Odd event=0x1b,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_ak_used.all uncore cache AK Ring In Use; All event=0x1c,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_even uncore cache AK Ring In Use; Down and Even event=0x1c,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ak_used.down_odd uncore cache AK Ring In Use; Down and Odd event=0x1c,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ak_used.up_even uncore cache AK Ring In Use; Up and Even event=0x1c,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ak_used.up_odd uncore cache AK Ring In Use; Up and Odd event=0x1c,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_bl_used.all uncore cache BL Ring in Use; Down event=0x1d,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_even uncore cache BL Ring in Use; Down and Even event=0x1d,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_bl_used.down_odd uncore cache BL Ring in Use; Down and Odd event=0x1d,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_bl_used.up_even uncore cache BL Ring in Use; Up and Even event=0x1d,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_bl_used.up_odd uncore cache BL Ring in Use; Up and Odd event=0x1d,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_iv_used.any uncore cache BL Ring in Use; Any event=0x1e,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.dn uncore cache BL Ring in Use; Any event=0x1e,umask=0xc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.down uncore cache BL Ring in Use; Down event=0x1e,umask=0xcc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity unc_c_ring_iv_used.up uncore cache BL Ring in Use; Any event=0x1e,umask=3 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_sink_starved.ad uncore cache UNC_C_RING_SINK_STARVED.AD event=6,umask=1 01 unc_c_ring_sink_starved.ak uncore cache UNC_C_RING_SINK_STARVED.AK event=6,umask=2 01 unc_c_ring_sink_starved.bl uncore cache UNC_C_RING_SINK_STARVED.BL event=6,umask=4 01 unc_c_ring_sink_starved.iv uncore cache UNC_C_RING_SINK_STARVED.IV event=6,umask=8 01 unc_c_tor_inserts.local_opcode uncore cache TOR Inserts; Local Memory - Opcode Matched event=0x35,umask=0x21 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory unc_h_snoop_resp.rspsfwd uncore cache Shared line forwarded from remote cache event=0x21,umask=8 0164Bytes Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state unc_h_snp_resp_recv_local.rspsfwd uncore cache Snoop Responses Received Local; RspSFwd event=0x60,umask=8 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x16,umask=2 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry unc_q_clockticks uncore interconnect Number of qfclks event=0x14 01 Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. HSX does not support dynamic link speeds, so this frequency is fixed unc_q_rxl_crc_errors.normal_op uncore interconnect CRC Errors Detected; Normal Operations event=3,umask=2 01 Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation unc_s_ring_ad_used.down_even uncore interconnect AD Ring In Use; Down and Event event=0x1b,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ad_used.down_odd uncore interconnect AD Ring In Use; Down and Odd event=0x1b,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ad_used.up_even uncore interconnect AD Ring In Use; Up and Even event=0x1b,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ad_used.up_odd uncore interconnect AD Ring In Use; Up and Odd event=0x1b,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_ak_used.down_even uncore interconnect AK Ring In Use; Down and Event event=0x1c,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ak_used.down_odd uncore interconnect AK Ring In Use; Down and Odd event=0x1c,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ak_used.up_even uncore interconnect AK Ring In Use; Up and Even event=0x1c,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ak_used.up_odd uncore interconnect AK Ring In Use; Up and Odd event=0x1c,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_bl_used.down_even uncore interconnect BL Ring in Use; Down and Event event=0x1d,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_bl_used.down_odd uncore interconnect BL Ring in Use; Down and Odd event=0x1d,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_bl_used.up_even uncore interconnect BL Ring in Use; Up and Even event=0x1d,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_bl_used.up_odd uncore interconnect BL Ring in Use; Up and Odd event=0x1d,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_u_clockticks uncore interconnect UNC_U_CLOCKTICKS event=0 01 unc_m_clockticks uncore memory DRAM Clockticks event=0 01 unc_p_clockticks uncore power pclk Cycles event=0 01 The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time unc_p_freq_band0_cycles uncore power Frequency Residency event=0xb 01 Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_freq_band1_cycles uncore power Frequency Residency event=0xc 01 Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_freq_band2_cycles uncore power Frequency Residency event=0xd 01 Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_freq_band3_cycles uncore power Frequency Residency event=0xe 01 Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_ufs_transitions_no_change uncore power UNC_P_UFS_TRANSITIONS_NO_CHANGE event=0x79 01 Ring GV with same final and initial frequency l1d_pend_miss.l2_stall cache Number of cycles a demand request has waited due to L1D due to lack of L2 resources event=0x48,period=1000003,umask=4 00 Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l2_lines_out.non_silent cache Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill event=0xf2,period=200003,umask=2 00 Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 l2_lines_out.silent cache Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill event=0xf2,period=200003,umask=1 00 Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event l2_lines_out.useless_hwpf cache Cache lines that have been L2 hardware prefetched but not used by demand accesses event=0xf2,period=200003,umask=4 00 Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache l2_rqsts.miss cache This event is deprecated event=0x24,period=200003,umask=0x3f 10 l2_rqsts.references cache This event is deprecated event=0x24,period=200003,umask=0xff 10 mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or Bus Lock Supports address when precise (Precise event) event=0xd4,period=100007,umask=4 00 Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock) Supports address when precise (Precise event) ocr.demand_code_rd.l3_hit.any cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0004 00 ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004 00 ocr.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004 00 ocr.demand_code_rd.l3_hit.snoop_miss cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0004 00 ocr.demand_code_rd.l3_hit.snoop_not_needed cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004 00 ocr.demand_code_rd.l3_hit.snoop_sent cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C0004 00 ocr.demand_data_rd.l3_hit.any cache Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0001 00 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 00 ocr.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001 00 ocr.demand_data_rd.l3_hit.snoop_not_needed cache Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001 00 ocr.demand_data_rd.l3_hit.snoop_sent cache Counts demand data reads that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C0001 00 ocr.demand_rfo.l3_hit.any cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0002 00 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002 00 ocr.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002 00 ocr.demand_rfo.l3_hit.snoop_miss cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0002 00 ocr.demand_rfo.l3_hit.snoop_not_needed cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002 00 ocr.demand_rfo.l3_hit.snoop_sent cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C0002 00 ocr.hwpf_l1d_and_swpf.l3_hit.any cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0400 00 ocr.hwpf_l1d_and_swpf.l3_hit.snoop_miss cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0400 00 ocr.hwpf_l1d_and_swpf.l3_hit.snoop_not_needed cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0400 00 ocr.hwpf_l2_data_rd.l3_hit.any cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_hitm cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_no_fwd cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_miss cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_not_needed cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_sent cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C0010 00 ocr.hwpf_l2_rfo.l3_hit.any cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_hitm cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_hit_no_fwd cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_miss cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_not_needed cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_sent cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C0020 00 ocr.hwpf_l3.l3_hit.any cache Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C2380 00 ocr.other.l3_hit.snoop_hit_no_fwd cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C8000 00 ocr.other.l3_hit.snoop_miss cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C8000 00 ocr.other.l3_hit.snoop_not_needed cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C8000 00 ocr.other.l3_hit.snoop_sent cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C8000 00 ocr.streaming_wr.l3_hit.any cache Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0800 00 offcore_requests.all_requests cache Counts memory transactions sent to the uncore event=0xb0,period=100003,umask=0x80 00 Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses offcore_requests_outstanding.all_data_rd cache For every cycle, increments by the number of outstanding data read requests pending event=0x60,period=1000003,umask=8 00 For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.cycles_with_data_rd cache Cycles where at least 1 outstanding data read request is pending event=0x60,cmask=1,period=1000003,umask=8 00 Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles where at least 1 outstanding Demand RFO request is pending event=0x60,cmask=1,period=1000003,umask=4 00 Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.demand_data_rd cache For every cycle, increments by the number of outstanding demand data read requests pending event=0x60,period=1000003,umask=1 00 For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.demand_rfo cache Store Read transactions pending for off-core. Highly correlated event=0x60,period=1000003,umask=4 00 Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion sq_misc.bus_lock cache Counts bus locks, accounts for cache line split locks and UC locks event=0xf4,period=100003,umask=0x10 00 Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory sq_misc.sq_full cache Cycles the queue waiting for offcore responses is full event=0xf4,period=100003,umask=4 00 Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries sw_prefetch_access.any cache Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed event=0x32,period=100003,umask=0xf 00 sw_prefetch_access.nta cache Number of PREFETCHNTA instructions executed event=0x32,period=100003,umask=1 00 Counts the number of PREFETCHNTA instructions executed sw_prefetch_access.prefetchw cache Number of PREFETCHW instructions executed event=0x32,period=100003,umask=8 00 Counts the number of PREFETCHW instructions executed sw_prefetch_access.t0 cache Number of PREFETCHT0 instructions executed event=0x32,period=100003,umask=2 00 Counts the number of PREFETCHT0 instructions executed sw_prefetch_access.t1_t2 cache Number of PREFETCHT1 or PREFETCHT2 instructions executed event=0x32,period=100003,umask=4 00 Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed fp_arith_inst_retired.scalar floating point Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=1000003,umask=3 00 Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.vector floating point Number of any Vector retired FP arithmetic instructions event=0xc7,period=1000003,umask=0xfc 00 decode.lcp frontend Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP] event=0x87,period=500009,umask=1 00 Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP] dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE transitions count event=0xab,cmask=1,edge=1,period=100003,umask=2 00 Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions dsb2mite_switches.penalty_cycles frontend DSB-to-MITE switch true penalty cycles event=0xab,period=100003,umask=2 00 Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle (Precise event) event=0xc6,period=100007,umask=1,frontend=0x500106 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x508006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x501006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_2 frontend Retired instructions after front-end starvation of at least 2 cycles (Precise event) event=0xc6,period=100007,umask=1,frontend=0x500206 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x510006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x502006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x500406 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x520006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x504006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x500806 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) icache_16b.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS] event=0x80,period=500009,umask=4 00 Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS] icache_64b.iftag_hit frontend Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=1 00 Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses icache_64b.iftag_miss frontend Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=2 00 Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses icache_64b.iftag_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS] event=0x83,period=200003,umask=4 00 Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS] icache_data.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL] event=0x80,period=500009,umask=4 00 Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL] icache_tag.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL] event=0x83,period=200003,umask=4 00 Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL] idq.dsb_cycles_ok frontend Cycles DSB is delivering optimal number of Uops event=0x79,cmask=5,period=2000003,umask=8 00 Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ idq.mite_cycles_ok frontend Cycles MITE is delivering optimal number of Uops event=0x79,cmask=5,period=2000003,umask=4 00 Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles_any frontend Cycles when uops are being delivered to IDQ while MS is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_switches frontend Number of switches from DSB or MITE to the MS event=0x79,cmask=1,edge=1,period=100003,umask=0x30 00 Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer idq.ms_uops frontend Uops delivered to IDQ while MS is busy event=0x79,period=100003,umask=0x30 00 Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled event=0x9c,cmask=5,period=1000003,umask=1 00 Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle idq_uops_not_delivered.cycles_fe_was_ok frontend Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled event=0x9c,cmask=1,inv=1,period=1000003,umask=1 00 Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle hle_retired.aborted memory Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) event=0xc8,period=100003,umask=4 00 Counts the number of times HLE abort was triggered hle_retired.aborted_events memory Number of times an HLE execution aborted due to unfriendly events (such as interrupts) event=0xc8,period=100003,umask=0x80 00 Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts) hle_retired.aborted_mem memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=100003,umask=8 00 Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) hle_retired.aborted_unfriendly memory Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) event=0xc8,period=100003,umask=0x20 00 Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) hle_retired.commit memory Number of times an HLE execution successfully committed event=0xc8,period=100003,umask=2 00 Counts the number of times HLE commit succeeded hle_retired.start memory Number of times an HLE execution started event=0xc8,period=100003,umask=1 00 Counts the number of times we entered an HLE region. Does not count nested transactions ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00004 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00002 00 ocr.hwpf_l1d_and_swpf.l3_miss memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00400 00 ocr.hwpf_l2_data_rd.l3_miss memory Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00010 00 ocr.hwpf_l2_rfo.l3_miss memory Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00020 00 ocr.other.l3_miss memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC08000 00 ocr.streaming_wr.l3_miss memory Counts streaming stores that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00800 00 offcore_requests.l3_miss_demand_data_rd memory Counts demand data read requests that miss the L3 cache event=0xb0,period=100003,umask=0x10 00 offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd memory Cycles where at least one demand data read request known to have missed the L3 cache is pending event=0x60,cmask=1,period=1000003,umask=0x10 00 Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache tx_exec.misc2 memory Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region event=0x5d,period=100003,umask=2 00 Counts Unfriendly TSX abort triggered by a vzeroupper instruction tx_exec.misc3 memory Number of times an instruction execution caused the transactional nest count supported to be exceeded event=0x5d,period=100003,umask=4 00 Counts Unfriendly TSX abort triggered by a nest count that is too deep tx_mem.abort_hle_elision_buffer_mismatch memory Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer event=0x54,period=100003,umask=0x10 00 Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch tx_mem.abort_hle_elision_buffer_not_empty memory Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero event=0x54,period=100003,umask=8 00 Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer event=0x54,period=100003,umask=0x20 00 Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer tx_mem.abort_hle_store_to_elided_lock memory Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer event=0x54,period=100003,umask=4 00 Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock tx_mem.hle_elision_buffer_full memory Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero event=0x54,period=100003,umask=0x40 00 Counts the number of times we could not allocate Lock Buffer core_power.lvl0_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule event=0x28,period=200003,umask=7 00 Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes core_power.lvl1_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule event=0x28,period=200003,umask=0x18 00 Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions ocr.demand_code_rd.dram other Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000004 00 ocr.demand_code_rd.local_dram other Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000004 00 ocr.demand_data_rd.dram other Counts demand data reads that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001 00 ocr.demand_data_rd.local_dram other Counts demand data reads that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001 00 ocr.demand_rfo.any_response other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10002 00 ocr.demand_rfo.dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000002 00 ocr.demand_rfo.local_dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000002 00 ocr.hwpf_l1d_and_swpf.any_response other Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10400 00 ocr.hwpf_l1d_and_swpf.dram other Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000400 00 ocr.hwpf_l1d_and_swpf.local_dram other Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000400 00 ocr.hwpf_l2_data_rd.any_response other Counts hardware prefetch data reads (which bring data to L2) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10010 00 ocr.hwpf_l2_data_rd.dram other Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000010 00 ocr.hwpf_l2_data_rd.local_dram other Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000010 00 ocr.hwpf_l2_rfo.any_response other Counts hardware prefetch RFOs (which bring data to L2) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10020 00 ocr.hwpf_l2_rfo.dram other Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000020 00 ocr.hwpf_l2_rfo.local_dram other Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000020 00 ocr.other.any_response other Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x18000 00 ocr.other.dram other Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184008000 00 ocr.other.local_dram other Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184008000 00 ocr.streaming_wr.dram other Counts streaming stores that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000800 00 ocr.streaming_wr.local_dram other Counts streaming stores that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000800 00 arith.divider_active pipeline Cycles when divide unit is busy executing divide or square root operations event=0x14,cmask=1,period=1000003,umask=9 00 Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations assists.any pipeline Number of occurrences where a microcode assist is invoked by hardware event=0xc1,period=100003,umask=7 00 Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists br_misp_retired.all_branches pipeline All mispredicted branch instructions retired (Precise event) event=0xc5,period=50021 00 Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.cond pipeline Mispredicted conditional branch instructions retired (Precise event) event=0xc5,period=50021,umask=0x11 00 Counts mispredicted conditional branch instructions retired (Precise event) br_misp_retired.cond_ntaken pipeline Mispredicted non-taken conditional branch instructions retired (Precise event) event=0xc5,period=50021,umask=0x10 00 Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken (Precise event) br_misp_retired.cond_taken pipeline number of branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=50021,umask=1 00 Counts taken conditional mispredicted branch instructions retired (Precise event) br_misp_retired.indirect pipeline All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event) event=0xc5,period=50021,umask=0x80 00 Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event) br_misp_retired.indirect_call pipeline Mispredicted indirect CALL instructions retired (Precise event) event=0xc5,period=50021,umask=2 00 Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect (Precise event) br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=50021,umask=0x20 00 Counts number of near branch instructions retired that were mispredicted and taken (Precise event) br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) event=0xc5,period=50021,umask=8 00 This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired (Precise event) cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_xclk pipeline Core crystal clock cycles when the thread is unhalted event=0x3c,period=25003,umask=1 00 Counts core crystal clock cycles when the thread is unhalted cycle_activity.stalls_mem_any pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=20,period=1000003,umask=0x14 00 ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP] event=0x87,period=500009,umask=1 00 Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP] inst_retired.any pipeline Number of instructions retired. Fixed Counter - architectural event (Precise event) event=0xc0,period=2000003 00 Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event) inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event (Precise event) event=0xc0,period=2000003 00 Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event) inst_retired.nop pipeline Number of all retired NOP instructions (Precise event) event=0xc0,period=2000003,umask=2 00 inst_retired.prec_dist pipeline Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution (Precise event) event=0,period=2000003,umask=1 00 A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0 (Precise event) inst_retired.stall_cycles pipeline Cycles without actually retired instructions event=0xc0,cmask=1,inv=1,period=1000003,umask=1 00 This event counts cycles without actually retired instructions int_misc.all_recovery_cycles pipeline Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall event=0xd,cmask=1,period=2000003,umask=3 00 Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall int_misc.clears_count pipeline Clears speculative count event=0xd,cmask=1,edge=1,period=500009,umask=1 00 Counts the number of speculative clears due to any type of branch misprediction or machine clears int_misc.clear_resteer_cycles pipeline Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path event=0xd,period=500009,umask=0x80 00 Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread event=0xd,period=500009,umask=1 00 Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event int_misc.uop_dropping pipeline TMA slots where uops got dropped event=0xd,period=1000003,umask=0x10 00 Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons ld_blocks.no_sr pipeline The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=3,period=100003,umask=8 00 Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks_partial.address_alias pipeline False dependencies due to partial compare on address event=7,period=100003,umask=1 00 Counts the number of times a load got blocked due to false dependencies due to partial compare on address lsd.cycles_ok pipeline Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder event=0xa8,cmask=5,period=2000003,umask=1 00 Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector) misc_retired.lbr_inserts pipeline Increments whenever there is an update to the LBR array event=0xcc,period=100003,umask=0x20 00 Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly misc_retired.pause_inst pipeline Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products event=0xcc,period=100003,umask=0x40 00 Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=1000003,umask=1 00 Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses) rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty event=0x5e,cmask=1,edge=1,inv=1,period=100003,umask=1 00 Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) topdown.backend_bound_slots pipeline TMA slots where no uops were being issued due to lack of back-end resources event=0xa4,period=10000003,umask=2 00 Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources uops_decoded.dec0 pipeline Number of uops decoded out of instructions exclusively fetched by decoder 0 event=0x56,period=1000003,umask=1 00 Uops exclusively fetched by decoder 0 uops_dispatched.port_0 pipeline Number of uops executed on port 0 event=0xa1,period=2000003,umask=1 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0 uops_dispatched.port_1 pipeline Number of uops executed on port 1 event=0xa1,period=2000003,umask=2 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1 uops_dispatched.port_2_3 pipeline Number of uops executed on port 2 and 3 event=0xa1,period=2000003,umask=4 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3 uops_dispatched.port_4_9 pipeline Number of uops executed on port 4 and 9 event=0xa1,period=2000003,umask=0x10 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9 uops_dispatched.port_5 pipeline Number of uops executed on port 5 event=0xa1,period=2000003,umask=0x20 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5 uops_dispatched.port_6 pipeline Number of uops executed on port 6 event=0xa1,period=2000003,umask=0x40 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6 uops_dispatched.port_7_8 pipeline Number of uops executed on port 7 and 8 event=0xa1,period=2000003,umask=0x80 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8 uops_issued.any pipeline Uops that RAT issues to RS event=0xe,period=2000003,umask=1 00 Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) uops_issued.stall_cycles pipeline Cycles when RAT does not issue Uops to RS for the thread event=0xe,cmask=1,inv=1,period=1000003,umask=1 00 Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_issued.vector_width_mismatch pipeline Uops inserted at issue-stage in order to preserve upper bits of vector registers event=0xe,period=100003,umask=2 00 Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=1000003,umask=2 00 This event counts cycles without actually retired uops uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=10,inv=1,period=1000003,umask=2 00 Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event unc_arb_coh_trk_requests.all uncore interconnect Number of entries allocated. Account for Any type: e.g. Snoop, etc event=0x84,umask=1 01 unc_arb_dat_occupancy.all uncore interconnect This event is deprecated. Refer to new event UNC_ARB_IFA_OCCUPANCY.ALL event=0x85,umask=1 11 unc_arb_dat_occupancy.rd uncore interconnect This event is deprecated event=0x85,umask=2 11 unc_arb_req_trk_occupancy.drd uncore interconnect This event is deprecated. Refer to new event UNC_ARB_TRK_OCCUPANCY.RD event=0x80,umask=2 11 unc_arb_req_trk_request.drd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches event=0x81,umask=2 01 unc_arb_trk_occupancy.all uncore interconnect This event is deprecated event=0x80,umask=1 11 unc_arb_trk_occupancy.rd uncore interconnect This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_OCCUPANCY.DRD event=0x80,umask=2 11 unc_arb_trk_requests.all uncore interconnect Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic event=0x81,umask=1 01 unc_arb_trk_requests.rd uncore interconnect This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD event=0x81,umask=2 11 unc_clock.socket uncore other UNC_CLOCK.SOCKET event=0xff 01 dtlb_load_misses.stlb_hit virtual memory Loads that miss the DTLB and hit the STLB event=8,period=100003,umask=0x20 00 Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) dtlb_load_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a demand load event=8,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load dtlb_load_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data load to a 2M/4M page event=8,period=100003,umask=4 00 Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_4k virtual memory Page walks completed due to a demand data load to a 4K page event=8,period=100003,umask=2 00 Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_pending virtual memory Number of page walks outstanding for a demand load in the PMH each cycle event=8,period=100003,umask=0x10 00 Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle dtlb_store_misses.stlb_hit virtual memory Stores that miss the DTLB and hit the STLB event=0x49,period=100003,umask=0x20 00 Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) dtlb_store_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a store event=0x49,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store dtlb_store_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data store to a 2M/4M page event=0x49,period=100003,umask=4 00 Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_4k virtual memory Page walks completed due to a demand data store to a 4K page event=0x49,period=100003,umask=2 00 Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_pending virtual memory Number of page walks outstanding for a store in the PMH each cycle event=0x49,period=100003,umask=0x10 00 Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle itlb_misses.stlb_hit virtual memory Instruction fetch requests that miss the ITLB and hit the STLB event=0x85,period=100003,umask=0x20 00 Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB) itlb_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request event=0x85,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request itlb_misses.walk_pending virtual memory Number of page walks outstanding for an outstanding code request in the PMH each cycle event=0x85,period=100003,umask=0x10 00 Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle l2_lines_out.non_silent cache Cache lines that are evicted by L2 cache when triggered by an L2 cache fill event=0xf2,period=200003,umask=2 00 Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities mem_load_l3_hit_retired.xsnp_hit cache This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD Supports address when precise (Precise event) event=0xd2,period=20011,umask=2 10 mem_load_l3_hit_retired.xsnp_hitm cache This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD Supports address when precise (Precise event) event=0xd2,period=20011,umask=4 10 ocr.demand_code_rd.l3_hit cache Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004 00 ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004 00 ocr.demand_code_rd.snc_cache.hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x1008000004 00 ocr.demand_code_rd.snc_cache.hit_with_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x808000004 00 ocr.demand_data_rd.l3_hit cache Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001 00 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001 00 ocr.demand_data_rd.remote_cache.snoop_hitm cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x1030000001 00 ocr.demand_data_rd.remote_cache.snoop_hit_with_fwd cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=1,offcore_rsp=0x830000001 00 ocr.demand_data_rd.snc_cache.hitm cache Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x1008000001 00 ocr.demand_data_rd.snc_cache.hit_with_fwd cache Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x808000001 00 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002 00 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002 00 ocr.demand_rfo.snc_cache.hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x1008000002 00 ocr.demand_rfo.snc_cache.hit_with_fwd cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x808000002 00 ocr.hwpf_l1d_and_swpf.l3_hit cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0400 00 ocr.hwpf_l3.l3_hit cache Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x80082380 00 ocr.prefetches.l3_hit cache Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C27F0 00 ocr.reads_to_core.l3_hit cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F003C0477 00 ocr.reads_to_core.l3_hit.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0477 00 ocr.reads_to_core.l3_hit.snoop_hit_no_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0477 00 ocr.reads_to_core.l3_hit.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0477 00 ocr.reads_to_core.remote_cache.snoop_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified) event=0xb7,period=100003,umask=1,offcore_rsp=0x1830000477 00 ocr.reads_to_core.remote_cache.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x1030000477 00 ocr.reads_to_core.remote_cache.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=1,offcore_rsp=0x830000477 00 ocr.reads_to_core.snc_cache.hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x1008000477 00 ocr.reads_to_core.snc_cache.hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x808000477 00 ocr.streaming_wr.l3_hit cache Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x80080800 00 offcore_requests.demand_code_rd cache Counts cacheable and non-cacheable code reads to the core event=0xb0,period=100003,umask=2 00 Counts both cacheable and non-cacheable code reads to the core offcore_requests_outstanding.cycles_with_demand_code_rd cache Cycles with outstanding code read requests pending event=0x60,cmask=1,period=1000003,umask=2 00 Cycles with outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.demand_code_rd cache For every cycle, increments by the number of outstanding code read requests pending event=0x60,period=1000003,umask=2 00 For every cycle, increments by the number of outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00004 00 ocr.demand_code_rd.l3_miss_local memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400004 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00001 00 ocr.demand_data_rd.l3_miss_local memory Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3F3FC00002 00 ocr.demand_rfo.l3_miss_local memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F04400002 00 ocr.hwpf_l1d_and_swpf.l3_miss memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00400 00 ocr.hwpf_l1d_and_swpf.l3_miss_local memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400400 00 ocr.hwpf_l3.l3_miss memory Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x94002380 00 ocr.hwpf_l3.l3_miss_local memory Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x84002380 00 ocr.itom.l3_miss_local memory Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x84000002 00 ocr.other.l3_miss memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC08000 00 ocr.other.l3_miss_local memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84408000 00 ocr.prefetches.l3_miss_local memory Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x3F844027F0 00 ocr.reads_to_core.l3_miss memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3F3FC00477 00 ocr.reads_to_core.l3_miss_local memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F04400477 00 ocr.reads_to_core.l3_miss_local_socket memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x70CC00477 00 ocr.streaming_wr.l3_miss memory Counts streaming stores that missed the local socket's L1, L2, and L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x94000800 00 ocr.streaming_wr.l3_miss_local memory Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x84000800 00 offcore_requests_outstanding.l3_miss_demand_data_rd memory This event is deprecated event=0x60,period=2000003,umask=0x10 10 offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6 memory Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache event=0x60,cmask=6,period=2000003,umask=0x10 00 Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache core_snoop_response.i_fwd_fe other Hit snoop reply with data, line invalidated event=0xef,period=1000003,umask=0x20 00 Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.i_fwd_m other HitM snoop reply with data, line invalidated event=0xef,period=1000003,umask=0x10 00 Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.i_hit_fse other Hit snoop reply without sending the data, line invalidated event=0xef,period=1000003,umask=2 00 Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.miss other Line not found snoop reply event=0xef,period=1000003,umask=1 00 Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core core_snoop_response.s_fwd_fe other Hit snoop reply with data, line kept in Shared state event=0xef,period=1000003,umask=0x40 00 Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.s_fwd_m other HitM snoop reply with data, line kept in Shared state event=0xef,period=1000003,umask=8 00 Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state. A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.s_hit_fse other Hit snoop reply without sending the data, line kept in Shared state event=0xef,period=1000003,umask=4 00 Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state. A single snoop response from the core counts on all hyperthreads of the core ocr.demand_code_rd.dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x73C000004 00 ocr.demand_code_rd.local_dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x104000004 00 ocr.demand_code_rd.snc_dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x708000004 00 ocr.demand_data_rd.dram other Counts demand data reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x73C000001 00 ocr.demand_data_rd.local_dram other Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x104000001 00 ocr.demand_data_rd.local_pmm other Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x100400001 00 ocr.demand_data_rd.pmm other Counts demand data reads that were supplied by PMM event=0xb7,period=100003,umask=1,offcore_rsp=0x703C00001 00 ocr.demand_data_rd.remote_dram other Counts demand data reads that were supplied by DRAM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x730000001 00 ocr.demand_data_rd.remote_pmm other Counts demand data reads that were supplied by PMM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x703000001 00 ocr.demand_data_rd.snc_dram other Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x708000001 00 ocr.demand_data_rd.snc_pmm other Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x700800001 00 ocr.demand_rfo.any_response other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x3F3FFC0002 00 ocr.demand_rfo.dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x73C000002 00 ocr.demand_rfo.local_dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x104000002 00 ocr.demand_rfo.local_pmm other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x100400002 00 ocr.demand_rfo.pmm other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM event=0xb7,period=100003,umask=1,offcore_rsp=0x703C00002 00 ocr.demand_rfo.remote_pmm other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x703000002 00 ocr.demand_rfo.snc_dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x708000002 00 ocr.demand_rfo.snc_pmm other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x700800002 00 ocr.hwpf_l1d_and_swpf.dram other Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x73C000400 00 ocr.hwpf_l1d_and_swpf.local_dram other Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x104000400 00 ocr.hwpf_l2.any_response other Counts hardware prefetch (which bring data to L2) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10070 00 ocr.hwpf_l3.any_response other Counts hardware prefetches to the L3 only that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x12380 00 ocr.hwpf_l3.remote other Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket event=0xb7,period=100003,umask=1,offcore_rsp=0x90002380 00 ocr.itom.remote other Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket event=0xb7,period=100003,umask=1,offcore_rsp=0x90000002 00 ocr.reads_to_core.any_response other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x3F3FFC0477 00 ocr.reads_to_core.dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x73C000477 00 ocr.reads_to_core.local_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x104000477 00 ocr.reads_to_core.local_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x100400477 00 ocr.reads_to_core.local_socket_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x70C000477 00 ocr.reads_to_core.local_socket_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x700C00477 00 ocr.reads_to_core.remote other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F33000477 00 ocr.reads_to_core.remote_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x730000477 00 ocr.reads_to_core.remote_memory other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x731800477 00 ocr.reads_to_core.remote_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x703000477 00 ocr.reads_to_core.snc_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x708000477 00 ocr.reads_to_core.snc_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x700800477 00 ocr.write_estimate.memory other Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) event=0xb7,period=100003,umask=1,offcore_rsp=0xFBFF80822 00 br_misp_retired.indirect_call pipeline Mispredicted indirect CALL instructions retired (Precise event) event=0xc5,period=50021,umask=2 00 Counts retired mispredicted indirect (near taken) calls, including both register and memory indirect (Precise event) unc_cha_2lm_nm_invitox.local uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL event=0x65,umask=1 11 unc_cha_2lm_nm_invitox.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE event=0x65,umask=2 11 unc_cha_2lm_nm_invitox.setconflict uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT event=0x65,umask=4 11 unc_cha_2lm_nm_setconflicts.llc uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC event=0x64,umask=2 11 unc_cha_2lm_nm_setconflicts.sf uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF event=0x64,umask=1 11 unc_cha_2lm_nm_setconflicts.tor uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR event=0x64,umask=4 11 unc_cha_2lm_nm_setconflicts2.memwr uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR event=0x70,umask=2 11 unc_cha_2lm_nm_setconflicts2.memwrni uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI event=0x70,umask=4 11 unc_cha_ag0_ad_crd_acquired0.tgr0 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=1 01 CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr1 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=2 01 CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr2 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=4 01 CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr3 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=8 01 CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr4 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10 01 CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr5 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20 01 CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr6 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40 01 CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr7 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80 01 CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired1.tgr10 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=4 01 CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired1.tgr8 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=1 01 CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired1.tgr9 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=2 01 CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr0 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=1 01 CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr1 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=2 01 CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr2 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=4 01 CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr3 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=8 01 CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr4 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10 01 CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr5 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20 01 CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr6 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40 01 CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr7 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80 01 CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy1.tgr10 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=4 01 CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy1.tgr8 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=1 01 CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy1.tgr9 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=2 01 CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr0 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=1 01 CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr1 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=2 01 CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr2 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=4 01 CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr3 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=8 01 CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr4 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10 01 CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr5 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20 01 CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr6 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40 01 CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr7 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80 01 CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired1.tgr10 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=4 01 CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired1.tgr8 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=1 01 CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired1.tgr9 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=2 01 CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr0 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=1 01 CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr1 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=2 01 CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr2 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=4 01 CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr3 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=8 01 CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr4 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10 01 CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr5 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20 01 CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr6 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40 01 CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr7 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80 01 CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy1.tgr10 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=4 01 CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy1.tgr8 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=1 01 CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy1.tgr9 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=2 01 CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr0 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=1 01 CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr1 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=2 01 CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr2 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=4 01 CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr3 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=8 01 CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr4 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10 01 CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr5 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20 01 CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr6 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40 01 CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr7 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80 01 CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired1.tgr10 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=4 01 CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired1.tgr8 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=1 01 CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired1.tgr9 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=2 01 CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr0 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=1 01 CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr1 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=2 01 CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr2 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=4 01 CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr3 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=8 01 CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr4 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10 01 CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr5 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20 01 CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr6 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40 01 CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr7 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80 01 CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy1.tgr10 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=4 01 CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy1.tgr8 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=1 01 CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy1.tgr9 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=2 01 CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr0 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=1 01 CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr1 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=2 01 CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr2 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=4 01 CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr3 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=8 01 CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr4 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr5 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr6 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr7 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired1.tgr10 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=4 01 CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired1.tgr8 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=1 01 CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired1.tgr9 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=2 01 CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr0 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=1 01 CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr1 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=2 01 CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr2 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=4 01 CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr3 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=8 01 CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr4 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10 01 CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr5 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20 01 CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr6 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40 01 CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr7 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80 01 CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy1.tgr10 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=4 01 CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy1.tgr8 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=1 01 CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy1.tgr9 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=2 01 CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_clockticks uncore cache Clockticks of the uncore caching and home agent (CHA) event=0 01 unc_cha_counter0_occupancy uncore cache Counter 0 Occupancy event=0x1f 01 Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry unc_cha_dir_lookup.no_snp uncore cache Multi-socket cacheline directory state lookups : Snoop Not Needed event=0x53,umask=2 01 Multi-socket cacheline directory state lookups : Snoop Not Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that did not have to send any snoops because the directory was clean unc_cha_dir_lookup.snp uncore cache Multi-socket cacheline directory state lookups : Snoop Needed event=0x53,umask=1 01 Multi-socket cacheline directory state lookups : Snoop Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that had to send one or more snoops because the directory was not clean unc_cha_dir_update.ha uncore cache Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe event=0x54,umask=1 01 Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_dir_update.tor uncore cache Multi-socket cacheline directory state updates; memory write due to directory update from (table of requests) TOR pipe event=0x54,umask=2 01 Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_distress_asserted.dpt_local uncore cache Distress signal asserted : DPT Local event=0xaf,umask=4 01 Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_cha_distress_asserted.dpt_nonlocal uncore cache Distress signal asserted : DPT Remote event=0xaf,umask=8 01 Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_cha_distress_asserted.dpt_stall_iv uncore cache Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40 01 Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_cha_distress_asserted.dpt_stall_nocrd uncore cache Distress signal asserted : DPT Stalled - No Credit event=0xaf,umask=0x80 01 Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_cha_distress_asserted.horz uncore cache Distress signal asserted : Horizontal event=0xaf,umask=2 01 Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_cha_distress_asserted.pmm_local uncore cache Distress signal asserted : PMM Local event=0xaf,umask=0x10 01 Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_cha_distress_asserted.pmm_nonlocal uncore cache Distress signal asserted : PMM Remote event=0xaf,umask=0x20 01 Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_cha_distress_asserted.vert uncore cache Distress signal asserted : Vertical event=0xaf,umask=1 01 Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_cha_hitme_hit.shared_ownreq uncore cache Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state event=0x5f,umask=4 01 Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state. : Shared hit and op is RdInvOwn, RdInv, Inv* unc_cha_hitme_hit.wbmtoe uncore cache Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests event=0x5f,umask=8 01 unc_cha_hitme_hit.wbmtoi_or_s uncore cache Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests event=0x5f,umask=0x10 01 Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS unc_cha_hitme_lookup.read uncore cache Counts Number of times HitMe Cache is accessed : Remote socket read requests event=0x5e,umask=1 01 Counts Number of times HitMe Cache is accessed : Remote socket read requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv* unc_cha_hitme_lookup.write uncore cache Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests event=0x5e,umask=2 01 Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS unc_cha_hitme_miss.notshared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line event=0x60,umask=0x40 01 Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line : No SF/LLC HitS/F and op is RdInvOwn unc_cha_hitme_miss.read_or_inv uncore cache Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests event=0x60,umask=0x80 01 Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv* unc_cha_hitme_miss.shared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line event=0x60,umask=0x20 01 Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line : SF/LLC HitS/F and op is RdInvOwn unc_cha_horz_ring_ad_in_use.left_even uncore cache Horizontal AD Ring In Use : Left and Even event=0xb6,umask=1 01 Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.left_odd uncore cache Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=2 01 Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_even uncore cache Horizontal AD Ring In Use : Right and Even event=0xb6,umask=4 01 Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_odd uncore cache Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=8 01 Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.left_even uncore cache Horizontal AK Ring In Use : Left and Even event=0xbb,umask=1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.left_odd uncore cache Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.right_even uncore cache Horizontal AK Ring In Use : Right and Even event=0xbb,umask=4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.right_odd uncore cache Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_even uncore cache Horizontal AK Ring In Use : Left and Even event=0xb7,umask=1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_odd uncore cache Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_even uncore cache Horizontal AK Ring In Use : Right and Even event=0xb7,umask=4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_odd uncore cache Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_even uncore cache Horizontal BL Ring in Use : Left and Even event=0xb8,umask=1 01 Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_odd uncore cache Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=2 01 Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_even uncore cache Horizontal BL Ring in Use : Right and Even event=0xb8,umask=4 01 Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_odd uncore cache Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=8 01 Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_iv_in_use.left uncore cache Horizontal IV Ring in Use : Left event=0xb9,umask=1 01 Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_horz_ring_iv_in_use.right uncore cache Horizontal IV Ring in Use : Right event=0xb9,umask=4 01 Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_imc_writes_count.full uncore cache CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH event=0x5b,umask=1 01 Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels unc_cha_llc_lookup.all_remote uncore cache Cache Lookups : All transactions from Remote Agents event=0x34,umask=0x1e20ff 01 Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.any_f uncore cache Cache Lookups : All Request Filter event=0x34 01 Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch unc_cha_llc_lookup.code uncore cache This event is deprecated event=0x34,umask=0x1bd0ff 11 unc_cha_llc_lookup.code_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL event=0x34,umask=0x19d0ff 11 unc_cha_llc_lookup.code_read uncore cache Cache Lookups : Code Reads event=0x34,umask=0x1bd0ff 01 Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.code_read_f uncore cache Cache Lookups : CRd Request Filter event=0x34 01 Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.code_read_local uncore cache Cache Lookups : CRd Requests that come from the local socket (usually the core) event=0x34,umask=0x19d0ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.code_read_miss uncore cache Cache Lookups : Code Read Misses event=0x34,umask=0x1bd001 01 Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.code_read_remote uncore cache Cache Lookups : CRd Requests that come from a Remote socket event=0x34,umask=0x1a10ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.code_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE event=0x34,umask=0x1a10ff 11 unc_cha_llc_lookup.corepref_or_dmnd_local_f uncore cache Cache Lookups : Local request Filter event=0x34 01 Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core unc_cha_llc_lookup.data_rd uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ event=0x34,umask=0x1bc1ff 11 unc_cha_llc_lookup.data_read uncore cache Cache and Snoop Filter Lookups; Data Read Request event=0x34,umask=0x1bc1ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_all uncore cache This event is deprecated event=0x34,umask=0x1fc1ff 11 unc_cha_llc_lookup.data_read_f uncore cache Cache Lookups : Data Read Request Filter event=0x34 01 Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Read transactions unc_cha_llc_lookup.data_read_local uncore cache Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core) event=0x34,umask=0x19c1ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_miss uncore cache Cache Lookups : Data Read Misses event=0x34,umask=0x1bc101 01 Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.data_read_remote uncore cache Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket event=0x34,umask=0x1a01ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.dmnd_read_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL event=0x34,umask=0x841ff 11 unc_cha_llc_lookup.e uncore cache Cache Lookups : E State event=0x34,umask=0x20 01 Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Exclusive State unc_cha_llc_lookup.f uncore cache Cache Lookups : F State event=0x34,umask=0x80 01 Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Forward State unc_cha_llc_lookup.flush_inv_local uncore cache Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core) event=0x34,umask=0x1844ff 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.flush_inv_remote uncore cache Cache Lookups : Flush or Invalidate requests that come from a Remote socket event=0x34,umask=0x1a04ff 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.flush_or_inv_f uncore cache Cache Lookups : Flush or Invalidate Filter event=0x34 01 Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.i uncore cache Cache Lookups : I State event=0x34,umask=1 01 Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Miss unc_cha_llc_lookup.llcpref_local uncore cache Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core) event=0x34,umask=0x189dff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.llcpref_local_f uncore cache Cache Lookups : Local LLC prefetch requests (from LLC) Filter event=0x34 01 Cache Lookups : Local LLC prefetch requests (from LLC) Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC unc_cha_llc_lookup.llc_pf_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL event=0x34,umask=0x189dff 11 unc_cha_llc_lookup.locally_homed_address uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM event=0x34,umask=0xbdfff 11 unc_cha_llc_lookup.local_f uncore cache Cache Lookups : Transactions homed locally Filter event=0x34 01 Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.loc_hom uncore cache Cache Lookups : Transactions homed locally event=0x34,umask=0xbdfff 01 Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.m uncore cache Cache Lookups : M State event=0x34,umask=0x40 01 Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Modified State unc_cha_llc_lookup.miss_all uncore cache Cache Lookups : All Misses event=0x34,umask=0x1fe001 01 Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.other_req_f uncore cache Cache Lookups : Write Request Filter event=0x34 01 Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Writeback transactions to the LLC This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.pref_or_dmnd_remote_f uncore cache Cache Lookups : Remote non-snoop request Filter event=0x34 01 Cache Lookups : Remote non-snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Non-snoop transactions to the LLC from remote agent unc_cha_llc_lookup.read uncore cache Cache Lookups : Reads event=0x34,umask=0x1bd9ff 01 Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_local_loc_hom uncore cache Cache Lookups : Locally Requested Reads that are Locally HOMed event=0x34,umask=0x9d9ff 01 Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_local_rem_hom uncore cache Cache Lookups : Locally Requested Reads that are Remotely HOMed event=0x34,umask=0x11d9ff 01 Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_miss uncore cache Cache Lookups : Read Misses event=0x34,umask=0x1bd901 01 Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_miss_loc_hom uncore cache Cache Lookups : Locally HOMed Read Misses event=0x34,umask=0xbd901 01 Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_miss_rem_hom uncore cache Cache Lookups : Remotely HOMed Read Misses event=0x34,umask=0x13d901 01 Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_or_snoop_remote_miss_rem_hom uncore cache Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed event=0x34,umask=0x161901 01 Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_remote_loc_hom uncore cache Cache Lookups : Remotely Requested Reads that are Locally HOMed event=0x34,umask=0xa19ff 01 Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_sf_hit uncore cache Cache Lookups : Reads that Hit the Snoop Filter event=0x34,umask=0x1bd90e 01 Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.remotely_homed_address uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM event=0x34,umask=0x15dfff 11 unc_cha_llc_lookup.remote_f uncore cache Cache Lookups : Transactions homed remotely Filter event=0x34 01 Cache Lookups : Transactions homed remotely Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_snoop_f uncore cache Cache Lookups : Remote snoop request Filter event=0x34 01 Cache Lookups : Remote snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Snoop transactions to the LLC from remote agent unc_cha_llc_lookup.rem_hom uncore cache Cache Lookups : Transactions homed remotely event=0x34,umask=0x15dfff 01 Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.rfo_f uncore cache Cache Lookups : RFO Request Filter event=0x34 01 Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.rfo_local uncore cache Cache Lookups : RFO Requests that come from the local socket (usually the core) event=0x34,umask=0x19c8ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.rfo_miss uncore cache Cache Lookups : RFO Misses event=0x34,umask=0x1bc801 01 Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.rfo_pref_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL event=0x34,umask=0x888ff 11 unc_cha_llc_lookup.rfo_remote uncore cache Cache Lookups : RFO Requests that come from a Remote socket event=0x34,umask=0x1a08ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.s uncore cache Cache Lookups : S State event=0x34,umask=0x10 01 Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Shared State unc_cha_llc_lookup.sf_e uncore cache Cache Lookups : SnoopFilter - E State event=0x34,umask=4 01 Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Exclusive State unc_cha_llc_lookup.sf_h uncore cache Cache Lookups : SnoopFilter - H State event=0x34,umask=8 01 Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit HitMe State unc_cha_llc_lookup.sf_s uncore cache Cache Lookups : SnoopFilter - S State event=0x34,umask=2 01 Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Shared State unc_cha_llc_lookup.writes_and_other uncore cache Cache Lookups : Filters Requests for those that write info into the cache event=0x34,umask=0x1a42ff 01 Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.write_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER event=0x34,umask=0x842ff 11 unc_cha_llc_lookup.write_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER event=0x34,umask=0x17c2ff 11 unc_cha_llc_victims.all uncore cache Lines Victimized : All Lines Victimized event=0x37,umask=0xf 01 Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_all uncore cache Lines Victimized : Local - All Lines event=0x37,umask=0x200f 01 Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_e uncore cache Lines Victimized : Local - Lines in E State event=0x37,umask=0x2002 01 Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_m uncore cache Lines Victimized : Local - Lines in M State event=0x37,umask=0x2001 01 Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_s uncore cache Lines Victimized : Local - Lines in S State event=0x37,umask=0x2004 01 Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_all uncore cache Lines Victimized : Remote - All Lines event=0x37,umask=0x800f 01 Lines Victimized : Remote - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_e uncore cache Lines Victimized : Remote - Lines in E State event=0x37,umask=0x8002 01 Lines Victimized : Remote - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_m uncore cache Lines Victimized : Remote - Lines in M State event=0x37,umask=0x8001 01 Lines Victimized : Remote - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_s uncore cache Lines Victimized : Remote - Lines in S State event=0x37,umask=0x8004 01 Lines Victimized : Remote - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_misc_external.mbe_inst0 uncore cache Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=1 01 unc_cha_misc_external.mbe_inst1 uncore cache Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=2 01 unc_cha_pipe_reject.adegrcredit uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.akegrcredit uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.allrsfways_res uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.blegrcredit uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.fsf_vicp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_allowsnp uncore cache Pipe Rejects event=0x42,umask=4 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_allwayrsv uncore cache Pipe Rejects event=0x42,umask=0x10 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_pamatch uncore cache Pipe Rejects event=0x42,umask=2 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_waymatch uncore cache Pipe Rejects event=0x42,umask=8 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.hacredit uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.idx_inpipe uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ipq_setmatch_vicp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.irq_pmm uncore cache Pipe Rejects event=0x42,umask=0x20 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.irq_setmatch_vicp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ismq_setmatch_vicp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ivegrcredit uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.llc_ways_res uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.notallowsnoop uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.one_fsf_vic uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.one_rsp_con uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.pmm_memmode_tormatch_multi uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.pmm_memmode_tor_match uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.prq_pmm uncore cache Pipe Rejects event=0x42,umask=0x40 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ptl_inpipe uncore cache Pipe Rejects event=0x42,umask=0x80 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.rmw_setmatch uncore cache Pipe Rejects event=0x42,umask=1 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.rrq_setmatch_vicp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.setmatchentrywsct uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.sf_ways_res uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.topa_match uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.torid_match_go_p uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_ad_req uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_ad_rsp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_bl_rsp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.way_match uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pmm_memmode_nm_setconflicts.llc uncore cache PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=2 01 PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the LLC unc_cha_pmm_memmode_nm_setconflicts.sf uncore cache PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=1 01 PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the SF unc_cha_pmm_memmode_nm_setconflicts.tor uncore cache PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR event=0x64,umask=4 01 PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR : No Reject in the CHA due to a pending read to the same near memory set in the TOR unc_cha_pmm_qos_occupancy.ddr_slow_fifo uncore cache UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO event=0x67,umask=1 01 : count # of SLOW TOR Request inserted to ha_pmm_tor_req_fifo unc_cha_read_no_credits.mc10 uncore cache CHA iMC CHNx READ Credits Empty : MC10 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only unc_cha_read_no_credits.mc11 uncore cache CHA iMC CHNx READ Credits Empty : MC11 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only unc_cha_read_no_credits.mc12 uncore cache CHA iMC CHNx READ Credits Empty : MC12 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only unc_cha_read_no_credits.mc13 uncore cache CHA iMC CHNx READ Credits Empty : MC13 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only unc_cha_read_no_credits.mc6 uncore cache CHA iMC CHNx READ Credits Empty : MC6 event=0x58,umask=0x40 01 CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only unc_cha_read_no_credits.mc7 uncore cache CHA iMC CHNx READ Credits Empty : MC7 event=0x58,umask=0x80 01 CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only unc_cha_read_no_credits.mc8 uncore cache CHA iMC CHNx READ Credits Empty : MC8 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only unc_cha_read_no_credits.mc9 uncore cache CHA iMC CHNx READ Credits Empty : MC9 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only unc_cha_requests.invitoe uncore cache Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent event=0x50,umask=0x30 01 Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_local uncore cache Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent event=0x50,umask=0x10 01 Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_remote uncore cache Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent event=0x50,umask=0x20 01 Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.reads uncore cache Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent event=0x50,umask=3 01 Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.reads_local uncore cache Local read requests that miss the SF/LLC and are sent to the CHA's home agent event=0x50,umask=1 01 Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.reads_remote uncore cache Remote read requests sent to the CHA's home agent event=0x50,umask=2 01 Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.writes uncore cache Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent event=0x50,umask=0xc 01 Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_local uncore cache Local write requests that miss the SF/LLC and are sent to the CHA's home agent event=0x50,umask=4 01 Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_remote uncore cache Remote write requests sent to the CHA's home agent event=0x50,umask=8 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc) unc_cha_ring_bounces_horz.ad uncore cache Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=1 01 Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.ak uncore cache Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=2 01 Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.bl uncore cache Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=4 01 Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.iv uncore cache Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=8 01 Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_vert.ad uncore cache Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=1 01 Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.ak uncore cache Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=2 01 Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.akc uncore cache Messages that bounced on the Vertical Ring event=0xaa,umask=0x10 01 Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.bl uncore cache Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=4 01 Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.iv uncore cache Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=8 01 Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_sink_starved_horz.ad uncore cache Sink Starvation on Horizontal Ring : AD event=0xad,umask=1 01 unc_cha_ring_sink_starved_horz.ak uncore cache Sink Starvation on Horizontal Ring : AK event=0xad,umask=2 01 unc_cha_ring_sink_starved_horz.ak_ag1 uncore cache Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20 01 unc_cha_ring_sink_starved_horz.bl uncore cache Sink Starvation on Horizontal Ring : BL event=0xad,umask=4 01 unc_cha_ring_sink_starved_horz.iv uncore cache Sink Starvation on Horizontal Ring : IV event=0xad,umask=8 01 unc_cha_ring_sink_starved_vert.ad uncore cache Sink Starvation on Vertical Ring : AD event=0xab,umask=1 01 unc_cha_ring_sink_starved_vert.ak uncore cache Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=2 01 unc_cha_ring_sink_starved_vert.akc uncore cache Sink Starvation on Vertical Ring event=0xab,umask=0x10 01 unc_cha_ring_sink_starved_vert.bl uncore cache Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=4 01 unc_cha_ring_sink_starved_vert.iv uncore cache Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=8 01 unc_cha_ring_src_thrtl uncore cache Source Throttle event=0xae 01 unc_cha_rxc_occupancy.irq uncore cache Ingress (from CMS) Occupancy : IRQ event=0x11,umask=1 01 Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxr_busy_starved.ad_all uncore cache Transgress Injection Starvation : AD - All event=0xe5,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_cha_rxr_busy_starved.ad_crd uncore cache Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.ad_uncrd uncore cache Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_all uncore cache Transgress Injection Starvation : BL - All event=0xe5,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_cha_rxr_busy_starved.bl_crd uncore cache Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_uncrd uncore cache Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_bypass.ad_all uncore cache Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11 01 Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_cha_rxr_bypass.ad_crd uncore cache Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10 01 Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ad_uncrd uncore cache Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=1 01 Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ak uncore cache Transgress Ingress Bypass : AK event=0xe2,umask=2 01 Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.akc_uncrd uncore cache Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80 01 Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_all uncore cache Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44 01 Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_cha_rxr_bypass.bl_crd uncore cache Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40 01 Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_uncrd uncore cache Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=4 01 Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.iv uncore cache Transgress Ingress Bypass : IV event=0xe2,umask=8 01 Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_cha_rxr_crd_starved.ad_all uncore cache Transgress Injection Starvation : AD - All event=0xe3,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_cha_rxr_crd_starved.ad_crd uncore cache Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ad_uncrd uncore cache Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ak uncore cache Transgress Injection Starvation : AK event=0xe3,umask=2 01 Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_all uncore cache Transgress Injection Starvation : BL - All event=0xe3,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_cha_rxr_crd_starved.bl_crd uncore cache Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_uncrd uncore cache Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ifv uncore cache Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80 01 Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.iv uncore cache Transgress Injection Starvation : IV event=0xe3,umask=8 01 Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved_1 uncore cache Transgress Injection Starvation event=0xe4 01 Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_inserts.ad_all uncore cache Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11 01 Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_inserts.ad_crd uncore cache Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10 01 Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ad_uncrd uncore cache Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=1 01 Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ak uncore cache Transgress Ingress Allocations : AK event=0xe1,umask=2 01 Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.akc_uncrd uncore cache Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80 01 Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_all uncore cache Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44 01 Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_inserts.bl_crd uncore cache Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40 01 Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_uncrd uncore cache Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=4 01 Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.iv uncore cache Transgress Ingress Allocations : IV event=0xe1,umask=8 01 Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_all uncore cache Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11 01 Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_occupancy.ad_crd uncore cache Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10 01 Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_uncrd uncore cache Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=1 01 Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ak uncore cache Transgress Ingress Occupancy : AK event=0xe0,umask=2 01 Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.akc_uncrd uncore cache Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80 01 Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_all uncore cache Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44 01 Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_occupancy.bl_crd uncore cache Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20 01 Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_uncrd uncore cache Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=4 01 Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.iv uncore cache Transgress Ingress Occupancy : IV event=0xe0,umask=8 01 Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_sf_eviction.e_state uncore cache Snoop filter capacity evictions for E-state entries event=0x3d,umask=2 01 Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.m_state uncore cache Snoop filter capacity evictions for M-state entries event=0x3d,umask=1 01 Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.s_state uncore cache Snoop filter capacity evictions for S-state entries event=0x3d,umask=4 01 Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline unc_cha_snoops_sent.bcst_local uncore cache Snoops Sent : Broadcast snoops for Local Requests event=0x51,umask=0x10 01 Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests unc_cha_snoops_sent.bcst_remote uncore cache Snoops Sent : Broadcast snoops for Remote Requests event=0x51,umask=0x20 01 Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to remote requests unc_cha_snoops_sent.direct_local uncore cache Snoops Sent : Directed snoops for Local Requests event=0x51,umask=0x40 01 Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests unc_cha_snoops_sent.direct_remote uncore cache Snoops Sent : Directed snoops for Remote Requests event=0x51,umask=0x80 01 Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to remote requests unc_cha_snoops_sent.local uncore cache Snoops Sent : Snoops sent for Local Requests event=0x51,umask=4 01 Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests unc_cha_snoops_sent.remote uncore cache Snoops Sent : Snoops sent for Remote Requests event=0x51,umask=8 01 Snoops Sent : Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to remote requests unc_cha_snoop_resp.rspi uncore cache Snoop Responses Received : RspI event=0x5c,umask=1 01 Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data) unc_cha_snoop_resp.rspifwd uncore cache Snoop Responses Received : RspIFwd event=0x5c,umask=4 01 Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states unc_cha_snoop_resp.rsps uncore cache Snoop Responses Received : RspS event=0x5c,umask=2 01 Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_cha_snoop_resp.rspsfwd uncore cache Snoop Responses Received : RspSFwd event=0x5c,umask=8 01 Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state unc_cha_snoop_resp_local.rspsfwd uncore cache Snoop Responses Received Local : RspSFwd event=0x5d,umask=8 01 Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=8 01 Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10 01 Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20 01 Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40 01 Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80 01 Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=8 01 Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10 01 Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20 01 Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40 01 Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80 01 Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=8 01 Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10 01 Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20 01 Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40 01 Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80 01 Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=8 01 Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10 01 Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20 01 Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40 01 Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80 01 Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_tor_inserts.all uncore cache TOR Inserts : All event=0x35,umask=0xc001ffff 01 TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ddr uncore cache TOR Inserts : DDR4 Access event=0x35 01 TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ddr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR event=0x35 11 unc_cha_tor_inserts.evict uncore cache TOR Inserts : SF/LLC Evictions event=0x35,umask=2 01 TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.hit uncore cache TOR Inserts : Just Hits event=0x35 01 TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia uncore cache TOR Inserts : All requests from iA Cores event=0x35,umask=0xc001ff01 01 TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_clflush uncore cache TOR Inserts : CLFlushes issued by iA Cores event=0x35,umask=0xc8c7ff01 01 TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_clflushopt uncore cache TOR Inserts : CLFlushOpts issued by iA Cores event=0x35,umask=0xc8d7ff01 01 TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_crd uncore cache TOR Inserts : CRDs issued by iA Cores event=0x35,umask=0xc80fff01 01 TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd uncore cache TOR Inserts : DRds issued by iA Cores event=0x35,umask=0xc817ff01 01 TOR Inserts : DRds issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_opt uncore cache TOR Inserts : DRd_Opts issued by iA Cores event=0x35,umask=0xc827ff01 01 TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_opt_pref uncore cache TOR Inserts : DRd_Opt_Prefs issued by iA Cores event=0x35,umask=0xc8a7ff01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_pref uncore cache TOR Inserts : DRd_Prefs issued by iA Cores event=0x35,umask=0xc897ff01 01 TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit uncore cache TOR Inserts : All requests from iA Cores that Hit the LLC event=0x35,umask=0xc001fd01 01 TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_crd uncore cache TOR Inserts : CRds issued by iA Cores that Hit the LLC event=0x35,umask=0xc80ffd01 01 TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_crd_pref uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC event=0x35,umask=0xc88ffd01 01 TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd uncore cache TOR Inserts : DRds issued by iA Cores that Hit the LLC event=0x35,umask=0xc817fd01 01 TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_opt uncore cache TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC event=0x35,umask=0xc827fd01 01 TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_opt_pref uncore cache TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC event=0x35,umask=0xc8a7fd01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_pref uncore cache TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC event=0x35,umask=0xc897fd01 01 TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Hit LLC event=0x35,umask=0xcc47fd01 01 TOR Inserts : ItoMs issued by iA Cores that Hit LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcode uncore cache TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC event=0x35,umask=0xcccffd01 01 TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcrd uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE event=0x35,umask=0xcccffd01 11 unc_cha_tor_inserts.ia_hit_llcprefdata uncore cache TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC event=0x35,umask=0xccd7fd01 01 TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefdrd uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA event=0x35,umask=0xccd7fd01 11 unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC event=0x35,umask=0xccc7fd01 01 TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Hit the LLC event=0x35,umask=0xc807fd01 01 TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_rfo_pref uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC event=0x35,umask=0xc887fd01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_specitom uncore cache TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC event=0x35,umask=0xcc57fd01 01 TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_itom uncore cache TOR Inserts : ItoMs issued by iA Cores event=0x35,umask=0xcc47ff01 01 TOR Inserts : ItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_itomcachenear uncore cache TOR Inserts : ItoMCacheNears issued by iA Cores event=0x35,umask=0xcd47ff01 01 TOR Inserts : ItoMCacheNears issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefcode uncore cache TOR Inserts : LLCPrefCode issued by iA Cores event=0x35,umask=0xcccfff01 01 TOR Inserts : LLCPrefCode issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefdata uncore cache TOR Inserts : LLCPrefData issued by iA Cores event=0x35,umask=0xccd7ff01 01 TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores event=0x35,umask=0xccc7ff01 01 TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss uncore cache TOR Inserts : All requests from iA Cores that Missed the LLC event=0x35,umask=0xc001fe01 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd uncore cache TOR Inserts : CRds issued by iA Cores that Missed the LLC event=0x35,umask=0xc80ffe01 01 TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_local uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc80efe01 01 TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC event=0x35,umask=0xc88ffe01 01 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref_local uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc88efe01 01 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref_remote uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc88f7e01 01 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_remote uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc80f7e01 01 TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC event=0x35,umask=0xc817fe01 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8178601 01 TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc816fe01 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168601 01 TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168a01 01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_opt uncore cache TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC event=0x35,umask=0xc827fe01 01 TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_opt_pref uncore cache TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC event=0x35,umask=0xc8a7fe01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8178a01 01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref uncore cache TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC event=0x35,umask=0xc897fe01 01 TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8978601 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local uncore cache TOR Inserts; DRd Pref misses from local IA event=0x35,umask=0xc896fe01 01 TOR Inserts; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_pref_local_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968601 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968a01 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8978a01 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote uncore cache TOR Inserts; DRd Pref misses from local IA event=0x35,umask=0xc8977e01 01 TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_pref_remote_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970601 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970a01 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc8177e01 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170601 01 TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170a01 01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_full_streaming_wr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc867fe01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_ddr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8678601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR event=0x35,umask=0xc8678601 11 unc_cha_tor_inserts.ia_miss_full_streaming_wr_local_ddr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8668601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_local_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR event=0x35,umask=0xc8668601 11 unc_cha_tor_inserts.ia_miss_full_streaming_wr_local_pmm uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8668a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_pmm uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8678a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_remote_ddr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8670601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_remote_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR event=0x35,umask=0xc8670601 11 unc_cha_tor_inserts.ia_miss_full_streaming_wr_remote_pmm uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8670a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Missed LLC event=0x35,umask=0xcc47fe01 01 TOR Inserts : ItoMs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefcode uncore cache TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC event=0x35,umask=0xcccffe01 01 TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefdata uncore cache TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC event=0x35,umask=0xccd7fe01 01 TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC event=0x35,umask=0xccc7fe01 01 TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc8668601 01 TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc8668a01 01 TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc86e8601 01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc86e8a01 01 TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_partial_streaming_wr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86ffe01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_ddr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f8601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR event=0x35,umask=0xc86f8601 11 unc_cha_tor_inserts.ia_miss_partial_streaming_wr_local_ddr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86e8601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_local_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR event=0x35,umask=0xc86e8601 11 unc_cha_tor_inserts.ia_miss_partial_streaming_wr_local_pmm uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86e8a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_pmm uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f8a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_remote_ddr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f0601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_remote_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR event=0x35,umask=0xc86f0601 11 unc_cha_tor_inserts.ia_miss_partial_streaming_wr_remote_pmm uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f0a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_remote_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc8670601 01 TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory event=0x35,umask=0xc8670a01 01 TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0601 01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0a01 01 TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC event=0x35,umask=0xc807fe01 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_local uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc806fe01 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_pref uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC event=0x35,umask=0xc887fe01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_pref_local uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc886fe01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_pref_remote uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc8877e01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_remote uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc8077e01 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_specitom uncore cache TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC event=0x35,umask=0xcc57fe01 01 TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_ucrdf uncore cache TOR Inserts : UCRdFs issued by iA Cores that Missed LLC event=0x35,umask=0xc877de01 01 TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores that Missed the LLC event=0x35,umask=0xc86ffe01 01 TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores that Missed the LLC event=0x35,umask=0xc867fe01 01 TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc8678601 01 TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc8678a01 01 TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc86f8601 01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc86f8a01 01 TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wil uncore cache TOR Inserts : WiLs issued by iA Cores that Missed LLC event=0x35,umask=0xc87fde01 01 TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_rfo uncore cache TOR Inserts : RFOs issued by iA Cores event=0x35,umask=0xc807ff01 01 TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_rfo_pref uncore cache TOR Inserts : RFO_Prefs issued by iA Cores event=0x35,umask=0xc887ff01 01 TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_specitom uncore cache TOR Inserts : SpecItoMs issued by iA Cores event=0x35,umask=0xcc57ff01 01 TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbeftoi uncore cache TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc37ff01 01 WbEFtoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbmtoe uncore cache TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc2fff01 01 WbMtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbstoi uncore cache TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc67ff01 01 WbStoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores event=0x35,umask=0xc86fff01 01 TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores event=0x35,umask=0xc867ff01 01 TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io uncore cache TOR Inserts : All requests from IO Devices event=0x35,umask=0xc001ff04 01 TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_clflush uncore cache TOR Inserts : CLFlushes issued by IO Devices event=0x35,umask=0xc8c3ff04 01 TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit uncore cache TOR Inserts : All requests from IO Devices that hit the LLC event=0x35,umask=0xc001fd04 01 TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_itom uncore cache TOR Inserts : ItoMs issued by IO Devices that Hit the LLC event=0x35,umask=0xcc43fd04 01 TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_pcirdcur uncore cache TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC event=0x35,umask=0xc8f3fd04 01 TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_rfo uncore cache TOR Inserts : RFOs issued by IO Devices that hit the LLC event=0x35,umask=0xc803fd04 01 TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom uncore cache TOR Inserts : ItoMs issued by IO Devices event=0x35,umask=0xcc43ff04 01 TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices event=0x35,umask=0xcd43ff04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear_local uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory event=0x35,umask=0xcd42ff04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear_remote uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory event=0x35,umask=0xcd437f04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom_local uncore cache TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory event=0x35,umask=0xcc42ff04 01 TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom_remote uncore cache TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory event=0x35,umask=0xcc437f04 01 TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss uncore cache TOR Inserts : All requests from IO Devices that missed the LLC event=0x35,umask=0xc001fe04 01 TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_itom uncore cache TOR Inserts : ItoMs issued by IO Devices that missed the LLC event=0x35,umask=0xcc43fe04 01 TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_pcirdcur uncore cache TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC event=0x35,umask=0xc8f3fe04 01 TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_rfo uncore cache TOR Inserts : RFOs issued by IO Devices that missed the LLC event=0x35,umask=0xc803fe04 01 TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur uncore cache TOR Inserts : PCIRdCurs issued by IO Devices event=0x35,umask=0xc8f3ff04 01 TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur_local uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xc8f2ff04 01 TOR Inserts : PCIRdCurs issued by IO Devices and targets local memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur_remote uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xc8f37f04 01 TOR Inserts : PCIRdCurs issued by IO Devices and targets remote memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_rfo uncore cache TOR Inserts : RFOs issued by IO Devices event=0x35,umask=0xc803ff04 01 TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_wbmtoi uncore cache TOR Inserts : WbMtoIs issued by IO Devices event=0x35,umask=0xcc23ff04 01 TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ipq uncore cache TOR Inserts : IPQ event=0x35,umask=8 01 TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.irq_ia uncore cache TOR Inserts : IRQ - iA event=0x35,umask=1 01 TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core unc_cha_tor_inserts.irq_non_ia uncore cache TOR Inserts : IRQ - Non iA event=0x35,umask=0x10 01 TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.isoc uncore cache TOR Inserts : Just ISOC event=0x35 01 TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.local_tgt uncore cache TOR Inserts : Just Local Targets event=0x35 01 TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.loc_all uncore cache TOR Inserts : All from Local iA and IO event=0x35,umask=0xc000ff05 01 TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests unc_cha_tor_inserts.loc_ia uncore cache TOR Inserts : All from Local iA event=0x35,umask=0xc000ff01 01 TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores unc_cha_tor_inserts.loc_io uncore cache TOR Inserts : All from Local IO event=0x35,umask=0xc000ff04 01 TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic unc_cha_tor_inserts.match_opc uncore cache TOR Inserts : Match the Opcode in b[29:19] of the extended umask field event=0x35 01 TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.miss uncore cache TOR Inserts : Just Misses event=0x35 01 TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.mmcfg uncore cache TOR Inserts : MMCFG Access event=0x35 01 TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.nearmem uncore cache TOR Inserts : Just NearMem event=0x35 01 TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.noncoh uncore cache TOR Inserts : Just NonCoherent event=0x35 01 TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.not_nearmem uncore cache TOR Inserts : Just NotNearMem event=0x35 01 TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.pmm uncore cache TOR Inserts : PMM Access event=0x35 01 TOR Inserts : PMM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.premorph_opc uncore cache TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x35 01 TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.prq_iosf uncore cache TOR Inserts : PRQ - IOSF event=0x35,umask=4 01 TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device unc_cha_tor_inserts.prq_non_iosf uncore cache TOR Inserts : PRQ - Non IOSF event=0x35,umask=0x20 01 TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.remote_tgt uncore cache TOR Inserts : Just Remote Targets event=0x35 01 TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.rrq uncore cache TOR Inserts : RRQ event=0x35,umask=0x40 01 TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.wbq uncore cache TOR Inserts : WBQ event=0x35,umask=0x80 01 TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ddr uncore cache TOR Occupancy : DDR4 Access event=0x36 01 TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.evict uncore cache TOR Occupancy : SF/LLC Evictions event=0x36,umask=2 01 TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_occupancy.hit uncore cache TOR Occupancy : Just Hits event=0x36 01 TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia uncore cache TOR Occupancy : All requests from iA Cores event=0x36,umask=0xc001ff01 01 TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_crd uncore cache TOR Occupancy : CRDs issued by iA Cores event=0x36,umask=0xc80fff01 01 TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd uncore cache TOR Occupancy : DRds issued by iA Cores event=0x36,umask=0xc817ff01 01 TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_opt uncore cache TOR Occupancy : DRd_Opts issued by iA Cores event=0x36,umask=0xc827ff01 01 TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_opt_pref uncore cache TOR Occupancy : DRd_Opt_Prefs issued by iA Cores event=0x36,umask=0xc8a7ff01 01 TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_pref uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores event=0x36,umask=0xc897ff01 01 TOR Occupancy : DRd_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy : All requests from iA Cores that Hit the LLC event=0x36,umask=0xc001fd01 01 TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Hit the LLC event=0x36,umask=0xc80ffd01 01 TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_crd_pref uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC event=0x36,umask=0xc88ffd01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Hit the LLC event=0x36,umask=0xc817fd01 01 TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_opt uncore cache TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC event=0x36,umask=0xc827fd01 01 TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_opt_pref uncore cache TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC event=0x36,umask=0xc8a7fd01 01 TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_pref uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC event=0x36,umask=0xc897fd01 01 TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefcode uncore cache TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC event=0x36,umask=0xcccffd01 01 TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefdata uncore cache TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC event=0x36,umask=0xccd7fd01 01 TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC event=0x36,umask=0xccc7fd01 01 TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Hit the LLC event=0x36,umask=0xc807fd01 01 TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_rfo_pref uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC event=0x36,umask=0xc887fd01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefcode uncore cache TOR Occupancy : LLCPrefCode issued by iA Cores event=0x36,umask=0xcccfff01 01 TOR Occupancy : LLCPrefCode issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefdata uncore cache TOR Occupancy : LLCPrefData issued by iA Cores event=0x36,umask=0xccd7ff01 01 TOR Occupancy : LLCPrefData issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores event=0x36,umask=0xccc7ff01 01 TOR Occupancy : LLCPrefRFO issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy : All requests from iA Cores that Missed the LLC event=0x36,umask=0xc001fe01 01 TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Missed the LLC event=0x36,umask=0xc80ffe01 01 TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_pref uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC event=0x36,umask=0xc88ffe01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC event=0x36,umask=0xc817fe01 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_ddr uncore cache TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8178601 01 TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_local uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc816fe01 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_opt uncore cache TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC event=0x36,umask=0xc827fe01 01 TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_opt_pref uncore cache TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC event=0x36,umask=0xc8a7fe01 01 TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pmm uncore cache TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8178a01 01 TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC event=0x36,umask=0xc897fe01 01 TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_remote uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc8177e01 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_full_streaming_wr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc867fe01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_ddr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8678601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_local_ddr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8668601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_local_pmm uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8668a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_pmm uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8678a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_remote_ddr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8670601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_remote_pmm uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8670a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefcode uncore cache TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC event=0x36,umask=0xcccffe01 01 TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefdata uncore cache TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC event=0x36,umask=0xccd7fe01 01 TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC event=0x36,umask=0xccc7fe01 01 TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_partial_streaming_wr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86ffe01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_ddr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f8601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_local_ddr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86e8601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_local_pmm uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86e8a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_pmm uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f8a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_remote_ddr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f0601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_remote_pmm uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f0a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC event=0x36,umask=0xc807fe01 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_local uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc806fe01 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_pref uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC event=0x36,umask=0xc887fe01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_pref_local uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc886fe01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_pref_remote uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc8877e01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_remote uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc8077e01 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_specitom uncore cache TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC event=0x36,umask=0xcc57fe01 01 TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC: For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores event=0x36,umask=0xc807ff01 01 TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_rfo_pref uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores event=0x36,umask=0xc887ff01 01 TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io uncore cache TOR Occupancy : All requests from IO Devices event=0x36,umask=0xc001ff04 01 TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy : All requests from IO Devices that hit the LLC event=0x36,umask=0xc001fd04 01 TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_itom uncore cache TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC event=0x36,umask=0xcc43fd04 01 TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_pcirdcur uncore cache TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC event=0x36,umask=0xc8f3fd04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_rfo uncore cache TOR Occupancy : RFOs issued by IO Devices that hit the LLC event=0x36,umask=0xc803fd04 01 TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_itom uncore cache TOR Occupancy : ItoMs issued by IO Devices event=0x36,umask=0xcc43ff04 01 TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy : All requests from IO Devices that missed the LLC event=0x36,umask=0xc001fe04 01 TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy : ItoMs issued by IO Devices that missed the LLC event=0x36,umask=0xcc43fe04 01 TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_pcirdcur uncore cache TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC event=0x36,umask=0xc8f3fe04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy : RFOs issued by IO Devices that missed the LLC event=0x36,umask=0xc803fe04 01 TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_pcirdcur uncore cache TOR Occupancy : PCIRdCurs issued by IO Devices event=0x36,umask=0xc8f3ff04 01 TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_rfo uncore cache TOR Occupancy : RFOs issued by IO Devices event=0x36,umask=0xc803ff04 01 TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ipq uncore cache TOR Occupancy : IPQ event=0x36,umask=8 01 TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.irq_ia uncore cache TOR Occupancy : IRQ - iA event=0x36,umask=1 01 TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core unc_cha_tor_occupancy.irq_non_ia uncore cache TOR Occupancy : IRQ - Non iA event=0x36,umask=0x10 01 TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.isoc uncore cache TOR Occupancy : Just ISOC event=0x36 01 TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.local_tgt uncore cache TOR Occupancy : Just Local Targets event=0x36 01 TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.loc_all uncore cache TOR Occupancy : All from Local iA and IO event=0x36,umask=0xc000ff05 01 TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests unc_cha_tor_occupancy.loc_ia uncore cache TOR Occupancy : All from Local iA event=0x36,umask=0xc000ff01 01 TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores unc_cha_tor_occupancy.loc_io uncore cache TOR Occupancy : All from Local IO event=0x36,umask=0xc000ff04 01 TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic unc_cha_tor_occupancy.match_opc uncore cache TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field event=0x36 01 TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.miss uncore cache TOR Occupancy : Just Misses event=0x36 01 TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.mmcfg uncore cache TOR Occupancy : MMCFG Access event=0x36 01 TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.nearmem uncore cache TOR Occupancy : Just NearMem event=0x36 01 TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.noncoh uncore cache TOR Occupancy : Just NonCoherent event=0x36 01 TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.not_nearmem uncore cache TOR Occupancy : Just NotNearMem event=0x36 01 TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.pmm uncore cache TOR Occupancy : PMM Access event=0x36 01 TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.premorph_opc uncore cache TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x36 01 TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.prq uncore cache TOR Occupancy : PRQ - IOSF event=0x36,umask=4 01 TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device unc_cha_tor_occupancy.prq_non_iosf uncore cache TOR Occupancy : PRQ - Non IOSF event=0x36,umask=0x20 01 TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.remote_tgt uncore cache TOR Occupancy : Just Remote Targets event=0x36 01 TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_txr_horz_ads_used.ad_all uncore cache CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11 01 CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_ads_used.ad_crd uncore cache CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10 01 CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.ad_uncrd uncore cache CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=1 01 CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_all uncore cache CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44 01 CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_ads_used.bl_crd uncore cache CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40 01 CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_uncrd uncore cache CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=4 01 CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_all uncore cache CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11 01 CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_bypass.ad_crd uncore cache CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10 01 CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_uncrd uncore cache CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=1 01 CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ak uncore cache CMS Horizontal Bypass Used : AK event=0xa7,umask=2 01 CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.akc_uncrd uncore cache CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80 01 CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_all uncore cache CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44 01 CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_bypass.bl_crd uncore cache CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40 01 CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_uncrd uncore cache CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=4 01 CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.iv uncore cache CMS Horizontal Bypass Used : IV event=0xa7,umask=8 01 CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_cycles_full.ad_all uncore cache Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_full.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ad_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=1 01 Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ak uncore cache Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=2 01 Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.akc_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_all uncore cache Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_full.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=4 01 Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.iv uncore cache Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=8 01 Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_all uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_ne.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=1 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ak uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=2 01 Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.akc_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_all uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_ne.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=4 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.iv uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=8 01 Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_all uncore cache CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11 01 CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_inserts.ad_crd uncore cache CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10 01 CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_uncrd uncore cache CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=1 01 CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ak uncore cache CMS Horizontal Egress Inserts : AK event=0xa1,umask=2 01 CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.akc_uncrd uncore cache CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80 01 CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_all uncore cache CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44 01 CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_inserts.bl_crd uncore cache CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40 01 CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_uncrd uncore cache CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=4 01 CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.iv uncore cache CMS Horizontal Egress Inserts : IV event=0xa1,umask=8 01 CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_nack.ad_all uncore cache CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11 01 CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_cha_txr_horz_nack.ad_crd uncore cache CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10 01 CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ad_uncrd uncore cache CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=1 01 CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ak uncore cache CMS Horizontal Egress NACKs : AK event=0xa4,umask=2 01 CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.akc_uncrd uncore cache CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80 01 CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_all uncore cache CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44 01 CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_cha_txr_horz_nack.bl_crd uncore cache CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40 01 CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_uncrd uncore cache CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=4 01 CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.iv uncore cache CMS Horizontal Egress NACKs : IV event=0xa4,umask=8 01 CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_occupancy.ad_all uncore cache CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11 01 CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_occupancy.ad_crd uncore cache CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10 01 CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ad_uncrd uncore cache CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=1 01 CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ak uncore cache CMS Horizontal Egress Occupancy : AK event=0xa0,umask=2 01 CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.akc_uncrd uncore cache CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80 01 CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_all uncore cache CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44 01 CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_occupancy.bl_crd uncore cache CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40 01 CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_uncrd uncore cache CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=4 01 CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.iv uncore cache CMS Horizontal Egress Occupancy : IV event=0xa0,umask=8 01 CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_starved.ad_all uncore cache CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=1 01 CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_cha_txr_horz_starved.ad_uncrd uncore cache CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=1 01 CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.ak uncore cache CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=2 01 CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.akc_uncrd uncore cache CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80 01 CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.bl_all uncore cache CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=4 01 CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_cha_txr_horz_starved.bl_uncrd uncore cache CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=4 01 CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.iv uncore cache CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=8 01 CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_vert_ads_used.ad_ag0 uncore cache CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ad_ag1 uncore cache CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag0 uncore cache CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag1 uncore cache CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag0 uncore cache CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag1 uncore cache CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag0 uncore cache CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=2 01 CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag1 uncore cache CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20 01 CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag0 uncore cache CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag1 uncore cache CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.iv_ag1 uncore cache CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=8 01 CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass_1.akc_ag0 uncore cache CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=1 01 CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass_1.akc_ag1 uncore cache CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=2 01 CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_cycles_full0.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=1 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_full0.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_cycles_full0.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=2 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_full0.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_full0.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=4 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_full0.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_full0.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=8 01 Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_cycles_full1.akc_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=1 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_full1.akc_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=2 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_ne0.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_ne0.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_cycles_ne0.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_ne0.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_ne0.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=4 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_ne0.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_ne0.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=8 01 Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_cycles_ne1.akc_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_ne1.akc_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_inserts0.ad_ag0 uncore cache CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=1 01 CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_inserts0.ad_ag1 uncore cache CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10 01 CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_inserts0.ak_ag0 uncore cache CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=2 01 CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_inserts0.ak_ag1 uncore cache CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20 01 CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_inserts0.bl_ag0 uncore cache CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=4 01 CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_inserts0.bl_ag1 uncore cache CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40 01 CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_inserts0.iv_ag0 uncore cache CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=8 01 CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_inserts1.akc_ag0 uncore cache CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=1 01 CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_inserts1.akc_ag1 uncore cache CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=2 01 CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_nack0.ad_ag0 uncore cache CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=1 01 CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.ad_ag1 uncore cache CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10 01 CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.ak_ag0 uncore cache CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=2 01 CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.ak_ag1 uncore cache CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20 01 CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.bl_ag0 uncore cache CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=4 01 CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.bl_ag1 uncore cache CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40 01 CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.iv_ag0 uncore cache CMS Vertical Egress NACKs : IV event=0x98,umask=8 01 CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack1.akc_ag0 uncore cache CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=1 01 CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack1.akc_ag1 uncore cache CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=2 01 CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_occupancy0.ad_ag0 uncore cache CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=1 01 CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_occupancy0.ad_ag1 uncore cache CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10 01 CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_occupancy0.ak_ag0 uncore cache CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=2 01 CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_occupancy0.ak_ag1 uncore cache CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20 01 CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_occupancy0.bl_ag0 uncore cache CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=4 01 CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_occupancy0.bl_ag1 uncore cache CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40 01 CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_occupancy0.iv_ag0 uncore cache CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=8 01 CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_occupancy1.akc_ag0 uncore cache CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=1 01 CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_occupancy1.akc_ag1 uncore cache CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=2 01 CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_starved0.ad_ag0 uncore cache CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=1 01 CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.ad_ag1 uncore cache CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10 01 CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.ak_ag0 uncore cache CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=2 01 CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.ak_ag1 uncore cache CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20 01 CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.bl_ag0 uncore cache CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=4 01 CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.bl_ag1 uncore cache CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40 01 CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.iv_ag0 uncore cache CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=8 01 CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved1.akc_ag0 uncore cache CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=1 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved1.akc_ag1 uncore cache CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=2 01 CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved1.tgc uncore cache CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=4 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_vert_ring_ad_in_use.dn_even uncore cache Vertical AD Ring In Use : Down and Even event=0xb0,umask=4 01 Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.dn_odd uncore cache Vertical AD Ring In Use : Down and Odd event=0xb0,umask=8 01 Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_even uncore cache Vertical AD Ring In Use : Up and Even event=0xb0,umask=1 01 Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_odd uncore cache Vertical AD Ring In Use : Up and Odd event=0xb0,umask=2 01 Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.dn_even uncore cache Vertical AKC Ring In Use : Down and Even event=0xb4,umask=4 01 Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.dn_odd uncore cache Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=8 01 Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.up_even uncore cache Vertical AKC Ring In Use : Up and Even event=0xb4,umask=1 01 Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.up_odd uncore cache Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=2 01 Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_even uncore cache Vertical AK Ring In Use : Down and Even event=0xb1,umask=4 01 Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_odd uncore cache Vertical AK Ring In Use : Down and Odd event=0xb1,umask=8 01 Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_even uncore cache Vertical AK Ring In Use : Up and Even event=0xb1,umask=1 01 Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_odd uncore cache Vertical AK Ring In Use : Up and Odd event=0xb1,umask=2 01 Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_even uncore cache Vertical BL Ring in Use : Down and Even event=0xb2,umask=4 01 Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_odd uncore cache Vertical BL Ring in Use : Down and Odd event=0xb2,umask=8 01 Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_even uncore cache Vertical BL Ring in Use : Up and Even event=0xb2,umask=1 01 Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_odd uncore cache Vertical BL Ring in Use : Up and Odd event=0xb2,umask=2 01 Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_iv_in_use.dn uncore cache Vertical IV Ring in Use : Down event=0xb3,umask=4 01 Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_vert_ring_iv_in_use.up uncore cache Vertical IV Ring in Use : Up event=0xb3,umask=1 01 Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_vert_ring_tgc_in_use.dn_even uncore cache Vertical TGC Ring In Use : Down and Even event=0xb5,umask=4 01 Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_tgc_in_use.dn_odd uncore cache Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=8 01 Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_tgc_in_use.up_even uncore cache Vertical TGC Ring In Use : Up and Even event=0xb5,umask=1 01 Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_tgc_in_use.up_odd uncore cache Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=2 01 Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_write_no_credits.mc10 uncore cache CHA iMC CHNx WRITE Credits Empty : MC10 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only unc_cha_write_no_credits.mc11 uncore cache CHA iMC CHNx WRITE Credits Empty : MC11 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only unc_cha_write_no_credits.mc12 uncore cache CHA iMC CHNx WRITE Credits Empty : MC12 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only unc_cha_write_no_credits.mc13 uncore cache CHA iMC CHNx WRITE Credits Empty : MC13 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only unc_cha_write_no_credits.mc6 uncore cache CHA iMC CHNx WRITE Credits Empty : MC6 event=0x5a,umask=0x40 01 CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only unc_cha_write_no_credits.mc7 uncore cache CHA iMC CHNx WRITE Credits Empty : MC7 event=0x5a,umask=0x80 01 CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only unc_cha_write_no_credits.mc8 uncore cache CHA iMC CHNx WRITE Credits Empty : MC8 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only unc_cha_write_no_credits.mc9 uncore cache CHA iMC CHNx WRITE Credits Empty : MC9 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy : Any Source event=0xf,umask=1 01 Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port unc_i_cache_total_occupancy.iv_q uncore interconnect Total Write Cache Occupancy : Snoops event=0xf,umask=2 01 Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_clockticks uncore interconnect Clockticks of the IO coherency tracker (IRP) event=1 01 unc_i_coherent_ops.clflush uncore interconnect Coherent Ops : CLFlush event=0x10,umask=0x80 01 Coherent Ops : CLFlush : Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.wbmtoi uncore interconnect Coherent Ops : WbMtoI event=0x10,umask=0x40 01 Coherent Ops : WbMtoI : Counts the number of coherency related operations serviced by the IRP unc_i_p2p_inserts uncore interconnect P2P Requests event=0x14 01 P2P Requests : P2P requests from the ITC unc_i_p2p_occupancy uncore interconnect P2P Occupancy event=0x15 01 P2P Occupancy : P2P B & S Queue Occupancy unc_i_p2p_transactions.cmpl uncore interconnect P2P Transactions : P2P completions event=0x13,umask=8 01 unc_i_p2p_transactions.loc uncore interconnect P2P Transactions : match if local only event=0x13,umask=0x40 01 unc_i_p2p_transactions.loc_and_tgt_match uncore interconnect P2P Transactions : match if local and target matches event=0x13,umask=0x80 01 unc_i_p2p_transactions.msg uncore interconnect P2P Transactions : P2P Message event=0x13,umask=4 01 unc_i_p2p_transactions.rd uncore interconnect P2P Transactions : P2P reads event=0x13,umask=1 01 unc_i_p2p_transactions.rem uncore interconnect P2P Transactions : Match if remote only event=0x13,umask=0x10 01 unc_i_p2p_transactions.rem_and_tgt_match uncore interconnect P2P Transactions : match if remote and target matches event=0x13,umask=0x20 01 unc_i_p2p_transactions.wr uncore interconnect P2P Transactions : P2P Writes event=0x13,umask=2 01 unc_i_transactions.atomic uncore interconnect Inbound Transaction Count : Atomic event=0x11,umask=0x10 01 Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions unc_i_transactions.other uncore interconnect Inbound Transaction Count : Other event=0x11,umask=0x20 01 Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions unc_i_transactions.writes uncore interconnect Inbound Transaction Count : Writes event=0x11,umask=2 01 Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry unc_i_txr2_ad01_stall_credit_cycles uncore interconnect UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES event=0x1c 01 : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2 unc_m2m_ag0_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=1 01 CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=2 01 CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=4 01 CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=8 01 CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10 01 CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20 01 CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40 01 CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80 01 CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=4 01 CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=1 01 CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=2 01 CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=1 01 CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=2 01 CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=4 01 CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=8 01 CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10 01 CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20 01 CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40 01 CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80 01 CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=4 01 CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=1 01 CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=2 01 CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=1 01 CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=2 01 CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=4 01 CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=8 01 CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10 01 CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20 01 CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40 01 CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80 01 CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=4 01 CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=1 01 CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=2 01 CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=1 01 CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=2 01 CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=4 01 CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=8 01 CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10 01 CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20 01 CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40 01 CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80 01 CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=4 01 CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=1 01 CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=2 01 CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=1 01 CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=2 01 CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=4 01 CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=8 01 CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10 01 CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20 01 CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40 01 CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80 01 CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=4 01 CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=1 01 CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=2 01 CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=1 01 CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=2 01 CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=4 01 CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=8 01 CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10 01 CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20 01 CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40 01 CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80 01 CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=4 01 CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=1 01 CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=2 01 CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=1 01 CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=2 01 CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=4 01 CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=8 01 CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=4 01 CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=1 01 CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=2 01 CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=1 01 CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=2 01 CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=4 01 CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=8 01 CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10 01 CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20 01 CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40 01 CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80 01 CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=4 01 CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=1 01 CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=2 01 CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_bypass_m2m_egress.not_taken uncore interconnect M2M to iMC Bypass : Not Taken event=0x22,umask=2 01 unc_m2m_bypass_m2m_egress.taken uncore interconnect M2M to iMC Bypass : Taken event=0x22,umask=1 01 unc_m2m_bypass_m2m_ingress.not_taken uncore interconnect M2M to iMC Bypass : Not Taken event=0x21,umask=2 01 unc_m2m_bypass_m2m_ingress.taken uncore interconnect M2M to iMC Bypass : Taken event=0x21,umask=1 01 unc_m2m_clockticks uncore interconnect Clockticks of the mesh to memory (M2M) event=0 01 unc_m2m_direct2core_not_taken_dirstate uncore interconnect Cycles when direct to core mode, which bypasses the CHA, was disabled event=0x24 01 unc_m2m_direct2core_not_taken_notforked uncore interconnect UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED event=0x60 01 unc_m2m_direct2core_txn_override uncore interconnect Number of reads in which direct to core transaction was overridden event=0x25 01 unc_m2m_direct2upi_not_taken_credits uncore interconnect Number of reads in which direct to Intel UPI transactions were overridden event=0x28 01 unc_m2m_direct2upi_not_taken_dirstate uncore interconnect Cycles when Direct2UPI was Disabled event=0x27 01 unc_m2m_direct2upi_txn_override uncore interconnect Number of reads that a message sent direct2 Intel UPI was overridden event=0x29 01 Clockticks of the mesh to PCI (M2P) unc_m2m_directory_hit.clean_a uncore interconnect Directory Hit : On NonDirty Line in A State event=0x2a,umask=0x80 01 unc_m2m_directory_hit.clean_i uncore interconnect Directory Hit : On NonDirty Line in I State event=0x2a,umask=0x10 01 unc_m2m_directory_hit.clean_p uncore interconnect Directory Hit : On NonDirty Line in L State event=0x2a,umask=0x40 01 unc_m2m_directory_hit.clean_s uncore interconnect Directory Hit : On NonDirty Line in S State event=0x2a,umask=0x20 01 unc_m2m_directory_hit.dirty_a uncore interconnect Directory Hit : On Dirty Line in A State event=0x2a,umask=8 01 unc_m2m_directory_hit.dirty_i uncore interconnect Directory Hit : On Dirty Line in I State event=0x2a,umask=1 01 unc_m2m_directory_hit.dirty_p uncore interconnect Directory Hit : On Dirty Line in L State event=0x2a,umask=4 01 unc_m2m_directory_hit.dirty_s uncore interconnect Directory Hit : On Dirty Line in S State event=0x2a,umask=2 01 unc_m2m_directory_lookup.any uncore interconnect Multi-socket cacheline Directory Lookups : Found in any state event=0x2d,umask=1 01 unc_m2m_directory_lookup.state_a uncore interconnect Multi-socket cacheline Directory Lookups : Found in A state event=0x2d,umask=8 01 unc_m2m_directory_lookup.state_i uncore interconnect Multi-socket cacheline Directory Lookups : Found in I state event=0x2d,umask=2 01 unc_m2m_directory_lookup.state_s uncore interconnect Multi-socket cacheline Directory Lookups : Found in S state event=0x2d,umask=4 01 unc_m2m_directory_miss.clean_a uncore interconnect Directory Miss : On NonDirty Line in A State event=0x2b,umask=0x80 01 unc_m2m_directory_miss.clean_i uncore interconnect Directory Miss : On NonDirty Line in I State event=0x2b,umask=0x10 01 unc_m2m_directory_miss.clean_p uncore interconnect Directory Miss : On NonDirty Line in L State event=0x2b,umask=0x40 01 unc_m2m_directory_miss.clean_s uncore interconnect Directory Miss : On NonDirty Line in S State event=0x2b,umask=0x20 01 unc_m2m_directory_miss.dirty_a uncore interconnect Directory Miss : On Dirty Line in A State event=0x2b,umask=8 01 unc_m2m_directory_miss.dirty_i uncore interconnect Directory Miss : On Dirty Line in I State event=0x2b,umask=1 01 unc_m2m_directory_miss.dirty_p uncore interconnect Directory Miss : On Dirty Line in L State event=0x2b,umask=4 01 unc_m2m_directory_miss.dirty_s uncore interconnect Directory Miss : On Dirty Line in S State event=0x2b,umask=2 01 unc_m2m_directory_update.any uncore interconnect Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode event=0x2e,umask=1 01 unc_m2m_distress_asserted.dpt_local uncore interconnect Distress signal asserted : DPT Local event=0xaf,umask=4 01 Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_m2m_distress_asserted.dpt_nonlocal uncore interconnect Distress signal asserted : DPT Remote event=0xaf,umask=8 01 Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_m2m_distress_asserted.dpt_stall_iv uncore interconnect Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40 01 Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_m2m_distress_asserted.dpt_stall_nocrd uncore interconnect Distress signal asserted : DPT Stalled - No Credit event=0xaf,umask=0x80 01 Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_m2m_distress_asserted.horz uncore interconnect Distress signal asserted : Horizontal event=0xaf,umask=2 01 Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_m2m_distress_asserted.pmm_local uncore interconnect Distress signal asserted : PMM Local event=0xaf,umask=0x10 01 Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2m_distress_asserted.pmm_nonlocal uncore interconnect Distress signal asserted : PMM Remote event=0xaf,umask=0x20 01 Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2m_distress_asserted.vert uncore interconnect Distress signal asserted : Vertical event=0xaf,umask=1 01 Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_m2m_distress_pmm uncore interconnect UNC_M2M_DISTRESS_PMM event=0xf2 01 unc_m2m_distress_pmm_memmode uncore interconnect UNC_M2M_DISTRESS_PMM_MEMMODE event=0xf1 01 unc_m2m_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements : Down event=0xba,umask=4 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements : Up event=0xba,umask=1 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use : Left and Even event=0xb6,umask=1 01 Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=2 01 Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use : Right and Even event=0xb6,umask=4 01 Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=8 01 Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xbb,umask=1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xbb,umask=4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xb7,umask=1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xb7,umask=4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use : Left and Even event=0xb8,umask=1 01 Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=2 01 Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use : Right and Even event=0xb8,umask=4 01 Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=8 01 Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use : Left event=0xb9,umask=1 01 Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use : Right event=0xb9,umask=4 01 Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_imc_reads.all uncore interconnect M2M Reads Issued to iMC : All, regardless of priority. - All Channels event=0x37,umask=0x704 01 unc_m2m_imc_reads.ch0_all uncore interconnect M2M Reads Issued to iMC : All, regardless of priority. - Ch0 event=0x37,umask=0x104 01 unc_m2m_imc_reads.ch0_from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - Ch0 event=0x37,umask=0x140 01 unc_m2m_imc_reads.ch0_isoch uncore interconnect M2M Reads Issued to iMC : Critical Priority - Ch0 event=0x37,umask=0x102 01 unc_m2m_imc_reads.ch0_normal uncore interconnect M2M Reads Issued to iMC : Normal Priority - Ch0 event=0x37,umask=0x101 01 unc_m2m_imc_reads.ch0_to_ddr_as_cache uncore interconnect M2M Reads Issued to iMC : DDR, acting as Cache - Ch0 event=0x37,umask=0x110 01 unc_m2m_imc_reads.ch0_to_ddr_as_mem uncore interconnect M2M Reads Issued to iMC : DDR - Ch0 event=0x37,umask=0x108 01 unc_m2m_imc_reads.ch0_to_pmm uncore interconnect M2M Reads Issued to iMC : PMM - Ch0 event=0x37,umask=0x120 01 M2M Reads Issued to iMC : PMM - Ch0 : Counts all PMM dimm read requests(full line) sent from M2M to iMC unc_m2m_imc_reads.ch1_all uncore interconnect M2M Reads Issued to iMC : All, regardless of priority. - Ch1 event=0x37,umask=0x204 01 unc_m2m_imc_reads.ch1_from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - Ch1 event=0x37,umask=0x240 01 unc_m2m_imc_reads.ch1_isoch uncore interconnect M2M Reads Issued to iMC : Critical Priority - Ch1 event=0x37,umask=0x202 01 unc_m2m_imc_reads.ch1_normal uncore interconnect M2M Reads Issued to iMC : Normal Priority - Ch1 event=0x37,umask=0x201 01 unc_m2m_imc_reads.ch1_to_ddr_as_cache uncore interconnect M2M Reads Issued to iMC : DDR, acting as Cache - Ch1 event=0x37,umask=0x210 01 unc_m2m_imc_reads.ch1_to_ddr_as_mem uncore interconnect M2M Reads Issued to iMC : DDR - Ch1 event=0x37,umask=0x208 01 unc_m2m_imc_reads.ch1_to_pmm uncore interconnect M2M Reads Issued to iMC : PMM - Ch1 event=0x37,umask=0x220 01 M2M Reads Issued to iMC : PMM - Ch1 : Counts all PMM dimm read requests(full line) sent from M2M to iMC unc_m2m_imc_reads.ch2_from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - Ch2 event=0x37,umask=0x440 01 unc_m2m_imc_reads.from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - All Channels event=0x37,umask=0x740 01 unc_m2m_imc_reads.isoch uncore interconnect M2M Reads Issued to iMC : Critical Priority - All Channels event=0x37,umask=0x702 01 unc_m2m_imc_reads.normal uncore interconnect M2M Reads Issued to iMC : Normal Priority - All Channels event=0x37,umask=0x701 01 unc_m2m_imc_reads.to_ddr_as_cache uncore interconnect M2M Reads Issued to iMC : DDR, acting as Cache - All Channels event=0x37,umask=0x710 01 unc_m2m_imc_reads.to_ddr_as_mem uncore interconnect M2M Reads Issued to iMC : DDR - All Channels event=0x37,umask=0x708 01 unc_m2m_imc_reads.to_pmm uncore interconnect M2M Reads Issued to iMC : PMM - All Channels event=0x37,umask=0x720 01 unc_m2m_imc_writes.all uncore interconnect M2M Writes Issued to iMC : All Writes - All Channels event=0x38,umask=0x1c10 01 unc_m2m_imc_writes.ch0_all uncore interconnect M2M Writes Issued to iMC : All Writes - Ch0 event=0x38,umask=0x410 01 unc_m2m_imc_writes.ch0_from_tgr uncore interconnect M2M Writes Issued to iMC : From TGR - Ch0 event=0x38 01 unc_m2m_imc_writes.ch0_full uncore interconnect M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0 event=0x38,umask=0x401 01 unc_m2m_imc_writes.ch0_full_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Full Line - Ch0 event=0x38,umask=0x404 01 unc_m2m_imc_writes.ch0_ni uncore interconnect M2M Writes Issued to iMC : Non-Inclusive - Ch0 event=0x38 01 unc_m2m_imc_writes.ch0_ni_miss uncore interconnect M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0 event=0x38 01 unc_m2m_imc_writes.ch0_partial uncore interconnect M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0 event=0x38,umask=0x402 01 unc_m2m_imc_writes.ch0_partial_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Partial - Ch0 event=0x38,umask=0x408 01 unc_m2m_imc_writes.ch0_to_ddr_as_cache uncore interconnect M2M Writes Issued to iMC : DDR, acting as Cache - Ch0 event=0x38,umask=0x440 01 unc_m2m_imc_writes.ch0_to_ddr_as_mem uncore interconnect M2M Writes Issued to iMC : DDR - Ch0 event=0x38,umask=0x420 01 unc_m2m_imc_writes.ch0_to_pmm uncore interconnect M2M Writes Issued to iMC : PMM - Ch0 event=0x38,umask=0x480 01 M2M Writes Issued to iMC : PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.ch1_all uncore interconnect M2M Writes Issued to iMC : All Writes - Ch1 event=0x38,umask=0x810 01 unc_m2m_imc_writes.ch1_from_tgr uncore interconnect M2M Writes Issued to iMC : From TGR - Ch1 event=0x38 01 unc_m2m_imc_writes.ch1_full uncore interconnect M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1 event=0x38,umask=0x801 01 unc_m2m_imc_writes.ch1_full_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Full Line - Ch1 event=0x38,umask=0x804 01 unc_m2m_imc_writes.ch1_ni uncore interconnect M2M Writes Issued to iMC : Non-Inclusive - Ch1 event=0x38 01 unc_m2m_imc_writes.ch1_ni_miss uncore interconnect M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1 event=0x38 01 unc_m2m_imc_writes.ch1_partial uncore interconnect M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1 event=0x38,umask=0x802 01 unc_m2m_imc_writes.ch1_partial_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Partial - Ch1 event=0x38,umask=0x808 01 unc_m2m_imc_writes.ch1_to_ddr_as_cache uncore interconnect M2M Writes Issued to iMC : DDR, acting as Cache - Ch1 event=0x38,umask=0x840 01 unc_m2m_imc_writes.ch1_to_ddr_as_mem uncore interconnect M2M Writes Issued to iMC : DDR - Ch1 event=0x38,umask=0x820 01 unc_m2m_imc_writes.ch1_to_pmm uncore interconnect M2M Writes Issued to iMC : PMM - Ch1 event=0x38,umask=0x880 01 M2M Writes Issued to iMC : PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.from_tgr uncore interconnect M2M Writes Issued to iMC : From TGR - All Channels event=0x38 01 unc_m2m_imc_writes.full uncore interconnect M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels event=0x38,umask=0x1c01 01 unc_m2m_imc_writes.full_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Full Line - All Channels event=0x38,umask=0x1c04 01 unc_m2m_imc_writes.ni uncore interconnect M2M Writes Issued to iMC : Non-Inclusive - All Channels event=0x38 01 unc_m2m_imc_writes.ni_miss uncore interconnect M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels event=0x38 01 unc_m2m_imc_writes.partial uncore interconnect M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels event=0x38,umask=0x1c02 01 unc_m2m_imc_writes.partial_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Partial - All Channels event=0x38,umask=0x1c08 01 unc_m2m_imc_writes.to_ddr_as_cache uncore interconnect M2M Writes Issued to iMC : DDR, acting as Cache - All Channels event=0x38,umask=0x1c40 01 unc_m2m_imc_writes.to_ddr_as_mem uncore interconnect M2M Writes Issued to iMC : DDR - All Channels event=0x38,umask=0x1c20 01 unc_m2m_imc_writes.to_pmm uncore interconnect M2M Writes Issued to iMC : PMM - All Channels event=0x38,umask=0x1c80 01 unc_m2m_mirr_wrq_inserts uncore interconnect Write Tracker Inserts event=0x64 01 unc_m2m_mirr_wrq_occupancy uncore interconnect Write Tracker Occupancy event=0x65 01 unc_m2m_misc_external.mbe_inst0 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=1 01 unc_m2m_misc_external.mbe_inst1 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=2 01 unc_m2m_pkt_match.mc uncore interconnect Number Packet Header Matches : MC Match event=0x4c,umask=2 01 unc_m2m_pkt_match.mesh uncore interconnect Number Packet Header Matches : Mesh Match event=0x4c,umask=1 01 unc_m2m_prefcam_cis_drops uncore interconnect UNC_M2M_PREFCAM_CIS_DROPS event=0x73 01 unc_m2m_prefcam_cycles_full.allch uncore interconnect Prefetch CAM Cycles Full : All Channels event=0x6b,umask=7 01 unc_m2m_prefcam_cycles_full.ch0 uncore interconnect Prefetch CAM Cycles Full : Channel 0 event=0x6b,umask=1 01 unc_m2m_prefcam_cycles_full.ch1 uncore interconnect Prefetch CAM Cycles Full : Channel 1 event=0x6b,umask=2 01 unc_m2m_prefcam_cycles_full.ch2 uncore interconnect Prefetch CAM Cycles Full : Channel 2 event=0x6b,umask=4 01 unc_m2m_prefcam_cycles_ne.allch uncore interconnect Prefetch CAM Cycles Not Empty : All Channels event=0x6c,umask=7 01 unc_m2m_prefcam_cycles_ne.ch0 uncore interconnect Prefetch CAM Cycles Not Empty : Channel 0 event=0x6c,umask=1 01 unc_m2m_prefcam_cycles_ne.ch1 uncore interconnect Prefetch CAM Cycles Not Empty : Channel 1 event=0x6c,umask=2 01 unc_m2m_prefcam_cycles_ne.ch2 uncore interconnect Prefetch CAM Cycles Not Empty : Channel 2 event=0x6c,umask=4 01 unc_m2m_prefcam_deallocs.ch0_hita0_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=1 01 unc_m2m_prefcam_deallocs.ch0_hita1_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=2 01 unc_m2m_prefcam_deallocs.ch0_miss_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=4 01 unc_m2m_prefcam_deallocs.ch0_rsp_pdreset uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=8 01 unc_m2m_prefcam_deallocs.ch1_hita0_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x10 01 unc_m2m_prefcam_deallocs.ch1_hita1_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x20 01 unc_m2m_prefcam_deallocs.ch1_miss_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x40 01 unc_m2m_prefcam_deallocs.ch1_rsp_pdreset uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x80 01 unc_m2m_prefcam_deallocs.ch2_hita0_inval uncore interconnect Prefetch CAM Deallocs event=0x6e 01 unc_m2m_prefcam_deallocs.ch2_hita1_inval uncore interconnect Prefetch CAM Deallocs event=0x6e 01 unc_m2m_prefcam_deallocs.ch2_miss_inval uncore interconnect Prefetch CAM Deallocs event=0x6e 01 unc_m2m_prefcam_deallocs.ch2_rsp_pdreset uncore interconnect Prefetch CAM Deallocs event=0x6e 01 unc_m2m_prefcam_demand_drops.ch0_upi uncore interconnect Data Prefetches Dropped : UPI - Ch 0 event=0x6f,umask=2 01 unc_m2m_prefcam_demand_drops.ch0_xpt uncore interconnect Data Prefetches Dropped : XPT - Ch 0 event=0x6f,umask=1 01 unc_m2m_prefcam_demand_drops.ch1_upi uncore interconnect Data Prefetches Dropped : UPI - Ch 1 event=0x6f,umask=8 01 unc_m2m_prefcam_demand_drops.ch1_xpt uncore interconnect Data Prefetches Dropped : XPT - Ch 1 event=0x6f,umask=4 01 unc_m2m_prefcam_demand_drops.ch2_upi uncore interconnect Data Prefetches Dropped : UPI - Ch 2 event=0x6f,umask=0x20 01 unc_m2m_prefcam_demand_drops.ch2_xpt uncore interconnect Data Prefetches Dropped : XPT - Ch 2 event=0x6f,umask=0x10 01 unc_m2m_prefcam_demand_drops.upi_allch uncore interconnect Data Prefetches Dropped : UPI - All Channels event=0x6f,umask=0x2a 01 unc_m2m_prefcam_demand_drops.xpt_allch uncore interconnect Data Prefetches Dropped : XPT - All Channels event=0x6f,umask=0x15 01 unc_m2m_prefcam_demand_merge.ch0_xptupi uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0 event=0x74,umask=1 01 Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0 unc_m2m_prefcam_demand_merge.ch1_xptupi uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1 event=0x74,umask=4 01 Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1 unc_m2m_prefcam_demand_merge.ch2_xptupi uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2 event=0x74,umask=0x10 01 Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2 unc_m2m_prefcam_demand_merge.xptupi_allch uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI- All Channels event=0x74,umask=0x15 01 Demands Merged with CAMed Prefetches : XPT & UPI - All Channels unc_m2m_prefcam_demand_no_merge.ch0_xptupi uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0 event=0x75,umask=1 01 Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0 unc_m2m_prefcam_demand_no_merge.ch1_xptupi uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1 event=0x75,umask=4 01 Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1 unc_m2m_prefcam_demand_no_merge.ch2_xptupi uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2 event=0x75,umask=0x10 01 unc_m2m_prefcam_demand_no_merge.xptupi_allch uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels event=0x75,umask=0x15 01 unc_m2m_prefcam_drop_reasons_ch0.errorblk_rxc uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x10 01 unc_m2m_prefcam_drop_reasons_ch0.not_pf_sad_region uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=2 01 unc_m2m_prefcam_drop_reasons_ch0.pf_ad_crd uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x20 01 unc_m2m_prefcam_drop_reasons_ch0.pf_cam_full uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x40 01 unc_m2m_prefcam_drop_reasons_ch0.pf_cam_hit uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=4 01 unc_m2m_prefcam_drop_reasons_ch0.pf_secure_drop uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=1 01 unc_m2m_prefcam_drop_reasons_ch0.rpq_proxy uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70 01 unc_m2m_prefcam_drop_reasons_ch0.stop_b2b uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=8 01 unc_m2m_prefcam_drop_reasons_ch0.upi_thresh uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70 01 unc_m2m_prefcam_drop_reasons_ch0.wpq_proxy uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x80 01 unc_m2m_prefcam_drop_reasons_ch0.xpt_thresh uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70 01 unc_m2m_prefcam_drop_reasons_ch1.errorblk_rxc uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x10 01 unc_m2m_prefcam_drop_reasons_ch1.not_pf_sad_region uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=2 01 unc_m2m_prefcam_drop_reasons_ch1.pf_ad_crd uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x20 01 unc_m2m_prefcam_drop_reasons_ch1.pf_cam_full uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x40 01 unc_m2m_prefcam_drop_reasons_ch1.pf_cam_hit uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=4 01 unc_m2m_prefcam_drop_reasons_ch1.pf_secure_drop uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=1 01 unc_m2m_prefcam_drop_reasons_ch1.rpq_proxy uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71 01 unc_m2m_prefcam_drop_reasons_ch1.stop_b2b uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=8 01 unc_m2m_prefcam_drop_reasons_ch1.upi_thresh uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71 01 unc_m2m_prefcam_drop_reasons_ch1.wpq_proxy uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x80 01 unc_m2m_prefcam_drop_reasons_ch1.xpt_thresh uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71 01 unc_m2m_prefcam_drop_reasons_ch2.errorblk_rxc uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x10 01 unc_m2m_prefcam_drop_reasons_ch2.not_pf_sad_region uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=2 01 unc_m2m_prefcam_drop_reasons_ch2.pf_ad_crd uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x20 01 unc_m2m_prefcam_drop_reasons_ch2.pf_cam_full uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x40 01 unc_m2m_prefcam_drop_reasons_ch2.pf_cam_hit uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=4 01 unc_m2m_prefcam_drop_reasons_ch2.pf_secure_drop uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=1 01 unc_m2m_prefcam_drop_reasons_ch2.rpq_proxy uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72 01 unc_m2m_prefcam_drop_reasons_ch2.stop_b2b uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=8 01 unc_m2m_prefcam_drop_reasons_ch2.upi_thresh uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72 01 unc_m2m_prefcam_drop_reasons_ch2.wpq_proxy uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x80 01 unc_m2m_prefcam_drop_reasons_ch2.xpt_thresh uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72 01 unc_m2m_prefcam_inserts.ch0_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 0 event=0x6d,umask=2 01 unc_m2m_prefcam_inserts.ch0_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 0 event=0x6d,umask=1 01 unc_m2m_prefcam_inserts.ch1_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 1 event=0x6d,umask=8 01 unc_m2m_prefcam_inserts.ch1_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 1 event=0x6d,umask=4 01 unc_m2m_prefcam_inserts.ch2_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 2 event=0x6d,umask=0x20 01 unc_m2m_prefcam_inserts.ch2_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 2 event=0x6d,umask=0x10 01 unc_m2m_prefcam_inserts.upi_allch uncore interconnect Prefetch CAM Inserts : UPI - All Channels event=0x6d,umask=0x2a 01 unc_m2m_prefcam_inserts.xpt_allch uncore interconnect Prefetch CAM Inserts : XPT - All Channels event=0x6d,umask=0x15 01 unc_m2m_prefcam_occupancy.allch uncore interconnect Prefetch CAM Occupancy : All Channels event=0x6a,umask=7 01 unc_m2m_prefcam_occupancy.ch0 uncore interconnect Prefetch CAM Occupancy : Channel 0 event=0x6a,umask=1 01 unc_m2m_prefcam_occupancy.ch1 uncore interconnect Prefetch CAM Occupancy : Channel 1 event=0x6a,umask=2 01 unc_m2m_prefcam_occupancy.ch2 uncore interconnect Prefetch CAM Occupancy : Channel 2 event=0x6a,umask=4 01 unc_m2m_prefcam_resp_miss.allch uncore interconnect : All Channels event=0x76,umask=7 01 unc_m2m_prefcam_resp_miss.ch0 uncore interconnect : Channel 0 event=0x76,umask=1 01 unc_m2m_prefcam_resp_miss.ch1 uncore interconnect : Channel 1 event=0x76,umask=2 01 unc_m2m_prefcam_resp_miss.ch2 uncore interconnect : Channel 2 event=0x76,umask=4 01 unc_m2m_prefcam_rxc_cycles_ne uncore interconnect UNC_M2M_PREFCAM_RxC_CYCLES_NE event=0x79 01 unc_m2m_prefcam_rxc_deallocs.1lm_posted uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED event=0x7a,umask=2 01 unc_m2m_prefcam_rxc_deallocs.cis uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS event=0x7a,umask=8 01 unc_m2m_prefcam_rxc_deallocs.pmm_memmode_accept uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT event=0x7a,umask=4 01 unc_m2m_prefcam_rxc_deallocs.squashed uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED event=0x7a,umask=1 01 unc_m2m_prefcam_rxc_inserts uncore interconnect UNC_M2M_PREFCAM_RxC_INSERTS event=0x78 01 unc_m2m_prefcam_rxc_occupancy uncore interconnect UNC_M2M_PREFCAM_RxC_OCCUPANCY event=0x77 01 unc_m2m_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=1 01 Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=2 01 Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=4 01 Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=8 01 Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=1 01 Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=2 01 Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.akc uncore interconnect Messages that bounced on the Vertical Ring event=0xaa,umask=0x10 01 Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=4 01 Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=8 01 Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring : AD event=0xad,umask=1 01 unc_m2m_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring : AK event=0xad,umask=2 01 unc_m2m_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20 01 unc_m2m_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring : BL event=0xad,umask=4 01 unc_m2m_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring : IV event=0xad,umask=8 01 unc_m2m_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring : AD event=0xab,umask=1 01 unc_m2m_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=2 01 unc_m2m_ring_sink_starved_vert.akc uncore interconnect Sink Starvation on Vertical Ring event=0xab,umask=0x10 01 unc_m2m_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=4 01 unc_m2m_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=8 01 unc_m2m_ring_src_thrtl uncore interconnect Source Throttle event=0xae 01 unc_m2m_rpq_no_reg_crd.ch0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0 event=0x43,umask=1 01 unc_m2m_rpq_no_reg_crd.ch1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1 event=0x43,umask=2 01 unc_m2m_rpq_no_reg_crd.ch2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2 event=0x43,umask=4 01 unc_m2m_rpq_no_reg_crd_pmm.chn0 uncore interconnect M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0 event=0x4f,umask=1 01 unc_m2m_rpq_no_reg_crd_pmm.chn1 uncore interconnect M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1 event=0x4f,umask=2 01 unc_m2m_rpq_no_reg_crd_pmm.chn2 uncore interconnect M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2 event=0x4f,umask=4 01 unc_m2m_rpq_no_spec_crd.ch0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special : Channel 0 event=0x44,umask=1 01 unc_m2m_rpq_no_spec_crd.ch1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special : Channel 1 event=0x44,umask=2 01 unc_m2m_rpq_no_spec_crd.ch2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special : Channel 2 event=0x44,umask=4 01 unc_m2m_rxc_ad_inserts uncore interconnect AD Ingress (from CMS) Allocations event=1 01 unc_m2m_rxc_ad_pref_occupancy uncore interconnect AD Ingress (from CMS) Occupancy - Prefetches event=0x77 01 unc_m2m_rxc_ak_wr_cmp uncore interconnect AK Egress (to CMS) Allocations event=0x5c 01 unc_m2m_rxr_busy_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe5,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2m_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe5,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2m_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_bypass.ad_all uncore interconnect Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11 01 Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2m_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10 01 Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ad_uncrd uncore interconnect Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=1 01 Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ak uncore interconnect Transgress Ingress Bypass : AK event=0xe2,umask=2 01 Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.akc_uncrd uncore interconnect Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80 01 Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_all uncore interconnect Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44 01 Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2m_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40 01 Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_uncrd uncore interconnect Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=4 01 Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.iv uncore interconnect Transgress Ingress Bypass : IV event=0xe2,umask=8 01 Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_m2m_rxr_crd_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe3,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2m_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ak uncore interconnect Transgress Injection Starvation : AK event=0xe3,umask=2 01 Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe3,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2m_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80 01 Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.iv uncore interconnect Transgress Injection Starvation : IV event=0xe3,umask=8 01 Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved_1 uncore interconnect Transgress Injection Starvation event=0xe4 01 Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_inserts.ad_all uncore interconnect Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11 01 Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10 01 Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ad_uncrd uncore interconnect Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=1 01 Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ak uncore interconnect Transgress Ingress Allocations : AK event=0xe1,umask=2 01 Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.akc_uncrd uncore interconnect Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80 01 Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_all uncore interconnect Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44 01 Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40 01 Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_uncrd uncore interconnect Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=4 01 Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.iv uncore interconnect Transgress Ingress Allocations : IV event=0xe1,umask=8 01 Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_all uncore interconnect Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11 01 Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10 01 Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_uncrd uncore interconnect Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=1 01 Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ak uncore interconnect Transgress Ingress Occupancy : AK event=0xe0,umask=2 01 Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.akc_uncrd uncore interconnect Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80 01 Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_all uncore interconnect Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44 01 Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20 01 Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_uncrd uncore interconnect Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=4 01 Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.iv uncore interconnect Transgress Ingress Occupancy : IV event=0xe0,umask=8 01 Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_scoreboard_ad_retry_accepts uncore interconnect UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS event=0x33 01 unc_m2m_scoreboard_ad_retry_rejects uncore interconnect UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS event=0x34 01 unc_m2m_scoreboard_bl_retry_accepts uncore interconnect Retry - Mem Mirroring Mode event=0x35 01 unc_m2m_scoreboard_bl_retry_rejects uncore interconnect Retry - Mem Mirroring Mode event=0x36 01 unc_m2m_scoreboard_rd_accepts uncore interconnect Scoreboard Accepts event=0x2f 01 unc_m2m_scoreboard_rd_rejects uncore interconnect Scoreboard Rejects event=0x30 01 unc_m2m_scoreboard_wr_accepts uncore interconnect Scoreboard Accepts event=0x31 01 unc_m2m_scoreboard_wr_rejects uncore interconnect Scoreboard Rejects event=0x32 01 unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=8 01 Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10 01 Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20 01 Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40 01 Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80 01 Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=8 01 Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10 01 Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20 01 Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40 01 Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80 01 Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=8 01 Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10 01 Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20 01 Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40 01 Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80 01 Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=8 01 Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10 01 Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20 01 Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40 01 Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80 01 Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_tag_hit.nm_rd_hit_clean uncore interconnect Tag Hit : Clean NearMem Read Hit event=0x2c,umask=1 01 Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_rd_hit_dirty uncore interconnect Tag Hit : Dirty NearMem Read Hit event=0x2c,umask=2 01 Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_ufill_hit_clean uncore interconnect Tag Hit : Clean NearMem Underfill Hit event=0x2c,umask=4 01 Tag Hit : Clean NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write unc_m2m_tag_hit.nm_ufill_hit_dirty uncore interconnect Tag Hit : Dirty NearMem Underfill Hit event=0x2c,umask=8 01 Tag Hit : Dirty NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write unc_m2m_tag_miss uncore interconnect Tag Miss event=0x61 01 unc_m2m_tracker_full.ch0 uncore interconnect Tracker Cycles Full : Channel 0 event=0x45,umask=1 01 unc_m2m_tracker_full.ch1 uncore interconnect Tracker Cycles Full : Channel 1 event=0x45,umask=2 01 unc_m2m_tracker_full.ch2 uncore interconnect Tracker Cycles Full : Channel 2 event=0x45,umask=4 01 unc_m2m_tracker_inserts.ch0 uncore interconnect Tracker Inserts : Channel 0 event=0x49,umask=1 01 unc_m2m_tracker_inserts.ch1 uncore interconnect Tracker Inserts : Channel 1 event=0x49,umask=2 01 unc_m2m_tracker_inserts.ch2 uncore interconnect Tracker Inserts : Channel 2 event=0x49,umask=4 01 unc_m2m_tracker_ne.ch0 uncore interconnect Tracker Cycles Not Empty : Channel 0 event=0x46,umask=1 01 unc_m2m_tracker_ne.ch1 uncore interconnect Tracker Cycles Not Empty : Channel 1 event=0x46,umask=2 01 unc_m2m_tracker_ne.ch2 uncore interconnect Tracker Cycles Not Empty : Channel 2 event=0x46,umask=4 01 unc_m2m_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy : Channel 0 event=0x47,umask=1 01 unc_m2m_tracker_occupancy.ch1 uncore interconnect Tracker Occupancy : Channel 1 event=0x47,umask=2 01 unc_m2m_tracker_occupancy.ch2 uncore interconnect Tracker Occupancy : Channel 2 event=0x47,umask=4 01 unc_m2m_txc_ak.crd_cbo uncore interconnect Outbound Ring Transactions on AK : CRD Transactions to Cbo event=0x39,umask=2 01 unc_m2m_txc_ak.ndr uncore interconnect Outbound Ring Transactions on AK : NDR Transactions event=0x39,umask=1 01 unc_m2m_txc_akc_credits uncore interconnect AKC Credits event=0x5f 01 unc_m2m_txc_ak_credits_acquired.cms0 uncore interconnect AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side event=0x1d,umask=1 01 unc_m2m_txc_ak_credits_acquired.cms1 uncore interconnect AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side event=0x1d,umask=2 01 unc_m2m_txc_ak_cycles_full.all uncore interconnect AK Egress (to CMS) Full : All event=0x14,umask=3 01 unc_m2m_txc_ak_cycles_full.cms0 uncore interconnect AK Egress (to CMS) Full : Common Mesh Stop - Near Side event=0x14,umask=1 01 unc_m2m_txc_ak_cycles_full.cms1 uncore interconnect AK Egress (to CMS) Full : Common Mesh Stop - Far Side event=0x14,umask=2 01 unc_m2m_txc_ak_cycles_full.rdcrd0 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=8 01 unc_m2m_txc_ak_cycles_full.rdcrd1 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x88 01 unc_m2m_txc_ak_cycles_full.wrcmp0 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x20 01 unc_m2m_txc_ak_cycles_full.wrcmp1 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0xa0 01 unc_m2m_txc_ak_cycles_full.wrcrd0 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x10 01 unc_m2m_txc_ak_cycles_full.wrcrd1 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x90 01 unc_m2m_txc_ak_cycles_ne.all uncore interconnect AK Egress (to CMS) Not Empty : All event=0x13,umask=3 01 unc_m2m_txc_ak_cycles_ne.cms0 uncore interconnect AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side event=0x13,umask=1 01 unc_m2m_txc_ak_cycles_ne.cms1 uncore interconnect AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side event=0x13,umask=2 01 unc_m2m_txc_ak_cycles_ne.rdcrd uncore interconnect AK Egress (to CMS) Not Empty event=0x13,umask=8 01 unc_m2m_txc_ak_cycles_ne.wrcmp uncore interconnect AK Egress (to CMS) Not Empty event=0x13,umask=0x20 01 unc_m2m_txc_ak_cycles_ne.wrcrd uncore interconnect AK Egress (to CMS) Not Empty event=0x13,umask=0x10 01 unc_m2m_txc_ak_inserts.all uncore interconnect AK Egress (to CMS) Allocations : All event=0x11,umask=3 01 unc_m2m_txc_ak_inserts.cms0 uncore interconnect AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side event=0x11,umask=1 01 unc_m2m_txc_ak_inserts.cms1 uncore interconnect AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side event=0x11,umask=2 01 unc_m2m_txc_ak_inserts.pref_rd_cam_hit uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=0x40 01 unc_m2m_txc_ak_inserts.rdcrd uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=8 01 unc_m2m_txc_ak_inserts.wrcmp uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=0x20 01 unc_m2m_txc_ak_inserts.wrcrd uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=0x10 01 unc_m2m_txc_ak_no_credit_cycles.cms0 uncore interconnect Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x1f,umask=1 01 unc_m2m_txc_ak_no_credit_cycles.cms1 uncore interconnect Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x1f,umask=2 01 unc_m2m_txc_ak_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x20,umask=1 01 unc_m2m_txc_ak_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x20,umask=2 01 unc_m2m_txc_ak_occupancy.all uncore interconnect AK Egress (to CMS) Occupancy : All event=0x12,umask=3 01 unc_m2m_txc_ak_occupancy.cms0 uncore interconnect AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side event=0x12,umask=1 01 unc_m2m_txc_ak_occupancy.cms1 uncore interconnect AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side event=0x12,umask=2 01 unc_m2m_txc_ak_occupancy.rdcrd uncore interconnect AK Egress (to CMS) Occupancy event=0x12,umask=8 01 unc_m2m_txc_ak_occupancy.wrcmp uncore interconnect AK Egress (to CMS) Occupancy event=0x12,umask=0x20 01 unc_m2m_txc_ak_occupancy.wrcrd uncore interconnect AK Egress (to CMS) Occupancy event=0x12,umask=0x10 01 unc_m2m_txc_bl.drs_cache uncore interconnect Outbound DRS Ring Transactions to Cache : Data to Cache event=0x40,umask=1 01 unc_m2m_txc_bl.drs_core uncore interconnect Outbound DRS Ring Transactions to Cache : Data to Core event=0x40,umask=2 01 unc_m2m_txc_bl.drs_upi uncore interconnect Outbound DRS Ring Transactions to Cache : Data to QPI event=0x40,umask=4 01 unc_m2m_txc_bl_credits_acquired.cms0 uncore interconnect BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side event=0x19,umask=1 01 unc_m2m_txc_bl_credits_acquired.cms1 uncore interconnect BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side event=0x19,umask=2 01 unc_m2m_txc_bl_cycles_full.all uncore interconnect BL Egress (to CMS) Full : All event=0x18,umask=3 01 unc_m2m_txc_bl_cycles_full.cms0 uncore interconnect BL Egress (to CMS) Full : Common Mesh Stop - Near Side event=0x18,umask=1 01 unc_m2m_txc_bl_cycles_full.cms1 uncore interconnect BL Egress (to CMS) Full : Common Mesh Stop - Far Side event=0x18,umask=2 01 unc_m2m_txc_bl_cycles_ne.all uncore interconnect BL Egress (to CMS) Not Empty : All event=0x17,umask=3 01 unc_m2m_txc_bl_cycles_ne.cms0 uncore interconnect BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side event=0x17,umask=1 01 unc_m2m_txc_bl_cycles_ne.cms1 uncore interconnect BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side event=0x17,umask=2 01 unc_m2m_txc_bl_inserts.all uncore interconnect BL Egress (to CMS) Allocations : All event=0x15,umask=3 01 unc_m2m_txc_bl_inserts.cms0 uncore interconnect BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side event=0x15,umask=1 01 unc_m2m_txc_bl_inserts.cms1 uncore interconnect BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side event=0x15,umask=2 01 unc_m2m_txc_bl_no_credit_cycles.cms0 uncore interconnect Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x1b,umask=1 01 unc_m2m_txc_bl_no_credit_cycles.cms1 uncore interconnect Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x1b,umask=2 01 unc_m2m_txc_bl_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x1c,umask=1 01 unc_m2m_txc_bl_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x1c,umask=2 01 unc_m2m_txr_horz_ads_used.ad_all uncore interconnect CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11 01 CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10 01 CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.ad_uncrd uncore interconnect CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=1 01 CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_all uncore interconnect CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44 01 CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40 01 CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_uncrd uncore interconnect CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=4 01 CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_all uncore interconnect CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11 01 CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10 01 CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_uncrd uncore interconnect CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=1 01 CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ak uncore interconnect CMS Horizontal Bypass Used : AK event=0xa7,umask=2 01 CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.akc_uncrd uncore interconnect CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80 01 CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_all uncore interconnect CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44 01 CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40 01 CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_uncrd uncore interconnect CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=4 01 CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.iv uncore interconnect CMS Horizontal Bypass Used : IV event=0xa7,umask=8 01 CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_cycles_full.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=1 01 Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=2 01 Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=4 01 Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=8 01 Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=1 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=2 01 Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=4 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=8 01 Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_all uncore interconnect CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11 01 CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10 01 CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_uncrd uncore interconnect CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=1 01 CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ak uncore interconnect CMS Horizontal Egress Inserts : AK event=0xa1,umask=2 01 CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.akc_uncrd uncore interconnect CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80 01 CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_all uncore interconnect CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44 01 CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40 01 CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_uncrd uncore interconnect CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=4 01 CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.iv uncore interconnect CMS Horizontal Egress Inserts : IV event=0xa1,umask=8 01 CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_nack.ad_all uncore interconnect CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11 01 CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2m_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10 01 CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ad_uncrd uncore interconnect CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=1 01 CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ak uncore interconnect CMS Horizontal Egress NACKs : AK event=0xa4,umask=2 01 CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.akc_uncrd uncore interconnect CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80 01 CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_all uncore interconnect CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44 01 CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2m_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40 01 CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_uncrd uncore interconnect CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=4 01 CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.iv uncore interconnect CMS Horizontal Egress NACKs : IV event=0xa4,umask=8 01 CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_occupancy.ad_all uncore interconnect CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11 01 CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10 01 CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ad_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=1 01 CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ak uncore interconnect CMS Horizontal Egress Occupancy : AK event=0xa0,umask=2 01 CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.akc_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80 01 CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_all uncore interconnect CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44 01 CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40 01 CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_uncrd uncore interconnect CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=4 01 CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.iv uncore interconnect CMS Horizontal Egress Occupancy : IV event=0xa0,umask=8 01 CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_starved.ad_all uncore interconnect CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=1 01 CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2m_txr_horz_starved.ad_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=1 01 CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.ak uncore interconnect CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=2 01 CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.akc_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80 01 CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.bl_all uncore interconnect CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=4 01 CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2m_txr_horz_starved.bl_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=4 01 CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.iv uncore interconnect CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=8 01 CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=2 01 CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20 01 CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.iv_ag1 uncore interconnect CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=8 01 CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass_1.akc_ag0 uncore interconnect CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=1 01 CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass_1.akc_ag1 uncore interconnect CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=2 01 CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_cycles_full0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=1 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_full0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_cycles_full0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=2 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_full0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_full0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=4 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_full0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_full0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=8 01 Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_cycles_full1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=1 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_full1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=2 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_ne0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_ne0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_cycles_ne0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_ne0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_ne0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=4 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_ne0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_ne0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=8 01 Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_cycles_ne1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_ne1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_inserts0.ad_ag0 uncore interconnect CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=1 01 CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_inserts0.ad_ag1 uncore interconnect CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10 01 CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_inserts0.ak_ag0 uncore interconnect CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=2 01 CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_inserts0.ak_ag1 uncore interconnect CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20 01 CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_inserts0.bl_ag0 uncore interconnect CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=4 01 CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_inserts0.bl_ag1 uncore interconnect CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40 01 CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_inserts0.iv_ag0 uncore interconnect CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=8 01 CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_inserts1.akc_ag0 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=1 01 CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_inserts1.akc_ag1 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=2 01 CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_nack0.ad_ag0 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=1 01 CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.ad_ag1 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10 01 CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.ak_ag0 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=2 01 CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.ak_ag1 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20 01 CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.bl_ag0 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=4 01 CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.bl_ag1 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40 01 CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.iv_ag0 uncore interconnect CMS Vertical Egress NACKs : IV event=0x98,umask=8 01 CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack1.akc_ag0 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=1 01 CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack1.akc_ag1 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=2 01 CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_occupancy0.ad_ag0 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=1 01 CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_occupancy0.ad_ag1 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10 01 CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_occupancy0.ak_ag0 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=2 01 CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_occupancy0.ak_ag1 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20 01 CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_occupancy0.bl_ag0 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=4 01 CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_occupancy0.bl_ag1 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40 01 CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_occupancy0.iv_ag0 uncore interconnect CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=8 01 CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_occupancy1.akc_ag0 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=1 01 CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_occupancy1.akc_ag1 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=2 01 CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_starved0.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=1 01 CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10 01 CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=2 01 CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20 01 CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=4 01 CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40 01 CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.iv_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=8 01 CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved1.akc_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=1 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved1.akc_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=2 01 CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved1.tgc uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=4 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use : Down and Even event=0xb0,umask=4 01 Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use : Down and Odd event=0xb0,umask=8 01 Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use : Up and Even event=0xb0,umask=1 01 Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use : Up and Odd event=0xb0,umask=2 01 Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.dn_even uncore interconnect Vertical AKC Ring In Use : Down and Even event=0xb4,umask=4 01 Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.dn_odd uncore interconnect Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=8 01 Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.up_even uncore interconnect Vertical AKC Ring In Use : Up and Even event=0xb4,umask=1 01 Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.up_odd uncore interconnect Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=2 01 Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use : Down and Even event=0xb1,umask=4 01 Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use : Down and Odd event=0xb1,umask=8 01 Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use : Up and Even event=0xb1,umask=1 01 Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use : Up and Odd event=0xb1,umask=2 01 Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use : Down and Even event=0xb2,umask=4 01 Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use : Down and Odd event=0xb2,umask=8 01 Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use : Up and Even event=0xb2,umask=1 01 Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use : Up and Odd event=0xb2,umask=2 01 Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use : Down event=0xb3,umask=4 01 Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use : Up event=0xb3,umask=1 01 Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_vert_ring_tgc_in_use.dn_even uncore interconnect Vertical TGC Ring In Use : Down and Even event=0xb5,umask=4 01 Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_tgc_in_use.dn_odd uncore interconnect Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=8 01 Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_tgc_in_use.up_even uncore interconnect Vertical TGC Ring In Use : Up and Even event=0xb5,umask=1 01 Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_tgc_in_use.up_odd uncore interconnect Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=2 01 Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_wpq_flush.ch0 uncore interconnect WPQ Flush : Channel 0 event=0x58,umask=1 01 unc_m2m_wpq_flush.ch1 uncore interconnect WPQ Flush : Channel 1 event=0x58,umask=2 01 unc_m2m_wpq_flush.ch2 uncore interconnect WPQ Flush : Channel 2 event=0x58,umask=4 01 unc_m2m_wpq_no_reg_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0 event=0x4d,umask=1 01 unc_m2m_wpq_no_reg_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1 event=0x4d,umask=2 01 unc_m2m_wpq_no_reg_crd.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2 event=0x4d,umask=4 01 unc_m2m_wpq_no_reg_crd_pmm.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0 event=0x51,umask=1 01 unc_m2m_wpq_no_reg_crd_pmm.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1 event=0x51,umask=2 01 unc_m2m_wpq_no_reg_crd_pmm.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2 event=0x51,umask=4 01 unc_m2m_wpq_no_spec_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 0 event=0x4e,umask=1 01 unc_m2m_wpq_no_spec_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 1 event=0x4e,umask=2 01 unc_m2m_wpq_no_spec_crd.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 2 event=0x4e,umask=4 01 unc_m2m_wr_tracker_full.ch0 uncore interconnect Write Tracker Cycles Full : Channel 0 event=0x4a,umask=1 01 unc_m2m_wr_tracker_full.ch1 uncore interconnect Write Tracker Cycles Full : Channel 1 event=0x4a,umask=2 01 unc_m2m_wr_tracker_full.ch2 uncore interconnect Write Tracker Cycles Full : Channel 2 event=0x4a,umask=4 01 unc_m2m_wr_tracker_full.mirr uncore interconnect Write Tracker Cycles Full : Mirror event=0x4a,umask=8 01 unc_m2m_wr_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts : Channel 0 event=0x56,umask=1 01 unc_m2m_wr_tracker_inserts.ch1 uncore interconnect Write Tracker Inserts : Channel 1 event=0x56,umask=2 01 unc_m2m_wr_tracker_inserts.ch2 uncore interconnect Write Tracker Inserts : Channel 2 event=0x56,umask=4 01 unc_m2m_wr_tracker_ne.ch0 uncore interconnect Write Tracker Cycles Not Empty : Channel 0 event=0x4b,umask=1 01 unc_m2m_wr_tracker_ne.ch1 uncore interconnect Write Tracker Cycles Not Empty : Channel 1 event=0x4b,umask=2 01 unc_m2m_wr_tracker_ne.ch2 uncore interconnect Write Tracker Cycles Not Empty : Channel 2 event=0x4b,umask=4 01 unc_m2m_wr_tracker_ne.mirr uncore interconnect Write Tracker Cycles Not Empty : Mirror event=0x4b,umask=8 01 unc_m2m_wr_tracker_ne.mirr_nontgr uncore interconnect Write Tracker Cycles Not Empty event=0x4b,umask=0x10 01 unc_m2m_wr_tracker_ne.mirr_pwr uncore interconnect Write Tracker Cycles Not Empty event=0x4b,umask=0x20 01 unc_m2m_wr_tracker_nonposted_inserts.ch0 uncore interconnect Write Tracker Non-Posted Inserts : Channel 0 event=0x63,umask=1 01 unc_m2m_wr_tracker_nonposted_inserts.ch1 uncore interconnect Write Tracker Non-Posted Inserts : Channel 1 event=0x63,umask=2 01 unc_m2m_wr_tracker_nonposted_inserts.ch2 uncore interconnect Write Tracker Non-Posted Inserts : Channel 2 event=0x63,umask=4 01 unc_m2m_wr_tracker_nonposted_occupancy.ch0 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 0 event=0x62,umask=1 01 unc_m2m_wr_tracker_nonposted_occupancy.ch1 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 1 event=0x62,umask=2 01 unc_m2m_wr_tracker_nonposted_occupancy.ch2 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 2 event=0x62,umask=4 01 unc_m2m_wr_tracker_occupancy.ch0 uncore interconnect Write Tracker Occupancy : Channel 0 event=0x55,umask=1 01 unc_m2m_wr_tracker_occupancy.ch1 uncore interconnect Write Tracker Occupancy : Channel 1 event=0x55,umask=2 01 unc_m2m_wr_tracker_occupancy.ch2 uncore interconnect Write Tracker Occupancy : Channel 2 event=0x55,umask=4 01 unc_m2m_wr_tracker_occupancy.mirr uncore interconnect Write Tracker Occupancy : Mirror event=0x55,umask=8 01 unc_m2m_wr_tracker_occupancy.mirr_nontgr uncore interconnect Write Tracker Occupancy event=0x55,umask=0x10 01 unc_m2m_wr_tracker_occupancy.mirr_pwr uncore interconnect Write Tracker Occupancy event=0x55,umask=0x20 01 unc_m2m_wr_tracker_posted_inserts.ch0 uncore interconnect Write Tracker Posted Inserts : Channel 0 event=0x5e,umask=1 01 unc_m2m_wr_tracker_posted_inserts.ch1 uncore interconnect Write Tracker Posted Inserts : Channel 1 event=0x5e,umask=2 01 unc_m2m_wr_tracker_posted_inserts.ch2 uncore interconnect Write Tracker Posted Inserts : Channel 2 event=0x5e,umask=4 01 unc_m2m_wr_tracker_posted_occupancy.ch0 uncore interconnect Write Tracker Posted Occupancy : Channel 0 event=0x5d,umask=1 01 unc_m2m_wr_tracker_posted_occupancy.ch1 uncore interconnect Write Tracker Posted Occupancy : Channel 1 event=0x5d,umask=2 01 unc_m2m_wr_tracker_posted_occupancy.ch2 uncore interconnect Write Tracker Posted Occupancy : Channel 2 event=0x5d,umask=4 01 unc_m3upi_ag0_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=1 01 CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=2 01 CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=4 01 CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=8 01 CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10 01 CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20 01 CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40 01 CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80 01 CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=4 01 CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=1 01 CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=2 01 CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=1 01 CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=2 01 CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=4 01 CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=8 01 CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10 01 CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20 01 CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40 01 CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80 01 CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=4 01 CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=1 01 CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=2 01 CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=1 01 CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=2 01 CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=4 01 CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=8 01 CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10 01 CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20 01 CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40 01 CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80 01 CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=4 01 CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=1 01 CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=2 01 CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=1 01 CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=2 01 CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=4 01 CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=8 01 CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10 01 CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20 01 CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40 01 CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80 01 CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=4 01 CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=1 01 CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=2 01 CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=1 01 CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=2 01 CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=4 01 CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=8 01 CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10 01 CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20 01 CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40 01 CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80 01 CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=4 01 CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=1 01 CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=2 01 CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=1 01 CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=2 01 CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=4 01 CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=8 01 CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10 01 CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20 01 CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40 01 CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80 01 CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=4 01 CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=1 01 CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=2 01 CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=1 01 CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=2 01 CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=4 01 CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=8 01 CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=4 01 CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=1 01 CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=2 01 CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=1 01 CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=2 01 CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=4 01 CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=8 01 CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10 01 CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20 01 CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40 01 CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80 01 CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=4 01 CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=1 01 CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=2 01 CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_clockticks uncore interconnect Clockticks of the mesh to UPI (M3UPI) event=1 01 Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_m3upi_distress_asserted.dpt_local uncore interconnect Distress signal asserted : DPT Local event=0xaf,umask=4 01 Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_m3upi_distress_asserted.dpt_nonlocal uncore interconnect Distress signal asserted : DPT Remote event=0xaf,umask=8 01 Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_m3upi_distress_asserted.dpt_stall_iv uncore interconnect Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40 01 Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_m3upi_distress_asserted.dpt_stall_nocrd uncore interconnect Distress signal asserted : DPT Stalled - No Credit event=0xaf,umask=0x80 01 Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_m3upi_distress_asserted.horz uncore interconnect Distress signal asserted : Horizontal event=0xaf,umask=2 01 Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_m3upi_distress_asserted.pmm_local uncore interconnect Distress signal asserted : PMM Local event=0xaf,umask=0x10 01 Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m3upi_distress_asserted.pmm_nonlocal uncore interconnect Distress signal asserted : PMM Remote event=0xaf,umask=0x20 01 Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m3upi_distress_asserted.vert uncore interconnect Distress signal asserted : Vertical event=0xaf,umask=1 01 Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_m3upi_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use : Left and Even event=0xb6,umask=1 01 Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=2 01 Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use : Right and Even event=0xb6,umask=4 01 Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=8 01 Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xbb,umask=1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xbb,umask=4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xb7,umask=1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xb7,umask=4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use : Left and Even event=0xb8,umask=1 01 Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=2 01 Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use : Right and Even event=0xb8,umask=4 01 Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=8 01 Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use : Left event=0xb9,umask=1 01 Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use : Right event=0xb9,umask=4 01 Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_misc_external.mbe_inst0 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=1 01 unc_m3upi_misc_external.mbe_inst1 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=2 01 unc_m3upi_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=1 01 Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=2 01 Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=4 01 Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=8 01 Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=1 01 Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=2 01 Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.akc uncore interconnect Messages that bounced on the Vertical Ring event=0xaa,umask=0x10 01 Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=4 01 Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=8 01 Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring : AD event=0xad,umask=1 01 unc_m3upi_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring : AK event=0xad,umask=2 01 unc_m3upi_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20 01 unc_m3upi_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring : BL event=0xad,umask=4 01 unc_m3upi_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring : IV event=0xad,umask=8 01 unc_m3upi_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring : AD event=0xab,umask=1 01 unc_m3upi_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=2 01 unc_m3upi_ring_sink_starved_vert.akc uncore interconnect Sink Starvation on Vertical Ring event=0xab,umask=0x10 01 unc_m3upi_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=4 01 unc_m3upi_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=8 01 unc_m3upi_ring_src_thrtl uncore interconnect Source Throttle event=0xae 01 unc_m3upi_rxc_cycles_ne_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD event=0x44,umask=1 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD event=0x44,umask=4 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD event=0x44,umask=2 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL event=0x44,umask=0x20 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL event=0x44,umask=0x40 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL event=0x44,umask=8 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL event=0x44,umask=0x10 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_inserts_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : REQ on AD event=0x41,umask=1 01 VN0 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : RSP on AD event=0x41,umask=4 01 VN0 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : SNP on AD event=0x41,umask=2 01 VN0 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : NCB on BL event=0x41,umask=0x20 01 VN0 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : NCS on BL event=0x41,umask=0x40 01 VN0 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : RSP on BL event=0x41,umask=8 01 VN0 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : WB on BL event=0x41,umask=0x10 01 VN0 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_inserts_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : REQ on AD event=0x42,umask=1 01 VN1 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : RSP on AD event=0x42,umask=4 01 VN1 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : SNP on AD event=0x42,umask=2 01 VN1 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : NCB on BL event=0x42,umask=0x20 01 VN1 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : NCS on BL event=0x42,umask=0x40 01 VN1 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : RSP on BL event=0x42,umask=8 01 VN1 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : WB on BL event=0x42,umask=0x10 01 VN1 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD event=0x45,umask=1 01 VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD event=0x45,umask=4 01 VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD event=0x45,umask=2 01 VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL event=0x45,umask=0x20 01 VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL event=0x45,umask=0x40 01 VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL event=0x45,umask=8 01 VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : WB on BL event=0x45,umask=0x10 01 VN0 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD event=0x46,umask=1 01 VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD event=0x46,umask=4 01 VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD event=0x46,umask=2 01 VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL event=0x46,umask=0x20 01 VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL event=0x46,umask=0x40 01 VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL event=0x46,umask=8 01 VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : WB on BL event=0x46,umask=0x10 01 VN1 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxr_busy_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe5,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m3upi_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe5,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m3upi_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_bypass.ad_all uncore interconnect Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11 01 Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m3upi_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10 01 Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ad_uncrd uncore interconnect Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=1 01 Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ak uncore interconnect Transgress Ingress Bypass : AK event=0xe2,umask=2 01 Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.akc_uncrd uncore interconnect Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80 01 Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_all uncore interconnect Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44 01 Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m3upi_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40 01 Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_uncrd uncore interconnect Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=4 01 Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.iv uncore interconnect Transgress Ingress Bypass : IV event=0xe2,umask=8 01 Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_crd_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe3,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m3upi_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ak uncore interconnect Transgress Injection Starvation : AK event=0xe3,umask=2 01 Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe3,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m3upi_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80 01 Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.iv uncore interconnect Transgress Injection Starvation : IV event=0xe3,umask=8 01 Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved_1 uncore interconnect Transgress Injection Starvation event=0xe4 01 Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_inserts.ad_all uncore interconnect Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11 01 Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10 01 Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ad_uncrd uncore interconnect Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=1 01 Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ak uncore interconnect Transgress Ingress Allocations : AK event=0xe1,umask=2 01 Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.akc_uncrd uncore interconnect Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80 01 Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_all uncore interconnect Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44 01 Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40 01 Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_uncrd uncore interconnect Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=4 01 Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.iv uncore interconnect Transgress Ingress Allocations : IV event=0xe1,umask=8 01 Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_all uncore interconnect Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11 01 Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10 01 Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_uncrd uncore interconnect Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=1 01 Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ak uncore interconnect Transgress Ingress Occupancy : AK event=0xe0,umask=2 01 Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.akc_uncrd uncore interconnect Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80 01 Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_all uncore interconnect Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44 01 Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20 01 Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_uncrd uncore interconnect Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=4 01 Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.iv uncore interconnect Transgress Ingress Occupancy : IV event=0xe0,umask=8 01 Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=8 01 Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10 01 Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20 01 Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40 01 Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80 01 Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=8 01 Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10 01 Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20 01 Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40 01 Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80 01 Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=8 01 Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10 01 Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20 01 Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40 01 Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80 01 Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=8 01 Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10 01 Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20 01 Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40 01 Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80 01 Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_txr_horz_ads_used.ad_all uncore interconnect CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11 01 CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10 01 CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.ad_uncrd uncore interconnect CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=1 01 CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_all uncore interconnect CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44 01 CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40 01 CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_uncrd uncore interconnect CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=4 01 CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_all uncore interconnect CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11 01 CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10 01 CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_uncrd uncore interconnect CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=1 01 CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ak uncore interconnect CMS Horizontal Bypass Used : AK event=0xa7,umask=2 01 CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.akc_uncrd uncore interconnect CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80 01 CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_all uncore interconnect CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44 01 CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40 01 CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_uncrd uncore interconnect CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=4 01 CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.iv uncore interconnect CMS Horizontal Bypass Used : IV event=0xa7,umask=8 01 CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_cycles_full.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=1 01 Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=2 01 Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=4 01 Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=8 01 Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=1 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=2 01 Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=4 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=8 01 Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_all uncore interconnect CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11 01 CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10 01 CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_uncrd uncore interconnect CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=1 01 CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ak uncore interconnect CMS Horizontal Egress Inserts : AK event=0xa1,umask=2 01 CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.akc_uncrd uncore interconnect CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80 01 CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_all uncore interconnect CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44 01 CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40 01 CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_uncrd uncore interconnect CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=4 01 CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.iv uncore interconnect CMS Horizontal Egress Inserts : IV event=0xa1,umask=8 01 CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_nack.ad_all uncore interconnect CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11 01 CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m3upi_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10 01 CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ad_uncrd uncore interconnect CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=1 01 CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ak uncore interconnect CMS Horizontal Egress NACKs : AK event=0xa4,umask=2 01 CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.akc_uncrd uncore interconnect CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80 01 CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_all uncore interconnect CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44 01 CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m3upi_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40 01 CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_uncrd uncore interconnect CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=4 01 CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.iv uncore interconnect CMS Horizontal Egress NACKs : IV event=0xa4,umask=8 01 CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_occupancy.ad_all uncore interconnect CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11 01 CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10 01 CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ad_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=1 01 CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ak uncore interconnect CMS Horizontal Egress Occupancy : AK event=0xa0,umask=2 01 CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.akc_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80 01 CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_all uncore interconnect CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44 01 CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40 01 CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_uncrd uncore interconnect CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=4 01 CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.iv uncore interconnect CMS Horizontal Egress Occupancy : IV event=0xa0,umask=8 01 CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_starved.ad_all uncore interconnect CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=1 01 CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m3upi_txr_horz_starved.ad_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=1 01 CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.ak uncore interconnect CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=2 01 CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.akc_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80 01 CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.bl_all uncore interconnect CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=4 01 CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m3upi_txr_horz_starved.bl_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=4 01 CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.iv uncore interconnect CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=8 01 CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=2 01 CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20 01 CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.iv_ag1 uncore interconnect CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=8 01 CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass_1.akc_ag0 uncore interconnect CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=1 01 CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass_1.akc_ag1 uncore interconnect CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=2 01 CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_cycles_full0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=1 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_full0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_full0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=2 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_full0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_full0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=4 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_full0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_full0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=8 01 Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_cycles_full1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=1 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_full1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=2 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_ne0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_ne0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_ne0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_ne0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_ne0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=4 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_ne0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_ne0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=8 01 Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_cycles_ne1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_ne1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_inserts0.ad_ag0 uncore interconnect CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=1 01 CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_inserts0.ad_ag1 uncore interconnect CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10 01 CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_inserts0.ak_ag0 uncore interconnect CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=2 01 CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_inserts0.ak_ag1 uncore interconnect CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20 01 CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_inserts0.bl_ag0 uncore interconnect CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=4 01 CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_inserts0.bl_ag1 uncore interconnect CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40 01 CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_inserts0.iv_ag0 uncore interconnect CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=8 01 CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_inserts1.akc_ag0 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=1 01 CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_inserts1.akc_ag1 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=2 01 CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_nack0.ad_ag0 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=1 01 CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.ad_ag1 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10 01 CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.ak_ag0 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=2 01 CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.ak_ag1 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20 01 CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.bl_ag0 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=4 01 CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.bl_ag1 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40 01 CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.iv_ag0 uncore interconnect CMS Vertical Egress NACKs : IV event=0x98,umask=8 01 CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack1.akc_ag0 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=1 01 CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack1.akc_ag1 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=2 01 CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_occupancy0.ad_ag0 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=1 01 CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_occupancy0.ad_ag1 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10 01 CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_occupancy0.ak_ag0 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=2 01 CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_occupancy0.ak_ag1 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20 01 CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_occupancy0.bl_ag0 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=4 01 CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_occupancy0.bl_ag1 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40 01 CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_occupancy0.iv_ag0 uncore interconnect CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=8 01 CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_occupancy1.akc_ag0 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=1 01 CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_occupancy1.akc_ag1 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=2 01 CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_starved0.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=1 01 CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10 01 CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=2 01 CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20 01 CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=4 01 CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40 01 CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.iv_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=8 01 CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved1.akc_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=1 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved1.akc_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=2 01 CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved1.tgc uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=4 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use : Down and Even event=0xb0,umask=4 01 Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use : Down and Odd event=0xb0,umask=8 01 Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use : Up and Even event=0xb0,umask=1 01 Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use : Up and Odd event=0xb0,umask=2 01 Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.dn_even uncore interconnect Vertical AKC Ring In Use : Down and Even event=0xb4,umask=4 01 Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.dn_odd uncore interconnect Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=8 01 Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.up_even uncore interconnect Vertical AKC Ring In Use : Up and Even event=0xb4,umask=1 01 Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.up_odd uncore interconnect Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=2 01 Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use : Down and Even event=0xb1,umask=4 01 Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use : Down and Odd event=0xb1,umask=8 01 Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use : Up and Even event=0xb1,umask=1 01 Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use : Up and Odd event=0xb1,umask=2 01 Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use : Down and Even event=0xb2,umask=4 01 Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use : Down and Odd event=0xb2,umask=8 01 Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use : Up and Even event=0xb2,umask=1 01 Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use : Up and Odd event=0xb2,umask=2 01 Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use : Down event=0xb3,umask=4 01 Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use : Up event=0xb3,umask=1 01 Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vert_ring_tgc_in_use.dn_even uncore interconnect Vertical TGC Ring In Use : Down and Even event=0xb5,umask=4 01 Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_tgc_in_use.dn_odd uncore interconnect Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=8 01 Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_tgc_in_use.up_even uncore interconnect Vertical TGC Ring In Use : Up and Even event=0xb5,umask=1 01 Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_tgc_in_use.up_odd uncore interconnect Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=2 01 Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_xpt_pftch.lost_qfull uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_QFULL event=0x61,umask=0x20 01 : xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full unc_upi_clockticks uncore interconnect Number of kfclks event=1 01 Number of kfclks : Counts the number of clocks in the UPI LL. This clock runs at 1/8th the GT/s speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixed unc_upi_rxl_basic_hdr_match.req uncore interconnect Matches on Receive path of a UPI Port : Request event=5,umask=8 01 Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.req_opc uncore interconnect Matches on Receive path of a UPI Port : Request, Match Opcode event=5,umask=0x108 01 Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rspcnflt uncore interconnect Matches on Receive path of a UPI Port : Response - Conflict event=5,umask=0x1aa 01 Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rspi uncore interconnect Matches on Receive path of a UPI Port : Response - Invalid event=5,umask=0x12a 01 Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_data uncore interconnect Matches on Receive path of a UPI Port : Response - Data event=5,umask=0xc 01 Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Receive path of a UPI Port : Response - Data, Match Opcode event=5,umask=0x10c 01 Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Receive path of a UPI Port : Response - No Data event=5,umask=0xa 01 Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Receive path of a UPI Port : Response - No Data, Match Opcode event=5,umask=0x10a 01 Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.snp uncore interconnect Matches on Receive path of a UPI Port : Snoop event=5,umask=9 01 Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.snp_opc uncore interconnect Matches on Receive path of a UPI Port : Snoop, Match Opcode event=5,umask=0x109 01 Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.wb uncore interconnect Matches on Receive path of a UPI Port : Writeback event=5,umask=0xd 01 Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.wb_opc uncore interconnect Matches on Receive path of a UPI Port : Writeback, Match Opcode event=5,umask=0x10d 01 Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_crc_llr_req_transmit uncore interconnect LLR Requests Sent event=8 01 LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs unc_upi_rxl_credits_consumed_vna uncore interconnect VNA Credit Consumed event=0x38 01 VNA Credit Consumed : Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_flits.all_null uncore interconnect Valid Flits Received : Null FLITs received from any slot event=3,umask=0x27 01 Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received : Null FLITs received from any slot event=3,umask=0x47 01 Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_basic_hdr_match.req uncore interconnect Matches on Transmit path of a UPI Port : Request event=4,umask=8 01 Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.req_opc uncore interconnect Matches on Transmit path of a UPI Port : Request, Match Opcode event=4,umask=0x108 01 Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rspcnflt uncore interconnect Matches on Transmit path of a UPI Port : Response - Conflict event=4,umask=0x1aa 01 Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rspi uncore interconnect Matches on Transmit path of a UPI Port : Response - Invalid event=4,umask=0x12a 01 Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_data uncore interconnect Matches on Transmit path of a UPI Port : Response - Data event=4,umask=0xc 01 Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Transmit path of a UPI Port : Response - Data, Match Opcode event=4,umask=0x10c 01 Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Transmit path of a UPI Port : Response - No Data event=4,umask=0xa 01 Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode event=4,umask=0x10a 01 Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.snp uncore interconnect Matches on Transmit path of a UPI Port : Snoop event=4,umask=9 01 Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.snp_opc uncore interconnect Matches on Transmit path of a UPI Port : Snoop, Match Opcode event=4,umask=0x109 01 Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.wb uncore interconnect Matches on Transmit path of a UPI Port : Writeback event=4,umask=0xd 01 Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.wb_opc uncore interconnect Matches on Transmit path of a UPI Port : Writeback, Match Opcode event=4,umask=0x10d 01 Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_flits.all_data uncore interconnect Valid Flits Sent : All Data event=2,umask=0xf 01 Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.all_null uncore interconnect Valid Flits Sent : Null FLITs transmitted to any slot event=2,umask=0x27 01 Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c) unc_u_lock_cycles uncore interconnect IDI Lock/SplitLock Cycles event=0x44 01 IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started unc_iio_clockticks uncore io Clockticks of the integrated IO (IIO) traffic controller event=1 01 Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz) unc_iio_clockticks_freerun uncore io Free running counter that increments for IIO clocktick event=0xff,umask=0x10 01 Free running counter that increments for integrated IO (IIO) traffic controller clockticks unc_iio_comp_buf_inserts.cmpd.all uncore io PCIe Completion Buffer Inserts : All Ports event=0xc2,ch_mask=0xff,fc_mask=4,umask=3 01 unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIe Completion Buffer Inserts of completions with data: Part 0-7 event=0xc2,ch_mask=0xff,fc_mask=4,umask=3 01 PCIe Completion Buffer Inserts of completions with data : Part 0-7 unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIe Completion Buffer Inserts of completions with data: Part 0 event=0xc2,ch_mask=1,fc_mask=4,umask=3 01 PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIe Completion Buffer Inserts of completions with data: Part 1 event=0xc2,ch_mask=2,fc_mask=4,umask=3 01 PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIe Completion Buffer Inserts of completions with data: Part 2 event=0xc2,ch_mask=4,fc_mask=4,umask=3 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIe Completion Buffer Inserts of completions with data: Part 3 event=0xc2,ch_mask=8,fc_mask=4,umask=3 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 unc_iio_comp_buf_inserts.cmpd.part4 uncore io PCIe Completion Buffer Inserts of completions with data: Part 4 event=0xc2,ch_mask=0x10,fc_mask=4,umask=3 01 PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 unc_iio_comp_buf_inserts.cmpd.part5 uncore io PCIe Completion Buffer Inserts of completions with data: Part 5 event=0xc2,ch_mask=0x20,fc_mask=4,umask=3 01 PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 unc_iio_comp_buf_inserts.cmpd.part6 uncore io PCIe Completion Buffer Inserts of completions with data: Part 6 event=0xc2,ch_mask=0x40,fc_mask=4,umask=3 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 unc_iio_comp_buf_inserts.cmpd.part7 uncore io PCIe Completion Buffer Inserts of completions with data: Part 7 event=0xc2,ch_mask=0x80,fc_mask=4,umask=3 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 unc_iio_comp_buf_occupancy.cmpd.all uncore io PCIe Completion Buffer Occupancy of completions with data : Part 0-7 event=0xd5,fc_mask=4,umask=0xff 01 PCIe Completion Buffer Occupancy : Part 0-7 unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io PCIe Completion Buffer Occupancy of completions with data : Part 0-7 event=0xd5,fc_mask=4,umask=0xff 01 PCIe Completion Buffer Occupancy : Part 0-7 unc_iio_comp_buf_occupancy.cmpd.part0 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 0 event=0xd5,fc_mask=4,umask=1 01 PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_occupancy.cmpd.part1 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 1 event=0xd5,fc_mask=4,umask=2 01 PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part2 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 2 event=0xd5,fc_mask=4,umask=4 01 PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 unc_iio_comp_buf_occupancy.cmpd.part3 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 3 event=0xd5,fc_mask=4,umask=8 01 PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 unc_iio_comp_buf_occupancy.cmpd.part4 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 4 event=0xd5,fc_mask=4,umask=0x10 01 PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 unc_iio_comp_buf_occupancy.cmpd.part5 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 5 event=0xd5,fc_mask=4,umask=0x20 01 PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 unc_iio_comp_buf_occupancy.cmpd.part6 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 6 event=0xd5,fc_mask=4,umask=0x40 01 PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 unc_iio_comp_buf_occupancy.cmpd.part7 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 7 event=0xd5,fc_mask=4,umask=0x80 01 PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.cfg_read.iommu0 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x100,fc_mask=7,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.cfg_read.iommu1 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x200,fc_mask=7,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.cfg_read.part0 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=1,fc_mask=7,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_read.part1 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=2,fc_mask=7,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_read.part2 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=4,fc_mask=7,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_read.part3 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=8,fc_mask=7,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_read.part4 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.cfg_read.part5 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.cfg_read.part6 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.cfg_read.part7 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.cfg_write.iommu0 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x100,fc_mask=7,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.cfg_write.iommu1 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x200,fc_mask=7,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.cfg_write.part0 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=1,fc_mask=7,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_write.part1 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=2,fc_mask=7,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_write.part2 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=4,fc_mask=7,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_write.part3 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=8,fc_mask=7,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_write.part4 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.cfg_write.part5 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.cfg_write.part6 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.cfg_write.part7 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.io_read.iommu0 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x100,fc_mask=7,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.io_read.iommu1 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x200,fc_mask=7,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.io_read.part0 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=1,fc_mask=7,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_read.part1 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=2,fc_mask=7,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_read.part2 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=4,fc_mask=7,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_read.part3 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=8,fc_mask=7,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_read.part4 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.io_read.part5 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.io_read.part6 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.io_read.part7 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.io_write.iommu0 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x100,fc_mask=7,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.io_write.iommu1 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x200,fc_mask=7,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.io_write.part0 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=1,fc_mask=7,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_write.part1 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=2,fc_mask=7,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_write.part2 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=4,fc_mask=7,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_write.part3 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=8,fc_mask=7,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_write.part4 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.io_write.part5 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.io_write.part6 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.io_write.part7 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.mem_read.iommu0 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x100,fc_mask=7,umask=4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.mem_read.iommu1 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x200,fc_mask=7,umask=4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.mem_read.part0 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=1,fc_mask=7,umask=4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_read.part1 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=2,fc_mask=7,umask=4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part2 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=4,fc_mask=7,umask=4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.mem_read.part3 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=8,fc_mask=7,umask=4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_read.part4 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x10,fc_mask=7,umask=4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.mem_read.part5 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x20,fc_mask=7,umask=4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.mem_read.part6 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x40,fc_mask=7,umask=4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.mem_read.part7 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x80,fc_mask=7,umask=4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.mem_write.iommu0 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x100,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.mem_write.iommu1 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x200,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.mem_write.part0 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=1,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_write.part1 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=2,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part2 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=4,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.mem_write.part3 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=8,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_write.part4 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.mem_write.part5 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.mem_write.part6 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.mem_write.part7 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.peer_read.iommu0 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x100,fc_mask=7,umask=8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.peer_read.iommu1 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x200,fc_mask=7,umask=8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.peer_read.part0 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=1,fc_mask=7,umask=8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_read.part1 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=2,fc_mask=7,umask=8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part2 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=4,fc_mask=7,umask=8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.peer_read.part3 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=8,fc_mask=7,umask=8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_read.part4 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.peer_read.part5 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.peer_read.part6 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x40,fc_mask=7,umask=8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.peer_read.part7 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x80,fc_mask=7,umask=8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.peer_write.iommu0 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x100,fc_mask=7,umask=2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.peer_write.iommu1 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x200,fc_mask=7,umask=2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.peer_write.part0 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=1,fc_mask=7,umask=2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_write.part1 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=2,fc_mask=7,umask=2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part2 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=4,fc_mask=7,umask=2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.peer_write.part3 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=8,fc_mask=7,umask=2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_write.part4 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.peer_write.part5 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.peer_write.part6 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x40,fc_mask=7,umask=2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.peer_write.part7 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x80,fc_mask=7,umask=2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.atomic.iommu0 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x100,fc_mask=7,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.atomic.iommu1 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x200,fc_mask=7,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.atomic.part0 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=1,fc_mask=7,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.atomic.part1 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=2,fc_mask=7,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.atomic.part2 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=4,fc_mask=7,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.atomic.part3 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=8,fc_mask=7,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.atomic.part4 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.atomic.part5 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.atomic.part6 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.atomic.part7 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.cmpd.iommu0 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x100,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.cmpd.iommu1 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x200,fc_mask=7,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.mem_read.iommu0 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x100,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.mem_read.iommu1 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x200,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.mem_read.part0 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=1,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part1 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=2,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part2 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=4,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_read.part3 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=8,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_read.part4 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.mem_read.part5 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.mem_read.part6 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.mem_read.part7 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.mem_write.iommu0 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x100,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.mem_write.iommu1 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x200,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.mem_write.part0 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=1,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part1 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=2,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part2 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=4,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_write.part3 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=8,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.part4 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.mem_write.part5 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.mem_write.part6 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.mem_write.part7 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.msg.iommu0 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x100,fc_mask=7,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.msg.iommu1 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x200,fc_mask=7,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.msg.part0 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=1,fc_mask=7,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.msg.part1 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=2,fc_mask=7,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.msg.part2 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=4,fc_mask=7,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.msg.part3 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=8,fc_mask=7,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.msg.part4 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x10,fc_mask=7,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.msg.part5 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x20,fc_mask=7,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.msg.part6 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x40,fc_mask=7,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.msg.part7 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x80,fc_mask=7,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.peer_read.iommu0 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x100,fc_mask=7,umask=8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.peer_read.iommu1 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x200,fc_mask=7,umask=8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.peer_read.part0 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=1,fc_mask=7,umask=8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_read.part1 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=2,fc_mask=7,umask=8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_read.part2 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=4,fc_mask=7,umask=8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.peer_read.part3 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=8,fc_mask=7,umask=8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_read.part4 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.peer_read.part5 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.peer_read.part6 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=7,umask=8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.peer_read.part7 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=7,umask=8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.peer_write.iommu0 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x100,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.peer_write.iommu1 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x200,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.peer_write.part0 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=1,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_write.part1 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=2,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part2 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=4,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.peer_write.part3 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=8,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_write.part4 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.peer_write.part5 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.peer_write.part6 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.peer_write.part7 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=7,umask=2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_inbound_arb_req.data uncore io Incoming arbitration requests : Passing data to be written event=0x86,ch_mask=0xff,fc_mask=7,umask=0x20 01 Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_req.req_own uncore io Incoming arbitration requests : Request Ownership event=0x86,ch_mask=0xff,fc_mask=7,umask=4 01 Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_req.wr uncore io Incoming arbitration requests : Writing line event=0x86,ch_mask=0xff,fc_mask=7,umask=0x10 01 Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.data uncore io Incoming arbitration requests granted : Passing data to be written event=0x87,ch_mask=0xff,fc_mask=7,umask=0x20 01 Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.final_rd_wr uncore io Incoming arbitration requests granted : Issuing final read or write of line event=0x87,ch_mask=0xff,fc_mask=7,umask=8 01 Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.iommu_hit uncore io Incoming arbitration requests granted : Processing response from IOMMU event=0x87,ch_mask=0xff,fc_mask=7,umask=2 01 Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.iommu_req uncore io Incoming arbitration requests granted : Issuing to IOMMU event=0x87,ch_mask=0xff,fc_mask=7,umask=1 01 Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.req_own uncore io Incoming arbitration requests granted : Request Ownership event=0x87,ch_mask=0xff,fc_mask=7,umask=4 01 Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.wr uncore io Incoming arbitration requests granted : Writing line event=0x87,ch_mask=0xff,fc_mask=7,umask=0x10 01 Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_iommu0.all_lookups uncore io : IOTLB lookups all event=0x40,umask=2 01 : IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB unc_iio_iommu0.misses uncore io : IOTLB Fills (same as IOTLB miss) event=0x40,umask=0x20 01 : IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB unc_iio_iommu1.cyc_pwt_full uncore io : Cycles PWT full event=0x41,umask=0x80 01 : Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks unc_iio_iommu1.num_mem_accesses uncore io : IOMMU memory access event=0x41,umask=0x40 01 : IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel unc_iio_iommu1.pwc_1g_hits uncore io : PWC Hit to a 1G page event=0x41,umask=8 01 : PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level unc_iio_iommu1.pwc_2m_hits uncore io : PWC Hit to a 2M page event=0x41,umask=4 01 : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.pwc_4k_hits uncore io : PWC Hit to a 4K page event=0x41,umask=2 01 : PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level unc_iio_iommu1.pwc_512g_hits uncore io : PWT Hit to a 256T page event=0x41,umask=0x10 01 : PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level unc_iio_iommu3.int_cache_hits uncore io : Interrupt Entry cache hit event=0x43,umask=0x80 01 : Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC unc_iio_iommu3.int_cache_lookups uncore io : Interrupt Entry cache lookup event=0x43,umask=0x40 01 : Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache unc_iio_iommu3.num_ctxt_cache_inval_device uncore io : Device-selective Context cache invalidation cycles event=0x43,umask=0x20 01 : Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events unc_iio_iommu3.num_ctxt_cache_inval_domain uncore io : Domain-selective Context cache invalidation cycles event=0x43,umask=0x10 01 : Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events unc_iio_iommu3.num_ctxt_cache_inval_gbl uncore io : Context cache global invalidation cycles event=0x43,umask=8 01 : Context cache global invalidation cycles : Counts number of Context Cache global invalidation events unc_iio_iommu3.num_inval_domain uncore io : Domain-selective IOTLB invalidation cycles event=0x43,umask=2 01 : Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events unc_iio_iommu3.num_inval_gbl uncore io : Global IOTLB invalidation cycles event=0x43,umask=1 01 : Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation unc_iio_iommu3.num_inval_page uncore io : Page-selective IOTLB invalidation cycles event=0x43,umask=4 01 : Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events unc_iio_nothing uncore io Counting disabled event=0x80 01 unc_iio_num_oustanding_req_from_cpu.to_io uncore io Occupancy of outbound request queue : To device event=0xc5,ch_mask=0xff,fc_mask=7,umask=8 01 Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing unc_iio_num_outstanding_req_of_cpu.data uncore io : Passing data to be written event=0x88,ch_mask=0xff,fc_mask=7,umask=0x20 01 : Passing data to be written : Only for posted requests unc_iio_num_outstanding_req_of_cpu.final_rd_wr uncore io : Issuing final read or write of line event=0x88,ch_mask=0xff,fc_mask=7,umask=8 01 unc_iio_num_outstanding_req_of_cpu.iommu_hit uncore io : Processing response from IOMMU event=0x88,ch_mask=0xff,fc_mask=7,umask=2 01 unc_iio_num_outstanding_req_of_cpu.iommu_req uncore io : Issuing to IOMMU event=0x88,ch_mask=0xff,fc_mask=7,umask=1 01 unc_iio_num_outstanding_req_of_cpu.req_own uncore io : Request Ownership event=0x88,ch_mask=0xff,fc_mask=7,umask=4 01 : Request Ownership : Only for posted requests unc_iio_num_outstanding_req_of_cpu.wr uncore io : Writing line event=0x88,ch_mask=0xff,fc_mask=7,umask=0x10 01 : Writing line : Only for posted requests unc_iio_num_req_from_cpu.itc uncore io Number requests sent to PCIe from main die : From ITC event=0xc2,ch_mask=0xff,fc_mask=7,umask=2 01 Number requests sent to PCIe from main die : From ITC : Confined P2P unc_iio_num_req_from_cpu.prealloc uncore io Number requests sent to PCIe from main die : Completion allocations event=0xc2,ch_mask=0xff,fc_mask=7,umask=4 01 unc_iio_num_req_of_cpu.all.drop uncore io Number requests PCIe makes of the main die : Drop request event=0x85,ch_mask=0xff,fc_mask=7,umask=2 01 Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped unc_iio_num_req_of_cpu.commit.all uncore io Number requests PCIe makes of the main die : All event=0x85,ch_mask=0xff,fc_mask=7,umask=1 01 Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU unc_iio_num_tgt_matched_req_of_cpu uncore io ITC address map 1 event=0x8f 01 unc_iio_pwt_occupancy uncore io PWT occupancy event=0x42 01 PWT occupancy : Indicates how many page walks are outstanding at any point in time unc_iio_req_from_pcie_cl_cmpl.data uncore io PCIe Request - cacheline complete : Passing data to be written event=0x91,ch_mask=0xff,fc_mask=7,umask=0x20 01 PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.final_rd_wr uncore io PCIe Request - cacheline complete : Issuing final read or write of line event=0x91,ch_mask=0xff,fc_mask=7,umask=8 01 PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line unc_iio_req_from_pcie_cl_cmpl.req_own uncore io PCIe Request - cacheline complete : Request Ownership event=0x91,ch_mask=0xff,fc_mask=7,umask=4 01 PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.wr uncore io PCIe Request - cacheline complete : Writing line event=0x91,ch_mask=0xff,fc_mask=7,umask=0x10 01 PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests unc_iio_req_from_pcie_cmpl.data uncore io PCIe Request complete : Passing data to be written event=0x92,ch_mask=0xff,fc_mask=7,umask=0x20 01 PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests unc_iio_req_from_pcie_cmpl.final_rd_wr uncore io PCIe Request complete : Issuing final read or write of line event=0x92,ch_mask=0xff,fc_mask=7,umask=8 01 PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cmpl.iommu_hit uncore io PCIe Request complete : Processing response from IOMMU event=0x92,ch_mask=0xff,fc_mask=7,umask=2 01 PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cmpl.iommu_req uncore io PCIe Request complete : Issuing to IOMMU event=0x92,ch_mask=0xff,fc_mask=7,umask=1 01 PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cmpl.req_own uncore io PCIe Request complete : Request Ownership event=0x92,ch_mask=0xff,fc_mask=7,umask=4 01 PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests unc_iio_req_from_pcie_cmpl.wr uncore io PCIe Request complete : Writing line event=0x92,ch_mask=0xff,fc_mask=7,umask=0x10 01 PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.data uncore io PCIe Request - pass complete : Passing data to be written event=0x90,ch_mask=0xff,fc_mask=7,umask=0x20 01 PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.req_own uncore io PCIe Request - pass complete : Request Ownership event=0x90,ch_mask=0xff,fc_mask=7,umask=4 01 PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.wr uncore io PCIe Request - pass complete : Writing line event=0x90,ch_mask=0xff,fc_mask=7,umask=0x10 01 PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_symbol_times uncore io Symbol Times on Link event=0x82 01 Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS unc_iio_txn_req_by_cpu.cfg_read.iommu0 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x100,fc_mask=7,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.cfg_read.iommu1 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x200,fc_mask=7,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.cfg_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=1,fc_mask=7,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=2,fc_mask=7,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=4,fc_mask=7,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=8,fc_mask=7,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.cfg_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.cfg_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.cfg_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.cfg_write.iommu0 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x100,fc_mask=7,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.cfg_write.iommu1 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x200,fc_mask=7,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.cfg_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=1,fc_mask=7,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=2,fc_mask=7,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=4,fc_mask=7,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=8,fc_mask=7,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.cfg_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.cfg_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.cfg_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.io_read.iommu0 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x100,fc_mask=7,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.io_read.iommu1 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x200,fc_mask=7,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.io_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=1,fc_mask=7,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=2,fc_mask=7,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=4,fc_mask=7,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=8,fc_mask=7,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.io_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.io_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.io_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.io_write.iommu0 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x100,fc_mask=7,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.io_write.iommu1 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x200,fc_mask=7,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.io_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=1,fc_mask=7,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=2,fc_mask=7,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=4,fc_mask=7,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=8,fc_mask=7,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.io_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.io_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.io_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.mem_read.iommu0 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x100,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.mem_read.iommu1 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x200,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=1,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=2,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=4,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=8,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.mem_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.mem_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.mem_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.mem_write.iommu0 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x100,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.mem_write.iommu1 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x200,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=1,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=2,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=4,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=8,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.mem_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.mem_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.mem_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.peer_read.iommu0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x100,fc_mask=7,umask=8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.peer_read.iommu1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x200,fc_mask=7,umask=8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.peer_read.part0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=1,fc_mask=7,umask=8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.peer_read.part1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=2,fc_mask=7,umask=8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.peer_read.part2 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=4,fc_mask=7,umask=8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.peer_read.part3 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=8,fc_mask=7,umask=8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_read.part4 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x10,fc_mask=7,umask=8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.peer_read.part5 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x20,fc_mask=7,umask=8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.peer_read.part6 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x40,fc_mask=7,umask=8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.peer_read.part7 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x80,fc_mask=7,umask=8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.peer_write.iommu0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x200,fc_mask=7,umask=2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.peer_write.part0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=1,fc_mask=7,umask=2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.peer_write.part1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=2,fc_mask=7,umask=2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.peer_write.part2 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=4,fc_mask=7,umask=2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.peer_write.part3 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=8,fc_mask=7,umask=2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_write.part4 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x10,fc_mask=7,umask=2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.peer_write.part5 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x20,fc_mask=7,umask=2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.peer_write.part6 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x40,fc_mask=7,umask=2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.peer_write.part7 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x80,fc_mask=7,umask=2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.atomic.iommu0 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x100,fc_mask=7,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.atomic.iommu1 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x200,fc_mask=7,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.atomic.part0 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=1,fc_mask=7,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.atomic.part1 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=2,fc_mask=7,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.atomic.part2 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=4,fc_mask=7,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.atomic.part3 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=8,fc_mask=7,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.atomic.part4 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.atomic.part5 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.atomic.part6 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.atomic.part7 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.cmpd.iommu0 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x100,fc_mask=7,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.cmpd.iommu1 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x200,fc_mask=7,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.mem_read.iommu0 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x100,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.mem_read.iommu1 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x200,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=1,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=2,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=4,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=8,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_read.part4 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.mem_read.part5 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.mem_read.part6 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.mem_read.part7 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.mem_write.iommu0 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x100,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.mem_write.iommu1 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x200,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=1,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=2,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=4,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=8,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_write.part4 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.mem_write.part5 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.mem_write.part6 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.mem_write.part7 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.msg.iommu0 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x100,fc_mask=7,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.msg.iommu1 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x200,fc_mask=7,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.msg.part0 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=1,fc_mask=7,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.msg.part1 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=2,fc_mask=7,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.msg.part2 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=4,fc_mask=7,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.msg.part3 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=8,fc_mask=7,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.msg.part4 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x10,fc_mask=7,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.msg.part5 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x20,fc_mask=7,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.msg.part6 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x40,fc_mask=7,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.msg.part7 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x80,fc_mask=7,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.peer_read.iommu0 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x100,fc_mask=7,umask=8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.peer_read.iommu1 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x200,fc_mask=7,umask=8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.peer_read.part0 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=1,fc_mask=7,umask=8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.peer_read.part1 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=2,fc_mask=7,umask=8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.peer_read.part2 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=4,fc_mask=7,umask=8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.peer_read.part3 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=8,fc_mask=7,umask=8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.peer_read.part4 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.peer_read.part5 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.peer_read.part6 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x40,fc_mask=7,umask=8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.peer_read.part7 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x80,fc_mask=7,umask=8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.peer_write.iommu0 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x100,fc_mask=7,umask=2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.peer_write.iommu1 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x200,fc_mask=7,umask=2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_m2p_ag0_ad_crd_acquired0.tgr0 uncore io CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=1 01 CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr1 uncore io CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=2 01 CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr2 uncore io CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=4 01 CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr3 uncore io CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=8 01 CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr4 uncore io CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10 01 CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr5 uncore io CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20 01 CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr6 uncore io CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40 01 CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr7 uncore io CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80 01 CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired1.tgr10 uncore io CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=4 01 CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired1.tgr8 uncore io CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=1 01 CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired1.tgr9 uncore io CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=2 01 CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr0 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=1 01 CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr1 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=2 01 CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr2 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=4 01 CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr3 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=8 01 CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr4 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10 01 CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr5 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20 01 CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr6 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40 01 CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr7 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80 01 CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy1.tgr10 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=4 01 CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy1.tgr8 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=1 01 CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy1.tgr9 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=2 01 CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr0 uncore io CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=1 01 CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr1 uncore io CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=2 01 CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr2 uncore io CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=4 01 CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr3 uncore io CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=8 01 CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr4 uncore io CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10 01 CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr5 uncore io CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20 01 CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr6 uncore io CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40 01 CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr7 uncore io CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80 01 CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired1.tgr10 uncore io CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=4 01 CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired1.tgr8 uncore io CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=1 01 CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired1.tgr9 uncore io CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=2 01 CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr0 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=1 01 CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr1 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=2 01 CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr2 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=4 01 CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr3 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=8 01 CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr4 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10 01 CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr5 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20 01 CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr6 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40 01 CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr7 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80 01 CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy1.tgr10 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=4 01 CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy1.tgr8 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=1 01 CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy1.tgr9 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=2 01 CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr0 uncore io CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=1 01 CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr1 uncore io CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=2 01 CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr2 uncore io CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=4 01 CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr3 uncore io CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=8 01 CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr4 uncore io CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10 01 CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr5 uncore io CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20 01 CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr6 uncore io CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40 01 CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr7 uncore io CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80 01 CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired1.tgr10 uncore io CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=4 01 CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired1.tgr8 uncore io CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=1 01 CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired1.tgr9 uncore io CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=2 01 CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr0 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=1 01 CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr1 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=2 01 CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr2 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=4 01 CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr3 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=8 01 CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr4 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10 01 CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr5 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20 01 CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr6 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40 01 CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr7 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80 01 CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy1.tgr10 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=4 01 CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy1.tgr8 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=1 01 CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy1.tgr9 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=2 01 CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr0 uncore io CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=1 01 CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr1 uncore io CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=2 01 CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr2 uncore io CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=4 01 CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr3 uncore io CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=8 01 CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr4 uncore io CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr5 uncore io CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr6 uncore io CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr7 uncore io CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired1.tgr10 uncore io CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=4 01 CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired1.tgr8 uncore io CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=1 01 CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired1.tgr9 uncore io CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=2 01 CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr0 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=1 01 CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr1 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=2 01 CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr2 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=4 01 CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr3 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=8 01 CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr4 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10 01 CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr5 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20 01 CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr6 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40 01 CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr7 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80 01 CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy1.tgr10 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=4 01 CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy1.tgr8 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=1 01 CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy1.tgr9 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=2 01 CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_clockticks uncore io Clockticks of the mesh to PCI (M2P) event=1 01 Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_m2p_distress_asserted.dpt_local uncore io Distress signal asserted : DPT Local event=0xaf,umask=4 01 Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_m2p_distress_asserted.dpt_nonlocal uncore io Distress signal asserted : DPT Remote event=0xaf,umask=8 01 Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_m2p_distress_asserted.dpt_stall_iv uncore io Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40 01 Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_m2p_distress_asserted.dpt_stall_nocrd uncore io Distress signal asserted : DPT Stalled - No Credit event=0xaf,umask=0x80 01 Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_m2p_distress_asserted.horz uncore io Distress signal asserted : Horizontal event=0xaf,umask=2 01 Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_m2p_distress_asserted.pmm_local uncore io Distress signal asserted : PMM Local event=0xaf,umask=0x10 01 Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2p_distress_asserted.pmm_nonlocal uncore io Distress signal asserted : PMM Remote event=0xaf,umask=0x20 01 Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2p_distress_asserted.vert uncore io Distress signal asserted : Vertical event=0xaf,umask=1 01 Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_m2p_horz_ring_ad_in_use.left_even uncore io Horizontal AD Ring In Use : Left and Even event=0xb6,umask=1 01 Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ad_in_use.left_odd uncore io Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=2 01 Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ad_in_use.right_even uncore io Horizontal AD Ring In Use : Right and Even event=0xb6,umask=4 01 Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ad_in_use.right_odd uncore io Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=8 01 Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.left_even uncore io Horizontal AK Ring In Use : Left and Even event=0xbb,umask=1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.left_odd uncore io Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.right_even uncore io Horizontal AK Ring In Use : Right and Even event=0xbb,umask=4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.right_odd uncore io Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.left_even uncore io Horizontal AK Ring In Use : Left and Even event=0xb7,umask=1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.left_odd uncore io Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.right_even uncore io Horizontal AK Ring In Use : Right and Even event=0xb7,umask=4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.right_odd uncore io Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.left_even uncore io Horizontal BL Ring in Use : Left and Even event=0xb8,umask=1 01 Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.left_odd uncore io Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=2 01 Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.right_even uncore io Horizontal BL Ring in Use : Right and Even event=0xb8,umask=4 01 Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.right_odd uncore io Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=8 01 Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_iv_in_use.left uncore io Horizontal IV Ring in Use : Left event=0xb9,umask=1 01 Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_horz_ring_iv_in_use.right uncore io Horizontal IV Ring in Use : Right event=0xb9,umask=4 01 Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB event=0x19,umask=0x10 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS event=0x19,umask=0x20 01 unc_m2p_misc_external.mbe_inst0 uncore io Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=1 01 unc_m2p_misc_external.mbe_inst1 uncore io Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=2 01 unc_m2p_ring_bounces_horz.ad uncore io Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=1 01 Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_horz.ak uncore io Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=2 01 Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_horz.bl uncore io Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=4 01 Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_horz.iv uncore io Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=8 01 Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_vert.ad uncore io Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=1 01 Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.ak uncore io Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=2 01 Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.akc uncore io Messages that bounced on the Vertical Ring event=0xaa,umask=0x10 01 Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.bl uncore io Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=4 01 Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.iv uncore io Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=8 01 Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_sink_starved_horz.ad uncore io Sink Starvation on Horizontal Ring : AD event=0xad,umask=1 01 unc_m2p_ring_sink_starved_horz.ak uncore io Sink Starvation on Horizontal Ring : AK event=0xad,umask=2 01 unc_m2p_ring_sink_starved_horz.ak_ag1 uncore io Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20 01 unc_m2p_ring_sink_starved_horz.bl uncore io Sink Starvation on Horizontal Ring : BL event=0xad,umask=4 01 unc_m2p_ring_sink_starved_horz.iv uncore io Sink Starvation on Horizontal Ring : IV event=0xad,umask=8 01 unc_m2p_ring_sink_starved_vert.ad uncore io Sink Starvation on Vertical Ring : AD event=0xab,umask=1 01 unc_m2p_ring_sink_starved_vert.ak uncore io Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=2 01 unc_m2p_ring_sink_starved_vert.akc uncore io Sink Starvation on Vertical Ring event=0xab,umask=0x10 01 unc_m2p_ring_sink_starved_vert.bl uncore io Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=4 01 unc_m2p_ring_sink_starved_vert.iv uncore io Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=8 01 unc_m2p_ring_src_thrtl uncore io Source Throttle event=0xae 01 unc_m2p_rxr_busy_starved.ad_all uncore io Transgress Injection Starvation : AD - All event=0xe5,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2p_rxr_busy_starved.ad_crd uncore io Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2p_rxr_busy_starved.ad_uncrd uncore io Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2p_rxr_busy_starved.bl_all uncore io Transgress Injection Starvation : BL - All event=0xe5,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2p_rxr_busy_starved.bl_crd uncore io Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2p_rxr_busy_starved.bl_uncrd uncore io Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2p_rxr_bypass.ad_all uncore io Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11 01 Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2p_rxr_bypass.ad_crd uncore io Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10 01 Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.ad_uncrd uncore io Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=1 01 Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.ak uncore io Transgress Ingress Bypass : AK event=0xe2,umask=2 01 Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.akc_uncrd uncore io Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80 01 Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.bl_all uncore io Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44 01 Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2p_rxr_bypass.bl_crd uncore io Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40 01 Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.bl_uncrd uncore io Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=4 01 Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.iv uncore io Transgress Ingress Bypass : IV event=0xe2,umask=8 01 Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_m2p_rxr_crd_starved.ad_all uncore io Transgress Injection Starvation : AD - All event=0xe3,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2p_rxr_crd_starved.ad_crd uncore io Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.ad_uncrd uncore io Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.ak uncore io Transgress Injection Starvation : AK event=0xe3,umask=2 01 Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.bl_all uncore io Transgress Injection Starvation : BL - All event=0xe3,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2p_rxr_crd_starved.bl_crd uncore io Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.bl_uncrd uncore io Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.ifv uncore io Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80 01 Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.iv uncore io Transgress Injection Starvation : IV event=0xe3,umask=8 01 Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved_1 uncore io Transgress Injection Starvation event=0xe4 01 Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_inserts.ad_all uncore io Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11 01 Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_inserts.ad_crd uncore io Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10 01 Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.ad_uncrd uncore io Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=1 01 Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.ak uncore io Transgress Ingress Allocations : AK event=0xe1,umask=2 01 Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.akc_uncrd uncore io Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80 01 Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.bl_all uncore io Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44 01 Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_inserts.bl_crd uncore io Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40 01 Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.bl_uncrd uncore io Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=4 01 Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.iv uncore io Transgress Ingress Allocations : IV event=0xe1,umask=8 01 Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.ad_all uncore io Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11 01 Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_occupancy.ad_crd uncore io Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10 01 Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.ad_uncrd uncore io Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=1 01 Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.ak uncore io Transgress Ingress Occupancy : AK event=0xe0,umask=2 01 Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.akc_uncrd uncore io Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80 01 Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.bl_all uncore io Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44 01 Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_occupancy.bl_crd uncore io Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20 01 Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.bl_uncrd uncore io Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=4 01 Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.iv uncore io Transgress Ingress Occupancy : IV event=0xe0,umask=8 01 Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=8 01 Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10 01 Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20 01 Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40 01 Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80 01 Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=8 01 Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10 01 Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20 01 Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40 01 Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80 01 Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=8 01 Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10 01 Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20 01 Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40 01 Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80 01 Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=8 01 Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10 01 Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20 01 Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40 01 Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80 01 Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_txc_cycles_full.ad_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=1 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.ad_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x10 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.ak_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=2 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.ak_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x20 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.bl_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=4 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.bl_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x40 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_ne.ad_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=1 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.ad_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x10 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.ak_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=2 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.ak_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x20 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.bl_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=4 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.bl_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x40 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_inserts.ad_0 uncore io Egress (to CMS) Ingress event=0x24,umask=1 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.ad_1 uncore io Egress (to CMS) Ingress event=0x24,umask=0x10 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.ak_crd_0 uncore io Egress (to CMS) Ingress event=0x24,umask=8 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.ak_crd_1 uncore io Egress (to CMS) Ingress event=0x24,umask=0x80 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.bl_0 uncore io Egress (to CMS) Ingress event=0x24,umask=4 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.bl_1 uncore io Egress (to CMS) Ingress event=0x24,umask=0x40 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txr_horz_ads_used.ad_all uncore io CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11 01 CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_ads_used.ad_crd uncore io CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10 01 CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_ads_used.ad_uncrd uncore io CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=1 01 CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_ads_used.bl_all uncore io CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44 01 CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_ads_used.bl_crd uncore io CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40 01 CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_ads_used.bl_uncrd uncore io CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=4 01 CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.ad_all uncore io CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11 01 CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_bypass.ad_crd uncore io CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10 01 CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.ad_uncrd uncore io CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=1 01 CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.ak uncore io CMS Horizontal Bypass Used : AK event=0xa7,umask=2 01 CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.akc_uncrd uncore io CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80 01 CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.bl_all uncore io CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44 01 CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_bypass.bl_crd uncore io CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40 01 CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.bl_uncrd uncore io CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=4 01 CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.iv uncore io CMS Horizontal Bypass Used : IV event=0xa7,umask=8 01 CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_cycles_full.ad_all uncore io Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_full.ad_crd uncore io Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.ad_uncrd uncore io Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=1 01 Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.ak uncore io Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=2 01 Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.akc_uncrd uncore io Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.bl_all uncore io Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_full.bl_crd uncore io Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.bl_uncrd uncore io Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=4 01 Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.iv uncore io Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=8 01 Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.ad_all uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_ne.ad_crd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.ad_uncrd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=1 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.ak uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=2 01 Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.akc_uncrd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.bl_all uncore io Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_ne.bl_crd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.bl_uncrd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=4 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.iv uncore io Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=8 01 Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.ad_all uncore io CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11 01 CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_inserts.ad_crd uncore io CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10 01 CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.ad_uncrd uncore io CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=1 01 CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.ak uncore io CMS Horizontal Egress Inserts : AK event=0xa1,umask=2 01 CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.akc_uncrd uncore io CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80 01 CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.bl_all uncore io CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44 01 CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_inserts.bl_crd uncore io CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40 01 CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.bl_uncrd uncore io CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=4 01 CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.iv uncore io CMS Horizontal Egress Inserts : IV event=0xa1,umask=8 01 CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_nack.ad_all uncore io CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11 01 CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2p_txr_horz_nack.ad_crd uncore io CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10 01 CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.ad_uncrd uncore io CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=1 01 CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.ak uncore io CMS Horizontal Egress NACKs : AK event=0xa4,umask=2 01 CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.akc_uncrd uncore io CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80 01 CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.bl_all uncore io CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44 01 CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2p_txr_horz_nack.bl_crd uncore io CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40 01 CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.bl_uncrd uncore io CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=4 01 CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.iv uncore io CMS Horizontal Egress NACKs : IV event=0xa4,umask=8 01 CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_occupancy.ad_all uncore io CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11 01 CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_occupancy.ad_crd uncore io CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10 01 CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.ad_uncrd uncore io CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=1 01 CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.ak uncore io CMS Horizontal Egress Occupancy : AK event=0xa0,umask=2 01 CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.akc_uncrd uncore io CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80 01 CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.bl_all uncore io CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44 01 CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_occupancy.bl_crd uncore io CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40 01 CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.bl_uncrd uncore io CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=4 01 CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.iv uncore io CMS Horizontal Egress Occupancy : IV event=0xa0,umask=8 01 CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_starved.ad_all uncore io CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=1 01 CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2p_txr_horz_starved.ad_uncrd uncore io CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=1 01 CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.ak uncore io CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=2 01 CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.akc_uncrd uncore io CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80 01 CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.bl_all uncore io CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=4 01 CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2p_txr_horz_starved.bl_uncrd uncore io CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=4 01 CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.iv uncore io CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=8 01 CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_vert_ads_used.ad_ag0 uncore io CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_ads_used.ad_ag1 uncore io CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_ads_used.bl_ag0 uncore io CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_ads_used.bl_ag1 uncore io CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ad_ag0 uncore io CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ad_ag1 uncore io CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ak_ag0 uncore io CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=2 01 CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ak_ag1 uncore io CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20 01 CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.bl_ag0 uncore io CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.bl_ag1 uncore io CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.iv_ag1 uncore io CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=8 01 CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass_1.akc_ag0 uncore io CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=1 01 CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass_1.akc_ag1 uncore io CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=2 01 CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_cycles_full0.ad_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=1 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_full0.ad_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2p_txr_vert_cycles_full0.ak_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=2 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_cycles_full0.ak_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_cycles_full0.bl_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=4 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_cycles_full0.bl_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_cycles_full0.iv_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=8 01 Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2p_txr_vert_cycles_full1.akc_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=1 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_full1.akc_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=2 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_cycles_ne0.ad_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_ne0.ad_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2p_txr_vert_cycles_ne0.ak_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_cycles_ne0.ak_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_cycles_ne0.bl_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=4 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_cycles_ne0.bl_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_cycles_ne0.iv_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=8 01 Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2p_txr_vert_cycles_ne1.akc_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_ne1.akc_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_inserts0.ad_ag0 uncore io CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=1 01 CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_inserts0.ad_ag1 uncore io CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10 01 CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2p_txr_vert_inserts0.ak_ag0 uncore io CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=2 01 CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_inserts0.ak_ag1 uncore io CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20 01 CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_inserts0.bl_ag0 uncore io CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=4 01 CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_inserts0.bl_ag1 uncore io CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40 01 CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_inserts0.iv_ag0 uncore io CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=8 01 CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2p_txr_vert_inserts1.akc_ag0 uncore io CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=1 01 CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_inserts1.akc_ag1 uncore io CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=2 01 CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_nack0.ad_ag0 uncore io CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=1 01 CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.ad_ag1 uncore io CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10 01 CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.ak_ag0 uncore io CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=2 01 CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.ak_ag1 uncore io CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20 01 CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.bl_ag0 uncore io CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=4 01 CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.bl_ag1 uncore io CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40 01 CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.iv_ag0 uncore io CMS Vertical Egress NACKs : IV event=0x98,umask=8 01 CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack1.akc_ag0 uncore io CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=1 01 CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack1.akc_ag1 uncore io CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=2 01 CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_occupancy0.ad_ag0 uncore io CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=1 01 CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_occupancy0.ad_ag1 uncore io CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10 01 CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2p_txr_vert_occupancy0.ak_ag0 uncore io CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=2 01 CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_occupancy0.ak_ag1 uncore io CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20 01 CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_occupancy0.bl_ag0 uncore io CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=4 01 CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_occupancy0.bl_ag1 uncore io CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40 01 CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_occupancy0.iv_ag0 uncore io CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=8 01 CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2p_txr_vert_occupancy1.akc_ag0 uncore io CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=1 01 CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_occupancy1.akc_ag1 uncore io CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=2 01 CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_starved0.ad_ag0 uncore io CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=1 01 CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.ad_ag1 uncore io CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10 01 CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.ak_ag0 uncore io CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=2 01 CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.ak_ag1 uncore io CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20 01 CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.bl_ag0 uncore io CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=4 01 CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.bl_ag1 uncore io CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40 01 CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.iv_ag0 uncore io CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=8 01 CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved1.akc_ag0 uncore io CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=1 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved1.akc_ag1 uncore io CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=2 01 CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved1.tgc uncore io CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=4 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_vert_ring_ad_in_use.dn_even uncore io Vertical AD Ring In Use : Down and Even event=0xb0,umask=4 01 Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ad_in_use.dn_odd uncore io Vertical AD Ring In Use : Down and Odd event=0xb0,umask=8 01 Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ad_in_use.up_even uncore io Vertical AD Ring In Use : Up and Even event=0xb0,umask=1 01 Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ad_in_use.up_odd uncore io Vertical AD Ring In Use : Up and Odd event=0xb0,umask=2 01 Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.dn_even uncore io Vertical AKC Ring In Use : Down and Even event=0xb4,umask=4 01 Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.dn_odd uncore io Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=8 01 Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.up_even uncore io Vertical AKC Ring In Use : Up and Even event=0xb4,umask=1 01 Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.up_odd uncore io Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=2 01 Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.dn_even uncore io Vertical AK Ring In Use : Down and Even event=0xb1,umask=4 01 Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.dn_odd uncore io Vertical AK Ring In Use : Down and Odd event=0xb1,umask=8 01 Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.up_even uncore io Vertical AK Ring In Use : Up and Even event=0xb1,umask=1 01 Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.up_odd uncore io Vertical AK Ring In Use : Up and Odd event=0xb1,umask=2 01 Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.dn_even uncore io Vertical BL Ring in Use : Down and Even event=0xb2,umask=4 01 Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.dn_odd uncore io Vertical BL Ring in Use : Down and Odd event=0xb2,umask=8 01 Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.up_even uncore io Vertical BL Ring in Use : Up and Even event=0xb2,umask=1 01 Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.up_odd uncore io Vertical BL Ring in Use : Up and Odd event=0xb2,umask=2 01 Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_iv_in_use.dn uncore io Vertical IV Ring in Use : Down event=0xb3,umask=4 01 Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_vert_ring_iv_in_use.up uncore io Vertical IV Ring in Use : Up event=0xb3,umask=1 01 Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_vert_ring_tgc_in_use.dn_even uncore io Vertical TGC Ring In Use : Down and Even event=0xb5,umask=4 01 Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_tgc_in_use.dn_odd uncore io Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=8 01 Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_tgc_in_use.up_even uncore io Vertical TGC Ring In Use : Up and Even event=0xb5,umask=1 01 Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_tgc_in_use.up_odd uncore io Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=2 01 Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m_act_count.all uncore memory DRAM Activate Count : All Activates event=1,umask=0xb 01 DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.byp uncore memory DRAM Activate Count : Activate due to Bypass event=1,umask=8 01 DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_cas_count.all uncore memory All DRAM CAS commands issued event=4,umask=0x3f 01 Counts the total number of DRAM CAS commands issued on this channel unc_m_cas_count.rd uncore memory All DRAM read CAS commands issued (including underfills) event=4,umask=0xf 01 Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills unc_m_cas_count.rd_pre_reg uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre event=4,umask=2 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with explicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_pre_underfill uncore memory DRAM RD_CAS and WR_CAS Commands event=4,umask=8 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd_reg uncore memory All DRAM read CAS commands issued (does not include underfills) event=4,umask=1 01 Counts the total number of DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_underfill uncore memory DRAM underfill read CAS commands issued event=4,umask=4 01 Counts the total of DRAM Read CAS commands issued due to an underfill unc_m_cas_count.wr uncore memory All DRAM write CAS commands issued event=4,umask=0x30 01 Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel unc_m_cas_count.wr_nonpre uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre event=4,umask=0x10 01 DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.wr_pre uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre event=4,umask=0x20 01 DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands unc_m_clockticks_freerun uncore memory Free running counter that increments for the Memory Controller event=0xff,umask=0x10 01 unc_m_dram_pre_all uncore memory DRAM Precharge All Commands event=0x44 01 DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent unc_m_dram_refresh.high uncore memory Number of DRAM Refreshes Issued event=0x45,umask=4 01 Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_dram_refresh.opportunistic uncore memory Number of DRAM Refreshes Issued event=0x45,umask=1 01 Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_dram_refresh.panic uncore memory Number of DRAM Refreshes Issued event=0x45,umask=2 01 Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_hclockticks uncore memory Half clockticks for IMC event=0xff 01 unc_m_parity_errors uncore memory UNC_M_PARITY_ERRORS event=0x2c 01 unc_m_pcls.rd uncore memory UNC_M_PCLS.RD event=0xa0,umask=1 01 unc_m_pcls.total uncore memory UNC_M_PCLS.TOTAL event=0xa0,umask=4 01 unc_m_pcls.wr uncore memory UNC_M_PCLS.WR event=0xa0,umask=2 01 unc_m_pmm_cmd1.all uncore memory PMM Commands : All event=0xea,umask=1 01 PMM Commands : All : Counts all commands issued to PMM unc_m_pmm_cmd1.misc uncore memory PMM Commands : Misc Commands (error, flow ACKs) event=0xea,umask=0x80 01 unc_m_pmm_cmd1.misc_gnt uncore memory PMM Commands : Misc GNTs event=0xea,umask=0x40 01 unc_m_pmm_cmd1.rd uncore memory PMM Commands : Reads - RPQ event=0xea,umask=2 01 PMM Commands : Reads - RPQ : Counts read requests issued to the PMM RPQ unc_m_pmm_cmd1.rpq_gnts uncore memory PMM Commands : RPQ GNTs event=0xea,umask=0x10 01 unc_m_pmm_cmd1.ufill_rd uncore memory PMM Commands : Underfill reads event=0xea,umask=8 01 PMM Commands : Underfill reads : Counts underfill read commands, due to a partial write, issued to PMM unc_m_pmm_cmd1.wpq_gnts uncore memory PMM Commands : Underfill GNTs event=0xea,umask=0x20 01 unc_m_pmm_cmd1.wr uncore memory PMM Commands : Writes event=0xea,umask=4 01 PMM Commands : Writes : Counts write commands issued to PMM unc_m_pmm_cmd2.nodata_exp uncore memory PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding) event=0xeb,umask=2 01 unc_m_pmm_cmd2.nodata_unexp uncore memory PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP) event=0xeb,umask=4 01 unc_m_pmm_cmd2.opp_rd uncore memory PMM Commands - Part 2 : Opportunistic Reads event=0xeb,umask=1 01 unc_m_pmm_cmd2.pmm_ecc_error uncore memory PMM Commands - Part 2 : ECC Errors event=0xeb,umask=0x20 01 unc_m_pmm_cmd2.pmm_erid_error uncore memory PMM Commands - Part 2 : ERID detectable parity error event=0xeb,umask=0x40 01 unc_m_pmm_cmd2.pmm_erid_starved uncore memory PMM Commands - Part 2 event=0xeb,umask=0x80 01 unc_m_pmm_cmd2.reqs_slot0 uncore memory PMM Commands - Part 2 : Read Requests - Slot 0 event=0xeb,umask=8 01 unc_m_pmm_cmd2.reqs_slot1 uncore memory PMM Commands - Part 2 : Read Requests - Slot 1 event=0xeb,umask=0x10 01 unc_m_pmm_rpq_inserts uncore memory PMM Read Queue Inserts event=0xe3 01 PMM Read Queue Inserts : Counts number of read requests allocated in the PMM Read Pending Queue. This includes both ISOCH and non-ISOCH requests unc_m_pmm_rpq_occupancy.all uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=1 01 PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.gnt_wait uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=4 01 PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.no_gnt uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=2 01 PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_wpq_flush uncore memory UNC_M_PMM_WPQ_FLUSH event=0xe8 01 unc_m_pmm_wpq_flush_cyc uncore memory UNC_M_PMM_WPQ_FLUSH_CYC event=0xe9 01 unc_m_pmm_wpq_inserts uncore memory PMM Write Queue Inserts event=0xe7 01 PMM Write Queue Inserts : Counts number of write requests allocated in the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.all uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=1 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.cas uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=2 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.pwr uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=4 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_power_throttle_cycles.slot0 uncore memory Throttle Cycles for Rank 0 event=0x46,umask=1 01 Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID unc_m_power_throttle_cycles.slot1 uncore memory Throttle Cycles for Rank 0 event=0x46,umask=2 01 Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_pre_count.all uncore memory DRAM Precharge commands event=2,umask=0x1c 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.page_miss uncore memory DRAM Precharge commands. : Precharge due to page miss event=2,umask=0xc 01 DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests) unc_m_pre_count.pgt uncore memory DRAM Precharge commands. : Precharge due to page table event=2,umask=0x10 01 DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Precharges from Page Table unc_m_pre_count.rd uncore memory DRAM Precharge commands. : Precharge due to read event=2,umask=4 01 DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_m_pre_count.wr uncore memory DRAM Precharge commands. : Precharge due to write event=2,umask=8 01 DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_m_rdb_full uncore memory Read Data Buffer Full event=0x19 01 unc_m_rdb_inserts uncore memory Read Data Buffer Inserts event=0x17 01 unc_m_rdb_not_empty uncore memory Read Data Buffer Not Empty event=0x18 01 unc_m_rdb_occupancy uncore memory Read Data Buffer Occupancy event=0x1a 01 unc_m_rpq_cycles_full_pch0 uncore memory Read Pending Queue Full Cycles event=0x12 01 Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries unc_m_rpq_cycles_full_pch1 uncore memory Read Pending Queue Full Cycles event=0x15 01 Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries unc_m_rpq_cycles_ne.pch0 uncore memory Read Pending Queue Not Empty event=0x11,umask=1 01 Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests unc_m_rpq_cycles_ne.pch1 uncore memory Read Pending Queue Not Empty event=0x11,umask=2 01 Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests unc_m_sb_accesses.accepts uncore memory Scoreboard Accesses : Scoreboard Accesses Accepted event=0xd2,umask=5 01 unc_m_sb_accesses.fmrd_cmps uncore memory This event is deprecated event=0xd2,umask=0x40 11 unc_m_sb_accesses.fmwr_cmps uncore memory This event is deprecated event=0xd2,umask=0x80 11 unc_m_sb_accesses.nmrd_cmps uncore memory This event is deprecated event=0xd2,umask=0x10 11 unc_m_sb_accesses.nmwr_cmps uncore memory This event is deprecated event=0xd2,umask=0x20 11 unc_m_sb_accesses.rejects uncore memory Scoreboard Accesses : Scoreboard Accesses Rejected event=0xd2,umask=0xa 01 unc_m_sb_canary.fmrd_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED event=0xd9,umask=0x20 11 unc_m_sb_canary.fmtgrwr_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED event=0xd9,umask=0x80 11 unc_m_sb_canary.fmwr_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED event=0xd9,umask=0x40 11 unc_m_sb_canary.nmrd_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED event=0xd9,umask=8 11 unc_m_sb_canary.nmwr_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED event=0xd9,umask=0x10 11 unc_m_sb_pref_inserts.pmm uncore memory Scoreboard Prefetch Inserts : Persistent Mem event=0xda,umask=4 01 unc_m_sb_pref_occupancy.pmem uncore memory This event is deprecated. Refer to new event UNC_M_SB_PREF_OCCUPANCY.PMM event=0xdb,umask=4 11 unc_m_sb_strv_alloc.fmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD event=0xd7,umask=2 11 unc_m_sb_strv_alloc.fmtgr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR event=0xd7,umask=0x10 11 unc_m_sb_strv_alloc.fmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR event=0xd7,umask=8 11 unc_m_sb_strv_alloc.nmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD event=0xd7,umask=1 11 unc_m_sb_strv_alloc.nmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR event=0xd7,umask=4 11 unc_m_sb_strv_dealloc.fmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD event=0xde,umask=2 11 unc_m_sb_strv_dealloc.fmtgr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR event=0xde,umask=0x10 11 unc_m_sb_strv_dealloc.fmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR event=0xde,umask=8 11 unc_m_sb_strv_dealloc.nmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD event=0xde,umask=1 11 unc_m_sb_strv_dealloc.nmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR event=0xde,umask=4 11 unc_m_sb_strv_occ.fmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD event=0xd8,umask=2 11 unc_m_sb_strv_occ.fmtgr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR event=0xd8,umask=0x10 11 unc_m_sb_strv_occ.fmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR event=0xd8,umask=8 11 unc_m_sb_strv_occ.nmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD event=0xd8,umask=1 11 unc_m_sb_strv_occ.nmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR event=0xd8,umask=4 11 unc_m_tagchk.hit uncore memory 2LM Tag Check : Hit in Near Memory Cache event=0xd3,umask=1 01 unc_m_tagchk.miss_clean uncore memory 2LM Tag Check : Miss, no data in this line event=0xd3,umask=2 01 unc_m_tagchk.miss_dirty uncore memory 2LM Tag Check : Miss, existing data may be evicted to Far Memory event=0xd3,umask=4 01 unc_m_tagchk.nm_rd_hit uncore memory 2LM Tag Check : Read Hit in Near Memory Cache event=0xd3,umask=8 01 unc_m_tagchk.nm_wr_hit uncore memory 2LM Tag Check : Write Hit in Near Memory Cache event=0xd3,umask=0x10 01 unc_m_wpq_cycles_full_pch0 uncore memory Write Pending Queue Full Cycles event=0x22 01 Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_full_pch1 uncore memory Write Pending Queue Full Cycles event=0x16 01 Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_ne.pch0 uncore memory Write Pending Queue Not Empty event=0x21,umask=1 01 Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_cycles_ne.pch1 uncore memory Write Pending Queue Not Empty event=0x21,umask=2 01 Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_read_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x23,umask=1 01 Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_read_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x23,umask=2 01 Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_write_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x24,umask=1 01 Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_write_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x24,umask=2 01 Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_p_clockticks uncore power Clockticks of the power control unit (PCU) event=0 01 Clockticks of the power control unit (PCU) : The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time unc_p_pkg_residency_c3_cycles uncore power Package C State Residency - C3 event=0x2c 01 Package C State Residency - C3 : Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C-State : C0 and C1 event=0x80,umask=0x40 01 Number of cores in C-State : C0 and C1 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C-State : C3 event=0x80,umask=0x80 01 Number of cores in C-State : C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C-State : C6 and C7 event=0x80,umask=0xc0 01 Number of cores in C-State : C6 and C7 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details dtlb_load_misses.walk_completed_1g virtual memory Page walks completed due to a demand data load to a 1G page event=8,period=100003,umask=8 00 Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_1g virtual memory Page walks completed due to a demand data store to a 1G page event=0x49,period=100003,umask=8 00 Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=1 00 Counts the number of lines brought into the L1 data cache l1d_pend_miss.fb_full cache Cycles a demand request was blocked due to Fill Buffers unavailability event=0x48,cmask=1,period=2000003,umask=2 00 Cycles a demand request was blocked due to Fill Buffers unavailability l1d_pend_miss.pending_cycles_any cache Cycles with L1D load Misses outstanding from any thread on physical core event=0x48,any=1,cmask=1,period=2000003,umask=1 00 Cycles with L1D load Misses outstanding from any thread on physical core l2_l1d_wb_rqsts.all cache Not rejected writebacks from L1D to L2 cache lines in any state event=0x28,period=200003,umask=0xf 00 l2_l1d_wb_rqsts.hit_e cache Not rejected writebacks from L1D to L2 cache lines in E state event=0x28,period=200003,umask=4 00 Not rejected writebacks from L1D to L2 cache lines in E state l2_l1d_wb_rqsts.hit_m cache Not rejected writebacks from L1D to L2 cache lines in M state event=0x28,period=200003,umask=8 00 Not rejected writebacks from L1D to L2 cache lines in M state l2_l1d_wb_rqsts.miss cache Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.) event=0x28,period=200003,umask=1 00 Not rejected writebacks that missed LLC l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=7 00 L2 cache lines filling L2 l2_lines_out.demand_clean cache Clean L2 cache lines evicted by demand event=0xf2,period=100003,umask=1 00 Clean L2 cache lines evicted by demand l2_lines_out.demand_dirty cache Dirty L2 cache lines evicted by demand event=0xf2,period=100003,umask=2 00 Dirty L2 cache lines evicted by demand l2_lines_out.dirty_all cache Dirty L2 cache lines filling the L2 event=0xf2,period=100003,umask=0xa 00 Dirty L2 cache lines filling the L2 l2_lines_out.pf_clean cache Clean L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=4 00 Clean L2 cache lines evicted by the MLC prefetcher l2_lines_out.pf_dirty cache Dirty L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=8 00 Dirty L2 cache lines evicted by the MLC prefetcher l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0x30 00 Counts all L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=3 00 Counts any demand and L1 HW prefetch data load requests to L2 l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xc0 00 Counts all L2 HW prefetcher requests l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xc 00 Counts all L2 store RFO requests l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0x10 00 Number of instruction fetches that hit the L2 cache l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x20 00 Number of instruction fetches that missed the L2 cache l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=1 00 Demand Data Read requests that hit L2 cache l2_rqsts.pf_hit cache Requests from the L2 hardware prefetchers that hit L2 cache event=0x24,period=200003,umask=0x40 00 Counts all L2 HW prefetcher requests that hit L2 l2_rqsts.pf_miss cache Requests from the L2 hardware prefetchers that miss L2 cache event=0x24,period=200003,umask=0x80 00 Counts all L2 HW prefetcher requests that missed L2 l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=4 00 RFO requests that hit L2 cache l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=8 00 Counts the number of store RFO requests that miss the L2 cache l2_store_lock_rqsts.all cache RFOs that access cache lines in any state event=0x27,period=200003,umask=0xf 00 RFOs that access cache lines in any state l2_store_lock_rqsts.hit_m cache RFOs that hit cache lines in M state event=0x27,period=200003,umask=8 00 RFOs that hit cache lines in M state l2_store_lock_rqsts.miss cache RFOs that miss cache lines event=0x27,period=200003,umask=1 00 RFOs that miss cache lines l2_trans.all_pf cache L2 or LLC HW prefetches that access L2 cache event=0xf0,period=200003,umask=8 00 Any MLC or LLC HW prefetch accessing L2, including rejects l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=1 00 Demand Data Read requests that access L2 cache longest_lat_cache.miss cache Core-originated cacheable demand requests missed LLC event=0x2e,period=100003,umask=0x41 00 This event counts each cache miss condition for references to the last level cache longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to LLC event=0x2e,period=100003,umask=0x4f 00 This event counts requests originating from the core that reference a cache line in the last level cache mem_load_uops_llc_hit_retired.xsnp_hit cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache (Precise event) event=0xd2,period=20011,umask=2 00 mem_load_uops_llc_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared LLC (Precise event) event=0xd2,period=20011,umask=4 00 mem_load_uops_llc_hit_retired.xsnp_miss cache Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache (Precise event) event=0xd2,period=20011,umask=1 00 mem_load_uops_llc_hit_retired.xsnp_none cache Retired load uops which data sources were hits in LLC without snoops required (Precise event) event=0xd2,period=100003,umask=8 00 mem_load_uops_llc_miss_retired.local_dram cache Retired load uops which data sources missed LLC but serviced from local dram event=0xd3,period=100007,umask=1 00 Retired load uops whose data source was local memory (cross-socket snoop not needed or missed) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready (Precise event) event=0xd1,period=100003,umask=0x40 00 mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources (Precise event) event=0xd1,period=2000003,umask=1 00 mem_load_uops_retired.l1_miss cache Retired load uops which data sources following L1 data-cache miss (Precise event) event=0xd1,period=100003,umask=8 00 mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources (Precise event) event=0xd1,period=100003,umask=2 00 mem_load_uops_retired.l2_miss cache Retired load uops with L2 cache misses as data sources (Precise event) event=0xd1,period=50021,umask=0x10 00 mem_load_uops_retired.llc_hit cache Retired load uops which data sources were data hits in LLC without snoops required (Precise event) event=0xd1,period=50021,umask=4 00 mem_load_uops_retired.llc_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source (Precise event) event=0xd1,period=100007,umask=0x20 00 mem_uops_retired.all_loads cache All retired load uops. (Precise Event) event=0xd0,period=2000003,umask=0x81 00 mem_uops_retired.all_stores cache All retired store uops. (Precise Event) event=0xd0,period=2000003,umask=0x82 00 mem_uops_retired.lock_loads cache Retired load uops with locked access. (Precise Event) event=0xd0,period=100007,umask=0x21 00 mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary. (Precise Event) event=0xd0,period=100003,umask=0x41 00 mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary. (Precise Event) event=0xd0,period=100003,umask=0x42 00 mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB. (Precise Event) event=0xd0,period=100003,umask=0x11 00 mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB. (Precise Event) event=0xd0,period=100003,umask=0x12 00 offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=1 00 Demand data read requests sent to uncore offcore_requests_buffer.sq_full cache Cases when offcore requests buffer cannot take more entries for core event=0xb2,period=2000003,umask=1 00 Cases when offcore requests buffer cannot take more entries for core offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=8 00 Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=8 00 Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore offcore_requests_outstanding.cycles_with_demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,cmask=1,period=2000003,umask=2 00 Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=1 00 Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,cmask=1,period=2000003,umask=4 00 Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle offcore_requests_outstanding.demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,period=2000003,umask=2 00 Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue event=0x60,period=2000003,umask=1 00 Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue event=0x60,cmask=6,period=2000003,umask=1 00 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=4 00 Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_response.all_code_rd.llc_hit.any_response cache Counts all demand & prefetch code reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0244 00 offcore_response.all_code_rd.llc_hit.no_snoop_needed cache Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0244 00 offcore_response.all_data_rd.any_response cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x000105B3 00 offcore_response.all_data_rd.llc_hit.any_response cache Counts all demand & prefetch data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0091 00 offcore_response.all_data_rd.llc_hit.hitm_other_core cache Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0091 00 offcore_response.all_data_rd.llc_hit.hit_other_core_no_fwd cache Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0091 00 offcore_response.all_data_rd.llc_hit.no_snoop_needed cache Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0091 00 offcore_response.all_reads.any_response cache Counts all data/code/rfo references (demand & prefetch) event=0xb7,period=100003,umask=1,offcore_rsp=0x000107F7 00 offcore_response.all_rfo.any_response cache Counts all demand & prefetch prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x00010122 00 offcore_response.all_rfo.llc_hit.any_response cache Counts all demand & prefetch RFOs that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0122 00 offcore_response.all_rfo.llc_hit.no_snoop_needed cache Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0122 00 offcore_response.corewb.any_response cache Counts all writebacks from the core to the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x10008 00 offcore_response.demand_code_rd.any_response cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x00010004 00 offcore_response.demand_code_rd.llc_hit.any_response cache Counts all demand code reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0004 00 offcore_response.demand_code_rd.llc_hit.no_snoop_needed cache Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0004 00 offcore_response.demand_data_rd.any_response cache Counts all demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x00010001 00 offcore_response.demand_data_rd.llc_hit.any_response cache Counts all demand data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0001 00 offcore_response.demand_data_rd.llc_hit.hitm_other_core cache Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0001 00 offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwd cache Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0001 00 offcore_response.demand_data_rd.llc_hit.no_snoop_needed cache Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0001 00 offcore_response.demand_rfo.any_response cache Counts all demand rfo's event=0xb7,period=100003,umask=1,offcore_rsp=0x00010002 00 offcore_response.demand_rfo.llc_hit.any_response cache Counts all demand data writes (RFOs) that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0002 00 offcore_response.demand_rfo.llc_hit.hitm_other_core cache Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0002 00 offcore_response.demand_rfo.llc_hit.no_snoop_needed cache Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0002 00 offcore_response.other.any_response cache Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches event=0xb7,period=100003,umask=1,offcore_rsp=0x18000 00 offcore_response.split_lock_uc_lock.any_response cache Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address event=0xb7,period=100003,umask=1,offcore_rsp=0x10400 00 offcore_response.streaming_stores.any_response cache Counts non-temporal stores event=0xb7,period=100003,umask=1,offcore_rsp=0x10800 00 fp_comp_ops_exe.sse_packed_double floating point Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle event=0x10,period=2000003,umask=0x10 00 Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle fp_comp_ops_exe.sse_packed_single floating point Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle event=0x10,period=2000003,umask=0x40 00 Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle fp_comp_ops_exe.sse_scalar_double floating point Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle event=0x10,period=2000003,umask=0x80 00 Counts number of SSE* or AVX-128 double precision FP scalar uops executed fp_comp_ops_exe.sse_scalar_single floating point Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle event=0x10,period=2000003,umask=0x20 00 Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle fp_comp_ops_exe.x87 floating point Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s event=0x10,period=2000003,umask=1 00 Counts number of X87 uops executed other_assists.avx_store floating point Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations event=0xc1,period=100003,umask=8 00 Number of assists associated with 256-bit AVX store operations other_assists.avx_to_sse floating point Number of transitions from AVX-256 to legacy SSE when penalty applicable event=0xc1,period=100003,umask=0x10 00 other_assists.sse_to_avx floating point Number of transitions from SSE to AVX-256 when penalty applicable event=0xc1,period=100003,umask=0x20 00 simd_fp_256.packed_double floating point number of AVX-256 Computational FP double precision uops issued this cycle event=0x11,period=2000003,umask=2 00 Counts 256-bit packed double-precision floating-point instructions simd_fp_256.packed_single floating point number of GSSE-256 Computational FP single precision uops issued this cycle event=0x11,period=2000003,umask=1 00 Counts 256-bit packed single-precision floating-point instructions dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE switches event=0xab,period=2000003,umask=1 00 Number of DSB to MITE switches dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=2 00 Cycles DSB to MITE switches caused delay dsb_fill.exceed_dsb_lines frontend Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines event=0xac,period=2000003,umask=8 00 DSB Fill encountered > 3 DSB lines icache.hit frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches event=0x80,period=2000003,umask=1 00 Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches icache.ifetch_stall frontend Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss event=0x80,period=2000003,umask=4 00 Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss icache.misses frontend Instruction cache, streaming buffer and victim cache misses event=0x80,period=200003,umask=2 00 Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24 00 Counts cycles MITE is delivered at least one uops. Set Cmask = 1 idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=8 00 Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path idq.empty frontend Instruction Decode Queue (IDQ) empty cycles event=0x79,period=2000003,umask=2 00 Counts cycles the IDQ is empty idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=4 00 Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10 00 Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy idq.ms_dsb_occur frontend Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,edge=1,period=2000003,umask=0x10 00 Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30 00 Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=1 00 Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=4,period=2000003,umask=1 00 idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=3,period=2000003,umask=1 00 machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=2 00 mem_trans_retired.load_latency_gt_128 memory Loads with latency value being above 128 (Must be precise) event=0xcd,period=1009,umask=1,ldlat=0x80 00 Loads with latency value being above 128 (Must be precise) mem_trans_retired.load_latency_gt_16 memory Loads with latency value being above 16 (Must be precise) event=0xcd,period=20011,umask=1,ldlat=0x10 00 Loads with latency value being above 16 (Must be precise) mem_trans_retired.load_latency_gt_256 memory Loads with latency value being above 256 (Must be precise) event=0xcd,period=503,umask=1,ldlat=0x100 00 Loads with latency value being above 256 (Must be precise) mem_trans_retired.load_latency_gt_32 memory Loads with latency value being above 32 (Must be precise) event=0xcd,period=100007,umask=1,ldlat=0x20 00 Loads with latency value being above 32 (Must be precise) mem_trans_retired.load_latency_gt_4 memory Loads with latency value being above 4 (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x4 00 Loads with latency value being above 4 (Must be precise) mem_trans_retired.load_latency_gt_512 memory Loads with latency value being above 512 (Must be precise) event=0xcd,period=101,umask=1,ldlat=0x200 00 Loads with latency value being above 512 (Must be precise) mem_trans_retired.load_latency_gt_64 memory Loads with latency value being above 64 (Must be precise) event=0xcd,period=2003,umask=1,ldlat=0x40 00 Loads with latency value being above 64 (Must be precise) mem_trans_retired.load_latency_gt_8 memory Loads with latency value being above 8 (Must be precise) event=0xcd,period=50021,umask=1,ldlat=0x8 00 Loads with latency value being above 8 (Must be precise) mem_trans_retired.precise_store memory Sample stores and collect precise store operation via PEBS record. PMC3 only (Must be precise) event=0xcd,period=2000003,umask=2 00 misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=5,period=2000003,umask=2 00 Speculative cache-line split Store-address uops dispatched to L1D offcore_response.all_code_rd.llc_miss.dram memory Counts all demand & prefetch code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400244 00 offcore_response.all_data_rd.llc_miss.dram memory Counts all demand & prefetch data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400091 00 offcore_response.all_reads.llc_miss.dram memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x3004003f7 00 offcore_response.data_in_socket.llc_miss.local_dram memory Counts LLC replacements event=0xb7,period=100003,umask=1,offcore_rsp=0x6004001b3 00 offcore_response.demand_code_rd.llc_miss.dram memory Counts demand code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400004 00 offcore_response.demand_data_rd.llc_miss.dram memory Counts demand data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400001 00 page_walks.llc_miss memory Number of any page walk that had a miss in LLC event=0xbe,period=100003,umask=1 00 cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100007,umask=1 00 Number of intervals between processor halts while thread is in ring 0 arith.fpu_div pipeline Divide operations executed event=0x14,cmask=1,edge=1,period=100003,umask=4 00 Divide operations executed arith.fpu_div_active pipeline Cycles when divider is busy executing divide operations event=0x14,period=2000003,umask=1 00 Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides br_inst_exec.all_conditional pipeline Speculative and retired macro-conditional branches event=0x88,period=200003,umask=0xc1 00 Speculative and retired macro-conditional branches br_inst_exec.all_direct_jmp pipeline Speculative and retired macro-unconditional branches excluding calls and indirects event=0x88,period=200003,umask=0xc2 00 Speculative and retired macro-unconditional branches excluding calls and indirects br_inst_exec.all_direct_near_call pipeline Speculative and retired direct near calls event=0x88,period=200003,umask=0xd0 00 Speculative and retired direct near calls br_inst_exec.all_indirect_jump_non_call_ret pipeline Speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0xc4 00 Speculative and retired indirect branches excluding calls and returns br_inst_exec.nontaken_conditional pipeline Not taken macro-conditional branches event=0x88,period=200003,umask=0x41 00 Not taken macro-conditional branches br_inst_exec.taken_conditional pipeline Taken speculative and retired macro-conditional branches event=0x88,period=200003,umask=0x81 00 Taken speculative and retired macro-conditional branches br_inst_exec.taken_direct_jump pipeline Taken speculative and retired macro-conditional branch instructions excluding calls and indirects event=0x88,period=200003,umask=0x82 00 Taken speculative and retired macro-conditional branch instructions excluding calls and indirects br_inst_exec.taken_direct_near_call pipeline Taken speculative and retired direct near calls event=0x88,period=200003,umask=0x90 00 Taken speculative and retired direct near calls br_inst_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0x84 00 Taken speculative and retired indirect branches excluding calls and returns br_inst_exec.taken_indirect_near_call pipeline Taken speculative and retired indirect calls event=0x88,period=200003,umask=0xa0 00 Taken speculative and retired indirect calls br_inst_exec.taken_indirect_near_return pipeline Taken speculative and retired indirect branches with return mnemonic event=0x88,period=200003,umask=0x88 00 Taken speculative and retired indirect branches with return mnemonic br_inst_retired.conditional pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=1 00 br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100007,umask=0x40 00 Number of far branches retired br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100007,umask=2 00 br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) event=0xc4,period=100007,umask=2 00 br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100007,umask=8 00 br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20 00 br_misp_exec.all_conditional pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xc1 00 Speculative and retired mispredicted macro conditional branches br_misp_exec.all_indirect_jump_non_call_ret pipeline Mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0xc4 00 Mispredicted indirect branches excluding calls and returns br_misp_exec.nontaken_conditional pipeline Not taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x41 00 Not taken speculative and retired mispredicted macro conditional branches br_misp_exec.taken_conditional pipeline Taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x81 00 Taken speculative and retired mispredicted macro conditional branches br_misp_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0x84 00 Taken speculative and retired mispredicted indirect branches excluding calls and returns br_misp_exec.taken_indirect_near_call pipeline Taken speculative and retired mispredicted indirect calls event=0x89,period=200003,umask=0xa0 00 Taken speculative and retired mispredicted indirect calls br_misp_exec.taken_return_near pipeline Taken speculative and retired mispredicted indirect branches with return mnemonic event=0x89,period=200003,umask=0x88 00 Taken speculative and retired mispredicted indirect branches with return mnemonic br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired (Must be precise) event=0xc5,period=400009,umask=4 00 br_misp_retired.near_taken pipeline number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20 00 cpu_clk_thread_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other is halted event=0x3c,period=2000003,umask=2 00 cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=1 00 Increments at the frequency of XCLK (100 MHz) when not halted cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=1 00 cpu_clk_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other thread is halted event=0x3c,period=2000003,umask=2 00 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3 00 cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=1 00 Reference cycles when the thread is unhalted. (counts at 100 MHz rate) cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=1 00 cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003 00 cpu_clk_unhalted.thread_any pipeline Core cycles when at least one thread on the physical core is not in halt state event=0x3c,any=1,period=2000003 00 Core cycles when at least one thread on the physical core is not in halt state cpu_clk_unhalted.thread_p_any pipeline Core cycles when at least one thread on the physical core is not in halt state event=0x3c,any=1,period=2000003 00 Core cycles when at least one thread on the physical core is not in halt state cycle_activity.cycles_l1d_pending pipeline Cycles with pending L1 cache miss loads event=0xa3,cmask=8,period=2000003,umask=8 00 Cycles with pending L1 cache miss loads. Set AnyThread to count per core cycle_activity.cycles_l2_miss pipeline Cycles while L2 cache miss load* is outstanding event=0xa3,cmask=1,period=2000003,umask=1 00 cycle_activity.cycles_l2_pending pipeline Cycles with pending L2 cache miss loads event=0xa3,cmask=1,period=2000003,umask=1 00 Cycles with pending L2 miss loads. Set AnyThread to count per core cycle_activity.cycles_ldm_pending pipeline Cycles with pending memory loads event=0xa3,cmask=2,period=2000003,umask=2 00 Cycles with pending memory loads. Set AnyThread to count per core cycle_activity.cycles_no_execute pipeline This event increments by 1 for every cycle where there was no execute for this thread event=0xa3,cmask=4,period=2000003,umask=4 00 Total execution stalls cycle_activity.stalls_l2_miss pipeline Execution stalls while L2 cache miss load* is outstanding event=0xa3,cmask=5,period=2000003,umask=5 00 cycle_activity.stalls_l2_pending pipeline Execution stalls due to L2 cache misses event=0xa3,cmask=5,period=2000003,umask=5 00 Number of loads missed L2 cycle_activity.stalls_ldm_pending pipeline Execution stalls due to memory subsystem event=0xa3,cmask=6,period=2000003,umask=6 00 ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction event=0x87,period=2000003,umask=1 00 inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003 00 inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event event=0xc0,period=2000003 00 Number of instructions at retirement inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise) event=0xc0,period=2000003,umask=1 00 Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise) int_misc.recovery_cycles pipeline Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) event=0xd,cmask=1,period=2000003,umask=3 00 int_misc.recovery_stalls_count pipeline Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) event=0xd,cmask=1,edge=1,period=2000003,umask=3 00 ld_blocks.no_sr pipeline This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=3,period=100003,umask=8 00 The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=3,period=100003,umask=2 00 Loads blocked by overlapping with store buffer that cannot be forwarded ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=7,period=100003,umask=1 00 False dependencies in MOB due to partial compare on address lsd.cycles_4_uops pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=4,period=2000003,umask=1 00 Cycles 4 Uops delivered by the LSD, but didn't come from the decoder lsd.cycles_active pipeline Cycles Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=1,period=2000003,umask=1 00 Cycles Uops delivered by the LSD, but didn't come from the decoder machine_clears.maskmov pipeline This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 event=0xc3,period=100003,umask=0x20 00 Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0 machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=4 00 Number of self-modifying-code machine clears detected other_assists.any_wb_assist pipeline Number of times any microcode assist is invoked by HW upon uop writeback event=0xc1,period=100003,umask=0x80 00 resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=1 00 Cycles Allocation is stalled due to Resource Related reason resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=8 00 Cycles stalled due to no store buffers available (not including draining form sync) rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=1 00 Cycles the RS is empty for the thread uops_dispatched_port.port_0 pipeline Cycles per thread when uops are dispatched to port 0 event=0xa1,period=2000003,umask=1 00 Cycles which a Uop is dispatched on port 0 uops_dispatched_port.port_0_core pipeline Cycles per core when uops are dispatched to port 0 event=0xa1,any=1,period=2000003,umask=1 00 Cycles per core when uops are dispatched to port 0 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are dispatched to port 1 event=0xa1,period=2000003,umask=2 00 Cycles which a Uop is dispatched on port 1 uops_dispatched_port.port_1_core pipeline Cycles per core when uops are dispatched to port 1 event=0xa1,any=1,period=2000003,umask=2 00 Cycles per core when uops are dispatched to port 1 uops_dispatched_port.port_2 pipeline Cycles per thread when load or STA uops are dispatched to port 2 event=0xa1,period=2000003,umask=0xc 00 Cycles which a Uop is dispatched on port 2 uops_dispatched_port.port_2_core pipeline Uops dispatched to port 2, loads and stores per core (speculative and retired) event=0xa1,any=1,period=2000003,umask=0xc 00 uops_dispatched_port.port_3 pipeline Cycles per thread when load or STA uops are dispatched to port 3 event=0xa1,period=2000003,umask=0x30 00 Cycles which a Uop is dispatched on port 3 uops_dispatched_port.port_3_core pipeline Cycles per core when load or STA uops are dispatched to port 3 event=0xa1,any=1,period=2000003,umask=0x30 00 Cycles per core when load or STA uops are dispatched to port 3 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are dispatched to port 4 event=0xa1,period=2000003,umask=0x40 00 Cycles which a Uop is dispatched on port 4 uops_dispatched_port.port_4_core pipeline Cycles per core when uops are dispatched to port 4 event=0xa1,any=1,period=2000003,umask=0x40 00 Cycles per core when uops are dispatched to port 4 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are dispatched to port 5 event=0xa1,period=2000003,umask=0x80 00 Cycles which a Uop is dispatched on port 5 uops_dispatched_port.port_5_core pipeline Cycles per core when uops are dispatched to port 5 event=0xa1,any=1,period=2000003,umask=0x80 00 Cycles per core when uops are dispatched to port 5 uops_executed.core pipeline Number of uops executed on the core event=0xb1,period=2000003,umask=2 00 Counts total number of uops to be executed per-core each cycle uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core event=0xb1,cmask=1,period=2000003,umask=2 00 Cycles at least 1 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core event=0xb1,cmask=2,period=2000003,umask=2 00 Cycles at least 2 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core event=0xb1,cmask=3,period=2000003,umask=2 00 Cycles at least 3 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core event=0xb1,cmask=4,period=2000003,umask=2 00 Cycles at least 4 micro-op is executed from any thread on physical core uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core event=0xb1,inv=1,period=2000003,umask=2 00 Cycles with no micro-ops executed from any thread on physical core uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=1 00 uops_executed.thread pipeline Counts the number of uops to be executed per-thread each cycle event=0xb1,period=2000003,umask=1 00 Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=1 00 Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core uops_issued.core_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads event=0xe,any=1,cmask=1,inv=1,period=2000003,umask=1 00 Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads uops_issued.flags_merge pipeline Number of flags-merge uops being allocated event=0xe,period=2000003,umask=0x10 00 Number of flags-merge uops allocated. Such uops adds delay uops_issued.slow_lea pipeline Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not event=0xe,period=2000003,umask=0x20 00 Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=1 00 Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread uops_retired.all pipeline Retired uops (Precise event) event=0xc2,period=2000003,umask=1 00 uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=2 00 uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=10,inv=1,period=2000003,umask=1 00 unc_arb_coh_trk_occupancy.all uncore interconnect Cycles weighted by number of requests pending in Coherency Tracker event=0x83,umask=1 01 unc_arb_trk_occupancy.all uncore interconnect Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC event=0x80,umask=1 01 unc_arb_trk_occupancy.cycles_over_half_full uncore interconnect Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC event=0x80,cmask=10,umask=1 01 unc_arb_trk_requests.evictions uncore interconnect Counts the number of LLC evictions allocated event=0x81,umask=0x80 01 unc_arb_trk_requests.writes uncore interconnect Counts the number of allocated write entries, include full, partial, and LLC evictions event=0x81,umask=0x20 01 unc_clock.socket uncore interconnect This 48-bit fixed counter counts the UCLK cycles event=0xff 01 dtlb_load_misses.large_page_walk_completed virtual memory Page walk for a large page completed for Demand load event=8,period=100003,umask=0x88 00 dtlb_load_misses.miss_causes_a_walk virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size event=8,period=100003,umask=0x81 00 Misses in all TLB levels that cause a page walk of any page size from demand loads dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=0x5f,period=100003,umask=4 00 Counts load operations that missed 1st level DTLB but hit the 2nd level dtlb_load_misses.walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size event=8,period=100003,umask=0x82 00 Misses in all TLB levels that caused page walk completed of any size by demand loads dtlb_load_misses.walk_duration virtual memory Demand load cycles page miss handler (PMH) is busy with this walk event=8,period=2000003,umask=0x84 00 Cycle PMH is busy with a walk due to demand loads dtlb_store_misses.stlb_hit virtual memory Store operations that miss the first TLB level but hit the second and do not cause page walks event=0x49,period=100003,umask=0x10 00 Store operations that miss the first TLB level but hit the second and do not cause page walks dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks event=0x49,period=100003,umask=2 00 Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G) dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x49,period=2000003,umask=4 00 Cycles PMH is busy with this walk ept.walk_cycles virtual memory Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches event=0x4f,period=2000003,umask=0x10 00 itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=1 00 Counts the number of ITLB flushes, includes 4k/2M/4M pages itlb_misses.large_page_walk_completed virtual memory Completed page walks in ITLB due to STLB load misses for large pages event=0x85,period=100003,umask=0x80 00 Completed page walks in ITLB due to STLB load misses for large pages itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=1 00 Misses in all ITLB levels that cause page walks itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x10 00 Number of cache load STLB hits. No page walk itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks event=0x85,period=100003,umask=2 00 Misses in all ITLB levels that cause completed page walks itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x85,period=2000003,umask=4 00 Cycle PMH is busy with a walk tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=1 00 DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20 00 Count number of STLB flush attempts mem_load_uops_llc_miss_retired.local_dram cache Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) event=0xd3,period=100007,umask=3 00 mem_load_uops_llc_miss_retired.remote_dram cache Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) event=0xd3,period=100007,umask=0xc 00 mem_load_uops_llc_miss_retired.remote_fwd cache Data forwarded from remote cache event=0xd3,period=100007,umask=0x20 00 mem_load_uops_llc_miss_retired.remote_hitm cache Remote cache HITM event=0xd3,period=100007,umask=0x10 00 offcore_response.all_data_rd.llc_hit.snoop_miss cache Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0091 00 offcore_response.all_pf_data_rd.llc_hit.any_response cache Counts all prefetch data reads that hit the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0090 00 offcore_response.all_pf_data_rd.llc_hit.hitm_other_core cache Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0090 00 offcore_response.all_pf_data_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0090 00 offcore_response.all_pf_data_rd.llc_hit.no_snoop_needed cache Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0090 00 offcore_response.all_pf_data_rd.llc_hit.snoop_miss cache Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0090 00 offcore_response.all_reads.llc_hit.any_response cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c03f7 00 offcore_response.all_reads.llc_hit.hitm_other_core cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c03f7 00 offcore_response.all_reads.llc_hit.hit_other_core_no_fwd cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c03f7 00 offcore_response.all_reads.llc_hit.no_snoop_needed cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c03f7 00 offcore_response.all_reads.llc_hit.snoop_miss cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c03f7 00 offcore_response.demand_data_rd.llc_hit.snoop_miss cache Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0001 00 offcore_response.other.lru_hints cache Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches event=0xb7,period=100003,umask=1,offcore_rsp=0x803c8000 00 offcore_response.other.portio_mmio_uc cache Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses event=0xb7,period=100003,umask=1,offcore_rsp=0x23ffc08000 00 offcore_response.pf_l2_code_rd.llc_hit.any_response cache Counts all prefetch (that bring data to L2) code reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0040 00 offcore_response.pf_l2_data_rd.llc_hit.any_response cache Counts prefetch (that bring data to L2) data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0010 00 offcore_response.pf_l2_data_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0010 00 offcore_response.pf_l2_data_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0010 00 offcore_response.pf_l2_data_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0010 00 offcore_response.pf_l2_data_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0010 00 offcore_response.pf_llc_code_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0200 00 offcore_response.pf_llc_data_rd.llc_hit.any_response cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0080 00 offcore_response.pf_llc_data_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0080 00 offcore_response.pf_llc_data_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0080 00 offcore_response.pf_llc_data_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0080 00 offcore_response.pf_llc_data_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0080 00 offcore_response.all_code_rd.llc_miss.any_response memory Counts all demand & prefetch code reads that miss the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc00244 00 offcore_response.all_code_rd.llc_miss.remote_dram memory Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67f800244 00 offcore_response.all_code_rd.llc_miss.remote_hit_forward memory Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87f800244 00 offcore_response.all_data_rd.llc_miss.any_response memory Counts all demand & prefetch data reads that hits the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20091 00 offcore_response.all_reads.llc_miss.any_response memory Counts all data/code/rfo reads (demand & prefetch) that hit the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc203f7 00 offcore_response.all_reads.llc_miss.local_dram memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x6004003f7 00 offcore_response.all_reads.llc_miss.remote_hitm memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=1,offcore_rsp=0x107fc003f7 00 offcore_response.all_reads.llc_miss.remote_hit_forward memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87f8203f7 00 offcore_response.demand_code_rd.llc_miss.any_response memory Counts all demand code reads that miss the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20004 00 offcore_response.demand_code_rd.llc_miss.local_dram memory Counts all demand code reads that miss the LLC and the data returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400004 00 offcore_response.demand_code_rd.llc_miss.remote_dram memory Counts all demand code reads that miss the LLC and the data returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67f800004 00 offcore_response.demand_code_rd.llc_miss.remote_hitm memory Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=1,offcore_rsp=0x107fc00004 00 offcore_response.demand_code_rd.llc_miss.remote_hit_forward memory Counts all demand code reads that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87f820004 00 offcore_response.demand_data_rd.llc_miss.any_dram memory Counts demand data reads that miss the LLC and the data returned from remote & local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67fc00001 00 offcore_response.demand_data_rd.llc_miss.any_response memory Counts demand data reads that miss in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20001 00 offcore_response.demand_data_rd.llc_miss.local_dram memory Counts demand data reads that miss the LLC and the data returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400001 00 offcore_response.demand_data_rd.llc_miss.remote_dram memory Counts demand data reads that miss the LLC and the data returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67f800001 00 offcore_response.demand_data_rd.llc_miss.remote_hitm memory Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=1,offcore_rsp=0x107fc00001 00 offcore_response.demand_data_rd.llc_miss.remote_hit_forward memory Counts demand data reads that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87f820001 00 offcore_response.demand_rfo.llc_miss.remote_hitm memory Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=1,offcore_rsp=0x107fc20002 00 offcore_response.pf_l2_code_rd.llc_miss.any_response memory Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20040 00 offcore_response.pf_l2_data_rd.llc_miss.any_dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67fc00010 00 offcore_response.pf_l2_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to L2) data reads that miss in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20010 00 offcore_response.pf_l2_data_rd.llc_miss.local_dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400010 00 offcore_response.pf_l2_data_rd.llc_miss.remote_dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67f800010 00 offcore_response.pf_l2_data_rd.llc_miss.remote_hitm memory Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=1,offcore_rsp=0x107fc00010 00 offcore_response.pf_l2_data_rd.llc_miss.remote_hit_forward memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87f820010 00 offcore_response.pf_llc_code_rd.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20200 00 offcore_response.pf_llc_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to LLC only) data reads that miss in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20080 00 unc_c_llc_lookup.any uncore cache Cache Lookups; Any Request event=0x34,umask=0x11 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_c_llc_lookup.data_read uncore cache Cache Lookups; Data Read Request event=0x34,umask=3 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Read transactions unc_c_llc_lookup.nid uncore cache Cache Lookups; Lookups that Match NID event=0x34,umask=0x41 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_llc_lookup.remote_snoop uncore cache Cache Lookups; External Snoop Request event=0x34,umask=9 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ unc_c_llc_lookup.write uncore cache Cache Lookups; Write Requests event=0x34,umask=5 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_c_llc_victims.miss uncore cache Lines Victimized event=0x37,umask=8 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.s_state uncore cache Lines Victimized; Lines in S State event=0x37,umask=4 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_ring_ad_used.ccw uncore cache AD Ring In Use; Counterclockwise event=0x1b,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.cw uncore cache AD Ring In Use; Clockwise event=0x1b,umask=3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down uncore cache AD Ring In Use; Down event=0x1b,umask=0xcc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_vr0_even uncore cache AD Ring In Use; Down and Even on Vring 0 event=0x1b,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0 unc_c_ring_ad_used.down_vr0_odd uncore cache AD Ring In Use; Down and Odd on Vring 0 event=0x1b,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0 unc_c_ring_ad_used.down_vr1_even uncore cache AD Ring In Use; Down and Even on VRing 1 event=0x1b,umask=0x40 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1 unc_c_ring_ad_used.down_vr1_odd uncore cache AD Ring In Use; Down and Odd on VRing 1 event=0x1b,umask=0x80 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1 unc_c_ring_ad_used.up uncore cache AD Ring In Use; Up event=0x1b,umask=0x33 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_vr0_even uncore cache AD Ring In Use; Up and Even on Vring 0 event=0x1b,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0 unc_c_ring_ad_used.up_vr0_odd uncore cache AD Ring In Use; Up and Odd on Vring 0 event=0x1b,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0 unc_c_ring_ad_used.up_vr1_even uncore cache AD Ring In Use; Up and Even on VRing 1 event=0x1b,umask=0x10 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1 unc_c_ring_ad_used.up_vr1_odd uncore cache AD Ring In Use; Up and Odd on VRing 1 event=0x1b,umask=0x20 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1 unc_c_ring_ak_used.ccw uncore cache AK Ring In Use; Counterclockwise event=0x1c,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.cw uncore cache AK Ring In Use; Clockwise event=0x1c,umask=3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down uncore cache AK Ring In Use; Down event=0x1c,umask=0xcc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_vr0_even uncore cache AK Ring In Use; Down and Even on Vring 0 event=0x1c,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0 unc_c_ring_ak_used.down_vr0_odd uncore cache AK Ring In Use; Down and Odd on Vring 0 event=0x1c,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0 unc_c_ring_ak_used.down_vr1_even uncore cache AK Ring In Use; Down and Even on VRing 1 event=0x1c,umask=0x40 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1 unc_c_ring_ak_used.down_vr1_odd uncore cache AK Ring In Use; Down and Odd on VRing 1 event=0x1c,umask=0x80 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1 unc_c_ring_ak_used.up uncore cache AK Ring In Use; Up event=0x1c,umask=0x33 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up_vr0_even uncore cache AK Ring In Use; Up and Even on Vring 0 event=0x1c,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0 unc_c_ring_ak_used.up_vr0_odd uncore cache AK Ring In Use; Up and Odd on Vring 0 event=0x1c,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0 unc_c_ring_ak_used.up_vr1_even uncore cache AK Ring In Use; Up and Even on VRing 1 event=0x1c,umask=0x10 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1 unc_c_ring_ak_used.up_vr1_odd uncore cache AK Ring In Use; Up and Odd on VRing 1 event=0x1c,umask=0x20 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1 unc_c_ring_bl_used.ccw uncore cache BL Ring in Use; Counterclockwise event=0x1d,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.cw uncore cache BL Ring in Use; Clockwise event=0x1d,umask=3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down uncore cache BL Ring in Use; Down event=0x1d,umask=0xcc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_vr0_even uncore cache BL Ring in Use; Down and Even on Vring 0 event=0x1d,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0 unc_c_ring_bl_used.down_vr0_odd uncore cache BL Ring in Use; Down and Odd on Vring 0 event=0x1d,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0 unc_c_ring_bl_used.down_vr1_even uncore cache BL Ring in Use; Down and Even on VRing 1 event=0x1d,umask=0x40 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1 unc_c_ring_bl_used.down_vr1_odd uncore cache BL Ring in Use; Down and Odd on VRing 1 event=0x1d,umask=0x80 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1 unc_c_ring_bl_used.up uncore cache BL Ring in Use; Up event=0x1d,umask=0x33 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up_vr0_even uncore cache BL Ring in Use; Up and Even on Vring 0 event=0x1d,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0 unc_c_ring_bl_used.up_vr0_odd uncore cache BL Ring in Use; Up and Odd on Vring 0 event=0x1d,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0 unc_c_ring_bl_used.up_vr1_even uncore cache BL Ring in Use; Up and Even on VRing 1 event=0x1d,umask=0x10 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1 unc_c_ring_bl_used.up_vr1_odd uncore cache BL Ring in Use; Up and Odd on VRing 1 event=0x1d,umask=0x20 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1 unc_c_ring_bounces.ad_irq uncore cache Number of LLC responses that bounced on the Ring event=5,umask=2 01 unc_c_ring_bounces.ak uncore cache Number of LLC responses that bounced on the Ring.; Acknowledgements to core event=5,umask=4 01 unc_c_ring_bounces.ak_core uncore cache Number of LLC responses that bounced on the Ring.: Acknowledgements to core event=5,umask=2 01 unc_c_ring_bounces.bl uncore cache Number of LLC responses that bounced on the Ring.; Data Responses to core event=5,umask=8 01 unc_c_ring_bounces.bl_core uncore cache Number of LLC responses that bounced on the Ring.: Data Responses to core event=5,umask=4 01 unc_c_ring_bounces.iv_core uncore cache Number of LLC responses that bounced on the Ring.: Snoops of processor's cache event=5,umask=8 01 unc_c_ring_iv_used.any uncore cache IV Ring in Use; Any event=0x1e,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters any polarity unc_c_ring_iv_used.down uncore cache IV Ring in Use; Down event=0x1e,umask=0xcc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Down polarity unc_c_ring_iv_used.up uncore cache IV Ring in Use; Up event=0x1e,umask=0x33 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Up polarity unc_c_ring_sink_starved.ad_ipq uncore cache event=6,umask=2 01 unc_c_ring_sink_starved.ad_irq uncore cache event=6,umask=1 01 unc_c_ring_sink_starved.iv uncore cache event=6,umask=0x10 01 unc_c_ring_src_thrtl uncore cache event=7 01 unc_c_rxr_ext_starved.prq uncore cache Ingress Arbiter Blocking Cycles event=0x12,umask=4 01 IRQ is blocking the ingress queue and causing the starvation unc_c_rxr_inserts.irq_rejected uncore cache Ingress Allocations: IRQ Rejected event=0x13,umask=2 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.vfifo uncore cache Ingress Allocations; VFIFO event=0x13,umask=0x10 01 Counts number of allocations per cycle into the specified Ingress queue.; Counts the number of allocations into the IRQ Ordering FIFO. In JKT, it is necessary to keep IO requests in order. Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other). This event, in conjunction with the Occupancy Accumulator event, can be used to calculate average lifetime in the FIFO. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ unc_c_rxr_ismq_retry.wb_credits uncore cache ISMQ Retries; No WB Credits event=0x33,umask=0x80 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Retries of writes to local memory due to lack of HT WB credits unc_c_rxr_occupancy.irq_rejected uncore cache IRQ Rejected event=0x11,umask=2 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.vfifo uncore cache Ingress Occupancy; VFIFO event=0x11,umask=0x10 01 Counts number of entries in the specified Ingress queue in each cycle.; Accumulates the number of used entries in the IRQ Ordering FIFO in each cycle. In JKT, it is necessary to keep IO requests in order. Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other). This event, in conjunction with the Allocations event, can be used to calculate average lifetime in the FIFO. This event can be used in conjunction with the Not Empty event to calculate average queue occupancy. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ unc_h_bt_bypass uncore cache BT Bypass event=0x52 01 Number of transactions that bypass the BT (fifo) to HT unc_h_bt_cycles_ne.local uncore cache BT Cycles Not Empty: Local event=0x42,umask=1 01 Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT unc_h_bt_cycles_ne.remote uncore cache BT Cycles Not Empty: Remote event=0x42,umask=2 01 Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT unc_h_bt_occupancy.local uncore cache BT Occupancy; Local event=0x43,umask=1 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.reads_local uncore cache BT Occupancy; Reads Local event=0x43,umask=4 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.reads_remote uncore cache BT Occupancy; Reads Remote event=0x43,umask=8 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.remote uncore cache BT Occupancy; Remote event=0x43,umask=2 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.writes_local uncore cache BT Occupancy; Writes Local event=0x43,umask=0x10 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.writes_remote uncore cache BT Occupancy; Writes Remote event=0x43,umask=0x20 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_conflict_cycles.ackcnflts uncore cache Conflict Checks; Acknowledge Conflicts event=0xb,umask=8 01 Count the number of Ackcnflts unc_h_conflict_cycles.cmp_fwds uncore cache Conflict Checks; Cmp Fwds event=0xb,umask=0x10 01 Count the number of Cmp_Fwd. This will give the number of late conflicts unc_h_conflict_cycles.conflict uncore cache Conflict Checks; Conflict Detected event=0xb,umask=2 01 Counts the number of cycles that we are handling conflicts unc_h_conflict_cycles.last uncore cache Conflict Checks; Last in conflict chain event=0xb,umask=4 01 Count every last conflictor in conflict chain. Can be used to compute the average conflict chain length as (#Ackcnflts/#LastConflictor)+1. This can be used to give a feel for the conflict chain lengths while analyzing lock kernels unc_h_directory_lookup.any uncore cache Directory Lookups: Any state event=0xc,umask=0x10 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.snoop_a uncore cache Directory Lookups: Snoop A event=0xc,umask=8 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.snoop_s uncore cache Directory Lookups: Snoop S event=0xc,umask=2 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.state_a uncore cache Directory Lookups: A State event=0xc,umask=0x80 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.state_i uncore cache Directory Lookups: I State event=0xc,umask=0x20 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.state_s uncore cache Directory Lookups: S State event=0xc,umask=0x40 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_update.a2i uncore cache Directory Updates: A2I event=0xd,umask=0x20 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.a2s uncore cache Directory Updates: A2S event=0xd,umask=0x40 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.i2a uncore cache Directory Updates: I2A event=0xd,umask=4 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.i2s uncore cache Directory Updates: I2S event=0xd,umask=2 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.s2a uncore cache Directory Updates: S2A event=0xd,umask=0x10 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.s2i uncore cache Directory Updates: S2I event=0xd,umask=8 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_igr_ad_qpi2_accumulator uncore cache AD QPI Link 2 Credit Accumulator event=0x59 01 Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer unc_h_igr_bl_qpi2_accumulator uncore cache BL QPI Link 2 Credit Accumulator event=0x5a 01 Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer unc_h_igr_credits_ad_qpi2 uncore cache AD QPI Link 2 Credit Accumulator event=0x59 01 Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer unc_h_igr_credits_bl_qpi2 uncore cache BL QPI Link 2 Credit Accumulator event=0x5a 01 Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer unc_h_iodc_conflicts.any uncore cache IODC Conflicts; Any Conflict event=0x57,umask=1 01 unc_h_iodc_conflicts.last uncore cache IODC Conflicts; Last Conflict event=0x57,umask=4 01 unc_h_iodc_conflicts.remote_invi2e_same_rtid uncore cache IODC Conflicts: Remote InvItoE - Same RTID event=0x57,umask=1 01 unc_h_iodc_conflicts.remote_other_same_addr uncore cache IODC Conflicts: Remote (Other) - Same Addr event=0x57,umask=4 01 unc_h_iodc_inserts uncore cache IODC Inserts event=0x56 01 IODC Allocations unc_h_iodc_olen_wbmtoi uncore cache Num IODC 0 Length Writes event=0x58 01 Num IODC 0 Length Writebacks M to I - All of which are dropped unc_h_ring_ad_used.ccw uncore cache HA AD Ring in Use; Counterclockwise event=0x3e,umask=0xcc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.ccw_vr0_even uncore cache HA AD Ring in Use; Counterclockwise and Even on VRing 0 event=0x3e,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ad_used.ccw_vr0_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd on VRing 0 event=0x3e,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ad_used.ccw_vr1_even uncore cache HA AD Ring in Use; Counterclockwise and Even on VRing 1 event=0x3e,umask=0x40 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ad_used.ccw_vr1_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd on VRing 1 event=0x3e,umask=0x80 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_ad_used.cw uncore cache HA AD Ring in Use; Clockwise event=0x3e,umask=0x33 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_vr0_even uncore cache HA AD Ring in Use; Clockwise and Even on VRing 0 event=0x3e,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ad_used.cw_vr0_odd uncore cache HA AD Ring in Use; Clockwise and Odd on VRing 0 event=0x3e,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ad_used.cw_vr1_even uncore cache HA AD Ring in Use; Clockwise and Even on VRing 1 event=0x3e,umask=0x10 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ad_used.cw_vr1_odd uncore cache HA AD Ring in Use; Clockwise and Odd on VRing 1 event=0x3e,umask=0x20 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_ak_used.ccw uncore cache HA AK Ring in Use; Counterclockwise event=0x3f,umask=0xcc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_vr0_even uncore cache HA AK Ring in Use; Counterclockwise and Even on VRing 0 event=0x3f,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ak_used.ccw_vr0_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd on VRing 0 event=0x3f,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ak_used.ccw_vr1_even uncore cache HA AK Ring in Use; Counterclockwise and Even on VRing 1 event=0x3f,umask=0x40 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ak_used.ccw_vr1_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd on VRing 1 event=0x3f,umask=0x80 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_ak_used.cw uncore cache HA AK Ring in Use; Clockwise event=0x3f,umask=0x33 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_vr0_even uncore cache HA AK Ring in Use; Clockwise and Even on VRing 0 event=0x3f,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ak_used.cw_vr0_odd uncore cache HA AK Ring in Use; Clockwise and Odd on VRing 0 event=0x3f,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ak_used.cw_vr1_even uncore cache HA AK Ring in Use; Clockwise and Even on VRing 1 event=0x3f,umask=0x10 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ak_used.cw_vr1_odd uncore cache HA AK Ring in Use; Clockwise and Odd on VRing 1 event=0x3f,umask=0x20 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_bl_used.ccw uncore cache HA BL Ring in Use; Counterclockwise event=0x40,umask=0xcc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_vr0_even uncore cache HA BL Ring in Use; Counterclockwise and Even on VRing 0 event=0x40,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_bl_used.ccw_vr0_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd on VRing 0 event=0x40,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_bl_used.ccw_vr1_even uncore cache HA BL Ring in Use; Counterclockwise and Even on VRing 1 event=0x40,umask=0x40 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_bl_used.ccw_vr1_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd on VRing 1 event=0x40,umask=0x80 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_bl_used.cw uncore cache HA BL Ring in Use; Clockwise event=0x40,umask=0x33 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_vr0_even uncore cache HA BL Ring in Use; Clockwise and Even on VRing 0 event=0x40,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_bl_used.cw_vr0_odd uncore cache HA BL Ring in Use; Clockwise and Odd on VRing 0 event=0x40,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_bl_used.cw_vr1_even uncore cache HA BL Ring in Use; Clockwise and Even on VRing 1 event=0x40,umask=0x10 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_bl_used.cw_vr1_odd uncore cache HA BL Ring in Use; Clockwise and Odd on VRing 1 event=0x40,umask=0x20 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_h_snoop_resp.rspsfwd uncore cache Snoop Responses Received; RspSFwd event=0x21,umask=8 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state unc_h_tracker_cycles_ne uncore cache Tracker Cycles Not Empty event=3 01 Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_txr_ad_occupancy.sched0 uncore cache AD Egress Occupancy; Scheduler 0 event=0x28,umask=1 01 AD Egress Occupancy; Filter for occupancy from scheduler bank 0 unc_h_txr_ad_occupancy.sched1 uncore cache AD Egress Occupancy; Scheduler 1 event=0x28,umask=2 01 AD Egress Occupancy; Filter for occupancy from scheduler bank 1 unc_h_txr_ak.crd_cbo uncore cache Outbound Ring Transactions on AK: CRD Transactions to Cbo event=0xe,umask=2 01 unc_h_txr_ak_occupancy.sched0 uncore cache AK Egress Occupancy; Scheduler 0 event=0x30,umask=1 01 AK Egress Occupancy; Filter for occupancy from scheduler bank 0 unc_h_txr_ak_occupancy.sched1 uncore cache AK Egress Occupancy; Scheduler 1 event=0x30,umask=2 01 AK Egress Occupancy; Filter for occupancy from scheduler bank 1 unc_h_txr_bl_occupancy.all uncore cache BL Egress Occupancy: All event=0x34,umask=3 01 unc_h_txr_bl_occupancy.sched0 uncore cache BL Egress Occupancy; Scheduler 0 event=0x34,umask=1 01 BL Egress Occupancy; Filter for occupancy from scheduler bank 0 unc_h_txr_bl_occupancy.sched1 uncore cache BL Egress Occupancy; Scheduler 1 event=0x34,umask=2 01 BL Egress Occupancy; Filter for occupancy from scheduler bank 1 unc_i_address_match.merge_count uncore interconnect Address Match (Conflict) Count; Conflict Merges event=0x17,umask=2 01 Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When two requests to the same address from the same source are received back to back, it is possible to merge the two of them together unc_i_address_match.stall_count uncore interconnect Address Match (Conflict) Count; Conflict Stalls event=0x17,umask=1 01 Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When it is not possible to merge two conflicting requests, a stall event occurs. This is bad for performance unc_i_cache_ack_pending_occupancy.any uncore interconnect Write Ack Pending Occupancy; Any Source event=0x14,umask=1 01 Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time unc_i_cache_ack_pending_occupancy.source uncore interconnect Write Ack Pending Occupancy; Select Source event=0x14,umask=2 01 Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks all requests from any source port unc_i_cache_own_occupancy.any uncore interconnect Outstanding Write Ownership Occupancy; Any Source event=0x13,umask=1 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks all requests from any source port unc_i_cache_own_occupancy.source uncore interconnect Outstanding Write Ownership Occupancy; Select Source event=0x13,umask=2 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time unc_i_cache_read_occupancy.any uncore interconnect Outstanding Read Occupancy; Any Source event=0x10,umask=1 01 Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks all requests from any source port unc_i_cache_read_occupancy.source uncore interconnect Outstanding Read Occupancy; Select Source event=0x10,umask=2 01 Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time unc_i_cache_write_occupancy.any uncore interconnect Outstanding Write Occupancy; Any Source event=0x11,umask=1 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks all requests from any source port unc_i_cache_write_occupancy.source uncore interconnect Outstanding Write Occupancy; Select Source event=0x11,umask=2 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time unc_i_rxr_ak_cycles_full uncore interconnect event=0xb 01 Counts the number of cycles when the AK Ingress is full. This queue is where the IRP receives responses from R2PCIe (the ring) unc_i_rxr_ak_occupancy uncore interconnect event=0xc 01 Accumulates the occupancy of the AK Ingress in each cycles. This queue is where the IRP receives responses from R2PCIe (the ring) unc_i_rxr_bl_drs_cycles_full uncore interconnect event=4 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_drs_occupancy uncore interconnect event=7 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_cycles_full uncore interconnect event=5 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_occupancy uncore interconnect event=8 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_cycles_full uncore interconnect event=6 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_occupancy uncore interconnect event=9 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_tickles.lost_ownership uncore interconnect Tickle Count; Ownership Lost event=0x16,umask=1 01 Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of requests that lost ownership as a result of a tickle. When a tickle comes in, if the request is not at the head of the queue in the switch, then that request as well as any requests behind it in the switch queue will lose ownership and have to re-acquire it later when they get to the head of the queue. This will therefore track the number of requests that lost ownership and not just the number of tickles unc_i_tickles.top_of_queue uncore interconnect Tickle Count; Data Returned event=0x16,umask=2 01 Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of cases when a tickle was received but the requests was at the head of the queue in the switch. In this case, data is returned rather than releasing ownership unc_i_transactions.pd_prefetches uncore interconnect Inbound Transaction Count: Read Prefetches event=0x15,umask=4 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_i_transactions.rd_prefetches uncore interconnect Inbound Transaction Count; Read Prefetches event=0x15,umask=4 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x15,umask=1 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches) unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x15,umask=2 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry unc_i_write_ordering_stall_cycles uncore interconnect Write Ordering Stalls event=0x1a 01 Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized unc_q_clockticks uncore interconnect Number of qfclks event=0x14 01 Counts the number of clocks in the QPI LL. This clock runs at 1/8th the GT/s speed of the QPI link. For example, a 8GT/s link will have qfclk or 1GHz. JKT does not support dynamic link speeds, so this frequency is fixed unc_q_match_mask uncore interconnect event=0x38 01 unc_q_message.drs.anydatac uncore interconnect event=0x38 01 unc_q_message.drs.anyresp uncore interconnect event=0x38 01 unc_q_message.drs.anyresp11flits uncore interconnect event=0x38 01 unc_q_message.drs.anyresp9flits uncore interconnect event=0x38 01 unc_q_message.drs.datac_e uncore interconnect event=0x38 01 unc_q_message.drs.datac_e_cmp uncore interconnect event=0x38 01 unc_q_message.drs.datac_e_frcackcnflt uncore interconnect event=0x38 01 unc_q_message.drs.datac_f uncore interconnect event=0x38 01 unc_q_message.drs.datac_f_cmp uncore interconnect event=0x38 01 unc_q_message.drs.datac_f_frcackcnflt uncore interconnect event=0x38 01 unc_q_message.drs.datac_m uncore interconnect event=0x38 01 unc_q_message.drs.wbedata uncore interconnect event=0x38 01 unc_q_message.drs.wbidata uncore interconnect event=0x38 01 unc_q_message.drs.wbsdata uncore interconnect event=0x38 01 unc_q_message.hom.anyreq uncore interconnect event=0x38 01 unc_q_message.hom.anyresp uncore interconnect event=0x38 01 unc_q_message.hom.respfwd uncore interconnect event=0x38 01 unc_q_message.hom.respfwdi uncore interconnect event=0x38 01 unc_q_message.hom.respfwdiwb uncore interconnect event=0x38 01 unc_q_message.hom.respfwds uncore interconnect event=0x38 01 unc_q_message.hom.respfwdswb uncore interconnect event=0x38 01 unc_q_message.hom.respiwb uncore interconnect event=0x38 01 unc_q_message.hom.respswb uncore interconnect event=0x38 01 unc_q_message.ncb.anyint uncore interconnect event=0x38 01 unc_q_message.ncb.anymsg uncore interconnect event=0x38 01 unc_q_message.ncb.anymsg11flits uncore interconnect event=0x38 01 unc_q_message.ncb.anymsg9flits uncore interconnect event=0x38 01 unc_q_message.ncs.anymsg1or2flits uncore interconnect event=0x38 01 unc_q_message.ncs.anymsg3flits uncore interconnect event=0x38 01 unc_q_message.ncs.ncrd uncore interconnect event=0x38 01 unc_q_message.ndr.anycmp uncore interconnect event=0x38 01 unc_q_message.snp.anysnp uncore interconnect event=0x38 01 unc_q_rxl_flits_g0.data uncore interconnect Flits Received - Group 0; Data Tx Flits event=1,umask=2 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits received over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets unc_q_rxl_flits_g0.non_data uncore interconnect Flits Received - Group 0; Non-Data protocol Tx Flits event=1,umask=4 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits received across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets unc_q_rxl_inserts_drs uncore interconnect Rx Flit Buffer Allocations - DRS event=9 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits unc_q_rxl_inserts_hom uncore interconnect Rx Flit Buffer Allocations - HOM event=0xc 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits unc_q_rxl_inserts_ncb uncore interconnect Rx Flit Buffer Allocations - NCB event=0xa 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits unc_q_rxl_inserts_ncs uncore interconnect Rx Flit Buffer Allocations - NCS event=0xb 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits unc_q_rxl_inserts_ndr uncore interconnect Rx Flit Buffer Allocations - NDR event=0xe 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits unc_q_rxl_inserts_snp uncore interconnect Rx Flit Buffer Allocations - SNP event=0xd 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits unc_q_rxl_occupancy_drs uncore interconnect RxQ Occupancy - DRS event=0x15 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only unc_q_rxl_occupancy_hom uncore interconnect RxQ Occupancy - HOM event=0x18 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only unc_q_rxl_occupancy_ncb uncore interconnect RxQ Occupancy - NCB event=0x16 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only unc_q_rxl_occupancy_ncs uncore interconnect RxQ Occupancy - NCS event=0x17 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only unc_q_rxl_occupancy_ndr uncore interconnect RxQ Occupancy - NDR event=0x1a 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only unc_q_rxl_occupancy_snp uncore interconnect RxQ Occupancy - SNP event=0x19 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only unc_q_txr_ak_ndr_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN0 event=0x29,umask=1 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN1 event=0x29,umask=2 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN0 event=0x25,umask=1 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN1 event=0x25,umask=2 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress unc_r3_c_hi_ad_credits_empty.cbo10 uncore interconnect CBox AD Credits Empty event=0x2c,umask=4 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10 unc_r3_c_hi_ad_credits_empty.cbo11 uncore interconnect CBox AD Credits Empty event=0x2c,umask=8 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11 unc_r3_c_hi_ad_credits_empty.cbo12 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x10 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12 unc_r3_c_hi_ad_credits_empty.cbo13 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x20 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13 unc_r3_c_hi_ad_credits_empty.cbo14 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x40 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16 unc_r3_c_hi_ad_credits_empty.cbo8 uncore interconnect CBox AD Credits Empty event=0x2c,umask=1 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8 unc_r3_c_hi_ad_credits_empty.cbo9 uncore interconnect CBox AD Credits Empty event=0x2c,umask=2 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9 unc_r3_c_lo_ad_credits_empty.cbo0 uncore interconnect CBox AD Credits Empty event=0x2b,umask=1 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0 unc_r3_c_lo_ad_credits_empty.cbo1 uncore interconnect CBox AD Credits Empty event=0x2b,umask=2 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1 unc_r3_c_lo_ad_credits_empty.cbo2 uncore interconnect CBox AD Credits Empty event=0x2b,umask=4 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2 unc_r3_c_lo_ad_credits_empty.cbo3 uncore interconnect CBox AD Credits Empty event=0x2b,umask=8 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3 unc_r3_c_lo_ad_credits_empty.cbo4 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x10 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4 unc_r3_c_lo_ad_credits_empty.cbo5 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x20 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5 unc_r3_c_lo_ad_credits_empty.cbo6 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x40 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6 unc_r3_c_lo_ad_credits_empty.cbo7 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x80 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7 unc_r3_ha_r2_bl_credits_empty.ha0 uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=1 01 No credits available to send to either HA or R2 on the BL Ring; HA0 unc_r3_ha_r2_bl_credits_empty.ha1 uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=2 01 No credits available to send to either HA or R2 on the BL Ring; HA1 unc_r3_ha_r2_bl_credits_empty.r2_ncb uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=4 01 No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages unc_r3_ha_r2_bl_credits_empty.r2_ncs uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=8 01 No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages unc_r3_qpi0_ad_credits_empty.vn0_hom uncore interconnect QPI0 AD Credits Empty event=0x29,umask=2 01 No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages unc_r3_qpi0_ad_credits_empty.vn0_ndr uncore interconnect QPI0 AD Credits Empty event=0x29,umask=8 01 No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages unc_r3_qpi0_ad_credits_empty.vn0_snp uncore interconnect QPI0 AD Credits Empty event=0x29,umask=4 01 No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages unc_r3_qpi0_ad_credits_empty.vn1_hom uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x10 01 No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages unc_r3_qpi0_ad_credits_empty.vn1_ndr uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x40 01 No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages unc_r3_qpi0_ad_credits_empty.vn1_snp uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x20 01 No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages unc_r3_qpi0_ad_credits_empty.vna uncore interconnect QPI0 AD Credits Empty event=0x29,umask=1 01 No credits available to send to QPI0 on the AD Ring; VNA unc_r3_qpi0_bl_credits_empty.vn0_hom uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=2 01 No credits available to send to QPI0 on the BL Ring; VN0 HOM Messages unc_r3_qpi0_bl_credits_empty.vn0_ndr uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=8 01 No credits available to send to QPI0 on the BL Ring; VN0 NDR Messages unc_r3_qpi0_bl_credits_empty.vn0_snp uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=4 01 No credits available to send to QPI0 on the BL Ring; VN0 SNP Messages unc_r3_qpi0_bl_credits_empty.vn1_hom uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x10 01 No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages unc_r3_qpi0_bl_credits_empty.vn1_ndr uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x40 01 No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages unc_r3_qpi0_bl_credits_empty.vn1_snp uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x20 01 No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages unc_r3_qpi0_bl_credits_empty.vna uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=1 01 No credits available to send to QPI0 on the BL Ring; VNA unc_r3_qpi1_ad_credits_empty.vn0_hom uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=2 01 No credits available to send to QPI1 on the AD Ring; VN0 HOM Messages unc_r3_qpi1_ad_credits_empty.vn0_ndr uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=8 01 No credits available to send to QPI1 on the AD Ring; VN0 NDR Messages unc_r3_qpi1_ad_credits_empty.vn0_snp uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=4 01 No credits available to send to QPI1 on the AD Ring; VN0 SNP Messages unc_r3_qpi1_ad_credits_empty.vn1_hom uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x10 01 No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages unc_r3_qpi1_ad_credits_empty.vn1_ndr uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x40 01 No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages unc_r3_qpi1_ad_credits_empty.vn1_snp uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x20 01 No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages unc_r3_qpi1_ad_credits_empty.vna uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=1 01 No credits available to send to QPI1 on the AD Ring; VNA unc_r3_qpi1_bl_credits_empty.vn0_hom uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=2 01 No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages unc_r3_qpi1_bl_credits_empty.vn0_ndr uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=8 01 No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages unc_r3_qpi1_bl_credits_empty.vn0_snp uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=4 01 No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages unc_r3_qpi1_bl_credits_empty.vn1_hom uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x10 01 No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages unc_r3_qpi1_bl_credits_empty.vn1_ndr uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x40 01 No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages unc_r3_qpi1_bl_credits_empty.vn1_snp uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x20 01 No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages unc_r3_qpi1_bl_credits_empty.vna uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=1 01 No credits available to send to QPI1 on the BL Ring; VNA unc_r3_ring_ad_used.ccw uncore interconnect R3 AD Ring in Use; Counterclockwise event=7,umask=0xcc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw_vr0_even uncore interconnect R3 AD Ring in Use; Counterclockwise and Even on VRing 0 event=7,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ad_used.ccw_vr0_odd uncore interconnect R3 AD Ring in Use; Counterclockwise and Odd on VRing 0 event=7,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_ad_used.cw uncore interconnect R3 AD Ring in Use; Clockwise event=7,umask=0x33 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_vr0_even uncore interconnect R3 AD Ring in Use; Clockwise and Even on VRing 0 event=7,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ad_used.cw_vr0_odd uncore interconnect R3 AD Ring in Use; Clockwise and Odd on VRing 0 event=7,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.ccw uncore interconnect R3 AK Ring in Use; Counterclockwise event=8,umask=0xcc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw_vr0_even uncore interconnect R3 AK Ring in Use; Counterclockwise and Even on VRing 0 event=8,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.ccw_vr0_odd uncore interconnect R3 AK Ring in Use; Counterclockwise and Odd on VRing 0 event=8,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.cw uncore interconnect R3 AK Ring in Use; Clockwise event=8,umask=0x33 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.cw_vr0_even uncore interconnect R3 AK Ring in Use; Clockwise and Even on VRing 0 event=8,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.cw_vr0_odd uncore interconnect R3 AK Ring in Use; Clockwise and Odd on VRing 0 event=8,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.ccw uncore interconnect R3 BL Ring in Use; Counterclockwise event=9,umask=0xcc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw_vr0_even uncore interconnect R3 BL Ring in Use; Counterclockwise and Even on VRing 0 event=9,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.ccw_vr0_odd uncore interconnect R3 BL Ring in Use; Counterclockwise and Odd on VRing 0 event=9,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.cw uncore interconnect R3 BL Ring in Use; Clockwise event=9,umask=0x33 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_vr0_even uncore interconnect R3 BL Ring in Use; Clockwise and Even on VRing 0 event=9,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.cw_vr0_odd uncore interconnect R3 BL Ring in Use; Clockwise and Odd on VRing 0 event=9,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_iv_used.any uncore interconnect R2 IV Ring in Use; Any event=0xa,umask=0xff 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity unc_r3_ring_iv_used.ccw uncore interconnect R2 IV Ring in Use; Counterclockwise event=0xa,umask=0xcc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity unc_r3_ring_iv_used.cw uncore interconnect R2 IV Ring in Use; Clockwise event=0xa,umask=0x33 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity unc_r3_rxr_ad_bypassed uncore interconnect AD Ingress Bypassed event=0x12 01 Counts the number of times when the AD Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain unc_r3_rxr_bypassed.ad uncore interconnect Ingress Bypassed event=0x12,umask=1 01 Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain unc_r3_rxr_occupancy.drs uncore interconnect Ingress Occupancy Accumulator; DRS event=0x13,umask=8 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue unc_r3_rxr_occupancy.hom uncore interconnect Ingress Occupancy Accumulator; HOM event=0x13,umask=1 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue unc_r3_rxr_occupancy.ncb uncore interconnect Ingress Occupancy Accumulator; NCB event=0x13,umask=0x10 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue unc_r3_rxr_occupancy.ncs uncore interconnect Ingress Occupancy Accumulator; NCS event=0x13,umask=0x20 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue unc_r3_rxr_occupancy.ndr uncore interconnect Ingress Occupancy Accumulator; NDR event=0x13,umask=4 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue unc_r3_rxr_occupancy.snp uncore interconnect Ingress Occupancy Accumulator; SNP event=0x13,umask=2 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue unc_r3_txr_nack_ccw.ad uncore interconnect Egress NACK; AK CCW event=0x28,umask=1 01 BL CounterClockwise Egress Queue unc_r3_txr_nack_ccw.ak uncore interconnect Egress NACK; BL CW event=0x28,umask=2 01 AD Clockwise Egress Queue unc_r3_txr_nack_ccw.bl uncore interconnect Egress NACK; BL CCW event=0x28,umask=4 01 AD CounterClockwise Egress Queue unc_r3_txr_nack_cw.ad uncore interconnect Egress NACK; AD CW event=0x26,umask=1 01 AD Clockwise Egress Queue unc_r3_txr_nack_cw.ak uncore interconnect Egress NACK; AD CCW event=0x26,umask=2 01 AD CounterClockwise Egress Queue unc_r3_txr_nack_cw.bl uncore interconnect Egress NACK; AK CW event=0x26,umask=4 01 BL Clockwise Egress Queue unc_r3_vna_credits_acquired uncore interconnect VNA credit Acquisitions event=0x33 01 Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event unc_r3_vna_credit_cycles_out uncore interconnect Cycles with no VNA credits available event=0x31 01 Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel. Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit. Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth unc_r3_vna_credit_cycles_used uncore interconnect Cycles with 1 or more VNA credits in use event=0x32 01 Number of QPI uclk cycles with one or more VNA credits in use. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits unc_u_clockticks uncore interconnect event=0 01 unc_u_event_msg.int_prio uncore interconnect VLW Received event=0x42,umask=0x10 01 Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_event_msg.ipi_rcvd uncore interconnect VLW Received event=0x42,umask=4 01 Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_event_msg.msi_rcvd uncore interconnect VLW Received event=0x42,umask=2 01 Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_event_msg.vlw_rcvd uncore interconnect VLW Received event=0x42,umask=1 01 Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_racu_requests uncore interconnect RACU Request event=0x46 01 unc_r2_iio_credits_reject.drs uncore io R2PCIe IIO Failed to Acquire a Credit; DRS event=0x34,umask=8 01 Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class unc_r2_ring_ad_used.ccw uncore io R2 AD Ring in Use; Counterclockwise event=7,umask=0xcc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw_vr0_even uncore io R2 AD Ring in Use; Counterclockwise and Even on VRing 0 event=7,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.ccw_vr0_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd on VRing 0 event=7,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.ccw_vr1_even uncore io R2 AD Ring in Use; Counterclockwise and Even on VRing 1 event=7,umask=0x40 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ad_used.ccw_vr1_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd on VRing 1 event=7,umask=0x80 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_ad_used.cw uncore io R2 AD Ring in Use; Clockwise event=7,umask=0x33 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_vr0_even uncore io R2 AD Ring in Use; Clockwise and Even on VRing 0 event=7,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.cw_vr0_odd uncore io R2 AD Ring in Use; Clockwise and Odd on VRing 0 event=7,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.cw_vr1_even uncore io R2 AD Ring in Use; Clockwise and Even on VRing 1 event=7,umask=0x10 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ad_used.cw_vr1_odd uncore io R2 AD Ring in Use; Clockwise and Odd on VRing 1 event=7,umask=0x20 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.ccw uncore io R2 AK Ring in Use; Counterclockwise event=8,umask=0xcc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_vr0_even uncore io R2 AK Ring in Use; Counterclockwise and Even on VRing 0 event=8,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.ccw_vr0_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd on VRing 0 event=8,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.ccw_vr1_even uncore io R2 AK Ring in Use; Counterclockwise and Even on VRing 1 event=8,umask=0x40 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.ccw_vr1_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd on VRing 1 event=8,umask=0x80 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.cw uncore io R2 AK Ring in Use; Clockwise event=8,umask=0x33 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_vr0_even uncore io R2 AK Ring in Use; Clockwise and Even on VRing 0 event=8,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.cw_vr0_odd uncore io R2 AK Ring in Use; Clockwise and Odd on VRing 0 event=8,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.cw_vr1_even uncore io R2 AK Ring in Use; Clockwise and Even on VRing 1 event=8,umask=0x10 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.cw_vr1_odd uncore io R2 AK Ring in Use; Clockwise and Odd on VRing 1 event=8,umask=0x20 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.ccw uncore io R2 BL Ring in Use; Counterclockwise event=9,umask=0xcc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_vr0_even uncore io R2 BL Ring in Use; Counterclockwise and Even on VRing 0 event=9,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.ccw_vr0_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd on VRing 0 event=9,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.ccw_vr1_even uncore io R2 BL Ring in Use; Counterclockwise and Even on VRing 1 event=9,umask=0x40 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.ccw_vr1_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd on VRing 1 event=9,umask=0x80 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.cw uncore io R2 BL Ring in Use; Clockwise event=9,umask=0x33 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_vr0_even uncore io R2 BL Ring in Use; Clockwise and Even on VRing 0 event=9,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.cw_vr0_odd uncore io R2 BL Ring in Use; Clockwise and Odd on VRing 0 event=9,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.cw_vr1_even uncore io R2 BL Ring in Use; Clockwise and Even on VRing 1 event=9,umask=0x10 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.cw_vr1_odd uncore io R2 BL Ring in Use; Clockwise and Odd on VRing 1 event=9,umask=0x20 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_iv_used.any uncore io R2 IV Ring in Use; Any event=0xa,umask=0xff 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity unc_r2_ring_iv_used.ccw uncore io R2 IV Ring in Use; Counterclockwise event=0xa,umask=0xcc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity unc_r2_ring_iv_used.cw uncore io R2 IV Ring in Use; Clockwise event=0xa,umask=0x33 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity unc_r2_rxr_ak_bounces uncore io AK Ingress Bounced event=0x12 01 Counts the number of times when a request destined for the AK ingress bounced unc_r2_rxr_ak_bounces.ccw uncore io AK Ingress Bounced; Counterclockwise event=0x12,umask=2 01 Counts the number of times when a request destined for the AK ingress bounced unc_r2_rxr_ak_bounces.cw uncore io AK Ingress Bounced; Clockwise event=0x12,umask=1 01 Counts the number of times when a request destined for the AK ingress bounced unc_r2_txr_nack_ccw.ad uncore io Egress CCW NACK; AD CCW event=0x28,umask=1 01 AD CounterClockwise Egress Queue unc_r2_txr_nack_ccw.ak uncore io Egress CCW NACK; AK CCW event=0x28,umask=2 01 AK CounterClockwise Egress Queue unc_r2_txr_nack_ccw.bl uncore io Egress CCW NACK; BL CCW event=0x28,umask=4 01 BL CounterClockwise Egress Queue unc_r2_txr_nack_cw.ad uncore io Egress CW NACK; AD CW event=0x26,umask=1 01 AD Clockwise Egress Queue unc_r2_txr_nack_cw.ak uncore io Egress CW NACK; AK CW event=0x26,umask=2 01 AK Clockwise Egress Queue unc_r2_txr_nack_cw.bl uncore io Egress CW NACK; BL CW event=0x26,umask=4 01 BL Clockwise Egress Queue unc_m_power_pcu_throttling uncore memory event=0x42 01 unc_m_rd_cas_rank0.bank0 uncore memory RD_CAS Access to Rank 0; Bank 0 event=0xb0,umask=1 01 unc_m_rd_cas_rank0.bank1 uncore memory RD_CAS Access to Rank 0; Bank 1 event=0xb0,umask=2 01 unc_m_rd_cas_rank0.bank2 uncore memory RD_CAS Access to Rank 0; Bank 2 event=0xb0,umask=4 01 unc_m_rd_cas_rank0.bank3 uncore memory RD_CAS Access to Rank 0; Bank 3 event=0xb0,umask=8 01 unc_m_rd_cas_rank0.bank4 uncore memory RD_CAS Access to Rank 0; Bank 4 event=0xb0,umask=0x10 01 unc_m_rd_cas_rank0.bank5 uncore memory RD_CAS Access to Rank 0; Bank 5 event=0xb0,umask=0x20 01 unc_m_rd_cas_rank0.bank6 uncore memory RD_CAS Access to Rank 0; Bank 6 event=0xb0,umask=0x40 01 unc_m_rd_cas_rank0.bank7 uncore memory RD_CAS Access to Rank 0; Bank 7 event=0xb0,umask=0x80 01 unc_m_rd_cas_rank1.bank0 uncore memory RD_CAS Access to Rank 1; Bank 0 event=0xb1,umask=1 01 unc_m_rd_cas_rank1.bank1 uncore memory RD_CAS Access to Rank 1; Bank 1 event=0xb1,umask=2 01 unc_m_rd_cas_rank1.bank2 uncore memory RD_CAS Access to Rank 1; Bank 2 event=0xb1,umask=4 01 unc_m_rd_cas_rank1.bank3 uncore memory RD_CAS Access to Rank 1; Bank 3 event=0xb1,umask=8 01 unc_m_rd_cas_rank1.bank4 uncore memory RD_CAS Access to Rank 1; Bank 4 event=0xb1,umask=0x10 01 unc_m_rd_cas_rank1.bank5 uncore memory RD_CAS Access to Rank 1; Bank 5 event=0xb1,umask=0x20 01 unc_m_rd_cas_rank1.bank6 uncore memory RD_CAS Access to Rank 1; Bank 6 event=0xb1,umask=0x40 01 unc_m_rd_cas_rank1.bank7 uncore memory RD_CAS Access to Rank 1; Bank 7 event=0xb1,umask=0x80 01 unc_m_rd_cas_rank2.bank0 uncore memory RD_CAS Access to Rank 2; Bank 0 event=0xb2,umask=1 01 unc_m_rd_cas_rank2.bank1 uncore memory RD_CAS Access to Rank 2; Bank 1 event=0xb2,umask=2 01 unc_m_rd_cas_rank2.bank2 uncore memory RD_CAS Access to Rank 2; Bank 2 event=0xb2,umask=4 01 unc_m_rd_cas_rank2.bank3 uncore memory RD_CAS Access to Rank 2; Bank 3 event=0xb2,umask=8 01 unc_m_rd_cas_rank2.bank4 uncore memory RD_CAS Access to Rank 2; Bank 4 event=0xb2,umask=0x10 01 unc_m_rd_cas_rank2.bank5 uncore memory RD_CAS Access to Rank 2; Bank 5 event=0xb2,umask=0x20 01 unc_m_rd_cas_rank2.bank6 uncore memory RD_CAS Access to Rank 2; Bank 6 event=0xb2,umask=0x40 01 unc_m_rd_cas_rank2.bank7 uncore memory RD_CAS Access to Rank 2; Bank 7 event=0xb2,umask=0x80 01 unc_m_rd_cas_rank3.bank0 uncore memory RD_CAS Access to Rank 3; Bank 0 event=0xb3,umask=1 01 unc_m_rd_cas_rank3.bank1 uncore memory RD_CAS Access to Rank 3; Bank 1 event=0xb3,umask=2 01 unc_m_rd_cas_rank3.bank2 uncore memory RD_CAS Access to Rank 3; Bank 2 event=0xb3,umask=4 01 unc_m_rd_cas_rank3.bank3 uncore memory RD_CAS Access to Rank 3; Bank 3 event=0xb3,umask=8 01 unc_m_rd_cas_rank3.bank4 uncore memory RD_CAS Access to Rank 3; Bank 4 event=0xb3,umask=0x10 01 unc_m_rd_cas_rank3.bank5 uncore memory RD_CAS Access to Rank 3; Bank 5 event=0xb3,umask=0x20 01 unc_m_rd_cas_rank3.bank6 uncore memory RD_CAS Access to Rank 3; Bank 6 event=0xb3,umask=0x40 01 unc_m_rd_cas_rank3.bank7 uncore memory RD_CAS Access to Rank 3; Bank 7 event=0xb3,umask=0x80 01 unc_m_rd_cas_rank4.bank0 uncore memory RD_CAS Access to Rank 4; Bank 0 event=0xb4,umask=1 01 unc_m_rd_cas_rank4.bank1 uncore memory RD_CAS Access to Rank 4; Bank 1 event=0xb4,umask=2 01 unc_m_rd_cas_rank4.bank2 uncore memory RD_CAS Access to Rank 4; Bank 2 event=0xb4,umask=4 01 unc_m_rd_cas_rank4.bank3 uncore memory RD_CAS Access to Rank 4; Bank 3 event=0xb4,umask=8 01 unc_m_rd_cas_rank4.bank4 uncore memory RD_CAS Access to Rank 4; Bank 4 event=0xb4,umask=0x10 01 unc_m_rd_cas_rank4.bank5 uncore memory RD_CAS Access to Rank 4; Bank 5 event=0xb4,umask=0x20 01 unc_m_rd_cas_rank4.bank6 uncore memory RD_CAS Access to Rank 4; Bank 6 event=0xb4,umask=0x40 01 unc_m_rd_cas_rank4.bank7 uncore memory RD_CAS Access to Rank 4; Bank 7 event=0xb4,umask=0x80 01 unc_m_rd_cas_rank5.bank0 uncore memory RD_CAS Access to Rank 5; Bank 0 event=0xb5,umask=1 01 unc_m_rd_cas_rank5.bank1 uncore memory RD_CAS Access to Rank 5; Bank 1 event=0xb5,umask=2 01 unc_m_rd_cas_rank5.bank2 uncore memory RD_CAS Access to Rank 5; Bank 2 event=0xb5,umask=4 01 unc_m_rd_cas_rank5.bank3 uncore memory RD_CAS Access to Rank 5; Bank 3 event=0xb5,umask=8 01 unc_m_rd_cas_rank5.bank4 uncore memory RD_CAS Access to Rank 5; Bank 4 event=0xb5,umask=0x10 01 unc_m_rd_cas_rank5.bank5 uncore memory RD_CAS Access to Rank 5; Bank 5 event=0xb5,umask=0x20 01 unc_m_rd_cas_rank5.bank6 uncore memory RD_CAS Access to Rank 5; Bank 6 event=0xb5,umask=0x40 01 unc_m_rd_cas_rank5.bank7 uncore memory RD_CAS Access to Rank 5; Bank 7 event=0xb5,umask=0x80 01 unc_m_rd_cas_rank6.bank0 uncore memory RD_CAS Access to Rank 6; Bank 0 event=0xb6,umask=1 01 unc_m_rd_cas_rank6.bank1 uncore memory RD_CAS Access to Rank 6; Bank 1 event=0xb6,umask=2 01 unc_m_rd_cas_rank6.bank2 uncore memory RD_CAS Access to Rank 6; Bank 2 event=0xb6,umask=4 01 unc_m_rd_cas_rank6.bank3 uncore memory RD_CAS Access to Rank 6; Bank 3 event=0xb6,umask=8 01 unc_m_rd_cas_rank6.bank4 uncore memory RD_CAS Access to Rank 6; Bank 4 event=0xb6,umask=0x10 01 unc_m_rd_cas_rank6.bank5 uncore memory RD_CAS Access to Rank 6; Bank 5 event=0xb6,umask=0x20 01 unc_m_rd_cas_rank6.bank6 uncore memory RD_CAS Access to Rank 6; Bank 6 event=0xb6,umask=0x40 01 unc_m_rd_cas_rank6.bank7 uncore memory RD_CAS Access to Rank 6; Bank 7 event=0xb6,umask=0x80 01 unc_m_rd_cas_rank7.bank0 uncore memory RD_CAS Access to Rank 7; Bank 0 event=0xb7,umask=1 01 unc_m_rd_cas_rank7.bank1 uncore memory RD_CAS Access to Rank 7; Bank 1 event=0xb7,umask=2 01 unc_m_rd_cas_rank7.bank2 uncore memory RD_CAS Access to Rank 7; Bank 2 event=0xb7,umask=4 01 unc_m_rd_cas_rank7.bank3 uncore memory RD_CAS Access to Rank 7; Bank 3 event=0xb7,umask=8 01 unc_m_rd_cas_rank7.bank4 uncore memory RD_CAS Access to Rank 7; Bank 4 event=0xb7,umask=0x10 01 unc_m_rd_cas_rank7.bank5 uncore memory RD_CAS Access to Rank 7; Bank 5 event=0xb7,umask=0x20 01 unc_m_rd_cas_rank7.bank6 uncore memory RD_CAS Access to Rank 7; Bank 6 event=0xb7,umask=0x40 01 unc_m_rd_cas_rank7.bank7 uncore memory RD_CAS Access to Rank 7; Bank 7 event=0xb7,umask=0x80 01 unc_m_wpq_inserts uncore memory Write Pending Queue Allocations event=0x20 01 Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_m_wr_cas_rank0.bank0 uncore memory WR_CAS Access to Rank 0; Bank 0 event=0xb8,umask=1 01 unc_m_wr_cas_rank0.bank1 uncore memory WR_CAS Access to Rank 0; Bank 1 event=0xb8,umask=2 01 unc_m_wr_cas_rank0.bank2 uncore memory WR_CAS Access to Rank 0; Bank 2 event=0xb8,umask=4 01 unc_m_wr_cas_rank0.bank3 uncore memory WR_CAS Access to Rank 0; Bank 3 event=0xb8,umask=8 01 unc_m_wr_cas_rank0.bank4 uncore memory WR_CAS Access to Rank 0; Bank 4 event=0xb8,umask=0x10 01 unc_m_wr_cas_rank0.bank5 uncore memory WR_CAS Access to Rank 0; Bank 5 event=0xb8,umask=0x20 01 unc_m_wr_cas_rank0.bank6 uncore memory WR_CAS Access to Rank 0; Bank 6 event=0xb8,umask=0x40 01 unc_m_wr_cas_rank0.bank7 uncore memory WR_CAS Access to Rank 0; Bank 7 event=0xb8,umask=0x80 01 unc_m_wr_cas_rank1.bank0 uncore memory WR_CAS Access to Rank 1; Bank 0 event=0xb9,umask=1 01 unc_m_wr_cas_rank1.bank1 uncore memory WR_CAS Access to Rank 1; Bank 1 event=0xb9,umask=2 01 unc_m_wr_cas_rank1.bank2 uncore memory WR_CAS Access to Rank 1; Bank 2 event=0xb9,umask=4 01 unc_m_wr_cas_rank1.bank3 uncore memory WR_CAS Access to Rank 1; Bank 3 event=0xb9,umask=8 01 unc_m_wr_cas_rank1.bank4 uncore memory WR_CAS Access to Rank 1; Bank 4 event=0xb9,umask=0x10 01 unc_m_wr_cas_rank1.bank5 uncore memory WR_CAS Access to Rank 1; Bank 5 event=0xb9,umask=0x20 01 unc_m_wr_cas_rank1.bank6 uncore memory WR_CAS Access to Rank 1; Bank 6 event=0xb9,umask=0x40 01 unc_m_wr_cas_rank1.bank7 uncore memory WR_CAS Access to Rank 1; Bank 7 event=0xb9,umask=0x80 01 unc_m_wr_cas_rank2.bank0 uncore memory WR_CAS Access to Rank 2; Bank 0 event=0xba,umask=1 01 unc_m_wr_cas_rank2.bank1 uncore memory WR_CAS Access to Rank 2; Bank 1 event=0xba,umask=2 01 unc_m_wr_cas_rank2.bank2 uncore memory WR_CAS Access to Rank 2; Bank 2 event=0xba,umask=4 01 unc_m_wr_cas_rank2.bank3 uncore memory WR_CAS Access to Rank 2; Bank 3 event=0xba,umask=8 01 unc_m_wr_cas_rank2.bank4 uncore memory WR_CAS Access to Rank 2; Bank 4 event=0xba,umask=0x10 01 unc_m_wr_cas_rank2.bank5 uncore memory WR_CAS Access to Rank 2; Bank 5 event=0xba,umask=0x20 01 unc_m_wr_cas_rank2.bank6 uncore memory WR_CAS Access to Rank 2; Bank 6 event=0xba,umask=0x40 01 unc_m_wr_cas_rank2.bank7 uncore memory WR_CAS Access to Rank 2; Bank 7 event=0xba,umask=0x80 01 unc_m_wr_cas_rank3.bank0 uncore memory WR_CAS Access to Rank 3; Bank 0 event=0xbb,umask=1 01 unc_m_wr_cas_rank3.bank1 uncore memory WR_CAS Access to Rank 3; Bank 1 event=0xbb,umask=2 01 unc_m_wr_cas_rank3.bank2 uncore memory WR_CAS Access to Rank 3; Bank 2 event=0xbb,umask=4 01 unc_m_wr_cas_rank3.bank3 uncore memory WR_CAS Access to Rank 3; Bank 3 event=0xbb,umask=8 01 unc_m_wr_cas_rank3.bank4 uncore memory WR_CAS Access to Rank 3; Bank 4 event=0xbb,umask=0x10 01 unc_m_wr_cas_rank3.bank5 uncore memory WR_CAS Access to Rank 3; Bank 5 event=0xbb,umask=0x20 01 unc_m_wr_cas_rank3.bank6 uncore memory WR_CAS Access to Rank 3; Bank 6 event=0xbb,umask=0x40 01 unc_m_wr_cas_rank3.bank7 uncore memory WR_CAS Access to Rank 3; Bank 7 event=0xbb,umask=0x80 01 unc_m_wr_cas_rank4.bank0 uncore memory WR_CAS Access to Rank 4; Bank 0 event=0xbc,umask=1 01 unc_m_wr_cas_rank4.bank1 uncore memory WR_CAS Access to Rank 4; Bank 1 event=0xbc,umask=2 01 unc_m_wr_cas_rank4.bank2 uncore memory WR_CAS Access to Rank 4; Bank 2 event=0xbc,umask=4 01 unc_m_wr_cas_rank4.bank3 uncore memory WR_CAS Access to Rank 4; Bank 3 event=0xbc,umask=8 01 unc_m_wr_cas_rank4.bank4 uncore memory WR_CAS Access to Rank 4; Bank 4 event=0xbc,umask=0x10 01 unc_m_wr_cas_rank4.bank5 uncore memory WR_CAS Access to Rank 4; Bank 5 event=0xbc,umask=0x20 01 unc_m_wr_cas_rank4.bank6 uncore memory WR_CAS Access to Rank 4; Bank 6 event=0xbc,umask=0x40 01 unc_m_wr_cas_rank4.bank7 uncore memory WR_CAS Access to Rank 4; Bank 7 event=0xbc,umask=0x80 01 unc_m_wr_cas_rank5.bank0 uncore memory WR_CAS Access to Rank 5; Bank 0 event=0xbd,umask=1 01 unc_m_wr_cas_rank5.bank1 uncore memory WR_CAS Access to Rank 5; Bank 1 event=0xbd,umask=2 01 unc_m_wr_cas_rank5.bank2 uncore memory WR_CAS Access to Rank 5; Bank 2 event=0xbd,umask=4 01 unc_m_wr_cas_rank5.bank3 uncore memory WR_CAS Access to Rank 5; Bank 3 event=0xbd,umask=8 01 unc_m_wr_cas_rank5.bank4 uncore memory WR_CAS Access to Rank 5; Bank 4 event=0xbd,umask=0x10 01 unc_m_wr_cas_rank5.bank5 uncore memory WR_CAS Access to Rank 5; Bank 5 event=0xbd,umask=0x20 01 unc_m_wr_cas_rank5.bank6 uncore memory WR_CAS Access to Rank 5; Bank 6 event=0xbd,umask=0x40 01 unc_m_wr_cas_rank5.bank7 uncore memory WR_CAS Access to Rank 5; Bank 7 event=0xbd,umask=0x80 01 unc_m_wr_cas_rank6.bank0 uncore memory WR_CAS Access to Rank 6; Bank 0 event=0xbe,umask=1 01 unc_m_wr_cas_rank6.bank1 uncore memory WR_CAS Access to Rank 6; Bank 1 event=0xbe,umask=2 01 unc_m_wr_cas_rank6.bank2 uncore memory WR_CAS Access to Rank 6; Bank 2 event=0xbe,umask=4 01 unc_m_wr_cas_rank6.bank3 uncore memory WR_CAS Access to Rank 6; Bank 3 event=0xbe,umask=8 01 unc_m_wr_cas_rank6.bank4 uncore memory WR_CAS Access to Rank 6; Bank 4 event=0xbe,umask=0x10 01 unc_m_wr_cas_rank6.bank5 uncore memory WR_CAS Access to Rank 6; Bank 5 event=0xbe,umask=0x20 01 unc_m_wr_cas_rank6.bank6 uncore memory WR_CAS Access to Rank 6; Bank 6 event=0xbe,umask=0x40 01 unc_m_wr_cas_rank6.bank7 uncore memory WR_CAS Access to Rank 6; Bank 7 event=0xbe,umask=0x80 01 unc_m_wr_cas_rank7.bank0 uncore memory WR_CAS Access to Rank 7; Bank 0 event=0xbf,umask=1 01 unc_m_wr_cas_rank7.bank1 uncore memory WR_CAS Access to Rank 7; Bank 1 event=0xbf,umask=2 01 unc_m_wr_cas_rank7.bank2 uncore memory WR_CAS Access to Rank 7; Bank 2 event=0xbf,umask=4 01 unc_m_wr_cas_rank7.bank3 uncore memory WR_CAS Access to Rank 7; Bank 3 event=0xbf,umask=8 01 unc_m_wr_cas_rank7.bank4 uncore memory WR_CAS Access to Rank 7; Bank 4 event=0xbf,umask=0x10 01 unc_m_wr_cas_rank7.bank5 uncore memory WR_CAS Access to Rank 7; Bank 5 event=0xbf,umask=0x20 01 unc_m_wr_cas_rank7.bank6 uncore memory WR_CAS Access to Rank 7; Bank 6 event=0xbf,umask=0x40 01 unc_m_wr_cas_rank7.bank7 uncore memory WR_CAS Access to Rank 7; Bank 7 event=0xbf,umask=0x80 01 unc_p_core0_transition_cycles uncore power Core 0 C State Transition Cycles event=0x70 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core10_transition_cycles uncore power Core 10 C State Transition Cycles event=0x7a 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core11_transition_cycles uncore power Core 11 C State Transition Cycles event=0x7b 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core12_transition_cycles uncore power Core 12 C State Transition Cycles event=0x7c 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core13_transition_cycles uncore power Core 13 C State Transition Cycles event=0x7d 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core14_transition_cycles uncore power Core 14 C State Transition Cycles event=0x7e 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core1_transition_cycles uncore power Core 1 C State Transition Cycles event=0x71 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core2_transition_cycles uncore power Core 2 C State Transition Cycles event=0x72 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core3_transition_cycles uncore power Core 3 C State Transition Cycles event=0x73 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core4_transition_cycles uncore power Core 4 C State Transition Cycles event=0x74 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core5_transition_cycles uncore power Core 5 C State Transition Cycles event=0x75 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core6_transition_cycles uncore power Core 6 C State Transition Cycles event=0x76 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core7_transition_cycles uncore power Core 7 C State Transition Cycles event=0x77 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core8_transition_cycles uncore power Core 8 C State Transition Cycles event=0x78 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core9_transition_cycles uncore power Core 9 C State Transition Cycles event=0x79 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_delayed_c_state_abort_core0 uncore power Deep C State Rejection - Core 0 event=0x17 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core1 uncore power Deep C State Rejection - Core 1 event=0x18 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core10 uncore power Deep C State Rejection - Core 10 event=0x21 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core11 uncore power Deep C State Rejection - Core 11 event=0x22 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core12 uncore power Deep C State Rejection - Core 12 event=0x23 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core13 uncore power Deep C State Rejection - Core 13 event=0x24 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core14 uncore power Deep C State Rejection - Core 14 event=0x25 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core2 uncore power Deep C State Rejection - Core 2 event=0x19 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core3 uncore power Deep C State Rejection - Core 3 event=0x1a 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core4 uncore power Deep C State Rejection - Core 4 event=0x1b 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core5 uncore power Deep C State Rejection - Core 5 event=0x1c 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core6 uncore power Deep C State Rejection - Core 6 event=0x1d 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core7 uncore power Deep C State Rejection - Core 7 event=0x1e 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core8 uncore power Deep C State Rejection - Core 8 event=0x1f 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core9 uncore power Deep C State Rejection - Core 9 event=0x20 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_demotions_core0 uncore power Core 0 C State Demotions event=0x1e 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core1 uncore power Core 1 C State Demotions event=0x1f 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core10 uncore power Core 10 C State Demotions event=0x42 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core11 uncore power Core 11 C State Demotions event=0x43 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core12 uncore power Core 12 C State Demotions event=0x44 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core13 uncore power Core 13 C State Demotions event=0x45 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core14 uncore power Core 14 C State Demotions event=0x46 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core2 uncore power Core 2 C State Demotions event=0x20 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core3 uncore power Core 3 C State Demotions event=0x21 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core4 uncore power Core 4 C State Demotions event=0x22 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core5 uncore power Core 5 C State Demotions event=0x23 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core6 uncore power Core 6 C State Demotions event=0x24 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core7 uncore power Core 7 C State Demotions event=0x25 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core8 uncore power Core 8 C State Demotions event=0x40 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core9 uncore power Core 9 C State Demotions event=0x41 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_freq_max_current_cycles uncore power Current Strongest Upper Limit Cycles event=7 01 Counts the number of cycles when current is the upper limit on frequency unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=0x61 01 Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_min_perf_p_cycles uncore power Perf P Limit Strongest Lower Limit Cycles event=0x62 01 Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower. Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down. This is largely to minimize increases in snoop and remote read latencies unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0x60 01 Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_pkg_c_exit_latency uncore power Package C State Exit Latency event=0x26 01 Counts the number of cycles that the package is transitioning from package C2 to C3 unc_p_pkg_c_exit_latency_sel uncore power Package C State Exit Latency event=0x26 01 Counts the number of cycles that the package is transitioning from package C2 to C3 unc_p_pkg_c_state_residency_c0_cycles uncore power Package C State Residency - C0 event=0x2a 01 Counts the number of cycles that the package is in C0 unc_p_pkg_c_state_residency_c2_cycles uncore power Package C State Residency - C2 event=0x2b 01 Counts the number of cycles that the package is in C2 unc_p_pkg_c_state_residency_c3_cycles uncore power Package C State Residency - C3 event=0x2c 01 Counts the number of cycles that the package is in C3 unc_p_pkg_c_state_residency_c6_cycles uncore power Package C State Residency - C6 event=0x2d 01 Counts the number of cycles that the package is in C6 unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0x63 01 Number of cycles spent performing core C state transitions across all cores unc_p_volt_trans_cycles_change uncore power Cycles Changing Voltage event=3 01 Counts the number of cycles when the system is changing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition. This event is calculated by or'ing together the increasing and decreasing events unc_p_volt_trans_cycles_decrease uncore power Cycles Decreasing Voltage event=2 01 Counts the number of cycles when the system is decreasing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition unc_p_volt_trans_cycles_increase uncore power Cycles Increasing Voltage event=1 01 Counts the number of cycles when the system is increasing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition unc_p_vr_hot_cycles uncore power VR Hot event=0x32 01 dtlb_load_misses.demand_ld_walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size event=8,period=100003,umask=0x82 00 dtlb_load_misses.demand_ld_walk_duration virtual memory Demand load cycles page miss handler (PMH) is busy with this walk event=8,period=2000003,umask=0x84 00 l1d.allocated_in_m cache Allocated L1D data cache lines in M state event=0x51,period=2000003,umask=2 00 l1d.all_m_replacement cache Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement event=0x51,period=2000003,umask=8 00 l1d.eviction cache L1D data cache lines in M state evicted due to replacement event=0x51,period=2000003,umask=4 00 l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=1 00 This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier l1d_blocks.bank_conflict_cycles cache Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports event=0xbf,cmask=1,period=100003,umask=5 00 l1d_pend_miss.pending cache L1D miss outstanding duration in cycles event=0x48,period=2000003,umask=1 00 l2_l1d_wb_rqsts.hit_e cache Not rejected writebacks from L1D to L2 cache lines in E state event=0x28,period=200003,umask=4 00 l2_l1d_wb_rqsts.hit_m cache Not rejected writebacks from L1D to L2 cache lines in M state event=0x28,period=200003,umask=8 00 l2_l1d_wb_rqsts.hit_s cache Not rejected writebacks from L1D to L2 cache lines in S state event=0x28,period=200003,umask=2 00 l2_l1d_wb_rqsts.miss cache Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.) event=0x28,period=200003,umask=1 00 l2_lines_in.e cache L2 cache lines in E state filling L2 event=0xf1,period=100003,umask=4 00 l2_lines_in.i cache L2 cache lines in I state filling L2 event=0xf1,period=100003,umask=1 00 l2_lines_in.s cache L2 cache lines in S state filling L2 event=0xf1,period=100003,umask=2 00 l2_lines_out.demand_clean cache Clean L2 cache lines evicted by demand event=0xf2,period=100003,umask=1 00 l2_lines_out.demand_dirty cache Dirty L2 cache lines evicted by demand event=0xf2,period=100003,umask=2 00 l2_lines_out.dirty_all cache Dirty L2 cache lines filling the L2 event=0xf2,period=100003,umask=0xa 00 l2_lines_out.pf_clean cache Clean L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=4 00 l2_lines_out.pf_dirty cache Dirty L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=8 00 l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0x30 00 l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=3 00 l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xc0 00 l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xc 00 l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0x10 00 l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x20 00 l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=1 00 l2_rqsts.pf_hit cache Requests from the L2 hardware prefetchers that hit L2 cache event=0x24,period=200003,umask=0x40 00 l2_rqsts.pf_miss cache Requests from the L2 hardware prefetchers that miss L2 cache event=0x24,period=200003,umask=0x80 00 l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=4 00 l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=8 00 l2_store_lock_rqsts.all cache RFOs that access cache lines in any state event=0x27,period=200003,umask=0xf 00 l2_store_lock_rqsts.hit_e cache RFOs that hit cache lines in E state event=0x27,period=200003,umask=4 00 l2_store_lock_rqsts.hit_m cache RFOs that hit cache lines in M state event=0x27,period=200003,umask=8 00 l2_store_lock_rqsts.miss cache RFOs that miss cache lines event=0x27,period=200003,umask=1 00 l2_trans.all_pf cache L2 or LLC HW prefetches that access L2 cache event=0xf0,period=200003,umask=8 00 l2_trans.all_requests cache Transactions accessing L2 pipe event=0xf0,period=200003,umask=0x80 00 l2_trans.code_rd cache L2 cache accesses when fetching instructions event=0xf0,period=200003,umask=4 00 l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=1 00 l2_trans.l1d_wb cache L1D writebacks that access L2 cache event=0xf0,period=200003,umask=0x10 00 l2_trans.l2_fill cache L2 fill requests that access L2 cache event=0xf0,period=200003,umask=0x20 00 l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40 00 l2_trans.rfo cache RFO requests that access L2 cache event=0xf0,period=200003,umask=2 00 lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x63,period=2000003,umask=2 00 longest_lat_cache.miss cache Core-originated cacheable demand requests missed LLC event=0x2e,period=100003,umask=0x41 00 longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to LLC event=0x2e,period=100003,umask=0x4f 00 mem_load_uops_llc_hit_retired.xsnp_hit cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache event=0xd2,period=20011,umask=2 00 This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state mem_load_uops_llc_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared LLC event=0xd2,period=20011,umask=4 00 This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2 mem_load_uops_llc_hit_retired.xsnp_miss cache Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache event=0xd2,period=20011,umask=1 00 mem_load_uops_llc_hit_retired.xsnp_none cache Retired load uops which data sources were hits in LLC without snoops required event=0xd2,period=100003,umask=8 00 mem_load_uops_llc_miss_retired.local_dram cache Data from local DRAM either Snoop not needed or Snoop Miss (RspI) event=0xd3,period=100007,umask=1 00 mem_load_uops_llc_miss_retired.remote_dram cache Data from remote DRAM either Snoop not needed or Snoop Miss (RspI) event=0xd3,period=100007,umask=4 00 mem_load_uops_retired.llc_hit cache Retired load uops which data sources were data hits in LLC without snoops required event=0xd1,period=50021,umask=4 00 This event counts retired load uops that hit in the last-level (L3) cache without snoops required mem_load_uops_retired.llc_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source event=0xd1,period=100007,umask=0x20 00 mem_uops_retired.all_loads cache All retired load uops (Precise event) event=0xd0,period=2000003,umask=0x81 00 This event counts the number of load uops retired (Precise event) mem_uops_retired.all_stores cache All retired store uops (Precise event) event=0xd0,period=2000003,umask=0x82 00 This event counts the number of store uops retired (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access (Precise event) event=0xd0,period=100007,umask=0x21 00 mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary (Precise event) event=0xd0,period=100003,umask=0x41 00 This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary (Precise event) event=0xd0,period=100003,umask=0x42 00 This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB (Precise event) event=0xd0,period=100003,umask=0x11 00 mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB (Precise event) event=0xd0,period=100003,umask=0x12 00 offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=8 00 offcore_requests.demand_code_rd cache Cacheable and non-cacheable code read requests event=0xb0,period=100003,umask=2 00 offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=1 00 offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=4 00 offcore_requests_buffer.sq_full cache Cases when offcore requests buffer cannot take more entries for core event=0xb2,period=2000003,umask=1 00 offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=8 00 offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=8 00 offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=1 00 offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,cmask=1,period=2000003,umask=4 00 offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue event=0x60,period=2000003,umask=1 00 offcore_requests_outstanding.demand_data_rd_c6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue event=0x60,cmask=6,period=2000003,umask=1 00 offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=4 00 fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e 00 fp_assist.simd_input floating point Number of SIMD FP assists due to input values event=0xca,period=100003,umask=0x10 00 fp_assist.simd_output floating point Number of SIMD FP assists due to Output values event=0xca,period=100003,umask=8 00 fp_assist.x87_input floating point Number of X87 assists due to input value event=0xca,period=100003,umask=4 00 fp_assist.x87_output floating point Number of X87 assists due to output value event=0xca,period=100003,umask=2 00 fp_comp_ops_exe.sse_packed_double floating point Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle event=0x10,period=2000003,umask=0x10 00 fp_comp_ops_exe.sse_packed_single floating point Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle event=0x10,period=2000003,umask=0x40 00 fp_comp_ops_exe.sse_scalar_double floating point Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle event=0x10,period=2000003,umask=0x80 00 fp_comp_ops_exe.sse_scalar_single floating point Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle event=0x10,period=2000003,umask=0x20 00 fp_comp_ops_exe.x87 floating point Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s event=0x10,period=2000003,umask=1 00 other_assists.avx_store floating point Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations event=0xc1,period=100003,umask=8 00 simd_fp_256.packed_double floating point Number of AVX-256 Computational FP double precision uops issued this cycle event=0x11,period=2000003,umask=2 00 simd_fp_256.packed_single floating point Number of GSSE-256 Computational FP single precision uops issued this cycle event=0x11,period=2000003,umask=1 00 dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE switches event=0xab,period=2000003,umask=1 00 dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=2 00 This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end dsb_fill.all_cancel frontend Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit event=0xac,period=2000003,umask=0xa 00 dsb_fill.exceed_dsb_lines frontend Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines event=0xac,period=2000003,umask=8 00 dsb_fill.other_cancel frontend Cases of cancelling valid DSB fill not because of exceeding way limit event=0xac,period=2000003,umask=2 00 icache.misses frontend Instruction cache, streaming buffer and victim cache misses event=0x80,period=200003,umask=2 00 This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x18 00 idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x18 00 idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24 00 idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24 00 idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=8 00 idq.empty frontend Instruction Decode Queue (IDQ) empty cycles event=0x79,period=2000003,umask=2 00 idq.mite_all_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x3c 00 idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=4 00 idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information idq.ms_dsb_uops frontend Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x10 00 idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20 00 idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30 00 idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=1 00 This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization idq_uops_not_delivered.cycles_ge_1_uop_deliv.core frontend Cycles when 1 or more uops were delivered to the by the front end event=0x9c,cmask=4,inv=1,period=2000003,umask=1 00 machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=2 00 This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently mem_trans_retired.load_latency_gt_128 memory Loads with latency value being above 128 (Must be precise) event=0xcd,period=1009,umask=1,ldlat=0x80 00 mem_trans_retired.load_latency_gt_16 memory Loads with latency value being above 16 (Must be precise) event=0xcd,period=20011,umask=1,ldlat=0x10 00 mem_trans_retired.load_latency_gt_256 memory Loads with latency value being above 256 (Must be precise) event=0xcd,period=503,umask=1,ldlat=0x100 00 mem_trans_retired.load_latency_gt_32 memory Loads with latency value being above 32 (Must be precise) event=0xcd,period=100007,umask=1,ldlat=0x20 00 mem_trans_retired.load_latency_gt_4 memory Loads with latency value being above 4 (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x4 00 mem_trans_retired.load_latency_gt_512 memory Loads with latency value being above 512 (Must be precise) event=0xcd,period=101,umask=1,ldlat=0x200 00 mem_trans_retired.load_latency_gt_64 memory Loads with latency value being above 64 (Must be precise) event=0xcd,period=2003,umask=1,ldlat=0x40 00 mem_trans_retired.load_latency_gt_8 memory Loads with latency value being above 8 (Must be precise) event=0xcd,period=50021,umask=1,ldlat=0x8 00 mem_trans_retired.precise_store memory Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS) (Must be precise) event=0xcd,period=2000003,umask=2 00 misalign_mem_ref.loads memory Speculative cache line split load uops dispatched to L1 cache event=5,period=2000003,umask=1 00 misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=5,period=2000003,umask=2 00 offcore_response.all_demand_mlc_pref_reads.llc_miss.any_response memory This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC20077 00 offcore_response.all_demand_mlc_pref_reads.llc_miss.local_dram memory Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded event=0xb7,period=100003,umask=1,offcore_rsp=0x600400077 00 offcore_response.all_demand_mlc_pref_reads.llc_miss.remote_hitm_hit_forward memory This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded event=0xb7,period=100003,umask=1,offcore_rsp=0x187FC20077 00 offcore_response.pf_llc_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20080 00 cpl_cycles.ring0 other Unhalted core cycles when the thread is in ring 0 event=0x5c,period=2000003,umask=1 00 cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100007,umask=1 00 cpl_cycles.ring123 other Unhalted core cycles when thread is in rings 1, 2, or 3 event=0x5c,period=2000003,umask=2 00 hw_pre_req.dl1_miss other Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for event=0x4e,period=2000003,umask=2 00 insts_written_to_iq.insts other Valid instructions written to IQ per cycle event=0x17,period=2000003,umask=1 00 lock_cycles.split_lock_uc_lock_duration other Cycles when L1 and L2 are locked due to UC or split lock event=0x63,period=2000003,umask=1 00 agu_bypass_cancel.count pipeline This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an event=0xb6,period=100003,umask=1 00 arith.fpu_div pipeline Divide operations executed event=0x14,cmask=1,edge=1,period=100003,umask=1 00 This event counts the number of the divide operations executed arith.fpu_div_active pipeline Cycles when divider is busy executing divide operations event=0x14,period=2000003,umask=1 00 br_inst_exec.all_branches pipeline Speculative and retired branches event=0x88,period=200003,umask=0xff 00 br_inst_retired.all_branches pipeline All (macro) branch instructions retired event=0xc4,period=400009 00 br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc4,period=400009,umask=4 00 br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100007,umask=0x40 00 br_inst_retired.not_taken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10 00 br_misp_exec.all_branches pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xff 00 br_misp_exec.all_direct_near_call pipeline Speculative and retired mispredicted direct near calls event=0x89,period=200003,umask=0xd0 00 br_misp_exec.taken_direct_near_call pipeline Taken speculative and retired mispredicted direct near calls event=0x89,period=200003,umask=0x90 00 br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009 00 br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc5,period=400009,umask=4 00 br_misp_retired.near_call pipeline Direct and indirect mispredicted near call instructions retired (Precise event) event=0xc5,period=100007,umask=2 00 br_misp_retired.not_taken pipeline Mispredicted not taken branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x10 00 br_misp_retired.taken pipeline Mispredicted taken branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x20 00 cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=1 00 cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=1 00 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3 00 This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=1 00 cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=1 00 cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state event=0x3c,period=2000003 00 cycle_activity.cycles_l1d_pending pipeline Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING event=0xa3,cmask=2,period=2000003,umask=2 00 cycle_activity.cycles_l2_pending pipeline Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 event=0xa3,cmask=1,period=2000003,umask=1 00 cycle_activity.cycles_no_dispatch pipeline Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event event=0xa3,cmask=4,period=2000003,umask=4 00 cycle_activity.stalls_l1d_pending pipeline Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING event=0xa3,cmask=6,period=2000003,umask=6 00 cycle_activity.stalls_l2_pending pipeline Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2 event=0xa3,cmask=5,period=2000003,umask=5 00 ild_stall.iq_full pipeline Stall cycles because IQ is full event=0x87,period=2000003,umask=4 00 inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003 00 This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event event=0xc0,period=2000003 00 inst_retired.prec_dist pipeline Instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc0,period=2000003,umask=1 00 int_misc.rat_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread event=0xd,period=2000003,umask=0x40 00 int_misc.recovery_cycles pipeline Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) event=0xd,cmask=1,period=2000003,umask=3 00 int_misc.recovery_stalls_count pipeline Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) event=0xd,cmask=1,edge=1,period=2000003,umask=3 00 ld_blocks.all_block pipeline Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss) event=3,period=100003,umask=0x10 00 ld_blocks.data_unknown pipeline Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data event=3,period=100003,umask=1 00 ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=3,period=100003,umask=2 00 This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare event=7,period=100003,umask=1 00 Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles ld_blocks_partial.all_sta_block pipeline This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type event=7,period=100003,umask=8 00 load_hit_pre.hw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for hardware prefetch event=0x4c,period=100003,umask=2 00 load_hit_pre.sw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for software prefetch event=0x4c,period=100003,umask=1 00 other_assists.itlb_miss_retired pipeline Retired instructions experiencing ITLB misses event=0xc1,period=100003,umask=2 00 partial_rat_stalls.flags_merge_uop pipeline Increments the number of flags-merge uops in flight each cycle event=0x59,period=2000003,umask=0x20 00 partial_rat_stalls.flags_merge_uop_cycles pipeline Performance sensitive flags-merging uops added by Sandy Bridge u-arch event=0x59,cmask=1,period=2000003,umask=0x20 00 This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual partial_rat_stalls.mul_single_uop pipeline Multiply packed/scalar single precision uops allocated event=0x59,period=2000003,umask=0x80 00 partial_rat_stalls.slow_lea_window pipeline Cycles with at least one slow LEA uop being allocated event=0x59,period=2000003,umask=0x40 00 This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=1 00 resource_stalls.lb pipeline Counts the cycles of stall due to lack of load buffers event=0xa2,period=2000003,umask=2 00 resource_stalls.lb_sb pipeline Resource stalls due to load or store buffers all being in use event=0xa2,period=2000003,umask=0xa 00 resource_stalls.mem_rs pipeline Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized event=0xa2,period=2000003,umask=0xe 00 resource_stalls.ooo_rsrc pipeline Resource stalls due to Rob being full, FCSW, MXCSR and OTHER event=0xa2,period=2000003,umask=0xf0 00 resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=8 00 resource_stalls2.all_fl_empty pipeline Cycles with either free list is empty event=0x5b,period=2000003,umask=0xc 00 resource_stalls2.all_prf_control pipeline Resource stalls2 control structures full for physical registers event=0x5b,period=2000003,umask=0xf 00 resource_stalls2.bob_full pipeline Cycles when Allocator is stalled if BOB is full and new branch needs it event=0x5b,period=2000003,umask=0x40 00 resource_stalls2.ooo_rsrc pipeline Resource stalls out of order resources full event=0x5b,period=2000003,umask=0x4f 00 rob_misc_events.lbr_inserts pipeline Count cases of saving new LBR event=0xcc,period=2000003,umask=0x20 00 rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=1 00 rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues event=0x5e,cmask=1,edge=1,inv=1,period=2000003,umask=1 00 uops_dispatched.core pipeline Uops dispatched from any thread event=0xb1,period=2000003,umask=2 00 uops_dispatched.thread pipeline Uops dispatched per thread event=0xb1,period=2000003,umask=1 00 uops_dispatched_port.port_0 pipeline Cycles per thread when uops are dispatched to port 0 event=0xa1,period=2000003,umask=1 00 uops_dispatched_port.port_0_core pipeline Cycles per core when uops are dispatched to port 0 event=0xa1,any=1,period=2000003,umask=1 00 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are dispatched to port 1 event=0xa1,period=2000003,umask=2 00 uops_dispatched_port.port_1_core pipeline Cycles per core when uops are dispatched to port 1 event=0xa1,any=1,period=2000003,umask=2 00 uops_dispatched_port.port_2 pipeline Cycles per thread when load or STA uops are dispatched to port 2 event=0xa1,period=2000003,umask=0xc 00 uops_dispatched_port.port_2_core pipeline Cycles per core when load or STA uops are dispatched to port 2 event=0xa1,any=1,period=2000003,umask=0xc 00 uops_dispatched_port.port_3 pipeline Cycles per thread when load or STA uops are dispatched to port 3 event=0xa1,period=2000003,umask=0x30 00 uops_dispatched_port.port_3_core pipeline Cycles per core when load or STA uops are dispatched to port 3 event=0xa1,any=1,period=2000003,umask=0x30 00 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are dispatched to port 4 event=0xa1,period=2000003,umask=0x40 00 uops_dispatched_port.port_4_core pipeline Cycles per core when uops are dispatched to port 4 event=0xa1,any=1,period=2000003,umask=0x40 00 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are dispatched to port 5 event=0xa1,period=2000003,umask=0x80 00 uops_dispatched_port.port_5_core pipeline Cycles per core when uops are dispatched to port 5 event=0xa1,any=1,period=2000003,umask=0x80 00 uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=1 00 This event counts the number of Uops issued by the front-end of the pipeilne to the back-end uops_retired.all pipeline Actually retired uops (Precise event) event=0xc2,period=2000003,umask=1 00 This event counts the number of micro-ops retired (Precise event) uops_retired.core_stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=1 00 uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=2 00 This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization (Precise event) unc_c_ismq_drd_miss_occ uncore cache event=0x21 01 unc_c_llc_lookup.data_read uncore cache Cache Lookups; Data Read Request event=0x34,umask=3 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_lookup.nid uncore cache Cache Lookups; RTID event=0x34,umask=0x41 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_lookup.remote_snoop uncore cache Cache Lookups; External Snoop Request event=0x34,umask=9 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_lookup.write uncore cache Cache Lookups; Write Requests event=0x34,umask=5 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_victims.nid uncore cache Lines Victimized; Victimized Lines that Match NID event=0x37,umask=0x40 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_misc.rfo_hit_s uncore cache Cbo Misc; RFO HitS event=0x39,umask=8 01 Miscellaneous events in the Cbo unc_c_misc.rspi_was_fse uncore cache Cbo Misc; Silent Snoop Eviction event=0x39,umask=1 01 Miscellaneous events in the Cbo unc_c_misc.wc_aliasing uncore cache Cbo Misc; Write Combining Aliasing event=0x39,umask=2 01 Miscellaneous events in the Cbo unc_c_ring_ad_used.down_even uncore cache AD Ring In Use; Down and Even event=0x1b,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_odd uncore cache AD Ring In Use; Down and Odd event=0x1b,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_even uncore cache AD Ring In Use; Up and Even event=0x1b,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_odd uncore cache AD Ring In Use; Up and Odd event=0x1b,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_even uncore cache AK Ring In Use; Down and Even event=0x1c,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_odd uncore cache AK Ring In Use; Down and Odd event=0x1c,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up_even uncore cache AK Ring In Use; Up and Even event=0x1c,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up_odd uncore cache AK Ring In Use; Up and Odd event=0x1c,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_even uncore cache BL Ring in Use; Down and Even event=0x1d,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_odd uncore cache BL Ring in Use; Down and Odd event=0x1d,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up_even uncore cache BL Ring in Use; Up and Even event=0x1d,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up_odd uncore cache BL Ring in Use; Up and Odd event=0x1d,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bounces.ak_core uncore cache Number of LLC responses that bounced on the Ring.; Acknowledgements to core event=5,umask=2 01 unc_c_ring_bounces.bl_core uncore cache Number of LLC responses that bounced on the Ring.; Data Responses to core event=5,umask=4 01 unc_c_ring_bounces.iv_core uncore cache Number of LLC responses that bounced on the Ring.; Snoops of processor's cache event=5,umask=8 01 unc_c_ring_iv_used.any uncore cache BL Ring in Use; Any event=0x1e,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in JKT. Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN. To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD unc_c_ring_sink_starved.ad_cache uncore cache event=6,umask=1 01 unc_c_ring_sink_starved.ak_core uncore cache event=6,umask=2 01 unc_c_ring_sink_starved.bl_core uncore cache event=6,umask=4 01 unc_c_ring_sink_starved.iv_core uncore cache event=6,umask=8 01 unc_c_rxr_ext_starved.ipq uncore cache Ingress Arbiter Blocking Cycles; IRQ event=0x12,umask=2 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_ext_starved.irq uncore cache Ingress Arbiter Blocking Cycles; IPQ event=0x12,umask=1 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_ext_starved.ismq uncore cache Ingress Arbiter Blocking Cycles; ISMQ event=0x12,umask=4 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_ext_starved.ismq_bids uncore cache Ingress Arbiter Blocking Cycles; ISMQ_BID event=0x12,umask=8 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_inserts.irq_rejected uncore cache Ingress Allocations; IRQ Rejected event=0x13,umask=2 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.vfifo uncore cache Ingress Allocations; VFIFO event=0x13,umask=0x10 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_int_starved.ipq uncore cache Ingress Internal Starvation Cycles; IPQ event=0x14,umask=4 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_int_starved.irq uncore cache Ingress Internal Starvation Cycles; IRQ event=0x14,umask=1 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_int_starved.ismq uncore cache Ingress Internal Starvation Cycles; ISMQ event=0x14,umask=8 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_ipq_retry.addr_conflict uncore cache Probe Queue Retries; Address Conflict event=0x31,umask=4 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries unc_c_rxr_ipq_retry.any uncore cache Probe Queue Retries; Any Reject event=0x31,umask=1 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries unc_c_rxr_ipq_retry.full uncore cache Probe Queue Retries; No Egress Credits event=0x31,umask=2 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries unc_c_rxr_irq_retry.addr_conflict uncore cache Ingress Request Queue Rejects; Address Conflict event=0x32,umask=4 01 unc_c_rxr_irq_retry.any uncore cache Ingress Request Queue Rejects; Any Reject event=0x32,umask=1 01 unc_c_rxr_irq_retry.full uncore cache Ingress Request Queue Rejects; No Egress Credits event=0x32,umask=2 01 unc_c_rxr_irq_retry.qpi_credits uncore cache Ingress Request Queue Rejects; No QPI Credits event=0x32,umask=0x10 01 unc_c_rxr_irq_retry.rtid uncore cache Ingress Request Queue Rejects; No RTIDs event=0x32,umask=8 01 unc_c_rxr_ismq_retry.any uncore cache ISMQ Retries; Any Reject event=0x33,umask=1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.full uncore cache ISMQ Retries; No Egress Credits event=0x33,umask=2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.iio_credits uncore cache ISMQ Retries; No IIO Credits event=0x33,umask=0x20 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.rtid uncore cache ISMQ Retries; No RTIDs event=0x33,umask=8 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_occupancy.irq_rejected uncore cache Ingress Occupancy; IRQ Rejected event=0x11,umask=2 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.vfifo uncore cache Ingress Occupancy; VFIFO event=0x11,umask=0x10 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_tor_inserts.eviction uncore cache TOR Inserts; Evictions event=0x35,umask=4 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.miss_all uncore cache TOR Inserts; Miss All event=0x35,umask=0xa 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.miss_opcode uncore cache TOR Inserts; Miss Opcode Match event=0x35,umask=3 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_all uncore cache TOR Inserts; NID Matched event=0x35,umask=0x48 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_eviction uncore cache TOR Inserts; NID Matched Evictions event=0x35,umask=0x44 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_miss_all uncore cache TOR Inserts; NID Matched Miss All event=0x35,umask=0x4a 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_miss_opcode uncore cache TOR Inserts; NID and Opcode Matched Miss event=0x35,umask=0x43 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_opcode uncore cache TOR Inserts; NID and Opcode Matched event=0x35,umask=0x41 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_wb uncore cache TOR Inserts; NID Matched Writebacks event=0x35,umask=0x50 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.opcode uncore cache TOR Inserts; Opcode Match event=0x35,umask=1 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.wb uncore cache TOR Inserts; Writebacks event=0x35,umask=0x10 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.all uncore cache TOR Occupancy; Any event=0x36,umask=8 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.eviction uncore cache TOR Occupancy; Evictions event=0x36,umask=4 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_all uncore cache TOR Occupancy; Miss All event=0x36,umask=0xa 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_opcode uncore cache TOR Occupancy; Miss Opcode Match event=0x36,umask=3 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x48 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_eviction uncore cache TOR Occupancy; NID Matched Evictions event=0x36,umask=0x44 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_miss_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x4a 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_miss_opcode uncore cache TOR Occupancy; NID and Opcode Matched Miss event=0x36,umask=0x43 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_opcode uncore cache TOR Occupancy; NID and Opcode Matched event=0x36,umask=0x41 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.opcode uncore cache TOR Occupancy; Opcode Match event=0x36,umask=1 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_txr_ads_used uncore cache event=4 01 unc_c_txr_inserts.ad_cache uncore cache Egress Allocations; AD - Cachebo event=2,umask=1 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.ad_core uncore cache Egress Allocations; AD - Corebo event=2,umask=0x10 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.ak_cache uncore cache Egress Allocations; AK - Cachebo event=2,umask=2 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.ak_core uncore cache Egress Allocations; AK - Corebo event=2,umask=0x20 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.bl_cache uncore cache Egress Allocations; BL - Cacheno event=2,umask=4 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.bl_core uncore cache Egress Allocations; BL - Corebo event=2,umask=0x40 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.iv_cache uncore cache Egress Allocations; IV - Cachebo event=2,umask=8 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_starved.ak uncore cache Injection Starvation; Onto AK Ring event=3,umask=2 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_c_txr_starved.bl uncore cache Injection Starvation; Onto BL Ring event=3,umask=4 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_h_bypass_imc.not_taken uncore cache HA to iMC Bypass; Not Taken event=0x14,umask=2 01 Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not unc_h_bypass_imc.taken uncore cache HA to iMC Bypass; Taken event=0x14,umask=1 01 Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not unc_h_conflict_cycles.conflict uncore cache Conflict Checks; Conflict Detected event=0xb,umask=2 01 unc_h_conflict_cycles.no_conflict uncore cache Conflict Checks; No Conflict event=0xb,umask=1 01 unc_h_directory_lookup.no_snp uncore cache Directory Lookups; Snoop Not Needed event=0xc,umask=2 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.snp uncore cache Directory Lookups; Snoop Needed event=0xc,umask=1 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_update.clear uncore cache Directory Updates; Directory Clear event=0xd,umask=2 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.set uncore cache Directory Updates; Directory Set event=0xd,umask=1 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_requests.reads uncore cache Read and Write Requests; Reads event=1,umask=3 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc) unc_h_requests.writes uncore cache Read and Write Requests; Writes event=1,umask=0xc 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc) unc_h_ring_ad_used.ccw_even uncore cache HA AD Ring in Use; Counterclockwise and Even event=0x3e,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.ccw_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd event=0x3e,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_even uncore cache HA AD Ring in Use; Clockwise and Even event=0x3e,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_odd uncore cache HA AD Ring in Use; Clockwise and Odd event=0x3e,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_even uncore cache HA AK Ring in Use; Counterclockwise and Even event=0x3f,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd event=0x3f,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_even uncore cache HA AK Ring in Use; Clockwise and Even event=0x3f,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_odd uncore cache HA AK Ring in Use; Clockwise and Odd event=0x3f,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_even uncore cache HA BL Ring in Use; Counterclockwise and Even event=0x40,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd event=0x40,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_even uncore cache HA BL Ring in Use; Clockwise and Even event=0x40,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_odd uncore cache HA BL Ring in Use; Clockwise and Odd event=0x40,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_rpq_cycles_no_reg_credits.chn0 uncore cache iMC RPQ Credits Empty - Regular; Channel 0 event=0x15,umask=1 01 Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_reg_credits.chn1 uncore cache iMC RPQ Credits Empty - Regular; Channel 1 event=0x15,umask=2 01 Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_reg_credits.chn2 uncore cache iMC RPQ Credits Empty - Regular; Channel 2 event=0x15,umask=4 01 Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_reg_credits.chn3 uncore cache iMC RPQ Credits Empty - Regular; Channel 3 event=0x15,umask=8 01 Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn0 uncore cache iMC RPQ Credits Empty - Special; Channel 0 event=0x16,umask=1 01 Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn1 uncore cache iMC RPQ Credits Empty - Special; Channel 1 event=0x16,umask=2 01 Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn2 uncore cache iMC RPQ Credits Empty - Special; Channel 2 event=0x16,umask=4 01 Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn3 uncore cache iMC RPQ Credits Empty - Special; Channel 3 event=0x16,umask=8 01 Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_tad_requests_g0.region0 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 0 event=0x1b,umask=1 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region1 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 1 event=0x1b,umask=2 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region2 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 2 event=0x1b,umask=4 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region3 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 3 event=0x1b,umask=8 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region4 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 4 event=0x1b,umask=0x10 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region5 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 5 event=0x1b,umask=0x20 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region6 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 6 event=0x1b,umask=0x40 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region7 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 7 event=0x1b,umask=0x80 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region10 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 10 event=0x1c,umask=4 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region11 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 11 event=0x1c,umask=8 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region8 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 8 event=0x1c,umask=1 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region9 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 9 event=0x1c,umask=2 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tracker_inserts.all uncore cache Tracker Allocations; All Requests event=6,umask=3 01 Counts the number of allocations into the local HA tracker pool. This can be used in conjunction with the occupancy accumulation event in order to calculate average latency. One cannot filter between reads and writes. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_txr_ad.ndr uncore cache Outbound NDR Ring Transactions; Non-data Responses event=0xf,umask=1 01 Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details unc_h_txr_ad.snp uncore cache Outbound NDR Ring Transactions; Snoops event=0xf,umask=2 01 Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details unc_h_txr_ad_cycles_full.all uncore cache AD Egress Full; All event=0x2a,umask=3 01 unc_h_txr_ad_cycles_full.sched0 uncore cache AD Egress Full; Scheduler 0 event=0x2a,umask=1 01 unc_h_txr_ad_cycles_full.sched1 uncore cache AD Egress Full; Scheduler 1 event=0x2a,umask=2 01 unc_h_txr_ad_cycles_ne.all uncore cache AD Egress Not Empty; All event=0x29,umask=3 01 unc_h_txr_ad_cycles_ne.sched0 uncore cache AD Egress Not Empty; Scheduler 0 event=0x29,umask=1 01 unc_h_txr_ad_cycles_ne.sched1 uncore cache AD Egress Not Empty; Scheduler 1 event=0x29,umask=2 01 unc_h_txr_ad_inserts.all uncore cache AD Egress Allocations; All event=0x27,umask=3 01 unc_h_txr_ad_inserts.sched0 uncore cache AD Egress Allocations; Scheduler 0 event=0x27,umask=1 01 unc_h_txr_ad_inserts.sched1 uncore cache AD Egress Allocations; Scheduler 1 event=0x27,umask=2 01 unc_h_txr_ad_occupancy.all uncore cache AD Egress Occupancy; All event=0x28,umask=3 01 unc_h_txr_ad_occupancy.sched0 uncore cache AD Egress Occupancy; Scheduler 0 event=0x28,umask=1 01 unc_h_txr_ad_occupancy.sched1 uncore cache AD Egress Occupancy; Scheduler 1 event=0x28,umask=2 01 unc_h_txr_ak_cycles_full.all uncore cache AK Egress Full; All event=0x32,umask=3 01 unc_h_txr_ak_cycles_full.sched0 uncore cache AK Egress Full; Scheduler 0 event=0x32,umask=1 01 unc_h_txr_ak_cycles_full.sched1 uncore cache AK Egress Full; Scheduler 1 event=0x32,umask=2 01 unc_h_txr_ak_cycles_ne.all uncore cache AK Egress Not Empty; All event=0x31,umask=3 01 unc_h_txr_ak_cycles_ne.sched0 uncore cache AK Egress Not Empty; Scheduler 0 event=0x31,umask=1 01 unc_h_txr_ak_cycles_ne.sched1 uncore cache AK Egress Not Empty; Scheduler 1 event=0x31,umask=2 01 unc_h_txr_ak_inserts.all uncore cache AK Egress Allocations; All event=0x2f,umask=3 01 unc_h_txr_ak_inserts.sched0 uncore cache AK Egress Allocations; Scheduler 0 event=0x2f,umask=1 01 unc_h_txr_ak_inserts.sched1 uncore cache AK Egress Allocations; Scheduler 1 event=0x2f,umask=2 01 unc_h_txr_ak_ndr uncore cache Outbound NDR Ring Transactions event=0xe 01 Counts the number of outbound NDR transactions sent on the AK ring. NDR stands for 'non-data response' and is generally used for completions that do not include data. AK NDR is used for messages to the local socket unc_h_txr_ak_occupancy.all uncore cache AK Egress Occupancy; All event=0x30,umask=3 01 unc_h_txr_ak_occupancy.sched0 uncore cache AK Egress Occupancy; Scheduler 0 event=0x30,umask=1 01 unc_h_txr_ak_occupancy.sched1 uncore cache AK Egress Occupancy; Scheduler 1 event=0x30,umask=2 01 unc_h_txr_bl.drs_cache uncore cache Outbound DRS Ring Transactions to Cache; Data to Cache event=0x10,umask=1 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination unc_h_txr_bl.drs_core uncore cache Outbound DRS Ring Transactions to Cache; Data to Core event=0x10,umask=2 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination unc_h_txr_bl.drs_qpi uncore cache Outbound DRS Ring Transactions to Cache; Data to QPI event=0x10,umask=4 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination unc_h_txr_bl_cycles_full.all uncore cache BL Egress Full; All event=0x36,umask=3 01 unc_h_txr_bl_cycles_full.sched0 uncore cache BL Egress Full; Scheduler 0 event=0x36,umask=1 01 unc_h_txr_bl_cycles_full.sched1 uncore cache BL Egress Full; Scheduler 1 event=0x36,umask=2 01 unc_h_txr_bl_cycles_ne.all uncore cache BL Egress Not Empty; All event=0x35,umask=3 01 unc_h_txr_bl_cycles_ne.sched0 uncore cache BL Egress Not Empty; Scheduler 0 event=0x35,umask=1 01 unc_h_txr_bl_cycles_ne.sched1 uncore cache BL Egress Not Empty; Scheduler 1 event=0x35,umask=2 01 unc_h_txr_bl_inserts.all uncore cache BL Egress Allocations; All event=0x33,umask=3 01 unc_h_txr_bl_inserts.sched0 uncore cache BL Egress Allocations; Scheduler 0 event=0x33,umask=1 01 unc_h_txr_bl_inserts.sched1 uncore cache BL Egress Allocations; Scheduler 1 event=0x33,umask=2 01 unc_h_txr_bl_occupancy.all uncore cache BL Egress Occupancy; All event=0x34,umask=3 01 unc_h_txr_bl_occupancy.sched0 uncore cache BL Egress Occupancy; Scheduler 0 event=0x34,umask=1 01 unc_h_txr_bl_occupancy.sched1 uncore cache BL Egress Occupancy; Scheduler 1 event=0x34,umask=2 01 unc_h_wpq_cycles_no_reg_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0 event=0x18,umask=1 01 Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_reg_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1 event=0x18,umask=2 01 Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_reg_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2 event=0x18,umask=4 01 Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_reg_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3 event=0x18,umask=8 01 Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 0 event=0x19,umask=1 01 Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 1 event=0x19,umask=2 01 Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 2 event=0x19,umask=4 01 Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 3 event=0x19,umask=8 01 Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_i_address_match.merge_count uncore interconnect Address Match (Conflict) Count; Conflict Merges event=0x17,umask=2 01 Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache unc_i_address_match.stall_count uncore interconnect Address Match (Conflict) Count; Conflict Stalls event=0x17,umask=1 01 Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache unc_i_cache_ack_pending_occupancy.any uncore interconnect Write Ack Pending Occupancy; Any Source event=0x14,umask=1 01 Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements unc_i_cache_ack_pending_occupancy.source uncore interconnect Write Ack Pending Occupancy; Select Source event=0x14,umask=2 01 Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements unc_i_cache_own_occupancy.any uncore interconnect Outstanding Write Ownership Occupancy; Any Source event=0x13,umask=1 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned unc_i_cache_own_occupancy.source uncore interconnect Outstanding Write Ownership Occupancy; Select Source event=0x13,umask=2 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned unc_i_cache_read_occupancy.any uncore interconnect Outstanding Read Occupancy; Any Source event=0x10,umask=1 01 Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned unc_i_cache_read_occupancy.source uncore interconnect Outstanding Read Occupancy; Select Source event=0x10,umask=2 01 Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy; Any Source event=0x12,umask=1 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_cache_total_occupancy.source uncore interconnect Total Write Cache Occupancy; Select Source event=0x12,umask=2 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_cache_write_occupancy.any uncore interconnect Outstanding Write Occupancy; Any Source event=0x11,umask=1 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore unc_i_cache_write_occupancy.source uncore interconnect Outstanding Write Occupancy; Select Source event=0x11,umask=2 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore unc_i_tickles.lost_ownership uncore interconnect Tickle Count; Ownership Lost event=0x16,umask=1 01 Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles unc_i_tickles.top_of_queue uncore interconnect Tickle Count; Data Returned event=0x16,umask=2 01 Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles unc_i_transactions.pd_prefetches uncore interconnect Inbound Transaction Count; Read Prefetches event=0x15,umask=4 01 Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x15,umask=1 01 Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x15,umask=2 01 Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_q_clockticks uncore interconnect Number of qfclks event=0x14 01 Counts the number of clocks in the QPI LL. This clock runs at 1/8th the 'GT/s' speed of the QPI link. For example, a 8GT/s link will have qfclk or 1GHz. JKT does not support dynamic link speeds, so this frequency is fixed unc_q_direct2core.failure_credits uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress Credits event=0x13,umask=2 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_direct2core.failure_credits_rbt uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT event=0x13,umask=8 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_direct2core.failure_rbt uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Not Set event=0x13,umask=4 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_direct2core.success uncore interconnect Direct 2 Core Spawning; Spawn Success event=0x13,umask=1 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_rxl_crc_errors.link_init uncore interconnect CRC Errors Detected; LinkInit event=3,umask=1 01 Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_q_rxl_crc_errors.normal_op uncore interconnect CRC Errors Detected; Normal Operations event=3,umask=2 01 Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_q_rxl_credits_consumed_vn0.drs uncore interconnect VN0 Credit Consumed; DRS event=0x1e,umask=1 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.hom uncore interconnect VN0 Credit Consumed; HOM event=0x1e,umask=8 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.ncb uncore interconnect VN0 Credit Consumed; NCB event=0x1e,umask=2 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.ncs uncore interconnect VN0 Credit Consumed; NCS event=0x1e,umask=4 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.ndr uncore interconnect VN0 Credit Consumed; NDR event=0x1e,umask=0x20 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.snp uncore interconnect VN0 Credit Consumed; SNP event=0x1e,umask=0x10 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_flits_g0.data uncore interconnect Flits Received - Group 0; Data Tx Flits event=1,umask=2 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_rxl_flits_g0.idle uncore interconnect Flits Received - Group 0; Idle and Null Flits event=1,umask=1 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_rxl_flits_g0.non_data uncore interconnect Flits Received - Group 0; Non-Data protocol Tx Flits event=1,umask=4 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_rxl_flits_g1.drs uncore interconnect Flits Received - Group 1; DRS Flits (both Header and Data) event=2,umask=0x18 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.drs_data uncore interconnect Flits Received - Group 1; DRS Data Flits event=2,umask=8 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.drs_nondata uncore interconnect Flits Received - Group 1; DRS Header Flits event=2,umask=0x10 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.hom uncore interconnect Flits Received - Group 1; HOM Flits event=2,umask=6 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.hom_nonreq uncore interconnect Flits Received - Group 1; HOM Non-Request Flits event=2,umask=4 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.hom_req uncore interconnect Flits Received - Group 1; HOM Request Flits event=2,umask=2 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.snp uncore interconnect Flits Received - Group 1; SNP Flits event=2,umask=1 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncb uncore interconnect Flits Received - Group 2; Non-Coherent Rx Flits event=3,umask=0xc 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncb_data uncore interconnect Flits Received - Group 2; Non-Coherent data Rx Flits event=3,umask=4 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncb_nondata uncore interconnect Flits Received - Group 2; Non-Coherent non-data Rx Flits event=3,umask=8 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncs uncore interconnect Flits Received - Group 2; Non-Coherent standard Rx Flits event=3,umask=0x10 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ndr_ad uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AD event=3,umask=1 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ndr_ak uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AK event=3,umask=2 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_stalls.bgf_drs uncore interconnect Stalls Sending to R3QPI; BGF Stall - HOM event=0x35,umask=1 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_hom uncore interconnect Stalls Sending to R3QPI; BGF Stall - DRS event=0x35,umask=8 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_ncb uncore interconnect Stalls Sending to R3QPI; BGF Stall - SNP event=0x35,umask=2 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_ncs uncore interconnect Stalls Sending to R3QPI; BGF Stall - NDR event=0x35,umask=4 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_ndr uncore interconnect Stalls Sending to R3QPI; BGF Stall - NCS event=0x35,umask=0x20 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_snp uncore interconnect Stalls Sending to R3QPI; BGF Stall - NCB event=0x35,umask=0x10 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.egress_credits uncore interconnect Stalls Sending to R3QPI; Egress Credits event=0x35,umask=0x40 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.gv uncore interconnect Stalls Sending to R3QPI; GV event=0x35,umask=0x80 01 Number of stalls trying to send to R3QPI unc_q_txl_crc_no_credits.almost_full uncore interconnect Cycles Stalled with no LLR Credits; LLR is almost full event=2,umask=2 01 Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall unc_q_txl_crc_no_credits.full uncore interconnect Cycles Stalled with no LLR Credits; LLR is full event=2,umask=1 01 Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall unc_q_txl_flits_g0.data uncore interconnect Flits Transferred - Group 0; Data Tx Flits event=0,umask=2 01 Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_txl_flits_g0.idle uncore interconnect Flits Transferred - Group 0; Idle and Null Flits event=0,umask=1 01 Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_txl_flits_g0.non_data uncore interconnect Flits Transferred - Group 0; Non-Data protocol Tx Flits event=0,umask=4 01 Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_txl_flits_g1.drs uncore interconnect Flits Transferred - Group 1; DRS Flits (both Header and Data) event=0,umask=0x18 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.drs_data uncore interconnect Flits Transferred - Group 1; DRS Data Flits event=0,umask=8 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.drs_nondata uncore interconnect Flits Transferred - Group 1; DRS Header Flits event=0,umask=0x10 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.hom uncore interconnect Flits Transferred - Group 1; HOM Flits event=0,umask=6 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.hom_nonreq uncore interconnect Flits Transferred - Group 1; HOM Non-Request Flits event=0,umask=4 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.hom_req uncore interconnect Flits Transferred - Group 1; HOM Request Flits event=0,umask=2 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.snp uncore interconnect Flits Transferred - Group 1; SNP Flits event=0,umask=1 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncb uncore interconnect Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits event=1,umask=0xc 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncb_data uncore interconnect Flits Transferred - Group 2; Non-Coherent data Tx Flits event=1,umask=4 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncb_nondata uncore interconnect Flits Transferred - Group 2; Non-Coherent non-data Tx Flits event=1,umask=8 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncs uncore interconnect Flits Transferred - Group 2; Non-Coherent standard Tx Flits event=1,umask=0x10 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ndr_ad uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AD event=1,umask=1 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ndr_ak uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AK event=1,umask=2 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_r3_iio_credits_acquired.drs uncore interconnect to IIO BL Credit Acquired event=0x20,umask=8 01 Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_acquired.ncb uncore interconnect to IIO BL Credit Acquired event=0x20,umask=0x10 01 Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_acquired.ncs uncore interconnect to IIO BL Credit Acquired event=0x20,umask=0x20 01 Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_reject.drs uncore interconnect to IIO BL Credit Rejected event=0x21,umask=8 01 Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_reject.ncb uncore interconnect to IIO BL Credit Rejected event=0x21,umask=0x10 01 Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_reject.ncs uncore interconnect to IIO BL Credit Rejected event=0x21,umask=0x20 01 Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_used.drs uncore interconnect to IIO BL Credit In Use event=0x22,umask=8 01 Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_used.ncb uncore interconnect to IIO BL Credit In Use event=0x22,umask=0x10 01 Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_used.ncs uncore interconnect to IIO BL Credit In Use event=0x22,umask=0x20 01 Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_ring_ad_used.ccw_even uncore interconnect R3 AD Ring in Use; Counterclockwise and Even event=7,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw_odd uncore interconnect R3 AD Ring in Use; Counterclockwise and Odd event=7,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_even uncore interconnect R3 AD Ring in Use; Clockwise and Even event=7,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_odd uncore interconnect R3 AD Ring in Use; Clockwise and Odd event=7,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw_even uncore interconnect R3 AK Ring in Use; Counterclockwise and Even event=8,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_ak_used.ccw_odd uncore interconnect R3 AK Ring in Use; Counterclockwise and Odd event=8,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_ak_used.cw_even uncore interconnect R3 AK Ring in Use; Clockwise and Even event=8,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_ak_used.cw_odd uncore interconnect R3 AK Ring in Use; Clockwise and Odd event=8,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_bl_used.ccw_even uncore interconnect R3 BL Ring in Use; Counterclockwise and Even event=9,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw_odd uncore interconnect R3 BL Ring in Use; Counterclockwise and Odd event=9,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_even uncore interconnect R3 BL Ring in Use; Clockwise and Even event=9,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_odd uncore interconnect R3 BL Ring in Use; Clockwise and Odd event=9,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_iv_used.any uncore interconnect R3 IV Ring in Use; Any event=0xa,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time unc_r3_rxr_cycles_ne.drs uncore interconnect Ingress Cycles Not Empty; DRS event=0x10,umask=8 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.hom uncore interconnect Ingress Cycles Not Empty; HOM event=0x10,umask=1 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.ncb uncore interconnect Ingress Cycles Not Empty; NCB event=0x10,umask=0x10 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.ncs uncore interconnect Ingress Cycles Not Empty; NCS event=0x10,umask=0x20 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.ndr uncore interconnect Ingress Cycles Not Empty; NDR event=0x10,umask=4 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.snp uncore interconnect Ingress Cycles Not Empty; SNP event=0x10,umask=2 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.drs uncore interconnect Ingress Allocations; DRS event=0x11,umask=8 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.hom uncore interconnect Ingress Allocations; HOM event=0x11,umask=1 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.ncb uncore interconnect Ingress Allocations; NCB event=0x11,umask=0x10 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.ncs uncore interconnect Ingress Allocations; NCS event=0x11,umask=0x20 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.ndr uncore interconnect Ingress Allocations; NDR event=0x11,umask=4 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.snp uncore interconnect Ingress Allocations; SNP event=0x11,umask=2 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_occupancy.drs uncore interconnect Ingress Occupancy Accumulator; DRS event=0x13,umask=8 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.hom uncore interconnect Ingress Occupancy Accumulator; HOM event=0x13,umask=1 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.ncb uncore interconnect Ingress Occupancy Accumulator; NCB event=0x13,umask=0x10 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.ncs uncore interconnect Ingress Occupancy Accumulator; NCS event=0x13,umask=0x20 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.ndr uncore interconnect Ingress Occupancy Accumulator; NDR event=0x13,umask=4 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.snp uncore interconnect Ingress Occupancy Accumulator; SNP event=0x13,umask=2 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_vn0_credits_reject.drs uncore interconnect VN0 Credit Acquisition Failed on DRS; DRS Message Class event=0x37,umask=8 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_reject.hom uncore interconnect VN0 Credit Acquisition Failed on DRS; HOM Message Class event=0x37,umask=1 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_reject.ncb uncore interconnect VN0 Credit Acquisition Failed on DRS; NCB Message Class event=0x37,umask=0x10 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_reject.ncs uncore interconnect VN0 Credit Acquisition Failed on DRS; NCS Message Class event=0x37,umask=0x20 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_reject.ndr uncore interconnect VN0 Credit Acquisition Failed on DRS; NDR Message Class event=0x37,umask=4 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_reject.snp uncore interconnect VN0 Credit Acquisition Failed on DRS; SNP Message Class event=0x37,umask=2 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_used.drs uncore interconnect VN0 Credit Used; DRS Message Class event=0x36,umask=8 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.hom uncore interconnect VN0 Credit Used; HOM Message Class event=0x36,umask=1 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.ncb uncore interconnect VN0 Credit Used; NCB Message Class event=0x36,umask=0x10 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.ncs uncore interconnect VN0 Credit Used; NCS Message Class event=0x36,umask=0x20 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.ndr uncore interconnect VN0 Credit Used; NDR Message Class event=0x36,umask=4 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.snp uncore interconnect VN0 Credit Used; SNP Message Class event=0x36,umask=2 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vna_credits_reject.drs uncore interconnect VNA Credit Reject; DRS Message Class event=0x34,umask=8 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.hom uncore interconnect VNA Credit Reject; HOM Message Class event=0x34,umask=1 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.ncb uncore interconnect VNA Credit Reject; NCB Message Class event=0x34,umask=0x10 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.ncs uncore interconnect VNA Credit Reject; NCS Message Class event=0x34,umask=0x20 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.ndr uncore interconnect VNA Credit Reject; NDR Message Class event=0x34,umask=4 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.snp uncore interconnect VNA Credit Reject; SNP Message Class event=0x34,umask=2 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_u_msg_chnl_size_count.4b uncore interconnect MsgCh Requests by Size; 4B Requests event=0x47,umask=1 01 Number of transactions on the message channel filtered by request size. This includes both reads and writes unc_u_msg_chnl_size_count.8b uncore interconnect MsgCh Requests by Size; 8B Requests event=0x47,umask=2 01 Number of transactions on the message channel filtered by request size. This includes both reads and writes unc_u_phold_cycles.ack_to_deassert uncore interconnect Cycles PHOLD Assert to Ack; ACK to Deassert event=0x45,umask=2 01 PHOLD cycles. Filter from source CoreID unc_u_racu_requests.count uncore interconnect RACU Request event=0x46,umask=1 01 unc_u_u2c_events.livelock uncore interconnect Monitor Sent to T0; Livelock event=0x43,umask=4 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.lterror uncore interconnect Monitor Sent to T0; LTError event=0x43,umask=8 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.monitor_t0 uncore interconnect Monitor Sent to T0; Monitor T0 event=0x43,umask=1 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.monitor_t1 uncore interconnect Monitor Sent to T0; Monitor T1 event=0x43,umask=2 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.other uncore interconnect Monitor Sent to T0; Other event=0x43,umask=0x80 01 Events coming from Uncore can be sent to one or all cores unc_r2_iio_credits_acquired.drs uncore io R2PCIe IIO Credit Acquired; DRS event=0x33,umask=8 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_acquired.ncb uncore io R2PCIe IIO Credit Acquired; NCB event=0x33,umask=0x10 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_acquired.ncs uncore io R2PCIe IIO Credit Acquired; NCS event=0x33,umask=0x20 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_reject.drs uncore io R2PCIe IIO Failed to Acquire a Credit; DRS event=0x34,umask=8 01 Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_reject.ncb uncore io R2PCIe IIO Failed to Acquire a Credit; NCB event=0x34,umask=0x10 01 Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_reject.ncs uncore io R2PCIe IIO Failed to Acquire a Credit; NCS event=0x34,umask=0x20 01 Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_used.drs uncore io R2PCIe IIO Credits in Use; DRS event=0x32,umask=8 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_used.ncb uncore io R2PCIe IIO Credits in Use; NCB event=0x32,umask=0x10 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_used.ncs uncore io R2PCIe IIO Credits in Use; NCS event=0x32,umask=0x20 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_ring_ad_used.ccw_even uncore io R2 AD Ring in Use; Counterclockwise and Even event=7,umask=4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd event=7,umask=8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_even uncore io R2 AD Ring in Use; Clockwise and Even event=7,umask=1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_odd uncore io R2 AD Ring in Use; Clockwise and Odd event=7,umask=2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_even uncore io R2 AK Ring in Use; Counterclockwise and Even event=8,umask=4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd event=8,umask=8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_even uncore io R2 AK Ring in Use; Clockwise and Even event=8,umask=1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_odd uncore io R2 AK Ring in Use; Clockwise and Odd event=8,umask=2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_even uncore io R2 BL Ring in Use; Counterclockwise and Even event=9,umask=4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd event=9,umask=8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_even uncore io R2 BL Ring in Use; Clockwise and Even event=9,umask=1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_odd uncore io R2 BL Ring in Use; Clockwise and Odd event=9,umask=2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_iv_used.any uncore io R2 IV Ring in Use; Any event=0xa,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time unc_r2_rxr_cycles_ne.drs uncore io Ingress Cycles Not Empty; DRS event=0x10,umask=8 01 Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r2_rxr_cycles_ne.ncb uncore io Ingress Cycles Not Empty; NCB event=0x10,umask=0x10 01 Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r2_rxr_cycles_ne.ncs uncore io Ingress Cycles Not Empty; NCS event=0x10,umask=0x20 01 Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r2_txr_cycles_full.ad uncore io Egress Cycles Full; AD event=0x25,umask=1 01 Counts the number of cycles when the R2PCIe Egress buffer is full unc_r2_txr_cycles_full.ak uncore io Egress Cycles Full; AK event=0x25,umask=2 01 Counts the number of cycles when the R2PCIe Egress buffer is full unc_r2_txr_cycles_full.bl uncore io Egress Cycles Full; BL event=0x25,umask=4 01 Counts the number of cycles when the R2PCIe Egress buffer is full unc_r2_txr_cycles_ne.ad uncore io Egress Cycles Not Empty; AD event=0x23,umask=1 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_r2_txr_cycles_ne.ak uncore io Egress Cycles Not Empty; AK event=0x23,umask=2 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_r2_txr_cycles_ne.bl uncore io Egress Cycles Not Empty; BL event=0x23,umask=4 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_r2_txr_nacks.ad uncore io Egress NACK; AD event=0x26,umask=1 01 Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction unc_r2_txr_nacks.ak uncore io Egress NACK; AK event=0x26,umask=2 01 Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction unc_r2_txr_nacks.bl uncore io Egress NACK; BL event=0x26,umask=4 01 Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction unc_m_act_count uncore memory DRAM Activate Count event=1 01 Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_cas_count.all uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre) event=4,umask=0xf 01 unc_m_cas_count.rd uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills) event=4,umask=3 01 unc_m_cas_count.rd_reg uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre) event=4,umask=1 01 unc_m_cas_count.rd_underfill uncore memory DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued event=4,umask=2 01 unc_m_cas_count.wr uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes) event=4,umask=0xc 01 unc_m_cas_count.wr_rmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode event=4,umask=8 01 unc_m_cas_count.wr_wmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode event=4,umask=4 01 unc_m_clockticks uncore memory uclks event=0 01 Uncore Fixed Counter - uclks unc_m_major_modes.isoch uncore memory Cycles in a Major Mode; Isoch Major Mode event=7,umask=8 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_major_modes.partial uncore memory Cycles in a Major Mode; Partial Major Mode event=7,umask=4 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_major_modes.read uncore memory Cycles in a Major Mode; Read Major Mode event=7,umask=1 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_major_modes.write uncore memory Cycles in a Major Mode; Write Major Mode event=7,umask=2 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_power_throttle_cycles.rank0 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=1 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_preemption.rd_preempt_rd uncore memory Read Preemption Count; Read over Read Preemption event=8,umask=1 01 Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency unc_m_preemption.rd_preempt_wr uncore memory Read Preemption Count; Read over Write Preemption event=8,umask=2 01 Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency unc_m_pre_count.page_close uncore memory DRAM Precharge commands.; Precharge due to timer expiration event=2,umask=2 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.page_miss uncore memory DRAM Precharge commands.; Precharges due to page miss event=2,umask=1 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_rpq_occupancy uncore memory Read Pending Queue Occupancy event=0x80 01 Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_m_wpq_cycles_ne uncore memory Write Pending Queue Not Empty event=0x21 01 Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_inserts uncore memory Write Pending Queue Allocations event=0x20 01 Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC unc_m_wpq_occupancy uncore memory Write Pending Queue Occupancy event=0x81 01 Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_p_core0_transition_cycles uncore power Core C State Transition Cycles event=3 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core1_transition_cycles uncore power Core C State Transition Cycles event=4 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core2_transition_cycles uncore power Core C State Transition Cycles event=5 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core3_transition_cycles uncore power Core C State Transition Cycles event=6 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core4_transition_cycles uncore power Core C State Transition Cycles event=7 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core5_transition_cycles uncore power Core C State Transition Cycles event=8 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core6_transition_cycles uncore power Core C State Transition Cycles event=9 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core7_transition_cycles uncore power Core C State Transition Cycles event=0xa 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_demotions_core0 uncore power Core C State Demotions event=0x1e 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core1 uncore power Core C State Demotions event=0x1f 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core2 uncore power Core C State Demotions event=0x20 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core3 uncore power Core C State Demotions event=0x21 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core4 uncore power Core C State Demotions event=0x22 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core5 uncore power Core C State Demotions event=0x23 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core6 uncore power Core C State Demotions event=0x24 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core7 uncore power Core C State Demotions event=0x25 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=1 01 Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_min_perf_p_cycles uncore power Perf P Limit Strongest Lower Limit Cycles event=2 01 Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower. Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down. This is largely to minimize increases in snoop and remote read latencies unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0 01 Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C0 event=0x80,occ_sel=1 01 This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C0 event=0x80,occ_sel=2 01 This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C0 event=0x80,occ_sel=3 01 This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0xb 01 Number of cycles spent performing core C state transitions across all cores dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks event=8,period=100003,umask=1 00 dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=8,period=100003,umask=0x10 00 This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles dtlb_load_misses.walk_completed virtual memory Load misses at all DTLB levels that cause completed page walks event=8,period=100003,umask=2 00 dtlb_load_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=8,period=2000003,umask=4 00 This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks event=0x49,period=100003,umask=1 00 dtlb_store_misses.stlb_hit virtual memory Store operations that miss the first TLB level but hit the second and do not cause page walks event=0x49,period=100003,umask=0x10 00 dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks event=0x49,period=100003,umask=2 00 dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x49,period=2000003,umask=4 00 itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=1 00 itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=1 00 itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x10 00 itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks event=0x85,period=100003,umask=2 00 itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x85,period=2000003,umask=4 00 This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=1 00 tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20 00 core_reject_l2q.all cache Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path event=0x31,period=200003 00 fetch_stall.icache_fill_pending_cycles cache This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses event=0x86,period=200003,umask=4 00 l2_prefetcher.alloc_xq cache Counts the number of L2HWP allocated into XQ GP event=0x3e,period=100007,umask=4 00 l2_requests.miss cache Counts the number of L2 cache misses event=0x2e,period=200003,umask=0x41 00 l2_requests.reference cache Counts the total number of L2 cache references event=0x2e,period=200003,umask=0x4f 00 l2_requests_reject.all cache Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times event=0x30,period=200003 00 mem_uops_retired.all_loads cache Counts all the load micro-ops retired event=4,period=200003,umask=0x40 00 This event counts the number of load micro-ops retired mem_uops_retired.all_stores cache Counts all the store micro-ops retired event=4,period=200003,umask=0x80 00 This event counts the number of store micro-ops retired mem_uops_retired.hitm cache Counts the loads retired that get the data from the other core in the same tile in M state (Precise Event) Supports address when precise event=4,period=200003,umask=0x20 00 This event counts the number of load micro-ops retired that got data from another core's cache. (Precise Event) Supports address when precise mem_uops_retired.l1_miss_loads cache Counts the number of load micro-ops retired that miss in L1 D cache event=4,period=200003,umask=1 00 This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted mem_uops_retired.l2_hit_loads cache Counts the number of load micro-ops retired that hit in the L2 (Precise Event) Supports address when precise event=4,period=200003,umask=2 00 This event counts the number of load micro-uops retired that hit in the L2 (Precise Event) Supports address when precise mem_uops_retired.l2_miss_loads cache Counts the number of load micro-ops retired that miss in the L2 (Precise Event) Supports address when precise event=4,period=100007,umask=4 00 This event counts the number of load micro-ops retired that miss in the L2 (Precise Event) Supports address when precise mem_uops_retired.utlb_miss_loads cache Counts the number of load micro-ops retired that caused micro TLB miss event=4,period=200003,umask=0x10 00 offcore_response cache Counts the matrix events specified by MSR_OFFCORE_RESPx event=0xb7,period=100007,umask=1 00 offcore_response.any_code_rd.any_response cache Counts Demand code reads and prefetch code read requests that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010044 00 offcore_response.any_code_rd.l2_hit_far_tile cache Counts Demand code reads and prefetch code read requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400044 00 offcore_response.any_code_rd.l2_hit_far_tile_e_f cache Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400044 00 offcore_response.any_code_rd.l2_hit_far_tile_m cache Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400044 00 offcore_response.any_code_rd.l2_hit_near_tile cache Counts Demand code reads and prefetch code read requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180044 00 offcore_response.any_code_rd.l2_hit_near_tile_e_f cache Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080044 00 offcore_response.any_code_rd.l2_hit_near_tile_m cache Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080044 00 offcore_response.any_code_rd.l2_hit_this_tile_e cache Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000044 00 offcore_response.any_code_rd.l2_hit_this_tile_f cache Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000044 00 offcore_response.any_code_rd.l2_hit_this_tile_m cache Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000044 00 offcore_response.any_code_rd.l2_hit_this_tile_s cache Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000044 00 offcore_response.any_code_rd.outstanding cache Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000044 00 offcore_response.any_data_rd.any_response cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000013091 00 offcore_response.any_data_rd.l2_hit_far_tile cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800403091 00 offcore_response.any_data_rd.l2_hit_far_tile_e_f cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800403091 00 offcore_response.any_data_rd.l2_hit_far_tile_m cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000403091 00 offcore_response.any_data_rd.l2_hit_near_tile cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800183091 00 offcore_response.any_data_rd.l2_hit_near_tile_e_f cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800083091 00 offcore_response.any_data_rd.l2_hit_near_tile_m cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000083091 00 offcore_response.any_data_rd.l2_hit_this_tile_e cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004003091 00 offcore_response.any_data_rd.l2_hit_this_tile_f cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010003091 00 offcore_response.any_data_rd.l2_hit_this_tile_m cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002003091 00 offcore_response.any_data_rd.l2_hit_this_tile_s cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008003091 00 offcore_response.any_data_rd.outstanding cache Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000003091 00 offcore_response.any_pf_l2.any_response cache Counts any Prefetch requests that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010070 00 offcore_response.any_pf_l2.l2_hit_far_tile cache Counts any Prefetch requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400070 00 offcore_response.any_pf_l2.l2_hit_far_tile_e_f cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400070 00 offcore_response.any_pf_l2.l2_hit_far_tile_m cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400070 00 offcore_response.any_pf_l2.l2_hit_near_tile cache Counts any Prefetch requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180070 00 offcore_response.any_pf_l2.l2_hit_near_tile_e_f cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080070 00 offcore_response.any_pf_l2.l2_hit_near_tile_m cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080070 00 offcore_response.any_pf_l2.l2_hit_this_tile_e cache Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000070 00 offcore_response.any_pf_l2.l2_hit_this_tile_f cache Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000070 00 offcore_response.any_pf_l2.l2_hit_this_tile_m cache Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000070 00 offcore_response.any_pf_l2.outstanding cache Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000070 00 offcore_response.any_read.any_response cache Counts any Read request that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x00000132f7 00 offcore_response.any_read.l2_hit_far_tile cache Counts any Read request that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x18004032f7 00 offcore_response.any_read.l2_hit_far_tile_e_f cache Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x08004032f7 00 offcore_response.any_read.l2_hit_far_tile_m cache Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x10004032f7 00 offcore_response.any_read.l2_hit_near_tile cache Counts any Read request that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x18001832f7 00 offcore_response.any_read.l2_hit_near_tile_e_f cache Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x08000832f7 00 offcore_response.any_read.l2_hit_near_tile_m cache Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x10000832f7 00 offcore_response.any_read.l2_hit_this_tile_e cache Counts any Read request that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x00040032f7 00 offcore_response.any_read.l2_hit_this_tile_f cache Counts any Read request that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x00100032f7 00 offcore_response.any_read.l2_hit_this_tile_m cache Counts any Read request that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x00020032f7 00 offcore_response.any_read.l2_hit_this_tile_s cache Counts any Read request that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x00080032f7 00 offcore_response.any_read.outstanding cache Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x40000032f7 00 offcore_response.any_request.any_response cache Counts any request that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000018000 00 offcore_response.any_request.l2_hit_far_tile cache Counts any request that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800408000 00 offcore_response.any_request.l2_hit_far_tile_e_f cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800408000 00 offcore_response.any_request.l2_hit_far_tile_m cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000408000 00 offcore_response.any_request.l2_hit_near_tile cache Counts any request that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800188000 00 offcore_response.any_request.l2_hit_near_tile_e_f cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800088000 00 offcore_response.any_request.l2_hit_near_tile_m cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000088000 00 offcore_response.any_request.l2_hit_this_tile_e cache Counts any request that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004008000 00 offcore_response.any_request.l2_hit_this_tile_f cache Counts any request that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010008000 00 offcore_response.any_request.l2_hit_this_tile_m cache Counts any request that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002008000 00 offcore_response.any_request.l2_hit_this_tile_s cache Counts any request that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008008000 00 offcore_response.any_request.l2_miss cache Accounts for responses which miss its own tile's L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x18001981F8 00 offcore_response.any_request.outstanding cache Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000008000 00 offcore_response.any_rfo.any_response cache Counts Demand cacheable data write requests that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010022 00 offcore_response.any_rfo.l2_hit_far_tile cache Counts Demand cacheable data write requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400022 00 offcore_response.any_rfo.l2_hit_far_tile_e_f cache Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400022 00 offcore_response.any_rfo.l2_hit_far_tile_m cache Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400022 00 offcore_response.any_rfo.l2_hit_near_tile cache Counts Demand cacheable data write requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180022 00 offcore_response.any_rfo.l2_hit_near_tile_e_f cache Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080022 00 offcore_response.any_rfo.l2_hit_near_tile_m cache Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080022 00 offcore_response.any_rfo.l2_hit_this_tile_e cache Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000022 00 offcore_response.any_rfo.l2_hit_this_tile_f cache Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000022 00 offcore_response.any_rfo.l2_hit_this_tile_m cache Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000022 00 offcore_response.any_rfo.l2_hit_this_tile_s cache Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000022 00 offcore_response.any_rfo.outstanding cache Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000022 00 offcore_response.bus_locks.any_response cache Counts Bus locks and split lock requests that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010400 00 offcore_response.bus_locks.l2_hit_far_tile cache Counts Bus locks and split lock requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400400 00 offcore_response.bus_locks.l2_hit_far_tile_e_f cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400400 00 offcore_response.bus_locks.l2_hit_far_tile_m cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400400 00 offcore_response.bus_locks.l2_hit_near_tile cache Counts Bus locks and split lock requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180400 00 offcore_response.bus_locks.l2_hit_near_tile_e_f cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080400 00 offcore_response.bus_locks.l2_hit_near_tile_m cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080400 00 offcore_response.bus_locks.l2_hit_this_tile_e cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000400 00 offcore_response.bus_locks.l2_hit_this_tile_f cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000400 00 offcore_response.bus_locks.l2_hit_this_tile_m cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000400 00 offcore_response.bus_locks.l2_hit_this_tile_s cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000400 00 offcore_response.bus_locks.outstanding cache Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000400 00 offcore_response.demand_code_rd.any_response cache Counts demand code reads and prefetch code reads that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010004 00 offcore_response.demand_code_rd.l2_hit_far_tile cache Counts demand code reads and prefetch code reads that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400004 00 offcore_response.demand_code_rd.l2_hit_far_tile_e_f cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400004 00 offcore_response.demand_code_rd.l2_hit_far_tile_m cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400004 00 offcore_response.demand_code_rd.l2_hit_near_tile cache Counts demand code reads and prefetch code reads that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180004 00 offcore_response.demand_code_rd.l2_hit_near_tile_e_f cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080004 00 offcore_response.demand_code_rd.l2_hit_near_tile_m cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080004 00 offcore_response.demand_code_rd.l2_hit_this_tile_e cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000004 00 offcore_response.demand_code_rd.l2_hit_this_tile_f cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000004 00 offcore_response.demand_code_rd.l2_hit_this_tile_m cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000004 00 offcore_response.demand_code_rd.l2_hit_this_tile_s cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000004 00 offcore_response.demand_code_rd.outstanding cache Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000004 00 offcore_response.demand_data_rd.any_response cache Counts demand cacheable data and L1 prefetch data reads that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010001 00 offcore_response.demand_data_rd.l2_hit_far_tile_e_f cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400001 00 offcore_response.demand_data_rd.l2_hit_far_tile_m cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400001 00 offcore_response.demand_data_rd.l2_hit_near_tile_e_f cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080001 00 offcore_response.demand_data_rd.l2_hit_near_tile_m cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080001 00 offcore_response.demand_data_rd.l2_hit_this_tile_e cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000001 00 offcore_response.demand_data_rd.l2_hit_this_tile_f cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000001 00 offcore_response.demand_data_rd.l2_hit_this_tile_m cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000001 00 offcore_response.demand_data_rd.l2_hit_this_tile_s cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000001 00 offcore_response.demand_data_rd.outstanding cache Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000001 00 offcore_response.demand_rfo.any_response cache Counts Demand cacheable data writes that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010002 00 offcore_response.demand_rfo.l2_hit_far_tile cache Counts Demand cacheable data writes that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400002 00 offcore_response.demand_rfo.l2_hit_far_tile_e_f cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400002 00 offcore_response.demand_rfo.l2_hit_far_tile_m cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400002 00 offcore_response.demand_rfo.l2_hit_near_tile cache Counts Demand cacheable data writes that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180002 00 offcore_response.demand_rfo.l2_hit_near_tile_e_f cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080002 00 offcore_response.demand_rfo.l2_hit_near_tile_m cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080002 00 offcore_response.demand_rfo.l2_hit_this_tile_e cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000002 00 offcore_response.demand_rfo.l2_hit_this_tile_f cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000002 00 offcore_response.demand_rfo.l2_hit_this_tile_m cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000002 00 offcore_response.demand_rfo.l2_hit_this_tile_s cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000002 00 offcore_response.demand_rfo.outstanding cache Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000002 00 offcore_response.full_streaming_stores.any_response cache Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010800 00 offcore_response.partial_reads.any_response cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010080 00 offcore_response.partial_reads.l2_hit_far_tile cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400080 00 offcore_response.partial_reads.l2_hit_far_tile_e_f cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400080 00 offcore_response.partial_reads.l2_hit_far_tile_m cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400080 00 offcore_response.partial_reads.l2_hit_near_tile cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180080 00 offcore_response.partial_reads.l2_hit_near_tile_e_f cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080080 00 offcore_response.partial_reads.l2_hit_near_tile_m cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080080 00 offcore_response.partial_reads.l2_hit_this_tile_e cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000080 00 offcore_response.partial_reads.l2_hit_this_tile_f cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000080 00 offcore_response.partial_reads.l2_hit_this_tile_m cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000080 00 offcore_response.partial_reads.l2_hit_this_tile_s cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000080 00 offcore_response.partial_reads.outstanding cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000080 00 offcore_response.partial_streaming_stores.any_response cache Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000014000 00 offcore_response.partial_writes.any_response cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010100 00 offcore_response.partial_writes.l2_hit_far_tile cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400100 00 offcore_response.partial_writes.l2_hit_far_tile_e_f cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400100 00 offcore_response.partial_writes.l2_hit_far_tile_m cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400100 00 offcore_response.partial_writes.l2_hit_near_tile cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180100 00 offcore_response.partial_writes.l2_hit_near_tile_e_f cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080100 00 offcore_response.partial_writes.l2_hit_near_tile_m cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080100 00 offcore_response.partial_writes.l2_hit_this_tile_e cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000100 00 offcore_response.partial_writes.l2_hit_this_tile_f cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000100 00 offcore_response.partial_writes.l2_hit_this_tile_m cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000100 00 offcore_response.partial_writes.l2_hit_this_tile_s cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000100 00 offcore_response.pf_l1_data_rd.any_response cache Counts L1 data HW prefetches that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000012000 00 offcore_response.pf_l1_data_rd.l2_hit_far_tile cache Counts L1 data HW prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800402000 00 offcore_response.pf_l1_data_rd.l2_hit_far_tile_e_f cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800402000 00 offcore_response.pf_l1_data_rd.l2_hit_far_tile_m cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000402000 00 offcore_response.pf_l1_data_rd.l2_hit_near_tile cache Counts L1 data HW prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800182000 00 offcore_response.pf_l1_data_rd.l2_hit_near_tile_e_f cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800082000 00 offcore_response.pf_l1_data_rd.l2_hit_near_tile_m cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000082000 00 offcore_response.pf_l1_data_rd.l2_hit_this_tile_e cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004002000 00 offcore_response.pf_l1_data_rd.l2_hit_this_tile_f cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010002000 00 offcore_response.pf_l1_data_rd.l2_hit_this_tile_m cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002002000 00 offcore_response.pf_l1_data_rd.l2_hit_this_tile_s cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008002000 00 offcore_response.pf_l1_data_rd.outstanding cache Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000002000 00 offcore_response.pf_l2_code_rd.any_response cache Counts L2 code HW prefetches that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010040 00 offcore_response.pf_l2_code_rd.l2_hit_far_tile cache Counts L2 code HW prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400040 00 offcore_response.pf_l2_code_rd.l2_hit_far_tile_e_f cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400040 00 offcore_response.pf_l2_code_rd.l2_hit_far_tile_m cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400040 00 offcore_response.pf_l2_code_rd.l2_hit_near_tile cache Counts L2 code HW prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180040 00 offcore_response.pf_l2_code_rd.l2_hit_near_tile_e_f cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080040 00 offcore_response.pf_l2_code_rd.l2_hit_near_tile_m cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080040 00 offcore_response.pf_l2_code_rd.l2_hit_this_tile_e cache Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000040 00 offcore_response.pf_l2_code_rd.l2_hit_this_tile_f cache Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000040 00 offcore_response.pf_l2_code_rd.outstanding cache Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000040 00 offcore_response.pf_l2_rfo.any_response cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010020 00 offcore_response.pf_l2_rfo.l2_hit_far_tile_e_f cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400020 00 offcore_response.pf_l2_rfo.l2_hit_far_tile_m cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400020 00 offcore_response.pf_l2_rfo.l2_hit_near_tile cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180020 00 offcore_response.pf_l2_rfo.l2_hit_near_tile_e_f cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080020 00 offcore_response.pf_l2_rfo.l2_hit_near_tile_m cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080020 00 offcore_response.pf_l2_rfo.l2_hit_this_tile_e cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000020 00 offcore_response.pf_l2_rfo.l2_hit_this_tile_f cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000020 00 offcore_response.pf_l2_rfo.l2_hit_this_tile_m cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000020 00 offcore_response.pf_l2_rfo.l2_hit_this_tile_s cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000020 00 offcore_response.pf_software.any_response cache Counts Software Prefetches that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000011000 00 offcore_response.pf_software.l2_hit_far_tile cache Counts Software Prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800401000 00 offcore_response.pf_software.l2_hit_far_tile_e_f cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800401000 00 offcore_response.pf_software.l2_hit_far_tile_m cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000401000 00 offcore_response.pf_software.l2_hit_near_tile cache Counts Software Prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800181000 00 offcore_response.pf_software.l2_hit_near_tile_e_f cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800081000 00 offcore_response.pf_software.l2_hit_near_tile_m cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000081000 00 offcore_response.pf_software.l2_hit_this_tile_e cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004001000 00 offcore_response.pf_software.l2_hit_this_tile_f cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010001000 00 offcore_response.pf_software.l2_hit_this_tile_m cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002001000 00 offcore_response.pf_software.l2_hit_this_tile_s cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008001000 00 offcore_response.pf_software.outstanding cache Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000001000 00 offcore_response.streaming_stores.any_response cache Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000014800 00 offcore_response.uc_code_reads.any_response cache Counts UC code reads (valid only for Outstanding response type) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010200 00 offcore_response.uc_code_reads.l2_hit_far_tile_e_f cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400200 00 offcore_response.uc_code_reads.l2_hit_far_tile_m cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400200 00 offcore_response.uc_code_reads.l2_hit_near_tile cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180200 00 offcore_response.uc_code_reads.l2_hit_near_tile_e_f cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080200 00 offcore_response.uc_code_reads.l2_hit_near_tile_m cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080200 00 offcore_response.uc_code_reads.l2_hit_this_tile_e cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000200 00 offcore_response.uc_code_reads.l2_hit_this_tile_f cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000200 00 offcore_response.uc_code_reads.l2_hit_this_tile_m cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000200 00 offcore_response.uc_code_reads.l2_hit_this_tile_s cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000200 00 offcore_response.uc_code_reads.outstanding cache Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000200 00 machine_clears.fp_assist floating point Counts the number of floating operations retired that required microcode assists event=0xc3,period=200003,umask=4 00 This event counts the number of times that the pipeline stalled due to FP operations needing assists uops_retired.packed_simd floating point Counts the number of packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies event=0xc2,period=200003,umask=0x40 00 The length of the packed operation (128bits, 256bits or 512bits) is not taken into account when updating the counter; all count the same (+1). Mask (k) registers are ignored. For example: a micro-op operating with a mask that only enables one element or even zero elements will still trigger this counter (+1) This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all uops_retired.scalar_simd floating point Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt event=0xc2,period=200003,umask=0x20 00 This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all baclears.all frontend Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end event=0xe6,period=200003,umask=1 00 baclears.cond frontend Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end event=0xe6,period=200003,umask=0x10 00 baclears.return frontend Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end event=0xe6,period=200003,umask=8 00 icache.accesses frontend Counts all instruction fetches, including uncacheable fetches event=0x80,period=200003,umask=3 00 icache.hit frontend Counts all instruction fetches that hit the instruction cache event=0x80,period=200003,umask=1 00 icache.misses frontend Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding event=0x80,period=200003,umask=2 00 ms_decoded.ms_entry frontend Counts the number of times the MSROM starts a flow of uops event=0xe7,period=200003,umask=1 00 machine_clears.memory_ordering memory Counts the number of times the machine clears due to memory ordering hazards event=0xc3,period=200003,umask=2 00 offcore_response.any_code_rd.ddr memory Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800044 00 offcore_response.any_code_rd.ddr_far memory Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000044 00 offcore_response.any_code_rd.ddr_near memory Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800044 00 offcore_response.any_code_rd.mcdram memory Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600044 00 offcore_response.any_code_rd.mcdram_far memory Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400044 00 offcore_response.any_code_rd.mcdram_near memory Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200044 00 offcore_response.any_data_rd.ddr memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181803091 00 offcore_response.any_data_rd.ddr_far memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101003091 00 offcore_response.any_data_rd.ddr_near memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080803091 00 offcore_response.any_data_rd.mcdram memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180603091 00 offcore_response.any_data_rd.mcdram_far memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100403091 00 offcore_response.any_data_rd.mcdram_near memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080203091 00 offcore_response.any_pf_l2.ddr_far memory Counts any Prefetch requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000070 00 offcore_response.any_pf_l2.ddr_near memory Counts any Prefetch requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800070 00 offcore_response.any_pf_l2.mcdram memory Counts any Prefetch requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600070 00 offcore_response.any_pf_l2.mcdram_far memory Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400070 00 offcore_response.any_pf_l2.mcdram_near memory Counts any Prefetch requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200070 00 offcore_response.any_read.ddr memory Counts any Read request that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x01818032f7 00 offcore_response.any_read.ddr_far memory Counts any Read request that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x01010032f7 00 offcore_response.any_read.ddr_near memory Counts any Read request that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x00808032f7 00 offcore_response.any_read.mcdram memory Counts any Read request that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x01806032f7 00 offcore_response.any_read.mcdram_far memory Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x01004032f7 00 offcore_response.any_read.mcdram_near memory Counts any Read request that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x00802032f7 00 offcore_response.any_request.ddr memory Counts any request that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181808000 00 offcore_response.any_request.ddr_far memory Counts any request that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101008000 00 offcore_response.any_request.ddr_near memory Counts any request that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080808000 00 offcore_response.any_request.mcdram memory Counts any request that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180608000 00 offcore_response.any_request.mcdram_far memory Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100408000 00 offcore_response.any_request.mcdram_near memory Counts any request that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080208000 00 offcore_response.any_rfo.ddr memory Counts Demand cacheable data write requests that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800022 00 offcore_response.any_rfo.ddr_far memory Counts Demand cacheable data write requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000022 00 offcore_response.any_rfo.ddr_near memory Counts Demand cacheable data write requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800022 00 offcore_response.any_rfo.mcdram memory Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600022 00 offcore_response.any_rfo.mcdram_far memory Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400022 00 offcore_response.any_rfo.mcdram_near memory Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200022 00 offcore_response.bus_locks.ddr memory Counts Bus locks and split lock requests that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800400 00 offcore_response.bus_locks.ddr_far memory Counts Bus locks and split lock requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000400 00 offcore_response.bus_locks.ddr_near memory Counts Bus locks and split lock requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800400 00 offcore_response.bus_locks.mcdram memory Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600400 00 offcore_response.bus_locks.mcdram_far memory Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400400 00 offcore_response.bus_locks.mcdram_near memory Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200400 00 offcore_response.demand_code_rd.ddr memory Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800004 00 offcore_response.demand_code_rd.ddr_far memory Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000004 00 offcore_response.demand_code_rd.ddr_near memory Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800004 00 offcore_response.demand_code_rd.mcdram memory Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600004 00 offcore_response.demand_code_rd.mcdram_far memory Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400004 00 offcore_response.demand_code_rd.mcdram_near memory Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200004 00 offcore_response.demand_data_rd.ddr memory Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800001 00 offcore_response.demand_data_rd.ddr_far memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000001 00 offcore_response.demand_data_rd.ddr_near memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800001 00 offcore_response.demand_data_rd.mcdram memory Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600001 00 offcore_response.demand_data_rd.mcdram_far memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400001 00 offcore_response.demand_data_rd.mcdram_near memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200001 00 offcore_response.demand_rfo.ddr memory Counts Demand cacheable data writes that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800002 00 offcore_response.demand_rfo.ddr_far memory Counts Demand cacheable data writes that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000002 00 offcore_response.demand_rfo.ddr_near memory Counts Demand cacheable data writes that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800002 00 offcore_response.demand_rfo.mcdram memory Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600002 00 offcore_response.demand_rfo.mcdram_far memory Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400002 00 offcore_response.demand_rfo.mcdram_near memory Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200002 00 offcore_response.partial_reads.ddr memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800080 00 offcore_response.partial_reads.ddr_far memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000080 00 offcore_response.partial_reads.ddr_near memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800080 00 offcore_response.partial_reads.mcdram memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600080 00 offcore_response.partial_reads.mcdram_far memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400080 00 offcore_response.partial_reads.mcdram_near memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200080 00 offcore_response.partial_reads.non_dram memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions event=0xb7,period=100007,umask=1,offcore_rsp=0x2000020080 00 offcore_response.partial_writes.ddr_far memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000100 00 offcore_response.partial_writes.ddr_near memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800100 00 offcore_response.partial_writes.mcdram memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600100 00 offcore_response.partial_writes.mcdram_far memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400100 00 offcore_response.partial_writes.mcdram_near memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200100 00 offcore_response.pf_l1_data_rd.ddr memory Counts L1 data HW prefetches that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181802000 00 offcore_response.pf_l1_data_rd.ddr_far memory Counts L1 data HW prefetches that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101002000 00 offcore_response.pf_l1_data_rd.ddr_near memory Counts L1 data HW prefetches that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080802000 00 offcore_response.pf_l1_data_rd.mcdram_far memory Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100402000 00 offcore_response.pf_l1_data_rd.mcdram_near memory Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080202000 00 offcore_response.pf_l2_code_rd.ddr memory Counts L2 code HW prefetches that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800040 00 offcore_response.pf_l2_code_rd.ddr_far memory Counts L2 code HW prefetches that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000040 00 offcore_response.pf_l2_code_rd.ddr_near memory Counts L2 code HW prefetches that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800040 00 offcore_response.pf_l2_code_rd.mcdram_far memory Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400040 00 offcore_response.pf_l2_code_rd.mcdram_near memory Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200040 00 offcore_response.pf_l2_rfo.ddr memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800020 00 offcore_response.pf_l2_rfo.ddr_far memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000020 00 offcore_response.pf_l2_rfo.ddr_near memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800020 00 offcore_response.pf_l2_rfo.mcdram memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600020 00 offcore_response.pf_l2_rfo.mcdram_far memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400020 00 offcore_response.pf_l2_rfo.mcdram_near memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200020 00 offcore_response.pf_l2_rfo.non_dram memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions event=0xb7,period=100007,umask=1,offcore_rsp=0x2000020020 00 offcore_response.pf_software.ddr memory Counts Software Prefetches that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181801000 00 offcore_response.pf_software.ddr_far memory Counts Software Prefetches that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101001000 00 offcore_response.pf_software.ddr_near memory Counts Software Prefetches that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080801000 00 offcore_response.pf_software.mcdram memory Counts Software Prefetches that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180601000 00 offcore_response.pf_software.mcdram_far memory Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100401000 00 offcore_response.pf_software.mcdram_near memory Counts Software Prefetches that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080201000 00 offcore_response.uc_code_reads.ddr memory Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800200 00 offcore_response.uc_code_reads.ddr_far memory Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000200 00 offcore_response.uc_code_reads.ddr_near memory Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800200 00 offcore_response.uc_code_reads.mcdram memory Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600200 00 offcore_response.uc_code_reads.mcdram_far memory Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400200 00 offcore_response.uc_code_reads.mcdram_near memory Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200200 00 br_inst_retired.all_branches pipeline Counts the number of branch instructions retired (Precise Event) event=0xc4,period=200003 00 br_inst_retired.call pipeline Counts the number of near CALL branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xf9 00 br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xbf 00 br_inst_retired.ind_call pipeline Counts the number of near indirect CALL branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xfb 00 br_inst_retired.jcc pipeline Counts the number of branch instructions retired that were conditional jumps. (Precise Event) event=0xc4,period=200003,umask=0x7e 00 br_inst_retired.non_return_ind pipeline Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event) event=0xc4,period=200003,umask=0xeb 00 br_inst_retired.rel_call pipeline Counts the number of near relative CALL branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xfd 00 br_inst_retired.return pipeline Counts the number of near RET branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xf7 00 br_inst_retired.taken_jcc pipeline Counts the number of branch instructions retired that were conditional jumps and predicted taken. (Precise Event) event=0xc4,period=200003,umask=0xfe 00 br_misp_retired.all_branches pipeline Counts the number of mispredicted branch instructions retired (Precise Event) event=0xc5,period=200003 00 br_misp_retired.call pipeline Counts the number of mispredicted near CALL branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xf9 00 br_misp_retired.far_branch pipeline Counts the number of mispredicted far branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xbf 00 br_misp_retired.ind_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xfb 00 br_misp_retired.jcc pipeline Counts the number of mispredicted branch instructions retired that were conditional jumps. (Precise Event) event=0xc5,period=200003,umask=0x7e 00 br_misp_retired.non_return_ind pipeline Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event) event=0xc5,period=200003,umask=0xeb 00 br_misp_retired.rel_call pipeline Counts the number of mispredicted near relative CALL branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xfd 00 br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xf7 00 br_misp_retired.taken_jcc pipeline Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken. (Precise Event) event=0xc5,period=200003,umask=0xfe 00 cpu_clk_unhalted.ref pipeline Counts the number of unhalted reference clock cycles event=0x0,umask=0x03,period=2000003 00 cpu_clk_unhalted.thread pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 cycles_div_busy.all pipeline Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider event=0xcd,period=2000003,umask=1 00 This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides inst_retired.any pipeline Fixed Counter: Counts the number of instructions retired event=0xc0,period=2000003 00 This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps inst_retired.any_p pipeline Counts the total number of instructions retired event=0xc0,period=2000003 00 inst_retired.any_ps pipeline Counts the number of instructions retired (Precise Event) event=0xc0,period=2000003 00 machine_clears.all pipeline Counts all machine clears event=0xc3,period=200003,umask=8 00 machine_clears.smc pipeline Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page event=0xc3,period=200003,umask=1 00 no_alloc_cycles.all pipeline Counts the total number of core cycles when no micro-ops are allocated for any reason event=0xca,period=200003,umask=0x7f 00 no_alloc_cycles.mispredicts pipeline Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire event=0xca,period=200003,umask=4 00 This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire no_alloc_cycles.not_delivered pipeline Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation event=0xca,period=200003,umask=0x90 00 This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched no_alloc_cycles.rat_stall pipeline Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted event=0xca,period=200003,umask=0x20 00 no_alloc_cycles.rob_full pipeline Counts the number of core cycles when no micro-ops are allocated and the ROB is full event=0xca,period=200003,umask=1 00 recycleq.any_ld pipeline Counts any retired load that was pushed into the recycle queue for any reason event=3,period=200003,umask=0x40 00 recycleq.any_st pipeline Counts any retired store that was pushed into the recycle queue for any reason event=3,period=200003,umask=0x80 00 recycleq.ld_block_std_notready pipeline Counts the number of occurrences a retired load gets blocked because its address overlaps with a store whose data is not ready event=3,period=200003,umask=2 00 recycleq.ld_block_st_forward pipeline Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store (Precise Event) Supports address when precise event=3,period=200003,umask=1 00 This event counts the number of retired loads that were prohibited from receiving forwarded data from a previous store because of address mismatch Supports address when precise recycleq.ld_splits pipeline Counts the number of occurrences a retired load was pushed into the rehab queue because it sees a cache line split. Each split should be counted only once. (Precise Event) Supports address when precise event=3,period=200003,umask=8 00 This event counts the number of retired loads which was pushed into the recycled queue that experienced cache line boundary splits (Precise event). Not that each split should be counted only once Supports address when precise recycleq.lock pipeline Counts all the retired locked loads. It does not include stores because we would double count if we count stores event=3,period=200003,umask=0x10 00 recycleq.sta_full pipeline Counts the store micro-ops retired that were pushed in the rehab queue because the store address buffer is full event=3,period=200003,umask=0x20 00 recycleq.st_splits pipeline Counts the number of occurrences a retired store that is a cache line split. Each split should be counted only once event=3,period=200003,umask=4 00 This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once rs_full_stall.all pipeline Counts the total number of core cycles allocation pipeline is stalled when any one of the reservation stations is full event=0xcb,period=200003,umask=0x1f 00 rs_full_stall.mec pipeline Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry event=0xcb,period=200003,umask=1 00 uops_retired.all pipeline Counts the number of micro-ops retired event=0xc2,period=2000003,umask=0x10 00 This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists uops_retired.ms pipeline Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS) event=0xc2,period=2000003,umask=1 00 This event counts the number of micro-ops retired that were supplied from MSROM unc_c_tor_inserts.ipq_hit uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ event=0x35,umask=0x18 01 unc_c_tor_inserts.ipq_miss uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ event=0x35,umask=0x28 01 unc_c_tor_inserts.irq_hit uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ event=0x35,umask=0x11 01 unc_c_tor_inserts.irq_miss uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ event=0x35,umask=0x21 01 unc_c_tor_inserts.loc_all uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ or PRQ event=0x35,umask=0x37 01 unc_c_tor_inserts.prq_hit uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ event=0x35,umask=0x14 01 unc_c_tor_inserts.prq_miss uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ event=0x35,umask=0x24 01 unc_h_ag0_ad_crd_acquired.tgr0 uncore cache CMS Agent0 AD Credits Acquired For Transgress 0 event=0x80,umask=1 01 unc_h_ag0_ad_crd_acquired.tgr1 uncore cache CMS Agent0 AD Credits Acquired For Transgress 1 event=0x80,umask=2 01 unc_h_ag0_ad_crd_acquired.tgr2 uncore cache CMS Agent0 AD Credits Acquired For Transgress 2 event=0x80,umask=4 01 unc_h_ag0_ad_crd_acquired.tgr3 uncore cache CMS Agent0 AD Credits Acquired For Transgress 3 event=0x80,umask=8 01 unc_h_ag0_ad_crd_acquired.tgr4 uncore cache CMS Agent0 AD Credits Acquired For Transgress 4 event=0x80,umask=0x10 01 unc_h_ag0_ad_crd_acquired.tgr5 uncore cache CMS Agent0 AD Credits Acquired For Transgress 5 event=0x80,umask=0x20 01 unc_h_ag0_ad_crd_acquired.tgr6 uncore cache CMS Agent0 AD Credits Acquired For Transgress 6 event=0x80,umask=0x40 01 unc_h_ag0_ad_crd_acquired.tgr7 uncore cache CMS Agent0 AD Credits Acquired For Transgress 7 event=0x80,umask=0x80 01 unc_h_ag0_ad_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 AD Credits Acquired For Transgress 0-7 event=0x81,umask=2 01 unc_h_ag0_ad_crd_acquired_ext.tgr8 uncore cache CMS Agent0 AD Credits Acquired For Transgress 8 event=0x81,umask=1 01 unc_h_ag0_ad_crd_occupancy.tgr0 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 0 event=0x82,umask=1 01 unc_h_ag0_ad_crd_occupancy.tgr1 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 1 event=0x82,umask=2 01 unc_h_ag0_ad_crd_occupancy.tgr2 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 2 event=0x82,umask=4 01 unc_h_ag0_ad_crd_occupancy.tgr3 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 3 event=0x82,umask=8 01 unc_h_ag0_ad_crd_occupancy.tgr4 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 4 event=0x82,umask=0x10 01 unc_h_ag0_ad_crd_occupancy.tgr5 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 5 event=0x82,umask=0x20 01 unc_h_ag0_ad_crd_occupancy.tgr6 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 6 event=0x82,umask=0x40 01 unc_h_ag0_ad_crd_occupancy.tgr7 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 7 event=0x82,umask=0x80 01 unc_h_ag0_ad_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 0-7 event=0x83,umask=2 01 unc_h_ag0_ad_crd_occupancy_ext.tgr8 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 8 event=0x83,umask=1 01 unc_h_ag0_bl_crd_acquired.tgr0 uncore cache CMS Agent0 BL Credits Acquired For Transgress 0 event=0x88,umask=1 01 unc_h_ag0_bl_crd_acquired.tgr1 uncore cache CMS Agent0 BL Credits Acquired For Transgress 1 event=0x88,umask=2 01 unc_h_ag0_bl_crd_acquired.tgr2 uncore cache CMS Agent0 BL Credits Acquired For Transgress 2 event=0x88,umask=4 01 unc_h_ag0_bl_crd_acquired.tgr3 uncore cache CMS Agent0 BL Credits Acquired For Transgress 3 event=0x88,umask=8 01 unc_h_ag0_bl_crd_acquired.tgr4 uncore cache CMS Agent0 BL Credits Acquired For Transgress 4 event=0x88,umask=0x10 01 unc_h_ag0_bl_crd_acquired.tgr5 uncore cache CMS Agent0 BL Credits Acquired For Transgress 5 event=0x88,umask=0x20 01 unc_h_ag0_bl_crd_acquired.tgr6 uncore cache CMS Agent0 BL Credits Acquired For Transgress 6 event=0x88,umask=0x40 01 unc_h_ag0_bl_crd_acquired.tgr7 uncore cache CMS Agent0 BL Credits Acquired For Transgress 7 event=0x88,umask=0x80 01 unc_h_ag0_bl_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 BL Credits Acquired For Transgress 0-7 event=0x89,umask=2 01 unc_h_ag0_bl_crd_acquired_ext.tgr8 uncore cache CMS Agent0 BL Credits Acquired For Transgress 8 event=0x89,umask=1 01 unc_h_ag0_bl_crd_occupancy.tgr0 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 0 event=0x8a,umask=1 01 unc_h_ag0_bl_crd_occupancy.tgr1 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 1 event=0x8a,umask=2 01 unc_h_ag0_bl_crd_occupancy.tgr2 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 2 event=0x8a,umask=4 01 unc_h_ag0_bl_crd_occupancy.tgr3 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 3 event=0x8a,umask=8 01 unc_h_ag0_bl_crd_occupancy.tgr4 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 4 event=0x8a,umask=0x10 01 unc_h_ag0_bl_crd_occupancy.tgr5 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 5 event=0x8a,umask=0x20 01 unc_h_ag0_bl_crd_occupancy.tgr6 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 6 event=0x8a,umask=0x40 01 unc_h_ag0_bl_crd_occupancy.tgr7 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 7 event=0x8a,umask=0x80 01 unc_h_ag0_bl_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 0-7 event=0x8b,umask=2 01 unc_h_ag0_bl_crd_occupancy_ext.tgr8 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 8 event=0x8b,umask=1 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd0,umask=1 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd0,umask=2 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd0,umask=4 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd0,umask=8 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd0,umask=0x10 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd0,umask=0x20 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd0,umask=0x40 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd0,umask=0x80 01 unc_h_ag0_stall_no_crd_egress_horz_ad_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd1,umask=2 01 unc_h_ag0_stall_no_crd_egress_horz_ad_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd1,umask=1 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd4,umask=1 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd4,umask=2 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd4,umask=4 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd4,umask=8 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd4,umask=0x10 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd4,umask=0x20 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd4,umask=0x40 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd4,umask=0x80 01 unc_h_ag0_stall_no_crd_egress_horz_bl_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd5,umask=2 01 unc_h_ag0_stall_no_crd_egress_horz_bl_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd5,umask=1 01 unc_h_ag1_ad_crd_acquired.tgr0 uncore cache CMS Agent1 AD Credits Acquired For Transgress 0 event=0x84,umask=1 01 unc_h_ag1_ad_crd_acquired.tgr1 uncore cache CMS Agent1 AD Credits Acquired For Transgress 1 event=0x84,umask=2 01 unc_h_ag1_ad_crd_acquired.tgr2 uncore cache CMS Agent1 AD Credits Acquired For Transgress 2 event=0x84,umask=4 01 unc_h_ag1_ad_crd_acquired.tgr3 uncore cache CMS Agent1 AD Credits Acquired For Transgress 3 event=0x84,umask=8 01 unc_h_ag1_ad_crd_acquired.tgr4 uncore cache CMS Agent1 AD Credits Acquired For Transgress 4 event=0x84,umask=0x10 01 unc_h_ag1_ad_crd_acquired.tgr5 uncore cache CMS Agent1 AD Credits Acquired For Transgress 5 event=0x84,umask=0x20 01 unc_h_ag1_ad_crd_acquired.tgr6 uncore cache CMS Agent1 AD Credits Acquired For Transgress 6 event=0x84,umask=0x40 01 unc_h_ag1_ad_crd_acquired.tgr7 uncore cache CMS Agent1 AD Credits Acquired For Transgress 7 event=0x84,umask=0x80 01 unc_h_ag1_ad_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 AD Credits Acquired For Transgress 0-7 event=0x85,umask=2 01 unc_h_ag1_ad_crd_acquired_ext.tgr8 uncore cache CMS Agent1 AD Credits Acquired For Transgress 8 event=0x85,umask=1 01 unc_h_ag1_ad_crd_occupancy.tgr0 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 0 event=0x86,umask=1 01 unc_h_ag1_ad_crd_occupancy.tgr1 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 1 event=0x86,umask=2 01 unc_h_ag1_ad_crd_occupancy.tgr2 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 2 event=0x86,umask=4 01 unc_h_ag1_ad_crd_occupancy.tgr3 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 3 event=0x86,umask=8 01 unc_h_ag1_ad_crd_occupancy.tgr4 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 4 event=0x86,umask=0x10 01 unc_h_ag1_ad_crd_occupancy.tgr5 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 5 event=0x86,umask=0x20 01 unc_h_ag1_ad_crd_occupancy.tgr6 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 6 event=0x86,umask=0x40 01 unc_h_ag1_ad_crd_occupancy.tgr7 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 7 event=0x86,umask=0x80 01 unc_h_ag1_ad_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 0-7 event=0x87,umask=2 01 unc_h_ag1_ad_crd_occupancy_ext.tgr8 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 8 event=0x87,umask=1 01 unc_h_ag1_bl_crd_acquired.tgr0 uncore cache CMS Agent1 BL Credits Acquired For Transgress 0 event=0x8c,umask=1 01 unc_h_ag1_bl_crd_acquired.tgr1 uncore cache CMS Agent1 BL Credits Acquired For Transgress 1 event=0x8c,umask=2 01 unc_h_ag1_bl_crd_acquired.tgr2 uncore cache CMS Agent1 BL Credits Acquired For Transgress 2 event=0x8c,umask=4 01 unc_h_ag1_bl_crd_acquired.tgr3 uncore cache CMS Agent1 BL Credits Acquired For Transgress 3 event=0x8c,umask=8 01 unc_h_ag1_bl_crd_acquired.tgr4 uncore cache CMS Agent1 BL Credits Acquired For Transgress 4 event=0x8c,umask=0x10 01 unc_h_ag1_bl_crd_acquired.tgr5 uncore cache CMS Agent1 BL Credits Acquired For Transgress 5 event=0x8c,umask=0x20 01 unc_h_ag1_bl_crd_acquired.tgr6 uncore cache CMS Agent1 BL Credits Acquired For Transgress 6 event=0x8c,umask=0x40 01 unc_h_ag1_bl_crd_acquired.tgr7 uncore cache CMS Agent1 BL Credits Acquired For Transgress 7 event=0x8c,umask=0x80 01 unc_h_ag1_bl_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 BL Credits Acquired For Transgress 0-7 event=0x8d,umask=2 01 unc_h_ag1_bl_crd_acquired_ext.tgr8 uncore cache CMS Agent1 BL Credits Acquired For Transgress 8 event=0x8d,umask=1 01 unc_h_ag1_bl_crd_occupancy.tgr0 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 0 event=0x8e,umask=1 01 unc_h_ag1_bl_crd_occupancy.tgr1 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 1 event=0x8e,umask=2 01 unc_h_ag1_bl_crd_occupancy.tgr2 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 2 event=0x8e,umask=4 01 unc_h_ag1_bl_crd_occupancy.tgr3 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 3 event=0x8e,umask=8 01 unc_h_ag1_bl_crd_occupancy.tgr4 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 4 event=0x8e,umask=0x10 01 unc_h_ag1_bl_crd_occupancy.tgr5 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 5 event=0x8e,umask=0x20 01 unc_h_ag1_bl_crd_occupancy.tgr6 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 6 event=0x8e,umask=0x40 01 unc_h_ag1_bl_crd_occupancy.tgr7 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 7 event=0x8e,umask=0x80 01 unc_h_ag1_bl_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 0-7 event=0x8f,umask=2 01 unc_h_ag1_bl_crd_occupancy_ext.tgr8 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 8 event=0x8f,umask=1 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd2,umask=1 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd2,umask=2 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd2,umask=4 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd2,umask=8 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd2,umask=0x10 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd2,umask=0x20 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd2,umask=0x40 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd2,umask=0x80 01 unc_h_ag1_stall_no_crd_egress_horz_ad_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd3,umask=2 01 unc_h_ag1_stall_no_crd_egress_horz_ad_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd3,umask=1 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd6,umask=1 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd6,umask=2 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd6,umask=4 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd6,umask=8 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd6,umask=0x10 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd6,umask=0x20 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd6,umask=0x40 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd6,umask=0x80 01 unc_h_ag1_stall_no_crd_egress_horz_bl_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd7,umask=2 01 unc_h_ag1_stall_no_crd_egress_horz_bl_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd7,umask=1 01 unc_h_cache_lines_victimized.e_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC event=0x37,umask=2 01 unc_h_cache_lines_victimized.f_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ event=0x37,umask=8 01 unc_h_cache_lines_victimized.local uncore cache Lines Victimized that Match NID event=0x37,umask=0x20 01 unc_h_cache_lines_victimized.m_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Read transactions event=0x37,umask=1 01 unc_h_cache_lines_victimized.remote uncore cache Lines Victimized that Does Not Match NID event=0x37,umask=0x80 01 unc_h_cache_lines_victimized.s_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ event=0x37,umask=4 01 unc_h_clock uncore cache Uncore Clocks event=0xc0 01 unc_h_egress_horz_ads_used.ad uncore cache CMS Horizontal ADS Used event=0x9d,umask=1 01 unc_h_egress_horz_ads_used.ak uncore cache CMS Horizontal ADS Used event=0x9d,umask=2 01 unc_h_egress_horz_ads_used.bl uncore cache CMS Horizontal ADS Used event=0x9d,umask=4 01 unc_h_egress_horz_bypass.ad uncore cache CMS Horizontal Egress Bypass. AD ring event=0x9f,umask=1 01 unc_h_egress_horz_bypass.ak uncore cache CMS Horizontal Egress Bypass. AK ring event=0x9f,umask=2 01 unc_h_egress_horz_bypass.bl uncore cache CMS Horizontal Egress Bypass. BL ring event=0x9f,umask=4 01 unc_h_egress_horz_bypass.iv uncore cache CMS Horizontal Egress Bypass. IV ring event=0x9f,umask=8 01 unc_h_egress_horz_cycles_full.ad uncore cache Cycles CMS Horizontal Egress Queue is Full AD event=0x96,umask=1 01 unc_h_egress_horz_cycles_full.ak uncore cache Cycles CMS Horizontal Egress Queue is Full AK event=0x96,umask=2 01 unc_h_egress_horz_cycles_full.bl uncore cache Cycles CMS Horizontal Egress Queue is Full BL event=0x96,umask=4 01 unc_h_egress_horz_cycles_full.iv uncore cache Cycles CMS Horizontal Egress Queue is Full IV event=0x96,umask=8 01 unc_h_egress_horz_cycles_ne.ad uncore cache Cycles CMS Horizontal Egress Queue is Not Empty AD event=0x97,umask=1 01 unc_h_egress_horz_cycles_ne.ak uncore cache Cycles CMS Horizontal Egress Queue is Not Empty AK event=0x97,umask=2 01 unc_h_egress_horz_cycles_ne.bl uncore cache Cycles CMS Horizontal Egress Queue is Not Empty BL event=0x97,umask=4 01 unc_h_egress_horz_cycles_ne.iv uncore cache Cycles CMS Horizontal Egress Queue is Not Empty IV event=0x97,umask=8 01 unc_h_egress_horz_inserts.ad uncore cache CMS Horizontal Egress Inserts AD event=0x95,umask=1 01 unc_h_egress_horz_inserts.ak uncore cache CMS Horizontal Egress Inserts AK event=0x95,umask=2 01 unc_h_egress_horz_inserts.bl uncore cache CMS Horizontal Egress Inserts BL event=0x95,umask=4 01 unc_h_egress_horz_inserts.iv uncore cache CMS Horizontal Egress Inserts IV event=0x95,umask=8 01 unc_h_egress_horz_nack.ad uncore cache CMS Horizontal Egress NACKs event=0x99,umask=1 01 unc_h_egress_horz_nack.ak uncore cache CMS Horizontal Egress NACKs event=0x99,umask=2 01 unc_h_egress_horz_nack.bl uncore cache CMS Horizontal Egress NACKs event=0x99,umask=4 01 unc_h_egress_horz_nack.iv uncore cache CMS Horizontal Egress NACKs event=0x99,umask=8 01 unc_h_egress_horz_occupancy.ad uncore cache CMS Horizontal Egress Occupancy AD event=0x94,umask=1 01 unc_h_egress_horz_occupancy.ak uncore cache CMS Horizontal Egress Occupancy AK event=0x94,umask=2 01 unc_h_egress_horz_occupancy.bl uncore cache CMS Horizontal Egress Occupancy BL event=0x94,umask=4 01 unc_h_egress_horz_occupancy.iv uncore cache CMS Horizontal Egress Occupancy IV event=0x94,umask=8 01 unc_h_egress_horz_starved.ad uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=1 01 unc_h_egress_horz_starved.ak uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=2 01 unc_h_egress_horz_starved.bl uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=4 01 unc_h_egress_horz_starved.iv uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=8 01 unc_h_egress_ordering.iv_snp_go_dn uncore cache Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements event=0xae,umask=4 01 unc_h_egress_ordering.iv_snp_go_up uncore cache Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements event=0xae,umask=1 01 unc_h_egress_vert_ads_used.ad_ag0 uncore cache CMS Vertical ADS Used event=0x9c,umask=1 01 unc_h_egress_vert_ads_used.ad_ag1 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x10 01 unc_h_egress_vert_ads_used.ak_ag0 uncore cache CMS Vertical ADS Used event=0x9c,umask=2 01 unc_h_egress_vert_ads_used.ak_ag1 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x20 01 unc_h_egress_vert_ads_used.bl_ag0 uncore cache CMS Vertical ADS Used event=0x9c,umask=4 01 unc_h_egress_vert_ads_used.bl_ag1 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x40 01 unc_h_egress_vert_bypass.ad_ag0 uncore cache CMS Vertical Egress Bypass. AD ring agent 0 event=0x9e,umask=1 01 unc_h_egress_vert_bypass.ad_ag1 uncore cache CMS Vertical Egress Bypass. AD ring agent 1 event=0x9e,umask=0x10 01 unc_h_egress_vert_bypass.ak_ag0 uncore cache CMS Vertical Egress Bypass. AK ring agent 0 event=0x9e,umask=2 01 unc_h_egress_vert_bypass.ak_ag1 uncore cache CMS Vertical Egress Bypass. AK ring agent 1 event=0x9e,umask=0x20 01 unc_h_egress_vert_bypass.bl_ag0 uncore cache CMS Vertical Egress Bypass. BL ring agent 0 event=0x9e,umask=4 01 unc_h_egress_vert_bypass.bl_ag1 uncore cache CMS Vertical Egress Bypass. BL ring agent 1 event=0x9e,umask=0x40 01 unc_h_egress_vert_bypass.iv uncore cache CMS Vertical Egress Bypass. IV ring agent 0 event=0x9e,umask=8 01 unc_h_egress_vert_cycles_full.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full AD - Agent 0 event=0x92,umask=1 01 unc_h_egress_vert_cycles_full.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full AD - Agent 1 event=0x92,umask=0x10 01 unc_h_egress_vert_cycles_full.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full AK - Agent 0 event=0x92,umask=2 01 unc_h_egress_vert_cycles_full.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full AK - Agent 1 event=0x92,umask=0x20 01 unc_h_egress_vert_cycles_full.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full BL - Agent 0 event=0x92,umask=4 01 unc_h_egress_vert_cycles_full.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full BL - Agent 1 event=0x92,umask=0x40 01 unc_h_egress_vert_cycles_full.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full IV - Agent 0 event=0x92,umask=8 01 unc_h_egress_vert_cycles_ne.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 0 event=0x93,umask=1 01 unc_h_egress_vert_cycles_ne.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 1 event=0x93,umask=0x10 01 unc_h_egress_vert_cycles_ne.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 0 event=0x93,umask=2 01 unc_h_egress_vert_cycles_ne.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 1 event=0x93,umask=0x20 01 unc_h_egress_vert_cycles_ne.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 0 event=0x93,umask=4 01 unc_h_egress_vert_cycles_ne.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 1 event=0x93,umask=0x40 01 unc_h_egress_vert_cycles_ne.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty IV - Agent 0 event=0x93,umask=8 01 unc_h_egress_vert_inserts.ad_ag0 uncore cache CMS Vert Egress Allocations AD - Agent 0 event=0x91,umask=1 01 unc_h_egress_vert_inserts.ad_ag1 uncore cache CMS Vert Egress Allocations AD - Agent 1 event=0x91,umask=0x10 01 unc_h_egress_vert_inserts.ak_ag0 uncore cache CMS Vert Egress Allocations AK - Agent 0 event=0x91,umask=2 01 unc_h_egress_vert_inserts.ak_ag1 uncore cache CMS Vert Egress Allocations AK - Agent 1 event=0x91,umask=0x20 01 unc_h_egress_vert_inserts.bl_ag0 uncore cache CMS Vert Egress Allocations BL - Agent 0 event=0x91,umask=4 01 unc_h_egress_vert_inserts.bl_ag1 uncore cache CMS Vert Egress Allocations BL - Agent 1 event=0x91,umask=0x40 01 unc_h_egress_vert_inserts.iv_ag0 uncore cache CMS Vert Egress Allocations IV - Agent 0 event=0x91,umask=8 01 unc_h_egress_vert_nack.ad_ag0 uncore cache CMS Vertical Egress NACKs event=0x98,umask=1 01 unc_h_egress_vert_nack.ad_ag1 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x10 01 unc_h_egress_vert_nack.ak_ag0 uncore cache CMS Vertical Egress NACKs Onto AK Ring event=0x98,umask=2 01 unc_h_egress_vert_nack.ak_ag1 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x20 01 unc_h_egress_vert_nack.bl_ag0 uncore cache CMS Vertical Egress NACKs Onto BL Ring event=0x98,umask=4 01 unc_h_egress_vert_nack.bl_ag1 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x40 01 unc_h_egress_vert_nack.iv_ag0 uncore cache CMS Vertical Egress NACKs event=0x98,umask=8 01 unc_h_egress_vert_occupancy.ad_ag0 uncore cache CMS Vert Egress Occupancy AD - Agent 0 event=0x90,umask=1 01 unc_h_egress_vert_occupancy.ad_ag1 uncore cache CMS Vert Egress Occupancy AD - Agent 1 event=0x90,umask=0x10 01 unc_h_egress_vert_occupancy.ak_ag0 uncore cache CMS Vert Egress Occupancy AK - Agent 0 event=0x90,umask=2 01 unc_h_egress_vert_occupancy.ak_ag1 uncore cache CMS Vert Egress Occupancy AK - Agent 1 event=0x90,umask=0x20 01 unc_h_egress_vert_occupancy.bl_ag0 uncore cache CMS Vert Egress Occupancy BL - Agent 0 event=0x90,umask=4 01 unc_h_egress_vert_occupancy.bl_ag1 uncore cache CMS Vert Egress Occupancy BL - Agent 1 event=0x90,umask=0x40 01 unc_h_egress_vert_occupancy.iv_ag0 uncore cache CMS Vert Egress Occupancy IV - Agent 0 event=0x90,umask=8 01 unc_h_egress_vert_starved.ad_ag0 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=1 01 unc_h_egress_vert_starved.ad_ag1 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x10 01 unc_h_egress_vert_starved.ak_ag0 uncore cache CMS Vertical Egress Injection Starvation Onto AK Ring event=0x9a,umask=2 01 unc_h_egress_vert_starved.ak_ag1 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x20 01 unc_h_egress_vert_starved.bl_ag0 uncore cache CMS Vertical Egress Injection Starvation Onto BL Ring event=0x9a,umask=4 01 unc_h_egress_vert_starved.bl_ag1 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x40 01 unc_h_egress_vert_starved.iv_ag0 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=8 01 unc_h_fast_asserted.horz uncore cache Counts cycles source throttling is asserted - horizontal event=0xa5,umask=1 01 unc_h_fast_asserted.vert uncore cache Counts cycles source throttling is asserted - vertical event=0xa5 01 unc_h_horz_ring_ad_in_use.left_even uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Even event=0xa7,umask=1 01 unc_h_horz_ring_ad_in_use.left_odd uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Odd event=0xa7,umask=2 01 unc_h_horz_ring_ad_in_use.right_even uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Even event=0xa7,umask=4 01 unc_h_horz_ring_ad_in_use.right_odd uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Odd event=0xa7,umask=8 01 unc_h_horz_ring_ak_in_use.left_even uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Even event=0xa9,umask=1 01 unc_h_horz_ring_ak_in_use.left_odd uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Odd event=0xa9,umask=2 01 unc_h_horz_ring_ak_in_use.right_even uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Even event=0xa9,umask=4 01 unc_h_horz_ring_ak_in_use.right_odd uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Odd event=0xa9,umask=8 01 unc_h_horz_ring_bl_in_use.left_even uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Even event=0xab,umask=1 01 unc_h_horz_ring_bl_in_use.left_odd uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Odd event=0xab,umask=2 01 unc_h_horz_ring_bl_in_use.right_even uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Even event=0xab,umask=4 01 unc_h_horz_ring_bl_in_use.right_odd uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Odd event=0xab,umask=8 01 unc_h_horz_ring_iv_in_use.left uncore cache Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Left event=0xad,umask=1 01 unc_h_horz_ring_iv_in_use.right uncore cache Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Right event=0xad,umask=4 01 unc_h_ingress_inserts.ipq uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IPQ event=0x13,umask=4 01 unc_h_ingress_inserts.irq uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ event=0x13,umask=1 01 unc_h_ingress_inserts.irq_rej uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ Rejected event=0x13,umask=2 01 unc_h_ingress_inserts.prq uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ event=0x13,umask=0x10 01 unc_h_ingress_inserts.prq_rej uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ Rejected event=0x13,umask=0x20 01 unc_h_ingress_int_starved.ipq uncore cache Cycles with the IPQ in Internal Starvation event=0x14,umask=4 01 unc_h_ingress_int_starved.irq uncore cache Cycles with the IRQ in Internal Starvation event=0x14,umask=1 01 unc_h_ingress_int_starved.ismq uncore cache Cycles with the ISMQ in Internal Starvation event=0x14,umask=8 01 unc_h_ingress_int_starved.prq uncore cache Ingress internal starvation cycles. Counts cycles in internal starvation. This occurs when one or more of the entries in the ingress queue are being starved out by other entries in the queue event=0x14,umask=0x10 01 unc_h_ingress_occupancy.ipq uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IPQ event=0x11,umask=4 01 unc_h_ingress_occupancy.irq uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ event=0x11,umask=1 01 unc_h_ingress_occupancy.irq_rej uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ Rejected event=0x11,umask=2 01 unc_h_ingress_occupancy.prq uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ event=0x11,umask=0x10 01 unc_h_ingress_occupancy.prq_rej uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ Rejected event=0x11,umask=0x20 01 unc_h_ingress_retry_ipq0_reject.ad_req_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=1 01 unc_h_ingress_retry_ipq0_reject.ad_rsp_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=2 01 unc_h_ingress_retry_ipq0_reject.ak_non_upi uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x40 01 unc_h_ingress_retry_ipq0_reject.bl_ncb_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x10 01 unc_h_ingress_retry_ipq0_reject.bl_ncs_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x20 01 unc_h_ingress_retry_ipq0_reject.bl_rsp_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=4 01 unc_h_ingress_retry_ipq0_reject.bl_wb_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=8 01 unc_h_ingress_retry_ipq0_reject.iv_non_upi uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x80 01 unc_h_ingress_retry_ipq1_reject.allow_snp uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x40 01 unc_h_ingress_retry_ipq1_reject.any_reject_ipq0 uncore cache Ingress Probe Queue Rejects event=0x23,umask=1 01 unc_h_ingress_retry_ipq1_reject.pa_match uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x80 01 unc_h_ingress_retry_ipq1_reject.sf_victim uncore cache Ingress Probe Queue Rejects event=0x23,umask=8 01 unc_h_ingress_retry_ipq1_reject.sf_way uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x20 01 unc_h_ingress_retry_irq0_reject.ad_req_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=1 01 unc_h_ingress_retry_irq0_reject.ad_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=2 01 unc_h_ingress_retry_irq0_reject.ak_non_upi uncore cache Ingress Request Queue Rejects event=0x18,umask=0x40 01 unc_h_ingress_retry_irq0_reject.bl_ncb_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=0x10 01 unc_h_ingress_retry_irq0_reject.bl_ncs_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=0x20 01 unc_h_ingress_retry_irq0_reject.bl_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=4 01 unc_h_ingress_retry_irq0_reject.bl_wb_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=8 01 unc_h_ingress_retry_irq0_reject.iv_non_upi uncore cache Ingress Request Queue Rejects event=0x18,umask=0x80 01 unc_h_ingress_retry_irq1_reject.allow_snp uncore cache Ingress Request Queue Rejects event=0x19,umask=0x40 01 unc_h_ingress_retry_irq1_reject.any_reject_irq0 uncore cache Ingress Request Queue Rejects event=0x19,umask=1 01 unc_h_ingress_retry_irq1_reject.pa_match uncore cache Ingress Request Queue Rejects event=0x19,umask=0x80 01 unc_h_ingress_retry_irq1_reject.sf_victim uncore cache Ingress Request Queue Rejects event=0x19,umask=8 01 unc_h_ingress_retry_irq1_reject.sf_way uncore cache Ingress Request Queue Rejects event=0x19,umask=0x20 01 unc_h_ingress_retry_ismq0_reject.ad_req_vn0 uncore cache ISMQ Rejects event=0x24,umask=1 01 unc_h_ingress_retry_ismq0_reject.ad_rsp_vn0 uncore cache ISMQ Rejects event=0x24,umask=2 01 unc_h_ingress_retry_ismq0_reject.ak_non_upi uncore cache ISMQ Rejects event=0x24,umask=0x40 01 unc_h_ingress_retry_ismq0_reject.bl_ncb_vn0 uncore cache ISMQ Rejects event=0x24,umask=0x10 01 unc_h_ingress_retry_ismq0_reject.bl_ncs_vn0 uncore cache ISMQ Rejects event=0x24,umask=0x20 01 unc_h_ingress_retry_ismq0_reject.bl_rsp_vn0 uncore cache ISMQ Rejects event=0x24,umask=4 01 unc_h_ingress_retry_ismq0_reject.bl_wb_vn0 uncore cache ISMQ Rejects event=0x24,umask=8 01 unc_h_ingress_retry_ismq0_reject.iv_non_upi uncore cache ISMQ Rejects event=0x24,umask=0x80 01 unc_h_ingress_retry_ismq0_retry.ad_req_vn0 uncore cache ISMQ Retries event=0x2c,umask=1 01 unc_h_ingress_retry_ismq0_retry.ad_rsp_vn0 uncore cache ISMQ Retries event=0x2c,umask=2 01 unc_h_ingress_retry_ismq0_retry.ak_non_upi uncore cache ISMQ Retries event=0x2c,umask=0x40 01 unc_h_ingress_retry_ismq0_retry.bl_ncb_vn0 uncore cache ISMQ Retries event=0x2c,umask=0x10 01 unc_h_ingress_retry_ismq0_retry.bl_ncs_vn0 uncore cache ISMQ Retries event=0x2c,umask=0x20 01 unc_h_ingress_retry_ismq0_retry.bl_rsp_vn0 uncore cache ISMQ Retries event=0x2c,umask=4 01 unc_h_ingress_retry_ismq0_retry.bl_wb_vn0 uncore cache ISMQ Retries event=0x2c,umask=8 01 unc_h_ingress_retry_ismq0_retry.iv_non_upi uncore cache ISMQ Retries event=0x2c,umask=0x80 01 unc_h_ingress_retry_other0_retry.ad_req_vn0 uncore cache Other Queue Retries event=0x2e,umask=1 01 unc_h_ingress_retry_other0_retry.ad_rsp_vn0 uncore cache Other Queue Retries event=0x2e,umask=2 01 unc_h_ingress_retry_other0_retry.ak_non_upi uncore cache Other Queue Retries event=0x2e,umask=0x40 01 unc_h_ingress_retry_other0_retry.bl_ncb_vn0 uncore cache Other Queue Retries event=0x2e,umask=0x10 01 unc_h_ingress_retry_other0_retry.bl_ncs_vn0 uncore cache Other Queue Retries event=0x2e,umask=0x20 01 unc_h_ingress_retry_other0_retry.bl_rsp_vn0 uncore cache Other Queue Retries event=0x2e,umask=4 01 unc_h_ingress_retry_other0_retry.bl_wb_vn0 uncore cache Other Queue Retries event=0x2e,umask=8 01 unc_h_ingress_retry_other0_retry.iv_non_upi uncore cache Other Queue Retries event=0x2e,umask=0x80 01 unc_h_ingress_retry_other1_retry.allow_snp uncore cache Other Queue Retries event=0x2f,umask=0x40 01 unc_h_ingress_retry_other1_retry.any_reject_irq0 uncore cache Other Queue Retries event=0x2f,umask=1 01 unc_h_ingress_retry_other1_retry.pa_match uncore cache Other Queue Retries event=0x2f,umask=0x80 01 unc_h_ingress_retry_other1_retry.sf_victim uncore cache Other Queue Retries event=0x2f,umask=8 01 unc_h_ingress_retry_other1_retry.sf_way uncore cache Other Queue Retries event=0x2f,umask=0x20 01 unc_h_ingress_retry_prq0_reject.ad_req_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=1 01 unc_h_ingress_retry_prq0_reject.ad_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=2 01 unc_h_ingress_retry_prq0_reject.ak_non_upi uncore cache Ingress Request Queue Rejects event=0x20,umask=0x40 01 unc_h_ingress_retry_prq0_reject.bl_ncb_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=0x10 01 unc_h_ingress_retry_prq0_reject.bl_ncs_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=0x20 01 unc_h_ingress_retry_prq0_reject.bl_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=4 01 unc_h_ingress_retry_prq0_reject.bl_wb_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=8 01 unc_h_ingress_retry_prq0_reject.iv_non_upi uncore cache Ingress Request Queue Rejects event=0x20,umask=0x80 01 unc_h_ingress_retry_prq1_reject.allow_snp uncore cache Ingress Request Queue Rejects event=0x21,umask=0x40 01 unc_h_ingress_retry_prq1_reject.any_reject_irq0 uncore cache Ingress Request Queue Rejects event=0x21,umask=1 01 unc_h_ingress_retry_prq1_reject.pa_match uncore cache Ingress Request Queue Rejects event=0x21,umask=0x80 01 unc_h_ingress_retry_prq1_reject.sf_victim uncore cache Ingress Request Queue Rejects event=0x21,umask=8 01 unc_h_ingress_retry_prq1_reject.sf_way uncore cache Ingress Request Queue Rejects event=0x21,umask=0x20 01 unc_h_ingress_retry_req_q0_retry.ad_req_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=1 01 unc_h_ingress_retry_req_q0_retry.ad_rsp_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=2 01 unc_h_ingress_retry_req_q0_retry.ak_non_upi uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x40 01 unc_h_ingress_retry_req_q0_retry.bl_ncb_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x10 01 unc_h_ingress_retry_req_q0_retry.bl_ncs_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x20 01 unc_h_ingress_retry_req_q0_retry.bl_rsp_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=4 01 unc_h_ingress_retry_req_q0_retry.bl_wb_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=8 01 unc_h_ingress_retry_req_q0_retry.iv_non_upi uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x80 01 unc_h_ingress_retry_req_q1_retry.allow_snp uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x40 01 unc_h_ingress_retry_req_q1_retry.any_reject_irq0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=1 01 unc_h_ingress_retry_req_q1_retry.pa_match uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x80 01 unc_h_ingress_retry_req_q1_retry.sf_victim uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=8 01 unc_h_ingress_retry_req_q1_retry.sf_way uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x20 01 unc_h_misc.cv0_pref_miss uncore cache Miscellaneous events in the Cbo. CV0 Prefetch Miss event=0x39,umask=0x20 01 unc_h_misc.cv0_pref_vic uncore cache Miscellaneous events in the Cbo. CV0 Prefetch Victim event=0x39,umask=0x10 01 unc_h_misc.rfo_hit_s uncore cache Miscellaneous events in the Cbo. RFO HitS event=0x39,umask=8 01 unc_h_misc.rspi_was_fse uncore cache Miscellaneous events in the Cbo. Silent Snoop Eviction event=0x39,umask=1 01 unc_h_misc.wc_aliasing uncore cache Miscellaneous events in the Cbo. Write Combining Aliasing event=0x39,umask=2 01 unc_h_ring_bounces_horz.ad uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type event=0xa1,umask=1 01 unc_h_ring_bounces_horz.ak uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type - Acknowledgements to core event=0xa1,umask=2 01 unc_h_ring_bounces_horz.bl uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type - Data Responses to core event=0xa1,umask=4 01 unc_h_ring_bounces_horz.iv uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type - Snoops of processor's cache event=0xa1,umask=8 01 unc_h_ring_bounces_vert.ad uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type event=0xa0,umask=1 01 unc_h_ring_bounces_vert.ak uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type - Acknowledgements to core event=0xa0,umask=2 01 unc_h_ring_bounces_vert.bl uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type - Data Responses to core event=0xa0,umask=4 01 unc_h_ring_bounces_vert.iv uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type - Snoops of processor's cache event=0xa0,umask=8 01 unc_h_ring_sink_starved_horz.ad uncore cache Horizontal ring sink starvation count - AD ring event=0xa3,umask=1 01 unc_h_ring_sink_starved_horz.ak uncore cache Horizontal ring sink starvation count - AK ring event=0xa3,umask=2 01 unc_h_ring_sink_starved_horz.bl uncore cache Horizontal ring sink starvation count - BL ring event=0xa3,umask=4 01 unc_h_ring_sink_starved_horz.iv uncore cache Horizontal ring sink starvation count - IV ring event=0xa3,umask=8 01 unc_h_ring_sink_starved_vert.ad uncore cache Vertical ring sink starvation count - AD ring event=0xa2,umask=1 01 unc_h_ring_sink_starved_vert.ak uncore cache Vertical ring sink starvation count - AK ring event=0xa2,umask=2 01 unc_h_ring_sink_starved_vert.bl uncore cache Vertical ring sink starvation count - BL ring event=0xa2,umask=4 01 unc_h_ring_sink_starved_vert.iv uncore cache Vertical ring sink starvation count - IV ring event=0xa2,umask=8 01 unc_h_ring_src_thrtl uncore cache Counts cycles in throttle mode event=0xa4 01 unc_h_sf_lookup.any uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ event=0x34,umask=0x11 01 unc_h_sf_lookup.data_read uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Read transactions event=0x34,umask=3 01 unc_h_sf_lookup.remote_snoop uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ event=0x34,umask=9 01 unc_h_sf_lookup.write uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC event=0x34,umask=5 01 unc_h_tg_ingress_busy_starved.ad_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority event=0xb4,umask=1 01 unc_h_tg_ingress_busy_starved.ad_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority event=0xb4,umask=0x10 01 unc_h_tg_ingress_busy_starved.bl_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority event=0xb4,umask=4 01 unc_h_tg_ingress_busy_starved.bl_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority event=0xb4,umask=0x40 01 unc_h_tg_ingress_bypass.ad_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=1 01 unc_h_tg_ingress_bypass.ad_crd uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=0x10 01 unc_h_tg_ingress_bypass.ak_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=2 01 unc_h_tg_ingress_bypass.bl_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=4 01 unc_h_tg_ingress_bypass.bl_crd uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=0x40 01 unc_h_tg_ingress_bypass.iv_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=8 01 unc_h_tg_ingress_crd_starved.ad_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=1 01 unc_h_tg_ingress_crd_starved.ad_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x10 01 unc_h_tg_ingress_crd_starved.ak_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=2 01 unc_h_tg_ingress_crd_starved.bl_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=4 01 unc_h_tg_ingress_crd_starved.bl_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x40 01 unc_h_tg_ingress_crd_starved.ifv uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x80 01 unc_h_tg_ingress_crd_starved.iv_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=8 01 unc_h_tg_ingress_inserts.ad_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=1 01 unc_h_tg_ingress_inserts.ad_crd uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=0x10 01 unc_h_tg_ingress_inserts.ak_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=2 01 unc_h_tg_ingress_inserts.bl_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=4 01 unc_h_tg_ingress_inserts.bl_crd uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=0x40 01 unc_h_tg_ingress_inserts.iv_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=8 01 unc_h_tg_ingress_occupancy.ad_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=1 01 unc_h_tg_ingress_occupancy.ad_crd uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=0x10 01 unc_h_tg_ingress_occupancy.ak_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=2 01 unc_h_tg_ingress_occupancy.bl_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=4 01 unc_h_tg_ingress_occupancy.bl_crd uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=0x40 01 unc_h_tg_ingress_occupancy.iv_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=8 01 unc_h_tor_inserts.evict uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -SF/LLC Evictions event=0x35,umask=0x32 01 unc_h_tor_inserts.hit uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Hit (Not a Miss) event=0x35,umask=0x1f 01 unc_h_tor_inserts.ipq uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ event=0x35,umask=0x38 01 unc_h_tor_inserts.irq uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ event=0x35,umask=0x31 01 unc_h_tor_inserts.miss uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Miss event=0x35,umask=0x2f 01 unc_h_tor_inserts.prq uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ event=0x35,umask=0x34 01 unc_h_tor_occupancy.evict uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -SF/LLC Evictions event=0x36,umask=0x32 01 unc_h_tor_occupancy.hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Hit (Not a Miss) event=0x36,umask=0x1f 01 unc_h_tor_occupancy.ipq uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ event=0x36,umask=0x38 01 unc_h_tor_occupancy.ipq_hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ hit event=0x36,umask=0x18 01 unc_h_tor_occupancy.ipq_miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ miss event=0x36,umask=0x28 01 unc_h_tor_occupancy.irq uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ event=0x36,umask=0x31 01 unc_h_tor_occupancy.irq_hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ hit event=0x36,umask=0x11 01 unc_h_tor_occupancy.irq_miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ miss event=0x36,umask=0x21 01 unc_h_tor_occupancy.miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Miss event=0x36,umask=0x2f 01 unc_h_tor_occupancy.prq uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ event=0x36,umask=0x34 01 unc_h_tor_occupancy.prq_hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ hit event=0x36,umask=0x14 01 unc_h_tor_occupancy.prq_miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ miss event=0x36,umask=0x24 01 unc_h_u_clockticks uncore cache Uncore Clocks event=0 01 unc_h_vert_ring_ad_in_use.dn_even uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Even event=0xa6,umask=4 01 unc_h_vert_ring_ad_in_use.dn_odd uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Odd event=0xa6,umask=8 01 unc_h_vert_ring_ad_in_use.up_even uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Even event=0xa6,umask=1 01 unc_h_vert_ring_ad_in_use.up_odd uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Odd event=0xa6,umask=2 01 unc_h_vert_ring_ak_in_use.dn_even uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Even event=0xa8,umask=4 01 unc_h_vert_ring_ak_in_use.dn_odd uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Odd event=0xa8,umask=8 01 unc_h_vert_ring_ak_in_use.up_even uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Even event=0xa8,umask=1 01 unc_h_vert_ring_ak_in_use.up_odd uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Odd event=0xa8,umask=2 01 unc_h_vert_ring_bl_in_use.dn_even uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Even event=0xaa,umask=4 01 unc_h_vert_ring_bl_in_use.dn_odd uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Odd event=0xaa,umask=8 01 unc_h_vert_ring_bl_in_use.up_even uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Even event=0xaa,umask=1 01 unc_h_vert_ring_bl_in_use.up_odd uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Odd event=0xaa,umask=2 01 unc_h_vert_ring_iv_in_use.dn uncore cache Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Down event=0xac,umask=4 01 unc_h_vert_ring_iv_in_use.up uncore cache Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Up event=0xac,umask=1 01 unc_m2p_egress_cycles_full.ad_0 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_0 event=0x25,umask=1 01 unc_m2p_egress_cycles_full.ad_1 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_1 event=0x25,umask=8 01 unc_m2p_egress_cycles_full.ak_0 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_0 event=0x25,umask=2 01 unc_m2p_egress_cycles_full.ak_1 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_1 event=0x25,umask=0x10 01 unc_m2p_egress_cycles_full.bl_0 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_0 event=0x25,umask=4 01 unc_m2p_egress_cycles_full.bl_1 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_1 event=0x25,umask=0x20 01 unc_m2p_egress_cycles_ne.ad_0 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_0 event=0x23,umask=1 01 unc_m2p_egress_cycles_ne.ad_1 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_1 event=0x23,umask=8 01 unc_m2p_egress_cycles_ne.ak_0 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_0 event=0x23,umask=2 01 unc_m2p_egress_cycles_ne.ak_1 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_1 event=0x23,umask=0x10 01 unc_m2p_egress_cycles_ne.bl_0 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_0 event=0x23,umask=4 01 unc_m2p_egress_cycles_ne.bl_1 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_1 event=0x23,umask=0x20 01 unc_m2p_egress_inserts.ad_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_0 event=0x24,umask=1 01 unc_m2p_egress_inserts.ad_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_1 event=0x24,umask=0x10 01 unc_m2p_egress_inserts.ak_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_0 event=0x24,umask=2 01 unc_m2p_egress_inserts.ak_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_1 event=0x24,umask=0x20 01 unc_m2p_egress_inserts.ak_crd_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0 event=0x24,umask=8 01 unc_m2p_egress_inserts.ak_crd_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1 event=0x24,umask=0x80 01 unc_m2p_egress_inserts.bl_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_0 event=0x24,umask=4 01 unc_m2p_egress_inserts.bl_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_1 event=0x24,umask=0x40 01 unc_m2p_ingress_cycles_ne.all uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL event=0x10,umask=0x80 01 unc_m2p_ingress_cycles_ne.cbo_idi uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI event=0x10,umask=1 01 unc_m2p_ingress_cycles_ne.cbo_ncb uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB event=0x10,umask=2 01 unc_m2p_ingress_cycles_ne.cbo_ncs uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS event=0x10,umask=4 01 uncore_edc_uclk unc_e_edc_access.hit_clean uncore memory Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode event=2,umask=1 01 unc_e_edc_access.hit_dirty uncore memory Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode event=2,umask=2 01 unc_e_edc_access.miss_clean uncore memory Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode event=2,umask=4 01 unc_e_edc_access.miss_dirty uncore memory Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode event=2,umask=8 01 unc_e_edc_access.miss_invalid uncore memory Number of EDC Hits or Misses. Miss I event=2,umask=0x10 01 uncore_edc_eclk unc_e_e_clockticks uncore memory ECLK count event=0 01 unc_e_rpq_inserts uncore memory Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache event=1,umask=1 01 unc_e_u_clockticks uncore memory UCLK count event=0 01 unc_e_wpq_inserts uncore memory Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache event=2,umask=1 01 uncore_imc_dclk unc_m_cas_count.all uncore memory CAS All event=3,umask=3 01 unc_m_cas_count.rd uncore memory CAS Reads event=3,umask=1 01 unc_m_cas_count.wr uncore memory CAS Writes event=3,umask=2 01 unc_m_d_clockticks uncore memory DCLK count event=0 01 uncore_imc_uclk unc_m_u_clockticks uncore memory UCLK count event=0 01 mem_uops_retired.dtlb_miss_loads virtual memory Counts the number of load micro-ops retired that cause a DTLB miss (Precise Event) Supports address when precise event=4,period=200003,umask=8 00 page_walks.cycles virtual memory Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included event=5,period=200003,umask=3 00 This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress page_walks.d_side_cycles virtual memory Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included event=5,period=200003,umask=1 00 page_walks.d_side_walks virtual memory Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted event=5,edge=1,period=100003,umask=1 00 page_walks.i_side_cycles virtual memory Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included event=5,period=200003,umask=2 00 This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress page_walks.i_side_walks virtual memory Counts the total I-side page walks that are completed event=5,edge=1,period=100003,umask=2 00 page_walks.walks virtual memory Counts the total page walks that are completed (I-side and D-side) event=5,edge=1,period=100003,umask=3 00 l2_request.all cache Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only, per core event event=0x24,period=1000003,umask=7 00 Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only mem_uops_retired.all_loads cache Counts the number of load uops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x81 00 mem_uops_retired.all_stores cache Counts the number of store uops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x82 00 mem_uops_retired.load_latency_gt_1024 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=200003,umask=5,ldlat=0x400 00 mem_uops_retired.load_latency_gt_128 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=200003,umask=5,ldlat=0x80 00 mem_uops_retired.load_latency_gt_16 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=200003,umask=5,ldlat=0x10 00 mem_uops_retired.load_latency_gt_2048 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=200003,umask=5,ldlat=0x800 00 mem_uops_retired.load_latency_gt_256 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=200003,umask=5,ldlat=0x100 00 mem_uops_retired.load_latency_gt_32 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=200003,umask=5,ldlat=0x20 00 mem_uops_retired.load_latency_gt_4 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=200003,umask=5,ldlat=0x4 00 mem_uops_retired.load_latency_gt_512 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=200003,umask=5,ldlat=0x200 00 mem_uops_retired.load_latency_gt_64 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=200003,umask=5,ldlat=0x40 00 mem_uops_retired.load_latency_gt_8 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=200003,umask=5,ldlat=0x8 00 mem_uops_retired.store_latency cache Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES Supports address when precise (Must be precise) event=0xd0,period=200003,umask=6 00 idq_bubbles.core frontend This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations event=0x9c,period=1000003,umask=1 00 This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method ocr.demand_data_rd.l3_miss memory Counts cacheable demand data reads were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00001 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0xFE7F8000001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00002 00 ocr.demand_rfo.l3_miss memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0xFE7F8000002 00 ocr.demand_data_rd.any_response other Counts cacheable demand data reads Catch all value for any response types - this includes response types not define in the OCR. If this is set all other response types will be ignored event=0xb7,period=100003,umask=1,offcore_rsp=0x10001 00 ocr.demand_data_rd.dram other Counts cacheable demand data reads were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1FBC000001 00 ocr.demand_data_rd.dram other Counts demand data reads that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x1E780000001 00 ocr.demand_rfo.any_response other Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR. If this is set all other response types will be ignored event=0xb7,period=100003,umask=1,offcore_rsp=0x10002 00 cpu_clk_unhalted.core pipeline Core cycles when the core is not in a halt state event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the programmable counters available for other events cpu_clk_unhalted.core_p pipeline Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.THREAD_P] event=0x3c,period=2000003 00 This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. [This event is alias to CPU_CLK_UNHALTED.THREAD_P] cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_tsc_p pipeline Counts the number of unhalted reference clock cycles event=0x3c,period=2000003,umask=1 00 Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter cpu_clk_unhalted.ref_tsc_p pipeline Reference cycles when the core is not in halt state event=0x3c,period=2000003,umask=1 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in a halt state event=0x3c,period=2000003 00 Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the programmable counters available for other events cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.CORE_P] event=0x3c,period=2000003 00 This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. [This event is alias to CPU_CLK_UNHALTED.CORE_P] inst_retired.any_p pipeline Counts the number of instructions retired (Precise event) event=0xc0,period=2000003 00 ld_blocks.store_forward pipeline Counts the number of occurrences a retired load gets blocked because its address partially overlaps with an older store (size mismatch) - unknown_sta/bad_forward (Precise event) event=3,period=1000003,umask=2 00 misc_retired.lbr_inserts pipeline Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL (Precise event) event=0xe4,period=1000003,umask=1 00 misc_retired.lbr_inserts pipeline LBR record is inserted (Precise event) event=0xe4,period=1000003,umask=1 00 topdown.backend_bound_slots pipeline This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions event=0xa4,period=10000003,umask=2 00 This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method topdown.slots pipeline TMA slots available for an unhalted logical processor. Fixed counter - architectural event event=0,period=10000003,umask=4 00 Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3) topdown.slots_p pipeline TMA slots available for an unhalted logical processor. General counter - architectural event event=0xa4,period=10000003,umask=1 00 Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method topdown_bad_speculation.all pipeline Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P] event=0x73,period=1000003 00 topdown_bad_speculation.all_p pipeline Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL] event=0x73,period=1000003 00 topdown_be_bound.all pipeline Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P] event=0xa4,period=1000003,umask=2 00 topdown_be_bound.all_p pipeline Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL] event=0xa4,period=1000003,umask=2 00 topdown_fe_bound.all pipeline Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls event=0,period=1000003,umask=6 00 topdown_fe_bound.all_p pipeline Counts the number of retirement slots not consumed due to front end stalls event=0x9c,period=1000003,umask=1 00 topdown_retiring.all pipeline Fixed Counter: Counts the number of consumed retirement slots (Precise event) event=0,period=1000003,umask=7 00 topdown_retiring.all_p pipeline Counts the number of consumed retirement slots (Precise event) event=0xc2,period=1000003,umask=2 00 itlb_misses.walk_completed virtual memory Counts the number of page walks completed due to instruction fetch misses to any page size event=0x85,period=2000003,umask=0xe 00 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x42,period=2000003,umask=2 00 This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION) mem_load_uops_misc_retired.local_dram cache Counts the number of load ops retired that miss the L3 cache and hit in DRAM event=0xd4,period=1000003,umask=2 00 fp_vint_uops_executed.std floating point Counts the number of uops executed on floating point and vector integer store data port event=0xb2,period=1000003,umask=1 00 ocr.demand_data_rd.dram other Counts demand data reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001 00 uncore_hac_cbo unc_hac_cbo_tor_allocation.all uncore cache Number of all entries allocated. Includes also retries event=0x35,umask=8 01 unc_hac_cbo_tor_allocation.drd uncore cache Asserted on coherent DRD + DRdPref allocations into the queue. Cacheable only event=0x35,umask=1 01 uncore_hac_arb unc_hac_arb_coh_trk_requests.all uncore interconnect Number of entries allocated. Account for Any type: e.g. Snoop, etc event=0x84,umask=1 01 unc_hac_arb_req_trk_request.drd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches event=0x81,umask=2 01 unc_hac_arb_transactions.all uncore interconnect Number of all CMI transactions event=0x8a,umask=1 01 unc_hac_arb_transactions.reads uncore interconnect Number of all CMI reads event=0x8a,umask=2 01 unc_hac_arb_transactions.writes uncore interconnect Number of all CMI writes not including Mflush event=0x8a,umask=4 01 unc_hac_arb_trk_requests.all uncore interconnect Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic event=0x81,umask=1 01 unc_mc0_rdcas_count_freerun uncore memory Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels) event=0xff,umask=0x20 01 Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data unc_mc0_total_reqcount_freerun uncore memory Counts every read and write request entering the Memory Controller 0 event=0xff,umask=0x10 01 Counts every read and write request entering the Memory Controller 0 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW unc_mc0_wrcas_count_freerun uncore memory Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels) event=0xff,umask=0x30 01 Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data unc_mc1_rdcas_count_freerun uncore memory Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels) event=0xff,umask=0x20 01 Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data unc_mc1_total_reqcount_freerun uncore memory Counts every read and write request entering the Memory Controller 1 event=0xff,umask=0x10 01 Counts every read and write request entering the Memory Controller 1 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW unc_mc1_wrcas_count_freerun uncore memory Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels) event=0xff,umask=0x30 01 Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data unc_m_rd_data uncore memory Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data event=0x3a 01 unc_m_total_data uncore memory Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data event=0x3c 01 unc_m_wr_data uncore memory Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data event=0x3b 01 cache_lock_cycles.l1d cache Cycles L1D locked event=0x63,period=2000000,umask=2 00 cache_lock_cycles.l1d_l2 cache Cycles L1D and L2 locked event=0x63,period=2000000,umask=1 00 l1d.m_evict cache L1D cache lines replaced in M state event=0x51,period=2000000,umask=4 00 l1d.m_repl cache L1D cache lines allocated in the M state event=0x51,period=2000000,umask=2 00 l1d.m_snoop_evict cache L1D snoop eviction of cache lines in M state event=0x51,period=2000000,umask=8 00 l1d.repl cache L1 data cache lines allocated event=0x51,period=2000000,umask=1 00 l1d_all_ref.any cache All references to the L1 data cache event=0x43,period=2000000,umask=1 00 l1d_all_ref.cacheable cache L1 data cacheable reads and writes event=0x43,period=2000000,umask=2 00 l1d_cache_ld.e_state cache L1 data cache read in E state event=0x40,period=2000000,umask=4 00 l1d_cache_ld.i_state cache L1 data cache read in I state (misses) event=0x40,period=2000000,umask=1 00 l1d_cache_ld.mesi cache L1 data cache reads event=0x40,period=2000000,umask=0xf 00 l1d_cache_ld.m_state cache L1 data cache read in M state event=0x40,period=2000000,umask=8 00 l1d_cache_ld.s_state cache L1 data cache read in S state event=0x40,period=2000000,umask=2 00 l1d_cache_lock.e_state cache L1 data cache load locks in E state event=0x42,period=2000000,umask=4 00 l1d_cache_lock.hit cache L1 data cache load lock hits event=0x42,period=2000000,umask=1 00 l1d_cache_lock.m_state cache L1 data cache load locks in M state event=0x42,period=2000000,umask=8 00 l1d_cache_lock.s_state cache L1 data cache load locks in S state event=0x42,period=2000000,umask=2 00 l1d_cache_lock_fb_hit cache L1D load lock accepted in fill buffer event=0x53,period=2000000,umask=1 00 l1d_cache_prefetch_lock_fb_hit cache L1D prefetch load lock accepted in fill buffer event=0x52,period=2000000,umask=1 00 l1d_cache_st.e_state cache L1 data cache stores in E state event=0x41,period=2000000,umask=4 00 l1d_cache_st.m_state cache L1 data cache stores in M state event=0x41,period=2000000,umask=8 00 l1d_cache_st.s_state cache L1 data cache stores in S state event=0x41,period=2000000,umask=2 00 l1d_prefetch.miss cache L1D hardware prefetch misses event=0x4e,period=200000,umask=2 00 l1d_prefetch.requests cache L1D hardware prefetch requests event=0x4e,period=200000,umask=1 00 l1d_prefetch.triggers cache L1D hardware prefetch requests triggered event=0x4e,period=200000,umask=4 00 l1d_wb_l2.e_state cache L1 writebacks to L2 in E state event=0x28,period=100000,umask=4 00 l1d_wb_l2.i_state cache L1 writebacks to L2 in I state (misses) event=0x28,period=100000,umask=1 00 l1d_wb_l2.mesi cache All L1 writebacks to L2 event=0x28,period=100000,umask=0xf 00 l1d_wb_l2.m_state cache L1 writebacks to L2 in M state event=0x28,period=100000,umask=8 00 l1d_wb_l2.s_state cache L1 writebacks to L2 in S state event=0x28,period=100000,umask=2 00 l2_data_rqsts.any cache All L2 data requests event=0x26,period=200000,umask=0xff 00 l2_data_rqsts.demand.e_state cache L2 data demand loads in E state event=0x26,period=200000,umask=4 00 l2_data_rqsts.demand.i_state cache L2 data demand loads in I state (misses) event=0x26,period=200000,umask=1 00 l2_data_rqsts.demand.mesi cache L2 data demand requests event=0x26,period=200000,umask=0xf 00 l2_data_rqsts.demand.m_state cache L2 data demand loads in M state event=0x26,period=200000,umask=8 00 l2_data_rqsts.demand.s_state cache L2 data demand loads in S state event=0x26,period=200000,umask=2 00 l2_data_rqsts.prefetch.e_state cache L2 data prefetches in E state event=0x26,period=200000,umask=0x40 00 l2_data_rqsts.prefetch.i_state cache L2 data prefetches in the I state (misses) event=0x26,period=200000,umask=0x10 00 l2_data_rqsts.prefetch.mesi cache All L2 data prefetches event=0x26,period=200000,umask=0xf0 00 l2_data_rqsts.prefetch.m_state cache L2 data prefetches in M state event=0x26,period=200000,umask=0x80 00 l2_data_rqsts.prefetch.s_state cache L2 data prefetches in the S state event=0x26,period=200000,umask=0x20 00 l2_lines_in.any cache L2 lines allocated event=0xf1,period=100000,umask=7 00 l2_lines_in.e_state cache L2 lines allocated in the E state event=0xf1,period=100000,umask=4 00 l2_lines_in.s_state cache L2 lines allocated in the S state event=0xf1,period=100000,umask=2 00 l2_lines_out.any cache L2 lines evicted event=0xf2,period=100000,umask=0xf 00 l2_lines_out.demand_clean cache L2 lines evicted by a demand request event=0xf2,period=100000,umask=1 00 l2_lines_out.demand_dirty cache L2 modified lines evicted by a demand request event=0xf2,period=100000,umask=2 00 l2_lines_out.prefetch_clean cache L2 lines evicted by a prefetch request event=0xf2,period=100000,umask=4 00 l2_lines_out.prefetch_dirty cache L2 modified lines evicted by a prefetch request event=0xf2,period=100000,umask=8 00 l2_rqsts.ifetches cache L2 instruction fetches event=0x24,period=200000,umask=0x30 00 l2_rqsts.ifetch_hit cache L2 instruction fetch hits event=0x24,period=200000,umask=0x10 00 l2_rqsts.ifetch_miss cache L2 instruction fetch misses event=0x24,period=200000,umask=0x20 00 l2_rqsts.ld_hit cache L2 load hits event=0x24,period=200000,umask=1 00 l2_rqsts.ld_miss cache L2 load misses event=0x24,period=200000,umask=2 00 l2_rqsts.loads cache L2 requests event=0x24,period=200000,umask=3 00 l2_rqsts.miss cache All L2 misses event=0x24,period=200000,umask=0xaa 00 l2_rqsts.prefetches cache All L2 prefetches event=0x24,period=200000,umask=0xc0 00 l2_rqsts.prefetch_hit cache L2 prefetch hits event=0x24,period=200000,umask=0x40 00 l2_rqsts.prefetch_miss cache L2 prefetch misses event=0x24,period=200000,umask=0x80 00 l2_rqsts.references cache All L2 requests event=0x24,period=200000,umask=0xff 00 l2_rqsts.rfos cache L2 RFO requests event=0x24,period=200000,umask=0xc 00 l2_rqsts.rfo_hit cache L2 RFO hits event=0x24,period=200000,umask=4 00 l2_rqsts.rfo_miss cache L2 RFO misses event=0x24,period=200000,umask=8 00 l2_transactions.any cache All L2 transactions event=0xf0,period=200000,umask=0x80 00 l2_transactions.fill cache L2 fill transactions event=0xf0,period=200000,umask=0x20 00 l2_transactions.ifetch cache L2 instruction fetch transactions event=0xf0,period=200000,umask=4 00 l2_transactions.l1d_wb cache L1D writeback to L2 transactions event=0xf0,period=200000,umask=0x10 00 l2_transactions.load cache L2 Load transactions event=0xf0,period=200000,umask=1 00 l2_transactions.prefetch cache L2 prefetch transactions event=0xf0,period=200000,umask=8 00 l2_transactions.rfo cache L2 RFO transactions event=0xf0,period=200000,umask=2 00 l2_transactions.wb cache L2 writeback to LLC transactions event=0xf0,period=200000,umask=0x40 00 l2_write.lock.e_state cache L2 demand lock RFOs in E state event=0x27,period=100000,umask=0x40 00 l2_write.lock.hit cache All demand L2 lock RFOs that hit the cache event=0x27,period=100000,umask=0xe0 00 l2_write.lock.i_state cache L2 demand lock RFOs in I state (misses) event=0x27,period=100000,umask=0x10 00 l2_write.lock.mesi cache All demand L2 lock RFOs event=0x27,period=100000,umask=0xf0 00 l2_write.lock.m_state cache L2 demand lock RFOs in M state event=0x27,period=100000,umask=0x80 00 l2_write.lock.s_state cache L2 demand lock RFOs in S state event=0x27,period=100000,umask=0x20 00 l2_write.rfo.hit cache All L2 demand store RFOs that hit the cache event=0x27,period=100000,umask=0xe 00 l2_write.rfo.i_state cache L2 demand store RFOs in I state (misses) event=0x27,period=100000,umask=1 00 l2_write.rfo.mesi cache All L2 demand store RFOs event=0x27,period=100000,umask=0xf 00 l2_write.rfo.m_state cache L2 demand store RFOs in M state event=0x27,period=100000,umask=8 00 l2_write.rfo.s_state cache L2 demand store RFOs in S state event=0x27,period=100000,umask=2 00 longest_lat_cache.miss cache Longest latency cache miss event=0x2e,period=100000,umask=0x41 00 longest_lat_cache.reference cache Longest latency cache reference event=0x2e,period=200000,umask=0x4f 00 mem_inst_retired.latency_above_threshold_0 cache Memory instructions retired above 0 clocks (Precise Event) event=0xb,period=2000000,umask=0x10,ldlat=None 00 mem_inst_retired.latency_above_threshold_1024 cache Memory instructions retired above 1024 clocks (Precise Event) event=0xb,period=100,umask=0x10,ldlat=0x400 00 mem_inst_retired.latency_above_threshold_128 cache Memory instructions retired above 128 clocks (Precise Event) event=0xb,period=1000,umask=0x10,ldlat=0x80 00 mem_inst_retired.latency_above_threshold_16 cache Memory instructions retired above 16 clocks (Precise Event) event=0xb,period=10000,umask=0x10,ldlat=0x10 00 mem_inst_retired.latency_above_threshold_16384 cache Memory instructions retired above 16384 clocks (Precise Event) event=0xb,period=5,umask=0x10,ldlat=0x4000 00 mem_inst_retired.latency_above_threshold_2048 cache Memory instructions retired above 2048 clocks (Precise Event) event=0xb,period=50,umask=0x10,ldlat=0x800 00 mem_inst_retired.latency_above_threshold_256 cache Memory instructions retired above 256 clocks (Precise Event) event=0xb,period=500,umask=0x10,ldlat=0x100 00 mem_inst_retired.latency_above_threshold_32 cache Memory instructions retired above 32 clocks (Precise Event) event=0xb,period=5000,umask=0x10,ldlat=0x20 00 mem_inst_retired.latency_above_threshold_32768 cache Memory instructions retired above 32768 clocks (Precise Event) event=0xb,period=3,umask=0x10,ldlat=0x8000 00 mem_inst_retired.latency_above_threshold_4 cache Memory instructions retired above 4 clocks (Precise Event) event=0xb,period=50000,umask=0x10,ldlat=0x4 00 mem_inst_retired.latency_above_threshold_4096 cache Memory instructions retired above 4096 clocks (Precise Event) event=0xb,period=20,umask=0x10,ldlat=0x1000 00 mem_inst_retired.latency_above_threshold_512 cache Memory instructions retired above 512 clocks (Precise Event) event=0xb,period=200,umask=0x10,ldlat=0x200 00 mem_inst_retired.latency_above_threshold_64 cache Memory instructions retired above 64 clocks (Precise Event) event=0xb,period=2000,umask=0x10,ldlat=0x40 00 mem_inst_retired.latency_above_threshold_8 cache Memory instructions retired above 8 clocks (Precise Event) event=0xb,period=20000,umask=0x10,ldlat=0x8 00 mem_inst_retired.latency_above_threshold_8192 cache Memory instructions retired above 8192 clocks (Precise Event) event=0xb,period=10,umask=0x10,ldlat=0x2000 00 mem_inst_retired.loads cache Instructions retired which contains a load (Precise Event) event=0xb,period=2000000,umask=1 00 mem_inst_retired.stores cache Instructions retired which contains a store (Precise Event) event=0xb,period=2000000,umask=2 00 mem_load_retired.hit_lfb cache Retired loads that miss L1D and hit an previously allocated LFB (Precise Event) event=0xcb,period=200000,umask=0x40 00 mem_load_retired.l1d_hit cache Retired loads that hit the L1 data cache (Precise Event) event=0xcb,period=2000000,umask=1 00 mem_load_retired.l2_hit cache Retired loads that hit the L2 cache (Precise Event) event=0xcb,period=200000,umask=2 00 mem_load_retired.llc_miss cache Retired loads that miss the LLC cache (Precise Event) event=0xcb,period=10000,umask=0x10 00 mem_load_retired.llc_unshared_hit cache Retired loads that hit valid versions in the LLC cache (Precise Event) event=0xcb,period=40000,umask=4 00 mem_load_retired.other_core_l2_hit_hitm cache Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event) event=0xcb,period=40000,umask=8 00 mem_uncore_retired.local_dram cache Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event) event=0xf,period=10000,umask=0x20 00 mem_uncore_retired.other_core_l2_hitm cache Load instructions retired that HIT modified data in sibling core (Precise Event) event=0xf,period=40000,umask=2 00 mem_uncore_retired.remote_cache_local_home_hit cache Load instructions retired remote cache HIT data source (Precise Event) event=0xf,period=20000,umask=8 00 mem_uncore_retired.remote_dram cache Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) event=0xf,period=10000,umask=0x10 00 mem_uncore_retired.uncacheable cache Load instructions retired IO (Precise Event) event=0xf,period=4000,umask=0x80 00 offcore_requests.l1d_writeback cache Offcore L1 data cache writebacks event=0xb0,period=100000,umask=0x40 00 offcore_requests_sq_full cache Offcore requests blocked due to Super Queue full event=0xb2,period=100000,umask=1 00 offcore_response.any_data.any_cache_dram cache Offcore data reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F11 00 offcore_response.any_data.any_location cache All offcore data reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF11 00 offcore_response.any_data.io_csr_mmio cache Offcore data reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8011 00 offcore_response.any_data.llc_hit_no_other_core cache Offcore data reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x111 00 offcore_response.any_data.llc_hit_other_core_hit cache Offcore data reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x211 00 offcore_response.any_data.llc_hit_other_core_hitm cache Offcore data reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x411 00 offcore_response.any_data.local_cache cache Offcore data reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x711 00 offcore_response.any_data.local_cache_dram cache Offcore data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4711 00 offcore_response.any_data.remote_cache cache Offcore data reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1811 00 offcore_response.any_data.remote_cache_dram cache Offcore data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3811 00 offcore_response.any_data.remote_cache_hit cache Offcore data reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1011 00 offcore_response.any_data.remote_cache_hitm cache Offcore data reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x811 00 offcore_response.any_ifetch.any_cache_dram cache Offcore code reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F44 00 offcore_response.any_ifetch.any_location cache All offcore code reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF44 00 offcore_response.any_ifetch.io_csr_mmio cache Offcore code reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8044 00 offcore_response.any_ifetch.llc_hit_no_other_core cache Offcore code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x144 00 offcore_response.any_ifetch.llc_hit_other_core_hit cache Offcore code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x244 00 offcore_response.any_ifetch.llc_hit_other_core_hitm cache Offcore code reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x444 00 offcore_response.any_ifetch.local_cache cache Offcore code reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x744 00 offcore_response.any_ifetch.local_cache_dram cache Offcore code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4744 00 offcore_response.any_ifetch.remote_cache cache Offcore code reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1844 00 offcore_response.any_ifetch.remote_cache_dram cache Offcore code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3844 00 offcore_response.any_ifetch.remote_cache_hit cache Offcore code reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1044 00 offcore_response.any_ifetch.remote_cache_hitm cache Offcore code reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x844 00 offcore_response.any_request.any_cache_dram cache Offcore requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7FFF 00 offcore_response.any_request.any_location cache All offcore requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFFFF 00 offcore_response.any_request.io_csr_mmio cache Offcore requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x80FF 00 offcore_response.any_request.llc_hit_no_other_core cache Offcore requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x1FF 00 offcore_response.any_request.llc_hit_other_core_hit cache Offcore requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x2FF 00 offcore_response.any_request.llc_hit_other_core_hitm cache Offcore requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x4FF 00 offcore_response.any_request.local_cache cache Offcore requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x7FF 00 offcore_response.any_request.local_cache_dram cache Offcore requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x47FF 00 offcore_response.any_request.remote_cache cache Offcore requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x18FF 00 offcore_response.any_request.remote_cache_dram cache Offcore requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x38FF 00 offcore_response.any_request.remote_cache_hit cache Offcore requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x10FF 00 offcore_response.any_request.remote_cache_hitm cache Offcore requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x8FF 00 offcore_response.any_rfo.any_cache_dram cache Offcore RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F22 00 offcore_response.any_rfo.any_location cache All offcore RFO requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF22 00 offcore_response.any_rfo.io_csr_mmio cache Offcore RFO requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8022 00 offcore_response.any_rfo.llc_hit_no_other_core cache Offcore RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x122 00 offcore_response.any_rfo.llc_hit_other_core_hit cache Offcore RFO requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x222 00 offcore_response.any_rfo.llc_hit_other_core_hitm cache Offcore RFO requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x422 00 offcore_response.any_rfo.local_cache cache Offcore RFO requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x722 00 offcore_response.any_rfo.local_cache_dram cache Offcore RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4722 00 offcore_response.any_rfo.remote_cache cache Offcore RFO requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1822 00 offcore_response.any_rfo.remote_cache_dram cache Offcore RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3822 00 offcore_response.any_rfo.remote_cache_hit cache Offcore RFO requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1022 00 offcore_response.any_rfo.remote_cache_hitm cache Offcore RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x822 00 offcore_response.corewb.any_cache_dram cache Offcore writebacks to any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F08 00 offcore_response.corewb.any_location cache All offcore writebacks event=0xb7,period=100000,umask=1,offcore_rsp=0xFF08 00 offcore_response.corewb.io_csr_mmio cache Offcore writebacks to the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8008 00 offcore_response.corewb.llc_hit_no_other_core cache Offcore writebacks to the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x108 00 offcore_response.corewb.llc_hit_other_core_hitm cache Offcore writebacks to the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x408 00 offcore_response.corewb.local_cache cache Offcore writebacks to the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x708 00 offcore_response.corewb.local_cache_dram cache Offcore writebacks to the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4708 00 offcore_response.corewb.remote_cache cache Offcore writebacks to a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1808 00 offcore_response.corewb.remote_cache_dram cache Offcore writebacks to a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3808 00 offcore_response.corewb.remote_cache_hit cache Offcore writebacks that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1008 00 offcore_response.corewb.remote_cache_hitm cache Offcore writebacks that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x808 00 offcore_response.data_ifetch.any_cache_dram cache Offcore code or data read requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F77 00 offcore_response.data_ifetch.any_location cache All offcore code or data read requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF77 00 offcore_response.data_ifetch.io_csr_mmio cache Offcore code or data read requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8077 00 offcore_response.data_ifetch.llc_hit_no_other_core cache Offcore code or data read requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x177 00 offcore_response.data_ifetch.llc_hit_other_core_hit cache Offcore code or data read requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x277 00 offcore_response.data_ifetch.llc_hit_other_core_hitm cache Offcore code or data read requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x477 00 offcore_response.data_ifetch.local_cache cache Offcore code or data read requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x777 00 offcore_response.data_ifetch.local_cache_dram cache Offcore code or data read requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4777 00 offcore_response.data_ifetch.remote_cache cache Offcore code or data read requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1877 00 offcore_response.data_ifetch.remote_cache_dram cache Offcore code or data read requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3877 00 offcore_response.data_ifetch.remote_cache_hit cache Offcore code or data read requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1077 00 offcore_response.data_ifetch.remote_cache_hitm cache Offcore code or data read requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x877 00 offcore_response.data_in.any_cache_dram cache Offcore request = all data, response = any cache_dram event=0xb7,period=100000,umask=1,offcore_rsp=0x7F33 00 offcore_response.data_in.any_location cache Offcore request = all data, response = any location event=0xb7,period=100000,umask=1,offcore_rsp=0xFF33 00 offcore_response.data_in.io_csr_mmio cache Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8033 00 offcore_response.data_in.llc_hit_no_other_core cache Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x133 00 offcore_response.data_in.llc_hit_other_core_hit cache Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x233 00 offcore_response.data_in.llc_hit_other_core_hitm cache Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x433 00 offcore_response.data_in.local_cache cache Offcore request = all data, response = local cache event=0xb7,period=100000,umask=1,offcore_rsp=0x733 00 offcore_response.data_in.local_cache_dram cache Offcore request = all data, response = local cache or dram event=0xb7,period=100000,umask=1,offcore_rsp=0x4733 00 offcore_response.data_in.remote_cache cache Offcore request = all data, response = remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1833 00 offcore_response.data_in.remote_cache_dram cache Offcore request = all data, response = remote cache or dram event=0xb7,period=100000,umask=1,offcore_rsp=0x3833 00 offcore_response.data_in.remote_cache_hit cache Offcore data reads, RFOs, and prefetches that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1033 00 offcore_response.data_in.remote_cache_hitm cache Offcore data reads, RFOs, and prefetches that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x833 00 offcore_response.demand_data.any_cache_dram cache Offcore demand data requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F03 00 offcore_response.demand_data.any_location cache All offcore demand data requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF03 00 offcore_response.demand_data.io_csr_mmio cache Offcore demand data requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8003 00 offcore_response.demand_data.llc_hit_no_other_core cache Offcore demand data requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x103 00 offcore_response.demand_data.llc_hit_other_core_hit cache Offcore demand data requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x203 00 offcore_response.demand_data.llc_hit_other_core_hitm cache Offcore demand data requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x403 00 offcore_response.demand_data.local_cache cache Offcore demand data requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x703 00 offcore_response.demand_data.local_cache_dram cache Offcore demand data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4703 00 offcore_response.demand_data.remote_cache cache Offcore demand data requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1803 00 offcore_response.demand_data.remote_cache_dram cache Offcore demand data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3803 00 offcore_response.demand_data.remote_cache_hit cache Offcore demand data requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1003 00 offcore_response.demand_data.remote_cache_hitm cache Offcore demand data requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x803 00 offcore_response.demand_data_rd.any_cache_dram cache Offcore demand data reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F01 00 offcore_response.demand_data_rd.any_location cache All offcore demand data reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF01 00 offcore_response.demand_data_rd.io_csr_mmio cache Offcore demand data reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8001 00 offcore_response.demand_data_rd.llc_hit_no_other_core cache Offcore demand data reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x101 00 offcore_response.demand_data_rd.llc_hit_other_core_hit cache Offcore demand data reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x201 00 offcore_response.demand_data_rd.llc_hit_other_core_hitm cache Offcore demand data reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x401 00 offcore_response.demand_data_rd.local_cache cache Offcore demand data reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x701 00 offcore_response.demand_data_rd.local_cache_dram cache Offcore demand data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4701 00 offcore_response.demand_data_rd.remote_cache cache Offcore demand data reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1801 00 offcore_response.demand_data_rd.remote_cache_dram cache Offcore demand data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3801 00 offcore_response.demand_data_rd.remote_cache_hit cache Offcore demand data reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1001 00 offcore_response.demand_data_rd.remote_cache_hitm cache Offcore demand data reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x801 00 offcore_response.demand_ifetch.any_cache_dram cache Offcore demand code reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F04 00 offcore_response.demand_ifetch.any_location cache All offcore demand code reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF04 00 offcore_response.demand_ifetch.io_csr_mmio cache Offcore demand code reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8004 00 offcore_response.demand_ifetch.llc_hit_no_other_core cache Offcore demand code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x104 00 offcore_response.demand_ifetch.llc_hit_other_core_hit cache Offcore demand code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x204 00 offcore_response.demand_ifetch.llc_hit_other_core_hitm cache Offcore demand code reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x404 00 offcore_response.demand_ifetch.local_cache cache Offcore demand code reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x704 00 offcore_response.demand_ifetch.local_cache_dram cache Offcore demand code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4704 00 offcore_response.demand_ifetch.remote_cache cache Offcore demand code reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1804 00 offcore_response.demand_ifetch.remote_cache_dram cache Offcore demand code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3804 00 offcore_response.demand_ifetch.remote_cache_hit cache Offcore demand code reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1004 00 offcore_response.demand_ifetch.remote_cache_hitm cache Offcore demand code reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x804 00 offcore_response.demand_rfo.any_cache_dram cache Offcore demand RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F02 00 offcore_response.demand_rfo.any_location cache All offcore demand RFO requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF02 00 offcore_response.demand_rfo.io_csr_mmio cache Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8002 00 offcore_response.demand_rfo.llc_hit_no_other_core cache Offcore demand RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x102 00 offcore_response.demand_rfo.llc_hit_other_core_hit cache Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x202 00 offcore_response.demand_rfo.llc_hit_other_core_hitm cache Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x402 00 offcore_response.demand_rfo.local_cache cache Offcore demand RFO requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x702 00 offcore_response.demand_rfo.local_cache_dram cache Offcore demand RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4702 00 offcore_response.demand_rfo.remote_cache cache Offcore demand RFO requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1802 00 offcore_response.demand_rfo.remote_cache_dram cache Offcore demand RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3802 00 offcore_response.demand_rfo.remote_cache_hit cache Offcore demand RFO requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1002 00 offcore_response.demand_rfo.remote_cache_hitm cache Offcore demand RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x802 00 offcore_response.other.any_cache_dram cache Offcore other requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F80 00 offcore_response.other.any_location cache All offcore other requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF80 00 offcore_response.other.io_csr_mmio cache Offcore other requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8080 00 offcore_response.other.llc_hit_no_other_core cache Offcore other requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x180 00 offcore_response.other.llc_hit_other_core_hit cache Offcore other requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x280 00 offcore_response.other.llc_hit_other_core_hitm cache Offcore other requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x480 00 offcore_response.other.local_cache cache Offcore other requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x780 00 offcore_response.other.local_cache_dram cache Offcore other requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4780 00 offcore_response.other.remote_cache cache Offcore other requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1880 00 offcore_response.other.remote_cache_dram cache Offcore other requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3880 00 offcore_response.other.remote_cache_hit cache Offcore other requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1080 00 offcore_response.other.remote_cache_hitm cache Offcore other requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x880 00 offcore_response.pf_data.any_cache_dram cache Offcore prefetch data requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F30 00 offcore_response.pf_data.any_location cache All offcore prefetch data requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF30 00 offcore_response.pf_data.io_csr_mmio cache Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8030 00 offcore_response.pf_data.llc_hit_no_other_core cache Offcore prefetch data requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x130 00 offcore_response.pf_data.llc_hit_other_core_hit cache Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x230 00 offcore_response.pf_data.llc_hit_other_core_hitm cache Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x430 00 offcore_response.pf_data.local_cache cache Offcore prefetch data requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x730 00 offcore_response.pf_data.local_cache_dram cache Offcore prefetch data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4730 00 offcore_response.pf_data.remote_cache cache Offcore prefetch data requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1830 00 offcore_response.pf_data.remote_cache_dram cache Offcore prefetch data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3830 00 offcore_response.pf_data.remote_cache_hit cache Offcore prefetch data requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1030 00 offcore_response.pf_data.remote_cache_hitm cache Offcore prefetch data requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x830 00 offcore_response.pf_data_rd.any_cache_dram cache Offcore prefetch data reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F10 00 offcore_response.pf_data_rd.any_location cache All offcore prefetch data reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF10 00 offcore_response.pf_data_rd.io_csr_mmio cache Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8010 00 offcore_response.pf_data_rd.llc_hit_no_other_core cache Offcore prefetch data reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x110 00 offcore_response.pf_data_rd.llc_hit_other_core_hit cache Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x210 00 offcore_response.pf_data_rd.llc_hit_other_core_hitm cache Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x410 00 offcore_response.pf_data_rd.local_cache cache Offcore prefetch data reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x710 00 offcore_response.pf_data_rd.local_cache_dram cache Offcore prefetch data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4710 00 offcore_response.pf_data_rd.remote_cache cache Offcore prefetch data reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1810 00 offcore_response.pf_data_rd.remote_cache_dram cache Offcore prefetch data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3810 00 offcore_response.pf_data_rd.remote_cache_hit cache Offcore prefetch data reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1010 00 offcore_response.pf_data_rd.remote_cache_hitm cache Offcore prefetch data reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x810 00 offcore_response.pf_ifetch.any_cache_dram cache Offcore prefetch code reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F40 00 offcore_response.pf_ifetch.any_location cache All offcore prefetch code reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF40 00 offcore_response.pf_ifetch.io_csr_mmio cache Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8040 00 offcore_response.pf_ifetch.llc_hit_no_other_core cache Offcore prefetch code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x140 00 offcore_response.pf_ifetch.llc_hit_other_core_hit cache Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x240 00 offcore_response.pf_ifetch.llc_hit_other_core_hitm cache Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x440 00 offcore_response.pf_ifetch.local_cache cache Offcore prefetch code reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x740 00 offcore_response.pf_ifetch.local_cache_dram cache Offcore prefetch code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4740 00 offcore_response.pf_ifetch.remote_cache cache Offcore prefetch code reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1840 00 offcore_response.pf_ifetch.remote_cache_dram cache Offcore prefetch code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3840 00 offcore_response.pf_ifetch.remote_cache_hit cache Offcore prefetch code reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1040 00 offcore_response.pf_ifetch.remote_cache_hitm cache Offcore prefetch code reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x840 00 offcore_response.pf_rfo.any_cache_dram cache Offcore prefetch RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F20 00 offcore_response.pf_rfo.any_location cache All offcore prefetch RFO requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF20 00 offcore_response.pf_rfo.io_csr_mmio cache Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8020 00 offcore_response.pf_rfo.llc_hit_no_other_core cache Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x120 00 offcore_response.pf_rfo.llc_hit_other_core_hit cache Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x220 00 offcore_response.pf_rfo.llc_hit_other_core_hitm cache Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x420 00 offcore_response.pf_rfo.local_cache cache Offcore prefetch RFO requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x720 00 offcore_response.pf_rfo.local_cache_dram cache Offcore prefetch RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4720 00 offcore_response.pf_rfo.remote_cache cache Offcore prefetch RFO requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1820 00 offcore_response.pf_rfo.remote_cache_dram cache Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3820 00 offcore_response.pf_rfo.remote_cache_hit cache Offcore prefetch RFO requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1020 00 offcore_response.pf_rfo.remote_cache_hitm cache Offcore prefetch RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x820 00 offcore_response.prefetch.any_cache_dram cache Offcore prefetch requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F70 00 offcore_response.prefetch.any_location cache All offcore prefetch requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF70 00 offcore_response.prefetch.io_csr_mmio cache Offcore prefetch requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8070 00 offcore_response.prefetch.llc_hit_no_other_core cache Offcore prefetch requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x170 00 offcore_response.prefetch.llc_hit_other_core_hit cache Offcore prefetch requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x270 00 offcore_response.prefetch.llc_hit_other_core_hitm cache Offcore prefetch requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x470 00 offcore_response.prefetch.local_cache cache Offcore prefetch requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x770 00 offcore_response.prefetch.local_cache_dram cache Offcore prefetch requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4770 00 offcore_response.prefetch.remote_cache cache Offcore prefetch requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1870 00 offcore_response.prefetch.remote_cache_dram cache Offcore prefetch requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3870 00 offcore_response.prefetch.remote_cache_hit cache Offcore prefetch requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1070 00 offcore_response.prefetch.remote_cache_hitm cache Offcore prefetch requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x870 00 sq_misc.split_lock cache Super Queue lock splits across a cache line event=0xf4,period=2000000,umask=0x10 00 store_blocks.at_ret cache Loads delayed with at-Retirement block code event=6,period=200000,umask=4 00 store_blocks.l1d_block cache Cacheable loads delayed with L1D block code event=6,period=200000,umask=8 00 fp_assist.all floating point X87 Floating point assists (Precise Event) event=0xf7,period=20000,umask=1 00 fp_assist.input floating point X87 Floating point assists for invalid input value (Precise Event) event=0xf7,period=20000,umask=4 00 fp_assist.output floating point X87 Floating point assists for invalid output value (Precise Event) event=0xf7,period=20000,umask=2 00 fp_comp_ops_exe.mmx floating point MMX Uops event=0x10,period=2000000,umask=2 00 fp_comp_ops_exe.sse2_integer floating point SSE2 integer Uops event=0x10,period=2000000,umask=8 00 fp_comp_ops_exe.sse_double_precision floating point SSE* FP double precision Uops event=0x10,period=2000000,umask=0x80 00 fp_comp_ops_exe.sse_fp floating point SSE and SSE2 FP Uops event=0x10,period=2000000,umask=4 00 fp_comp_ops_exe.sse_fp_packed floating point SSE FP packed Uops event=0x10,period=2000000,umask=0x10 00 fp_comp_ops_exe.sse_fp_scalar floating point SSE FP scalar Uops event=0x10,period=2000000,umask=0x20 00 fp_comp_ops_exe.sse_single_precision floating point SSE* FP single precision Uops event=0x10,period=2000000,umask=0x40 00 fp_comp_ops_exe.x87 floating point Computational floating-point operations executed event=0x10,period=2000000,umask=1 00 fp_mmx_trans.any floating point All Floating Point to and from MMX transitions event=0xcc,period=2000000,umask=3 00 fp_mmx_trans.to_fp floating point Transitions from MMX to Floating Point instructions event=0xcc,period=2000000,umask=1 00 fp_mmx_trans.to_mmx floating point Transitions from Floating Point to MMX instructions event=0xcc,period=2000000,umask=2 00 simd_int_128.pack floating point 128 bit SIMD integer pack operations event=0x12,period=200000,umask=4 00 simd_int_128.packed_arith floating point 128 bit SIMD integer arithmetic operations event=0x12,period=200000,umask=0x20 00 simd_int_128.packed_logical floating point 128 bit SIMD integer logical operations event=0x12,period=200000,umask=0x10 00 simd_int_128.packed_mpy floating point 128 bit SIMD integer multiply operations event=0x12,period=200000,umask=1 00 simd_int_128.packed_shift floating point 128 bit SIMD integer shift operations event=0x12,period=200000,umask=2 00 simd_int_128.shuffle_move floating point 128 bit SIMD integer shuffle/move operations event=0x12,period=200000,umask=0x40 00 simd_int_128.unpack floating point 128 bit SIMD integer unpack operations event=0x12,period=200000,umask=8 00 simd_int_64.pack floating point SIMD integer 64 bit pack operations event=0xfd,period=200000,umask=4 00 simd_int_64.packed_arith floating point SIMD integer 64 bit arithmetic operations event=0xfd,period=200000,umask=0x20 00 simd_int_64.packed_logical floating point SIMD integer 64 bit logical operations event=0xfd,period=200000,umask=0x10 00 simd_int_64.packed_mpy floating point SIMD integer 64 bit packed multiply operations event=0xfd,period=200000,umask=1 00 simd_int_64.packed_shift floating point SIMD integer 64 bit shift operations event=0xfd,period=200000,umask=2 00 simd_int_64.shuffle_move floating point SIMD integer 64 bit shuffle/move operations event=0xfd,period=200000,umask=0x40 00 simd_int_64.unpack floating point SIMD integer 64 bit unpack operations event=0xfd,period=200000,umask=8 00 macro_insts.decoded frontend Instructions decoded event=0xd0,period=2000000,umask=1 00 macro_insts.fusions_decoded frontend Macro-fused instructions decoded event=0xa6,period=2000000,umask=1 00 two_uop_insts_decoded frontend Two Uop instructions decoded event=0x19,period=2000000,umask=1 00 offcore_response.any_data.any_dram memory Offcore data reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6011 00 offcore_response.any_data.any_llc_miss memory Offcore data reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF811 00 offcore_response.any_data.local_dram memory Offcore data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4011 00 offcore_response.any_data.remote_dram memory Offcore data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2011 00 offcore_response.any_ifetch.any_dram memory Offcore code reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6044 00 offcore_response.any_ifetch.any_llc_miss memory Offcore code reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF844 00 offcore_response.any_ifetch.local_dram memory Offcore code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4044 00 offcore_response.any_ifetch.remote_dram memory Offcore code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2044 00 offcore_response.any_request.any_dram memory Offcore requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x60FF 00 offcore_response.any_request.any_llc_miss memory Offcore requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF8FF 00 offcore_response.any_request.local_dram memory Offcore requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x40FF 00 offcore_response.any_request.remote_dram memory Offcore requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x20FF 00 offcore_response.any_rfo.any_dram memory Offcore RFO requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6022 00 offcore_response.any_rfo.any_llc_miss memory Offcore RFO requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF822 00 offcore_response.any_rfo.local_dram memory Offcore RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4022 00 offcore_response.any_rfo.remote_dram memory Offcore RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2022 00 offcore_response.corewb.any_dram memory Offcore writebacks to any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6008 00 offcore_response.corewb.any_llc_miss memory Offcore writebacks that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF808 00 offcore_response.corewb.local_dram memory Offcore writebacks to the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4008 00 offcore_response.corewb.remote_dram memory Offcore writebacks to a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2008 00 offcore_response.data_ifetch.any_dram memory Offcore code or data read requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6077 00 offcore_response.data_ifetch.any_llc_miss memory Offcore code or data read requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF877 00 offcore_response.data_ifetch.local_dram memory Offcore code or data read requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4077 00 offcore_response.data_ifetch.remote_dram memory Offcore code or data read requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2077 00 offcore_response.data_in.any_dram memory Offcore request = all data, response = any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6033 00 offcore_response.data_in.any_llc_miss memory Offcore request = all data, response = any LLC miss event=0xb7,period=100000,umask=1,offcore_rsp=0xF833 00 offcore_response.data_in.local_dram memory Offcore data reads, RFOs, and prefetches satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4033 00 offcore_response.data_in.remote_dram memory Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2033 00 offcore_response.demand_data.any_dram memory Offcore demand data requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6003 00 offcore_response.demand_data.any_llc_miss memory Offcore demand data requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF803 00 offcore_response.demand_data.local_dram memory Offcore demand data requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4003 00 offcore_response.demand_data.remote_dram memory Offcore demand data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2003 00 offcore_response.demand_data_rd.any_dram memory Offcore demand data reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6001 00 offcore_response.demand_data_rd.any_llc_miss memory Offcore demand data reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF801 00 offcore_response.demand_data_rd.local_dram memory Offcore demand data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4001 00 offcore_response.demand_data_rd.remote_dram memory Offcore demand data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2001 00 offcore_response.demand_ifetch.any_dram memory Offcore demand code reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6004 00 offcore_response.demand_ifetch.any_llc_miss memory Offcore demand code reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF804 00 offcore_response.demand_ifetch.local_dram memory Offcore demand code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4004 00 offcore_response.demand_ifetch.remote_dram memory Offcore demand code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2004 00 offcore_response.demand_rfo.any_dram memory Offcore demand RFO requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6002 00 offcore_response.demand_rfo.any_llc_miss memory Offcore demand RFO requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF802 00 offcore_response.demand_rfo.local_dram memory Offcore demand RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4002 00 offcore_response.demand_rfo.remote_dram memory Offcore demand RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2002 00 offcore_response.other.any_dram memory Offcore other requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6080 00 offcore_response.other.any_llc_miss memory Offcore other requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF880 00 offcore_response.other.remote_dram memory Offcore other requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2080 00 offcore_response.pf_data.any_dram memory Offcore prefetch data requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6030 00 offcore_response.pf_data.any_llc_miss memory Offcore prefetch data requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF830 00 offcore_response.pf_data.local_dram memory Offcore prefetch data requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4030 00 offcore_response.pf_data.remote_dram memory Offcore prefetch data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2030 00 offcore_response.pf_data_rd.any_dram memory Offcore prefetch data reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6010 00 offcore_response.pf_data_rd.any_llc_miss memory Offcore prefetch data reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF810 00 offcore_response.pf_data_rd.local_dram memory Offcore prefetch data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4010 00 offcore_response.pf_data_rd.remote_dram memory Offcore prefetch data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2010 00 offcore_response.pf_ifetch.any_dram memory Offcore prefetch code reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6040 00 offcore_response.pf_ifetch.any_llc_miss memory Offcore prefetch code reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF840 00 offcore_response.pf_ifetch.local_dram memory Offcore prefetch code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4040 00 offcore_response.pf_ifetch.remote_dram memory Offcore prefetch code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2040 00 offcore_response.pf_rfo.any_dram memory Offcore prefetch RFO requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6020 00 offcore_response.pf_rfo.any_llc_miss memory Offcore prefetch RFO requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF820 00 offcore_response.pf_rfo.local_dram memory Offcore prefetch RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4020 00 offcore_response.pf_rfo.remote_dram memory Offcore prefetch RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2020 00 offcore_response.prefetch.any_dram memory Offcore prefetch requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6070 00 offcore_response.prefetch.any_llc_miss memory Offcore prefetch requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF870 00 offcore_response.prefetch.local_dram memory Offcore prefetch requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4070 00 offcore_response.prefetch.remote_dram memory Offcore prefetch requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2070 00 es_reg_renames other ES segment renames event=0xd5,period=2000000,umask=1 00 io_transactions other I/O transactions event=0x6c,period=2000000,umask=1 00 l1i.cycles_stalled other L1I instruction fetch stall cycles event=0x80,period=2000000,umask=4 00 l1i.hits other L1I instruction fetch hits event=0x80,period=2000000,umask=1 00 l1i.misses other L1I instruction fetch misses event=0x80,period=2000000,umask=2 00 l1i.reads other L1I Instruction fetches event=0x80,period=2000000,umask=3 00 large_itlb.hit other Large ITLB hit event=0x82,period=200000,umask=1 00 load_dispatch.any other All loads dispatched event=0x13,period=2000000,umask=7 00 load_dispatch.mob other Loads dispatched from the MOB event=0x13,period=2000000,umask=4 00 load_dispatch.rs other Loads dispatched that bypass the MOB event=0x13,period=2000000,umask=1 00 load_dispatch.rs_delayed other Loads dispatched from stage 305 event=0x13,period=2000000,umask=2 00 partial_address_alias other False dependencies due to partial address aliasing event=7,period=200000,umask=1 00 sb_drain.any other All Store buffer stall cycles event=4,period=200000,umask=7 00 seg_rename_stalls other Segment rename stall cycles event=0xd4,period=2000000,umask=1 00 snoop_response.hit other Thread responded HIT to snoop event=0xb8,period=100000,umask=1 00 snoop_response.hite other Thread responded HITE to snoop event=0xb8,period=100000,umask=2 00 snoop_response.hitm other Thread responded HITM to snoop event=0xb8,period=100000,umask=4 00 sq_full_stall_cycles other Super Queue full stall cycles event=0xf6,period=2000000,umask=1 00 arith.cycles_div_busy pipeline Cycles the divider is busy event=0x14,period=2000000,umask=1 00 arith.div pipeline Divide Operations executed event=0x14,cmask=1,edge=1,inv=1,period=2000000,umask=1 00 arith.mul pipeline Multiply operations executed event=0x14,period=2000000,umask=2 00 baclear.bad_target pipeline BACLEAR asserted with bad target address event=0xe6,period=2000000,umask=2 00 baclear.clear pipeline BACLEAR asserted, regardless of cause event=0xe6,period=2000000,umask=1 00 baclear_force_iq pipeline Instruction queue forced BACLEAR event=0xa7,period=2000000,umask=1 00 bpu_clears.early pipeline Early Branch Prediciton Unit clears event=0xe8,period=2000000,umask=1 00 bpu_clears.late pipeline Late Branch Prediction Unit clears event=0xe8,period=2000000,umask=2 00 bpu_missed_call_ret pipeline Branch prediction unit missed call or return event=0xe5,period=2000000,umask=1 00 br_inst_exec.any pipeline Branch instructions executed event=0x88,period=200000,umask=0x7f 00 br_inst_exec.cond pipeline Conditional branch instructions executed event=0x88,period=200000,umask=1 00 br_inst_exec.direct pipeline Unconditional branches executed event=0x88,period=200000,umask=2 00 br_inst_exec.direct_near_call pipeline Unconditional call branches executed event=0x88,period=20000,umask=0x10 00 br_inst_exec.indirect_near_call pipeline Indirect call branches executed event=0x88,period=20000,umask=0x20 00 br_inst_exec.indirect_non_call pipeline Indirect non call branches executed event=0x88,period=20000,umask=4 00 br_inst_exec.near_calls pipeline Call branches executed event=0x88,period=20000,umask=0x30 00 br_inst_exec.non_calls pipeline All non call branches executed event=0x88,period=200000,umask=7 00 br_inst_exec.return_near pipeline Indirect return branches executed event=0x88,period=20000,umask=8 00 br_inst_exec.taken pipeline Taken branches executed event=0x88,period=200000,umask=0x40 00 br_inst_retired.all_branches pipeline Retired branch instructions (Precise Event) event=0xc4,period=200000,umask=4 00 br_inst_retired.conditional pipeline Retired conditional branch instructions (Precise Event) event=0xc4,period=200000,umask=1 00 br_inst_retired.near_call pipeline Retired near call instructions (Precise Event) event=0xc4,period=20000,umask=2 00 br_misp_exec.any pipeline Mispredicted branches executed event=0x89,period=20000,umask=0x7f 00 br_misp_exec.cond pipeline Mispredicted conditional branches executed event=0x89,period=20000,umask=1 00 br_misp_exec.direct pipeline Mispredicted unconditional branches executed event=0x89,period=20000,umask=2 00 br_misp_exec.direct_near_call pipeline Mispredicted non call branches executed event=0x89,period=2000,umask=0x10 00 br_misp_exec.indirect_near_call pipeline Mispredicted indirect call branches executed event=0x89,period=2000,umask=0x20 00 br_misp_exec.indirect_non_call pipeline Mispredicted indirect non call branches executed event=0x89,period=2000,umask=4 00 br_misp_exec.near_calls pipeline Mispredicted call branches executed event=0x89,period=2000,umask=0x30 00 br_misp_exec.non_calls pipeline Mispredicted non call branches executed event=0x89,period=20000,umask=7 00 br_misp_exec.return_near pipeline Mispredicted return branches executed event=0x89,period=2000,umask=8 00 br_misp_exec.taken pipeline Mispredicted taken branches executed event=0x89,period=20000,umask=0x40 00 br_misp_retired.near_call pipeline Mispredicted near retired calls (Precise Event) event=0xc5,period=2000,umask=2 00 cpu_clk_unhalted.ref pipeline Reference cycles when thread is not halted (fixed counter) event=0x0,umask=0x03,period=2000003 00 cpu_clk_unhalted.ref_p pipeline Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) event=0x3c,period=100000,umask=1 00 cpu_clk_unhalted.thread pipeline Cycles when thread is not halted (fixed counter) event=0x3c,period=2000003 00 cpu_clk_unhalted.thread_p pipeline Cycles when thread is not halted (programmable counter) event=0x3c,period=2000000 00 cpu_clk_unhalted.total_cycles pipeline Total CPU cycles event=0x3c,cmask=2,inv=1,period=2000000 00 ild_stall.any pipeline Any Instruction Length Decoder stall cycles event=0x87,period=2000000,umask=0xf 00 ild_stall.iq_full pipeline Instruction Queue full stall cycles event=0x87,period=2000000,umask=4 00 ild_stall.lcp pipeline Length Change Prefix stall cycles event=0x87,period=2000000,umask=1 00 ild_stall.mru pipeline Stall cycles due to BPU MRU bypass event=0x87,period=2000000,umask=2 00 ild_stall.regen pipeline Regen stall cycles event=0x87,period=2000000,umask=8 00 inst_decoded.dec0 pipeline Instructions that must be decoded by decoder 0 event=0x18,period=2000000,umask=1 00 inst_queue_writes pipeline Instructions written to instruction queue event=0x17,period=2000000,umask=1 00 inst_queue_write_cycles pipeline Cycles instructions are written to the instruction queue event=0x1e,period=2000000,umask=1 00 inst_retired.any pipeline Instructions retired (fixed counter) event=0xc0,period=2000003 00 inst_retired.any_p pipeline Instructions retired (Programmable counter and Precise Event) (Precise event) event=0xc0,period=2000003 00 inst_retired.mmx pipeline Retired MMX instructions (Precise Event) event=0xc0,period=2000000,umask=4 00 inst_retired.total_cycles pipeline Total cycles (Precise Event) event=0xc0,cmask=16,inv=1,period=2000000,umask=1 00 inst_retired.total_cycles_ps pipeline Total cycles (Precise Event) event=0xc0,cmask=16,inv=1,period=2000000,umask=1 00 inst_retired.x87 pipeline Retired floating-point operations (Precise Event) event=0xc0,period=2000000,umask=2 00 load_hit_pre pipeline Load operations conflicting with software prefetches event=0x4c,period=200000,umask=1 00 lsd.active pipeline Cycles when uops were delivered by the LSD event=0xa8,cmask=1,period=2000000,umask=1 00 lsd.inactive pipeline Cycles no uops were delivered by the LSD event=0xa8,cmask=1,inv=1,period=2000000,umask=1 00 lsd_overflow pipeline Loops that can't stream from the instruction queue event=0x20,period=2000000,umask=1 00 machine_clears.cycles pipeline Cycles machine clear asserted event=0xc3,period=20000,umask=1 00 machine_clears.mem_order pipeline Execution pipeline restart due to Memory ordering conflicts event=0xc3,period=20000,umask=2 00 machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=20000,umask=4 00 rat_stalls.any pipeline All RAT stall cycles event=0xd2,period=2000000,umask=0xf 00 rat_stalls.flags pipeline Flag stall cycles event=0xd2,period=2000000,umask=1 00 rat_stalls.registers pipeline Partial register stall cycles event=0xd2,period=2000000,umask=2 00 rat_stalls.rob_read_port pipeline ROB read port stalls cycles event=0xd2,period=2000000,umask=4 00 rat_stalls.scoreboard pipeline Scoreboard stall cycles event=0xd2,period=2000000,umask=8 00 resource_stalls.any pipeline Resource related stall cycles event=0xa2,period=2000000,umask=1 00 resource_stalls.fpcw pipeline FPU control word write stall cycles event=0xa2,period=2000000,umask=0x20 00 resource_stalls.load pipeline Load buffer stall cycles event=0xa2,period=2000000,umask=2 00 resource_stalls.mxcsr pipeline MXCSR rename stall cycles event=0xa2,period=2000000,umask=0x40 00 resource_stalls.other pipeline Other Resource related stall cycles event=0xa2,period=2000000,umask=0x80 00 resource_stalls.rob_full pipeline ROB full stall cycles event=0xa2,period=2000000,umask=0x10 00 resource_stalls.rs_full pipeline Reservation Station full stall cycles event=0xa2,period=2000000,umask=4 00 resource_stalls.store pipeline Store buffer stall cycles event=0xa2,period=2000000,umask=8 00 ssex_uops_retired.packed_double pipeline SIMD Packed-Double Uops retired (Precise Event) event=0xc7,period=200000,umask=4 00 ssex_uops_retired.packed_single pipeline SIMD Packed-Single Uops retired (Precise Event) event=0xc7,period=200000,umask=1 00 ssex_uops_retired.scalar_double pipeline SIMD Scalar-Double Uops retired (Precise Event) event=0xc7,period=200000,umask=8 00 ssex_uops_retired.scalar_single pipeline SIMD Scalar-Single Uops retired (Precise Event) event=0xc7,period=200000,umask=2 00 ssex_uops_retired.vector_integer pipeline SIMD Vector Integer Uops retired (Precise Event) event=0xc7,period=200000,umask=0x10 00 uops_decoded.esp_folding pipeline Stack pointer instructions decoded event=0xd1,period=2000000,umask=4 00 uops_decoded.esp_sync pipeline Stack pointer sync operations event=0xd1,period=2000000,umask=8 00 uops_decoded.ms_cycles_active pipeline Uops decoded by Microcode Sequencer event=0xd1,cmask=1,period=2000000,umask=2 00 uops_decoded.stall_cycles pipeline Cycles no Uops are decoded event=0xd1,cmask=1,inv=1,period=2000000,umask=1 00 uops_executed.core_active_cycles pipeline Cycles Uops executed on any port (core count) event=0xb1,any=1,cmask=1,period=2000000,umask=0x3f 00 uops_executed.core_active_cycles_no_port5 pipeline Cycles Uops executed on ports 0-4 (core count) event=0xb1,any=1,cmask=1,period=2000000,umask=0x1f 00 uops_executed.core_stall_count pipeline Uops executed on any port (core count) event=0xb1,any=1,cmask=1,edge=1,inv=1,period=2000000,umask=0x3f 00 uops_executed.core_stall_count_no_port5 pipeline Uops executed on ports 0-4 (core count) event=0xb1,any=1,cmask=1,edge=1,inv=1,period=2000000,umask=0x1f 00 uops_executed.core_stall_cycles pipeline Cycles no Uops issued on any port (core count) event=0xb1,any=1,cmask=1,inv=1,period=2000000,umask=0x3f 00 uops_executed.core_stall_cycles_no_port5 pipeline Cycles no Uops issued on ports 0-4 (core count) event=0xb1,any=1,cmask=1,inv=1,period=2000000,umask=0x1f 00 uops_executed.port0 pipeline Uops executed on port 0 event=0xb1,period=2000000,umask=1 00 uops_executed.port015 pipeline Uops issued on ports 0, 1 or 5 event=0xb1,period=2000000,umask=0x40 00 uops_executed.port015_stall_cycles pipeline Cycles no Uops issued on ports 0, 1 or 5 event=0xb1,cmask=1,inv=1,period=2000000,umask=0x40 00 uops_executed.port1 pipeline Uops executed on port 1 event=0xb1,period=2000000,umask=2 00 uops_executed.port234_core pipeline Uops issued on ports 2, 3 or 4 event=0xb1,any=1,period=2000000,umask=0x80 00 uops_executed.port2_core pipeline Uops executed on port 2 (core count) event=0xb1,any=1,period=2000000,umask=4 00 uops_executed.port3_core pipeline Uops executed on port 3 (core count) event=0xb1,any=1,period=2000000,umask=8 00 uops_executed.port4_core pipeline Uops executed on port 4 (core count) event=0xb1,any=1,period=2000000,umask=0x10 00 uops_executed.port5 pipeline Uops executed on port 5 event=0xb1,period=2000000,umask=0x20 00 uops_issued.any pipeline Uops issued event=0xe,period=2000000,umask=1 00 uops_issued.core_stall_cycles pipeline Cycles no Uops were issued on any thread event=0xe,any=1,cmask=1,inv=1,period=2000000,umask=1 00 uops_issued.cycles_all_threads pipeline Cycles Uops were issued on either thread event=0xe,any=1,cmask=1,period=2000000,umask=1 00 uops_issued.fused pipeline Fused Uops issued event=0xe,period=2000000,umask=2 00 uops_issued.stall_cycles pipeline Cycles no Uops were issued event=0xe,cmask=1,inv=1,period=2000000,umask=1 00 uops_retired.active_cycles pipeline Cycles Uops are being retired (Precise event) event=0xc2,cmask=1,period=2000000,umask=1 00 uops_retired.any pipeline Uops retired (Precise Event) event=0xc2,period=2000000,umask=1 00 uops_retired.macro_fused pipeline Macro-fused Uops retired (Precise Event) event=0xc2,period=2000000,umask=4 00 uops_retired.retire_slots pipeline Retirement slots used (Precise Event) event=0xc2,period=2000000,umask=2 00 uops_retired.stall_cycles pipeline Cycles Uops are not retiring (Precise Event) event=0xc2,cmask=1,inv=1,period=2000000,umask=1 00 uops_retired.total_cycles pipeline Total cycles using precise uop retired event (Precise Event) event=0xc2,cmask=16,inv=1,period=2000000,umask=1 00 uop_unfusion pipeline Uop unfusions due to FP exceptions event=0xdb,period=2000000,umask=1 00 dtlb_load_misses.any virtual memory DTLB load misses event=8,period=200000,umask=1 00 dtlb_load_misses.pde_miss virtual memory DTLB load miss caused by low part of address event=8,period=200000,umask=0x20 00 dtlb_load_misses.stlb_hit virtual memory DTLB second level hit event=8,period=2000000,umask=0x10 00 dtlb_load_misses.walk_completed virtual memory DTLB load miss page walks complete event=8,period=200000,umask=2 00 dtlb_misses.any virtual memory DTLB misses event=0x49,period=200000,umask=1 00 dtlb_misses.stlb_hit virtual memory DTLB first level misses but second level hit event=0x49,period=200000,umask=0x10 00 dtlb_misses.walk_completed virtual memory DTLB miss page walks event=0x49,period=200000,umask=2 00 itlb_flush virtual memory ITLB flushes event=0xae,period=2000000,umask=1 00 itlb_misses.any virtual memory ITLB miss event=0x85,period=200000,umask=1 00 itlb_misses.walk_completed virtual memory ITLB miss page walks event=0x85,period=200000,umask=2 00 itlb_miss_retired virtual memory Retired instructions that missed the ITLB (Precise Event) event=0xc8,period=200000,umask=0x20 00 mem_load_retired.dtlb_miss virtual memory Retired loads that miss the DTLB (Precise Event) event=0xcb,period=200000,umask=0x80 00 mem_store_retired.dtlb_miss virtual memory Retired stores that miss the DTLB (Precise Event) event=0xc,period=200000,umask=1 00 l2_rqsts.miss cache All requests that miss L2 cache event=0x24,period=200003,umask=0x3f 00 Counts all requests that miss L2 cache l2_rqsts.references cache All L2 requests event=0x24,period=200003,umask=0xff 00 Counts all L2 requests unc_arb_dat_occupancy.all uncore interconnect Each cycle counts number of any coherent requests at memory controller that were issued by any core event=0x85,umask=1 01 unc_arb_req_trk_occupancy.drd uncore interconnect Each cycle counts number of valid coherent Data Read entries. Such entry is defined as valid when it is allocated until deallocation. Does not include prefetches event=0x80,umask=2 01 unc_arb_trk_occupancy.all uncore interconnect Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk until deallocation. Accounts for Coherent and non-coherent traffic event=0x80,umask=1 01 unc_arb_trk_occupancy.rd uncore interconnect Each cycle counts number of valid coherent Data Read entries. Such entry is defined as valid when it is allocated until deallocation. Does not include prefetches event=0x80,umask=2 01 unc_arb_trk_requests.rd uncore interconnect Counts number of all coherent Data Read entries. Does not include prefetches event=0x81,umask=2 01 mem_load_uops_llc_hit_retired.xsnp_hit cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) (Precise event) event=0xd2,period=20011,umask=2 00 This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS) (Precise event) mem_load_uops_llc_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS) (Precise event) event=0xd2,period=20011,umask=4 00 This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS) (Precise event) mem_load_uops_llc_hit_retired.xsnp_miss cache Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) (Precise event) event=0xd2,period=20011,umask=1 00 mem_load_uops_llc_hit_retired.xsnp_none cache Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) event=0xd2,period=100003,umask=8 00 mem_load_uops_misc_retired.llc_miss cache Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS) (Precise event) event=0xd4,period=100007,umask=2 00 This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS) (Precise event) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) (Precise event) event=0xd1,period=100003,umask=0x40 00 mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) (Precise event) event=0xd1,period=2000003,umask=1 00 mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) (Precise event) event=0xd1,period=100003,umask=2 00 mem_load_uops_retired.llc_hit cache Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) event=0xd1,period=50021,umask=4 00 This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS) (Precise event) mem_uops_retired.all_loads cache All retired load uops. (Precise Event - PEBS) (Precise event) event=0xd0,period=2000003,umask=0x81 00 This event counts the number of load uops retired (Precise Event) (Precise event) mem_uops_retired.all_stores cache All retired store uops. (Precise Event - PEBS) (Precise event) event=0xd0,period=2000003,umask=0x82 00 This event counts the number of store uops retired. (Precise Event - PEBS) (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access. (Precise Event - PEBS) (Precise event) event=0xd0,period=100007,umask=0x21 00 mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x41 00 This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x42 00 This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x11 00 mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x12 00 offcore_requests.demand_code_rd cache Cacheable and noncacheable code read requests event=0xb0,period=100003,umask=2 00 offcore_response.all_code_rd.llc_hit.hitm_other_core cache Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0244 00 offcore_response.all_code_rd.llc_hit.snoop_miss cache Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0244 00 offcore_response.all_data_rd.llc_hit.snoop_miss cache Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0091 00 offcore_response.all_pf_code_rd.llc_hit.any_response cache Counts all prefetch code reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0240 00 offcore_response.all_pf_code_rd.llc_hit.hitm_other_core cache Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0240 00 offcore_response.all_pf_code_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0240 00 offcore_response.all_pf_code_rd.llc_hit.no_snoop_needed cache Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0240 00 offcore_response.all_pf_code_rd.llc_hit.snoop_miss cache Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0240 00 offcore_response.all_pf_data_rd.llc_hit.any_response cache Counts all prefetch data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0090 00 offcore_response.all_pf_data_rd.llc_hit.snoop_miss cache Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0090 00 offcore_response.all_pf_rfo.llc_hit.any_response cache Counts all prefetch RFOs that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0120 00 offcore_response.all_pf_rfo.llc_hit.hitm_other_core cache Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0120 00 offcore_response.all_pf_rfo.llc_hit.hit_other_core_no_fwd cache Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0120 00 offcore_response.all_pf_rfo.llc_hit.no_snoop_needed cache Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0120 00 offcore_response.all_pf_rfo.llc_hit.snoop_miss cache Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0120 00 offcore_response.all_reads.any_response cache Counts all data/code/rfo references (demand & prefetch) event=0xb7,period=100003,umask=1,offcore_rsp=0x000107F7 00 offcore_response.all_reads.llc_hit.hitm_other_core cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c03f7 00 offcore_response.all_reads.llc_hit.hit_other_core_no_fwd cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c03f7 00 offcore_response.all_reads.llc_hit.no_snoop_needed cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c03f7 00 offcore_response.all_reads.llc_hit.snoop_miss cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c03f7 00 offcore_response.all_rfo.any_response cache Counts all demand & prefetch prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x00010122 00 offcore_response.all_rfo.llc_hit.hitm_other_core cache Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0122 00 offcore_response.all_rfo.llc_hit.hit_other_core_no_fwd cache Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0122 00 offcore_response.all_rfo.llc_hit.snoop_miss cache Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0122 00 offcore_response.corewb.any_response cache OFFCORE_RESPONSE.COREWB.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10008 00 offcore_response.data_in.any_response cache REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10433 00 offcore_response.demand_code_rd.llc_hit.hitm_other_core cache Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0004 00 offcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwd cache Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0004 00 offcore_response.demand_code_rd.llc_hit.snoop_miss cache Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0004 00 offcore_response.demand_data_rd.any_response cache Counts all demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x00010001 00 offcore_response.demand_data_rd.llc_hit.snoop_miss cache Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0001 00 offcore_response.demand_rfo.any_response cache Counts all demand rfo's event=0xb7,period=100003,umask=1,offcore_rsp=0x00010002 00 offcore_response.demand_rfo.llc_hit.hit_other_core_no_fwd cache Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0002 00 offcore_response.demand_rfo.llc_hit.snoop_miss cache Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0002 00 offcore_response.demand_rfo.llc_hit_m.hitm cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040002 00 offcore_response.other.portio_mmio_uc cache Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses event=0xb7,period=100003,umask=1,offcore_rsp=0x2380408000 00 offcore_response.pf_ifetch.any_response cache REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10040 00 offcore_response.pf_l2_code_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0040 00 offcore_response.pf_l2_code_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0040 00 offcore_response.pf_l2_code_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0040 00 offcore_response.pf_l2_code_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0040 00 offcore_response.pf_l2_data_rd.llc_hit.any_response cache Counts all prefetch (that bring data to L2) data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0010 00 offcore_response.pf_l2_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to L2) RFOs that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0020 00 offcore_response.pf_l2_rfo.llc_hit.hitm_other_core cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0020 00 offcore_response.pf_l2_rfo.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0020 00 offcore_response.pf_l2_rfo.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0020 00 offcore_response.pf_l2_rfo.llc_hit.snoop_miss cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0020 00 offcore_response.pf_llc_code_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0200 00 offcore_response.pf_llc_code_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0200 00 offcore_response.pf_llc_code_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0200 00 offcore_response.pf_llc_code_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0200 00 offcore_response.pf_llc_data_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0080 00 offcore_response.pf_llc_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0100 00 offcore_response.pf_llc_rfo.llc_hit.hitm_other_core cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0100 00 offcore_response.pf_llc_rfo.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0100 00 offcore_response.pf_llc_rfo.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0100 00 offcore_response.pf_llc_rfo.llc_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0100 00 offcore_response.pf_l_data_rd.any_response cache REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10080 00 offcore_response.pf_l_ifetch.any_response cache REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10200 00 idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more information offcore_response.all_pf_code_rd.llc_miss.dram memory Counts all prefetch code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400240 00 offcore_response.all_pf_data_rd.llc_miss.dram memory Counts all prefetch data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400090 00 offcore_response.all_pf_rfo.llc_miss.dram memory Counts all prefetch RFOs that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400120 00 offcore_response.all_rfo.llc_miss.dram memory Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400122 00 offcore_response.any_request.llc_miss_local.dram memory REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80408fff 00 This event counts any requests that miss the LLC where the data was returned from local DRAM offcore_response.data_in_socket.llc_miss.local_dram memory Counts LLC replacements event=0xb7,period=100003,umask=1,offcore_rsp=0x6004001b3 00 This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM offcore_response.data_in_socket.llc_miss_local.any_llc_hit memory REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT event=0xb7,period=100003,umask=1,offcore_rsp=0x17004001b3 00 offcore_response.demand_ifetch.llc_miss_local.dram memory REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80400004 00 offcore_response.demand_rfo.llc_miss.dram memory Counts demand data writes (RFOs) that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400002 00 offcore_response.pf_data_rd.llc_miss_local.dram memory REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80400010 00 offcore_response.pf_ifetch.llc_miss_local.dram memory REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80400040 00 offcore_response.pf_l2_code_rd.llc_miss.dram memory Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400040 00 offcore_response.pf_l2_data_rd.llc_miss.dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400010 00 offcore_response.pf_l2_rfo.llc_miss.dram memory Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400020 00 offcore_response.pf_llc_code_rd.llc_miss.dram memory Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400200 00 offcore_response.pf_llc_data_rd.llc_miss.dram memory Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400080 00 offcore_response.pf_llc_rfo.llc_miss.dram memory Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400100 00 offcore_response.pf_l_data_rd.llc_miss_local.dram memory REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80400080 00 offcore_response.pf_l_ifetch.llc_miss_local.dram memory REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80400200 00 page_walks.llc_miss memory Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND event=0xbe,period=100003,umask=1 00 br_inst_retired.conditional pipeline Conditional branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=400009,umask=1 00 br_inst_retired.near_call pipeline Direct and indirect near call instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=100007,umask=2 00 br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS) (Precise event) event=0xc4,period=100007,umask=2 00 br_inst_retired.near_return pipeline Return instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=100007,umask=8 00 br_inst_retired.near_taken pipeline Taken branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=400009,umask=0x20 00 br_misp_retired.conditional pipeline Mispredicted conditional branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc5,period=400009,umask=1 00 br_misp_retired.near_call pipeline Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS) (Precise event) event=0xc5,period=100007,umask=2 00 br_misp_retired.not_taken pipeline Mispredicted not taken branch instructions retired.(Precise Event - PEBS) (Precise event) event=0xc5,period=400009,umask=0x10 00 br_misp_retired.taken pipeline Mispredicted taken branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc5,period=400009,umask=0x20 00 ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=3,period=100003,umask=2 00 This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued partial_rat_stalls.flags_merge_uop_cycles pipeline Performance sensitive flags-merging uops added by Sandy Bridge u-arch event=0x59,cmask=1,period=2000003,umask=0x20 00 This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual partial_rat_stalls.slow_lea_window pipeline Cycles with at least one slow LEA uop being allocated event=0x59,period=2000003,umask=0x40 00 This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions uops_retired.all pipeline Actually retired uops. (Precise Event - PEBS) (Precise event) event=0xc2,period=2000003,umask=1 00 This event counts the number of micro-ops retired. (Precise Event) (Precise event) uops_retired.retire_slots pipeline Retirement slots used. (Precise Event - PEBS) (Precise event) event=0xc2,period=2000003,umask=2 00 This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS) (Precise event) mem_load_l3_miss_retired.remote_pmm cache Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches (Precise event) event=0xd3,period=100007,umask=0x10 00 Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (Precise event) mem_load_retired.local_pmm cache Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches Supports address when precise (Precise event) event=0xd1,period=1000003,umask=0x80 00 Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 Supports address when precise (Precise event) ocr.demand_data_rd.local_socket_pmm other Counts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x700C00001 00 ocr.demand_data_rd.pmm other Counts demand data reads that were supplied by PMM event=0x2a,period=100003,umask=1,offcore_rsp=0x703C00001 00 ocr.demand_data_rd.remote_pmm other Counts demand data reads that were supplied by PMM attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x703000001 00 ocr.reads_to_core.local_socket_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x700C04477 00 ocr.reads_to_core.remote_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x703004477 00 unc_cha_tor_inserts.ia_miss_drd_opt_pref_remote uncore cache Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target remote memory event=0x35,umask=0xc8a77e01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_drd_opt_remote uncore cache Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd_Opt, and target remote memory event=0x35,umask=0xc8277e01 01 TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC unc_b2hot_clockticks uncore interconnect UNC_B2HOT_CLOCKTICKS event=1,umask=1 01 core_reject_l2q.all cache Counts the number of request that were not accepted into the L2Q because the L2Q is FULL event=0x31,period=200003 00 Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) fetch_stall.icache_fill_pending_cycles cache Cycles code-fetch stalled due to an outstanding ICache miss event=0x86,period=200003,umask=4 00 Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy. Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events l2_reject_xq.all cache Counts the number of request from the L2 that were not accepted into the XQ event=0x30,period=200003 00 This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims) longest_lat_cache.miss cache L2 cache request misses event=0x2e,period=200003,umask=0x41 00 This event counts the total number of L2 cache references and the number of L2 cache misses respectively longest_lat_cache.reference cache L2 cache requests from this core event=0x2e,period=200003,umask=0x4f 00 This event counts requests originating from the core that references a cache line in the L2 cache mem_uops_retired.all_loads cache All Loads event=4,period=200003,umask=0x40 00 This event counts the number of load ops retired mem_uops_retired.all_stores cache All Stores event=4,period=200003,umask=0x80 00 This event counts the number of store ops retired mem_uops_retired.hitm cache Cross core or cross module hitm (Precise event) event=4,period=200003,umask=0x20 00 This event counts the number of load ops retired that got data from the other core or from the other module (Precise event) mem_uops_retired.l1_miss_loads cache Loads missed L1 event=4,period=200003,umask=1 00 This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted mem_uops_retired.l2_hit_loads cache Loads hit L2 (Precise event) event=4,period=200003,umask=2 00 This event counts the number of load ops retired that hit in the L2 (Precise event) mem_uops_retired.l2_miss_loads cache Loads missed L2 (Precise event) event=4,period=100007,umask=4 00 This event counts the number of load ops retired that miss in the L2 (Precise event) mem_uops_retired.utlb_miss cache Loads missed UTLB event=4,period=200003,umask=0x10 00 This event counts the number of load ops retired that had UTLB miss offcore_response cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction event=0xb7,period=100007,umask=1 00 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction offcore_response.any_code_rd.any_response cache Counts any code reads (demand & prefetch) that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010044 00 offcore_response.any_code_rd.l2_miss.any cache Counts any code reads (demand & prefetch) that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000044 00 offcore_response.any_code_rd.l2_miss.hitm_other_core cache Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000044 00 offcore_response.any_code_rd.l2_miss.hit_other_core_no_fwd cache Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000044 00 offcore_response.any_code_rd.l2_miss.snoop_miss cache Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000044 00 offcore_response.any_data_rd.any_response cache Counts any data read (demand & prefetch) that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000013091 00 offcore_response.any_data_rd.l2_miss.any cache Counts any data read (demand & prefetch) that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680003091 00 offcore_response.any_data_rd.l2_miss.hitm_other_core cache Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000003091 00 offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwd cache Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400003091 00 offcore_response.any_data_rd.l2_miss.snoop_miss cache Counts any data read (demand & prefetch) that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200003091 00 offcore_response.any_request.any_response cache Counts any request that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000018008 00 offcore_response.any_request.l2_miss.hitm_other_core cache Counts any request that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000008008 00 offcore_response.any_request.l2_miss.hit_other_core_no_fwd cache Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400008008 00 offcore_response.any_request.l2_miss.snoop_miss cache Counts any request that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200008008 00 offcore_response.any_rfo.any_response cache Counts any rfo reads (demand & prefetch) that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010022 00 offcore_response.any_rfo.l2_miss.any cache Counts any rfo reads (demand & prefetch) that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000022 00 offcore_response.any_rfo.l2_miss.hitm_other_core cache Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000022 00 offcore_response.any_rfo.l2_miss.hit_other_core_no_fwd cache Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000022 00 offcore_response.any_rfo.l2_miss.snoop_miss cache Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000022 00 offcore_response.corewb.l2_miss.any cache Counts writeback (modified to exclusive) that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000008 00 offcore_response.corewb.l2_miss.no_snoop_needed cache Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information event=0xb7,period=100007,umask=1,offcore_rsp=0x0080000008 00 offcore_response.demand_code_rd.any_response cache Counts demand and DCU prefetch instruction cacheline that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010004 00 offcore_response.demand_code_rd.l2_miss.any cache Counts demand and DCU prefetch instruction cacheline that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000004 00 offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwd cache Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000004 00 offcore_response.demand_code_rd.l2_miss.snoop_miss cache Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000004 00 offcore_response.demand_code_rd.outstanding cache Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000004 00 offcore_response.demand_data_rd.any_response cache Counts demand and DCU prefetch data read that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010001 00 offcore_response.demand_data_rd.l2_miss.any cache Counts demand and DCU prefetch data read that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000001 00 offcore_response.demand_data_rd.l2_miss.hitm_other_core cache Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000001 00 offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwd cache Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000001 00 offcore_response.demand_data_rd.l2_miss.snoop_miss cache Counts demand and DCU prefetch data read that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000001 00 offcore_response.demand_data_rd.outstanding cache Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000001 00 offcore_response.demand_rfo.l2_miss.any cache Counts demand and DCU prefetch RFOs that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000002 00 offcore_response.demand_rfo.l2_miss.hitm_other_core cache Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000002 00 offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwd cache Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000002 00 offcore_response.demand_rfo.l2_miss.snoop_miss cache Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000002 00 offcore_response.demand_rfo.outstanding cache Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000002 00 offcore_response.partial_reads.l2_miss.any cache Counts demand reads of partial cache lines (including UC and WC) that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000080 00 offcore_response.partial_writes.l2_miss.any cache Countsof demand RFO requests to write to partial cache lines that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000100 00 offcore_response.pf_l1_data_rd.any_response cache Counts DCU hardware prefetcher data read that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000012000 00 offcore_response.pf_l1_data_rd.l2_miss.any cache Counts DCU hardware prefetcher data read that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680002000 00 offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core cache Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000002000 00 offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwd cache Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400002000 00 offcore_response.pf_l1_data_rd.l2_miss.snoop_miss cache Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200002000 00 offcore_response.pf_l2_code_rd.l2_miss.any cache Counts code reads generated by L2 prefetchers that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000040 00 offcore_response.pf_l2_code_rd.l2_miss.hit_other_core_no_fwd cache Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000040 00 offcore_response.pf_l2_code_rd.l2_miss.snoop_miss cache Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000040 00 offcore_response.pf_l2_data_rd.l2_miss.any cache Counts data cacheline reads generated by L2 prefetchers that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000010 00 offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core cache Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000010 00 offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000010 00 offcore_response.pf_l2_data_rd.l2_miss.snoop_miss cache Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000010 00 offcore_response.pf_l2_rfo.l2_miss.any cache Counts RFO requests generated by L2 prefetchers that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000020 00 offcore_response.pf_l2_rfo.l2_miss.hitm_other_core cache Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000020 00 offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwd cache Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000020 00 offcore_response.pf_l2_rfo.l2_miss.snoop_miss cache Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000020 00 offcore_response.streaming_stores.l2_miss.any cache Counts streaming store that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680004800 00 rehabq.any_ld cache Any reissued load uops event=3,period=200003,umask=0x40 00 This event counts the number of load uops reissued from Rehabq rehabq.any_st cache Any reissued store uops event=3,period=200003,umask=0x80 00 This event counts the number of store uops reissued from Rehabq rehabq.ld_block_std_notready cache Loads blocked due to store data not ready event=3,period=200003,umask=2 00 This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time rehabq.ld_block_st_forward cache Loads blocked due to store forward restriction (Precise event) event=3,period=200003,umask=1 00 This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise event) rehabq.ld_splits cache Load uops that split cache line boundary (Precise event) event=3,period=200003,umask=8 00 This event counts the number of retire loads that experienced cache line boundary splits (Precise event) rehabq.lock cache Uops with lock semantics event=3,period=200003,umask=0x10 00 This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0) rehabq.sta_full cache Store address buffer full event=3,period=200003,umask=0x20 00 This event counts the number of retired stores that are delayed because there is not a store address buffer available rehabq.st_splits cache Store uops that split cache line boundary event=3,period=200003,umask=4 00 This event counts the number of retire stores that experienced cache line boundary splits machine_clears.fp_assist floating point Stalls due to FP assists event=0xc3,period=200003,umask=4 00 This event counts the number of times that pipeline stalled due to FP operations needing assists baclears.all frontend Counts the number of baclears event=0xe6,period=200003,umask=1 00 The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.ANY event counts the number of baclears for any type of branch baclears.cond frontend Counts the number of JCC baclears event=0xe6,period=200003,umask=0x10 00 The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Conditional Code) baclears baclears.return frontend Counts the number of RETURN baclears event=0xe6,period=200003,umask=8 00 The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.RETURN event counts the number of RETURN baclears decode_restriction.predecode_wrong frontend Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction event=0xe9,period=200003,umask=1 00 Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction icache.accesses frontend Instruction fetches event=0x80,period=200003,umask=3 00 This event counts all instruction fetches, not including most uncacheable fetches icache.hit frontend Instruction fetches from Icache event=0x80,period=200003,umask=1 00 This event counts all instruction fetches from the instruction cache icache.misses frontend Icache miss event=0x80,period=200003,umask=2 00 This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding ms_decoded.ms_entry frontend Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count event=0xe7,period=200003,umask=1 00 Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort. The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear. Background: UOPS are produced by two mechanisms. Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction. MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition. This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions machine_clears.memory_ordering memory Stalls due to Memory ordering event=0xc3,period=200003,umask=2 00 This event counts the number of times that pipeline was cleared due to memory ordering issues fetch_stall.all other Cycles code-fetch stalled due to any reason event=0x86,period=200003,umask=0x3f 00 Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events fetch_stall.itlb_fill_pending_cycles other Cycles code-fetch stalled due to an outstanding ITLB miss event=0x86,period=200003,umask=2 00 Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation br_inst_retired.all_branches pipeline Counts the number of branch instructions retired.. (Precise event) event=0xc4,period=200003 00 ALL_BRANCHES counts the number of any branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.all_taken_branches pipeline Counts the number of taken branch instructions retired (Must be precise) event=0xc4,period=200003,umask=0x80 00 ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Must be precise) br_inst_retired.call pipeline Counts the number of near CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf9 00 CALL counts the number of near CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xbf 00 FAR counts the number of far branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.ind_call pipeline Counts the number of near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfb 00 IND_CALL counts the number of near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.jcc pipeline Counts the number of JCC branch instructions retired (Precise event) event=0xc4,period=200003,umask=0x7e 00 JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.non_return_ind pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xeb 00 NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.rel_call pipeline Counts the number of near relative CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfd 00 REL_CALL counts the number of near relative CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.return pipeline Counts the number of near RET branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf7 00 RETURN counts the number of near RET branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.taken_jcc pipeline Counts the number of taken JCC branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfe 00 TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_misp_retired.all_branches pipeline Counts the number of mispredicted branch instructions retired (Precise event) event=0xc5,period=200003 00 ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.ind_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfb 00 IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.jcc pipeline Counts the number of mispredicted JCC branch instructions retired (Precise event) event=0xc5,period=200003,umask=0x7e 00 JCC counts the number of mispredicted conditional branches (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.non_return_ind pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xeb 00 NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xf7 00 RETURN counts the number of mispredicted near RET branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.taken_jcc pipeline Counts the number of mispredicted taken JCC branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfe 00 TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) cpu_clk_unhalted.core pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF cpu_clk_unhalted.core_p pipeline Core cycles when core is not halted event=0x3c,period=2000003 00 This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003 00 This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time cpu_clk_unhalted.ref_tsc pipeline Fixed Counter: Counts the number of unhalted reference clock cycles event=0,period=2000003,umask=3 00 Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF cycles_div_busy.all pipeline Cycles the divider is busy. Does not imply a stall waiting for the divider event=0xcd,period=2000003,umask=1 00 Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty. The divide instruction is one of the longest latency instructions in the machine. Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions inst_retired.any pipeline Fixed Counter: Counts the number of instructions retired event=0xc0,period=2000003 00 This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. Background: Modern microprocessors employ extensive pipelining and speculative techniques. Since sometimes an instruction is started but never completed, the notion of "retirement" is introduced. A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires. This counter measures the number of completed instructions. The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P inst_retired.any_p pipeline Instructions retired event=0xc0,period=2000003 00 This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers machine_clears.all pipeline Counts all machine clears event=0xc3,period=200003,umask=8 00 Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path. All instructions "older" than this one will be allowed to finish. This instruction and all "younger" instructions must be cleared, since they must not be allowed to complete. Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine. This means all older instructions are retired, and all pending stores (from older instructions) are completed. Then the new path of instructions from the front end are allowed to start into the machine. There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault). All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=200003,umask=1 00 This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors no_alloc_cycles.all pipeline Counts the number of cycles when no uops are allocated for any reason event=0xca,period=200003,umask=0x3f 00 The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle no_alloc_cycles.mispredicts pipeline Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted event=0xca,period=200003,umask=4 00 Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted no_alloc_cycles.not_delivered pipeline Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation event=0xca,period=200003,umask=0x50 00 The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth no_alloc_cycles.rat_stall pipeline Counts the number of cycles when no uops are allocated and a RATstall is asserted event=0xca,period=200003,umask=0x20 00 no_alloc_cycles.rob_full pipeline Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available) event=0xca,period=200003,umask=1 00 Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available) rs_full_stall.all pipeline Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts event=0xcb,period=200003,umask=0x1f 00 rs_full_stall.mec pipeline Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M event=0xcb,period=200003,umask=1 00 Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M uops_retired.all pipeline Micro-ops retired event=0xc2,period=2000003,umask=0x10 00 This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops uops_retired.ms pipeline MSROM micro-ops retired event=0xc2,period=2000003,umask=1 00 This event counts the number of micro-ops retired that were supplied from MSROM mem_uops_retired.dtlb_miss_loads virtual memory Loads missed DTLB (Precise event) event=4,period=200003,umask=8 00 This event counts the number of load ops retired that had DTLB miss (Precise event) page_walks.cycles virtual memory Total cycles for all the page walks. (I-side and D-side) event=5,period=200003,umask=3 00 This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event page_walks.d_side_cycles virtual memory Duration of D-side page-walks in core cycles event=5,period=200003,umask=1 00 This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks page_walks.d_side_walks virtual memory D-side page-walks event=5,edge=1,period=100003,umask=1 00 This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks page_walks.i_side_cycles virtual memory Duration of I-side page-walks in core cycles event=5,period=200003,umask=2 00 This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks page_walks.i_side_walks virtual memory I-side page-walks event=5,edge=1,period=100003,umask=2 00 This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks page_walks.walks virtual memory Total page walks that are completed (I-side and D-side) event=5,edge=1,period=100003,umask=3 00 This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks l2_lines_out.non_silent cache Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 event=0xf2,period=200003,umask=2 00 l2_lines_out.silent cache Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event event=0xf2,period=200003,umask=1 00 offcore_response cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction event=0xb7,period=100003,umask=1 00 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction offcore_response.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC01C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10001C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4001C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2001C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x801C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1001C0004 00 offcore_response.demand_code_rd.l3_hit.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x401C0004 00 offcore_response.demand_code_rd.l3_hit_e.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0080004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400080004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100080004 00 offcore_response.demand_code_rd.l3_hit_e.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40080004 00 offcore_response.demand_code_rd.l3_hit_m.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0040004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400040004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100040004 00 offcore_response.demand_code_rd.l3_hit_m.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40040004 00 offcore_response.demand_code_rd.l3_hit_s.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0100004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400100004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100100004 00 offcore_response.demand_code_rd.l3_hit_s.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40100004 00 offcore_response.demand_code_rd.l4_hit_local_l4.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40400004 00 offcore_response.demand_code_rd.supplier_none.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0020004 00 offcore_response.demand_code_rd.supplier_none.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40020004 00 offcore_response.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC01C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10001C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4001C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2001C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x801C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1001C0001 00 offcore_response.demand_data_rd.l3_hit.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x401C0001 00 offcore_response.demand_data_rd.l3_hit_e.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0080001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400080001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100080001 00 offcore_response.demand_data_rd.l3_hit_e.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40080001 00 offcore_response.demand_data_rd.l3_hit_m.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0040001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400040001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100040001 00 offcore_response.demand_data_rd.l3_hit_m.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40040001 00 offcore_response.demand_data_rd.l3_hit_s.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0100001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400100001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100100001 00 offcore_response.demand_data_rd.l3_hit_s.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40100001 00 offcore_response.demand_data_rd.l4_hit_local_l4.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40400001 00 offcore_response.demand_data_rd.supplier_none.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0020001 00 offcore_response.demand_data_rd.supplier_none.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40020001 00 offcore_response.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC01C0002 00 offcore_response.demand_rfo.l3_hit.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x10001C0002 00 offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x4001C0002 00 offcore_response.demand_rfo.l3_hit.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2001C0002 00 offcore_response.demand_rfo.l3_hit.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x801C0002 00 offcore_response.demand_rfo.l3_hit.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1001C0002 00 offcore_response.demand_rfo.l3_hit.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x401C0002 00 offcore_response.demand_rfo.l3_hit_e.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0080002 00 offcore_response.demand_rfo.l3_hit_e.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080002 00 offcore_response.demand_rfo.l3_hit_e.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x400080002 00 offcore_response.demand_rfo.l3_hit_e.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200080002 00 offcore_response.demand_rfo.l3_hit_e.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80080002 00 offcore_response.demand_rfo.l3_hit_e.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x100080002 00 offcore_response.demand_rfo.l3_hit_e.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x40080002 00 offcore_response.demand_rfo.l3_hit_m.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0040002 00 offcore_response.demand_rfo.l3_hit_m.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040002 00 offcore_response.demand_rfo.l3_hit_m.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x400040002 00 offcore_response.demand_rfo.l3_hit_m.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200040002 00 offcore_response.demand_rfo.l3_hit_m.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80040002 00 offcore_response.demand_rfo.l3_hit_m.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x100040002 00 offcore_response.demand_rfo.l3_hit_m.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x40040002 00 offcore_response.demand_rfo.l3_hit_s.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0100002 00 offcore_response.demand_rfo.l3_hit_s.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100002 00 offcore_response.demand_rfo.l3_hit_s.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x400100002 00 offcore_response.demand_rfo.l3_hit_s.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200100002 00 offcore_response.demand_rfo.l3_hit_s.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80100002 00 offcore_response.demand_rfo.l3_hit_s.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x100100002 00 offcore_response.demand_rfo.l3_hit_s.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x40100002 00 offcore_response.demand_rfo.l4_hit_local_l4.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0400002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000400002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x400400002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200400002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80400002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x100400002 00 offcore_response.demand_rfo.l4_hit_local_l4.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x40400002 00 offcore_response.demand_rfo.supplier_none.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0020002 00 offcore_response.demand_rfo.supplier_none.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020002 00 offcore_response.demand_rfo.supplier_none.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x400020002 00 offcore_response.demand_rfo.supplier_none.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200020002 00 offcore_response.demand_rfo.supplier_none.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80020002 00 offcore_response.demand_rfo.supplier_none.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x100020002 00 offcore_response.demand_rfo.supplier_none.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x40020002 00 offcore_response.other.l3_hit.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC01C8000 00 offcore_response.other.l3_hit.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x10001C8000 00 offcore_response.other.l3_hit.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x4001C8000 00 offcore_response.other.l3_hit.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2001C8000 00 offcore_response.other.l3_hit.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x801C8000 00 offcore_response.other.l3_hit.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1001C8000 00 offcore_response.other.l3_hit.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x401C8000 00 offcore_response.other.l3_hit_e.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0088000 00 offcore_response.other.l3_hit_e.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1000088000 00 offcore_response.other.l3_hit_e.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x400088000 00 offcore_response.other.l3_hit_e.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200088000 00 offcore_response.other.l3_hit_e.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80088000 00 offcore_response.other.l3_hit_e.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x100088000 00 offcore_response.other.l3_hit_e.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x40088000 00 offcore_response.other.l3_hit_m.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0048000 00 offcore_response.other.l3_hit_m.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1000048000 00 offcore_response.other.l3_hit_m.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x400048000 00 offcore_response.other.l3_hit_m.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200048000 00 offcore_response.other.l3_hit_m.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80048000 00 offcore_response.other.l3_hit_m.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x100048000 00 offcore_response.other.l3_hit_m.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x40048000 00 offcore_response.other.l3_hit_s.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0108000 00 offcore_response.other.l3_hit_s.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1000108000 00 offcore_response.other.l3_hit_s.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x400108000 00 offcore_response.other.l3_hit_s.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200108000 00 offcore_response.other.l3_hit_s.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80108000 00 offcore_response.other.l3_hit_s.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x100108000 00 offcore_response.other.l3_hit_s.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x40108000 00 offcore_response.other.l4_hit_local_l4.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0408000 00 offcore_response.other.l4_hit_local_l4.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1000408000 00 offcore_response.other.l4_hit_local_l4.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x400408000 00 offcore_response.other.l4_hit_local_l4.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200408000 00 offcore_response.other.l4_hit_local_l4.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80408000 00 offcore_response.other.l4_hit_local_l4.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x100408000 00 offcore_response.other.l4_hit_local_l4.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x40408000 00 offcore_response.other.supplier_none.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0028000 00 offcore_response.other.supplier_none.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x40028000 00 offcore_response.demand_code_rd.l3_hit.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20001C0004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000080004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000040004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000100004 00 offcore_response.demand_code_rd.l3_miss.any_snoop memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFC400004 00 offcore_response.demand_code_rd.l3_miss.snoop_hitm memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x103C400004 00 offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C400004 00 offcore_response.demand_code_rd.l3_miss.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C400004 00 offcore_response.demand_code_rd.l3_miss.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC400004 00 offcore_response.demand_code_rd.l3_miss.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x203C400004 00 offcore_response.demand_code_rd.l3_miss.snoop_not_needed memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C400004 00 offcore_response.demand_code_rd.l3_miss.spl_hit memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x7C400004 00 offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC4000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.spl_hit memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x44000004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000400004 00 offcore_response.demand_data_rd.l3_hit.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20001C0001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000080001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000040001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000100001 00 offcore_response.demand_data_rd.l3_miss.any_snoop memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFC400001 00 offcore_response.demand_data_rd.l3_miss.snoop_hitm memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x103C400001 00 offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwd memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C400001 00 offcore_response.demand_data_rd.l3_miss.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C400001 00 offcore_response.demand_data_rd.l3_miss.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC400001 00 offcore_response.demand_data_rd.l3_miss.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x203C400001 00 offcore_response.demand_data_rd.l3_miss.snoop_not_needed memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C400001 00 offcore_response.demand_data_rd.l3_miss.spl_hit memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x7C400001 00 offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC4000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.spl_hit memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x44000001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000400001 00 offcore_response.demand_rfo.l3_hit.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x20001C0002 00 offcore_response.demand_rfo.l3_hit_e.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000080002 00 offcore_response.demand_rfo.l3_hit_m.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000040002 00 offcore_response.demand_rfo.l3_hit_s.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000100002 00 offcore_response.demand_rfo.l3_miss.any_snoop memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFC400002 00 offcore_response.demand_rfo.l3_miss.snoop_hitm memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x103C400002 00 offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwd memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x43C400002 00 offcore_response.demand_rfo.l3_miss.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x23C400002 00 offcore_response.demand_rfo.l3_miss.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0xBC400002 00 offcore_response.demand_rfo.l3_miss.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x203C400002 00 offcore_response.demand_rfo.l3_miss.snoop_not_needed memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x13C400002 00 offcore_response.demand_rfo.l3_miss.spl_hit memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x7C400002 00 offcore_response.demand_rfo.l3_miss_local_dram.any_snoop memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC4000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_hitm memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x404000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x204000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x84000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x104000002 00 offcore_response.demand_rfo.l3_miss_local_dram.spl_hit memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x44000002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000400002 00 offcore_response.demand_rfo.supplier_none.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020002 00 offcore_response.other.l3_hit.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x20001C8000 00 offcore_response.other.l3_hit_e.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2000088000 00 offcore_response.other.l3_hit_m.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2000048000 00 offcore_response.other.l3_hit_s.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2000108000 00 offcore_response.other.l3_miss.any_snoop memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFC408000 00 offcore_response.other.l3_miss.snoop_hitm memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x103C408000 00 offcore_response.other.l3_miss.snoop_hit_no_fwd memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x43C408000 00 offcore_response.other.l3_miss.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x23C408000 00 offcore_response.other.l3_miss.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0xBC408000 00 offcore_response.other.l3_miss.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x203C408000 00 offcore_response.other.l3_miss.snoop_not_needed memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x13C408000 00 offcore_response.other.l3_miss.spl_hit memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x7C408000 00 offcore_response.other.l3_miss_local_dram.any_snoop memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC4008000 00 offcore_response.other.l3_miss_local_dram.spl_hit memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x44008000 00 offcore_response.other.l4_hit_local_l4.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2000408000 00 memory_disambiguation.history_reset other MEMORY_DISAMBIGUATION.HISTORY_RESET event=9,period=2000003,umask=1 00 unc_arb_trk_occupancy.all uncore interconnect Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic event=0x80,umask=1 01 unc_arb_trk_occupancy.data_read uncore interconnect Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk event=0x80,umask=2 01 unc_arb_trk_requests.all uncore interconnect UNC_ARB_TRK_REQUESTS.ALL event=0x81,umask=1 01 unc_arb_trk_requests.data_read uncore interconnect Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent event=0x81,umask=2 01 unc_arb_trk_requests.drd_direct uncore interconnect Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent event=0x81,umask=2 01 offcore_response.all_data_rd.any_response cache Counts all demand & prefetch data reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10491 00 offcore_response.all_data_rd.l3_hit.any_snoop cache Counts all demand & prefetch data reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0491 00 offcore_response.all_data_rd.l3_hit.hitm_other_core cache Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0491 00 offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0491 00 offcore_response.all_data_rd.l3_hit.no_snoop_needed cache Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0491 00 offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0491 00 offcore_response.all_pf_data_rd.any_response cache Counts all prefetch data reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10490 00 offcore_response.all_pf_data_rd.l3_hit.any_snoop cache Counts all prefetch data reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0490 00 offcore_response.all_pf_data_rd.l3_hit.hitm_other_core cache Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0490 00 offcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0490 00 offcore_response.all_pf_data_rd.l3_hit.no_snoop_needed cache Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0490 00 offcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0490 00 offcore_response.all_pf_rfo.any_response cache Counts prefetch RFOs that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10120 00 offcore_response.all_pf_rfo.l3_hit.any_snoop cache Counts prefetch RFOs that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0120 00 offcore_response.all_pf_rfo.l3_hit.hitm_other_core cache Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0120 00 offcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwd cache Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0120 00 offcore_response.all_pf_rfo.l3_hit.no_snoop_needed cache Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0120 00 offcore_response.all_reads.l3_hit.hit_other_core_fwd cache OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD hit in the L3 and the snoop to one of the sibling cores hits the line in E/S/F state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C07F7 00 offcore_response.all_rfo.any_response cache Counts all demand & prefetch RFOs that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10122 00 offcore_response.all_rfo.l3_hit.any_snoop cache Counts all demand & prefetch RFOs that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0122 00 offcore_response.all_rfo.l3_hit.hitm_other_core cache Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122 00 offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122 00 offcore_response.all_rfo.l3_hit.no_snoop_needed cache Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0122 00 offcore_response.all_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0122 00 offcore_response.demand_code_rd.any_response cache Counts all demand code reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10004 00 offcore_response.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004 00 offcore_response.demand_code_rd.l3_hit.hitm_other_core cache Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004 00 offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004 00 offcore_response.demand_code_rd.l3_hit.no_snoop_needed cache Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0004 00 offcore_response.demand_data_rd.any_response cache Counts demand data reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10001 00 offcore_response.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001 00 offcore_response.demand_data_rd.l3_hit.hitm_other_core cache Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001 00 offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd cache Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001 00 offcore_response.demand_data_rd.l3_hit.no_snoop_needed cache Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001 00 offcore_response.demand_rfo.any_response cache Counts all demand data writes (RFOs) that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10002 00 offcore_response.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002 00 offcore_response.demand_rfo.l3_hit.hitm_other_core cache Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002 00 offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002 00 offcore_response.demand_rfo.l3_hit.no_snoop_needed cache Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002 00 offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0002 00 offcore_response.pf_l1d_and_sw.any_response cache Counts L1 data cache hardware prefetch requests and software prefetch requests that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10400 00 offcore_response.pf_l1d_and_sw.l3_hit.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0400 00 offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0400 00 offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0400 00 offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0400 00 offcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0400 00 offcore_response.pf_l2_data_rd.any_response cache Counts prefetch (that bring data to L2) data reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10010 00 offcore_response.pf_l2_data_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to L2) data reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010 00 offcore_response.pf_l2_data_rd.l3_hit.hitm_other_core cache Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0010 00 offcore_response.pf_l2_rfo.any_response cache Counts all prefetch (that bring data to L2) RFOs that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10020 00 offcore_response.pf_l2_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020 00 offcore_response.pf_l2_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020 00 offcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020 00 offcore_response.pf_l2_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0020 00 offcore_response.pf_l3_data_rd.any_response cache Counts all prefetch (that bring data to LLC only) data reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10080 00 offcore_response.pf_l3_data_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080 00 offcore_response.pf_l3_data_rd.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0080 00 offcore_response.pf_l3_rfo.any_response cache Counts all prefetch (that bring data to LLC only) RFOs that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10100 00 offcore_response.pf_l3_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100 00 offcore_response.pf_l3_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0100 00 offcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0100 00 offcore_response.pf_l3_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0100 00 fp_arith_inst_retired.512b_packed_double floating point Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x40 00 Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_single floating point Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x80 00 Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events offcore_response.all_data_rd.l3_miss.any_snoop memory Counts all demand & prefetch data reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000491 00 offcore_response.all_data_rd.l3_miss.remote_hitm memory Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00491 00 offcore_response.all_data_rd.l3_miss.remote_hit_forward memory Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00491 00 offcore_response.all_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00491 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000491 00 offcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800491 00 offcore_response.all_pf_data_rd.l3_miss.any_snoop memory Counts all prefetch data reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000490 00 offcore_response.all_pf_data_rd.l3_miss.remote_hitm memory Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00490 00 offcore_response.all_pf_data_rd.l3_miss.remote_hit_forward memory Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00490 00 offcore_response.all_pf_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00490 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000490 00 offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800490 00 offcore_response.all_pf_rfo.l3_miss.any_snoop memory Counts prefetch RFOs that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000120 00 offcore_response.all_pf_rfo.l3_miss.remote_hitm memory Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00120 00 offcore_response.all_pf_rfo.l3_miss.remote_hit_forward memory Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00120 00 offcore_response.all_pf_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts prefetch RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000120 00 offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts prefetch RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800120 00 offcore_response.all_rfo.l3_miss.any_snoop memory Counts all demand & prefetch RFOs that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000122 00 offcore_response.all_rfo.l3_miss.remote_hitm memory Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00122 00 offcore_response.all_rfo.l3_miss.remote_hit_forward memory Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00122 00 offcore_response.all_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000122 00 offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800122 00 offcore_response.demand_code_rd.l3_miss.any_snoop memory Counts all demand code reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000004 00 offcore_response.demand_code_rd.l3_miss.remote_hitm memory Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00004 00 offcore_response.demand_code_rd.l3_miss.remote_hit_forward memory Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00004 00 offcore_response.demand_code_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all demand code reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand code reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000004 00 offcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand code reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800004 00 offcore_response.demand_data_rd.l3_miss.any_snoop memory Counts demand data reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000001 00 offcore_response.demand_data_rd.l3_miss.remote_hitm memory Counts demand data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00001 00 offcore_response.demand_data_rd.l3_miss.remote_hit_forward memory Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00001 00 offcore_response.demand_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts demand data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts demand data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000001 00 offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts demand data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800001 00 offcore_response.demand_rfo.l3_miss.any_snoop memory Counts all demand data writes (RFOs) that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000002 00 offcore_response.demand_rfo.l3_miss.remote_hitm memory Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00002 00 offcore_response.demand_rfo.l3_miss.remote_hit_forward memory Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00002 00 offcore_response.demand_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000002 00 offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800002 00 offcore_response.pf_l1d_and_sw.l3_miss.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000400 00 offcore_response.pf_l1d_and_sw.l3_miss.remote_hitm memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00400 00 offcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forward memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00400 00 offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00400 00 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000400 00 offcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800400 00 offcore_response.pf_l2_data_rd.l3_miss.any_snoop memory Counts prefetch (that bring data to L2) data reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000010 00 offcore_response.pf_l2_data_rd.l3_miss.remote_hitm memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00010 00 offcore_response.pf_l2_data_rd.l3_miss.remote_hit_forward memory Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00010 00 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000010 00 offcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800010 00 offcore_response.pf_l2_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to L2) RFOs that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000020 00 offcore_response.pf_l2_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00020 00 offcore_response.pf_l2_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00020 00 offcore_response.pf_l2_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000020 00 offcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800020 00 offcore_response.pf_l3_data_rd.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000080 00 offcore_response.pf_l3_data_rd.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00080 00 offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00080 00 offcore_response.pf_l3_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000080 00 offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800080 00 offcore_response.pf_l3_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000100 00 offcore_response.pf_l3_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00100 00 offcore_response.pf_l3_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00100 00 offcore_response.pf_l3_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000100 00 offcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800100 00 unc_cha_clockticks uncore cache Clockticks of the uncore caching & home agent (CHA) event=0 01 Counts clockticks of the clock controlling the uncore caching and home agent (CHA) unc_upi_rxl_crc_errors uncore interconnect CRC Errors Detected event=0xb 01 Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_upi_rxl_crc_llr_req_transmit uncore interconnect LLR Requests Sent event=8 01 Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs unc_m_power_channel_ppd uncore memory Cycles where DRAM ranks are in power down (CKE) mode event=0x85 01 Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of unc_cha_clockticks uncore cache Uncore cache clock ticks event=0 01 unc_cha_llc_lookup.code uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ event=0x34,umask=0x1bd0ff 11 unc_cha_llc_lookup.dmnd_read_local uncore cache This event is deprecated event=0x34,umask=0x841ff 11 unc_cha_llc_lookup.rfo_pref_local uncore cache This event is deprecated event=0x34,umask=0x888ff 11 unc_cha_llc_lookup.write_local uncore cache This event is deprecated event=0x34,umask=0x842ff 11 unc_m2m_prefcam_demand_merge.ch0_xpt uncore interconnect Demands Merged with CAMed Prefetches : XPT - Ch 0 event=0x74,umask=1 01 unc_m2m_prefcam_demand_merge.ch1_xpt uncore interconnect Demands Merged with CAMed Prefetches : XPT - Ch 1 event=0x74,umask=4 01 unc_m2m_prefcam_demand_merge.xpt_allch uncore interconnect Demands Merged with CAMed Prefetches : XPT - All Channels event=0x74,umask=0x15 01 unc_m2m_prefcam_demand_no_merge.ch0_xpt uncore interconnect Demands Not Merged with CAMed Prefetches : XPT - Ch 0 event=0x75,umask=1 01 unc_m2m_prefcam_demand_no_merge.ch1_xpt uncore interconnect Demands Not Merged with CAMed Prefetches : XPT - Ch 1 event=0x75,umask=4 01 unc_m2m_prefcam_demand_no_merge.xpt_allch uncore interconnect Demands Not Merged with CAMed Prefetches : XPT - All Channels event=0x75,umask=0x15 01 llc_misses.pcie_read uncore io PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 event=0x83,ch_mask=1,fc_mask=7,umask=4,ch_mask=0x1f 014Bytes Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 llc_misses.pcie_write uncore io PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 event=0x83,ch_mask=1,fc_mask=7,umask=1,ch_mask=0x1f 014Bytes Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_clockticks uncore io Clockticks of the integrated IO (IIO) traffic controller event=1 01 unc_iio_data_req_of_cpu.mem_read.part0 uncore io PCI Express bandwidth reading at IIO, part 0 event=0x83,ch_mask=1,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part1 uncore io PCI Express bandwidth reading at IIO, part 1 event=0x83,ch_mask=2,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part2 uncore io PCI Express bandwidth reading at IIO, part 2 event=0x83,ch_mask=4,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_read.part3 uncore io PCI Express bandwidth reading at IIO, part 3 event=0x83,ch_mask=8,fc_mask=7,umask=4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.part0 uncore io PCI Express bandwidth writing at IIO, part 0 event=0x83,ch_mask=1,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part1 uncore io PCI Express bandwidth writing at IIO, part 1 event=0x83,ch_mask=2,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part2 uncore io PCI Express bandwidth writing at IIO, part 2 event=0x83,ch_mask=4,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_write.part3 uncore io PCI Express bandwidth writing at IIO, part 3 event=0x83,ch_mask=8,fc_mask=7,umask=1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_m2p_clockticks uncore io Clockticks of the mesh to PCI (M2P) event=1 01 llc_misses.mem_read uncore memory read requests to memory controller. Derived from unc_m_cas_count.rd event=4,umask=0xf 0164Bytes Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills llc_misses.mem_write uncore memory write requests to memory controller. Derived from unc_m_cas_count.wr event=4,umask=0x30 0164Bytes Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel unc_m_clockticks uncore memory Memory controller clock ticks event=0 01 Clockticks of the integrated memory controller (IMC) unc_m_power_channel_ppd uncore memory Cycles where DRAM ranks are in power down (CKE) mode event=0x85 01 Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of unc_m_power_self_refresh uncore memory Cycles Memory is in self refresh power mode event=0x43 01 Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_pre_count.page_miss uncore memory Pre-charges due to page misses event=2,umask=0xc 01 DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests) unc_m_pre_count.rd uncore memory Pre-charge for reads event=2,umask=4 01 DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_m_pre_count.wr uncore memory Pre-charge for writes event=2,umask=8 01 DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_p_clockticks uncore power Clockticks of the power control unit (PCU) event=0 01 l2_rqsts.miss cache Read requests with true-miss in L2 cache event=0x24,period=200003,umask=0x3f 00 Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses l2_rqsts.references cache All accesses to L2 cache event=0x24,period=200003,umask=0xff 00 Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses mem_load_l3_hit_retired.xsnp_fwd cache Snoop hit a modified(HITM) or clean line(HIT_W_FWD) in another on-pkg core which forwarded the data back due to a retired load instruction Supports address when precise (Precise event) event=0xd2,period=20011,umask=4 00 Counts retired load instructions where a cross-core snoop hit in another cores caches on this socket, the data was forwarded back to the requesting core as the data was modified (SNOOP_HITM) or the L3 did not have the data(SNOOP_HIT_WITH_FWD) Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_no_fwd cache Snoop hit without forwarding in another on-pkg core due to a retired load instruction, data was supplied by the L3 Supports address when precise (Precise event) event=0xd2,period=20011,umask=2 00 Counts retired load instructions in which the L3 supplied the data and a cross-core snoop hit in another cores caches on this socket but that other core did not forward the data back (SNOOP_HIT_NO_FWD) Supports address when precise (Precise event) mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or lock Supports address when precise (Precise event) event=0xd4,period=100007,umask=4 00 Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access Supports address when precise (Precise event) ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001 00 offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=1000003,umask=8 00 Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=1000003,umask=8 00 Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=1000003,umask=4 00 Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_data_rd cache Demand Data Read transactions pending for off-core. Highly correlated event=0x60,period=1000003,umask=1 00 Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core sq_misc.sq_full cache Cycles the superQ cannot take any more entries event=0xf4,period=100003,umask=4 00 Counts the cycles for which the thread is active and the superQ cannot take any more entries exe_activity.bound_on_loads pipeline Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle event=0xa6,cmask=5,period=2000003,umask=0x21 00 Counts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=7,period=100003,umask=1 00 Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address uops_issued.vector_width_mismatch pipeline Uops inserted at issue-stage in order to preserve upper bits of vector registers event=0xe,period=100003,umask=2 00 Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide unc_arb_coh_trk_requests.all uncore interconnect UNC_ARB_COH_TRK_REQUESTS.ALL event=0x84,umask=1 01 unc_arb_trk_occupancy.all uncore interconnect Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic event=0x80,umask=1 01 unc_mc0_rdcas_count_freerun uncore memory Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x20 01 unc_mc0_total_reqcount_freerun uncore memory Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x10 01 unc_mc0_wrcas_count_freerun uncore memory Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x30 01 unc_mc1_rdcas_count_freerun uncore memory Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x20 01 unc_mc1_total_reqcount_freerun uncore memory Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x10 01 unc_mc1_wrcas_count_freerun uncore memory Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x30 01 dtlb_store_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data store to a 2M/4M page event=0x49,period=100003,umask=4 00 Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault dtlb_store_misses.walk_completed_4k virtual memory Page walks completed due to a demand data store to a 4K page event=0x49,period=100003,umask=2 00 Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault offcore_requests.any cache All offcore requests event=0xb0,period=100000,umask=0x80 00 offcore_requests.any.read cache Offcore read requests event=0xb0,period=100000,umask=8 00 offcore_requests.any.rfo cache Offcore RFO requests event=0xb0,period=100000,umask=0x10 00 offcore_requests.demand.read_code cache Offcore demand code read requests event=0xb0,period=100000,umask=2 00 offcore_requests.demand.read_data cache Offcore demand data read requests event=0xb0,period=100000,umask=1 00 offcore_requests.demand.rfo cache Offcore demand RFO requests event=0xb0,period=100000,umask=4 00 offcore_requests_outstanding.any.read cache Outstanding offcore reads event=0x60,period=2000000,umask=8 00 offcore_requests_outstanding.any.read_not_empty cache Cycles offcore reads busy event=0x60,cmask=1,period=2000000,umask=8 00 offcore_requests_outstanding.demand.read_code cache Outstanding offcore demand code reads event=0x60,period=2000000,umask=2 00 offcore_requests_outstanding.demand.read_code_not_empty cache Cycles offcore demand code read busy event=0x60,cmask=1,period=2000000,umask=2 00 offcore_requests_outstanding.demand.read_data cache Outstanding offcore demand data reads event=0x60,period=2000000,umask=1 00 offcore_requests_outstanding.demand.read_data_not_empty cache Cycles offcore demand data read busy event=0x60,cmask=1,period=2000000,umask=1 00 offcore_requests_outstanding.demand.rfo cache Outstanding offcore demand RFOs event=0x60,period=2000000,umask=4 00 offcore_requests_outstanding.demand.rfo_not_empty cache Cycles offcore demand RFOs busy event=0x60,cmask=1,period=2000000,umask=4 00 offcore_response.any_data.all_local_dram_and_remote_cache_hit cache REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5011 00 offcore_response.any_data.any_cache_dram cache REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f11 00 offcore_response.any_data.any_location cache REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff11 00 offcore_response.any_data.io_csr_mmio cache REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8011 00 offcore_response.any_data.llc_hit_no_other_core cache REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x111 00 offcore_response.any_data.llc_hit_other_core_hit cache REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x211 00 offcore_response.any_data.llc_hit_other_core_hitm cache REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x411 00 offcore_response.any_data.local_cache cache REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x711 00 offcore_response.any_data.local_dram_and_remote_cache_hit cache REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1011 00 offcore_response.any_data.remote_cache_hitm cache REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x811 00 offcore_response.any_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5044 00 offcore_response.any_ifetch.any_cache_dram cache REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f44 00 offcore_response.any_ifetch.any_location cache REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff44 00 offcore_response.any_ifetch.io_csr_mmio cache REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8044 00 offcore_response.any_ifetch.llc_hit_no_other_core cache REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x144 00 offcore_response.any_ifetch.llc_hit_other_core_hit cache REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x244 00 offcore_response.any_ifetch.llc_hit_other_core_hitm cache REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x444 00 offcore_response.any_ifetch.local_cache cache REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x744 00 offcore_response.any_ifetch.local_dram_and_remote_cache_hit cache REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1044 00 offcore_response.any_ifetch.remote_cache_hitm cache REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x844 00 offcore_response.any_request.all_local_dram_and_remote_cache_hit cache REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x50ff 00 offcore_response.any_request.any_cache_dram cache REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7fff 00 offcore_response.any_request.any_location cache REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xffff 00 offcore_response.any_request.io_csr_mmio cache REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x80ff 00 offcore_response.any_request.llc_hit_no_other_core cache REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x1ff 00 offcore_response.any_request.llc_hit_other_core_hit cache REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x2ff 00 offcore_response.any_request.llc_hit_other_core_hitm cache REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x4ff 00 offcore_response.any_request.local_cache cache REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x7ff 00 offcore_response.any_request.local_dram_and_remote_cache_hit cache REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x10ff 00 offcore_response.any_request.remote_cache_hitm cache REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x8ff 00 offcore_response.any_rfo.all_local_dram_and_remote_cache_hit cache REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5022 00 offcore_response.any_rfo.any_cache_dram cache REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f22 00 offcore_response.any_rfo.any_location cache REQUEST = ANY RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff22 00 offcore_response.any_rfo.io_csr_mmio cache REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8022 00 offcore_response.any_rfo.llc_hit_no_other_core cache REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x122 00 offcore_response.any_rfo.llc_hit_other_core_hit cache REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x222 00 offcore_response.any_rfo.llc_hit_other_core_hitm cache REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x422 00 offcore_response.any_rfo.local_cache cache REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x722 00 offcore_response.any_rfo.local_dram_and_remote_cache_hit cache REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1022 00 offcore_response.any_rfo.remote_cache_hitm cache REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x822 00 offcore_response.corewb.all_local_dram_and_remote_cache_hit cache REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5008 00 offcore_response.corewb.any_cache_dram cache REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f08 00 offcore_response.corewb.any_location cache REQUEST = CORE_WB and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff08 00 offcore_response.corewb.io_csr_mmio cache REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8008 00 offcore_response.corewb.llc_hit_no_other_core cache REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x108 00 offcore_response.corewb.llc_hit_other_core_hit cache REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x208 00 offcore_response.corewb.llc_hit_other_core_hitm cache REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x408 00 offcore_response.corewb.local_cache cache REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x708 00 offcore_response.corewb.local_dram_and_remote_cache_hit cache REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1008 00 offcore_response.corewb.remote_cache_hitm cache REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x808 00 offcore_response.data_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5077 00 offcore_response.data_ifetch.any_cache_dram cache REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f77 00 offcore_response.data_ifetch.any_location cache REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff77 00 offcore_response.data_ifetch.io_csr_mmio cache REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8077 00 offcore_response.data_ifetch.llc_hit_no_other_core cache REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x177 00 offcore_response.data_ifetch.llc_hit_other_core_hit cache REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x277 00 offcore_response.data_ifetch.llc_hit_other_core_hitm cache REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x477 00 offcore_response.data_ifetch.local_cache cache REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x777 00 offcore_response.data_ifetch.local_dram_and_remote_cache_hit cache REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1077 00 offcore_response.data_ifetch.remote_cache_hitm cache REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x877 00 offcore_response.data_in.all_local_dram_and_remote_cache_hit cache REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5033 00 offcore_response.data_in.any_cache_dram cache REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f33 00 offcore_response.data_in.any_location cache REQUEST = DATA_IN and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff33 00 offcore_response.data_in.io_csr_mmio cache REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8033 00 offcore_response.data_in.llc_hit_no_other_core cache REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x133 00 offcore_response.data_in.llc_hit_other_core_hit cache REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x233 00 offcore_response.data_in.llc_hit_other_core_hitm cache REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x433 00 offcore_response.data_in.local_cache cache REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x733 00 offcore_response.data_in.local_dram_and_remote_cache_hit cache REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1033 00 offcore_response.data_in.remote_cache_hitm cache REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x833 00 offcore_response.demand_data.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5003 00 offcore_response.demand_data.any_cache_dram cache REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f03 00 offcore_response.demand_data.any_location cache REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff03 00 offcore_response.demand_data.io_csr_mmio cache REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8003 00 offcore_response.demand_data.llc_hit_no_other_core cache REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x103 00 offcore_response.demand_data.llc_hit_other_core_hit cache REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x203 00 offcore_response.demand_data.llc_hit_other_core_hitm cache REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x403 00 offcore_response.demand_data.local_cache cache REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x703 00 offcore_response.demand_data.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1003 00 offcore_response.demand_data.remote_cache_hitm cache REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x803 00 offcore_response.demand_data_rd.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5001 00 offcore_response.demand_data_rd.any_cache_dram cache REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f01 00 offcore_response.demand_data_rd.any_location cache REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff01 00 offcore_response.demand_data_rd.io_csr_mmio cache REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8001 00 offcore_response.demand_data_rd.llc_hit_no_other_core cache REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x101 00 offcore_response.demand_data_rd.llc_hit_other_core_hit cache REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x201 00 offcore_response.demand_data_rd.llc_hit_other_core_hitm cache REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x401 00 offcore_response.demand_data_rd.local_cache cache REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x701 00 offcore_response.demand_data_rd.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1001 00 offcore_response.demand_data_rd.remote_cache_hitm cache REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x801 00 offcore_response.demand_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5004 00 offcore_response.demand_ifetch.any_cache_dram cache REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f04 00 offcore_response.demand_ifetch.any_location cache REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff04 00 offcore_response.demand_ifetch.io_csr_mmio cache REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8004 00 offcore_response.demand_ifetch.llc_hit_no_other_core cache REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x104 00 offcore_response.demand_ifetch.llc_hit_other_core_hit cache REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x204 00 offcore_response.demand_ifetch.llc_hit_other_core_hitm cache REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x404 00 offcore_response.demand_ifetch.local_cache cache REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x704 00 offcore_response.demand_ifetch.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1004 00 offcore_response.demand_ifetch.remote_cache_hitm cache REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x804 00 offcore_response.demand_rfo.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5002 00 offcore_response.demand_rfo.any_cache_dram cache REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f02 00 offcore_response.demand_rfo.any_location cache REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff02 00 offcore_response.demand_rfo.io_csr_mmio cache REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8002 00 offcore_response.demand_rfo.llc_hit_no_other_core cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x102 00 offcore_response.demand_rfo.llc_hit_other_core_hit cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x202 00 offcore_response.demand_rfo.llc_hit_other_core_hitm cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x402 00 offcore_response.demand_rfo.local_cache cache REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x702 00 offcore_response.demand_rfo.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1002 00 offcore_response.demand_rfo.remote_cache_hitm cache REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x802 00 offcore_response.other.all_local_dram_and_remote_cache_hit cache REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5080 00 offcore_response.other.any_cache_dram cache REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f80 00 offcore_response.other.any_location cache REQUEST = OTHER and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff80 00 offcore_response.other.io_csr_mmio cache REQUEST = OTHER and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8080 00 offcore_response.other.llc_hit_no_other_core cache REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x180 00 offcore_response.other.llc_hit_other_core_hit cache REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x280 00 offcore_response.other.llc_hit_other_core_hitm cache REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x480 00 offcore_response.other.local_cache cache REQUEST = OTHER and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x780 00 offcore_response.other.local_dram_and_remote_cache_hit cache REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1080 00 offcore_response.other.remote_cache_hitm cache REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x880 00 offcore_response.pf_data.all_local_dram_and_remote_cache_hit cache REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5050 00 offcore_response.pf_data.any_cache_dram cache REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f50 00 offcore_response.pf_data.any_location cache REQUEST = PF_DATA and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff50 00 offcore_response.pf_data.io_csr_mmio cache REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8050 00 offcore_response.pf_data.llc_hit_no_other_core cache REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x150 00 offcore_response.pf_data.llc_hit_other_core_hit cache REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x250 00 offcore_response.pf_data.llc_hit_other_core_hitm cache REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x450 00 offcore_response.pf_data.local_cache cache REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x750 00 offcore_response.pf_data.local_dram_and_remote_cache_hit cache REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1050 00 offcore_response.pf_data.remote_cache_hitm cache REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x850 00 offcore_response.pf_data_rd.all_local_dram_and_remote_cache_hit cache REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5010 00 offcore_response.pf_data_rd.any_cache_dram cache REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f10 00 offcore_response.pf_data_rd.any_location cache REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff10 00 offcore_response.pf_data_rd.io_csr_mmio cache REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8010 00 offcore_response.pf_data_rd.llc_hit_no_other_core cache REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x110 00 offcore_response.pf_data_rd.llc_hit_other_core_hit cache REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x210 00 offcore_response.pf_data_rd.llc_hit_other_core_hitm cache REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x410 00 offcore_response.pf_data_rd.local_cache cache REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x710 00 offcore_response.pf_data_rd.local_dram_and_remote_cache_hit cache REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1010 00 offcore_response.pf_data_rd.remote_cache_hitm cache REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x810 00 offcore_response.pf_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5040 00 offcore_response.pf_ifetch.any_cache_dram cache REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f40 00 offcore_response.pf_ifetch.any_location cache REQUEST = PF_RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff40 00 offcore_response.pf_ifetch.io_csr_mmio cache REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8040 00 offcore_response.pf_ifetch.llc_hit_no_other_core cache REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x140 00 offcore_response.pf_ifetch.llc_hit_other_core_hit cache REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x240 00 offcore_response.pf_ifetch.llc_hit_other_core_hitm cache REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x440 00 offcore_response.pf_ifetch.local_cache cache REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x740 00 offcore_response.pf_ifetch.local_dram_and_remote_cache_hit cache REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1040 00 offcore_response.pf_ifetch.remote_cache_hitm cache REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x840 00 offcore_response.pf_rfo.all_local_dram_and_remote_cache_hit cache REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5020 00 offcore_response.pf_rfo.any_cache_dram cache REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f20 00 offcore_response.pf_rfo.any_location cache REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff20 00 offcore_response.pf_rfo.io_csr_mmio cache REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8020 00 offcore_response.pf_rfo.llc_hit_no_other_core cache REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x120 00 offcore_response.pf_rfo.llc_hit_other_core_hit cache REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x220 00 offcore_response.pf_rfo.llc_hit_other_core_hitm cache REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x420 00 offcore_response.pf_rfo.local_cache cache REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x720 00 offcore_response.pf_rfo.local_dram_and_remote_cache_hit cache REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1020 00 offcore_response.pf_rfo.remote_cache_hitm cache REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x820 00 offcore_response.prefetch.all_local_dram_and_remote_cache_hit cache REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5070 00 offcore_response.prefetch.any_cache_dram cache REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f70 00 offcore_response.prefetch.any_location cache REQUEST = PREFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff70 00 offcore_response.prefetch.io_csr_mmio cache REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8070 00 offcore_response.prefetch.llc_hit_no_other_core cache REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x170 00 offcore_response.prefetch.llc_hit_other_core_hit cache REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x270 00 offcore_response.prefetch.llc_hit_other_core_hitm cache REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x470 00 offcore_response.prefetch.local_cache cache REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x770 00 offcore_response.prefetch.local_dram_and_remote_cache_hit cache REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1070 00 offcore_response.prefetch.remote_cache_hitm cache REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x870 00 sq_misc.lru_hints cache Super Queue LRU hints sent to LLC event=0xf4,period=2000000,umask=4 00 misalign_mem_ref.store memory Misaligned store references event=5,period=200000,umask=2 00 offcore_response.any_data.any_dram_and_remote_fwd memory REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3011 00 offcore_response.any_data.any_llc_miss memory REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf811 00 offcore_response.any_data.other_local_dram memory REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4011 00 offcore_response.any_data.remote_dram memory REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2011 00 offcore_response.any_ifetch.any_dram_and_remote_fwd memory REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3044 00 offcore_response.any_ifetch.any_llc_miss memory REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf844 00 offcore_response.any_ifetch.other_local_dram memory REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4044 00 offcore_response.any_ifetch.remote_dram memory REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2044 00 offcore_response.any_request.any_dram_and_remote_fwd memory REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x30ff 00 offcore_response.any_request.any_llc_miss memory REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf8ff 00 offcore_response.any_request.other_local_dram memory REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x40ff 00 offcore_response.any_request.remote_dram memory REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x20ff 00 offcore_response.any_rfo.any_dram_and_remote_fwd memory REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3022 00 offcore_response.any_rfo.any_llc_miss memory REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf822 00 offcore_response.any_rfo.other_local_dram memory REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4022 00 offcore_response.any_rfo.remote_dram memory REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2022 00 offcore_response.corewb.any_dram_and_remote_fwd memory REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3008 00 offcore_response.corewb.any_llc_miss memory REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf808 00 offcore_response.corewb.other_local_dram memory REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4008 00 offcore_response.corewb.remote_dram memory REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2008 00 offcore_response.data_ifetch.any_dram_and_remote_fwd memory REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3077 00 offcore_response.data_ifetch.any_llc_miss memory REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf877 00 offcore_response.data_ifetch.other_local_dram memory REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4077 00 offcore_response.data_ifetch.remote_dram memory REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2077 00 offcore_response.data_in.any_dram_and_remote_fwd memory REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3033 00 offcore_response.data_in.any_llc_miss memory REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf833 00 offcore_response.data_in.other_local_dram memory REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4033 00 offcore_response.data_in.remote_dram memory REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2033 00 offcore_response.demand_data.any_dram_and_remote_fwd memory REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3003 00 offcore_response.demand_data.any_llc_miss memory REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf803 00 offcore_response.demand_data.other_local_dram memory REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4003 00 offcore_response.demand_data.remote_dram memory REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2003 00 offcore_response.demand_data_rd.any_dram_and_remote_fwd memory REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3001 00 offcore_response.demand_data_rd.any_llc_miss memory REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf801 00 offcore_response.demand_data_rd.other_local_dram memory REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4001 00 offcore_response.demand_data_rd.remote_dram memory REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2001 00 offcore_response.demand_ifetch.any_dram_and_remote_fwd memory REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3004 00 offcore_response.demand_ifetch.any_llc_miss memory REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf804 00 offcore_response.demand_ifetch.other_local_dram memory REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4004 00 offcore_response.demand_ifetch.remote_dram memory REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2004 00 offcore_response.demand_rfo.any_dram_and_remote_fwd memory REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3002 00 offcore_response.demand_rfo.any_llc_miss memory REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf802 00 offcore_response.demand_rfo.other_local_dram memory REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4002 00 offcore_response.demand_rfo.remote_dram memory REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2002 00 offcore_response.other.any_dram_and_remote_fwd memory REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3080 00 offcore_response.other.any_llc_miss memory REQUEST = OTHER and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf880 00 offcore_response.other.other_local_dram memory REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4080 00 offcore_response.other.remote_dram memory REQUEST = OTHER and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2080 00 offcore_response.pf_data.any_dram_and_remote_fwd memory REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3050 00 offcore_response.pf_data.any_llc_miss memory REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf850 00 offcore_response.pf_data.other_local_dram memory REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4050 00 offcore_response.pf_data.remote_dram memory REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2050 00 offcore_response.pf_data_rd.any_dram_and_remote_fwd memory REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3010 00 offcore_response.pf_data_rd.any_llc_miss memory REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf810 00 offcore_response.pf_data_rd.other_local_dram memory REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4010 00 offcore_response.pf_data_rd.remote_dram memory REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2010 00 offcore_response.pf_ifetch.any_dram_and_remote_fwd memory REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3040 00 offcore_response.pf_ifetch.any_llc_miss memory REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf840 00 offcore_response.pf_ifetch.other_local_dram memory REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4040 00 offcore_response.pf_ifetch.remote_dram memory REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2040 00 offcore_response.pf_rfo.any_dram_and_remote_fwd memory REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3020 00 offcore_response.pf_rfo.any_llc_miss memory REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf820 00 offcore_response.pf_rfo.other_local_dram memory REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4020 00 offcore_response.pf_rfo.remote_dram memory REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2020 00 offcore_response.prefetch.any_dram_and_remote_fwd memory REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3070 00 offcore_response.prefetch.any_llc_miss memory REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf870 00 offcore_response.prefetch.other_local_dram memory REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4070 00 offcore_response.prefetch.remote_dram memory REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2070 00 load_block.overlap_store other Loads that partially overlap an earlier store event=3,period=200000,umask=2 00 snoopq_requests.code other Snoop code requests event=0xb4,period=100000,umask=4 00 snoopq_requests.data other Snoop data requests event=0xb4,period=100000,umask=1 00 snoopq_requests.invalidate other Snoop invalidate requests event=0xb4,period=100000,umask=2 00 snoopq_requests_outstanding.code other Outstanding snoop code requests event=0xb3,period=2000000,umask=4 00 snoopq_requests_outstanding.code_not_empty other Cycles snoop code requests queued event=0xb3,cmask=1,period=2000000,umask=4 00 snoopq_requests_outstanding.data other Outstanding snoop data requests event=0xb3,period=2000000,umask=1 00 snoopq_requests_outstanding.data_not_empty other Cycles snoop data requests queued event=0xb3,cmask=1,period=2000000,umask=1 00 snoopq_requests_outstanding.invalidate other Outstanding snoop invalidate requests event=0xb3,period=2000000,umask=2 00 snoopq_requests_outstanding.invalidate_not_empty other Cycles snoop invalidate requests queued event=0xb3,cmask=1,period=2000000,umask=2 00 br_misp_retired.all_branches pipeline Mispredicted retired branch instructions (Precise Event) event=0xc5,period=20000,umask=4 00 br_misp_retired.conditional pipeline Mispredicted conditional retired branches (Precise Event) event=0xc5,period=20000,umask=1 00 dtlb_load_misses.large_walk_completed virtual memory DTLB load miss large page walks event=8,period=200000,umask=0x80 00 dtlb_load_misses.walk_cycles virtual memory DTLB load miss page walk cycles event=8,period=200000,umask=4 00 dtlb_misses.large_walk_completed virtual memory DTLB miss large page walks event=0x49,period=200000,umask=0x80 00 dtlb_misses.pde_miss virtual memory DTLB misses caused by low part of address event=0x49,period=200000,umask=0x20 00 dtlb_misses.walk_cycles virtual memory DTLB miss page walk cycles event=0x49,period=2000000,umask=4 00 ept.walk_cycles virtual memory Extended Page Table walk cycles event=0x4f,period=2000000,umask=0x10 00 itlb_misses.large_walk_completed virtual memory ITLB miss large page walks event=0x85,period=200000,umask=0x80 00 itlb_misses.walk_cycles virtual memory ITLB miss page walk cycles event=0x85,period=2000000,umask=4 00 mem_uncore_retired.local_dram cache Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event) event=0xf,period=10000,umask=0x10 00 mem_uncore_retired.remote_dram cache Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) event=0xf,period=10000,umask=0x20 00 offcore_requests.uncached_mem cache Offcore uncached memory accesses event=0xb0,period=100000,umask=0x20 00 offcore_response.any_data.local_cache_dram cache Offcore data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2711 00 offcore_response.any_data.remote_cache_dram cache Offcore data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5811 00 offcore_response.any_ifetch.local_cache_dram cache Offcore code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2744 00 offcore_response.any_ifetch.remote_cache_dram cache Offcore code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5844 00 offcore_response.any_request.local_cache_dram cache Offcore requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x27FF 00 offcore_response.any_request.remote_cache_dram cache Offcore requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x58FF 00 offcore_response.any_rfo.local_cache_dram cache Offcore RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2722 00 offcore_response.any_rfo.remote_cache_dram cache Offcore RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5822 00 offcore_response.corewb.local_cache_dram cache Offcore writebacks to the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2708 00 offcore_response.corewb.remote_cache_dram cache Offcore writebacks to a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5808 00 offcore_response.data_ifetch.local_cache_dram cache Offcore code or data read requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2777 00 offcore_response.data_ifetch.remote_cache_dram cache Offcore code or data read requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5877 00 offcore_response.data_in.local_cache_dram cache Offcore request = all data, response = local cache or dram event=0xb7,period=100000,umask=1,offcore_rsp=0x2733 00 offcore_response.data_in.remote_cache_dram cache Offcore request = all data, response = remote cache or dram event=0xb7,period=100000,umask=1,offcore_rsp=0x5833 00 offcore_response.demand_data.local_cache_dram cache Offcore demand data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2703 00 offcore_response.demand_data.remote_cache_dram cache Offcore demand data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5803 00 offcore_response.demand_data_rd.local_cache_dram cache Offcore demand data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2701 00 offcore_response.demand_data_rd.remote_cache_dram cache Offcore demand data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5801 00 offcore_response.demand_ifetch.local_cache_dram cache Offcore demand code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2704 00 offcore_response.demand_ifetch.remote_cache_dram cache Offcore demand code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5804 00 offcore_response.demand_rfo.local_cache_dram cache Offcore demand RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2702 00 offcore_response.demand_rfo.remote_cache_dram cache Offcore demand RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5802 00 offcore_response.other.local_cache_dram cache Offcore other requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2780 00 offcore_response.other.remote_cache_dram cache Offcore other requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5880 00 offcore_response.pf_data.any_cache_dram cache Offcore prefetch data requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F50 00 offcore_response.pf_data.any_location cache All offcore prefetch data requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF50 00 offcore_response.pf_data.io_csr_mmio cache Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8050 00 offcore_response.pf_data.llc_hit_no_other_core cache Offcore prefetch data requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x150 00 offcore_response.pf_data.llc_hit_other_core_hit cache Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x250 00 offcore_response.pf_data.llc_hit_other_core_hitm cache Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x450 00 offcore_response.pf_data.local_cache cache Offcore prefetch data requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x750 00 offcore_response.pf_data.local_cache_dram cache Offcore prefetch data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2750 00 offcore_response.pf_data.remote_cache cache Offcore prefetch data requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1850 00 offcore_response.pf_data.remote_cache_dram cache Offcore prefetch data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5850 00 offcore_response.pf_data.remote_cache_hit cache Offcore prefetch data requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1050 00 offcore_response.pf_data.remote_cache_hitm cache Offcore prefetch data requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x850 00 offcore_response.pf_data_rd.local_cache_dram cache Offcore prefetch data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2710 00 offcore_response.pf_data_rd.remote_cache_dram cache Offcore prefetch data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5810 00 offcore_response.pf_ifetch.local_cache_dram cache Offcore prefetch code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2740 00 offcore_response.pf_ifetch.remote_cache_dram cache Offcore prefetch code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5840 00 offcore_response.pf_rfo.local_cache_dram cache Offcore prefetch RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2720 00 offcore_response.pf_rfo.remote_cache_dram cache Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5820 00 offcore_response.prefetch.local_cache_dram cache Offcore prefetch requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2770 00 offcore_response.prefetch.remote_cache_dram cache Offcore prefetch requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5870 00 offcore_response.any_data.local_dram memory Offcore data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2011 00 offcore_response.any_data.remote_dram memory Offcore data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4011 00 offcore_response.any_ifetch.local_dram memory Offcore code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2044 00 offcore_response.any_ifetch.remote_dram memory Offcore code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4044 00 offcore_response.any_request.local_dram memory Offcore requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x20FF 00 offcore_response.any_request.remote_dram memory Offcore requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x40FF 00 offcore_response.any_rfo.local_dram memory Offcore RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2022 00 offcore_response.any_rfo.remote_dram memory Offcore RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4022 00 offcore_response.corewb.local_dram memory Offcore writebacks to the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2008 00 offcore_response.corewb.remote_dram memory Offcore writebacks to a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4008 00 offcore_response.data_ifetch.local_dram memory Offcore code or data read requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2077 00 offcore_response.data_ifetch.remote_dram memory Offcore code or data read requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4077 00 offcore_response.data_in.local_dram memory Offcore data reads, RFOs, and prefetches satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2033 00 offcore_response.data_in.remote_dram memory Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4033 00 offcore_response.demand_data.local_dram memory Offcore demand data requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2003 00 offcore_response.demand_data.remote_dram memory Offcore demand data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4003 00 offcore_response.demand_data_rd.local_dram memory Offcore demand data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2001 00 offcore_response.demand_data_rd.remote_dram memory Offcore demand data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4001 00 offcore_response.demand_ifetch.local_dram memory Offcore demand code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2004 00 offcore_response.demand_ifetch.remote_dram memory Offcore demand code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4004 00 offcore_response.demand_rfo.local_dram memory Offcore demand RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2002 00 offcore_response.demand_rfo.remote_dram memory Offcore demand RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4002 00 offcore_response.other.remote_dram memory Offcore other requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4080 00 offcore_response.pf_data.any_dram memory Offcore prefetch data requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6050 00 offcore_response.pf_data.any_llc_miss memory Offcore prefetch data requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF850 00 offcore_response.pf_data.local_dram memory Offcore prefetch data requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2050 00 offcore_response.pf_data.remote_dram memory Offcore prefetch data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4050 00 offcore_response.pf_data_rd.local_dram memory Offcore prefetch data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2010 00 offcore_response.pf_data_rd.remote_dram memory Offcore prefetch data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4010 00 offcore_response.pf_ifetch.local_dram memory Offcore prefetch code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2040 00 offcore_response.pf_ifetch.remote_dram memory Offcore prefetch code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4040 00 offcore_response.pf_rfo.local_dram memory Offcore prefetch RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2020 00 offcore_response.pf_rfo.remote_dram memory Offcore prefetch RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4020 00 offcore_response.prefetch.local_dram memory Offcore prefetch requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2070 00 offcore_response.prefetch.remote_dram memory Offcore prefetch requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4070 00 mem_uncore_retired.local_dram_and_remote_cache_hit cache Load instructions retired local dram and remote cache HIT data sources (Precise Event) event=0xf,period=20000,umask=8 00 mem_uncore_retired.local_hitm cache Load instructions retired that HIT modified data in sibling core (Precise Event) event=0xf,period=40000,umask=2 00 mem_uncore_retired.remote_hitm cache Retired loads that hit remote socket in modified state (Precise Event) event=0xf,period=40000,umask=4 00 bpu_clears.early pipeline Early Branch Prediction Unit clears event=0xe8,period=2000000,umask=1 00 uops_executed.core_stall_count pipeline Uops executed on any port (core count) event=0xb1,cmask=1,edge=1,inv=1,period=2000000,umask=0x3f 00 uops_executed.core_stall_count_no_port5 pipeline Uops executed on ports 0-4 (core count) event=0xb1,cmask=1,edge=1,inv=1,period=2000000,umask=0x1f 00 dtlb_misses.pde_miss virtual memory DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE event=0x49,period=200000,umask=0x20 00 CPI 1 / IPC 00IPC group1 inst_retired.any / cpu_clk_unhalted.thread 00Frontend_Bound_SMT idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk))) 00dcache_miss_cpi l1d\-loads\-misses / inst_retired.any 00icache_miss_cycles l1i\-loads\-misses / inst_retired.any 00cache_miss_cycles group1 dcache_miss_cpi + icache_miss_cycles 00DCache_L2_All_Hits l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit 00DCache_L2_All_Miss max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss 00DCache_L2_All DCache_L2_All_Hits + DCache_L2_All_Miss 00DCache_L2_Hits d_ratio(DCache_L2_All_Hits, DCache_L2_All) 00DCache_L2_Misses d_ratio(DCache_L2_All_Miss, DCache_L2_All) 00M1 ipc + M2 00M2 ipc + M1 00M3 1 / M3 00L1D_Cache_Fill_BW 64 * l1d.replacement / 1e9 / duration_time 00C10_Pkg_Residency Power cstate_pkg@c10\-residency@ / TSC C10 residency percent per package 100% 00C1_Core_Residency Power cstate_core@c1\-residency@ / TSC C1 residency percent per core 100% 00C2_Pkg_Residency Power cstate_pkg@c2\-residency@ / TSC C2 residency percent per package 100% 00C3_Pkg_Residency Power cstate_pkg@c3\-residency@ / TSC C3 residency percent per package 100% 00C6_Core_Residency Power cstate_core@c6\-residency@ / TSC C6 residency percent per core 100% 00C6_Pkg_Residency Power cstate_pkg@c6\-residency@ / TSC C6 residency percent per package 100% 00C7_Core_Residency Power cstate_core@c7\-residency@ / TSC C7 residency percent per core 100% 00C7_Pkg_Residency Power cstate_pkg@c7\-residency@ / TSC C7 residency percent per package 100% 00C8_Pkg_Residency Power cstate_pkg@c8\-residency@ / TSC C8 residency percent per package 100% 00C9_Pkg_Residency Power cstate_pkg@c9\-residency@ / TSC C9 residency percent per package 100% 00smi_cycles smi ((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0) smi_cycles > 0.1 Percentage of cycles spent in System Management Interrupts 100% 00smi_num smi msr@smi@ Number of SMI interrupts 1SMI# 00tsx_aborted_cycles transaction (max(cycles\-t - cycles\-ct, 0) / cycles if has_event(cycles\-t) else 0) Percentage of cycles in aborted transactions 100% 00tsx_cycles_per_elision transaction (cycles\-t / el\-start if has_event(el\-start) else 0) Number of cycles within a transaction divided by the number of elisions 1cycles / elision 00tsx_cycles_per_transaction transaction (cycles\-t / tx\-start if has_event(cycles\-t) else 0) Number of cycles within a transaction divided by the number of transactions 1cycles / transaction 00tsx_transactional_cycles transaction (cycles\-t / cycles if has_event(cycles\-t) else 0) Percentage of cycles within a transaction region 100% 00cpu_atom tma_allocation_restriction TopdownL3;tma_L3_group;tma_core_bound_group tma_core_bound tma_allocation_restriction > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions 100% 00tma_backend_bound Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_BE_BOUND.ALL@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_backend_bound > 0.1 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count 100% TopdownL1;Default TopdownL1 00tma_bad_speculation Default;TopdownL1;tma_L1_group (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@ - (cpu_atom@TOPDOWN_FE_BOUND.ALL@ + cpu_atom@TOPDOWN_BE_BOUND.ALL@ + cpu_atom@TOPDOWN_RETIRING.ALL@)) / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear 100% TopdownL1;Default TopdownL1 00tma_branch_detect TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches 100% 00tma_branch_mispredicts TopdownL2;tma_L2_group;tma_bad_speculation_group cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15 Counts the number of issue slots that were not consumed by the backend due to branch mispredicts 100% TopdownL2 00tma_branch_resteer TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch 100% 00tma_cisc TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.CISC@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS) 100% 00tma_core_bound TopdownL2;tma_L2_group;tma_backend_bound_group cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_core_bound > 0.1 & tma_backend_bound > 0.1 Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation 100% TopdownL2 00tma_decode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to decode stalls 100% 00tma_fast_nuke TopdownL3;tma_L3_group;tma_machine_clears_group cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming 100% 00tma_frontend_bound Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_FE_BOUND.ALL@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_frontend_bound > 0.2 Counts the number of issue slots that were not consumed by the backend due to frontend stalls 100% TopdownL1;Default TopdownL1 00tma_icache_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses 100% 00tma_ifetch_bandwidth TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations 100% TopdownL2 00tma_ifetch_latency TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations 100% TopdownL2 00tma_info_bottleneck_%_dtlb_miss_bound_cycles 100 * (cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ + cpu_atom@LD_HEAD.PGWALK_AT_RET@) / cpu_atom@CPU_CLK_UNHALTED.CORE@ Percentage of time that retirement is stalled due to a first level data TLB miss 00tma_info_bottleneck_%_ifetch_miss_bound_cycles Ifetch 100 * cpu_atom@MEM_BOUND_STALLS.IFETCH@ / cpu_atom@CPU_CLK_UNHALTED.CORE@ Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound 00tma_info_bottleneck_%_load_miss_bound_cycles Load_Store_Miss 100 * cpu_atom@MEM_BOUND_STALLS.LOAD@ / cpu_atom@CPU_CLK_UNHALTED.CORE@ Percentage of time that retirement is stalled due to an L1 miss Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound 00tma_info_bottleneck_%_mem_exec_bound_cycles Mem_Exec 100 * cpu_atom@LD_HEAD.ANY_AT_RET@ / cpu_atom@CPU_CLK_UNHALTED.CORE@ Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound 00tma_info_br_inst_mix_ipbranch cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIRED.ALL_BRANCHES@ Instructions per Branch (lower number means higher occurrence rate) 00tma_info_br_inst_mix_ipcall cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIRED.CALL@ Instruction per (near) call (lower number means higher occurrence rate) 00tma_info_br_inst_mix_ipfarbranch cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIRED.FAR_BRANCH@u Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate] 00tma_info_br_inst_mix_ipmisp_cond_ntaken cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_MISP_RETIRED.COND@ - cpu_atom@BR_MISP_RETIRED.COND_TAKEN@) Instructions per retired conditional Branch Misprediction where the branch was not taken 00tma_info_br_inst_mix_ipmisp_cond_taken cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.COND_TAKEN@ Instructions per retired conditional Branch Misprediction where the branch was taken 00tma_info_br_inst_mix_ipmisp_indirect cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.INDIRECT@ Instructions per retired indirect call or jump Branch Misprediction 00tma_info_br_inst_mix_ipmisp_ret cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.RETURN@ Instructions per retired return Branch Misprediction 00tma_info_br_inst_mix_ipmispredict cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ Instructions per retired Branch Misprediction 00tma_info_br_mispredict_bound_branch_mispredict_ratio cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / cpu_atom@BR_INST_RETIRED.ALL_BRANCHES@ Ratio of all branches which mispredict 00tma_info_br_mispredict_bound_branch_mispredict_to_unknown_branch_ratio cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / cpu_atom@BACLEARS.ANY@ Ratio between Mispredicted branches and unknown branches 00tma_info_buffer_stalls_%_load_buffer_stall_cycles 100 * cpu_atom@MEM_SCHEDULER_BLOCK.LD_BUF@ / cpu_atom@CPU_CLK_UNHALTED.CORE@ Percentage of time that allocation is stalled due to load buffer full 00tma_info_buffer_stalls_%_mem_rsv_stall_cycles 100 * cpu_atom@MEM_SCHEDULER_BLOCK.RSV@ / cpu_atom@CPU_CLK_UNHALTED.CORE@ Percentage of time that allocation is stalled due to memory reservation stations full 00tma_info_buffer_stalls_%_store_buffer_stall_cycles 100 * cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_atom@CPU_CLK_UNHALTED.CORE@ Percentage of time that allocation is stalled due to store buffer full 00tma_info_core_cpi cpu_atom@CPU_CLK_UNHALTED.CORE@ / cpu_atom@INST_RETIRED.ANY@ Cycles Per Instruction 00tma_info_core_ipc cpu_atom@INST_RETIRED.ANY@ / cpu_atom@CPU_CLK_UNHALTED.CORE@ Instructions Per Cycle 00tma_info_core_upi cpu_atom@UOPS_RETIRED.ALL@ / cpu_atom@INST_RETIRED.ANY@ Uops Per Instruction 00tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2hit 100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_L2_HIT@ / cpu_atom@MEM_BOUND_STALLS.IFETCH@ Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2 00tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3hit 100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS.IFETCH@ Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3 00tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3miss 100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_DRAM_HIT@ / cpu_atom@MEM_BOUND_STALLS.IFETCH@ Percentage of ifetch miss bound stalls, where the ifetch miss subsequently misses in the L3 00tma_info_load_miss_bound_%_loadmissbound_with_l2hit load_store_bound 100 * cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / cpu_atom@MEM_BOUND_STALLS.LOAD@ Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2 00tma_info_load_miss_bound_%_loadmissbound_with_l3hit load_store_bound 100 * cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS.LOAD@ Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3 00tma_info_load_miss_bound_%_loadmissbound_with_l3miss load_store_bound 100 * cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / cpu_atom@MEM_BOUND_STALLS.LOAD@ Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses the L3 00tma_info_load_store_bound_l1_bound load_store_bound 100 * cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ / cpu_atom@CPU_CLK_UNHALTED.CORE@ Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block 00tma_info_load_store_bound_load_bound load_store_bound 100 * (cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ + cpu_atom@MEM_BOUND_STALLS.LOAD@) / cpu_atom@CPU_CLK_UNHALTED.CORE@ Counts the number of cycles that the oldest load of the load buffer is stalled at retirement 00tma_info_load_store_bound_store_bound load_store_bound 100 * (cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_atom@MEM_SCHEDULER_BLOCK.ALL@) * tma_mem_scheduler Counts the number of cycles the core is stalled due to store buffer full 00tma_info_machine_clear_bound_machine_clears_disamb_pki 1e3 * cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@ / cpu_atom@INST_RETIRED.ANY@ Counts the number of machine clears relative to thousands of instructions retired, due to memory disambiguation 00tma_info_machine_clear_bound_machine_clears_fp_assist_pki 1e3 * cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / cpu_atom@INST_RETIRED.ANY@ Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists 00tma_info_machine_clear_bound_machine_clears_monuke_pki 1e3 * cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING@ / cpu_atom@INST_RETIRED.ANY@ Counts the number of machine clears relative to thousands of instructions retired, due to memory ordering 00tma_info_machine_clear_bound_machine_clears_mrn_pki 1e3 * cpu_atom@MACHINE_CLEARS.MRN_NUKE@ / cpu_atom@INST_RETIRED.ANY@ Counts the number of machine clears relative to thousands of instructions retired, due to memory renaming 00tma_info_machine_clear_bound_machine_clears_page_fault_pki 1e3 * cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / cpu_atom@INST_RETIRED.ANY@ Counts the number of machine clears relative to thousands of instructions retired, due to page faults 00tma_info_machine_clear_bound_machine_clears_smc_pki 1e3 * cpu_atom@MACHINE_CLEARS.SMC@ / cpu_atom@INST_RETIRED.ANY@ Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code 00tma_info_mem_exec_blocks_%_loads_with_adressaliasing 100 * cpu_atom@LD_BLOCKS.4K_ALIAS@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ Percentage of total non-speculative loads with an address aliasing block 00tma_info_mem_exec_blocks_%_loads_with_storefwdblk 100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ Percentage of total non-speculative loads with a store forward or unknown store address block 00tma_info_mem_exec_bound_%_loadhead_with_l1miss 100 * cpu_atom@LD_HEAD.L1_MISS_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@ Percentage of Memory Execution Bound due to a first level data cache miss 00tma_info_mem_exec_bound_%_loadhead_with_otherpipelineblks 100 * cpu_atom@LD_HEAD.OTHER_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@ Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc 00tma_info_mem_exec_bound_%_loadhead_with_pagewalk 100 * cpu_atom@LD_HEAD.PGWALK_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@ Percentage of Memory Execution Bound due to a pagewalk 00tma_info_mem_exec_bound_%_loadhead_with_stlbhit 100 * cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@ Percentage of Memory Execution Bound due to a second level TLB miss 00tma_info_mem_exec_bound_%_loadhead_with_storefwding 100 * cpu_atom@LD_HEAD.ST_ADDR_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@ Percentage of Memory Execution Bound due to a store forward address match 00tma_info_mem_mix_ipload cpu_atom@INST_RETIRED.ANY@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ Instructions per Load 00tma_info_mem_mix_ipstore cpu_atom@INST_RETIRED.ANY@ / cpu_atom@MEM_UOPS_RETIRED.ALL_STORES@ Instructions per Store 00tma_info_mem_mix_load_locks_ratio 100 * cpu_atom@MEM_UOPS_RETIRED.LOCK_LOADS@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ Percentage of total non-speculative loads that perform one or more locks 00tma_info_mem_mix_load_splits_ratio 100 * cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ Percentage of total non-speculative loads that are splits 00tma_info_mem_mix_memload_ratio 1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / cpu_atom@UOPS_RETIRED.ALL@ Ratio of mem load uops to all uops 00tma_info_serialization _%_tpause_cycles 100 * cpu_atom@SERIALIZATION.C01_MS_SCB@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction 00tma_info_system_cpu_utilization cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ / TSC Average CPU Utilization 00tma_info_system_kernel_utilization Summary cpu_atom@CPU_CLK_UNHALTED.CORE_P@k / cpu_atom@CPU_CLK_UNHALTED.CORE@ Fraction of cycles spent in Kernel mode 00tma_info_system_turbo_utilization Power cpu_atom@CPU_CLK_UNHALTED.CORE@ / cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ Average Frequency Utilization relative nominal frequency 00tma_info_uop_mix_fpdiv_uop_ratio 100 * cpu_atom@UOPS_RETIRED.FPDIV@ / cpu_atom@UOPS_RETIRED.ALL@ Percentage of all uops which are FPDiv uops 00tma_info_uop_mix_idiv_uop_ratio 100 * cpu_atom@UOPS_RETIRED.IDIV@ / cpu_atom@UOPS_RETIRED.ALL@ Percentage of all uops which are IDiv uops 00tma_info_uop_mix_microcode_uop_ratio 100 * cpu_atom@UOPS_RETIRED.MS@ / cpu_atom@UOPS_RETIRED.ALL@ Percentage of all uops which are microcode ops 00tma_info_uop_mix_x87_uop_ratio 100 * cpu_atom@UOPS_RETIRED.X87@ / cpu_atom@UOPS_RETIRED.ALL@ Percentage of all uops which are x87 uops 00tma_itlb_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.ITLB@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses 100% 00tma_machine_clears TopdownL2;tma_L2_group;tma_bad_speculation_group cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_machine_clears > 0.05 & tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation 100% TopdownL2 00tma_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops 100% 00tma_non_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops 100% 00tma_nuke TopdownL3;tma_L3_group;tma_machine_clears_group cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke) 100% 00tma_other_fb TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized 100% 00tma_predecode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes 100% 00tma_register TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls) 100% 00tma_reorder_buffer TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls) 100% 00tma_resource_bound TopdownL2;tma_L2_group;tma_backend_bound_group tma_backend_bound - tma_core_bound tma_resource_bound > 0.2 & tma_backend_bound > 0.1 Counts the number of cycles the core is stalled due to a resource limitation 100% TopdownL2 00tma_retiring Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_RETIRING.ALL@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_retiring > 0.75 Counts the number of issue slots that result in retirement slots 100% TopdownL1;Default TopdownL1 00tma_serialization TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS) 100% 00cpu_core UNCORE_FREQ SoC tma_info_system_socket_clks / #num_dies / duration_time / 1e9 Uncore frequency per die [GHZ] 00tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (cpu_core@UOPS_DISPATCHED.PORT_0@ + cpu_core@UOPS_DISPATCHED.PORT_1@ + cpu_core@UOPS_DISPATCHED.PORT_5_11@ + cpu_core@UOPS_DISPATCHED.PORT_6@) / (5 * tma_info_core_core_clks) tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 00tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 78 * cpu_core@ASSISTS.ANY@ / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100% 00tma_avx_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 63 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_thread_slots tma_avx_assists > 0.1 This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists 100% 00tma_backend_bound BvOB;Default;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-be\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) + 0 * tma_info_thread_slots tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100% TopdownL1;Default TopdownL1 00tma_bad_speculation Default;TmaL1;TopdownL1;tma_L1_group max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0) tma_bad_speculation > 0.15 This category represents fraction of slots wasted due to incorrect speculations This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example 100% TopdownL1;Default TopdownL1 00tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM cpu_core@topdown\-br\-mispredict@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) + 0 * tma_info_thread_slots tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 100% TopdownL2 00tma_branch_resteers FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks + tma_unknown_branches tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES 100% 00tma_c01_wait C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group cpu_core@CPU_CLK_UNHALTED.C01@ / tma_info_thread_clks tma_c01_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings) 100% 00tma_c02_wait C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group cpu_core@CPU_CLK_UNHALTED.C02@ / tma_info_thread_clks tma_c02_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings) 100% 00tma_cisc TopdownL4;tma_L4_group;tma_microcode_sequencer_group max(0, tma_microcode_sequencer - tma_assists) tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources. Sample with: FRONTEND_RETIRED.MS_FLOWS 100% 00tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC (1 - tma_branch_mispredicts / tma_bad_speculation) * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100% 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (25 * tma_info_system_core_frequency * (cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) + 24 * tma_info_system_core_frequency * cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_core_bound Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group max(0, tma_backend_bound - tma_memory_bound) tma_core_bound > 0.1 & tma_backend_bound > 0.2 This metric represents fraction of slots where Core non-memory issues were of a bottleneck This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations) 100% TopdownL2 00tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 24 * tma_info_system_core_frequency * (cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD@ + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * (1 - cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_decoder0_alone DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group (cpu_core@INST_DECODED.DECODERS\,cmask\=1@ - cpu_core@INST_DECODED.DECODERS\,cmask\=2@) / tma_info_core_core_clks / 2 tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & tma_fetch_bandwidth > 0.2) This metric represents fraction of cycles where decoder-0 was the only active decoder This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions 100% 00tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group cpu_core@ARITH.DIV_ACTIVE@ / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group cpu_core@MEMORY_ACTIVITY.STALLS_L3_MISS@ / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 00tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@IDQ.DSB_CYCLES_ANY@ - cpu_core@IDQ.DSB_CYCLES_OK@) / tma_info_core_core_clks / 2 tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100% 00tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES@ / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% 00tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(7 * cpu_core@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + cpu_core@DTLB_LOAD_MISSES.WALK_ACTIVE@, max(cpu_core@CYCLE_ACTIVITY.CYCLES_MEM_ANY@ - cpu_core@MEMORY_ACTIVITY.CYCLES_L1D_MISS@, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization 100% 00tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (7 * cpu_core@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@) / tma_info_core_core_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization 100% 00tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 28 * tma_info_system_core_frequency * cpu_core@OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM@ / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fb_full BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group cpu_core@L1D_PEND_MISS.FB_FULL@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100% 00tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB max(0, tma_frontend_bound - tma_fetch_latency) tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2 00tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_core@topdown\-fetch\-lat@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100% TopdownL2 00tma_few_uops_instructions TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0 max(0, tma_heavy_operations - tma_microcode_sequencer) tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone 100% 00tma_fp_arith HPC;TopdownL3;tma_L3_group;tma_light_operations_group tma_x87_use + tma_fp_scalar + tma_fp_vector tma_fp_arith > 0.2 & tma_light_operations > 0.6 This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired) This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of "Uops" CountDomain and FMA double-counting 100% 00tma_fp_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 30 * cpu_core@ASSISTS.FP@ / tma_info_thread_slots tma_fp_assists > 0.1 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals) 100% 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ / (tma_retiring * tma_info_thread_slots) tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu_core@FP_ARITH_INST_RETIRED.VECTOR@ / (tma_retiring * tma_info_thread_slots) tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_frontend_bound BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-fe\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS 100% TopdownL1;Default TopdownL1 00tma_fused_instructions Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * cpu_core@INST_RETIRED.MACRO_FUSED@ / (tma_retiring * tma_info_thread_slots) tma_fused_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)} 100% 00tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group cpu_core@topdown\-heavy\-ops@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) + 0 * tma_info_thread_slots tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .). Sample with: UOPS_RETIRED.HEAVY 100% TopdownL2 00tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_core@ICACHE_DATA.STALLS@ / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100% 00tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM tma_info_bottleneck_mispredictions * tma_info_thread_slots / cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ / 100 Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 00tma_info_bad_spec_ipmisp_cond_ntaken Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.COND_NTAKEN@ tma_info_bad_spec_ipmisp_cond_ntaken < 200 Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_cond_taken Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.COND_TAKEN@ tma_info_bad_spec_ipmisp_cond_taken < 200 Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_indirect Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.INDIRECT@ tma_info_bad_spec_ipmisp_indirect < 1e3 Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_ret Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.RET@ tma_info_bad_spec_ipmisp_ret < 500 Instructions per retired mispredicts for return branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmispredict Bad;BadSpec;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ tma_info_bad_spec_ipmispredict < 200 Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate) 00tma_info_bad_spec_spec_clears_ratio BrMispredicts cpu_core@INT_MISC.CLEARS_COUNT@ / (cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ + cpu_core@MACHINE_CLEARS.COUNT@) Speculative to Retired ratio of all clears (covering mispredicts and nukes) 00tma_info_botlnk_l0_core_bound_likely Cor;SMT (100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0) tma_info_botlnk_l0_core_bound_likely > 0.5 Probability of Core Bound bottleneck hidden by SMT-profiling artifacts 00tma_info_botlnk_l2_dsb_bandwidth DSB;FetchBW;tma_issueFB 100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_lsd + tma_mite))) tma_info_botlnk_l2_dsb_bandwidth > 10 Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 00tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 00tma_info_botlnk_l2_ic_misses Fed;FetchLat;IcMiss;tma_issueFL 100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_info_botlnk_l2_ic_misses > 5 Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: 00tma_info_bottleneck_big_code BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB 100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) tma_info_bottleneck_big_code > 20 Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses) 00tma_info_bottleneck_branching_overhead BvBO;Ret 100 * ((cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@INST_RETIRED.NOP@) / tma_info_thread_slots) tma_info_bottleneck_branching_overhead > 5 Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound) 00tma_info_bottleneck_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_info_bottleneck_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full 00tma_info_bottleneck_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_hit_latency / (tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_info_bottleneck_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency 00tma_info_bottleneck_compute_bound_est BvCB;Cor;tma_issueComp 100 * (tma_core_bound * tma_divider / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m))) tma_info_bottleneck_compute_bound_est > 20 Total pipeline cost when the execution is compute-bound - an estimation Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics: 00tma_info_bottleneck_instruction_fetch_bw BvFB;Fed;FetchBW;Frontend 100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - (1 - cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.MS\,cmask\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))) - tma_info_bottleneck_big_code tma_info_bottleneck_instruction_fetch_bw > 20 Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end) 00tma_info_bottleneck_irregular_overhead Bad;BvIO;Cor;Ret;tma_issueMS 100 * ((1 - cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.MS\,cmask\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + cpu_core@RS.EMPTY\,umask\=1@ / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_info_bottleneck_irregular_overhead > 10 Total pipeline cost of irregular execution (e.g Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches 00tma_info_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization 00tma_info_bottleneck_memory_synchronization BvMS;Mem;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_info_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs 00tma_info_bottleneck_mispredictions Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM 100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_info_bottleneck_mispredictions > 20 Total pipeline cost of Branch Misprediction related bottlenecks Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 00tma_info_bottleneck_other_bottlenecks BvOB;Cor;Offcore 100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info_bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_latency + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_synchronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_irregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottleneck_useful_work) tma_info_bottleneck_other_bottlenecks > 20 Total pipeline cost of remaining bottlenecks in the back-end Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls 00tma_info_bottleneck_useful_work BvUW;Ret 100 * (tma_retiring - (cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@INST_RETIRED.NOP@) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_info_bottleneck_useful_work > 20 Total pipeline cost of "useful operations" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead 00tma_info_branches_callret Bad;Branches (cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@BR_INST_RETIRED.NEAR_RETURN@) / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ Fraction of branches that are CALL or RET 00tma_info_branches_cond_nt Bad;Branches;CodeGen;PGO cpu_core@BR_INST_RETIRED.COND_NTAKEN@ / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ Fraction of branches that are non-taken conditionals 00tma_info_branches_cond_tk Bad;Branches;CodeGen;PGO cpu_core@BR_INST_RETIRED.COND_TAKEN@ / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ Fraction of branches that are taken conditionals 00tma_info_branches_jump Bad;Branches (cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu_core@BR_INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@) / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ Fraction of branches that are unconditional (direct or indirect) jumps 00tma_info_branches_other_branches Bad;Branches 1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_callret + tma_info_branches_jump) Fraction of branches of other types (not individually covered by other metrics in Info.Branches group) 00tma_info_core_core_clks SMT (cpu_core@CPU_CLK_UNHALTED.DISTRIBUTED@ if #SMT_on else tma_info_thread_clks) Core actual clocks when any Logical Processor is active on the Physical Core 00tma_info_core_coreipc Ret;SMT;TmaL1;tma_L1_group cpu_core@INST_RETIRED.ANY@ / tma_info_core_core_clks Instructions Per Cycle across hyper-threads (per physical core) 00tma_info_core_epc Power cpu_core@UOPS_EXECUTED.THREAD@ / tma_info_thread_clks uops Executed per Cycle 00tma_info_core_flopc Flops;Ret (cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_INST_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / tma_info_core_core_clks Floating Point Operations Per Cycle 00tma_info_core_fp_arith_utilization Cor;Flops;HPC (cpu_core@FP_ARITH_DISPATCHED.PORT_0@ + cpu_core@FP_ARITH_DISPATCHED.PORT_1@ + cpu_core@FP_ARITH_DISPATCHED.PORT_5@) / (2 * tma_info_core_core_clks) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common) 00tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil cpu_core@UOPS_EXECUTED.THREAD@ / cpu_core@UOPS_EXECUTED.THREAD\,cmask\=1@ Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor) 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB cpu_core@IDQ.DSB_UOPS@ / cpu_core@UOPS_ISSUED.ANY@ tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp 00tma_info_frontend_dsb_switch_cost DSBmiss cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES@ / cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES\,cmask\=1\,edge@ Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details 00tma_info_frontend_fetch_upc Fed;FetchBW cpu_core@UOPS_ISSUED.ANY@ / cpu_core@UOPS_ISSUED.ANY\,cmask\=1@ Average number of Uops issued by front-end when it issued something 00tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss cpu_core@ICACHE_DATA.STALLS@ / cpu_core@ICACHE_DATA.STALLS\,cmask\=1\,edge@ Average Latency for L1 instruction cache misses 00tma_info_frontend_ipdsb_miss_ret DSBmiss;Fed cpu_core@INST_RETIRED.ANY@ / cpu_core@FRONTEND_RETIRED.ANY_DSB_MISS@ tma_info_frontend_ipdsb_miss_ret < 50 Instructions per non-speculative DSB miss (lower number means higher occurrence rate) 00tma_info_frontend_ipunknown_branch Fed tma_info_inst_mix_instructions / cpu_core@BACLEARS.ANY@ Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate) 00tma_info_frontend_l2mpki_code IcMiss 1e3 * cpu_core@FRONTEND_RETIRED.L2_MISS@ / cpu_core@INST_RETIRED.ANY@ L2 cache true code cacheline misses per kilo instruction 00tma_info_frontend_l2mpki_code_all IcMiss 1e3 * cpu_core@L2_RQSTS.CODE_RD_MISS@ / cpu_core@INST_RETIRED.ANY@ L2 cache speculative code cacheline misses per kilo instruction 00tma_info_frontend_lsd_coverage Fed;LSD cpu_core@LSD.UOPS@ / cpu_core@UOPS_ISSUED.ANY@ Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache) 00tma_info_frontend_unknown_branch_cost Fed cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES@ / cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES\,cmask\=1\,edge@ Average number of cycles the front-end was delayed due to an Unknown Branch detection Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node 00tma_info_inst_mix_bptkbranch Branches;Fed;PGO cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ / cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ Branch instructions per taken branch 00tma_info_inst_mix_instructions Summary;TmaL1;tma_L1_group cpu_core@INST_RETIRED.ANY@ Total number of retired Instructions Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST 00tma_info_inst_mix_iparith Flops;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + cpu_core@FP_ARITH_INST_RETIRED.VECTOR@) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW 00tma_info_inst_mix_iparith_avx128 Flops;FpVector;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@) tma_info_inst_mix_iparith_avx128 < 10 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_iparith_avx256 Flops;FpVector;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) tma_info_inst_mix_iparith_avx256 < 10 Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_iparith_scalar_dp Flops;FpScalar;InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ tma_info_inst_mix_iparith_scalar_dp < 10 Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_iparith_scalar_sp Flops;FpScalar;InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE@ tma_info_inst_mix_iparith_scalar_sp < 10 Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_ipbranch Branches;Fed;InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ tma_info_inst_mix_ipbranch < 8 Instructions per Branch (lower number means higher occurrence rate) 00tma_info_inst_mix_ipcall Branches;Fed;PGO cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.NEAR_CALL@ tma_info_inst_mix_ipcall < 200 Instructions per (near) call (lower number means higher occurrence rate) 00tma_info_inst_mix_ipflop Flops;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_INST_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 00tma_info_inst_mix_ipload InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@MEM_INST_RETIRED.ALL_LOADS@ tma_info_inst_mix_ipload < 3 Instructions per Load (lower number means higher occurrence rate) 00tma_info_inst_mix_ippause Flops;FpVector;InsType tma_info_inst_mix_instructions / cpu_core@CPU_CLK_UNHALTED.PAUSE_INST@ Instructions per PAUSE (lower number means higher occurrence rate) 00tma_info_inst_mix_ipstore InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@ tma_info_inst_mix_ipstore < 8 Instructions per Store (lower number means higher occurrence rate) 00tma_info_inst_mix_ipswpf Prefetches cpu_core@INST_RETIRED.ANY@ / cpu_core@SW_PREFETCH_ACCESS.T0\,umask\=0xF@ tma_info_inst_mix_ipswpf < 100 Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate) 00tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ tma_info_inst_mix_iptb < 13 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp 00tma_info_memory_core_l1d_cache_fill_bw_2t Mem;MemoryBW tma_info_memory_l1d_cache_fill_bw Average per-core data fill bandwidth to the L1 data cache [GB / sec] 00tma_info_memory_core_l2_cache_fill_bw_2t Mem;MemoryBW tma_info_memory_l2_cache_fill_bw Average per-core data fill bandwidth to the L2 cache [GB / sec] 00tma_info_memory_core_l3_cache_access_bw_2t Mem;MemoryBW;Offcore tma_info_memory_l3_cache_access_bw Average per-core data access bandwidth to the L3 cache [GB / sec] 00tma_info_memory_core_l3_cache_fill_bw_2t Mem;MemoryBW tma_info_memory_l3_cache_fill_bw Average per-core data fill bandwidth to the L3 cache [GB / sec] 00tma_info_memory_fb_hpki CacheHits;Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@INST_RETIRED.ANY@ Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries) 00tma_info_memory_l1d_cache_fill_bw Mem;MemoryBW 64 * cpu_core@L1D.REPLACEMENT@ / 1e9 / duration_time Average per-thread data fill bandwidth to the L1 data cache [GB / sec] 00tma_info_memory_l1mpki CacheHits;Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / cpu_core@INST_RETIRED.ANY@ L1 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l1mpki_load CacheHits;Mem 1e3 * cpu_core@L2_RQSTS.ALL_DEMAND_DATA_RD@ / cpu_core@INST_RETIRED.ANY@ L1 cache true misses per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l2_cache_fill_bw Mem;MemoryBW 64 * cpu_core@L2_LINES_IN.ALL@ / 1e9 / duration_time Average per-thread data fill bandwidth to the L2 cache [GB / sec] 00tma_info_memory_l2hpki_all CacheHits;Mem 1e3 * (cpu_core@L2_RQSTS.REFERENCES@ - cpu_core@L2_RQSTS.MISS@) / cpu_core@INST_RETIRED.ANY@ L2 cache hits per kilo instruction for all request types (including speculative) 00tma_info_memory_l2hpki_load CacheHits;Mem 1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_HIT@ / cpu_core@INST_RETIRED.ANY@ L2 cache hits per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l2mpki Backend;CacheHits;Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.L2_MISS@ / cpu_core@INST_RETIRED.ANY@ L2 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l2mpki_all CacheHits;Mem;Offcore 1e3 * cpu_core@L2_RQSTS.MISS@ / cpu_core@INST_RETIRED.ANY@ L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative) 00tma_info_memory_l2mpki_load CacheHits;Mem 1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_MISS@ / cpu_core@INST_RETIRED.ANY@ L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l2mpki_rfo CacheMisses;Offcore 1e3 * cpu_core@L2_RQSTS.RFO_MISS@ / cpu_core@INST_RETIRED.ANY@ Offcore requests (L2 cache miss) per kilo instruction for demand RFOs 00tma_info_memory_l3_cache_access_bw Mem;MemoryBW;Offcore 64 * cpu_core@OFFCORE_REQUESTS.ALL_REQUESTS@ / 1e9 / duration_time Average per-thread data access bandwidth to the L3 cache [GB / sec] 00tma_info_memory_l3_cache_fill_bw Mem;MemoryBW 64 * cpu_core@LONGEST_LAT_CACHE.MISS@ / 1e9 / duration_time Average per-thread data fill bandwidth to the L3 cache [GB / sec] 00tma_info_memory_l3mpki Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.L3_MISS@ / cpu_core@INST_RETIRED.ANY@ L3 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_latency_data_l2_mlp Memory_BW;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DATA_RD@ / cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD@ Average Parallel L2 cache miss data reads 00tma_info_memory_latency_load_l2_miss_latency Memory_Lat;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD@ / cpu_core@OFFCORE_REQUESTS.DEMAND_DATA_RD@ Average Latency for L2 cache miss demand Loads 00tma_info_memory_latency_load_l2_mlp Memory_BW;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD@ / cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\,cmask\=1@ Average Parallel L2 cache miss demand Loads 00tma_info_memory_latency_load_l3_miss_latency Memory_Lat;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD@ / cpu_core@OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD@ Average Latency for L3 cache miss demand Loads 00tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat cpu_core@L1D_PEND_MISS.PENDING@ / cpu_core@MEM_LOAD_COMPLETED.L1_MISS_ANY@ Actual Average Latency for L1 data-cache miss demand load operations (in core cycles) 00tma_info_memory_mix_bus_lock_pki Mem 1e3 * cpu_core@SQ_MISC.BUS_LOCK@ / cpu_core@INST_RETIRED.ANY@ "Bus lock" per kilo instruction 00tma_info_memory_mix_uc_load_pki Mem 1e3 * cpu_core@MEM_LOAD_MISC_RETIRED.UC@ / cpu_core@INST_RETIRED.ANY@ Un-cacheable retired load per kilo instruction 00tma_info_memory_mlp Mem;MemoryBW;MemoryBound cpu_core@L1D_PEND_MISS.PENDING@ / cpu_core@L1D_PEND_MISS.PENDING_CYCLES@ Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor) 00tma_info_memory_tlb_code_stlb_mpki Fed;MemoryTLB 1e3 * cpu_core@ITLB_MISSES.WALK_COMPLETED@ / cpu_core@INST_RETIRED.ANY@ STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_tlb_load_stlb_mpki Mem;MemoryTLB 1e3 * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED@ / cpu_core@INST_RETIRED.ANY@ STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (cpu_core@ITLB_MISSES.WALK_PENDING@ + cpu_core@DTLB_LOAD_MISSES.WALK_PENDING@ + cpu_core@DTLB_STORE_MISSES.WALK_PENDING@) / (4 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_memory_tlb_store_stlb_mpki Mem;MemoryTLB 1e3 * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED@ / cpu_core@INST_RETIRED.ANY@ STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_pipeline_execute Cor;Pipeline;PortsUtil;SMT cpu_core@UOPS_EXECUTED.THREAD@ / (cpu_core@UOPS_EXECUTED.CORE_CYCLES_GE_1@ / 2 if #SMT_on else cpu_core@UOPS_EXECUTED.THREAD\,cmask\=1@) Instruction-Level-Parallelism (average number of uops executed when there is execution) per core 00tma_info_pipeline_fetch_dsb Fed;FetchBW cpu_core@IDQ.DSB_UOPS@ / cpu_core@IDQ.DSB_CYCLES_ANY@ Average number of uops fetched from DSB per cycle 00tma_info_pipeline_fetch_lsd Fed;FetchBW cpu_core@LSD.UOPS@ / cpu_core@LSD.CYCLES_ACTIVE@ Average number of uops fetched from LSD per cycle 00tma_info_pipeline_fetch_mite Fed;FetchBW cpu_core@IDQ.MITE_UOPS@ / cpu_core@IDQ.MITE_CYCLES_ANY@ Average number of uops fetched from MITE per cycle 00tma_info_pipeline_ipassist MicroSeq;Pipeline;Ret;Retire cpu_core@INST_RETIRED.ANY@ / cpu_core@ASSISTS.ANY@ tma_info_pipeline_ipassist < 100e3 Instructions per a microcode Assist invocation Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate) 00tma_info_pipeline_retire Pipeline;Ret tma_retiring * tma_info_thread_slots / cpu_core@UOPS_RETIRED.SLOTS\,cmask\=1@ Average number of Uops retired in cycles where at least one uop has retired 00tma_info_pipeline_strings_cycles MicroSeq;Pipeline;Ret cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.SLOTS\,cmask\=1@ tma_info_pipeline_strings_cycles > 0.1 Estimated fraction of retirement-cycles dealing with repeat instructions 00tma_info_system_c0_wait C0Wait cpu_core@CPU_CLK_UNHALTED.C0_WAIT@ / tma_info_thread_clks tma_info_system_c0_wait > 0.05 Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states 00tma_info_system_core_frequency Power;Summary tma_info_system_turbo_utilization * TSC / 1e9 / duration_time Measured Average Core Frequency for unhalted processors [GHz] 00tma_info_system_cpu_utilization HPC;Summary tma_info_system_cpus_utilized / #num_cpus_online Average CPU Utilization (percentage) 00tma_info_system_cpus_utilized Summary cpu_core@CPU_CLK_UNHALTED.REF_TSC@ / TSC Average number of utilized CPUs 00tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3 Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_mem_bandwidth, tma_sq_full 00tma_info_system_gflops Cor;Flops;HPC (cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_INST_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width 00tma_info_system_ipfarbranch Branches;OS cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.FAR_BRANCH@u tma_info_system_ipfarbranch < 1e6 Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate] 00tma_info_system_kernel_cpi OS cpu_core@CPU_CLK_UNHALTED.THREAD_P@k / cpu_core@INST_RETIRED.ANY_P@k Cycles Per Instruction for the Operating System (OS) Kernel mode 00tma_info_system_kernel_utilization OS cpu_core@CPU_CLK_UNHALTED.THREAD_P@k / cpu_core@CPU_CLK_UNHALTED.THREAD@ tma_info_system_kernel_utilization > 0.05 Fraction of cycles spent in the Operating System (OS) Kernel mode 00tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_ARB_DAT_OCCUPANCY.RD / UNC_ARB_DAT_OCCUPANCY.RD@cmask\=1@ Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC (UNC_ARB_TRK_OCCUPANCY.RD + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.RD Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 01tma_info_system_smt_2t_utilization SMT (1 - cpu_core@CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE@ / cpu_core@CPU_CLK_UNHALTED.REF_DISTRIBUTED@ if #SMT_on else 0) Fraction of cycles where both hardware Logical Processors were active 00tma_info_system_socket_clks SoC UNC_CLOCK.SOCKET Socket actual clocks when any core is active on that socket 00tma_info_system_turbo_utilization Power tma_info_thread_clks / cpu_core@CPU_CLK_UNHALTED.REF_TSC@ Average Frequency Utilization relative nominal frequency 00tma_info_thread_clks Pipeline cpu_core@CPU_CLK_UNHALTED.THREAD@ Per-Logical Processor actual clocks when the Logical Processor is active 00tma_info_thread_cpi Mem;Pipeline 1 / tma_info_thread_ipc Cycles Per Instruction (per Logical Processor) 00tma_info_thread_execute_per_issue Cor;Pipeline cpu_core@UOPS_EXECUTED.THREAD@ / cpu_core@UOPS_ISSUED.ANY@ The ratio of Executed- by Issued-Uops The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage 00tma_info_thread_ipc Ret;Summary cpu_core@INST_RETIRED.ANY@ / tma_info_thread_clks Instructions Per Cycle (per Logical Processor) 00tma_info_thread_slots TmaL1;tma_L1_group cpu_core@TOPDOWN.SLOTS@ Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward) 00tma_info_thread_slots_utilization SMT;TmaL1;tma_L1_group (tma_info_thread_slots / (cpu_core@TOPDOWN.SLOTS@ / 2) if #SMT_on else 1) Fraction of Physical Core issue-slots utilized by this Logical Processor 00tma_info_thread_uoppi Pipeline;Ret;Retire tma_retiring * tma_info_thread_slots / cpu_core@INST_RETIRED.ANY@ tma_info_thread_uoppi > 1.05 Uops Per Instruction 00tma_info_thread_uptb Branches;Fed;FetchBW tma_retiring * tma_info_thread_slots / cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ tma_info_thread_uptb < 9 Uops per taken branch 00tma_int_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_int_vector_128b + tma_int_vector_256b tma_int_operations > 0.1 & tma_light_operations > 0.6 This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired) This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of "Uops" CountDomain 100% 00tma_int_vector_128b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (cpu_core@INT_VEC_RETIRED.ADD_128@ + cpu_core@INT_VEC_RETIRED.VNNI_128@) / (tma_retiring * tma_info_thread_slots) tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_int_vector_256b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (cpu_core@INT_VEC_RETIRED.ADD_256@ + cpu_core@INT_VEC_RETIRED.MUL_256@ + cpu_core@INT_VEC_RETIRED.VNNI_256@) / (tma_retiring * tma_info_thread_slots) tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_core@ICACHE_TAG.STALLS@ / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS 100% 00tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 data cache This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100% 00tma_l1_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group min(2 * (cpu_core@MEM_INST_RETIRED.ALL_LOADS@ - cpu_core@MEM_LOAD_RETIRED.FB_HIT@ - cpu_core@MEM_LOAD_RETIRED.L1_MISS@) * 20 / 100, max(cpu_core@CYCLE_ACTIVITY.CYCLES_MEM_ANY@ - cpu_core@MEMORY_ACTIVITY.CYCLES_L1D_MISS@, 0)) / tma_info_thread_clks tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT 100% 00tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L2_MISS@) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS 100% 00tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (cpu_core@MEMORY_ACTIVITY.STALLS_L2_MISS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L3_MISS@) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100% 00tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 9 * tma_info_system_core_frequency * (cpu_core@MEM_LOAD_RETIRED.L3_HIT@ * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency 100% 00tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB cpu_core@DECODE.LCP@ / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb 100% 00tma_light_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group max(0, tma_retiring - tma_heavy_operations) tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation) This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .). Sample with: INST_RETIRED.PREC_DIST 100% TopdownL2 00tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group cpu_core@UOPS_DISPATCHED.PORT_2_3_10@ / (3 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10 100% 00tma_load_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group tma_dtlb_load - tma_load_stlb_miss tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB) 100% 00tma_load_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group cpu_core@DTLB_LOAD_MISSES.WALK_ACTIVE@ / tma_info_thread_clks tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk 100% 00tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (16 * max(0, cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ - cpu_core@L2_RQSTS.ALL_RFO@) + cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@ * (10 * cpu_core@L2_RQSTS.RFO_HIT@ + min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO@))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100% 00tma_lsd FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@LSD.CYCLES_ACTIVE@ - cpu_core@LSD.CYCLES_OK@) / tma_info_core_core_clks / 2 tma_lsd > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure 100% 00tma_machine_clears BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn max(0, tma_bad_speculation - tma_branch_mispredicts) tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100% TopdownL2 00tma_mem_bandwidth BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full 100% 00tma_mem_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD@) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_latency 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group cpu_core@topdown\-mem\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) + 0 * tma_info_thread_slots tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 00tma_memory_fence TopdownL4;tma_L4_group;tma_serializing_operation_group 13 * cpu_core@MISC2_RETIRED.LFENCE@ / tma_info_thread_clks tma_memory_fence > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions 100% 02tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * cpu_core@MEM_UOP_RETIRED.ANY@ / (tma_retiring * tma_info_thread_slots) tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses 100% 00tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS cpu_core@UOPS_RETIRED.MS@ / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 00tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM tma_branch_mispredicts / tma_bad_speculation * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions 100% 00tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@IDQ.MITE_CYCLES_ANY@ - cpu_core@IDQ.MITE_CYCLES_OK@) / tma_info_core_core_clks / 2 tma_mite > 0.1 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100% 00tma_mixing_vectors TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group 160 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_thread_clks tma_mixing_vectors > 0.05 This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles) This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches 100% 00tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * cpu_core@UOPS_RETIRED.MS\,cmask\=1\,edge@ / (cpu_core@UOPS_RETIRED.SLOTS@ / cpu_core@UOPS_ISSUED.ANY@) / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_non_fused_branches Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * (cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ - cpu_core@INST_RETIRED.MACRO_FUSED@) / (tma_retiring * tma_info_thread_slots) tma_non_fused_branches > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused 100% 00tma_nop_instructions BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group tma_light_operations * cpu_core@INST_RETIRED.NOP@ / (tma_retiring * tma_info_thread_slots) tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6) This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP 100% 00tma_other_light_ops Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches)) tma_other_light_ops > 0.3 & tma_light_operations > 0.6 This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting 100% 00tma_other_mispredicts BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_branch_mispredicts_group max(tma_branch_mispredicts * (1 - cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ / (cpu_core@INT_MISC.CLEARS_COUNT@ - cpu_core@MACHINE_CLEARS.COUNT@)), 0.0001) tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types) 100% 00tma_other_nukes BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group max(tma_machine_clears * (1 - cpu_core@MACHINE_CLEARS.MEMORY_ORDERING@ / cpu_core@MACHINE_CLEARS.COUNT@), 0.0001) tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering 100% 00tma_page_faults TopdownL5;tma_L5_group;tma_assists_group 99 * cpu_core@ASSISTS.PAGE_FAULT@ / tma_info_thread_slots tma_page_faults > 0.05 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost 100% 00tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P cpu_core@UOPS_DISPATCHED.PORT_0@ / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P cpu_core@UOPS_DISPATCHED.PORT_1@ / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P cpu_core@UOPS_DISPATCHED.PORT_6@ / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((tma_ports_utilized_0 * tma_info_thread_clks + (cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\,umask\=0xc@)) / tma_info_thread_clks if cpu_core@ARITH.DIV_ACTIVE@ < cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ else (cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\,umask\=0xc@) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 00tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu_core@EXE_ACTIVITY.EXE_BOUND_0_PORTS@ + max(cpu_core@RS.EMPTY\,umask\=1@ - cpu_core@RESOURCE_STALLS.SCOREBOARD@, 0)) / tma_info_thread_clks * (cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@) / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ / tma_info_thread_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group cpu_core@EXE_ACTIVITY.2_PORTS_UTIL@ / tma_info_thread_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 02tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group cpu_core@UOPS_EXECUTED.CYCLES_GE_3@ / tma_info_thread_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100% 02tma_retiring BvUW;Default;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-retiring@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) + 0 * tma_info_thread_slots tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS 100% TopdownL1;Default TopdownL1 00tma_serializing_operation BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO cpu_core@RESOURCE_STALLS.SCOREBOARD@ / tma_info_thread_clks + tma_c02_wait tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100% 00tma_shuffles_256b HPC;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group tma_light_operations * cpu_core@INT_VEC_RETIRED.SHUFFLES@ / (tma_retiring * tma_info_thread_slots) tma_shuffles_256b > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6) This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer) This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross "vector lane" data transfers 100% 00tma_slow_pause TopdownL4;tma_L4_group;tma_serializing_operation_group cpu_core@CPU_CLK_UNHALTED.PAUSE@ / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST 100% 02tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu_core@LD_BLOCKS.NO_SR@ / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100% 00tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group cpu_core@MEM_INST_RETIRED.SPLIT_STORES@ / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100% 00tma_sq_full BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (cpu_core@XQ.FULL_CYCLES@ + cpu_core@L1D_PEND_MISS.L2_STALLS@) / tma_info_thread_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth 100% 00tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group cpu_core@EXE_ACTIVITY.BOUND_ON_STORES@ / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS 100% 00tma_store_fwd_blk TopdownL4;tma_L4_group;tma_l1_bound_group 13 * cpu_core@LD_BLOCKS.STORE_FORWARD@ / tma_info_thread_clks tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading 100% 00tma_store_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (cpu_core@MEM_STORE_RETIRED.L2_HIT@ * 10 * (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@) + (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@) * min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO@)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 00tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (cpu_core@UOPS_DISPATCHED.PORT_4_9@ + cpu_core@UOPS_DISPATCHED.PORT_7_8@) / (4 * tma_info_core_core_clks) tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8 100% 00tma_store_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group tma_dtlb_store - tma_store_stlb_miss tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB) 100% 00tma_store_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@ / tma_info_core_core_clks tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk 100% 00tma_streaming_stores MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group 9 * cpu_core@OCR.STREAMING_WR.ANY_RESPONSE@ / tma_info_thread_clks tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full 100% 00tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES@ / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH 100% 00tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group tma_retiring * cpu_core@UOPS_EXECUTED.X87@ / cpu_core@UOPS_EXECUTED.THREAD@ tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00Backend Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet Bad BadSpec BigFootprint BrMispredicts Branches BvBC BvBO BvCB BvFB BvIO BvMB BvML BvMP BvMS BvMT BvOB BvUW C0Wait CacheHits CacheMisses CodeGen Compute Cor DSB DSBmiss DataSharing Fed FetchBW FetchLat Flops FpScalar FpVector Frontend HPC IcMiss Ifetch InsType IntVector L2Evicts Load_Store_Miss MachineClears Machine_Clears Mem MemOffcore Mem_Exec MemoryBW MemoryBound MemoryLat MemoryTLB Memory_BW Memory_Lat MicroSeq OS PGO Pipeline PortsUtil Power Ret Retire SMT Server Snoop SoC Summary TmaL1 TmaL2 TmaL3mem TopdownL1 Metrics for top-down breakdown at level 1 TopdownL2 Metrics for top-down breakdown at level 2 TopdownL3 Metrics for top-down breakdown at level 3 TopdownL4 Metrics for top-down breakdown at level 4 TopdownL5 Metrics for top-down breakdown at level 5 TopdownL6 Metrics for top-down breakdown at level 6 load_store_bound tma_L1_group tma_L2_group tma_L3_group tma_L4_group tma_L5_group tma_L6_group tma_alu_op_utilization_group Metrics contributing to tma_alu_op_utilization category tma_assists_group Metrics contributing to tma_assists category tma_backend_bound_group Metrics contributing to tma_backend_bound category tma_bad_speculation_group Metrics contributing to tma_bad_speculation category tma_branch_mispredicts_group Metrics contributing to tma_branch_mispredicts category tma_branch_resteers_group Metrics contributing to tma_branch_resteers category tma_core_bound_group Metrics contributing to tma_core_bound category tma_dram_bound_group Metrics contributing to tma_dram_bound category tma_dtlb_load_group Metrics contributing to tma_dtlb_load category tma_dtlb_store_group Metrics contributing to tma_dtlb_store category tma_fetch_bandwidth_group Metrics contributing to tma_fetch_bandwidth category tma_fetch_latency_group Metrics contributing to tma_fetch_latency category tma_fp_arith_group Metrics contributing to tma_fp_arith category tma_fp_vector_group Metrics contributing to tma_fp_vector category tma_frontend_bound_group Metrics contributing to tma_frontend_bound category tma_heavy_operations_group Metrics contributing to tma_heavy_operations category tma_ifetch_bandwidth_group Metrics contributing to tma_ifetch_bandwidth category tma_ifetch_latency_group Metrics contributing to tma_ifetch_latency category tma_int_operations_group Metrics contributing to tma_int_operations category tma_issue2P Metrics related by the issue $issue2P tma_issueBM Metrics related by the issue $issueBM tma_issueBW Metrics related by the issue $issueBW tma_issueComp Metrics related by the issue $issueComp tma_issueD0 Metrics related by the issue $issueD0 tma_issueFB Metrics related by the issue $issueFB tma_issueFL Metrics related by the issue $issueFL tma_issueL1 Metrics related by the issue $issueL1 tma_issueLat Metrics related by the issue $issueLat tma_issueMC Metrics related by the issue $issueMC tma_issueMS Metrics related by the issue $issueMS tma_issueMV Metrics related by the issue $issueMV tma_issueRFO Metrics related by the issue $issueRFO tma_issueSL Metrics related by the issue $issueSL tma_issueSO Metrics related by the issue $issueSO tma_issueSmSt Metrics related by the issue $issueSmSt tma_issueSpSt Metrics related by the issue $issueSpSt tma_issueSyncxn Metrics related by the issue $issueSyncxn tma_issueTLB Metrics related by the issue $issueTLB tma_l1_bound_group Metrics contributing to tma_l1_bound category tma_l3_bound_group Metrics contributing to tma_l3_bound category tma_light_operations_group Metrics contributing to tma_light_operations category tma_load_op_utilization_group Metrics contributing to tma_load_op_utilization category tma_machine_clears_group Metrics contributing to tma_machine_clears category tma_mem_latency_group Metrics contributing to tma_mem_latency category tma_memory_bound_group Metrics contributing to tma_memory_bound category tma_microcode_sequencer_group Metrics contributing to tma_microcode_sequencer category tma_mite_group Metrics contributing to tma_mite category tma_other_light_ops_group Metrics contributing to tma_other_light_ops category tma_ports_utilization_group Metrics contributing to tma_ports_utilization category tma_ports_utilized_0_group Metrics contributing to tma_ports_utilized_0 category tma_ports_utilized_3m_group Metrics contributing to tma_ports_utilized_3m category tma_resource_bound_group Metrics contributing to tma_resource_bound category tma_retiring_group Metrics contributing to tma_retiring category tma_serializing_operation_group Metrics contributing to tma_serializing_operation category tma_store_bound_group Metrics contributing to tma_store_bound category tma_store_op_utilization_group Metrics contributing to tma_store_op_utilization category tma_backend_bound Default;TopdownL1;tma_L1_group TOPDOWN_BE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE) tma_backend_bound > 0.1 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count 100% TopdownL1;Default TopdownL1 00tma_bad_speculation Default;TopdownL1;tma_L1_group (5 * CPU_CLK_UNHALTED.CORE - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / (5 * CPU_CLK_UNHALTED.CORE) tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear 100% TopdownL1;Default TopdownL1 00tma_branch_detect TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.BRANCH_DETECT / (5 * CPU_CLK_UNHALTED.CORE) tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches 100% 00tma_branch_mispredicts TopdownL2;tma_L2_group;tma_bad_speculation_group TOPDOWN_BAD_SPECULATION.MISPREDICT / (5 * CPU_CLK_UNHALTED.CORE) tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15 Counts the number of issue slots that were not consumed by the backend due to branch mispredicts 100% TopdownL2 00tma_branch_resteer TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.BRANCH_RESTEER / (5 * CPU_CLK_UNHALTED.CORE) tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch 100% 00tma_cisc TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.CISC / (5 * CPU_CLK_UNHALTED.CORE) tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS) 100% 00tma_core_bound TopdownL2;tma_L2_group;tma_backend_bound_group TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / (5 * CPU_CLK_UNHALTED.CORE) tma_core_bound > 0.1 & tma_backend_bound > 0.1 Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation 100% TopdownL2 00tma_decode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.DECODE / (5 * CPU_CLK_UNHALTED.CORE) tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to decode stalls 100% 00tma_fast_nuke TopdownL3;tma_L3_group;tma_machine_clears_group TOPDOWN_BAD_SPECULATION.FASTNUKE / (5 * CPU_CLK_UNHALTED.CORE) tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming 100% 00tma_frontend_bound Default;TopdownL1;tma_L1_group TOPDOWN_FE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE) tma_frontend_bound > 0.2 Counts the number of issue slots that were not consumed by the backend due to frontend stalls 100% TopdownL1;Default TopdownL1 00tma_icache_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.ICACHE / (5 * CPU_CLK_UNHALTED.CORE) tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses 100% 00tma_ifetch_bandwidth TopdownL2;tma_L2_group;tma_frontend_bound_group TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / (5 * CPU_CLK_UNHALTED.CORE) tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations 100% TopdownL2 00tma_ifetch_latency TopdownL2;tma_L2_group;tma_frontend_bound_group TOPDOWN_FE_BOUND.FRONTEND_LATENCY / (5 * CPU_CLK_UNHALTED.CORE) tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations 100% TopdownL2 00tma_info_bottleneck_%_dtlb_miss_bound_cycles 100 * (LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT_RET) / CPU_CLK_UNHALTED.CORE Percentage of time that retirement is stalled due to a first level data TLB miss 00tma_info_bottleneck_%_ifetch_miss_bound_cycles Ifetch 100 * MEM_BOUND_STALLS.IFETCH / CPU_CLK_UNHALTED.CORE Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound 00tma_info_bottleneck_%_load_miss_bound_cycles Load_Store_Miss 100 * MEM_BOUND_STALLS.LOAD / CPU_CLK_UNHALTED.CORE Percentage of time that retirement is stalled due to an L1 miss Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound 00tma_info_bottleneck_%_mem_exec_bound_cycles Mem_Exec 100 * LD_HEAD.ANY_AT_RET / CPU_CLK_UNHALTED.CORE Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound 00tma_info_br_inst_mix_ipbranch INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES Instructions per Branch (lower number means higher occurrence rate) 00tma_info_br_inst_mix_ipcall INST_RETIRED.ANY / BR_INST_RETIRED.CALL Instruction per (near) call (lower number means higher occurrence rate) 00tma_info_br_inst_mix_ipfarbranch INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate] 00tma_info_br_inst_mix_ipmisp_cond_ntaken INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN) Instructions per retired conditional Branch Misprediction where the branch was not taken 00tma_info_br_inst_mix_ipmisp_cond_taken INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN Instructions per retired conditional Branch Misprediction where the branch was taken 00tma_info_br_inst_mix_ipmisp_indirect INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT Instructions per retired indirect call or jump Branch Misprediction 00tma_info_br_inst_mix_ipmisp_ret INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN Instructions per retired return Branch Misprediction 00tma_info_br_inst_mix_ipmispredict INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES Instructions per retired Branch Misprediction 00tma_info_br_mispredict_bound_branch_mispredict_ratio BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES Ratio of all branches which mispredict 00tma_info_br_mispredict_bound_branch_mispredict_to_unknown_branch_ratio BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY Ratio between Mispredicted branches and unknown branches 00tma_info_buffer_stalls_%_load_buffer_stall_cycles 100 * MEM_SCHEDULER_BLOCK.LD_BUF / CPU_CLK_UNHALTED.CORE Percentage of time that allocation is stalled due to load buffer full 00tma_info_buffer_stalls_%_mem_rsv_stall_cycles 100 * MEM_SCHEDULER_BLOCK.RSV / CPU_CLK_UNHALTED.CORE Percentage of time that allocation is stalled due to memory reservation stations full 00tma_info_buffer_stalls_%_store_buffer_stall_cycles 100 * MEM_SCHEDULER_BLOCK.ST_BUF / CPU_CLK_UNHALTED.CORE Percentage of time that allocation is stalled due to store buffer full 00tma_info_core_cpi CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANY Cycles Per Instruction 00tma_info_core_ipc INST_RETIRED.ANY / CPU_CLK_UNHALTED.CORE Instructions Per Cycle 00tma_info_core_upi UOPS_RETIRED.ALL / INST_RETIRED.ANY Uops Per Instruction 00tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2hit 100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2 00tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3hit 100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3 00tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3miss 100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH Percentage of ifetch miss bound stalls, where the ifetch miss subsequently misses in the L3 00tma_info_load_miss_bound_%_loadmissbound_with_l2hit load_store_bound 100 * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2 00tma_info_load_miss_bound_%_loadmissbound_with_l3hit load_store_bound 100 * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3 00tma_info_load_miss_bound_%_loadmissbound_with_l3miss load_store_bound 100 * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses the L3 00tma_info_load_store_bound_l1_bound load_store_bound 100 * LD_HEAD.L1_BOUND_AT_RET / CPU_CLK_UNHALTED.CORE Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block 00tma_info_load_store_bound_load_bound load_store_bound 100 * (LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS.LOAD) / CPU_CLK_UNHALTED.CORE Counts the number of cycles that the oldest load of the load buffer is stalled at retirement 00tma_info_load_store_bound_store_bound load_store_bound 100 * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL) * tma_mem_scheduler Counts the number of cycles the core is stalled due to store buffer full 00tma_info_machine_clear_bound_machine_clears_disamb_pki 1e3 * MACHINE_CLEARS.DISAMBIGUATION / INST_RETIRED.ANY Counts the number of machine clears relative to thousands of instructions retired, due to memory disambiguation 00tma_info_machine_clear_bound_machine_clears_fp_assist_pki 1e3 * MACHINE_CLEARS.FP_ASSIST / INST_RETIRED.ANY Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists 00tma_info_machine_clear_bound_machine_clears_monuke_pki 1e3 * MACHINE_CLEARS.MEMORY_ORDERING / INST_RETIRED.ANY Counts the number of machine clears relative to thousands of instructions retired, due to memory ordering 00tma_info_machine_clear_bound_machine_clears_mrn_pki 1e3 * MACHINE_CLEARS.MRN_NUKE / INST_RETIRED.ANY Counts the number of machine clears relative to thousands of instructions retired, due to memory renaming 00tma_info_machine_clear_bound_machine_clears_page_fault_pki 1e3 * MACHINE_CLEARS.PAGE_FAULT / INST_RETIRED.ANY Counts the number of machine clears relative to thousands of instructions retired, due to page faults 00tma_info_machine_clear_bound_machine_clears_smc_pki 1e3 * MACHINE_CLEARS.SMC / INST_RETIRED.ANY Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code 00tma_info_mem_exec_blocks_%_loads_with_adressaliasing 100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads with an address aliasing block 00tma_info_mem_exec_blocks_%_loads_with_storefwdblk 100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads with a store forward or unknown store address block 00tma_info_mem_exec_bound_%_loadhead_with_l1miss 100 * LD_HEAD.L1_MISS_AT_RET / LD_HEAD.ANY_AT_RET Percentage of Memory Execution Bound due to a first level data cache miss 00tma_info_mem_exec_bound_%_loadhead_with_otherpipelineblks 100 * LD_HEAD.OTHER_AT_RET / LD_HEAD.ANY_AT_RET Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc 00tma_info_mem_exec_bound_%_loadhead_with_pagewalk 100 * LD_HEAD.PGWALK_AT_RET / LD_HEAD.ANY_AT_RET Percentage of Memory Execution Bound due to a pagewalk 00tma_info_mem_exec_bound_%_loadhead_with_stlbhit 100 * LD_HEAD.DTLB_MISS_AT_RET / LD_HEAD.ANY_AT_RET Percentage of Memory Execution Bound due to a second level TLB miss 00tma_info_mem_exec_bound_%_loadhead_with_storefwding 100 * LD_HEAD.ST_ADDR_AT_RET / LD_HEAD.ANY_AT_RET Percentage of Memory Execution Bound due to a store forward address match 00tma_info_mem_mix_ipload INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS Instructions per Load 00tma_info_mem_mix_ipstore INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES Instructions per Store 00tma_info_mem_mix_load_locks_ratio 100 * MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads that perform one or more locks 00tma_info_mem_mix_load_splits_ratio 100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads that are splits 00tma_info_mem_mix_memload_ratio 1e3 * MEM_UOPS_RETIRED.ALL_LOADS / UOPS_RETIRED.ALL Ratio of mem load uops to all uops 00tma_info_serialization _%_tpause_cycles 100 * SERIALIZATION.C01_MS_SCB / (5 * CPU_CLK_UNHALTED.CORE) Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction 00tma_info_system_cpu_utilization CPU_CLK_UNHALTED.REF_TSC / TSC Average CPU Utilization 00tma_info_system_kernel_utilization Summary cpu@CPU_CLK_UNHALTED.CORE_P@k / CPU_CLK_UNHALTED.CORE Fraction of cycles spent in Kernel mode 00tma_info_system_turbo_utilization Power CPU_CLK_UNHALTED.CORE / CPU_CLK_UNHALTED.REF_TSC Average Frequency Utilization relative nominal frequency 00tma_info_uop_mix_fpdiv_uop_ratio 100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL Percentage of all uops which are FPDiv uops 00tma_info_uop_mix_idiv_uop_ratio 100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL Percentage of all uops which are IDiv uops 00tma_info_uop_mix_microcode_uop_ratio 100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL Percentage of all uops which are microcode ops 00tma_info_uop_mix_x87_uop_ratio 100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL Percentage of all uops which are x87 uops 00tma_itlb_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.ITLB / (5 * CPU_CLK_UNHALTED.CORE) tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses 100% 00tma_machine_clears TopdownL2;tma_L2_group;tma_bad_speculation_group TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / (5 * CPU_CLK_UNHALTED.CORE) tma_machine_clears > 0.05 & tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation 100% TopdownL2 00tma_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.MEM_SCHEDULER / (5 * CPU_CLK_UNHALTED.CORE) tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops 100% 00tma_non_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / (5 * CPU_CLK_UNHALTED.CORE) tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops 100% 00tma_nuke TopdownL3;tma_L3_group;tma_machine_clears_group TOPDOWN_BAD_SPECULATION.NUKE / (5 * CPU_CLK_UNHALTED.CORE) tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke) 100% 00tma_other_fb TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.OTHER / (5 * CPU_CLK_UNHALTED.CORE) tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized 100% 00tma_predecode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.PREDECODE / (5 * CPU_CLK_UNHALTED.CORE) tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes 100% 00tma_register TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.REGISTER / (5 * CPU_CLK_UNHALTED.CORE) tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls) 100% 00tma_reorder_buffer TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.REORDER_BUFFER / (5 * CPU_CLK_UNHALTED.CORE) tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls) 100% 00tma_retiring Default;TopdownL1;tma_L1_group TOPDOWN_RETIRING.ALL / (5 * CPU_CLK_UNHALTED.CORE) tma_retiring > 0.75 Counts the number of issue slots that result in retirement slots 100% TopdownL1;Default TopdownL1 00tma_serialization TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.SERIALIZATION / (5 * CPU_CLK_UNHALTED.CORE) tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS) 100% 00branch_misprediction_ratio branch_prediction d_ratio(ex_ret_brn_misp, ex_ret_brn) Execution-Time Branch Misprediction Ratio (Non-Speculative) 100% 00all_l2_cache_accesses l2_cache l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 All L2 Cache Accesses 00l2_cache_accesses_from_l2_hwpf l2_cache l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 L2 Cache Accesses from L2 HWPF 00all_l2_cache_misses l2_cache l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 All L2 Cache Misses 00l2_cache_misses_from_l2_hwpf l2_cache l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 L2 Cache Misses from L2 HWPF 00all_l2_cache_hits l2_cache l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2 All L2 Cache Hits 00l3_read_miss_latency l3_cache xi_sys_fill_latency * 16 / xi_ccx_sdp_req1.all_l3_miss_req_typs Average L3 Read Miss Latency (in core clocks) 1core clocks 00ic_fetch_miss_ratio l2_cache d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss) L1 Instruction Cache (32B) Fetch Miss Ratio 100% 00l1_itlb_misses tlb bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss L1 ITLB Misses 00all_remote_links_outbound data_fabric remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3 Approximate: Outbound data bytes for all Remote Links for a node (die) 3e-5MiB 00nps1_die_to_dram data_fabric dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7 Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) 6.1e-5MiB 01ic_fetch_miss_ratio l2_cache d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss) L1 Instruction Cache (32B) Fetch Miss Ratio 100% 00l1_itlb_misses tlb bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss L1 ITLB Misses 00l2_cache_misses_from_l2_hwpf l2_cache l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 L2 Cache Misses from L2 Cache HWPF 00l3_read_miss_latency l3_cache xi_sys_fill_latency * 16 / xi_ccx_sdp_req1 Average L3 Read Miss Latency (in core clocks) 1core clocks 00op_cache_fetch_miss_ratio l2_cache d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses) Op Cache (64B) Fetch Miss Ratio 00ic_fetch_miss_ratio l2_cache d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses) Instruction Cache (32B) Fetch Miss Ratio 100% 00l1_itlb_misses tlb bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss L1 ITLB Misses 00macro_ops_dispatched decoder de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch Macro-ops Dispatched 00total_dispatch_slots 6 * ls_not_halted_cyc Total dispatch slots (upto 6 instructions can be dispatched in each cycle) 00frontend_bound PipelineL1 d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots) Fraction of dispatch slots that remained unused because the frontend did not supply enough instructions/ops 100% 00bad_speculation PipelineL1 d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots) Fraction of dispatched ops that did not retire 100% 00backend_bound PipelineL1 d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots) Fraction of dispatch slots that remained unused because of backend stalls 100% 00smt_contention PipelineL1 d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots) Fraction of dispatch slots that remained unused because the other thread was selected 100% 00retiring PipelineL1 d_ratio(ex_ret_ops, total_dispatch_slots) Fraction of dispatch slots used by ops that retired 100% 00frontend_bound_latency PipelineL2;frontend_bound_group d_ratio(6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x6@, total_dispatch_slots) Fraction of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses) 100% 00frontend_bound_bandwidth PipelineL2;frontend_bound_group d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - 6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x6@, total_dispatch_slots) Fraction of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth) 100% 00bad_speculation_mispredicts PipelineL2;bad_speculation_group d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + resyncs_or_nc_redirects) Fraction of dispatched ops that were flushed due to branch mispredicts 100% 00bad_speculation_pipeline_restarts PipelineL2;bad_speculation_group d_ratio(bad_speculation * resyncs_or_nc_redirects, ex_ret_brn_misp + resyncs_or_nc_redirects) Fraction of dispatched ops that were flushed due to pipeline restarts (resyncs) 100% 00backend_bound_memory PipelineL2;backend_bound_group backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete) Fraction of dispatch slots that remained unused because of stalls due to the memory subsystem 100% 00backend_bound_cpu PipelineL2;backend_bound_group backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)) Fraction of dispatch slots that remained unused because of stalls not related to the memory subsystem 100% 00retiring_fastpath PipelineL2;retiring_group retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops)) Fraction of dispatch slots used by fastpath ops that retired 100% 00retiring_microcode PipelineL2;retiring_group retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops) Fraction of dispatch slots used by microcode ops that retired 100% 00branch_misprediction_ratio branch_prediction d_ratio(ex_ret_brn_misp, ex_ret_brn) Execution-time branch misprediction ratio (non-speculative) 100% 00all_l2_cache_accesses l2_cache l2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all All L2 cache accesses 00l2_cache_accesses_from_l1_ic_misses l2_cache l2_request_g1.cacheable_ic_read L2 cache accesses from L1 instruction cache misses (including prefetch) 00l2_cache_accesses_from_l1_dc_misses l2_cache l2_request_g1.all_dc L2 cache accesses from L1 data cache misses (including prefetch) 00l2_cache_accesses_from_l2_hwpf l2_cache l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all L2 cache accesses from L2 cache hardware prefetcher 00all_l2_cache_misses l2_cache l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all All L2 cache misses 00l2_cache_misses_from_l1_ic_miss l2_cache l2_cache_req_stat.ic_fill_miss L2 cache misses from L1 instruction cache misses 00l2_cache_misses_from_l1_dc_miss l2_cache l2_cache_req_stat.ls_rd_blk_c L2 cache misses from L1 data cache misses 00l2_cache_misses_from_l2_hwpf l2_cache l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all L2 cache misses from L2 cache hardware prefetcher 00all_l2_cache_hits l2_cache l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.all All L2 cache hits 00l2_cache_hits_from_l1_ic_miss l2_cache l2_cache_req_stat.ic_hit_in_l2 L2 cache hits from L1 instruction cache misses 00l2_cache_hits_from_l1_dc_miss l2_cache l2_cache_req_stat.dc_hit_in_l2 L2 cache hits from L1 data cache misses 00l2_cache_hits_from_l2_hwpf l2_cache l2_pf_hit_l2.all L2 cache hits from L2 cache hardware prefetcher 00l3_cache_accesses l3_cache l3_lookup_state.all_coherent_accesses_to_l3 L3 cache accesses 00l3_misses l3_cache l3_lookup_state.l3_miss L3 misses (including cacheline state change requests) 00l3_read_miss_latency l3_cache l3_xi_sampled_latency.all * 10 / l3_xi_sampled_latency_requests.all Average L3 read miss latency (in core clocks) 1core clocks 00op_cache_fetch_miss_ratio d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses) Op cache miss ratio for all fetches 100% 00ic_fetch_miss_ratio d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses) Instruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hit 100% 00l1_data_cache_fills_from_memory l1_dcache ls_any_fills_from_sys.dram_io_all L1 data cache fills from DRAM or MMIO in any NUMA node 00l1_data_cache_fills_from_remote_node l1_dcache ls_any_fills_from_sys.far_all L1 data cache fills from a different NUMA node 00l1_data_cache_fills_from_same_ccx l1_dcache ls_any_fills_from_sys.local_all L1 data cache fills from within the same CCX 00l1_data_cache_fills_from_different_ccx l1_dcache ls_any_fills_from_sys.remote_cache L1 data cache fills from another CCX cache in any NUMA node 00all_l1_data_cache_fills l1_dcache ls_any_fills_from_sys.all All L1 data cache fills 00l1_demand_data_cache_fills_from_local_l2 l1_dcache ls_dmnd_fills_from_sys.local_l2 L1 demand data cache fills from local L2 cache 00l1_demand_data_cache_fills_from_same_ccx l1_dcache ls_dmnd_fills_from_sys.local_ccx L1 demand data cache fills from within the same CCX 00l1_demand_data_cache_fills_from_near_cache l1_dcache ls_dmnd_fills_from_sys.near_cache L1 demand data cache fills from another CCX cache in the same NUMA node 00l1_demand_data_cache_fills_from_near_memory l1_dcache ls_dmnd_fills_from_sys.dram_io_near L1 demand data cache fills from DRAM or MMIO in the same NUMA node 00l1_demand_data_cache_fills_from_far_cache l1_dcache ls_dmnd_fills_from_sys.far_cache L1 demand data cache fills from another CCX cache in a different NUMA node 00l1_demand_data_cache_fills_from_far_memory l1_dcache ls_dmnd_fills_from_sys.dram_io_far L1 demand data cache fills from DRAM or MMIO in a different NUMA node 00l1_itlb_misses tlb bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all L1 instruction TLB misses 00l2_itlb_misses tlb bp_l1_tlb_miss_l2_tlb_miss.all L2 instruction TLB misses and instruction page walks 00l1_dtlb_misses tlb ls_l1_d_tlb_miss.all L1 data TLB misses 00l2_dtlb_misses tlb ls_l1_d_tlb_miss.all_l2_miss L2 data TLB misses and data page walks 00all_tlbs_flushed tlb ls_tlb_flush.all All TLBs flushed 00macro_ops_dispatched decoder de_src_op_disp.all Macro-ops dispatched 00sse_avx_stalls fp_disp_faults.sse_avx_all Mixed SSE/AVX stalls 00macro_ops_retired ex_ret_ops Macro-ops retired 00dram_read_data_for_local_processor data_fabric local_processor_read_data_beats_cs0 + local_processor_read_data_beats_cs1 + local_processor_read_data_beats_cs2 + local_processor_read_data_beats_cs3 + local_processor_read_data_beats_cs4 + local_processor_read_data_beats_cs5 + local_processor_read_data_beats_cs6 + local_processor_read_data_beats_cs7 + local_processor_read_data_beats_cs8 + local_processor_read_data_beats_cs9 + local_processor_read_data_beats_cs10 + local_processor_read_data_beats_cs11 DRAM read data for local processor 6.103515625e-5MiB 00dram_write_data_for_local_processor data_fabric local_processor_write_data_beats_cs0 + local_processor_write_data_beats_cs1 + local_processor_write_data_beats_cs2 + local_processor_write_data_beats_cs3 + local_processor_write_data_beats_cs4 + local_processor_write_data_beats_cs5 + local_processor_write_data_beats_cs6 + local_processor_write_data_beats_cs7 + local_processor_write_data_beats_cs8 + local_processor_write_data_beats_cs9 + local_processor_write_data_beats_cs10 + local_processor_write_data_beats_cs11 DRAM write data for local processor 6.103515625e-5MiB 00dram_read_data_for_remote_processor data_fabric remote_processor_read_data_beats_cs0 + remote_processor_read_data_beats_cs1 + remote_processor_read_data_beats_cs2 + remote_processor_read_data_beats_cs3 + remote_processor_read_data_beats_cs4 + remote_processor_read_data_beats_cs5 + remote_processor_read_data_beats_cs6 + remote_processor_read_data_beats_cs7 + remote_processor_read_data_beats_cs8 + remote_processor_read_data_beats_cs9 + remote_processor_read_data_beats_cs10 + remote_processor_read_data_beats_cs11 DRAM read data for remote processor 6.103515625e-5MiB 00dram_write_data_for_remote_processor data_fabric remote_processor_write_data_beats_cs0 + remote_processor_write_data_beats_cs1 + remote_processor_write_data_beats_cs2 + remote_processor_write_data_beats_cs3 + remote_processor_write_data_beats_cs4 + remote_processor_write_data_beats_cs5 + remote_processor_write_data_beats_cs6 + remote_processor_write_data_beats_cs7 + remote_processor_write_data_beats_cs8 + remote_processor_write_data_beats_cs9 + remote_processor_write_data_beats_cs10 + remote_processor_write_data_beats_cs11 DRAM write data for remote processor 6.103515625e-5MiB 00local_socket_upstream_dma_read_data data_fabric local_socket_upstream_read_beats_iom0 + local_socket_upstream_read_beats_iom1 + local_socket_upstream_read_beats_iom2 + local_socket_upstream_read_beats_iom3 Local socket upstream DMA read data 6.103515625e-5MiB 00local_socket_upstream_dma_write_data data_fabric local_socket_upstream_write_beats_iom0 + local_socket_upstream_write_beats_iom1 + local_socket_upstream_write_beats_iom2 + local_socket_upstream_write_beats_iom3 Local socket upstream DMA write data 6.103515625e-5MiB 00remote_socket_upstream_dma_read_data data_fabric remote_socket_upstream_read_beats_iom0 + remote_socket_upstream_read_beats_iom1 + remote_socket_upstream_read_beats_iom2 + remote_socket_upstream_read_beats_iom3 Remote socket upstream DMA read data 6.103515625e-5MiB 00remote_socket_upstream_dma_write_data data_fabric remote_socket_upstream_write_beats_iom0 + remote_socket_upstream_write_beats_iom1 + remote_socket_upstream_write_beats_iom2 + remote_socket_upstream_write_beats_iom3 Remote socket upstream DMA write data 6.103515625e-5MiB 00local_socket_inbound_data_to_cpu data_fabric local_socket_inf0_inbound_data_beats_ccm0 + local_socket_inf1_inbound_data_beats_ccm0 + local_socket_inf0_inbound_data_beats_ccm1 + local_socket_inf1_inbound_data_beats_ccm1 + local_socket_inf0_inbound_data_beats_ccm2 + local_socket_inf1_inbound_data_beats_ccm2 + local_socket_inf0_inbound_data_beats_ccm3 + local_socket_inf1_inbound_data_beats_ccm3 + local_socket_inf0_inbound_data_beats_ccm4 + local_socket_inf1_inbound_data_beats_ccm4 + local_socket_inf0_inbound_data_beats_ccm5 + local_socket_inf1_inbound_data_beats_ccm5 + local_socket_inf0_inbound_data_beats_ccm6 + local_socket_inf1_inbound_data_beats_ccm6 + local_socket_inf0_inbound_data_beats_ccm7 + local_socket_inf1_inbound_data_beats_ccm7 Local socket inbound data to the CPU (e.g. read data) 3.0517578125e-5MiB 00local_socket_outbound_data_from_cpu data_fabric local_socket_inf0_outbound_data_beats_ccm0 + local_socket_inf1_outbound_data_beats_ccm0 + local_socket_inf0_outbound_data_beats_ccm1 + local_socket_inf1_outbound_data_beats_ccm1 + local_socket_inf0_outbound_data_beats_ccm2 + local_socket_inf1_outbound_data_beats_ccm2 + local_socket_inf0_outbound_data_beats_ccm3 + local_socket_inf1_outbound_data_beats_ccm3 + local_socket_inf0_outbound_data_beats_ccm4 + local_socket_inf1_outbound_data_beats_ccm4 + local_socket_inf0_outbound_data_beats_ccm5 + local_socket_inf1_outbound_data_beats_ccm5 + local_socket_inf0_outbound_data_beats_ccm6 + local_socket_inf1_outbound_data_beats_ccm6 + local_socket_inf0_outbound_data_beats_ccm7 + local_socket_inf1_outbound_data_beats_ccm7 Local socket outbound data from the CPU (e.g. write data) 6.103515625e-5MiB 00remote_socket_inbound_data_to_cpu data_fabric remote_socket_inf0_inbound_data_beats_ccm0 + remote_socket_inf1_inbound_data_beats_ccm0 + remote_socket_inf0_inbound_data_beats_ccm1 + remote_socket_inf1_inbound_data_beats_ccm1 + remote_socket_inf0_inbound_data_beats_ccm2 + remote_socket_inf1_inbound_data_beats_ccm2 + remote_socket_inf0_inbound_data_beats_ccm3 + remote_socket_inf1_inbound_data_beats_ccm3 + remote_socket_inf0_inbound_data_beats_ccm4 + remote_socket_inf1_inbound_data_beats_ccm4 + remote_socket_inf0_inbound_data_beats_ccm5 + remote_socket_inf1_inbound_data_beats_ccm5 + remote_socket_inf0_inbound_data_beats_ccm6 + remote_socket_inf1_inbound_data_beats_ccm6 + remote_socket_inf0_inbound_data_beats_ccm7 + remote_socket_inf1_inbound_data_beats_ccm7 Remote socket inbound data to the CPU (e.g. read data) 3.0517578125e-5MiB 00remote_socket_outbound_data_from_cpu data_fabric remote_socket_inf0_outbound_data_beats_ccm0 + remote_socket_inf1_outbound_data_beats_ccm0 + remote_socket_inf0_outbound_data_beats_ccm1 + remote_socket_inf1_outbound_data_beats_ccm1 + remote_socket_inf0_outbound_data_beats_ccm2 + remote_socket_inf1_outbound_data_beats_ccm2 + remote_socket_inf0_outbound_data_beats_ccm3 + remote_socket_inf1_outbound_data_beats_ccm3 + remote_socket_inf0_outbound_data_beats_ccm4 + remote_socket_inf1_outbound_data_beats_ccm4 + remote_socket_inf0_outbound_data_beats_ccm5 + remote_socket_inf1_outbound_data_beats_ccm5 + remote_socket_inf0_outbound_data_beats_ccm6 + remote_socket_inf1_outbound_data_beats_ccm6 + remote_socket_inf0_outbound_data_beats_ccm7 + remote_socket_inf1_outbound_data_beats_ccm7 Remote socket outbound data from the CPU (e.g. write data) 6.103515625e-5MiB 00local_socket_outbound_data_from_all_links data_fabric local_socket_outbound_data_beats_link0 + local_socket_outbound_data_beats_link1 + local_socket_outbound_data_beats_link2 + local_socket_outbound_data_beats_link3 + local_socket_outbound_data_beats_link4 + local_socket_outbound_data_beats_link5 + local_socket_outbound_data_beats_link6 + local_socket_outbound_data_beats_link7 Outbound data from all links (local socket) 6.103515625e-5MiB 00umc_data_bus_utilization memory_controller d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk) Memory controller data bus utilization 100% 00umc_cas_cmd_rate memory_controller d_ratio(umc_cas_cmd.all * 1e3, umc_mem_clk) Memory controller CAS command rate 00umc_cas_cmd_read_ratio memory_controller d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all) Ratio of memory controller CAS commands for reads 100% 00umc_cas_cmd_write_ratio memory_controller d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all) Ratio of memory controller CAS commands for writes 100% 00umc_mem_read_bandwidth memory_controller umc_cas_cmd.rd * 64 / 1e6 / duration_time Estimated memory read bandwidth 1MB/s 00umc_mem_write_bandwidth memory_controller umc_cas_cmd.wr * 64 / 1e6 / duration_time Estimated memory write bandwidth 1MB/s 00umc_mem_bandwidth memory_controller umc_cas_cmd.all * 64 / 1e6 / duration_time Estimated combined memory bandwidth 1MB/s 00umc_activate_cmd_rate memory_controller d_ratio(umc_act_cmd.all * 1e3, umc_mem_clk) Memory controller ACTIVATE command rate 00umc_precharge_cmd_rate memory_controller d_ratio(umc_pchg_cmd.all * 1e3, umc_mem_clk) Memory controller PRECHARGE command rate 00total_dispatch_slots 8 * ls_not_halted_cyc Total dispatch slots (up to 8 instructions can be dispatched in each cycle) 1slots 00frontend_bound PipelineL1 d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots) Percentage of dispatch slots that remained unused because the frontend did not supply enough instructions/ops 100%slots 00bad_speculation PipelineL1 d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots) Percentage of dispatched ops that did not retire 100%ops 00backend_bound PipelineL1 d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots) Percentage of dispatch slots that remained unused because of backend stalls 100%slots 00smt_contention PipelineL1 d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots) Percentage of dispatch slots that remained unused because the other thread was selected 100%slots 00retiring PipelineL1 d_ratio(ex_ret_ops, total_dispatch_slots) Percentage of dispatch slots used by ops that retired 100%slots 00frontend_bound_by_latency PipelineL2;frontend_bound_group d_ratio(8 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x8@, total_dispatch_slots) Percentage of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses) 100%slots 00frontend_bound_by_bandwidth PipelineL2;frontend_bound_group d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - 8 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x8@, total_dispatch_slots) Percentage of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth) 100%slots 00bad_speculation_from_mispredicts PipelineL2;bad_speculation_group d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + bp_redirects.resync) Percentage of dispatched ops that were flushed due to branch mispredicts 100%ops 00bad_speculation_from_pipeline_restarts PipelineL2;bad_speculation_group d_ratio(bad_speculation * bp_redirects.resync, ex_ret_brn_misp + bp_redirects.resync) Percentage of dispatched ops that were flushed due to pipeline restarts (resyncs) 100%ops 00backend_bound_by_memory PipelineL2;backend_bound_group backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete) Percentage of dispatch slots that remained unused because of stalls due to the memory subsystem 100%slots 00backend_bound_by_cpu PipelineL2;backend_bound_group backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)) Percentage of dispatch slots that remained unused because of stalls not related to the memory subsystem 100%slots 00retiring_from_fastpath PipelineL2;retiring_group retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops)) Percentage of dispatch slots used by fastpath ops that retired 100%slots 00retiring_from_microcode PipelineL2;retiring_group retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops) Percentage of dispatch slots used by microcode ops that retired 100%slots 00branch_misprediction_rate branch_prediction d_ratio(ex_ret_brn_misp, ex_ret_brn) Execution-time branch misprediction rate (non-speculative) 1per_branch 00all_data_cache_accesses_pti l1_dcache ls_dispatch.all / instructions All data cache accesses per thousand instructions 1e3per_1k_instr 00all_l2_cache_accesses_pti l2_cache (l2_request_g1.all_no_prefetch + l2_pf_hit_l2.l2_hwpf + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions All L2 cache accesses per thousand instructions 1e3per_1k_instr 00l2_cache_accesses_from_l1_ic_misses_pti l2_cache l2_request_g1.cacheable_ic_read / instructions L2 cache accesses from L1 instruction cache misses (including prefetch) per thousand instructions 1e3per_1k_instr 00l2_cache_accesses_from_l1_dc_misses_pti l2_cache l2_request_g1.all_dc / instructions L2 cache accesses from L1 data cache misses (including prefetch) per thousand instructions 1e3per_1k_instr 00l2_cache_accesses_from_l2_hwpf_pti l2_cache (l2_pf_hit_l2.l1_dc_l2_hwpf + l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions L2 cache accesses from L2 cache hardware prefetcher per thousand instructions 1e3per_1k_instr 00all_l2_cache_misses_pti l2_cache (l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions All L2 cache misses per thousand instructions 1e3per_1k_instr 00l2_cache_misses_from_l1_ic_miss_pti l2_cache l2_cache_req_stat.ic_fill_miss / instructions L2 cache misses from L1 instruction cache misses per thousand instructions 1e3per_1k_instr 00l2_cache_misses_from_l1_dc_miss_pti l2_cache l2_cache_req_stat.ls_rd_blk_c / instructions L2 cache misses from L1 data cache misses per thousand instructions 1e3per_1k_instr 00l2_cache_misses_from_l2_hwpf_pti l2_cache (l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions L2 cache misses from L2 cache hardware prefetcher per thousand instructions 1e3per_1k_instr 00all_l2_cache_hits_pti l2_cache (l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.l2_hwpf) / instructions All L2 cache hits per thousand instructions 1e3per_1k_instr 00l2_cache_hits_from_l1_ic_miss_pti l2_cache l2_cache_req_stat.ic_hit_in_l2 / instructions L2 cache hits from L1 instruction cache misses per thousand instructions 1e3per_1k_instr 00l2_cache_hits_from_l1_dc_miss_pti l2_cache l2_cache_req_stat.dc_hit_in_l2 / instructions L2 cache hits from L1 data cache misses per thousand instructions 1e3per_1k_instr 00l2_cache_hits_from_l2_hwpf_pti l2_cache l2_pf_hit_l2.l1_dc_l2_hwpf / instructions L2 cache hits from L2 cache hardware prefetcher per thousand instructions 1e3per_1k_instr 00l3_read_miss_latency l3_cache l3_xi_sampled_latency.all * 10 / l3_xi_sampled_latency_requests.all Average L3 read miss latency (in core clocks) 1ns 00l3_read_miss_latency_for_local_dram l3_cache l3_xi_sampled_latency.dram_near * 10 / l3_xi_sampled_latency_requests.dram_near Average L3 read miss latency (in core clocks) for local DRAM 1ns 00l3_read_miss_latency_for_remote_dram l3_cache l3_xi_sampled_latency.dram_far * 10 / l3_xi_sampled_latency_requests.dram_far Average L3 read miss latency (in core clocks) for remote DRAM 1ns 00l1_data_cache_fills_from_memory_pti l1_dcache ls_any_fills_from_sys.dram_io_all / instructions L1 data cache fills from DRAM or MMIO in any NUMA node per thousand instructions 1e3per_1k_instr 00l1_data_cache_fills_from_remote_node_pti l1_dcache ls_any_fills_from_sys.far_all / instructions L1 data cache fills from a different NUMA node per thousand instructions 1e3per_1k_instr 00l1_data_cache_fills_from_same_ccx_pti l1_dcache ls_any_fills_from_sys.local_all / instructions L1 data cache fills from within the same CCX per thousand instructions 1e3per_1k_instr 00l1_data_cache_fills_from_different_ccx_pti l1_dcache ls_any_fills_from_sys.remote_cache / instructions L1 data cache fills from another CCX cache in any NUMA node per thousand instructions 1e3per_1k_instr 00all_l1_data_cache_fills_pti l1_dcache ls_any_fills_from_sys.all / instructions All L1 data cache fills per thousand instructions 1e3per_1k_instr 00l1_demand_data_cache_fills_from_local_l2_pti l1_dcache ls_dmnd_fills_from_sys.local_l2 / instructions L1 demand data cache fills from local L2 cache per thousand instructions 1e3per_1k_instr 00l1_demand_data_cache_fills_from_same_ccx_pti l1_dcache ls_dmnd_fills_from_sys.local_ccx / instructions L1 demand data cache fills from within the same CCX per thousand instructions 1e3per_1k_instr 00l1_demand_data_cache_fills_from_near_cache_pti l1_dcache ls_dmnd_fills_from_sys.near_cache / instructions L1 demand data cache fills from another CCX cache in the same NUMA node per thousand instructions 1e3per_1k_instr 00l1_demand_data_cache_fills_from_near_memory_pti l1_dcache ls_dmnd_fills_from_sys.dram_io_near / instructions L1 demand data cache fills from DRAM or MMIO in the same NUMA node per thousand instructions 1e3per_1k_instr 00l1_demand_data_cache_fills_from_far_cache_pti l1_dcache ls_dmnd_fills_from_sys.far_cache / instructions L1 demand data cache fills from another CCX cache in a different NUMA node per thousand instructions 1e3per_1k_instr 00l1_demand_data_cache_fills_from_far_memory_pti l1_dcache ls_dmnd_fills_from_sys.dram_io_far / instructions L1 demand data cache fills from DRAM or MMIO in a different NUMA node per thousand instructions 1e3per_1k_instr 00l1_itlb_misses_pti tlb (bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all) / instructions L1 instruction TLB misses per thousand instructions 1e3per_1k_instr 00l2_itlb_misses_pti tlb bp_l1_tlb_miss_l2_tlb_miss.all / instructions L2 instruction TLB misses and instruction page walks per thousand instructions 1e3per_1k_instr 00l1_dtlb_misses_pti tlb ls_l1_d_tlb_miss.all / instructions L1 data TLB misses per thousand instructions 1e3per_1k_instr 00l2_dtlb_misses_pti tlb ls_l1_d_tlb_miss.all_l2_miss / instructions L2 data TLB misses and data page walks per thousand instructions 1e3per_1k_instr 00all_tlbs_flushed_pti tlb ls_tlb_flush.all / instructions All TLBs flushed per thousand instructions 1e3per_1k_instr 00umc_cas_cmd_rate memory_controller d_ratio(umc_cas_cmd.all * 1e3, umc_mem_clk) Memory controller CAS command rate 1per_memclk 00umc_activate_cmd_rate memory_controller d_ratio(umc_act_cmd.all * 1e3, umc_mem_clk) Memory controller ACTIVATE command rate 1per_memclk 00umc_precharge_cmd_rate memory_controller d_ratio(umc_pchg_cmd.all * 1e3, umc_mem_clk) Memory controller PRECHARGE command rate 1per_memclk 00C3_Core_Residency Power cstate_core@c3\-residency@ / TSC C3 residency percent per core 100% 00tma_4k_aliasing TopdownL4;tma_L4_group;tma_l1_bound_group LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_thread_clks tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound) 100% 00tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_thread_slots tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 02tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY 100% 00tma_backend_bound BvOB;TmaL1;TopdownL1;tma_L1_group 1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring) tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound 100% TopdownL1 02tma_bad_speculation TmaL1;TopdownL1;tma_L1_group (UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_thread_slots tma_bad_speculation > 0.15 This category represents fraction of slots wasted due to incorrect speculations This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example 100% TopdownL1 00tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 100% TopdownL2 01tma_branch_resteers FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group 12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_thread_clks tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES 100% 00tma_cisc TopdownL4;tma_L4_group;tma_microcode_sequencer_group max(0, tma_microcode_sequencer - tma_assists) tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources 100% 02tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100% 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_core_bound Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group tma_backend_bound - tma_memory_bound tma_core_bound > 0.1 & tma_backend_bound > 0.2 This metric represents fraction of slots where Core non-memory issues were of a bottleneck This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations) 100% TopdownL2 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100% 03tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_core_clks / 2 tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100% 00tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% 00tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100% 00tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100% 00tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fb_full BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100% 01tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2 00tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group 4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END 100% TopdownL2 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P FP_ARITH_INST_RETIRED.SCALAR / UOPS_RETIRED.RETIRE_SLOTS tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P FP_ARITH_INST_RETIRED.VECTOR / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_frontend_bound BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound 100% TopdownL1 00tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group tma_microcode_sequencer tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .) 100% TopdownL2 00tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE.IFDATA_STALL / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses 100% 00tma_info_bad_spec_ipmisp_indirect Bad;BrMispredicts tma_info_inst_mix_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * BR_MISP_EXEC.INDIRECT) tma_info_bad_spec_ipmisp_indirect < 1e3 Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmispredict Bad;BadSpec;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES tma_info_bad_spec_ipmispredict < 200 Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate) 00tma_info_core_core_clks SMT (CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_thread_clks)) Core actual clocks when any Logical Processor is active on the Physical Core 00tma_info_core_coreipc Ret;SMT;TmaL1;tma_L1_group INST_RETIRED.ANY / tma_info_core_core_clks Instructions Per Cycle across hyper-threads (per physical core) 00tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_core_clks Floating Point Operations Per Cycle 00tma_info_core_fp_arith_utilization Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED.VECTOR) / (2 * tma_info_core_core_clks) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common) 00tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\,cmask\=1@ Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor) 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_inst_mix_iptb, tma_lcp 00tma_info_frontend_ipunknown_branch Fed tma_info_inst_mix_instructions / BACLEARS.ANY Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate) 00tma_info_inst_mix_bptkbranch Branches;Fed;PGO BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN Branch instructions per taken branch 00tma_info_inst_mix_instructions Summary;TmaL1;tma_L1_group INST_RETIRED.ANY Total number of retired Instructions Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST 00tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED.VECTOR) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW 00tma_info_inst_mix_iparith_avx128 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) tma_info_inst_mix_iparith_avx128 < 10 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_iparith_avx256 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) tma_info_inst_mix_iparith_avx256 < 10 Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_iparith_scalar_dp Flops;FpScalar;InsType INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE tma_info_inst_mix_iparith_scalar_dp < 10 Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_iparith_scalar_sp Flops;FpScalar;InsType INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE tma_info_inst_mix_iparith_scalar_sp < 10 Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_ipbranch Branches;Fed;InsType INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES tma_info_inst_mix_ipbranch < 8 Instructions per Branch (lower number means higher occurrence rate) 00tma_info_inst_mix_ipcall Branches;Fed;PGO INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL tma_info_inst_mix_ipcall < 200 Instructions per (near) call (lower number means higher occurrence rate) 00tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 00tma_info_inst_mix_ipload InsType INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS tma_info_inst_mix_ipload < 3 Instructions per Load (lower number means higher occurrence rate) 00tma_info_inst_mix_ipstore InsType INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES tma_info_inst_mix_ipstore < 8 Instructions per Store (lower number means higher occurrence rate) 00tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 9 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_lcp 00tma_info_memory_l1d_cache_fill_bw Mem;MemoryBW 64 * L1D.REPLACEMENT / 1e9 / duration_time Average per-thread data fill bandwidth to the L1 data cache [GB / sec] 00tma_info_memory_l1mpki CacheHits;Mem 1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY L1 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l2_cache_fill_bw Mem;MemoryBW 64 * L2_LINES_IN.ALL / 1e9 / duration_time Average per-thread data fill bandwidth to the L2 cache [GB / sec] 00tma_info_memory_l2hpki_all CacheHits;Mem 1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY L2 cache hits per kilo instruction for all request types (including speculative) 00tma_info_memory_l2hpki_load CacheHits;Mem 1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY L2 cache hits per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l2mpki Backend;CacheHits;Mem 1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY L2 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l2mpki_all CacheHits;Mem;Offcore 1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative) 00tma_info_memory_l2mpki_load CacheHits;Mem 1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l2mpki_rfo CacheMisses;Offcore 1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.ANY Offcore requests (L2 cache miss) per kilo instruction for demand RFOs 00tma_info_memory_l3_cache_fill_bw Mem;MemoryBW 64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time Average per-thread data fill bandwidth to the L3 cache [GB / sec] 00tma_info_memory_l3mpki Mem 1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY L3 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_latency_data_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Average Parallel L2 cache miss data reads 00tma_info_memory_latency_load_l2_miss_latency Memory_Lat;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD Average Latency for L2 cache miss demand Loads 00tma_info_memory_latency_load_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD Average Parallel L2 cache miss demand Loads 00tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB) Actual Average Latency for L1 data-cache miss demand load operations (in core cycles) 01tma_info_memory_mlp Mem;MemoryBW;MemoryBound L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor) 01tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / tma_info_core_core_clks tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_pipeline_execute Cor;Pipeline;PortsUtil;SMT UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC) Instruction-Level-Parallelism (average number of uops executed when there is execution) per core 00tma_info_pipeline_retire Pipeline;Ret UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\,cmask\=1@ Average number of Uops retired in cycles where at least one uop has retired 00tma_info_system_cpus_utilized Summary CPU_CLK_UNHALTED.REF_TSC / TSC Average number of utilized CPUs 00tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3 Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full 00tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width 00tma_info_system_ipfarbranch Branches;OS INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u tma_info_system_ipfarbranch < 1e6 Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate] 00tma_info_system_kernel_cpi OS CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k Cycles Per Instruction for the Operating System (OS) Kernel mode 00tma_info_system_kernel_utilization OS CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD tma_info_system_kernel_utilization > 0.05 Fraction of cycles spent in the Operating System (OS) Kernel mode 00tma_info_system_smt_2t_utilization SMT (1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0) Fraction of cycles where both hardware Logical Processors were active 00tma_info_system_turbo_utilization Power tma_info_thread_clks / CPU_CLK_UNHALTED.REF_TSC Average Frequency Utilization relative nominal frequency 00tma_info_thread_clks Pipeline CPU_CLK_UNHALTED.THREAD Per-Logical Processor actual clocks when the Logical Processor is active 00tma_info_thread_execute_per_issue Cor;Pipeline UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY The ratio of Executed- by Issued-Uops The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage 00tma_info_thread_ipc Ret;Summary INST_RETIRED.ANY / tma_info_thread_clks Instructions Per Cycle (per Logical Processor) 00tma_info_thread_slots TmaL1;tma_L1_group 4 * tma_info_core_core_clks Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward) 00tma_info_thread_uoppi Pipeline;Ret;Retire UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY tma_info_thread_uoppi > 1.05 Uops Per Instruction 00tma_info_thread_uptb Branches;Fed;FetchBW UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN tma_info_thread_uptb < 6 Uops per taken branch 00tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED 100% 00tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 data cache This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100% 00tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS 100% 00tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100% 03tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100% 01tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB ILD_STALL.LCP / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb 100% 00tma_light_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group tma_retiring - tma_heavy_operations tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation) This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .). Sample with: INST_RETIRED.PREC_DIST 100% TopdownL2 00tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100% 02tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency 100% 01tma_machine_clears BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn tma_bad_speculation - tma_branch_mispredicts tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100% TopdownL2 01tma_mem_bandwidth BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full 100% 00tma_mem_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 01tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 00tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost 100% 00tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_clks / 2 tma_mite > 0.1 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck 100% 00tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 2 * IDQ.MS_SWITCHES / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_2 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_core_clks tma_port_2 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2 100% 00tma_port_3 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_core_clks tma_port_3 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3 100% 00tma_port_4 TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group tma_store_op_utilization tma_port_4 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores 100% 00tma_port_5 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_core_clks tma_port_5 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_port_7 TopdownL6;tma_L6_group;tma_store_op_utilization_group UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_core_clks tma_port_7 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7 100% 00tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 01tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,inv\,cmask\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_core_clks) tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_core_clks) tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks) tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) 100% 00tma_retiring BvUW;TmaL1;TopdownL1;tma_L1_group UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS 100% TopdownL1 00tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS 100% 01tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group 2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100% 00tma_sq_full BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth 100% 00tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group RESOURCE_STALLS.SB / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS 100% 00tma_store_fwd_blk TopdownL4;tma_L4_group;tma_l1_bound_group 13 * LD_BLOCKS.STORE_FORWARD / tma_info_thread_clks tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading 100% 00tma_store_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 01tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_core_clks tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations 100% 00tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY 100% 00tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group INST_RETIRED.X87 * tma_info_thread_uoppi / UOPS_RETIRED.RETIRE_SLOTS tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100% 00tma_backend_bound BvOB;TmaL1;TopdownL1;tma_L1_group 1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring) tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100% TopdownL1 02tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 100% TopdownL2 01tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100% 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 03tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% 00tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100% 00tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100% 00tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2 00tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group 4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100% TopdownL2 00tma_frontend_bound BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS 100% TopdownL1 00tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE.IFDATA_STALL / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100% 00tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full 00tma_info_system_socket_clks SoC cbox_0@event\=0x0@ Socket actual clocks when any core is active on that socket 00tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS 100% 00tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 data cache This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100% 00tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS 100% 00tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100% 03tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100% 01tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10 100% 02tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100% 01tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 00tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost 100% 00tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_clks / 2 tma_mite > 0.1 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100% 00tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_2 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_core_clks tma_port_2 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) 100% 00tma_port_3 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_core_clks tma_port_3 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) 100% 00tma_port_4 TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group tma_store_op_utilization tma_port_4 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Related metrics: tma_split_stores 100% 00tma_port_5 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_core_clks tma_port_5 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_port_7 TopdownL6;tma_L6_group;tma_store_op_utilization_group UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_core_clks tma_port_7 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_core_clks) tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks) tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100% 00tma_retiring BvUW;TmaL1;TopdownL1;tma_L1_group UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS 100% TopdownL1 00tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100% 01tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group 2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100% 00tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group RESOURCE_STALLS.SB / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS 100% 00tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_core_clks tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8 100% 00tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH 100% 00cpi CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles 1per_instr 00cpu_operating_frequency CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 CPU operating frequency (in GHz) 1GHz 00cpu_utilization tma_info_system_cpus_utilized Percentage of time spent in the active CPU power state C0 100% 00dtlb_load_mpi DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr 00dtlb_store_mpi DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr 00io_bandwidth_read cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x19e@ * 64 / 1e6 / duration_time Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU 1MB/s 00io_bandwidth_write (cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x1c8\,filter_tid\=0x3e@ + cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x180\,filter_tid\=0x3e@) * 64 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00itlb_large_page_mpi ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB 1per_instr 00itlb_mpi ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB 1per_instr 00l1_i_code_read_misses_with_prefetches_per_instr L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions 1per_instr 00l1d_demand_data_read_hits_per_instr MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions 1per_instr 00l1d_mpi L1D.REPLACEMENT / INST_RETIRED.ANY Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions 1per_instr 00l2_demand_code_mpi L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY Ratio of number of code read request missing L2 cache to the total number of completed instructions 1per_instr 00l2_demand_data_read_hits_per_instr MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions 1per_instr 00l2_demand_data_read_mpi MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY Ratio of number of completed data read request missing L2 cache to the total number of completed instructions 1per_instr 00l2_mpi L2_LINES_IN.ALL / INST_RETIRED.ANY Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions 1per_instr 00llc_code_read_mpi_demand_plus_prefetch (cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x191@) / INST_RETIRED.ANY Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_data_read_demand_plus_prefetch_miss_latency 1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\,filter_opc\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests 1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests 1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\,filter_opc\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds 1ns 00llc_data_read_mpi_demand_plus_prefetch (cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x192@) / INST_RETIRED.ANY Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00loads_per_instr MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY The ratio of number of completed memory load instructions to the total number completed instructions 1per_instr 00memory_bandwidth_read UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time DDR memory read bandwidth (MB/sec) 1MB/s 00memory_bandwidth_total (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time DDR memory bandwidth (MB/sec) 1MB/s 00memory_bandwidth_write UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time DDR memory write bandwidth (MB/sec) 1MB/s 00numa_reads_addressed_to_local_dram cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@) Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00numa_reads_addressed_to_remote_dram cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@) Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00percent_uops_delivered_from_decoded_icache IDQ.DSB_UOPS / UOPS_ISSUED.ANY Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue 100% 00percent_uops_delivered_from_legacy_decode_pipeline IDQ.MITE_UOPS / UOPS_ISSUED.ANY Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue 100% 00percent_uops_delivered_from_loop_stream_detector LSD.UOPS / UOPS_ISSUED.ANY Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue 100% 00percent_uops_delivered_from_microcode_sequencer IDQ.MS_UOPS / UOPS_ISSUED.ANY Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue 100% 00qpi_data_transmit_bw UNC_Q_TxL_FLITS_G0.DATA * 8 / 1e6 / duration_time Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec) 1MB/s 00stores_per_instr MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY The ratio of number of completed memory store instructions to the total number completed instructions 1per_instr 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\=0x182\,thresh\=1@ Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\=0x182@) / (tma_info_system_socket_clks / duration_time) Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 00tma_info_system_uncore_frequency SoC tma_info_system_socket_clks / 1e9 / duration_time Measured Average Uncore Frequency for the SoC [GHz] 00tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100% 01tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group 200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS 100% 00tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100% 01tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS 100% 00uncore_frequency UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time Uncore operating frequency in GHz 1GHz 00dtlb_2mb_large_page_load_mpi DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB 1per_instr 00io_bandwidth_read (UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e6 / duration_time Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU 1MB/s 00io_bandwidth_write (UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3) * 4 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00l1d_demand_data_read_hits_per_instr MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions 1per_instr 00l2_demand_data_read_hits_per_instr MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions 1per_instr 00l2_demand_data_read_mpi MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY Ratio of number of completed data read request missing L2 cache to the total number of completed instructions 1per_instr 00llc_code_read_mpi_demand_plus_prefetch cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x12cc0233@ / INST_RETIRED.ANY Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_data_read_demand_plus_prefetch_miss_latency 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40433@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40433@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40432@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40431@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds 1ns 00llc_data_read_mpi_demand_plus_prefetch cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x12d40433@ / INST_RETIRED.ANY Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_miss_local_memory_bandwidth_read UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory 1MB/s 00llc_miss_local_memory_bandwidth_write UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory 1MB/s 00llc_miss_remote_memory_bandwidth_read UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory 1MB/s 00llc_miss_remote_memory_bandwidth_write UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory 1MB/s 00loads_per_instr MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY The ratio of number of completed memory load instructions to the total number completed instructions 1per_instr 00numa_reads_addressed_to_local_dram cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@ / (cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@ + cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@) Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00numa_reads_addressed_to_remote_dram cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@ / (cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@ + cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@) Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00percent_uops_delivered_from_decoded_icache IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS) Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue 100% 00percent_uops_delivered_from_legacy_decode_pipeline IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS) Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue 100% 00percent_uops_delivered_from_microcode_sequencer IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS) Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue 100% 00pmem_memory_bandwidth_read UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec) 1MB/s 00pmem_memory_bandwidth_total (UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec) 1MB/s 00pmem_memory_bandwidth_write UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec) 1MB/s 00stores_per_instr MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY The ratio of number of completed memory store instructions to the total number completed instructions 1per_instr 00tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_thread_slots tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 00tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 34 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY 100% 00tma_backend_bound BvOB;TmaL1;TopdownL1;tma_L1_group 1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_thread_slots tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound 100% TopdownL1 00tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 100% TopdownL2 01tma_branch_resteers FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks + tma_unknown_branches tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES 100% 00tma_cisc TopdownL4;tma_L4_group;tma_microcode_sequencer_group max(0, tma_microcode_sequencer - tma_assists) tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources 100% 00tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC (1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100% 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) + 44 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_decoder0_alone DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group (cpu@INST_DECODED.DECODERS\,cmask\=1@ - cpu@INST_DECODED.DECODERS\,cmask\=2@) / tma_info_core_core_clks / 2 tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & tma_fetch_bandwidth > 0.2) This metric represents fraction of cycles where decoder-0 was the only active decoder This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions 100% 00tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group ARITH.DIVIDER_ACTIVE / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound - tma_pmm_bound if #has_pmem > 0 else CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound) tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 01tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2 tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100% 00tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% 00tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization 100% 02tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (9 * cpu@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization 100% 00tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (110 * tma_info_system_core_frequency * (OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_info_system_core_frequency * (OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_fb_full BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100% 02tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2 00tma_few_uops_instructions TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0 tma_heavy_operations - tma_microcode_sequencer tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone 100% 02tma_fp_arith HPC;TopdownL3;tma_L3_group;tma_light_operations_group tma_x87_use + tma_fp_scalar + tma_fp_vector tma_fp_arith > 0.2 & tma_light_operations > 0.6 This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired) This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of "Uops" CountDomain and FMA double-counting 100% 01tma_fp_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 34 * FP_ASSIST.ANY / tma_info_thread_slots tma_fp_assists > 0.1 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals) 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@ / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 01tma_fp_vector_512b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fused_instructions Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS tma_fused_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)} 100% 00tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group (UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / tma_info_thread_slots tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .) 100% TopdownL2 00tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group (ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@) / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100% 00tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM tma_info_bottleneck_mispredictions * tma_info_thread_slots / BR_MISP_RETIRED.ALL_BRANCHES / 100 Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 00tma_info_bad_spec_spec_clears_ratio BrMispredicts INT_MISC.CLEARS_COUNT / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) Speculative to Retired ratio of all clears (covering mispredicts and nukes) 00tma_info_botlnk_l0_core_bound_likely Cor;SMT (100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0) tma_info_botlnk_l0_core_bound_likely > 0.5 Probability of Core Bound bottleneck hidden by SMT-profiling artifacts 01tma_info_botlnk_l2_dsb_bandwidth DSB;FetchBW;tma_issueFB 100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite))) tma_info_botlnk_l2_dsb_bandwidth > 10 Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 00tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 01tma_info_bottleneck_big_code BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB 100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) tma_info_bottleneck_big_code > 20 Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses) 01tma_info_bottleneck_branching_overhead BvBO;Ret 100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots) tma_info_bottleneck_branching_overhead > 5 Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound) 00tma_info_bottleneck_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_info_bottleneck_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full 00tma_info_bottleneck_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_info_bottleneck_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency 00tma_info_bottleneck_instruction_fetch_bw BvFB;Fed;FetchBW;Frontend 100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code tma_info_bottleneck_instruction_fetch_bw > 20 Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end) 01tma_info_bottleneck_irregular_overhead Bad;BvIO;Cor;Ret;tma_issueMS 100 * (tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_info_bottleneck_irregular_overhead > 10 Total pipeline cost of irregular execution (e.g Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches 00tma_info_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization 01tma_info_bottleneck_memory_synchronization BvMS;Mem;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_info_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs 00tma_info_bottleneck_mispredictions Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM 100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_info_bottleneck_mispredictions > 20 Total pipeline cost of Branch Misprediction related bottlenecks Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 01tma_info_bottleneck_useful_work BvUW;Ret 100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_info_bottleneck_useful_work > 20 Total pipeline cost of "useful operations" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead 00tma_info_branches_callret Bad;Branches (BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are CALL or RET 00tma_info_branches_cond_nt Bad;Branches;CodeGen;PGO BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are non-taken conditionals 00tma_info_branches_cond_tk Bad;Branches;CodeGen;PGO (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are taken conditionals 00tma_info_branches_jump Bad;Branches (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.COND - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are unconditional (direct or indirect) jumps 01tma_info_core_epc Power UOPS_EXECUTED.THREAD / tma_info_thread_clks uops Executed per Cycle 00tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_core_clks Floating Point Operations Per Cycle 01tma_info_core_fp_arith_utilization Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@) / (2 * tma_info_core_core_clks) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common) 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp 00tma_info_frontend_dsb_switch_cost DSBmiss DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details 00tma_info_frontend_fetch_upc Fed;FetchBW UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\,cmask\=1@ Average number of Uops issued by front-end when it issued something 00tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ + 2 Average Latency for L1 instruction cache misses 00tma_info_frontend_ipdsb_miss_ret DSBmiss;Fed INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS tma_info_frontend_ipdsb_miss_ret < 50 Instructions per non-speculative DSB miss (lower number means higher occurrence rate) 00tma_info_frontend_l2mpki_code IcMiss 1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY L2 cache true code cacheline misses per kilo instruction 00tma_info_frontend_l2mpki_code_all IcMiss 1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY L2 cache speculative code cacheline misses per kilo instruction 00tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW 01tma_info_inst_mix_iparith_avx512 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) tma_info_inst_mix_iparith_avx512 < 10 Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 01tma_info_inst_mix_ipload InsType INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS tma_info_inst_mix_ipload < 3 Instructions per Load (lower number means higher occurrence rate) 00tma_info_inst_mix_ippause Flops;FpVector;InsType tma_info_inst_mix_instructions / ROB_MISC_EVENTS.PAUSE_INST Instructions per PAUSE (lower number means higher occurrence rate) 00tma_info_inst_mix_ipstore InsType INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES tma_info_inst_mix_ipstore < 8 Instructions per Store (lower number means higher occurrence rate) 00tma_info_inst_mix_ipswpf Prefetches INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\,umask\=0xF@ tma_info_inst_mix_ipswpf < 100 Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate) 00tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 9 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp 00tma_info_memory_core_l2_evictions_nonsilent_pki L2Evicts;Mem;Server 1e3 * L2_LINES_OUT.NON_SILENT / tma_info_inst_mix_instructions Rate of non silent evictions from the L2 cache per Kilo instruction 00tma_info_memory_core_l2_evictions_silent_pki L2Evicts;Mem;Server 1e3 * L2_LINES_OUT.SILENT / tma_info_inst_mix_instructions Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory) 00tma_info_memory_fb_hpki CacheHits;Mem 1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries) 00tma_info_memory_l1mpki CacheHits;Mem 1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY L1 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l1mpki_load CacheHits;Mem 1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY L1 cache true misses per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l2mpki Backend;CacheHits;Mem 1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY L2 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l3_cache_access_bw Mem;MemoryBW;Offcore 64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time Average per-thread data access bandwidth to the L3 cache [GB / sec] 00tma_info_memory_l3mpki Mem 1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY L3 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT) Actual Average Latency for L1 data-cache miss demand load operations (in core cycles) 00tma_info_memory_mix_uc_load_pki Mem 1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY Un-cacheable retired load per kilo instruction 00tma_info_memory_mlp Mem;MemoryBW;MemoryBound L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor) 00tma_info_memory_tlb_code_stlb_mpki Fed;MemoryTLB 1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_tlb_load_stlb_mpki Mem;MemoryTLB 1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 02tma_info_memory_tlb_store_stlb_mpki Mem;MemoryTLB 1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_pipeline_execute Cor;Pipeline;PortsUtil;SMT UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\,cmask\=1@) Instruction-Level-Parallelism (average number of uops executed when there is execution) per core 00tma_info_pipeline_fetch_dsb Fed;FetchBW IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY Average number of uops fetched from DSB per cycle 00tma_info_pipeline_fetch_mite Fed;FetchBW IDQ.MITE_UOPS / IDQ.MITE_CYCLES Average number of uops fetched from MITE per cycle 00tma_info_pipeline_ipassist MicroSeq;Pipeline;Ret;Retire INST_RETIRED.ANY / (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) tma_info_pipeline_ipassist < 100e3 Instructions per a microcode Assist invocation Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate) 00tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_mem_bandwidth, tma_sq_full 00tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width 01tma_info_system_io_read_bw IoBW;MemOffcore;Server;SoC (UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / duration_time Average IO (network or disk) Bandwidth Use for Reads [GB / sec] Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU 00tma_info_system_io_write_bw IoBW;MemOffcore;Server;SoC (UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time Average IO (network or disk) Bandwidth Use for Writes [GB / sec] Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 00tma_info_system_mem_dram_read_latency MemOffcore;MemoryLat;Server;SoC 1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\=0x0@ Average latency of data read request to external DRAM memory [in nanoseconds] Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\=1@ Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches 00tma_info_system_mem_pmm_read_latency MemOffcore;MemoryLat;Server;SoC (1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS) / imc_0@event\=0x0@ if #has_pmem > 0 else 0) Average latency of data read request to external 3D X-Point memory [in nanoseconds] Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (tma_info_system_socket_clks / duration_time) Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 00tma_info_system_pmm_read_bw MemOffcore;MemoryBW;Server;SoC (64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0) Average 3DXP Memory Bandwidth Use for reads [GB / sec] 00tma_info_system_pmm_write_bw MemOffcore;MemoryBW;Server;SoC (64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0) Average 3DXP Memory Bandwidth Use for Writes [GB / sec] 00tma_info_system_power_license0_utilization Power (CORE_POWER.LVL0_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_core_clks) Fraction of Core cycles where the core was running with power-delivery for baseline license level 0 Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes 00tma_info_system_power_license1_utilization Power (CORE_POWER.LVL1_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_core_clks) tma_info_system_power_license1_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 1 Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions 00tma_info_system_power_license2_utilization Power (CORE_POWER.LVL2_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_core_clks) tma_info_system_power_license2_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX) Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions 00tma_info_system_socket_clks SoC cha_0@event\=0x0@ Socket actual clocks when any core is active on that socket 00tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE_TAG.STALLS / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS 100% 00tma_l1_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT 100% 00tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks) tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS 100% 01tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100% 00tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 17 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency 100% 00tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DECODE.LCP / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb 100% 00tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100% 00tma_load_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group tma_dtlb_load - tma_load_stlb_miss tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB) 100% 02tma_load_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_thread_clks tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk 100% 00tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group 59.5 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM 100% 00tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100% 00tma_mem_bandwidth BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full 100% 00tma_mem_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_latency 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 01tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses 100% 00tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 02tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions 100% 00tma_mixing_vectors TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY tma_mixing_vectors > 0.05 This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles) This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches 100% 00tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 2 * IDQ.MS_SWITCHES / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_non_fused_branches Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS tma_non_fused_branches > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused 100% 00tma_nop_instructions BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6) This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP 100% 00tma_other_light_ops Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches)) tma_other_light_ops > 0.3 & tma_light_operations > 0.6 This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting 100% 00tma_other_mispredicts BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_branch_mispredicts_group max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001) tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types) 100% 00tma_other_nukes BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT), 0.0001) tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering 100% 00tma_pmm_bound MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0) tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module 100% 01tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((tma_ports_utilized_0 * tma_info_thread_clks + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 00tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group EXE_ACTIVITY.EXE_BOUND_0_PORTS / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / tma_info_core_core_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_core_core_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_core_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) 100% 00tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (89.5 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 89.5 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100% 02tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 127 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS 100% 00tma_serializing_operation BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_thread_clks tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100% 00tma_slow_pause TopdownL4;tma_L4_group;tma_serializing_operation_group 40 * ROB_MISC_EVENTS.PAUSE_INST / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST 100% 00tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100% 02tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100% 00tma_sq_full BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth 100% 00tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group EXE_ACTIVITY.BOUND_ON_STORES / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS 100% 00tma_store_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 02tma_store_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_core_clks tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk 100% 00tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group 9 * BACLEARS.ANY / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY 100% 00tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00uncore_frequency UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time Uncore operating frequency in GHz 1GHz 00upi_data_receive_bw UNC_UPI_RxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec) 1MB/s 00upi_data_transmit_bw UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec) 1MB/s 00IoBW LLC_MISSES.PCIE_READ UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus 4Bytes 00LLC_MISSES.PCIE_WRITE UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus 4Bytes 00UNC_M_PMM_BANDWIDTH.TOTAL UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts 6.103515625E-5MB/sec 00UNC_M_PMM_READ_LATENCY UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all 6000000000ns 00power_channel_ppd UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS * 100 Cycles where DRAM ranks are in power down (CKE) mode+C37 Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of 00power_self_refresh UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS * 100 Cycles Memory is in self refresh power mode Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases 00IPC INST_RETIRED.ANY / cycles Instructions Per Cycle (per Logical Processor) 00CPI 1 / IPC Cycles Per Instruction (per Logical Processor) 00CLKS cycles Per-Logical Processor actual clocks when the Logical Processor is active 00IpMispredict INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES Number of Instructions per non-speculative Branch Misprediction (JEClear) 00IpBranch INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES Instructions per Branch (lower number means higher occurrence rate) 00Instructions INST_RETIRED.ANY Total number of retired Instructions 00L3_Cache_Fill_BW 64 * LONGEST_LAT_CACHE.MISS / 1e9 Average per-core data fill bandwidth to the L3 cache [GB / sec] 00CPU_Utilization CPU_CLK_UNHALTED.REF_TSC / msr@tsc@ Average CPU Utilization 00Average_Frequency cycles / CPU_CLK_UNHALTED.REF_TSC * msr@tsc@ / 1e9 Measured Average Frequency for unhalted processors [GHz] 00Turbo_Utilization cycles / CPU_CLK_UNHALTED.REF_TSC Average Frequency Utilization relative nominal frequency 00Kernel_Utilization cycles:k / cycles Fraction of cycles spent in the Operating System (OS) Kernel mode 00dtlb_2nd_level_2mb_large_page_load_mpi DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB 1per_instr 00dtlb_2nd_level_load_mpi DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr 00dtlb_2nd_level_store_mpi DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr 00iio_bandwidth_read UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1e6 / duration_time Bandwidth observed by the integrated I/O traffic controller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU 1MB/s 00iio_bandwidth_write UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS * 4 / 1e6 / duration_time Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00io_bandwidth_read UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / duration_time Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU 1MB/s 00io_bandwidth_read_local UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1e6 / duration_time Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket 1MB/s 00io_bandwidth_read_remote UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1e6 / duration_time Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket 1MB/s 00io_bandwidth_write (UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00io_bandwidth_write_local (UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL) * 64 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket 1MB/s 00io_bandwidth_write_remote (UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE) * 64 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket 1MB/s 00io_percent_of_inbound_full_writes_that_miss_l3 UNC_CHA_TOR_INSERTS.IO_MISS_ITOM / UNC_CHA_TOR_INSERTS.IO_ITOM Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache 100% 00io_percent_of_inbound_partial_writes_that_miss_l3 (UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_RFO) / (UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_RFO) Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache 100% 00io_percent_of_inbound_reads_that_miss_l3 UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR / UNC_CHA_TOR_INSERTS.IO_PCIRDCUR Percentage of inbound reads initiated by end device controllers that miss the L3 cache 100% 00itlb_2nd_level_large_page_mpi ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB 1per_instr 00itlb_2nd_level_mpi ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB 1per_instr 00llc_code_read_mpi_demand_plus_prefetch UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_data_read_mpi_demand_plus_prefetch (UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_demand_data_read_miss_latency 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds 1ns 00llc_demand_data_read_miss_latency_for_local_requests 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds 1ns 00llc_demand_data_read_miss_latency_for_remote_requests 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds 1ns 00llc_demand_data_read_miss_to_dram_latency 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds 1ns 00llc_demand_data_read_miss_to_pmem_latency 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds 1ns 00memory_extra_write_bw_due_to_directory_updates (UNC_CHA_DIR_UPDATE.HA + UNC_CHA_DIR_UPDATE.TOR + UNC_M2M_DIRECTORY_UPDATE.ANY) * 64 / 1e6 / duration_time Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM) 1MB/s 00numa_reads_addressed_to_local_dram (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00numa_reads_addressed_to_remote_dram (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * tma_info_core_core_clks) tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 00tma_amx_busy BvCB;Compute;HPC;Server;TopdownL3;tma_L3_group;tma_core_bound_group EXE.AMX_BUSY / tma_info_core_core_clks tma_amx_busy > 0.5 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations 100% 00tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 78 * ASSISTS.ANY / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100% 00tma_avx_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 63 * ASSISTS.SSE_AVX_MIX / tma_info_thread_slots tma_avx_assists > 0.1 This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists 100% 00tma_backend_bound BvOB;Default;TmaL1;TopdownL1;tma_L1_group topdown\-be\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100% TopdownL1;Default TopdownL1 00tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;Default;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM topdown\-br\-mispredict / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 100% TopdownL2;Default TopdownL2 00tma_c01_wait C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group CPU_CLK_UNHALTED.C01 / tma_info_thread_clks tma_c01_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings) 100% 00tma_c02_wait C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group CPU_CLK_UNHALTED.C02 / tma_info_thread_clks tma_c02_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings) 100% 00tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC (1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100% 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (76.6 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 74.6 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_core_bound Backend;Compute;Default;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group max(0, tma_backend_bound - tma_memory_bound) tma_core_bound > 0.1 & tma_backend_bound > 0.2 This metric represents fraction of slots where Core non-memory issues were of a bottleneck This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations) 100% TopdownL2;Default TopdownL2 00tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 74.6 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group ARITH.DIV_ACTIVE / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 00tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization 100% 00tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (7 * cpu@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization 100% 00tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 81 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fb_full BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group L1D_PEND_MISS.FB_FULL / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100% 00tma_fetch_bandwidth Default;FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB max(0, tma_frontend_bound - tma_fetch_latency) tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2;Default TopdownL2 00tma_fetch_latency Default;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group topdown\-fetch\-lat / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) - INT_MISC.UOP_DROPPING / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100% TopdownL2;Default TopdownL2 00tma_fp_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 30 * ASSISTS.FP / tma_info_thread_slots tma_fp_assists > 0.1 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals) 100% 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR) / (tma_retiring * tma_info_thread_slots) tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_INST_RETIRED2.VECTOR) / (tma_retiring * tma_info_thread_slots) tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_512b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_frontend_bound BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group topdown\-fe\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) - INT_MISC.UOP_DROPPING / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS 100% TopdownL1;Default TopdownL1 00tma_fused_instructions Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * INST_RETIRED.MACRO_FUSED / (tma_retiring * tma_info_thread_slots) tma_fused_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)} 100% 00tma_heavy_operations Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group topdown\-heavy\-ops / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .) 100% TopdownL2;Default TopdownL2 00tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE_DATA.STALLS / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100% 00tma_info_bad_spec_ipmisp_cond_ntaken Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN tma_info_bad_spec_ipmisp_cond_ntaken < 200 Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_cond_taken Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN tma_info_bad_spec_ipmisp_cond_taken < 200 Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_indirect Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT tma_info_bad_spec_ipmisp_indirect < 1e3 Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_ret Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.RET tma_info_bad_spec_ipmisp_ret < 500 Instructions per retired mispredicts for return branches (lower number means higher occurrence rate) 00tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 00tma_info_bottleneck_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_store_fwd_blk + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_fb_full))) tma_info_bottleneck_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full 00tma_info_bottleneck_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound)) * (tma_store_latency / (tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store)) + tma_memory_bound * (tma_l1_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound)) * (tma_l1_hit_latency / (tma_dtlb_load + tma_store_fwd_blk + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_fb_full))) tma_info_bottleneck_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency 00tma_info_bottleneck_compute_bound_est BvCB;Cor;tma_issueComp 100 * (tma_core_bound * tma_divider / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * tma_amx_busy / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m))) tma_info_bottleneck_compute_bound_est > 20 Total pipeline cost when the execution is compute-bound - an estimation Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics: 00tma_info_bottleneck_instruction_fetch_bw BvFB;Fed;FetchBW;Frontend 100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - (1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\,cmask\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))) - tma_info_bottleneck_big_code tma_info_bottleneck_instruction_fetch_bw > 20 Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end) 00tma_info_bottleneck_irregular_overhead Bad;BvIO;Cor;Ret;tma_issueMS 100 * ((1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\,cmask\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + cpu@RS.EMPTY\,umask\=1@ / tma_info_thread_clks * tma_ports_utilized_0) / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_info_bottleneck_irregular_overhead > 10 Total pipeline cost of irregular execution (e.g Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches 00tma_info_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_store_fwd_blk + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_fb_full)) + tma_memory_bound * (tma_store_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound)) * (tma_dtlb_store / (tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization 00tma_info_bottleneck_memory_synchronization BvMS;Mem;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_dram_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_mem + tma_remote_cache) + tma_l3_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound) * tma_false_sharing / (tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_info_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs 00tma_info_branches_cond_nt Bad;Branches;CodeGen;PGO BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are non-taken conditionals 00tma_info_branches_cond_tk Bad;Branches;CodeGen;PGO BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are taken conditionals 00tma_info_branches_jump Bad;Branches (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are unconditional (direct or indirect) jumps 00tma_info_core_core_clks SMT (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else tma_info_thread_clks) Core actual clocks when any Logical Processor is active on the Physical Core 00tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / tma_info_core_core_clks Floating Point Operations Per Cycle 00tma_info_core_fp_arith_utilization Cor;Flops;HPC (FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * tma_info_core_core_clks) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common) 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / UOPS_ISSUED.ANY tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp 00tma_info_frontend_dsb_switch_cost DSBmiss DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\,cmask\=1\,edge@ Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details 00tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss ICACHE_DATA.STALLS / cpu@ICACHE_DATA.STALLS\,cmask\=1\,edge@ Average Latency for L1 instruction cache misses 00tma_info_frontend_unknown_branch_cost Fed INT_MISC.UNKNOWN_BRANCH_CYCLES / cpu@INT_MISC.UNKNOWN_BRANCH_CYCLES\,cmask\=1\,edge@ Average number of cycles the front-end was delayed due to an Unknown Branch detection Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node 00tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR + (FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_INST_RETIRED2.VECTOR)) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW 00tma_info_inst_mix_iparith_avx128 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) tma_info_inst_mix_iparith_avx128 < 10 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_iparith_avx256 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) tma_info_inst_mix_iparith_avx256 < 10 Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_iparith_avx512 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) tma_info_inst_mix_iparith_avx512 < 10 Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_iparith_scalar_hp Flops;FpScalar;InsType;Server INST_RETIRED.ANY / FP_ARITH_INST_RETIRED2.SCALAR tma_info_inst_mix_iparith_scalar_hp < 10 Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting 00tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 00tma_info_inst_mix_ippause Flops;FpVector;InsType tma_info_inst_mix_instructions / CPU_CLK_UNHALTED.PAUSE_INST Instructions per PAUSE (lower number means higher occurrence rate) 00tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 13 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp 00tma_info_memory_l2mpki_rfo CacheMisses;Offcore 1e3 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY Offcore requests (L2 cache miss) per kilo instruction for demand RFOs 00tma_info_memory_latency_data_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Average Parallel L2 cache miss data reads 00tma_info_memory_latency_load_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\,cmask\=1@ Average Parallel L2 cache miss demand Loads 00tma_info_memory_latency_load_l3_miss_latency Memory_Lat;Offcore OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD Average Latency for L3 cache miss demand Loads 00tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY Actual Average Latency for L1 data-cache miss demand load operations (in core cycles) 00tma_info_memory_mix_bus_lock_pki Mem 1e3 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY "Bus lock" per kilo instruction 00tma_info_memory_mix_offcore_mwrite_any_pki Offcore 1e3 * OCR.MODIFIED_WRITE.ANY_RESPONSE / tma_info_inst_mix_instructions Off-core accesses per kilo instruction for modified write requests 00tma_info_memory_mix_offcore_read_any_pki CacheHits;Offcore 1e3 * OCR.READS_TO_CORE.ANY_RESPONSE / tma_info_inst_mix_instructions Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches) 00tma_info_memory_mix_offcore_read_l3m_pki Offcore 1e3 * OCR.READS_TO_CORE.L3_MISS / tma_info_inst_mix_instructions L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches) 00tma_info_memory_soc_r2c_dram_bw HPC;Mem;MemoryBW;SoC 64 * OCR.READS_TO_CORE.DRAM / 1e9 / duration_time Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW 00tma_info_memory_soc_r2c_l3m_bw HPC;Mem;MemoryBW;SoC 64 * OCR.READS_TO_CORE.L3_MISS / 1e9 / duration_time Average L3-cache miss BW for Reads-to-Core (R2C) Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW 00tma_info_memory_soc_r2c_offcore_bw HPC;Mem;MemoryBW;SoC 64 * OCR.READS_TO_CORE.ANY_RESPONSE / 1e9 / duration_time Average Off-core access BW for Reads-to-Core (R2C) Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_pipeline_fetch_mite Fed;FetchBW IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY Average number of uops fetched from MITE per cycle 00tma_info_pipeline_ipassist MicroSeq;Pipeline;Ret;Retire INST_RETIRED.ANY / ASSISTS.ANY tma_info_pipeline_ipassist < 100e3 Instructions per a microcode Assist invocation Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate) 00tma_info_pipeline_retire Pipeline;Ret tma_retiring * tma_info_thread_slots / cpu@UOPS_RETIRED.SLOTS\,cmask\=1@ Average number of Uops retired in cycles where at least one uop has retired 00tma_info_pipeline_strings_cycles MicroSeq;Pipeline;Ret INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\,cmask\=1@ tma_info_pipeline_strings_cycles > 0.1 Estimated fraction of retirement-cycles dealing with repeat instructions 00tma_info_system_c0_wait C0Wait CPU_CLK_UNHALTED.C0_WAIT / tma_info_thread_clks tma_info_system_c0_wait > 0.05 Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states 00tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width 00tma_info_system_io_read_bw IoBW;MemOffcore;Server;SoC UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time Average IO (network or disk) Bandwidth Use for Reads [GB / sec] Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU 00tma_info_system_io_write_bw IoBW;MemOffcore;Server;SoC (UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e9 / duration_time Average IO (network or disk) Bandwidth Use for Writes [GB / sec] Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 00tma_info_system_mem_dram_read_latency MemOffcore;MemoryLat;Server;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\=0x1@ Average latency of data read request to external DRAM memory [in nanoseconds] Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_info_system_mem_pmm_read_latency MemOffcore;MemoryLat;Server;SoC (1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\=0x1@ if #has_pmem > 0 else 0) Average latency of data read request to external 3D X-Point memory [in nanoseconds] Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (tma_info_system_socket_clks / duration_time) Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 01tma_info_system_smt_2t_utilization SMT (1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0) Fraction of cycles where both hardware Logical Processors were active 00tma_info_system_socket_clks SoC uncore_cha_0@event\=0x1@ Socket actual clocks when any core is active on that socket 00tma_info_system_upi_data_transmit_bw Server;SoC UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1e6 Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec] 00tma_info_thread_slots TmaL1;tma_L1_group TOPDOWN.SLOTS Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward) 00tma_info_thread_slots_utilization SMT;TmaL1;tma_L1_group (tma_info_thread_slots / (TOPDOWN.SLOTS / 2) if #SMT_on else 1) Fraction of Physical Core issue-slots utilized by this Logical Processor 00tma_info_thread_uoppi Pipeline;Ret;Retire tma_retiring * tma_info_thread_slots / INST_RETIRED.ANY tma_info_thread_uoppi > 1.05 Uops Per Instruction 00tma_info_thread_uptb Branches;Fed;FetchBW tma_retiring * tma_info_thread_slots / BR_INST_RETIRED.NEAR_TAKEN tma_info_thread_uptb < 9 Uops per taken branch 00tma_int_vector_128b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (tma_retiring * tma_info_thread_slots) tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_int_vector_256b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * tma_info_thread_slots) tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 data cache This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100% 00tma_l1_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT 100% 00tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS 100% 00tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100% 00tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 32.6 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency 100% 00tma_light_operations Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group max(0, tma_retiring - tma_heavy_operations) tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation) This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .). Sample with: INST_RETIRED.PREC_DIST 100% TopdownL2;Default TopdownL2 00tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED.PORT_2_3_10 / (3 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10 100% 00tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group 72 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM 100% 00tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100% 00tma_machine_clears BadSpec;BvMS;Default;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn max(0, tma_bad_speculation - tma_branch_mispredicts) tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100% TopdownL2;Default TopdownL2 00tma_mba_stalls MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma_mem_bandwidth_group INT_MISC.MBA_STALLS / tma_info_thread_clks tma_mba_stalls > 0.1 & (tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling) 100% 00tma_memory_bound Backend;Default;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group topdown\-mem\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2;Default TopdownL2 00tma_memory_fence TopdownL4;tma_L4_group;tma_serializing_operation_group 13 * MISC2_RETIRED.LFENCE / tma_info_thread_clks tma_memory_fence > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions 100% 02tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_retiring * tma_info_thread_slots) tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses 100% 00tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.MS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 00tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM tma_branch_mispredicts / tma_bad_speculation * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions 100% 00tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2 tma_mite > 0.1 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100% 00tma_mixing_vectors TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group 160 * ASSISTS.SSE_AVX_MIX / tma_info_thread_clks tma_mixing_vectors > 0.05 This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles) This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches 100% 00tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * cpu@UOPS_RETIRED.MS\,cmask\=1\,edge@ / (UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY) / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_non_fused_branches Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (tma_retiring * tma_info_thread_slots) tma_non_fused_branches > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused 100% 00tma_nop_instructions BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_thread_slots) tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6) This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP 100% 00tma_page_faults TopdownL5;tma_L5_group;tma_assists_group 99 * ASSISTS.PAGE_FAULT / tma_info_thread_slots tma_page_faults > 0.05 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost 100% 00tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((tma_ports_utilized_0 * tma_info_thread_clks + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\,umask\=0xc@)) / tma_info_thread_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\,umask\=0xc@) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 00tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (EXE_ACTIVITY.EXE_BOUND_0_PORTS + max(cpu@RS.EMPTY\,umask\=1@ - RESOURCE_STALLS.SCOREBOARD, 0)) / tma_info_thread_clks * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group EXE_ACTIVITY.1_PORTS_UTIL / tma_info_thread_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group EXE_ACTIVITY.2_PORTS_UTIL / tma_info_thread_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 02tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100% 02tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (133 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 133 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100% 00tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 153 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS 100% 00tma_retiring BvUW;Default;TmaL1;TopdownL1;tma_L1_group topdown\-retiring / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS 100% TopdownL1;Default TopdownL1 00tma_serializing_operation BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks + tma_c02_wait tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100% 00tma_shuffles_256b HPC;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group tma_light_operations * INT_VEC_RETIRED.SHUFFLES / (tma_retiring * tma_info_thread_slots) tma_shuffles_256b > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6) This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer) This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross "vector lane" data transfers 100% 00tma_slow_pause TopdownL4;tma_L4_group;tma_serializing_operation_group CPU_CLK_UNHALTED.PAUSE / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST 100% 02tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100% 00tma_sq_full BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / tma_info_thread_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth 100% 00tma_store_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 00tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * tma_info_core_core_clks) tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8 100% 00tma_streaming_stores MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group 9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_thread_clks tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full 100% 00tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group INT_MISC.UNKNOWN_BRANCH_CYCLES / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH 100% 00tma_mem_bandwidth_group Metrics contributing to tma_mem_bandwidth category C6_Module_Residency Power cstate_module@c6\-residency@ / TSC C6 residency percent per module 100% 00cpu_utilization tma_info_system_cpu_utilization Percentage of time spent in the active CPU power state C0 100% 00l1_i_code_read_misses_with_prefetches_per_instr ICACHE.MISSES / INST_RETIRED.ANY Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions 1per_instr 00l2_mpi LONGEST_LAT_CACHE.REFERENCE / INST_RETIRED.ANY Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions 1per_instr 00llc_code_read_mpi_demand_plus_prefetch (UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_data_read_mpi_demand_plus_prefetch (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF + UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA) / INST_RETIRED.ANY Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_demand_data_read_miss_latency 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds 1ns 00loads_retired_per_instr MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY Load operations retired per instruction 1per_instr 00memory_bandwidth_read (UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD) * 64 / 1e6 / duration_time DDR memory read bandwidth (MB/sec) 1MB/s 00memory_bandwidth_total (UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD + UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) * 64 / 1e6 / duration_time DDR memory bandwidth (MB/sec) 1MB/s 00memory_bandwidth_write (UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) * 64 / 1e6 / duration_time DDR memory write bandwidth (MB/sec) 1MB/s 00stores_retired_per_instr MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY Store operations retired per instruction 1per_instr 00tma_backend_bound TopdownL1;tma_L1_group TOPDOWN_BE_BOUND.ALL_P / (6 * CPU_CLK_UNHALTED.CORE) tma_backend_bound > 0.1 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count 100% TopdownL1 00tma_bad_speculation TopdownL1;tma_L1_group TOPDOWN_BAD_SPECULATION.ALL_P / (6 * CPU_CLK_UNHALTED.CORE) tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear 100% TopdownL1 00tma_branch_detect TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.BRANCH_DETECT / (6 * CPU_CLK_UNHALTED.CORE) tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches 100% 00tma_branch_mispredicts TopdownL2;tma_L2_group;tma_bad_speculation_group TOPDOWN_BAD_SPECULATION.MISPREDICT / (6 * CPU_CLK_UNHALTED.CORE) tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15 Counts the number of issue slots that were not consumed by the backend due to branch mispredicts 100% TopdownL2 00tma_branch_resteer TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.BRANCH_RESTEER / (6 * CPU_CLK_UNHALTED.CORE) tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch 100% 00tma_cisc TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.CISC / (6 * CPU_CLK_UNHALTED.CORE) tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS) 100% 00tma_core_bound TopdownL2;tma_L2_group;tma_backend_bound_group TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / (6 * CPU_CLK_UNHALTED.CORE) tma_core_bound > 0.1 & tma_backend_bound > 0.1 Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation 100% TopdownL2 00tma_decode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.DECODE / (6 * CPU_CLK_UNHALTED.CORE) tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to decode stalls 100% 00tma_fast_nuke TopdownL3;tma_L3_group;tma_machine_clears_group TOPDOWN_BAD_SPECULATION.FASTNUKE / (6 * CPU_CLK_UNHALTED.CORE) tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming 100% 00tma_frontend_bound TopdownL1;tma_L1_group TOPDOWN_FE_BOUND.ALL_P / (6 * CPU_CLK_UNHALTED.CORE) tma_frontend_bound > 0.2 Counts the number of issue slots that were not consumed by the backend due to frontend stalls 100% TopdownL1 00tma_icache_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.ICACHE / (6 * CPU_CLK_UNHALTED.CORE) tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses 100% 00tma_ifetch_bandwidth TopdownL2;tma_L2_group;tma_frontend_bound_group TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / (6 * CPU_CLK_UNHALTED.CORE) tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations 100% TopdownL2 00tma_ifetch_latency TopdownL2;tma_L2_group;tma_frontend_bound_group TOPDOWN_FE_BOUND.FRONTEND_LATENCY / (6 * CPU_CLK_UNHALTED.CORE) tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations 100% TopdownL2 00tma_info_arith_inst_mix_ipflop Flops INST_RETIRED.ANY / FP_FLOPS_RETIRED.ALL Instructions per Floating Point (FP) Operation 00tma_info_arith_inst_mix_ipfparith_avx128 Flops INST_RETIRED.ANY / (FP_INST_RETIRED.128B_DP + FP_INST_RETIRED.128B_SP) Instructions per FP Arithmetic AVX/SSE 128-bit instruction 00tma_info_arith_inst_mix_ipfparith_scalar_dp Flops INST_RETIRED.ANY / FP_INST_RETIRED.64B_DP Instructions per FP Arithmetic Scalar Double-Precision instruction 00tma_info_arith_inst_mix_ipfparith_scalar_sp Flops INST_RETIRED.ANY / FP_INST_RETIRED.32B_SP Instructions per FP Arithmetic Scalar Single-Precision instruction 00tma_info_bottleneck_%_dtlb_miss_bound_cycles tma_info_bottleneck_dtlb_miss_bound_cycles Percentage of time that retirement is stalled due to a first level data TLB miss 00tma_info_bottleneck_%_ifetch_miss_bound_cycles Ifetch tma_info_bottleneck_ifetch_miss_bound_cycles Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound 00tma_info_bottleneck_%_load_miss_bound_cycles Load_Store_Miss tma_info_bottleneck_load_miss_bound_cycles Percentage of time that retirement is stalled due to an L1 miss Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound 00tma_info_bottleneck_%_mem_exec_bound_cycles Mem_Exec tma_info_bottleneck_mem_exec_bound_cycles Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound 00tma_info_bottleneck_dtlb_miss_bound_cycles Cycles 100 * (LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT_RET) / CPU_CLK_UNHALTED.CORE Percentage of time that retirement is stalled due to a first level data TLB miss 100% 00tma_info_bottleneck_ifetch_miss_bound_cycles Cycles;Ifetch 100 * MEM_BOUND_STALLS_IFETCH.ALL / CPU_CLK_UNHALTED.CORE Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound 100% 00tma_info_bottleneck_load_miss_bound_cycles Cycles;Load_Store_Miss 100 * MEM_BOUND_STALLS_LOAD.ALL / CPU_CLK_UNHALTED.CORE Percentage of time that retirement is stalled due to an L1 miss Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound 100% 00tma_info_bottleneck_mem_exec_bound_cycles Cycles;Mem_Exec 100 * LD_HEAD.ANY_AT_RET / CPU_CLK_UNHALTED.CORE Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound 100% 00tma_info_br_inst_mix_ipcall INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL Instruction per (near) call (lower number means higher occurrence rate) 00tma_info_buffer_stalls_%_load_buffer_stall_cycles tma_info_buffer_stalls_load_buffer_stall_cycles Percentage of time that allocation is stalled due to load buffer full 00tma_info_buffer_stalls_%_mem_rsv_stall_cycles tma_info_buffer_stalls_mem_rsv_stall_cycles Percentage of time that allocation is stalled due to memory reservation stations full 00tma_info_buffer_stalls_%_store_buffer_stall_cycles tma_info_buffer_stalls_store_buffer_stall_cycles Percentage of time that allocation is stalled due to store buffer full 00tma_info_buffer_stalls_load_buffer_stall_cycles 100 * MEM_SCHEDULER_BLOCK.LD_BUF / CPU_CLK_UNHALTED.CORE Percentage of time that allocation is stalled due to load buffer full 100% 00tma_info_buffer_stalls_mem_rsv_stall_cycles 100 * MEM_SCHEDULER_BLOCK.RSV / CPU_CLK_UNHALTED.CORE Percentage of time that allocation is stalled due to memory reservation stations full 100% 00tma_info_buffer_stalls_store_buffer_stall_cycles 100 * MEM_SCHEDULER_BLOCK.ST_BUF / CPU_CLK_UNHALTED.CORE Percentage of time that allocation is stalled due to store buffer full 100% 00tma_info_core_flopc Flops FP_FLOPS_RETIRED.ALL / CPU_CLK_UNHALTED.CORE Floating Point Operations Per Cycle 00tma_info_core_upi TOPDOWN_RETIRING.ALL_P / INST_RETIRED.ANY Uops Per Instruction 00tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2hit tma_info_ifetch_miss_bound_ifetchmissbound_with_l2hit Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2 00tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3hit tma_info_ifetch_miss_bound_ifetchmissbound_with_l3hit Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3 00tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3miss 100 * MEM_BOUND_STALLS_IFETCH.LLC_MISS / MEM_BOUND_STALLS_IFETCH.ALL Percentage of ifetch miss bound stalls, where the ifetch miss subsequently misses in the L3 00tma_info_ifetch_miss_bound_ifetchmissbound_with_l2hit 100 * MEM_BOUND_STALLS_IFETCH.L2_HIT / MEM_BOUND_STALLS_IFETCH.ALL Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2 100% 00tma_info_ifetch_miss_bound_ifetchmissbound_with_l3hit 100 * MEM_BOUND_STALLS_IFETCH.LLC_HIT / MEM_BOUND_STALLS_IFETCH.ALL Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3 100% 00tma_info_load_miss_bound_%_loadmissbound_with_l2hit load_store_bound tma_info_load_miss_bound_loadmissbound_with_l2hit Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2 00tma_info_load_miss_bound_%_loadmissbound_with_l3hit load_store_bound tma_info_load_miss_bound_loadmissbound_with_l3hit Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3 00tma_info_load_miss_bound_%_loadmissbound_with_l3miss load_store_bound 100 * MEM_BOUND_STALLS_LOAD.LLC_MISS / MEM_BOUND_STALLS_LOAD.ALL Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses the L3 00tma_info_load_miss_bound_loadmissbound_with_l2hit load_store_bound 100 * MEM_BOUND_STALLS_LOAD.L2_HIT / MEM_BOUND_STALLS_LOAD.ALL Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2 100% 00tma_info_load_miss_bound_loadmissbound_with_l3hit load_store_bound 100 * MEM_BOUND_STALLS_LOAD.LLC_HIT / MEM_BOUND_STALLS_LOAD.ALL Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3 100% 00tma_info_load_store_bound_load_bound load_store_bound 100 * (LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS_LOAD.ALL) / CPU_CLK_UNHALTED.CORE Counts the number of cycles that the oldest load of the load buffer is stalled at retirement 00tma_info_mem_exec_blocks_%_loads_with_adressaliasing tma_info_mem_exec_blocks_loads_with_adressaliasing Percentage of total non-speculative loads with an address aliasing block 00tma_info_mem_exec_blocks_%_loads_with_storefwdblk tma_info_mem_exec_blocks_loads_with_storefwdblk Percentage of total non-speculative loads with a store forward or unknown store address block 00tma_info_mem_exec_blocks_loads_with_adressaliasing 100 * LD_BLOCKS.ADDRESS_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads with an address aliasing block 100% 00tma_info_mem_exec_blocks_loads_with_storefwdblk 100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads with a store forward or unknown store address block 100% 00tma_info_mem_exec_bound_%_loadhead_with_l1miss tma_info_mem_exec_bound_loadhead_with_l1miss Percentage of Memory Execution Bound due to a first level data cache miss 00tma_info_mem_exec_bound_%_loadhead_with_otherpipelineblks tma_info_mem_exec_bound_loadhead_with_otherpipelineblks Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc 00tma_info_mem_exec_bound_%_loadhead_with_pagewalk tma_info_mem_exec_bound_loadhead_with_pagewalk Percentage of Memory Execution Bound due to a pagewalk 00tma_info_mem_exec_bound_%_loadhead_with_stlbhit tma_info_mem_exec_bound_loadhead_with_stlbhit Percentage of Memory Execution Bound due to a second level TLB miss 00tma_info_mem_exec_bound_%_loadhead_with_storefwding tma_info_mem_exec_bound_loadhead_with_storefwding Percentage of Memory Execution Bound due to a store forward address match 00tma_info_mem_exec_bound_loadhead_with_l1miss 100 * LD_HEAD.L1_MISS_AT_RET / LD_HEAD.ANY_AT_RET Percentage of Memory Execution Bound due to a first level data cache miss 100% 00tma_info_mem_exec_bound_loadhead_with_otherpipelineblks 100 * LD_HEAD.OTHER_AT_RET / LD_HEAD.ANY_AT_RET Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc 100% 00tma_info_mem_exec_bound_loadhead_with_pagewalk 100 * LD_HEAD.PGWALK_AT_RET / LD_HEAD.ANY_AT_RET Percentage of Memory Execution Bound due to a pagewalk 100% 00tma_info_mem_exec_bound_loadhead_with_stlbhit 100 * LD_HEAD.DTLB_MISS_AT_RET / LD_HEAD.ANY_AT_RET Percentage of Memory Execution Bound due to a second level TLB miss 100% 00tma_info_mem_exec_bound_loadhead_with_storefwding 100 * LD_HEAD.ST_ADDR_AT_RET / LD_HEAD.ANY_AT_RET Percentage of Memory Execution Bound due to a store forward address match 100% 00tma_info_mem_mix_memload_ratio 1e3 * MEM_UOPS_RETIRED.ALL_LOADS / TOPDOWN_RETIRING.ALL_P Ratio of mem load uops to all uops 00tma_info_serialization _%_tpause_cycles tma_info_serialization_tpause_cycles Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction 00tma_info_serialization_tpause_cycles 100 * SERIALIZATION.C01_MS_SCB / (6 * CPU_CLK_UNHALTED.CORE) Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction 100% 00tma_info_system_gflops Flops FP_FLOPS_RETIRED.ALL / (duration_time * 1e9) Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width 00tma_info_uop_mix_fpdiv_uop_ratio 100 * UOPS_RETIRED.FPDIV / TOPDOWN_RETIRING.ALL_P Percentage of all uops which are FPDiv uops 00tma_info_uop_mix_idiv_uop_ratio 100 * UOPS_RETIRED.IDIV / TOPDOWN_RETIRING.ALL_P Percentage of all uops which are IDiv uops 00tma_info_uop_mix_microcode_uop_ratio 100 * UOPS_RETIRED.MS / TOPDOWN_RETIRING.ALL_P Percentage of all uops which are microcode ops 00tma_info_uop_mix_x87_uop_ratio 100 * UOPS_RETIRED.X87 / TOPDOWN_RETIRING.ALL_P Percentage of all uops which are x87 uops 00tma_itlb_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.ITLB_MISS / (6 * CPU_CLK_UNHALTED.CORE) tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses 100% 00tma_machine_clears TopdownL2;tma_L2_group;tma_bad_speculation_group TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / (6 * CPU_CLK_UNHALTED.CORE) tma_machine_clears > 0.05 & tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation 100% TopdownL2 00tma_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.MEM_SCHEDULER / (6 * CPU_CLK_UNHALTED.CORE) tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops 100% 00tma_non_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / (6 * CPU_CLK_UNHALTED.CORE) tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops 100% 00tma_nuke TopdownL3;tma_L3_group;tma_machine_clears_group TOPDOWN_BAD_SPECULATION.NUKE / (6 * CPU_CLK_UNHALTED.CORE) tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke) 100% 00tma_other_fb TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.OTHER / (6 * CPU_CLK_UNHALTED.CORE) tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized 100% 00tma_predecode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.PREDECODE / (6 * CPU_CLK_UNHALTED.CORE) tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes 100% 00tma_register TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.REGISTER / (6 * CPU_CLK_UNHALTED.CORE) tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls) 100% 00tma_reorder_buffer TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.REORDER_BUFFER / (6 * CPU_CLK_UNHALTED.CORE) tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls) 100% 00tma_retiring TopdownL1;tma_L1_group TOPDOWN_RETIRING.ALL_P / (6 * CPU_CLK_UNHALTED.CORE) tma_retiring > 0.75 Counts the number of issue slots that result in retirement slots 100% TopdownL1 00tma_serialization TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.SERIALIZATION / (6 * CPU_CLK_UNHALTED.CORE) tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS) 100% 00tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group 10 * ARITH.DIVIDER_UOPS / tma_info_core_core_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100% 03tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100% 00tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100% 00tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fb_full BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\,cmask\=1@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100% 01tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group 4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END 100% TopdownL2 00tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil (UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@)) Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor) 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_core_core_clks tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED 100% 00tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 data cache This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100% 00tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS 100% 00tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100% 03tma_mem_bandwidth BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=6@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group ((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 01tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 01tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,inv\,cmask\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_core_clks) tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / tma_info_core_core_clks) tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / tma_info_core_core_clks) tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / tma_info_core_core_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) 100% 00io_bandwidth_write cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x1c8\,filter_tid\=0x3e@ * 64 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00percent_uops_delivered_from_loop_stream_detector (UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS) / UOPS_ISSUED.ANY Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue 100% 00tma_4k_aliasing TopdownL4;tma_L4_group;tma_l1_bound_group LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_thread_clks tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound) 100% 02tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * tma_info_core_core_clks) tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 00tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 34 * ASSISTS.ANY / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100% 00tma_backend_bound BvOB;Default;TmaL1;TopdownL1;tma_L1_group topdown\-be\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 5 * INT_MISC.CLEARS_COUNT / tma_info_thread_slots tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100% TopdownL1;Default TopdownL1 00tma_branch_instructions Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * tma_info_thread_slots) tma_branch_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions 100% 00tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 100% TopdownL2 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (29 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 23.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 23.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 01tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization 100% 00tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 32.5 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group (5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100% TopdownL2 00tma_few_uops_instructions TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0 tma_heavy_operations - tma_microcode_sequencer tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone 100% 00tma_fp_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 34 * ASSISTS.FP / tma_info_thread_slots tma_fp_assists > 0.1 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals) 100% 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P FP_ARITH_INST_RETIRED.SCALAR / (tma_retiring * tma_info_thread_slots) tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P FP_ARITH_INST_RETIRED.VECTOR / (tma_retiring * tma_info_thread_slots) tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_512b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\,cmask\=1@) / IDQ.MITE_UOPS tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .) 100% TopdownL2 00tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM tma_info_bottleneck_mispredictions * tma_info_thread_slots / BR_MISP_RETIRED.ALL_BRANCHES / 100 Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 01tma_info_botlnk_core_bound_likely Cor;Metric;SMT tma_info_botlnk_l0_core_bound_likely tma_info_botlnk_core_bound_likely > 0.5 Probability of Core Bound bottleneck hidden by SMT-profiling artifacts 00tma_info_botlnk_dsb_misses DSBmiss;Fed;Scaled_Slots;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches) + tma_fetch_bandwidth * tma_mite / (tma_mite + tma_dsb + tma_lsd)) tma_info_botlnk_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck 00tma_info_botlnk_ic_misses Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL 100 * (tma_fetch_latency * tma_icache_misses / (tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches)) tma_info_botlnk_ic_misses > 5 Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck 00tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 01tma_info_botlnk_l2_ic_misses Fed;FetchLat;IcMiss;tma_issueFL 100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_info_botlnk_l2_ic_misses > 5 Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: 01tma_info_bottleneck_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_info_bottleneck_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full 00tma_info_bottleneck_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_info_bottleneck_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency 00tma_info_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization 01tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_core_clks Floating Point Operations Per Cycle 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / UOPS_ISSUED.ANY tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 5 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp 00tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ Average Latency for L1 instruction cache misses 00tma_info_frontend_lsd_coverage Fed;LSD LSD.UOPS / UOPS_ISSUED.ANY Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache) 00tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 00tma_info_inst_mix_ippause Flops;FpVector;InsType tma_info_inst_mix_instructions / MISC_RETIRED.PAUSE_INST Instructions per PAUSE (lower number means higher occurrence rate) 00tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 11 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp 00tma_info_memory_bus_lock_pki Mem;Metric tma_info_memory_mix_bus_lock_pki "Bus lock" per kilo instruction 00tma_info_memory_code_stlb_mpki Fed;MemoryTLB;Metric tma_info_memory_tlb_code_stlb_mpki STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_data_l2_mlp Memory_BW;Metric;Offcore tma_info_memory_latency_data_l2_mlp Average Parallel L2 cache miss data reads 00tma_info_memory_l1d_cache_fill_bw_2t Core_Metric;Mem;MemoryBW tma_info_memory_l1d_cache_fill_bw Average per-core data fill bandwidth to the L1 data cache [GB / sec] 00tma_info_memory_l2_cache_fill_bw_2t Core_Metric;Mem;MemoryBW tma_info_memory_l2_cache_fill_bw Average per-core data fill bandwidth to the L2 cache [GB / sec] 00tma_info_memory_l2mpki_all CacheHits;Mem;Offcore 1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / tma_info_inst_mix_instructions L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative) 00tma_info_memory_l3_cache_access_bw_2t Core_Metric;Mem;MemoryBW;Offcore tma_info_memory_l3_cache_access_bw Average per-core data access bandwidth to the L3 cache [GB / sec] 00tma_info_memory_l3_cache_fill_bw_2t Core_Metric;Mem;MemoryBW tma_info_memory_l3_cache_fill_bw Average per-core data fill bandwidth to the L3 cache [GB / sec] 00tma_info_memory_latency_load_l2_miss_latency Memory_Lat;Offcore tma_info_memory_load_l2_miss_latency Average Latency for L2 cache miss demand Loads 00tma_info_memory_latency_load_l3_miss_latency Memory_Lat;Offcore cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\,umask\=0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD Average Latency for L3 cache miss demand Loads 00tma_info_memory_load_l2_miss_latency Clocks_Latency;Memory_Lat;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD Average Latency for L2 cache miss demand Loads 00tma_info_memory_load_l2_mlp Memory_BW;Metric;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\,cmask\=0x1@ Average Parallel L2 cache miss demand Loads 00tma_info_memory_load_l3_miss_latency Clocks_Latency;Memory_Lat;Offcore cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\,umask\=0x0@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD Average Latency for L3 cache miss demand Loads 00tma_info_memory_load_stlb_mpki Mem;MemoryTLB;Metric tma_info_memory_tlb_load_stlb_mpki STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_mix_uc_load_pki Mem tma_info_memory_uc_load_pki Un-cacheable retired load per kilo instruction 00tma_info_memory_page_walks_utilization Core_Metric;Mem;MemoryTLB tma_info_memory_tlb_page_walks_utilization tma_info_memory_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_memory_store_stlb_mpki Mem;MemoryTLB;Metric tma_info_memory_tlb_store_stlb_mpki STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_memory_uc_load_pki Mem;Metric 1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY Un-cacheable retired load per kilo instruction 00tma_info_pipeline_fetch_lsd Fed;FetchBW LSD.UOPS / LSD.CYCLES_ACTIVE Average number of uops fetched from LSD per cycle 00tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width 00tma_info_system_power_license0_utilization Power CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_core_clks Fraction of Core cycles where the core was running with power-delivery for baseline license level 0 Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes 00tma_info_system_power_license1_utilization Power CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_core_clks tma_info_system_power_license1_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 1 Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions 00tma_info_system_power_license2_utilization Power CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_core_clks tma_info_system_power_license2_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX) Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions 00tma_info_thread_uptb Branches;Fed;FetchBW tma_retiring * tma_info_thread_slots / BR_INST_RETIRED.NEAR_TAKEN tma_info_thread_uptb < 7.5 Uops per taken branch 00tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks) tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS 100% 01tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100% 02tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 9 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency 100% 00tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED.PORT_2_3 / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100% 00tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100% 01tma_lsd FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core_core_clks / 2 tma_lsd > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 00tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses 100% 01tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 00tma_mite_4wide DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group (cpu@IDQ.MITE_UOPS\,cmask\=4@ - cpu@IDQ.MITE_UOPS\,cmask\=5@) / tma_info_thread_clks tma_mite_4wide > 0.05 & (tma_mite > 0.1 & tma_fetch_bandwidth > 0.2) This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline 100% 00tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * IDQ.MS_SWITCHES / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_other_light_ops Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions)) tma_other_light_ops > 0.3 & tma_light_operations > 0.6 This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting 100% 01tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_5 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_5 / tma_info_core_core_clks tma_port_5 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group cpu@EXE_ACTIVITY.3_PORTS_UTIL\,umask\=0x80@ / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group EXE_ACTIVITY.2_PORTS_UTIL / tma_info_thread_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100% 00tma_serializing_operation BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100% 00tma_slow_pause TopdownL4;tma_L4_group;tma_serializing_operation_group 140 * MISC_RETIRED.PAUSE_INST / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST 100% 00tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100% 02tma_sq_full BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group L1D_PEND_MISS.L2_STALL / tma_info_thread_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth 100% 00tma_store_fwd_blk TopdownL4;tma_L4_group;tma_l1_bound_group 13 * LD_BLOCKS.STORE_FORWARD / tma_info_thread_clks tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading 100% 02tma_store_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 00tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group 10 * BACLEARS.ANY / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY 100% 00io_bandwidth_write (UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 43.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43.5 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 48 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_info_bottleneck_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_info_bottleneck_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency 00tma_info_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization 01tma_info_bottleneck_memory_synchronization BvMS;Mem;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_info_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs 00tma_info_system_io_write_bw IoBW;MemOffcore;Server;SoC (UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e9 / duration_time Average IO (network or disk) Bandwidth Use for Writes [GB / sec] Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 00tma_info_system_mem_dram_read_latency MemOffcore;MemoryLat;Server;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@event\=0x0@ Average latency of data read request to external DRAM memory [in nanoseconds] Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_info_system_mem_pmm_read_latency MemOffcore;MemoryLat;Server;SoC (1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\=0x0@ if #has_pmem > 0 else 0) Average latency of data read request to external 3D X-Point memory [in nanoseconds] Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 19 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency 100% 00tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group 43.5 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM 100% 00tma_pmm_bound MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0) tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module 100% 00tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (97 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 97 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100% 00tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 108 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS 100% 00tma_slow_pause TopdownL4;tma_L4_group;tma_serializing_operation_group 37 * MISC_RETIRED.PAUSE_INST / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST 100% 00tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5) / (3 * tma_info_core_core_clks) tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 02tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100% 03tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100% 00tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (7 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100% 00tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE) / UOPS_EXECUTED.THREAD tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (SIMD_FP_256.PACKED_DOUBLE + SIMD_FP_256.PACKED_SINGLE) / UOPS_EXECUTED.THREAD tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE.IFETCH_STALL / tma_info_thread_clks - tma_itlb_misses tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses 100% 00tma_info_core_flopc Flops;Ret (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / tma_info_core_core_clks Floating Point Operations Per Cycle 00tma_info_inst_mix_iparith Flops;InsType 1 / (tma_fp_scalar + tma_fp_vector) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW 00tma_info_memory_l3mpki Mem 1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY L3 cache true misses per kilo instruction for retired demand loads 00tma_info_system_gflops Cor;Flops;HPC (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width 00tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED 100% 00tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100% 03tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 29 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100% 01tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100% 02tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 01tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * IDQ.MS_SWITCHES / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 01tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group 13 * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS 100% 01tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_EXECUTED.THREAD tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 41 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100% 01tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group 200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS 100% 00tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100% 01tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 310 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS 100% 00tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_lcp 100% 00tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_load > 0.1 This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100% 00tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_lcp 100% TopdownL2 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_DISPATCHED.THREAD tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_DISPATCHED.THREAD tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE) / UOPS_DISPATCHED.THREAD tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (SIMD_FP_256.PACKED_DOUBLE + SIMD_FP_256.PACKED_SINGLE) / UOPS_DISPATCHED.THREAD tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2 100% 00tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil UOPS_DISPATCHED.THREAD / (cpu@UOPS_DISPATCHED.CORE\,cmask\=1@ / 2 if #SMT_on else cpu@UOPS_DISPATCHED.CORE\,cmask\=1@) Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor) 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_lcp 00tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_mem_bandwidth 00tma_info_thread_execute_per_issue Cor;Pipeline UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY The ratio of Executed- by Issued-Uops The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage 00tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB ILD_STALL.LCP / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage 100% 00tma_machine_clears BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn tma_bad_speculation - tma_branch_mispredicts tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100% TopdownL2 01tma_mem_bandwidth BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=6@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_info_system_dram_bw_use 100% 00tma_mem_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\,cmask\=1@ - (cpu@UOPS_DISPATCHED.THREAD\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 01tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\,cmask\=1@ - (cpu@UOPS_DISPATCHED.THREAD\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 01tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_DISPATCHED.THREAD tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC (UNC_ARB_TRK_OCCUPANCY.RD + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.RD Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100% 03tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3 Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_mem_bandwidth 00tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100% 03tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks - tma_pmm_bound if #has_pmem > 0 else MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks) tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 00tma_heavy_operations Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group topdown\-heavy\-ops / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .). Sample with: UOPS_RETIRED.HEAVY 100% TopdownL2;Default TopdownL2 00tma_info_bottleneck_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_info_bottleneck_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full 00tma_info_bottleneck_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l1_hit_latency / (tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_info_bottleneck_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency 00tma_info_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization 00tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * cpu@UOPS_RETIRED.MS\,cmask\=1\,edge@ / (UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY) / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_pmm_bound MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0) tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module 100% 00iio_bandwidth_read UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1e6 / duration_time Bandwidth observed by the integrated I/O traffic contoller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU 1MB/s 00numa_reads_addressed_to_local_dram (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE) Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00numa_reads_addressed_to_remote_dram (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE) Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (18.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 16.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 16.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 22 * tma_info_system_core_frequency * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P FP_ARITH_INST_RETIRED.VECTOR / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 01tma_info_bottleneck_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_info_bottleneck_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency 00tma_info_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization 01tma_info_bottleneck_memory_synchronization BvMS;Mem;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_info_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs 00tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_core_clks Floating Point Operations Per Cycle 01tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED.VECTOR) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW 01tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 01tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width 01tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ@cmask\=1@ Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_REQUESTS.DATA_READ) / (tma_info_system_socket_clks / duration_time) Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 00tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 6.5 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency 100% 00tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (9 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100% 00tma_store_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 02llc_data_read_demand_plus_prefetch_miss_latency 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40433@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40433@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40432@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40431@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds 1ns 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 44 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (110 * tma_info_system_core_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_info_system_core_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_info_bottleneck_memory_synchronization BvMS;Mem;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_info_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs 00uncore_frequency UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time Uncore operating frequency in GHz 1GHz 00power_channel_ppd UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS * 100 Cycles where DRAM ranks are in power down (CKE) mode Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of 00LLC_MISSES.PCIE_READ UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 4Bytes 00LLC_MISSES.PCIE_WRITE UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 4Bytes 00power_channel_ppd UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS * 100 Cycles where DRAM ranks are in power down (CKE) mode Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of 00power_self_refresh UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS * 100 Cycles Memory is in self refresh power mode Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases 00tma_contested_accesses BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (49 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 48 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 48 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_false_sharing BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 54 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (arb@event\=0x81\,umask\=0x1@ + arb@event\=0x84\,umask\=0x1@) / 1e6 / duration_time / 1e3 Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_mem_bandwidth, tma_sq_full 00tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 17.5 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency 100% 00 R R R R R R R R R R R R "R R 'R R ,R R 1R R 6R R ;R R @R R ER R JR R OR R TR R YR R ^R R eR R oR R {R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R V R R R 42 R R R R R (R R ;R R 7R R FR R OR R XR R dR R nR R xR R R R R R R R >R R R R R R R R R R / R R R R R R R R R R R R R R R R R R R R R R R 'R 1R [R eR R R R R R R +R R <R R IR 1R VR eR cR R pR R }R R R R R R R 6R iR R R R R 'R \R qR R R R R )R >R nR R R R R R IR ]R R R R R *R ER {R R R R R !R GR SR yR R R R R R R R ER QR wR R R R R R R R AR MR sR R R R R R R R AR OR wR R R R R R &R 9R gR R R R R (R 6,X N,X \R rR R R R R CR RR |R R R R R 9R oR R R R R "R PR pR R R R R U0M 0M 1M w1M 1M G2M 0P 3M q3M , 3M B4M 4M 5M 5M 5M e6M 6M *7M 7M 7M h8M 8M b9M 9M .:M :M ;M ;M <M y<M <M R=M wP P =M >L >L 2>M >M Q?M ?M <@M _M P _M t`M `M P OaM iP P aM bM TP P *M HL L <L L L }L L [L L /L L &L L L @M AM sAM AM 4BM BM dCM BM CM CDM DM 6EM EM %FM O*M bM cM bM &P cM P ;?L ?L ?L e@L \EL FL XGL GL $HL HL <IL HL IL *M +M Q+M +M IL LJL JL KL 'KL KL YLL LL ML >ML NL |NL NL -OL OL OL JPL PL -QL QL ZRL QL RL SL OSL SL 6TL TL SL TL UL UL 8UL VL pVL VL .WL WL WL IXL XL YL dYL YL ZL =ZL ZL _[L [L \L 4\L \L +M P ?,M ,M ,M S-M FM O]L ]L GM wGM GM [HM HM @IM M gM ^L ^L ^_L _L `L CaL aL bL %cL cL fdL eL eL IfL fL gL hL dM hL iL iL jL jL (kL dM SP P P P mnL cgP 7O O O IO O )O nL O O yO O O O O O ToL oL 7M M dpL pL }qL 3rL rL sL $tL QM tL YuL vL vL M 3wL yM M wL NxL xL yL WzL {L {L M =|L |L }L ~L -M ~L M PM OL L jL !L ӁL L L M L LL L L tM )L M M ĆL BL ߇L L HL L L % M +L L kL L M L O M M ,L L 7L L L L [ M L &L ÒL YL M L k M M L -L ܕL L iL 0L ϘL M L *L L L RM =L M M ڜL sL $L L L ~L L %M L QL L L M RL yM M L L ,L L L nL L M L VL L L NM WL M M L L 1L L L sL L #M L [L L L M \L eM M L L 3L L L rL L M L WL L L 7M UL M nM L L )L L L eL L M L GL L L M BL E M M L [L L L aL L L DL L L L a M L M M \L L L LL L L ^L & M L L ]L L M L d M M IL L xL 9L L L KL !M L L JL L 3"M L "M h#M 5L L bL "L L L 1L $M L zL -L L $M rL <%M %M L L @L L L vL L h&M L RL L L 'M GL 'M 5(M L lL L L L ?L L (M yL L L dL e)M -M IM IM GJM JM KM mKM KM ;LM LM LM iMM MM 9NM +.M .M L L L L rL L fL L @L L 5L L # M M .M 7/M /M P ْP .P P P P P oP P /M gP L NM OM OM PM PM sL L M @_M QM QM QM cRM RM fSM P #P 2UM UM hVM VM ,WM WM XM XM XM pYM YM FZM ZM [M [M [M d\M \M C]M ]M %^M ^M U0M 0M 1M w1M 1M G2M 2M 3M q3M , 3M B4M 4M 5M 5M 5M e6M 6M *7M 7M 7M h8M 8M b9M 9M .:M :M ;M ;M <M y<M <M R=M wP P =M >L >L 2>M >M Q?M ?M <@M _M _M t`M `M P OaM iP aM bM TP P *M HL L <L L L }L L [L L /L L &L L L @M AM sAM AM 4BM BM dCM BM CM CDM DM 6EM EM %FM O*M bM cM bM cM P ;?L ?L ?L e@L \EL FL XGL GL $HL HL <IL HL IL *M +M Q+M +M IL LJL JL KL 'KL KL YLL LL ML >ML NL |NL NL -OL OL OL JPL PL -QL QL ZRL QL RL SL OSL SL 6TL TL SL TL UL UL 8UL VL pVL VL .WL WL WL IXL XL YL dYL YL ZL =ZL ZL _[L [L \L 4\L \L +M P ?,M ,M ,M S-M FM O]L ]L GM wGM GM [HM HM @IM M gM ^L ^L ^_L _L `L CaL aL bL %cL cL fdL eL eL IfL fL gL hL dM hL iL iL jL jL (kL dM P lL )mL P mnL 7O O O IO O )O nL ZP O O yO O O O O O ToL oL 7M M dpL pL }qL 3rL rL sL ȜP P tL hP vL vL P 3wL yM M wL NxL xL yL WzL {L P 2P =|L P }L ~L ȻP ~L M PM OL L jL !L ӁL L ^P ^P L P L L P )L M M ĆL BL ߇L L HL L P P +L JP kL L P L O M M ,L L 7L L L P P L P ÒL YL :P L k M M L -L ܕL L iL 0L %P ¿P L أP L L iP =L M M ڜL sL $L L L ~L P P L 8P L L P RL yM M L L ,L L L nL ޥP dP L P L L P WL M M L L 1L L L sL AP P L P L L GP \L eM M L L 3L L L rL P P L PP L L P UL M nM L L )L L L eL P (P L P L L P BL E M M L [L L L aL L dP DL P L L fP P P P TP ܭP P DP P P VP +P P P UP P P L d M M IL L xL 9L L L P iP L GP JL L P L "M h#M 5L L bL "L L L P P L P -L L EP rL <%M %M L L @L L L vL XP P L P L L P GL 'M 5(M L lL L L L ?L P P yL ZP L dL P -M IM IM GJM JM KM mKM KM ;LM LM LM iMM MM 9NM +.M .M L L L L rL L fL L @L L 5L L # M M .M 7/M /M P ْP .P P P P P oP P /M gP L NM OM OM PM PM sL L M @_M QM QM QM cRM RM fSM TM TM 2UM UM hVM VM ,WM WM XM XM XM pYM YM FZM ZM [M [M [M d\M \M C]M ]M %^M ^M U0M 0M 1M w1M 1M G2M 2M 3M q3M , 3M B4M 4M 5M 5M 5M e6M 6M *7M 7M 7M h8M 8M b9M 9M .:M :M ;M ;M <M y<M <M R=M wP P =M >L >L 2>M >M Q?M ?M <@M _M P _M t`M `M P OaM iP ݘP aM bM TP P *M HL L <L L L }L L [L L /L L &L L L @M AM sAM AM 4BM BM dCM BM CM CDM DM 6EM EM %FM O*M bM cM bM &P cM P ;?L ?L ?L e@L \EL FL XGL GL $HL HL <IL HL IL *M +M Q+M +M IL LJL JL KL 'KL KL YLL LL ML >ML NL |NL NL -OL OL OL JPL PL -QL QL ZRL QL RL SL OSL SL 6TL TL SL TL UL UL 8UL VL pVL VL .WL WL WL IXL XL YL dYL YL ZL =ZL ZL _[L [L \L 4\L \L +M P ?,M ,M ,M S-M FM O]L ]L GM wGM GM [HM HM @IM M gM ^L ^L ^_L _L `L CaL aL bL %cL cL fdL eL eL IfL fL gL hL dM hL iL iL jL jL (kL dM cgP 7O O O IO O )O nL O O yO O O O O O ToL O cO gP qhP O O 3O O O :O O iP O iP 4O O HjP jP P 1P P rP P P bP kP !P 4lP P P lP ~mP +P P _P P P i P P nP P nP f P ' P XoP pP P QP P P ,P P dP pP P 2qP P yP qP mrP P P 1P P yP P P sP gP sP P P ,tP tP jP P P J P P P @ P zuP P vP P f P vP bwP P !P !"P "P k#P $P $P wP \%P xP %P &P $yP yP `'P 'P (P @)P )P *P 6+P rzP +P {P ,P j-P {P h|P .P .P O/P 0P 0P k1P 2P }P 2P }P z3P G4P T~P P 4P 5P &6P 6P 7P <8P 8P P 9P RP E:P ;P P P ;P B<P <P =P />P >P s?P :P 2@P ܂P @P AP tP P $BP BP @CP CP DP &EP EP P gFP BP FP GP ЅP zP WHP HP {IP JP JP mKP KP P LP P RMP NP <P P NP OOP OP PP <QP QP RP P ?SP (P SP TP P kP ;UP UP aVP WP WP VXP XP P YP P >ZP [P 0P ۍP [P ,\P \P c]P ^P ^P D_P pP _P P `P ^aP P LP aP bP cP cP mdP eP eP P dfP P -M IM IM GJM JM KM mKM KM ;LM LM LM iMM MM 9NM +.M .M L L L L rL L fL L @L L 5L L # M M .M 7/M /M P ْP .P P P P P oP P /M gP L NM OM OM PM PM sL L M @_M QM QM QM cRM RM fSM TM TM 2UM UM hVM VM ,WM WM XM XM XM pYM YM FZM ZM [M [M [M d\M \M C]M ]M %^M ^M xP BP P P mP P 4P P P 5Q `P P qX X X X v@Q X tX U U U Z XQ Z .U U X U U X B W Z 4&W |{Q cX <X τQ X xX X X X nX AW MY LW Y MW NW OW QW S U U Q Y x Y U DU 2Y KY Q U IU Y #Q V Q V V rW @sW sW Q tW BT V Y Y T T Y {W V U Y V T V V Y pT T T m T H T V T T T eT Y ? V %"Y V e V "Y R R HR R $V %T %V 2&V uT T T &V @ T T W 'V | T W(V T T W *Y (V W )V h*V +V ,V ;1Y .V /V 0V "3Y W EW rW R !R (T 'Z 3Y +T ,T a-T (R SZ e5Y 6Y 8Y W C,R /T /T -R &0T <1T W AW W `:Y HV T JV ;Y >Y Z ?VV PR YDY UR \V EY SIY ^R dV hV KY OY PY rtV W LTY wV UY aW ZY V V \Y _Y /aY cY dV ƔV W ohY >lY `X nY OqY X sY uY V wY m{Y g$X `R qV -&X ~Y V =P P P `P O XO O jO @O O 23 O } & n cO !O P3 m3 - F/ i1 &2 3 >5 6 +: ; < 3 3 a3 3 x3 3 3 3 3 S3 * Z \ ^ 3 3 oq v w vx y y ,z 3 z Wq3 s3 t3 q3 83 ܠ" < 4 4 4 4 4 " O O o4 -{ | } ~ }O ԕ O !# L# y# t 7 p3 5 v3 qw3 Fy3 {3 }|3 R~3 3 3 3 3 Q3 Lj3 '3 3 3 =3 z3 3 "3 h3 U3 ZA0 3 ,3 #3 { x B 3 a3 f3 3 3 3 j 4 ` 4 " " " 4 H .3 v7 =03 z13 c 9 O O > + C 3 7 O # h^ # 3 ߢ - G2 3 x4 t5 }6 7 8 : aO e@ O A qO |G I *K YL {M N O \ 0 S 3 O <3 IB3 ! fO KO " VO MO e3 *3 3 # # # # # # Q# 2g3 O i3 ]j3 k3 k3 Kl3 " ˾" 3 ܴ Q .3 -3 # U# # B3 3 3 3 3 3 3 3 $ T i 3 I3 O 3 3 Z NZ /Z wZ >- P) ) D) ) ) 2P> d) ) D) ) X) ) >) ) B) ) 2) ) ) ) ) V ) EO ܕ" 3" F, қ, ^, , v, ĝ, , , ȟ, ǡ, N, , ͥ, bB , h, B fB B ^, , , b@ c@ d@ e@ f@ g@ h@ i@ j@ k@ l@ m@ xn@ mo@ bp@ Wq@ Or@ Gs@ ?t@ 7u@ /v@ $w@ x@ y@ z@ z@ {@ |@ }@ ~@ @ @ @ @ @ @ @ x@ p@ h@ `@ X@ P@ E@ :@ .@ "@ @ @ @ @ @ @ ݕ@ і@ ŗ@ @ @ @ @ @ @ @ y@ q@ f@ [@ O@ C@ 7@ +@ "@ @ @ @ @ @ @ ۭ@ Ю@ ů@ @ @ @ @ @ @ @ O + @ @ -@ t@ Ƚ@ @ @ + N + @ J@ @ 4@ @ @ |@ @ @ %@ @ @ e@ @ J@ @ 5@ c@ X + + + + + N+ + + G!+ x#+ +&+ (+ ++ D.+ 0+ 3+ 54+ 4+ ?5+ 5+ L6+ 6+ \7+ 7+ i8+ 8+ s9+ 9+ :+ ;+ ;+ <+ <+ @ @ L>+ >+ ^?+ ?+ p@+ @+ ZA+ A+ VB+ B+ dC+ C+ uD+ D+ E+ F+ F+ G+ G+ H+ H+ #I+ I+ )J+ J+ /K+ K+ =L+ L+ KM+ M+ _N+ N+ sO+ O+ P+ Q+ @ C A Q+ Q+ TR+ R+ $S+ S+ S+ \T+ T+ 6U+ U+ V+ qV+ V+ IW+ ?_+ _+ -`+ `+ -a+ a+ A A A A A A A A A N A A & A A A A A t A A [A A ]k+ 2l+ m+ m+ n+ o+ r+ [s+ t+ u+ 0w+ zx+ A A ^A A A 5A A A bA %A A A f A & A A A B!A "A $A &A 'A ^)A +A ,A #.A /A 0A 1A 2A 3A 4A 5A 6A 8A 8A :A ,;A @<A 4=A N>A t?A @A AA BA CA EA AFA }GA HA IA :KA yLA MA NA -PA iQA RA SA &UA eVA WA XA ZA U[A \A ]A _A Q`A aA bA dA AeA fA gA hA =jA |kA lA mA 5oA spA qA rA 0tA nuA vA wA |+ +yA 4zA @{A I|A U}A ^~A jA UA CA .A A A A A *A ǏA gA A A A A A A A A A A A tA rA }A rA jA BA A A ]A A A aA A A IA °A %A A ѴA =A A A A ŻA A _A A A A lA A A A A A A A mA _A <A A A 3A tA A A &A }A A A &A A A HA A *A A A A A A A xA _A CA *A A A A A A {A .A A qA ?A A A A OA (B B B 9B B B B z B DB B B "B B 3B B mB B B B h B ; B !B !B "B y#B O$B %%B &B p(B *B {+B --B .B q0B (2B 3B 5B l6B 7B 9B Y:B ;B <B 5>B ?B @B ADB GB KB G\B _B cB fB }NB QB fUB XB iB ]mB pB .tB wB yB {B QB ĂB 6B x8 v8 t8 r8 p8 q8 r8 s8 t8 u8 s8 q8 p8 o8 n8 m8 o8 q8 s8 u8 w8 v8 u8 s8 q8 o8 m8 n8 o8 p8 q 9 r9 p9 n9 m9 l9 k9 j9 l9 n 9 p 9 r 9 t 9 s 9 r9 p9 n9 l9 j9 k9 l9 m9 n9 o9 m9 k9 j9 i9 h 9 g 9 i 9 k 9 m 9 o!9 q"9 p#9 o$9 m%9 k&9 i'9 g(9 h)9 i*9 j+9 k,9 l-9 j.9 h/9 g09 f19 e29 d39 f49 h59 j69 l79 n89 m99 l:9 :9 @;9 ;9 <9 A q<9 =9 v=9 I9 K9 AL9 M9 N9 R9 T9 U9 V9 |Z9 ]9 za9 s9 v9 z9 }9 d9 h9 l9 o9 9 9 9 9 9 59 p9 9 9 9 y9 ї9 X9 И9 N9 9 9 9 #9 9 9 9 9 9 m9 9 c9 ڥ9 H9 ɦ9 9 09 9 &9 9 9 9 9 9 59 9 ߰9 9 !9 9 9 O9 ų9 69 9 9 9 9 X9 ÷9 -9 9 9 t9 9 P9 <9 '9 O 9 O l9 .9 O 9 )O 9 O 9 d9 =O 9 9 9 9 "9 9 "9 9 9 9 9 9 9 9 9 9 9 9 9 r9 9 =9 9 9 _9 9 >9 9 s9 9 u9 9 Q9 K9 9 9 9 9 9 9 9 9 9 9 9 M9 9 99 9 E9 9 /9 9 ,9 9 A9 9 9 w9 9 9 t K9 9 ί % ٰ 9 9 f9 9 9 [9 9 9 9 s : : : : : i: : : : - : : z : $: : z: : : : : : : : : - : E : = : m : !: ": #: $: %: ': 1(: !,: g-: .: /: 91: 2: 3: 5: ]6: 7: 8: /:: u;: <: >: P?: @: A: %C: kD: E: F: CH: I: J: L: aM: N: O: 6Q: R: S: U: ZV: W: X: 1Z: y[: \: ^: T_: `: a: /c: t h: [i: %j: j: Qk: k: l: l: u 3 P m: ?n: n: o: p: p: q: q: q: \r: r: .s: s: t: lt: t: wu: u: Jv: v: !w: w: ,x: x: y: ty: y: yz: {: {: W|: |: I}: }: 6~: ~: n: : : }: : : : : : |: : : : y: : : 1: ԇ: v: : : : : : : Ϗ: ΐ: Б: : : ϔ: Ε: Ж: : (: : : .: : : m: Т: : : : s: é: 9: : ): : : K: : : : j: ̸: : g: : : y: c: -: : : : : : : `: : : 0: : : *: X: : H: : : : : N: F: A: 9: 4: ": : : : : : : : : : <: : : k: ?: : : : : L: : : : s; 8; ; ; ; G ; ; \ ; ; ; a; ; ; ; ; a; A; ; ; ; ; ; E ; ; "; $; %; y'; ); *; ,; -; </; 0; 1; G3; 4; 5; A7; 8; 9; k=; @; TD; U; /Y; \; `; G; EK; N; >R; c; f; rj; m; Sq; s; u; /y; |; (; ; ; ; %; ; ; ; ; ; v; R; ; +; ; v; X; Ǎ; 7; ; &; *; ; ; -; ; ~; ; [; ֔; ̕; K; 8 8 k' _8 8 }8 C h % Em' m' !n' n' -o' o' Np' p' 'q' q' Ar' r' s' rt' Gu' %v' w' w' 98 8 8 ~8 8 |8 8 E8 8 E8 F 2 ! x' (y' y' y' 7z' z' z' 8 8 8 $ r n j E8 |' }' ~' ' G' ' AB UO RO B ZB B B B ېB B B B pB [B 8O B oB B B hB B B 8B B O TG, tJ, M, P, S, V, +O ;B bB B VO B xO ]O B PB B B 3B B 1B UB h, k, Im, o, B B ZB B ͉, , , ), B DB B aB d) ) ) b) ) ) `) ) Q> ԹO O O R> S> S> CU> V> W> Y> bZ> [> \> @^> _> _> `> "b> Mc> xd> e> f> h> 0i> j> (l> m> o> .q> r> t> v> w> Py> z> B|> ~> > ?> Ă> > > ʇ> R> Ŋ> 8> > > #> > o> > > > > > > ;> ڠ> V> > > A> > Y> > > > O> > > > Z> > t> > > -> > L> > > => > a> > > > > .> +> > > d> > > > G> > > > k> => > ^> > > > > 6> > > '> > :> D5* -7* 8* :* *<* >* ?* {A* > 5? O O O O ? ? ? ? .? ? O O O O 0? ? e? ? r ? ? ? "? #? S%? &? ?(? )? +? X,? -? /? 1? S3? (5? 6? 8? :? g<? >? ?? bA? \C? E? F? H? J? ;L? N? O? Bl* ym* n* P? (R? FS? T? U? ,W? SX? Y? y* rz* *{* Z? {* |* E}* [? \? w]? s^? -_? _? `? 1* f* fa? b? b? c? d? e? f? Pg? * * * * Z* G* >* * َ* * v* `* )h? eh? ti? ,j? j? Ak? k? `l? l? m? in? o? * -* ɔ* ]* * w* * * 7q? * * q? r? Zt? v? x? z? }? ? ? ? ? ? * '? I? _? ? ? ? ? j? ? ? p? ? ? 1? ? !? ? t? ? ? q? ? ? )? ? ? ֲ? T? ? s? ?? ? d? ? T? ? ? ? ? ? ? d? ? ? ? k? 6? ? Y? ? ? *? ? S? ? 5? ? z? ? ? b? ? ? ? ? I? B? ? ? o? k? ? ? ? @ @ 6@ @ @ Z@ S @ @ @ @ @ j@ 6@ @ [@ @ @ /@ @ Z @ @ '* * * x* * * * s* !@ "@ L$@ &@ w'@ )@ z*@ 8,@ -@ A/@ 0@ 2@ v3@ .5@ 6@ +8@ 9@ S;@ <@ V>@ ?@ A@ RB@ C@ AE@ F@ H@ I@ J@ uL@ M@ sO@ Q@ S@ T@ V@ ^X@ aZ@ \@ ]@ _@ Ra@ * * * + B+ B+ + + 4 4 4 4 4 ۊ4 Ջ4 ό4 ɍ4 Î4 4 4 4 4 4 4 4 4 4 }4 x4 p4 h4 _4 V4 M4 D4 >4 84 24 ,4 &4 4 4 4 4 4 4 4 4 4 4 ۮ4 ӯ4 ˰4 ±4 4 4 4 4 4 4 4 4 4 w4 o4 g4 _4 W4 R4 M4 H4 C4 >4 64 .4 %4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 $ $ $ O $ $ $ !$ $$ '$ *$ x-$ 4 n6$ 6$ 7$ c7$ 7$ 7$ T8$ 8$ 8$ C9$ 9$ 4 4 4 34 4 n4 9$ :$ F4 4 34 5 "5 5 5 5 &5 5 ! 5 5 5 q$5 '5 _+5 .5 15 C yE$ ;35 F$ G$ H$ I$ s65 մO 95 ;5 @5 F5 H5 I5 lK5 K5 P5 cO U5 W5 Jg$ ^5 `5 i5 m5 o5 r5 v5 x5 b{5 }5 5 5 P5 5 K5 Ͳ$ S5 D5 ʵO o5 5 5 5 0O "5 5 $ 5 5 -5 $ ?5 $ *$ $ $ 6p $$ j$ 5 35 ʹ5 J5 ǵ5 G5 Ķ5 >5 ȷ5 V5 ߸5 i5 5 _5 f5 5 m5 5 h5 5 d5 x5 5 5 5 5 5 5 5 5 5 w5 $ m$ 5 /5 5 U5 $ $ 2$ $ 5 5 5 5 :5 q5 5 e5 j5 o5 t5 y5 x5 5 5 5 5 c5 5 a5 5 ?5 5 /5 5 5 5 J$ $ $ $ % % % % x% O% 5% % % % [% % % A% !% % [ % % % !% D#% %% &% (% G*% ,% -% z/% ,1% 2% 4% l6% %8% 9% S;% 5 2?% p@% A% B% D% ME% F% G% I% J% NK% BL% M% N% O% +Q% .R% S% S% T% U% V% rW% VX% ;Y% Y% Z% [% \% ~\% v]% V^% ^% _% a% !b% .c% ;d% We% qf% g% yh% i% \j% k% ul% m% n% 5 _5 5 5 ?5 5 r5 J5 5 5 y5 E5 6 6 6 L6 6 6 N6 6 6 0 6 6 x6 6 q6 6 6 6 6 6 6 6 6 6 6 + 6 B 6 9 6 V!6 "6 #6 $6 %6 \'6 )6 §% % % % +% % Y86 % % $% % *% % 8% % *6 2-6 /6 :6 ];6 <6 =6 ?6 \@6 A6 B6 "D6 aE6 F6 G6 I6 `J6 K6 L6 &N6 eO6 P6 Q6 "S6 dT6 U6 V6 *X6 iY6 Z6 [6 &]6 h^6 _6 `6 .b6 pc6 d6 e6 2g6 sh6 i6 j6 9l6 zm6 n6 o6 @q6 er6 s6 t6 u6 v6 w6 \y6 z6 r% a}6 ~6 % 6 6 u6 p6 6 % j6 6 6 _6 }6 o6 6 % {6 6 6 6 6 6 6 7 7 7 H-& 7 7 1& 7 &7 y7 7 #7 7 7 ;& ~7 7 7 7 $7 %7 K& '7 (7 0*7 .7 D07 27 37 157 77 87 s:7 R67 ;7 _=7 >7 ?7 @7 B7 ]D7 E7 ?G7 K7 0M7 N7 P7 fy& z& lQ7 }& 8T7 U7 ~~& X7 .Z7 [7 ^7 y`7 Y& h7 *j7 6p7 q7 ^s7 z7 {7 & k7 77 7 e7 & s& & ~& 7 Y7 & z& & Ρ7 & :7 ̤7 ' _7 7 7 y ' 7 7 A' .7 ԯ7 k7 7 / ' 7 Ҷ7 7 7 07 7 W7 87 7 7 K7 7 7 T7 7 ]7 7 7 7 7 !7 7 7 *7 "7 7 7 7 7 7 7 7 D7 7 7 57 7 7 _7 7 7 s7 7 B7 7 7 v7 7 E7 7 7 .7 v7 7 7 G7 7 7 8 8 8 8 w8 `8 U8 58 8 8 5 8 y 8 8 8 48 8 8 8 @8 8 "8 k8 8 S8 8 8 8 8 8 !8 "8 #8 $8 q%8 X&8 B'8 )(8 )8 *8 +8 -8 K/8 08 28 q48 &68 78 98 ;8 [=8 %?8 @8 B8 fD8 $F8 H8 I8 K8 M8 N8 P8 Q8 zS8 U8 V8 fX8 <Y8 Z8 Z8 [8 \8 s]8 5^8 _8 _8 a8 8c8 d8 If8 g8 i8 Hk8 m8 n8 o8 Oq8 r8 s8 Eu8 v8 w8 *y8 ~z8 {8 ?8 8 8 Z8 ˚8 98 8 8 8 s8 8 8 8 8 V8 8 8 8 8 8 p8 B' C' 9D' E' 8 z8 8 8 qG' I' J' HL' B8 8 8 8 M' N' O' P' }Q' R' # # w# # d# - uo# e4 p# p# q# => ;r# r# "@ s# ,t# t# R u# fv# <# M=# t># ># ?# @# A# nB# B# " W &Y )w# ` 2h x# # Jy# # " i# # "# # B# ʉ# h# # &# # # # # # # -# |# Й# C# D# `H# # # Q j {# G {# & # # # %# N" 1" S" " " .z# 0{# 9 # S|# " " }# G ) * , M- . / W0 0 " P [" o" ," Q " gR " U V [# *# # &m " m " # L # H# uI# ]" " " " " |" # # I# J# K# R" *!# !# 9L# IM# N# " " " " '" %" "# t## N# O# P# ." x" " *" " P" H$# J%# xQ# oR# S# T# " " " <" " i" R&# '# )U# U# V# 9" " N" 4w " " '# (# uW# RX# Y# " )# c*# YZ# " 9[# \# " " " " " " 4+# ,# \# ]# ^# _# " " #" " O" T # ,# -# P`# a# a# d# @# V# )# x# s# .# _/# b# Vc# yd# y# 00# 0# 8e# 6# 1# 2# e# H3# 3# f# # 4# 5# tg# h6# h# i# # # 9 # # # # 7# 8# i# j# ! # 9# 9# *l# l# x# # # # # # N:# :# Rm# m# n# # ;# /<# }# y E# e# { # D ] D T G B d uZ V V mV BP KS P P mP P 4P 5Q %U V&U &U pU ]'U (U rU sU ,U .U 60U 5uU 2U 2U vU vU 5U wU IZ Z fZ }U ~U kU 9U U U >U >U ?U U U BU CU KEU `P P U S @U U ؐU ְS U U U U Z S SZ .U U X U U U mU Z 5U U T MU U U 8S U VS (S QU T #U U U U S S U U U U ϯQ U DU 2Y qZ Q U IU Z Z V Q V V V N V V T BT V {V V T V V V QV V T V V pT T 'V m T H T V T T T eT V ? V V e V i!V R R "V #V HR R $V %T %V 2&V uT T T &V @ T T T 'V | T W(V T T L!T (V )V h*V +V ,V -V .V /V 0V u1V 1V W'T R !R (T >3V 4V 6V s8V +T ,T a-T Y:V ;V >V AV CV EV 0.T GV /T [U /T -R &0T <1T 1T b2T 2T HV T JV LV OV uRV ?VV ET XV ZV \V ^V `V NT dV hV kV oV qV rtV T wV zV V xV V V V ikT mT oT qT sT !uT wT yT dV ƔV AV ˛V ͟V áV V T V V V V V >T V {T `R qV V V =P P P `P Z &V V ? 7 o t l ۪ ; 6 1 ; ɴ 1 i ɹ h U C 7 n O O v k A ; b j ) m K " i F P $ 2 e P " 2 + 0 ] C 2 R ? v >- [ I V q ܕ" 3" p" " \" җ" < S ( H" ( R " " u" " E i p " [ % P { E s = k 5 c - X % M { E w E < j j } h d Z S L b z X ) M # W / u! ]" J# # 8$ $ F% % 2& & F' ' !( !) :* + :, , . j/ j0 1 V2 3 F4 ^5 6 o7 `8 Q9 E: 9; < < .> z? @ A B !D E F (H .I J K L WN O P Q DS <T U W HX Y Z \ \ E^ _ ` a b c e df fg h i j l m n o Tq Fr s u u v {w :x x y xz !{ { | ~ Z x a L Γ F T 1 y Ե G W \ ʣ ޠ # ٤ j z ۧ < ` t x O R L N r M = 1 c 3 m a B m l J u t R 6 r v 6 .! " $ o% & & @' ' w( ) * + p- . [0 1 D3 $4 5 5 6 7 8 r9 ]: E; -< = > ? @ A B +C 6D >E FF NG VH aI lJ tK |L M N O P Q R S T U V }W "X X jY Z Z b[ \ \ ] ^ _ z` $a a vb #c c }d (e f fh j k Dm n p q zq q jr r bs s t u v w x z { | | } {~ L 4 e J / . < H Y j { ݒ 4 ٓ ~ # ƕ n d b d [ 6 إ y 5 ' m O / ܳ * A X o Y 1 ۿ R . M t = U p @ b , D Y n K k @ f . R a R ^ p % ` D ] y $ { ! m" # $ % & ( *) :* * + S, - - u. / / 0 1 y2 R3 *4 4 6 _9 < ? DC F I -M xP S W [Z ] _ a f /j $n 2r u z U{ {| t} ~ R b ͈ ΐ t < b * ! M" # # $ p% 8& ' ' ( ^) &* * + , L- . . / o0 :1 2 2 3 Z4 %5 5 6 7 H8 9 9 : r; >< = = > t? Y@ @ ,A A A !B B C D E F yG H H oI I _J J CK K 'L FM 3O Q S S T |T T jU U RV V W X Y Z [ w\ j] K^ *_ ` ` Pd g j Fn q t 6x { ~ & y ʈ ފ c } C A v ڝ \ . \ Ѥ f ۥ P æ L ӧ _ P ! + 7 n t ί % ٰ 3 k ն m 8 ӹ k ݻ R ľ 6 n O - e N 4 : @ F L U ^ d j p v t 4 x T } K u 3 P 2 Y C ? = < & / . # , / ` ] S ] } p _ h ; G P # u A w C ` ! " # % D& i' ( ) * + - . 6/ O0 e1 2 2 3 44 4 5 6 7 8 9 ; < ?= i> ? @ A `B 0C D D E lF 5G G H I SJ K L (N O Q R 7T U IW X \Z [ Q] ^ a` a Vc d f g i rj "k k l 8m m n =o p @r s u v x y z { | } 0 > և ! j M * s Ȫ Ԭ x C Ư I Ͱ Q ձ L ò : . h ۶ J $ j a C h % ~ ` r a A A L Y " V F 2 ! t & G $ r n j h J ' a ! ! ! Q! [ ! ]! X! ! ! ! H! ! b! ! ! ! ! / ? j O t q n k h h h h h p! W C ? ! K! A! G ! 6! ! ! O! ! ! x! ! >! ! ! [! ! ! x! ! 6! ! ! ! ! u! ! +! ! ! T! ! ! }! ! ;! ! ! X! ! ! u! ! _! ! L! ! ! j! ! 0! ! ! Y! ! ! z! ! 8! ! ! U! ! )! ! ! ! ! J " " " o" " 5" " " Z" " " w" " 5" " " h" " S" " 2" " " K " " " t " " : " " " W " " " t " " 2" " " " " q" " '" " " P" " " y" " 7" " " T" " " q" " [" " H" " " f" " ," " " U" " " v " " 4 " " " Q " " % " " " " " F!" !" "" k"" "" 1#" #" #" V$" $" %" s%" %" 1&" &" &" d'" '" O(" (" V +" k-" \ ] ^ F" CH" K" =N" c f S" LT" T" U" eU" U" +V" V" V" TW" W" X" qX" X" /Y" Y" Y" LZ" Z" 6[" [" #\" \" \" A]" ]" ^" j^" ^" 0_" _" _" Q`" `" a" na" a" ,b" b" c" uc" c" bd" d" !e" e" e" Ff" f" g" og" g" 1h" h" h" Ni" i" j" kj" j" ?k" k" *l" l" m" `m" m" "n" n" n" Ko" o" p" pp" p" .q" q" q" Kr" r" s" ~s" s" it" t" Hu" u" u" av" v" 'w" w" w" Px" x" y" my" y" +z" z" z" H{" {" 2|" |" }" }" }" =~" ~" " f" " ," " " M" " " j" ɂ" (" " " q" " ^" ƅ" " |" ߆" B" " " k" Έ" -" " " J" " " g" Ƌ" ;" " &" " " \" " " " " G" " " l" ˑ" *" " " G" " " z" " e" yh D ! [" " # 1$ $ e% % ]& & U' ' ( ) ) A* + , - / #0 .1 2 3 4 6 7 8 p9 : ; < = > >@ TA B C D E 7H RJ |L N O P 2S NU zW Y Z [ ^^ ` c Re of g Ij l n Bq ^r zs t u w x y z a{ }| } ~ & ֆ LJ ֎ Г ו ɖ 0 Ŭ ح ( k ɮ [ 8 z U @ y * ۷ = X Ƽ } / E _ { 0 ; = Q n # E i A g H i ; ] 4 M j ? _ 5 Z & p N / \ 6 f b ! w ! ! M! ! %! ! ! n! ! J! ! *! ! ! w! ! W! ! s! ! ! t ! ! ! y ! & ! ! ! .! ! ! )! ! |! &! ! |! '! ! ~! *! ! z! "! ! s! ! ! p ! ! ! o ! ! ! n ! !! !! m"! #! #! p$! %! %! u&! "'! (! )! +! E,! c-! .! /! !1! r2! 3! 4! 5! H7! r8! 9! :! <! =! >! ?! @! &B! >C! VD! G! OI! K! M! O! P! R! U! nW! Y! Z! [! ^! Ca! c! Bf! rg! h! k! m! p! s! /t! ^u! v! w! 7y! ]z! r{! |! ~! 9! ! ʁ! J! \! |! ! ! ! *! <! ]! s! ~! ! ژ! ! ! $! ! ! ! ɢ! ! ! H! w! ! 9! r! ! γ! ! Z! ! ! P! ! ! U! ! Y Į E Ư P հ \ n ~ # Z ܸ f M Һ W ܻ \ r ͽ ( ߾ ; ÿ J + - % 7 b # l - s 7 z ; E O S ] g ( k / } B Y } NO Q p 2 ^ C v J o { S 7 B L > { $ R 3" ~% ( , Y/ 2 5 49 < ? A C D E F G I -J |K L ?M M N &O O AP P gQ T fV X Z c] ` ` a ta Pb 1c d d e ^f f g h i tj Wk k l m cn 9o o 6p q /r fs y z { v} ~ i 8 # $ ` + ϐ = 9 L Q V t b ؛ N 2 m ۠ F ơ F Q ԣ T Ҥ Z ڥ K j h [ # ] # U & P a Q e N 2 r @ S 1 H P V T \ : = 9 g M u + u ] x & e % ] " 7 & V y 8 c 6 w / S ; ] [ 1 v M ' e G & } 3! 6 8 R* + . >0 S2 Z5 >E G l; 9= > P@ B C " a# {$ % & ' ) H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ a b c bd e f g h Aj k Ul l |n p }q s t )u u Yw x y z { | F~ p ̀ + I Dž $ ߆ < ψ 9 $ G Ր ` ϗ m ] 9 ˞ ( 2 ] 5 ̫ b 5 ٰ t @ Դ a & ɹ ' = [ | ' 6 H W ^ e q ? i 2 > 2 A 4 8 = $ & } 4 [ Y ) J T 8 / 2 5 9 D< h? B E ? S" % ' h* - H L GO R U Y W\ _ b !f ci l o q s t u Rw x Oz { J} # ~ " m ʅ @ ` Ƙ ( Z $ Y } 9 a I m ) Q y 9 ] A i + S ~ I } O k \ n w " < T b k m g ! 3 F k ( \ v J V * X z / _ & 6 C S l q w k - Q u 1 Y K _ s 9 l ( P P [ i! ! " # # J$ $ t% & & ' ' T( ( }) * * :+ + l, - - -. . H/ / }0 1 1 72 2 g3 4 4 55 5 a6 6 7 )8 8 S9 9 l: : {; ; < = = )> > \? ? @ %A A IB B rC D D 7E E `F F G (H H RI I wJ J K 2L L [M M N O O RP P Q R R ,S S eT T U %V V QW W X Y Y DZ Z X[ [ \ "] ] G^ ^ s_ ` ` ;a a fb b zc d d De e if f g h h 3i i >j j Ik k [l l zm n n $o o 8p p Gq q Vr r fs s }t u u v v .w ~ 3 { | | } } ~ w 3x x Ry y yz z * ƃ V w Z F 8 ܈ $ Ȋ o ^ M < + ғ d @ ї _ ~ ? כ o 6 ͞ a C Ӣ c ' > ȧ \ F ֫ f ? ԯ f 9 dz X z H { : κ e C Ӿ f , C Z p 2 ] } 3 V v : h . \ > p - U } @ l 5 e " X - tY 8Z l[ ] \ ^ _ ` a b 7 : dc Te *B pf g P ` * x R ( Bh h ui "j j p +q q r R v ~S T U i u Y [ j bv c_ / 1 [3 ĝ" " " ܠ" 6" " " 8" " " " " " h" ɮ" !" ~" -{ | } ~ v w zfO jO d # E> , 5 7 58 8 R: j; 0= D> \? @ A xC D E F k k l Xm 6n n o <p l }H I GJ J K ) p uL N O &Q R T U LW X Y [ \ |^ _ a b Re qp f Ch i x { { ~ " ó" " ~" " a" " " r" 1 1 3 6 7J v7 "8 : ; a< < = > ? ;T ? @ 3A 4B 8C C 7 $D E J v v p wG H I J }6 7 8 : KK L N N D AP # AR cU V W }Y Z [ \ ^ \ 0 O ? $ / " ] . N #O t$O 3&O "%O I'O {(O nO lpO oO \qO GrO 3sO -)O )O +O }*O ,O -O !tO uO tO vO |wO bxO |.O /O 0O /O 1O 2O JyO zO yO {O m|O E}O }3O 4O >5O 6O 5O 7O 9O ~O O ~O O jO LO 9O m:O <O ;O *=O T>O 0O O كO O O gO ?O ?O UAO P@O _BO CO MO ͉O O O O pO =DO DO FO EO GO HO RO O O ΏO O O IO eJO vLO <KO MO OO O qO aO O O O OO PO ZRO <QO }SO TO ʘO |O O yO qO jO rUO 'VO WO VO YO JZO eO O O O O O ZO [O ]O \O ^O `O ܣO O O O O O `O aO jcO LbO dO eO O eO qO bO ZO SO L ~ ( - : * ; ^ < O p > " ˾" T 0 ύ n Q ߤ ] G BP KS P P mP P 4P 5Q `P P S @U U ؐU ְS U U U U Z S Z .U U X U U U mU cZ 5U U T MU U U 8S Z VS (S T #U U U U S S U U U U ϯQ U DU 2Y qZ Q U IU Z QZ V Q V V V N V V T BT V 0Z T T V V V QV V T V V pT T 5Z m T H T T T T eT ܜZ ? V V e V i!V R R HR R $V %T %V 2&V uT T T &V @ T T T 'V | T W(V T T L!T (V )V h*V +V ,V -V .V /V 0V u1V 1V W'T R !R (T "R 7Z +T ,T a-T ֟Z Z 0.T C,R /T /T -R &0T <1T 1T b2T 2T HV T JV LV OV Z ?VV ET XV ZV \V oZ NT dV hV kV oV qV rtV T wV zV V xV V V V ikT mT oT qT sT !uT wT yT dV ƔV AV ˛V ͟V T V V V V V >T éZ {T `R qV V V =P P P `P Ѵ L [ 2 ӱ j ` O /j2 O !O ="O #O ۻ X - tY 8Z l[ ] \ ^ _ ` a b 7 : dc Te *B pf g Bh h ui "j j p +q q r R v ~S T U i u Y [ j bv c_ / 1 [3 ĝ" " " ܠ" 6" " " 8" " " " " " h" ɮ" !" ~" -{ | } ~ v w # E> , 5 7 58 8 R: j; 0= D> \? @ A xC D E F k k l Xm 6n n o <p l }H I GJ J K uL N O &Q R T U LW X Y [ \ |^ _ a b Re qp f Ch i x { { ~ " ó" " ~" " a" " " r" 1 1 3 6 7J v7 N N ; a< < = > ? ;T ? @ 3A 4B 8C C 7 $D E J v v p wG H I J }6 7 8 : KK L N N cU V W }Y Z [ \ ^ \ 0 O ? $ / " ] . N N N {N N N ;N ͡N fN N N N N ON PN N N N ;N N ֨N N kN N N +N VN N N N N N N N KN N N N {N N DN N H ο / s uN FN N N !N O N XN N N V ,N ´N N QN vN O N N (N N ֹN DN mN HO N N %N N սN CN lN O N N $N N N BN kN vO N N #N O 0O O O O XO ~O O O 9 x P >O N N HN N O N N LN N ( [ vN " N 7N N N t O kN N N 1N dN N N O N 4N N hN N N :N O N kN N N N 8N qN O O N N AN O ! O O O O YO O .O O O gO O O ZO O PO N N vN N O ]N N N >N {N N N O N ZN N ] N N N 4N :O N AN N QN dN N N O |N N N N +N N N VO CN N ZN N N hN N O N N !N tO O O O ' O O O D O O # Q } ] O N N 6N ]N O N |N N N E g ,N L ~ ( - : * ; ^ < O p > " ˾" T 0 ύ n Q ߤ ] G &N >(N )N E7N *:N 4=N "@N CN FN HN >LN FON 6RN ;UN XN ZN d]N Y`N bN M eN ,jN kN ~mN SrN T+N R4N M 5N ,N <-N -N 2uN yN CM M M vzN %N 3N N M M N M sM EM M M /N N tN N N N TM JM M M M M sM 'M M M M M M 5M M M oM M M M M n N FN N N N N N lN N N N N N w N N } N =N 1N N N `N N N N N N N cN #N N @N N N N N N ГN N HN bN N N 2 N N T!N R N r"N M#N 6%N k$N ӌN ʍN N aN P P ,X mP %U V&U ,X V V DV 7zZ V V V V V nV uV qV nV a-X +1U t3U N4U O.X /X B0X 1X ~U kU 9U U 2X u3X 4X 4X ?{Z "}Z `P P i5X P 5X 7X I;X _>X ?X AX KBX CX DX FX GX HX >JX KX ILX MX MX PNX OX PX QX RX SX VUX uVX o S WX S S ~S 1S S WS S S VXX YX YX tZX 0[X [X o S \X S &]X ]X D^X _X _X `X aX qbX PcX OdX =eX S ,fX S QS S S gX gX hX biX 7jX jX kX hlX mX mX nX ^oX pX pX S 4 S S O S pqX qX rX 4 S ^sX S %!S ktX tX xuX vX vX wX xyX zX |X ~X XX X X |1Q >X X V V 1 l1 G1 1 i1 1 1 1 1 61 1 _1 1 %1 1 w1 1 1 1 1 M 1 1 1 3 1 1 1 !1 "1 #1 $1 n%1 '1 )1 +1 ),1 ,1 -1 -1 '.1 .1 O/1 /1 r11 11 21 &31 Y01 01 31 @41 41 K51 51 q61 61 81 81 91 :1 l;1 <1 =1 ^>1 5?1 @1 A1 c0 P0 8/ / / l' f/ / y/ / / i/ / / / W/ / // / / / / N/ / &/ / / / / / D/ / s/ / m/ / ./ / / / 5/ / 9/ / 6 0 0 ,0 0 0 g0 0 m0 0 s0 0 k0 0 ڛ/ / ל/ / Q/ / ˟/ / K/ / ˢ/ d/ / / / / A/ ֦/ k/ / / u/ ,/ / / T/ / ȭ/ / ,/ ϯ/ r/ / / ^/ / / C1 D1 PE1 P/ / / 0/ ж/ s/ / / F1 \/ / / 9/ ػ/ z/ / / F1 G1 gH1 "I1 I1 J1 YK1 L1 L1 `/ / Կ/ / H/ / / / </ / / M1 2/ / / 9/ / M1 ON1 / x/ N1 / &O1 O1 O1 EP1 P1 Q1 mQ1 Q1 :R1 R1 S1 T1 T1 1U1 U1 .V1 ]/ / 2/ / / g/ V1 / 3/ W1 / ?/ / / U/ / / t/ W1 )/ / / </ / / U/ / |X1 MY1 / c/ / / U/ / / P/ / / C/ / / 5/ / / Z1 Z1 [1 x\1 A]1 ^1 ^1 _1 -/ / / / M/ / / / h' ^' X0 . )Y0 Z0 Z0 [0 . s. R. 1. . . . I]0 . . T. . . !. . M. . V. . Z. . U / / W/ o. y`0 a0 c0 -d0 ]0 / / i/ d0 / / / / t / k / b / Y / e0 sf0 lg0 eh0 P / '/ / / / / l/ ^i0 W/ Gj0 j0 k0 k0 k0 Fl0 l0 m0 Wm0 m0 "n0 n0 Y/ Z/ n0 ;/ !/ o0 / / p0 / q0 &r0 r0 Js0 s0 `t0 t0 |u0 v0 v0 w0 w0 >x0 x0 Ry0 y0 lz0 z0 F/ / / 6 / / / F / / / p / % 1!/ !/ "/ n#/ E$/ %/ %/ &/ {'/ (/ (/ t)/ #*/ */ +/ h,/ 5-/ -/ 0 0 % 0 ./ // 0/ 1/ M ?M % 2/ r3/ N4/ & *5/ & 7/ 0 6/ 0 ɘ0 ҙ0 0 0 8/ z& 8/ 9/ & y:/ ܚ0 Û0 ^;/ </ >/ 0 </ =/ 0 q?/ )@/ @/ A/ +B/ B/ C/ dD/ D/ E/ MF/ F/ uG/ H/ H/ I/ J/ RK/ L/ ݠ0 0 L/ l0 0 M/ NN/ O/ .P/ P/ Q/ 0 0 TR/ R/ uS/ ;T/ T/ DU/ 0 0 U/ V0 0 0 E0 0 0 *0 Ǫ0 f0 0 0 E0 0 0 )0 ϯ0 k0 0 7V/ V/ W/ iX/ Y/ Y/ Z/ [/ c\/ ']/ ^& ]/ ^/ _/ }`/ ja/ Wb/ Kc/ d/ d/ e/ nf/ 3g/ g/ h/ i/ j/ bk/ >l/ l0 g0 & {& 6m/ n/ & n/ o/ p/ & q/ & s/ 0 r/ }0 0 0 0 0 t/ & u/ v/ <& zw/ >0 ;0 ux/ Iy/ {/ '0 z/ z/ %0 |/ }/ }~/ I/ / / _/ / / c/ 7/ / (/ / ȇ/ {/ y/ R/ 0 u0 3/ &0 T0 ^/ h0 g0 9/ / Ǝ/ g/ / / H/ f0 30 0 SM 0 / 80 D/ ͒/ 0 {0 X0 0 0 {0 :0 0 0 0 0 r0 0 \0 0 0 A0 0 0 0 0 w0 0 _0 0 M0 0 &0 0 0 0 :0 0 >0 0 0 0 0 0 0 L0 0 *0 / / 0 Q/ Ք/ 8/ 0 _0 / 0 / ;0 t/ 0 / / %0 0 0 ~0 0 b0 0 L0 0 S0 0 Z0 0 / _/ ɘ/ ̴. . # U. Ͷ. . ;. =. . . Ӻ. Z. . . . @. . . ). . 6. . 2h c. . 0 0 # B# < 0 0 0 # # 0 . 0. ç. . m. . . p. .. . B. . د. . . {# & # # .0 c. l. c. &. ( G ] R ! a% G 3. . 3. . . `. e. . . . . . -. . E. S S sT U . . 2. H. \. o. . . . . ӟ. . . . H. . z. ܰ. Z. . `t q ڱ. 4w {. ! . . . Q. p =. P . . . =. n. . . . P. . . s. *. . 4 . 3. . . . . . .. . 6. . . . . P BP P mP 5Q %U V&U &U V V DV V V V V V V nV uV ~V `V V qV nV 60U 5uU 2U 2U vU vU 5U V V fV V =V V ?V ~U kU 9U U U >U >U ?U V V V _U lU U U %U U `P P U V V PV _V pV v@Q w W U W W LQ W W W W .U PW [Z U U W B W #W 4&W )W 5-W \Q τQ Z0W +2W 4W 7W .;W a>W AW IFW ]Z LW U MW NW OW QW S U Q U QW ϯQ Q DU `Z dZ ]W aW dW ~jZ Y Q Q V V rW @sW sW Q tW BT V uW wW T yW {W V |W V T V V >}W pT T ~W tW yW xW T uW T T eT 1W ? V W V e V EW R R "V #V HR R $V %T %V 2&V uT T T &V @ T T W 'V | T W(V `W T W W ȏW W W ڑW ԒW )V h*V W W *W +V ,V fW .V /V 0V W EW rW 5W "W R !R (T >3V .W ͟W 1W +T ,T a-T W ;V KW W .@V @V W mW /T [U W /T -R &0T <1T W AW W W 2R HW GW HV hW W zW W <W ?VV W W UR \V W ?W W <W dV hV W mW W "W mW W OW 8nZ W aW ݆R V V W tsZ W -W rW W wW W X X m X X `X iX X 2X X V X V >T X g$X `R qV -&X )X V =P P `P V &V V c) \d) Vf) 7 o Ph) t l ۪ ; 6 1 ; 7j) m) ɴ 1 r) p) t) &u) u) u) [v) v) *w) w) w) z) @}) ) ) ) ) ) ]) ) ) ) Ҏ) ;) ) >) }) ) D) ) ) ) ) ) ) ) ^) ٢) T) ) m a) K " i F ϧ) |) ެ) E) ) ) ~) ) F) ) C) ) ) Z) ) ) ) ;) ) V) ) I) ) {) 7) ) ) ) ) o) h) `) P) ) D) ) ) d) ) T) ) D) ) N) ) X) ) >) ) B) ) 2) ) ) ) ) V ) ͚, ܕ" 3" F, қ, ^, , v, ĝ, , , ȟ, ǡ, N, , ͥ, , h, , F, ҫ, ^, , , ,V) W) X) X) Y) Z) [) d\) s]) ^) _) `) a) b) G+ + i+ + + i+ + v+ + + @+ + + r+ + N+ + D+ + + + + H+ + + + + + )+ + A+ + + + @+ + n+ ?+ + y+ N+ + ~+ + + T+ ++ + + + m+ + 8 , j, , O, , , , Q, , W , , y", $, q', ^' ;' ' ' ' W' ' ' ' ' ' ' ' [' ' ' ' ' ' ' ' ' ' ' ' ' ' ' A' %' ^' ( ( .( "( p( T( ( ( ( ( ( ( @( f( ( ( ( n( ( *( K( ( s( ( H ( y ( !( %"( #( M%( &( (( /)( *( +( --( .( %0( 1( 2( 44( I5( 6( Y8( 9( :( <( ;=( ->( ,?( ?( @( A( oB( 6C( D( E( F( F( xG( fH( JI( K( yN( P( S( U( X( _[( \( m]( H^( Z_( Ip( q( s( it( u( v( x( y( ;z( L{( p|( }( ~( `( e( a( b( Kc( d( e( f( g( Zh( <i( i( tj( \k( 3l( #m( Nn( ro( ( F( 7( ( ( ( ( ( ( K( ( ( '( ( /( ( ( ގ( ( ( k( %( ( ( l( ( ( ɝ( ( V( ( ʤ( G( ( '( ( ( x( N( (( ( ܯ( ( ( H( ( ( ( 4( ( ζ( ( e( 5( ( պ( ( ( ( ( ( ( f( :( ( ( ( ( d( 8( ( ( ( Q( ( ( ( )( ( ( ( ( ( ݒ ( ( ( s( =( ( ( ( z( N( "( ( ( ( u( L( ( ( ( s( 9( ( ( ( ^( ( R( ( D( ( >( ( 6( ( 5( ( 7( ( =( ( ( ( ( ( ( A( G ) I) J) S) X) \) @) ) b ) ) ) ) ) ) h!) ") #) $) %) ') y+) /) 3) 7) ;) @) zA) B) C) E) E) "G) G) dH) I) I) GJ) J) nK) K) }L) M) M) N) tO) N) N) O) aP) P) NQ) Q) YR) R) xS) T) T) JU) + + @ + N + X + + + + + N+ + + G!+ x#+ +&+ (+ ++ D.+ 0+ 3+ 54+ 4+ ?5+ 5+ L6+ 6+ \7+ 7+ i8+ 8+ s9+ 9+ :+ ;+ ;+ <+ <+ 4=+ =+ L>+ >+ ^?+ ?+ p@+ @+ ZA+ A+ VB+ B+ dC+ C+ uD+ D+ E+ F+ F+ G+ G+ H+ H+ #I+ I+ )J+ J+ /K+ K+ =L+ L+ KM+ M+ _N+ N+ sO+ O+ P+ Q+ Q+ Q+ TR+ R+ $S+ S+ S+ \T+ T+ 6U+ U+ V+ qV+ V+ IW+ W+ 7X+ X+ 9Y+ Y+ >Z+ Z+ C[+ [+ E\+ \+ A]+ ]+ =^+ ^+ ?_+ _+ -`+ `+ -a+ a+ ?b+ b+ =c+ c+ ;d+ d+ ?e+ e+ =f+ f+ ?g+ g+ Eh+ h+ Ni+ i+ Wj+ j+ ]k+ 2l+ m+ m+ n+ o+ fp+ <q+ r+ [s+ t+ u+ 0w+ zx+ y+ {+ U|+ |+ |+ ~+ + + `' A ɂ' b' ք' i' ' ' g' ' ' ' ' ' ' ' A' ' '' ' ' ' ' x' ' ^' =' )' ' ' z' ' p' ' `' ' J' ' @' H' I' E' F' ' B' 2' ' 4' 5' 1' 2' /' ' ' ' ' ' ' ' 7' T' ̭' &' ' ' j' د' @' ' &' ' ' v' ' L' ' "' ' ' ' ' P' ' ' ' ' \' Ƹ' (' ' ܹ' B' ' ' q' û' ' ' ' y' ' ' ' U' ' ' x' ' &' ' ' k' ' ' ' >' ' ' d' ' @' ' ' {' ' <' ' ' w' ' d' ' 6' ' :' ' ,' ' ' v' ' ' ' o' ' 5' ' ' ]' ' W' ' >' ' ' ' :' (' ' i' ' ' {' ' K' ' ' c' ' [' ' U' ' /' ' ' ' ' Z' ' ^' ' j' ' `' ' + W+ + 2+ K+ څ+ g+ + + + + ى+ + I+ Ջ+ J+ + 4+ + + + + e+ @+ (+ + + m+ + [+ Ҕ+ C+ + %+ + + + + + ۚ+ + ś+ + + + + v+ e+ P+ )+ + #+ + + + զ+ A+ + + + + f+ ͩ+ + + w+ ͬ+ /+ + + e+ Ů+ -+ + + Y+ + + {+ ڱ+ ?+ + + a+ dz+ 3+ + + L+ + + V+ ¶+ '+ + + G+ + + R+ + + ]+ + '+ {+ + H+ + + a+ ̽+ "+ + + Q+ + 4+ + + e+ + a+ + K+ + + + + + + r+ + 0+ + + N+ + 0+ + + z+ + t+ + n+ + + t+ + <+ + =+ + -+ + + + n+ + B+ + + + + + + V+ + R+ + V+ + D+ + k' 6l' l' l' % Em' m' !n' n' -o' o' Np' p' 'q' q' Ar' r' s' rt' Gu' %v' w' w' F 2 ! x' (y' y' y' 7z' z' z' $ r n j [{' |' }' ~' ' G' ' *, +, ,, |-, @., 7/, /, 0, x2, =3, 4, 4, 5, 5, 86, 6, )7, 7, :8, 8, -9, 9, r:, :, =;, ;, ;, d<, =, =, >, ^?, @, @, A, A, B, YC, (D, E, F, TG, tJ, M, P, S, V, W, Y, Z, H[, O\, ], ], ^, r_, "`, `, a, Bb, Kc, c, e, e, e, Uf, g, Xg, g, bh, h, k, Im, o, r, r, fs, s, @t, t, u, }u, u, ?v, v, v, 9w, w, w, Zx, x, y, 5" @6" Hy, y, !z, z, z, J{, {, |, |, |, ]}, }, ~, |~, ~, D, , , , , , ", , , p, ƃ, , s, ʄ, (, , , 1, ~, ؆, &, t, RB" B" B" IC" C" C" ZD" D" Ç, (, , , g, ͉, , , ), c f d) ) ) b) ) ) `) ) ) _) ) ) `) ) ) a) z) ) ) ) %) t) ) ) d) ) ) Z) ) ) g) -) ) ) Z) ) ) _) ") ) C) ) * * * Q* * ^* * * * * * * O* * p* e* * * * * S!* 0#* $* &* (* a** ,* .* /* 1* T3* D5* -7* 8* :* *<* >* ?* {A* C* C* jE* F* kH* I* K* L* N* P* P* OR* S* NU* V* mX* Y* j[* \* ^* e`* -b* c* e* zg* Oi* k* Bl* ym* n* o* p* r* as* t* v* 2w* |x* y* rz* *{* {* |* E}* ~* @* <* * * u* 1* f* * ۅ* * Z* * * * * Z* G* >* * َ* * v* `* T* * -* ɔ* ]* * w* * * * * * F* @* I* +* * * * * * v* * ި* * #* * c* * * G* ȶ* l* * * +* ˾* H* * * )* * * X* .* * * * q* '* * * x* * * * s* * * P* * g* * * '* * W* * l* * * * * * * * + B+ B+ + + Kh' h' i' ti' i' Bj' j' R' S' S' S' \T' T' <U' U' V' V' V' OW' W' #X' X' X' ]Y' Y' %Z' Z' Z' ][' [' G\' \' 1]' ]' -^' ^' (_' _' %`' `' )a' a' *b' b' b' Tc' c' d' d' d' Ye' e' Sf' f' Mg' g' $ $ $ $ $ $ $ !$ $$ '$ *$ x-$ d0$ m3$ J o n6$ 6$ 7$ c7$ 7$ 7$ T8$ 8$ 8$ C9$ 9$ 9$ :$ ;$ <$ =$ =$ N>$ >$ ?$ 9@$ @$ xA$ B$ C$ D$ C yE$ E F$ G$ H$ I$ `L$ N$ P$ HS$ U$ X$ cZ$ z\$ ^$ `$ c$ 5e$ Jg$ ii$ gk$ lm$ Dr$ t$ iw$ z$ |$ @$ $ $ $ $ $ D$ ސ$ o$ s$ $ ~$ $ Ş$ H$ ţ$ $ b$ 5$ $ $ P$ Ͳ$ )$ `$ u$ $ $ $ $$ $ $ $ $ n$ j$ l$ h$ i$ G$ #$ $ $ $ $ $ $ ^$ M$ *$ '$ $ $ $ $ 6p $$ j$ $ $ $ $ $ $ ;$ $ $ $ $ $ $ $ $ $ o$ ($ $ $ $ >$ $ N$ $ m$ $ $ 2$ $ f$ $ $ $ z$ J$ $ $ $ % }% P% 5% % % % % % x% ] % % % ( % " % % % x% % % % % x% O% 5% % % % [% % % A% !% % [ % % % !% D#% %% &% (% G*% ,% -% z/% ,1% 2% 4% l6% %8% 9% S;% <% =% c>% 2?% p@% A% B% D% ME% F% G% I% J% NK% BL% M% N% O% +Q% .R% S% S% T% U% V% rW% VX% ;Y% Y% Z% [% \% ~\% v]% V^% ^% _% a% !b% .c% ;d% We% qf% g% yh% i% \j% k% ul% m% n% o% p% q% r% s% t% v% -w% Fx% 0y% @z% {% <|% "}% N~% b% ?% R% f% y% ~% % % % % % % r% % z% % % k% % ȟ% . >0 % Z5 s% §% % % % +% % ڲ% % % $% % *% % 8% % % c% % % [% % % % s% % % % % % r% 1% K% % % % % i% % % % % R% % % % % % % % % >% % % T% % % % % % % % *% % % % % % U% % *% G% Z% % 4% % % c% % % % % % X% t% % b% % % [% % % S& % % & & & & & f& & & O & ]& & & & & ~& 3& & & z& .& F& & & & & & & & W & !& && "(& "& $& v%& w)& *& i+& 1,& H-& .& X0& 1& \3& 4& 6& 87& U8& 9& :& ;& =& +?& U@& E& G& @& A& C& sH& I& K& L& uN& O& P& Q& VS& T& U& V& W& X& \Z& [& \& jY& ]& _& _& `& a& b& c& vd& Qe& f& g& i& j& h& l& q& r& s& t& u& w& x& fy& z& U|& }& }& & π& & ~~& e& ك& & ^& & & & & & Y& {& & & Ȏ& & t& I& & 6& & Ε& & +& ͙& & U& & & & & `& & {& c& & & & Ĭ& & o& & & & & & g& & e& <& ,& & & & & & & & ף& & & (& & & & & & & & & & & & B& !& ~& `& & & q& & ^& <& & K& /& & & & s& & & & & Y& ~& & & & & z& & M& & %' ' ' ' ' ' y ' A ' ' ' ' A' 6' ' R' ' ^' ' T ' ' / ' !' "' #' $' &' '' 6)' %' p*' +' ,' -' .' /' 0' 1' 2' 4' ,5' K7' 8' =6' :' ?' "A' B' C' 9D' E' qG' I' J' HL' M' N' O' P' }Q' R' ) N) * + , , f F/ i1 &2 3 >5 6 +: ; < LC F F H |J WL ;O P `S T DV Z \ ] N^ ^ b %j oq v w vx y y ,z z I Q d v x 3 # -{ <| | } ~ ( ď \ ԕ O !# L# y# t 7 /# # 9# # L# # # 5 # / z L ` P 2 e _ v x B 8 X ސ $ $ Q ړ q E ~ H v H A D Χ# # N 4 ^# c 9 A > + ! I a # # >' ߢ - G2 3 x4 t5 }6 7 8 : C; L< e@ JC A D # # ۬# M F |G I *K YL {M N O :M U \ 0 v Pp x , S !# # # w# i# # ְ# # # # 8# # # # R# # M .M ƶ# # # M # # # # r# E# ^# # R $ # # $ $ $ {$ # # # $ $ $ $ Y# # # # # # ## $ M $ lM $ a# 4# # . $ B$ M B# # _$ # " # C# # $ y z B{ { } y # v# B 5 # # z Z " $ S% % n& # # # # # # Q# 4 ى " α ֲ r ܴ Q # U# # w D r $ T i ~ = *( BP KS P P mP P 4P 5Q `P P XS ְS ֳS S S S oTZ (!Z $Z c(Z bX τQ +Z -Z z0Z 3Z S S T BT Y 5Z 6Z T W'T R !R (T VZ UY +T ,T a-T 0.T C,R /T /T -R 9Z <1T 1T b2T )Y KXZ :Z ET =Z h@Z DZ GZ ]T Y CLZ T ]T PZ '\2 \2 7]2 ]2 G^2 ^2 s_2 `2 `2 ,a2 a2 :b2 b2 Zc2 c2 ld2 0f2 f2 d2 e2 ӱ j kg2 C qC C /j2 C 2C ԢC ډF !F ƋF 'K CF i 2 2 2 2 2 72 2 :2 2 s2 2 2 F F ?M F M ~M @M M -F F 2 +F ]2 : 2 2 F +2 > 2 IF F fM M M eM F F !F mC F F oC sF tF F O R F ~S 1F fF F F ٝF hF hF jF kF ElF {I y|I }I ^~I EI I I I UC _F t`F `F iaF aF ObF cF cF ndF #eF F 1 lF mF ZnF nF `oF 1 oF qpF pF 1 \qF ijM 1 1 tF tF i uF -vF HC qp >yF IC r Ws %F zC F F ~F ڈF F ĢF .k F I %I I SI ݃I 6F y6F |7F 7F 8F E 9F b1 7J B 9F y:F :F y;F {d1 <F |<F <F :=F =F >F }>F >F Y?F ?F @F u@F @F FAF AF *BF BF "CF ~CF CF LDF DF "EF EF EF OFF FF ,GF GF GF VHF NF UF 'l M F UF pF F HF LF IF IF ~u v v v Qx yF X62 jM lM {oM YpM #qM sM tM tM ZuM {F K|F |F x}F ~F ~F ;F F cF vM wM fxM xM dzM {M j|M (F F [XF }M >YF YF 3ZF ZF y[F U\F 0]F ]F ^F T_F }M OC ~M RC C C C C C yM SC `M M M M GM M (M $C C +C ՅM öM M XM YM UM uM M LM ,C M M M WM TC GM J!C M ܐM !C M CM M M KM M HM #C :$C M M $C M UC їM &C L(C E'C Q)C _M VC M >M *C ÙM +C ,C ̚M M ؼM -C C ^M M #M TM C ؞M M M 7M M /M <C C ZC C M M äM M ץM M M M -M &M M C #M M HM M M M LC %C qC C qM ZM 8M M SM M TM /C 0C nfF K7C F 7C M F M :F GM F F dF F F :2 M;2 F F !F F IF ¸F /F F SgF gF 1 I 5I F F YF ڻF dF F oF F F &F F CF F TF 0 ύ n F S2 W2 M qF M "[2 \C xP BP P P mP P 4P P P 5Q `P P qX X X X v@Q X tX U U U X XQ PX .U U X U U X B W EX 4&W |{Q cX <X τQ X xX X X X nX AW MY LW Y MW NW OW QW S U Y Y Y U Q Y x Y U DU 2Y KY Q U IU Y #Q V Q V V rW @sW sW Q tW BT V Y Y T T Y {W V U Y V T V V Y pT T T m T H T V T T T eT Y ? V %"Y V e V "Y M$Y $Y R R HR R %Y $V %T &Y %V 2&V uT &Y T T &V @ T T W 'V (Y | T Y)Y W(V T )Y W *Y z+Y F,Y -Y (V -Y W .Y h*V R/Y \0Y +V ,V ;1Y .V 2Y /V 0V "3Y W EW rW R !R (T "R 3Y +T ,T a-T (R SZ e5Y 6Y 8Y W C,R /T /T -R &0T <1T W AW W `:Y HV T JV ;Y >Y @Y ?VV PR YDY UR \V EY SIY ^R dV hV KY OY PY rtV W LTY wV UY aW ZY V V \Y _Y /aY cY dV eY W ohY >lY `X nY OqY X sY uY V wY m{Y g$X `R qV -&X ~Y V =P P P `P 23 }3 eM & fM 3 gM hM 3 |iM P3 m3 - F/ i1 &2 3 >5 6 +: ; < 3 3 a3 3 x3 3 3 3 3 S3 * Z \ ^ 3 3 oq v w vx B0 y y ,z 3 z Wq3 s3 t3 q3 83 ܠ" < 4 4 4 4 4 " 4 4 o4 -{ | } ~ ԕ O !# L# y# m3 7 p3 5 v3 qw3 Fy3 {3 }|3 R~3 3 3 3 3 ݘ3 3 3 3 F3 3 Q3 Lj3 '3 3 3 =3 z3 3 "3 h3 U3 ZA0 3 ,3 #3 { x3 f3 X3 3 3 a3 f3 3 3 3 j 4 ` 4 " " " 4 H .3 v7 =03 z13 23 < 4 ^# c ? eM eM > + C 3 7 3 # # 3 ߢ - G2 3 x4 t5 }6 7 8 : = ? e@ A 43 |G I *K YL {M N O \ 0 3 3 IM# ı3 63 &83 63 =93 B:3 J;3 3 3 L3 0<3 =3 <3 >3 ?3 @3 y3 3 z3 b3 @A3 C3 IB3 D3 E3 'G3 3 F3 03 3 0H3 %I3 9J3 3 Ը3 3 h3 PK3 VM3 /L3 fN3 dO3 eP3 3 "3 3 3 DQ3 4S3 R3 9T3 ,U3 "V3 3 D3 V3 3 3 W3 X3 Y3 Z3 f3 k3 ! (3 [3 )3 3 Q\3 Ƥ3 k]3 _3 b3 V3 d3 e3 *3 3 # # # # # # Q# 2g3 h3 i3 ]j3 k3 k3 Kl3 " ˾" 3 ܴ Q .3 -3 # U# # 3 i3 3 ̬3 3 B3 3 3 3 3 3 3 3 $ T i 3 I3 e3 3 3 U0M 0M 1M w1M 1M G2M 2M 3M q3M , 3M B4M 4M 5M 5M 5M e6M 6M *7M 7M 7M h8M 8M b9M 9M .:M :M ;M ;M <M y<M <M R=M =M >L >L 2>M >M Q?M ?M <@M _M _M t`M `M OaM aM bM *M HL L <L L L }L L [L L /L L &L L L @M AM sAM AM 4BM BM dCM BM CM CDM DM 6EM EM %FM O*M bM cM bM cM ;?L ?L ?L e@L @L AL AL AL BL IBL BL ^CL CL #DL DL DL \EL EL 9FL FL FL XGL GL $HL HL <IL HL IL *M +M Q+M +M IL LJL JL KL 'KL KL YLL LL ML >ML NL |NL NL -OL OL OL JPL PL -QL QL ZRL QL RL SL OSL SL 6TL TL SL TL UL UL 8UL VL pVL VL .WL WL WL IXL XL YL dYL YL ZL =ZL ZL _[L [L \L 4\L \L +M ?,M ,M ,M S-M FM O]L ]L GM wGM GM [HM HM @IM M gM ^L ^L ^_L _L `L CaL aL bL %cL cL fdL eL eL IfL fL gL hL dM hL iL iL jL jL (kL dM nL ToL oL 7M M dpL pL }qL 3rL rL sL $tL QM tL YuL vL vL M 3wL yM M wL NxL xL yL WzL {L {L M =|L |L }L ~L -M ~L M PM OL L jL !L ӁL L L M L LL L L tM )L M M ĆL BL ߇L L HL L L % M +L L kL L M L O M M ,L L 7L L L L [ M L &L ÒL YL M L k M M L -L ܕL L iL 0L ϘL M L *L L L RM =L M M ڜL sL $L L L ~L L %M L QL L L M RL yM M L L ,L L L nL L M L VL L L NM WL M M L L 1L L L sL L #M L [L L L M \L eM M L L 3L L L rL L M L WL L L 7M UL M nM L L )L L L eL L M L GL L L M BL E M M L [L L L aL L L DL L L L a M L M M \L L L LL L L ^L & M L L ]L L M L d M M IL L xL 9L L L KL !M L L JL L 3"M L "M h#M 5L L bL "L L L 1L $M L zL -L L $M rL <%M %M L L @L L L vL L h&M L RL L L 'M GL 'M 5(M L lL L L L ?L L (M yL L L dL e)M -M IM IM GJM JM KM mKM KM ;LM LM LM iMM MM 9NM +.M .M L L L L rL L fL L @L L 5L L # M M .M 7/M /M /M L NM OM OM PM PM sL L M @_M QM QM QM cRM RM fSM TM TM 2UM UM hVM VM ,WM WM XM XM XM pYM YM FZM ZM [M [M [M d\M \M C]M ]M %^M ^M U0M 0M 1M w1M 1M G2M 2M 3M q3M , 3M B4M 4M 5M 5M 5M e6M 6M *7M 7M 7M h8M 8M b9M 9M .:M :M ;M ;M <M y<M <M R=M =M >L >L 2>M >M Q?M ?M <@M _M _M t`M `M OaM aM bM *M HL L <L L L }L L [L L /L L &L L L @M AM sAM AM 4BM BM dCM BM CM CDM DM 6EM EM %FM O*M bM cM bM cM ;?L ?L ?L e@L @L AL AL AL BL IBL BL ^CL CL #DL DL DL \EL EL 9FL FL FL XGL GL $HL HL <IL HL IL *M +M Q+M +M IL LJL JL KL 'KL KL YLL LL ML >ML NL |NL NL -OL OL OL JPL PL -QL QL ZRL QL RL SL OSL SL 6TL TL SL TL UL UL 8UL VL pVL VL .WL WL WL IXL XL YL dYL YL ZL =ZL ZL _[L [L \L 4\L \L +M ?,M ,M ,M S-M FM O]L ]L GM wGM GM [HM HM @IM M gM ^L ^L ^_L _L `L CaL aL bL %cL cL fdL eL eL IfL fL gL hL dM hL iL iL jL jL (kL dM kL lL )mL mL mnL nL ToL oL 7M M dpL pL }qL 3rL rL sL $tL QM tL YuL vL vL M 3wL yM M wL NxL xL yL WzL {L {L M =|L |L }L ~L -M ~L M PM OL L jL !L ӁL L L M L LL L L tM )L M M ĆL BL ߇L L HL L L % M +L L kL L M L O M M ,L L 7L L L L [ M L &L ÒL YL M L k M M L -L ܕL L iL 0L ϘL M L *L L L RM =L M M ڜL sL $L L L ~L L %M L QL L L M RL yM M L L ,L L L nL L M L VL L L NM WL M M L L 1L L L sL L #M L [L L L M \L eM M L L 3L L L rL L M L WL L L 7M UL M nM L L )L L L eL L M L GL L L M BL E M M L [L L L aL L L DL L L L a M L M M \L L L LL L L ^L & M L L ]L L M L d M M IL L xL 9L L L KL !M L L JL L 3"M L "M h#M 5L L bL "L L L 1L $M L zL -L L $M rL <%M %M L L @L L L vL L h&M L RL L L 'M GL 'M 5(M L lL L L L ?L L (M yL L L dL e)M -M IM IM GJM JM KM mKM KM ;LM LM LM iMM MM 9NM +.M .M L L L L rL L fL L @L L 5L L # M M .M 7/M /M /M L NM OM OM PM PM sL L M @_M QM QM QM cRM RM fSM TM TM 2UM UM hVM VM ,WM WM XM XM XM pYM YM FZM ZM [M [M [M d\M \M C]M ]M %^M ^M ]8L 9L t;L 4L C5L )7L X ` <L :=L =L /L a0L 1L 1L %2L 2L 2L j3L & ) 0 + , f F/ i1 &2 3 >5 6 +: ; < LC F0 F G0 F ;I0 H J0 |J WL K0 M0 ;O qN0 P O0 `S T DV Z \ ] N^ ^ b %j oq v w vx B0 y y ,z z I Q d v x 3 -{ <| | } ~ ( ď \ ԕ O t 7 0 0 0 !0 "0 #0 $0 %0 '0 )0 +0 ,0 .0 00 |20 Q40 #60 90 90 S:0 Z;0 ` P 2 ;0 =0 e ZA0 _ v x B 8 P0 X ސ $ Q ړ q E ~ H v H A D Χ# # 0 0 4 ^# c 9 0 A 0 > + ! I a # -L # >' ߢ - G2 3 x4 t5 }6 7 0 @0 8 : C; L< e@ JC A D F |G I *K YL {M N O U >C0 \ 0 v Pp x , S 3 Xu r ! hx v " c0 z [0 { } y 0 B 5 0 E0 # z Z 0 " $ 3F0 4 ى " Q0 α ֲ r ܴ Q T0 w D r $ T i ~ = U0 *( ̴. . # U. Ͷ. . ;. =. . . Ӻ. Z. . . . @. . . ). . 6. . 2h c. . 0 0 # B# < 0 0 0 # # 0 . 0. ç. . m. . . p. .. . .L B. . د. . . {# & # # .0 c. l. c. &. ( G ] R ! a% }# G 3. . 3. . . `. e. . -L . . . -. . E. S S sT U . . 2. H. \. o. . . . . ӟ. . . . H. . z. ܰ. Z. . G/L p ts `t q ڱ. V# Rv 4w {. ! . . . Q. p =. P . . . =. n. . . . P. . . s. *. . 4 . 3. . . . . . .. . 6. . . . . F/ LC L L L L L L d UK x B a # >' G2 3 >C0 \ 0 v + L )L L L L @"L H$L U0 - "@ . 6. . L c. . . د. . L +L /K L " " K zK K CK hK K K K K K EK iK K { L zL L y L L L %L &L 'L (L E)L )L s*L +L *K K lK K K RK K K HK K K FK K K UK K K pK +K K K 6K K K K K 'K gK K MK JK GK TK aK [K K K K (J J J ]J J J J VJ J >J J &J J J J J J J {J J gJ J VJ J HJ J NJ J <J J $J J J J J tJ J wJ J cJ J OJ J A K K 3K K :K K @K K FK K RK K ^K K K K K K K K K K K = K K 8 K K K K K K K pK K sK K _K K KK K =K K /K K 6K K K K K }K K kK K mK K [K K G K K 6 K K ( K K . K K + K K 1!K !K :"K "K F#K #K f$K $K p%K %K v&K &K 'K (K (K )K )K 2*K %+K %,K ,K ,-K -K |.K .K /K i/K /K +0K 0K 0K `1K 1K H2K 2K 03K 3K 4K 4K 5K o5K 5K 56K 6K 6K N7K 7K 8K k8K 8K 99K 9K :K z:K :K T;K ;K <K <K [=K =K >K u>K >K F?K ?K +@K @K AK AK AK qBK BK tCK CK wDK DK zEK EK FK GK GK HK HK IK IK IK hJK JK IKK KK *LK LK LK QMK MK NK {NK NK GOK OK (PK PK QK {QK QK YRK RK GSK SK 5TK TK UK UK UK VK ZWK XK XK oYK ZK ZK [K 3\K \K ]K F^K ^K _K 1`K `K aK *bK bK KcK cK )dK .eK eK pfK gK gK shK hK KiK iK )jK jK kK okK kK LlK lK *mK mK nK nnK nK MoK oK /pK pK qK {qK qK ^rK rK :sK sK tK ctK tK %uK uK uK AvK vK vK \wK wK xK |xK xK 5yK yK yK _zK zK /{K {K {K `|K |K /}K }K }K c~K ~K 5K K K K K dK сK BK K %K K K nK K K ?K ܆K yK K K IK K K K K QK ŌK :K K K K K ͏K {K .K K oK K ̓K AK K +K K K K K lK K K @K K K QK K K eK K K K K 'K K K K K JK K K |K MK !K K ðK K hK AK K K ϵK K K KK K ȹK K :K K ȼK K cK 2K K K K K HK K K K K K BK K K CK K K BK K K EK K K kJ lJ XmJ xJ J J #J J gJ ,J J `J J J PJ J J NJ J J nJ I 9J . J qJ J I nJ nJ oJ CJ J tJ I I uI I J fJ pJ FJ =I I *K I I I I JI pJ J J J J NJ ސI SI qJ qJ rJ I I I 7I VI {I I I I I sJ {tJ muJ I ؞I IvJ &wJ xJ I I I أI I *I RI UI XI [I xJ yJ zJ ^I I {J S|J ZI I I I I I !I I ۵I }J }J ~J I I XJ J J I ˹I I 9I 4I 5I 2I I I I mJ %J J I I J ZJ J [I I I I I I I I I qI FI J lJ 7J I I J J tJ I I rI I I I I I I I :J J J I I J tJ 5J wI I %I ZI fI xI I oI XI AI J J J *I cI jJ :J J %I I I /I HI gI I xI nI dI ٓJ J J ZI I qJ HJ J iI I !I GI iI fI cI `I J ҙJ ŚJ ] J J J aJ J [J J J 2J :J HJ R J 7 J J J ޝJ J ~J J J J CJ 3J !J J XJ J BJ {J J J J !J 7J J J J J M J J J (J J m J J c"J #J $J "&J T'J a(J n)J {*J J J J +J ҫJ J FJ 5,J -J .J 0J 1J 2J 3J 3J 4J 5J J ٮJ 6J 7J J UJ J v8J 9J ;J A<J E=J O>J U?J 6@J ʱJ J AJ HBJ bJ ;J J CJ DJ EJ FJ HJ =IJ <JJ ;KJ :LJ J ˶J J J 9MJ J ]J J MJ )OJ xPJ QJ RJ SJ TJ UJ cVJ @WJ ʻJ J ZJ XJ JYJ ZJ J J ӿJ ZJ g\J ]J ^J `J 8aJ =bJ BcJ GdJ J J J LeJ K !K K K K K J xJ J J kJ WJ J J J J }J /J gJ njJ BP KS P P mP P 4P 5Q `P P XS ְS ֳS S S S QY (!Z $Z c(Z bX τQ +Z -Z z0Z 3Z S S T BT Y 5Z 6Z T W'T R !R (T l8Z UY +T ,T a-T XU 8ZU 0.T NT /T [U /T -R 9Z <1T 1T b2T )Y $Y :Z ET =Z h@Z DZ GZ ]T Y CLZ T ]T PZ E l E E lE @E m n [o &p I ^I 7I I p I r I I <I I |I 8v v 'H 5H FH WH H H YH eH tH H өH !H iH H H MH H ۲H +H yH H H {E H ǻH ~H 8H H H `H H H UH H H JH H `H H |H H H H H H H H H H H *H H GH lE jE qE H I I I 2 I HI w I 5I XI { I I I !I "I %I 0'I T)I *I +I -I X.I /I 0I 2I \3I 4I 5I $7I `8I vE _:I <I =I ?I @I @I CAI CI DI FI GI 4HI G hU G G G G j Io l Rq G lG 2G [G G G G G 6 N .G G G :H H H H dH 4H H $H )H X.H 23H 8H <H BE eE E E !E #E &E t(E *E -E v/E 1E AH IBH BH uCH DH DH =EH EH C A E cFH FGH dI HH LH QH ?VH [H _H dH iH anH 2sH wH |H H H kH IH % u $3 2hI hI iI ?jI jI kI LlI lI mI AnI nI koI pI pI *qI qI =%3 '3 )3 ,3 x&F < TrI &tI uI wI zxI yI E i D{I >0F 1F a3F 4F G G G cG G |G OG G mG G G iG E> ,D 1O D D Q D D T D D W D )G G G G BG h i oj k k E HI UJI JI UKI KI QLI LI [MI MI =NI OOI ePI uQI 6 t q n k h h h h h RI W C XI =YI )TI UVI (" V Y YI ^ }\I _I bI c f iEG FG GG cHG Z b HG IG JG KG / 0 3 @4 7 7 8 : 5; ^< LG MG NG PG ]QG RG SG ,UG uVG WG XG DZG [G \G ^G ZaG dG gG 5kG VnG wqG tG wG yzG 9}G G G |G ?G G ōG G KG G ͘G ǚG ћG ϜG %G G G @G G G aG şG )G G G JG G G bG G G G ܣG @G G ȥG !G G G G G hG G G G ٪G =G G G ^G ¬G G G G 9G G G ;G iG G G F F F F QF >C wF C YF F q AF F F +F ^F F F F (F WF F F F #F F 3F F F F ?F F +uD F F yF UF U V :F F G G G G uG @G hc G G G `G G <G G G U G h G UG G !G NG G G G 2 G z G G "G %G I'G {)G +G -G >0G 2G 4G 7G n9G ;G =G )>G >G ?G @G GAG BG BG CG DG ډF !F ƋF 'K CF i 2 2 2 2 2 72 2 :2 2 s2 2 2 F F cC F dC PeC eC -F F 2 +F ]2 : 2 2 F +2 > 2 IF F '2 jF F F F F !F mC F F oC sF tF F O R F ~S 1F fF F F ٝF hF hF jF kF ElF {I y|I }I ^~I EI I I I UC _F t`F `F iaF aF ObF cF cF ndF #eF F 1 lF mF ZnF nF `oF 1 oF qpF pF 1 \qF qF 1 1 tF tF i uF -vF HC qp >yF IC r Ws %F zC F F ~F ڈF F ĢF .k F I %I I SI ݃I 6F y6F |7F 7F 8F E 9F b1 7J B 9F y:F :F y;F {d1 <F |<F <F :=F =F >F }>F >F Y?F ?F @F u@F @F FAF AF *BF BF "CF ~CF CF LDF DF "EF EF EF OFF FF ,GF GF GF VHF NF UF 'l F F UF pF F HF LF IF IF ~u v v v Qx yF X62 JF `LF NF OF @PF PF C C C rQF oRF {F K|F |F x}F ~F ~F ;F F cF RF SF `TF TF VF OWF WF (F F [XF XF >YF YF 3ZF ZF y[F U\F 0]F ]F ^F T_F C C C C C (F F F qC $C C +C UC C ,C C C C [C C #C #C :$C aC C C C C &C &C L(C E'C Q)C EC wC IC C C xC C y*C C ӿC C FC \C <C C ZC C :C %C C C C C C C ^C LC %C qC C F /C 0C nfF K7C F 7C F F :F ưF F F dF F F :2 M;2 F F !F F IF ¸F /F F SgF gF 1 I 5I F F YF ڻF dF F oF F F &F F CF F TF 0 ύ n F S2 W2 F qF F "[2 \C BP KS P P mP P 4P 5Q `P P S cY 3S XS ְS ֳS S S Z S _Z S QY yS S Y Y SU {S S bX τQ Y *Y ;Y Y S S Y S S T BT Y T T T pT T =Y T eT T ;T T R R R %T T uT T T | T Y T T L!T "T #T X G&T W'T R !R (T T UY +T ,T a-T XU 8ZU 0.T NT /T [U /T -R &0T <1T 1T b2T 2T )Y X nX $Y ^ Z NCT ET >Y ?Z KT NT X VT $Y ]T cT Y ikT mT oT qT sT !uT fY X T T T -Z Z T Y T T ]T >T T {T Y E l E E lE @E m n [o &p I p E r r ns t t xu 8v v V8E 9E 9E :E <;E ;E <E f=E >E >E ?E :@E @E AE bBE CE CE jDE !EE EE FE 0GE GE HE :IE IE JE 0KE KE LE 7ME ME NE 0OE OE PE 4QE QE RE ASE SE TE 4UE UE VE >WE WE XE YE x[E ]E ]^E _E aE bE dE *fE ggE iE jE kE mE 4oE qpE rE sE uE xE 6zE {E h g ! U |E }E @E E E #E E 9E E E E E > ;B E DI L O jS W [ _ c g k so r tv y } ۄ ܐ ϔ lE jE qE ߘ s ݣ n \ ر w >z | ~ YE 1 ԅ VE E 2E ИE tE E HE ڞE iE E E ˤE lE E E OE E E E 8E ʲE E E DE E E E NE ݾE rE E E PE vE E E ] * o ۷ ' ZE E <E E E {E E hU V DY [ (^ ` c e qh j E %E eE E E /E nE E E ;E ~E E E GE E E E B E E E E C E E E E A E E E E O E E E E Io l Rq s 2 ju v x Zy z { P} ~ @ 6 N G ~ % ] ͗ = u K E uE u $ w W BE F eE ~ E , E f !E #E N &E g t(E = *E -E ~ v/E T# % 1E *( * - z. / n1 2 e4 5 47 $8 9 ; < > ? C A E ,G LH dI J P V )\ b (h m r Tx } g ] % Ԣ ۣ @ J T ĭ & "4E 5E 6E 67E & I : + E _ P A [ u $3 F F rF (F F F JF F F fF F F F 6 F F F F $ F iF F F 8F }F F F FF F F F R F F , F F \ F F F '!F !F W"F "F #F $F $F J%F %F =%3 '3 )3 ,3 x&F < 'F (F *F +F ,F 7-F -F e.F .F 0 E i /F >0F 1F a3F 4F +D D ND nD D D D AD : G< D D E> ,D 1O D D Q D D T D D W D D yD D D D s E h i oj k k E D j [ f 3 / ? j 6 t q n k h h h h h E W C ? j : G E {E E 9E E E \E E E E E =E E E `E E $E E E AE E E dE E (E E E EE E E hE E ,E E E IE E E lE E 0E E E ME E E pE E 4E E E QE E E tE E 8E E E UE E E xE E V Y [ \ \ \ ] ^ ^ 6` <E c f E GE E E dE E (E E E KE E E hE E ,E E E OE E E lE E 0E E E SE E E pE E 4E E E WE E E tE E 8E E E [E E E xE E <E E E _E E E |E E @E E E cE E !E E E DE E yh ~D 5 aD D D D D nD MD ;D +D D [D D Z b HD 7 4D D D D D ԔD ֕D ؖD חD ֘D ؙD U ךD D -D ԜD / 0 3 @4 6 7 7 8 : 5; ^< {D ֝D 3D D ,D yD C C E G nH ^I MJ >K 2L M N AP Q S T V D DD D D 6D ܧD D D ?D ٭D pD D VD D D HD D D D ED ܾD D D eD D D D D D D r ev y K} P 0 \ ] HD X $ ݳ ? 2 j R : " %D H # G s X D 0D D , h K FD D ) * < H l C } $ D D D # & * - 0 G4 7 @C C !C !C C >C C U R q j 2 # C C +C SC D TD D [ D D D tD D o D D "D %D k)D ,D k0D 3D 7D :D =D {AD DD %HD KKD qND QD nUD XD q\D _D cD fD jD {mD mD lnD nD woD G oD pD qD sD ftD tD tD +uD Q R T [uD U V "W uD vD Y <Z n[ ] ` a hc g aj k m $p dq w z | Q xyD h {D {D 6 ] ޙ " X ĩ ܬ S ϱ ^ M ڻ g & G % # O & " g 2 s % o XC 8YC M1 1 "ZC ZC [C p\C 2 Y]C ]C ^C _C `C xaC )bC C2 2 cC cC dC dC PeC eC [ 2 2 FfC gC : gC hC iC jC kC 2 zlC '2 mC t1 WC 1 mC VnC *oC oC pC qC qC rC sC 1 2 sC T tC uC -vC vC LX wC Y %!2 qxC yC yC ^ c_ 3:C :C |;C 5F 5F :C ϣC C եC C t2 C ɨC C UC 1 1 >1 1 1 0C 1C 2C 3C 4C K<C }=C f>C 1 p1 >1 :?C ?C Y1 AC 1 AC K1 BC CC %EC 1 1 _ oFC rGC HC qp IC r Ws #2 zC zC zC {C |C .k }C YC C C C C QC vB B Ga1 b1 B B NB B B B Xe1 e1 ^f1 B B (B B TB B dB B B B B VB B B PB B fB B B B ls1 s1 B %u1 u1 6v1 v1 EC C C 22 32 5w1 Z1 L C C CC C v v C JC 6C C C sC 9C C C C (C C C bC C C C C KC KC LC MC ONC OC OC PC QC e C C K C C b C C C 1 2RC z { E E 1 1 C 1 C {C C C C OC }C C C C C kC DC C C C C &C qC $C C +C UC ,C C C C [C C C vC tC #C :$C aC C C C C &C L(C E'C Q)C EC wC IC C C xC C +C NC C ӿC C FC \C <C C ZC C :C %C C C C C C C ^C LC %C qC C vC /C 0C ЅC (6C K7C 7C gC :2 M;2 C <2 C ȃ x8C U9C 1 C C C CC C C fC C njC C XC C ŏC sC 2C בC C C C oC Q ߤ IC C C C $C VU2 ӚC cC C bY2 C "[2 \C BP KS P P mP P 4P 5Q `P P S cY 3S XS ְS ֳS S S Y S Y S QY yS S Y Y YY {S S bX τQ Y *Y ;Y Y S S Y S S T BT Y T T T pT T =Y T eT T ;T T R R R %T T uT T T | T Y T T L!T "T #T X G&T W'T R !R (T (T UY +T ,T a-T 0.T C,R /T /T -R &0T <1T 1T b2T 2T )Y X nX $Y Y NCT ET >Y KT NT X VT $Y ]T cT Y ikT mT oT qT sT !uT fY X T T T T Y T T ]T >T T {T Y '\2 \2 7]2 ]2 G^2 ^2 s_2 `2 `2 ,a2 a2 :b2 b2 Zc2 c2 ld2 0f2 f2 d2 e2 ӱ j kg2 C qC C /j2 C 2C ԢC XC 8YC M1 1 "ZC ZC [C p\C 2 Y]C ]C ^C _C `C xaC )bC C2 2 cC cC dC dC PeC eC [ 2 2 FfC gC : gC hC iC jC kC 2 zlC '2 mC t1 WC 1 mC VnC *oC oC pC qC qC rC sC 1 2 sC T tC uC -vC vC LX wC Y %!2 qxC yC yC ^ c_ 3:C :C |;C :C ϣC C եC C t2 C ɨC C UC 1 1 >1 1 1 0C 1C 2C 3C 4C K<C }=C f>C 1 p1 >1 :?C ?C Y1 AC 1 AC K1 BC CC %EC 1 1 _ oFC rGC HC qp IC r Ws #2 zC zC zC {C |C .k }C YC C C C C QC vB B Ga1 b1 B B NB B B B Xe1 e1 ^f1 B B (B B TB B dB B B B B VB B B PB B fB B B B ls1 s1 B %u1 u1 6v1 v1 EC C C 22 32 5w1 Z1 L C C CC C v v C JC 6C C C sC 9C C C C bC C C C C KC KC LC MC ONC OC OC PC QC e C C K C C b C C C 1 2RC z { E E 1 1 C 1 C {C C C C OC }C C C C C OC RC C C C C C SC C TC C J!C !C #C ]UC #C :$C $C UC &C &C L(C E'C Q)C VC y*C *C +C ,C -C /C 0C ЅC (6C K7C 7C jWC gC :2 M;2 C <2 C ȃ x8C U9C 1 C C C CC C C fC C njC C XC C ŏC sC 2C בC C C C oC Q ߤ IC C C C $C VU2 ӚC cC C bY2 C "[2 \C P BP P mP 5Q %U V&U &U V V DV V V Y nV uV qV nV 60U 5uU 2U 2U vU vU 5U /X fV V =V ?V ~U kU 9U U U >U >U ?U V V V _U lU U U %U U `P P U qX X X X v@Q X tX U U U ƂY XQ ݇Y .U U DU U U X B W KY 4&W |{Q cX <X τQ X xX X X X nX AW MY LW Y MW NW OW QW S U U U U x Y U DU 9U gY Q U IU Y Y V Q V V rW @sW sW Q tW BT V Y Y T T Y {W V U Y V T V V pT T T m T H T V T T T eT Y ? V %"Y V e V "Y R R "V #V HR R $V %T %V 2&V uT T &V s'Y T W 'V | T W(V T T W *Y (V W )V h*V +V ,V ;1Y .V /V 0V W EW rW R !R (T >3V 3Y ͟W Y +T ,T a-T ҟY ;V ]Y >V .@V @V e5Y 6Y 8Y W GV /T [U /T -R &0T <1T W AW W `:Y HV T JV ;Y >Y Y ?VV PR YDY UR \V צY EY ^R dV hV KY OY PY rtV W LTY wV UY aW ZY V V Y \Y _Y /aY cY dV eY W ohY >lY Y ϴY `X nY Y X sY uY V wY m{Y g$X `R qV -&X ~Y V =P P P `P V &V V > \d) Vf) 7 o Ph) t l ۪ ; 6 1 ; 7j) m) ɴ 1 r) p) w) z) @}) ) > >> > > Z> > > {> > *#> %> G(> ) ) ) ) *> ) ) C,> ) s-> ;) a.> >) }) ) D) ) ) ) ) ) ) ) ^) ٢) T) ) m a) K " i F ϧ) ) C) ) ) K/> 1> 9> =<> >> A> m4> 7> SD> F> mI> K> Z) N> JO> V) ) I) ) {) 7) ) ) ) ) o) h) `) >- P) ) D) ) ) 2P> d) ) T) ) D) ) N) ) X) ) >) ) B) ) 2) ) ) ) ) V ) B ܕ" 3" F, қ, ^, , v, ĝ, , , ȟ, ǡ, N, , ͥ, bB , h, B fB B ^, , , I; I; I; I; I; L; O; R; U; X; X; X; Y; Z; [; \; `; d; h; l; p; q; r; r; r; r; r; u; x; {; ~; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ^' ;' ' ' ; ' ' r; ; ; ; y; ; ; x; ' ' ; 7; < 9< < Y< < W"< < B < < R< %< V)< ,< V0< 3< 6< ' ' ' [' ' ' ' ' M8< 8< ' ' ' ' ' ' 9< :< ;< << =< >< @< A< 8B< sC< C< cD< D< sE< E< aF< F< bG< G< {H< ' ' ' ' A' %' ^' ( ( .( "( p( T( ( ( ( ( ( ( @( f( ( ( ( n( ( *( K( ( s( ( H ( y ( !( %"( #( M%( &( (( /)( *( +( --( .( %0( 1( 2( 44( I5( 6( Y8( 9( :( <( ;=( ->( ,?( ?( @( A( oB( 6C( D( E( F( F( xG( fH( JI( K( yN( P( S( U( X( H< SK< M< UP< S< [U< W< _[( \( m]( H^( Z_( Ip( q( s( it( u( v( x( y( ;z( L{( p|( }( ~( `( e( a( b( Kc( d( e( f( g( Zh( <i( i( tj( \k( 3l( #m( Nn( ro( ( F( 7( ( ( ( ( ( ( K( ( ( '( ( /( ( ( ގ( ( ( Z< J]< _< b< d< f< _i< l< n< 'q< qs< v< Ox< z< }< < v< < *< G< < g< < 4< a< < < w< k( %( ( ( l( ( ( ɝ( ( V( ( ʤ( G( ( '( ( ( x( N( (( ( ܯ( ( ( H( ( ( ( %< ۠< |< < ֥< w< < < Ȫ< < F< < < Ȯ< < F< < < c< < < `< < < I< < < < "< < << h< < < < < < < < (< Z< w< < < < '< o< < < M< < < +< s< < < N< < < /< w< < < O< < < 0< {< < < S< < < 1< |< < < Z = = = 9= = = = d = = = 4( ( ζ( ( e( 5( ( պ( ( ( ( ( ( f( :( ( ( ( ( d( 8( ( ( ( Q( ( ( ( )( ( ( ( ( ( ݒ ( ( ( s( =( ( ( ( z( N( "( ( ( ( u( L( ( ( ( s( 9( ( ( ( ^( ( R( ( D( ( >( ( 6( ( 5( ( 7( ( E = `= e= m= = = = = = = = = = = = = = y = = #"= #= %= h&= '= )= *= ,= x-= .= B0= 1= 63= 4= 5= ^7= 8= 9= .;= <= == 7?= @= A= B= C= D= XE= JF= HG= 1H= I= I= LK= L= M= O= oP= Q= S= oT= U= !W= X= Y= ][= \= Q^= _= `= a= b= c= d= te= df= Wg= Gh= :i= *j= k= l= m= o= yq= s= t= v= xx= Wz= $|= ~= = = >= != = Lj= = = @= ޏ= = = = e= = = l= K= -= = = ͟= = z= \= >= = = O= ĩ= = <= ޮ= = R= = = c= = = w= = = w= =( ( ( ( ( ( ( A( G ) I) J) S) X) \) @) п= J= = 7= = = = = = ,= = )= ~= = k= = P= = = 2= > /> ) b ) ) ) ) ) ) h!) ") #) $) %) ') y+) /) 3) 7) ;) @) zA) B) C) E) E) "G) G) dH) I) I) GJ) J) nK) K) }L) M) M) N) tO) N) N) O) aP) P) NQ) Q) YR) R) xS) T) T) > b@ c@ d@ e@ f@ g@ h@ i@ j@ k@ l@ m@ xn@ mo@ bp@ Wq@ Or@ Gs@ ?t@ 7u@ /v@ $w@ x@ y@ z@ z@ {@ |@ }@ ~@ @ @ @ @ @ @ @ x@ p@ h@ `@ X@ P@ E@ :@ .@ "@ @ @ @ @ @ @ ݕ@ і@ ŗ@ @ @ @ @ @ @ @ y@ q@ f@ [@ O@ C@ 7@ +@ "@ @ @ @ @ @ @ ۭ@ Ю@ ů@ @ @ @ @ @ @ @ |@ + @ @ -@ t@ Ƚ@ @ L@ @ @ + N + @ J@ @ 4@ @ @ |@ @ @ %@ @ @ e@ @ J@ @ 5@ c@ X + + + + + N+ + + G!+ x#+ +&+ (+ ++ D.+ 0+ 3+ 54+ 4+ ?5+ 5+ L6+ 6+ \7+ 7+ i8+ 8+ s9+ 9+ :+ ;+ ;+ <+ <+ @ @ L>+ >+ ^?+ ?+ p@+ @+ ZA+ A+ VB+ B+ dC+ C+ uD+ D+ E+ F+ F+ G+ G+ H+ H+ #I+ I+ )J+ J+ /K+ K+ =L+ L+ KM+ M+ _N+ N+ sO+ O+ P+ Q+ @ C A Q+ Q+ TR+ R+ $S+ S+ S+ \T+ T+ 6U+ U+ V+ qV+ V+ IW+ W+ 7X+ X+ 9Y+ Y+ >Z+ Z+ C[+ [+ E\+ \+ A]+ ]+ =^+ ^+ ?_+ _+ -`+ `+ -a+ a+ ?b+ b+ =c+ c+ ;d+ d+ ?e+ e+ =f+ f+ ?g+ g+ Eh+ h+ Ni+ i+ Wj+ j+ A A A A A A A A A N A A & A A A A A t A A [A A ]k+ 2l+ m+ m+ n+ o+ fp+ <q+ r+ [s+ t+ u+ 0w+ zx+ y+ {+ A A ^A A A 5A A A bA %A A A f A & A A A B!A "A $A &A 'A ^)A +A ,A #.A /A 0A 1A 2A 3A 4A 5A 6A 8A 8A :A ,;A @<A 4=A N>A t?A @A AA BA CA EA AFA }GA HA IA :KA yLA MA NA -PA iQA RA SA &UA eVA WA XA ZA U[A \A ]A _A Q`A aA bA dA AeA fA gA hA =jA |kA lA mA 5oA spA qA rA 0tA nuA vA wA U|+ |+ +yA 4zA @{A I|A U}A ^~A |+ ~+ jA UA CA .A A A + + A A *A ǏA gA A A A A A A A A A A A tA rA }A rA jA BA A A ]A A A aA A A IA °A %A A ѴA =A A A A ŻA A _A A A A lA A A A A A A A mA _A <A A A 3A tA A A &A }A A A &A A A HA A *A A A A A A A xA _A CA *A A A A A A {A .A A qA ?A A A A OA (B B B 9B B B B z B DB B B "B B 3B B mB B B B h B ; B !B !B "B y#B O$B %%B &B p(B *B {+B --B .B q0B (2B 3B 5B l6B 7B 9B Y:B ;B <B 5>B ?B @B ADB GB KB G\B _B cB fB }NB QB fUB XB iB ]mB pB .tB wB yB {B QB ĂB 6B x8 v8 t8 r8 p8 q8 r8 s8 t8 u8 s8 q8 p8 o8 n8 m8 o8 q8 s8 u8 w8 v8 u8 s8 q8 o8 m8 n8 o8 p8 q 9 r9 p9 n9 m9 l9 k9 j9 l9 n 9 p 9 r 9 t 9 s 9 r9 p9 n9 l9 j9 k9 l9 m9 n9 o9 m9 k9 j9 i9 h 9 g 9 i 9 k 9 m 9 o!9 q"9 p#9 o$9 m%9 k&9 i'9 g(9 h)9 i*9 j+9 k,9 l-9 j.9 h/9 g09 f19 e29 d39 f49 h59 j69 l79 n89 m99 l:9 :9 @;9 ;9 <9 A q<9 =9 v=9 =9 >9 >9 ?9 $@9 @9 A9 A9 B9 uB9 B9 [C9 C9 kD9 D9 }E9 E9 sF9 F9 iG9 G9 SH9 H9 =I9 I9 K9 AL9 M9 N9 0P9 Q9 R9 %T9 sT9 T9 U9 V9 |Z9 ]9 za9 s9 v9 z9 }9 d9 h9 l9 o9 9 9 9 9 9 59 p9 9 9 9 y9 9 9 9 ї9 X9 И9 N9 ˙9 V9 Κ9 9 9 9 9 9 09 9 #9 9 9 9 9 9 9 m9 9 s9 9 z9 c9 ڥ9 H9 ɦ9 L9 9 09 9 69 é9 =9 &9 9 9 9 9 9 9 9 <9 9 59 9 ߰9 9 !9 9 9 O9 ų9 69 9 9 9 9 y9 9 X9 ÷9 -9 9 9 t9 9 O9 9 9 w9 ڻ9 P9 Ƽ9 <9 9 +9 9 '9 9 l9 .9 9 9 9 d9 9 9 9 9 "9 9 "9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 r9 9 h9 9 p9 9 r9 9 r9 9 c9 9 Y9 9 =9 9 9 9 9 i9 9 _9 9 >9 9 9 s9 9 9 u9 9 Q9 9 K9 9 9 9 9 9 9 9 9 9 9 9 M9 9 99 9 E9 9 /9 9 ,9 9 A9 9 9 9 9 9 9 w9 9 s9 9 t K9 9 ί % ٰ 9 9 f9 9 9 [9 9 9 9 s : : : : : i: : : : - : : z : $: : z: : : : : : : : : - : E : = : m : !: ": #: $: %: ': 1(: /): ): *: j*: *: "+: w+: +: !,: g-: .: /: 91: 2: 3: 5: ]6: 7: 8: /:: u;: <: >: P?: @: A: %C: kD: E: F: CH: I: J: L: aM: N: O: 6Q: R: S: U: ZV: W: X: 1Z: y[: \: ^: T_: `: a: /c: wd: e: f: g: h: t h: [i: i: %j: j: j: Qk: k: !l: l: l: Ym: u 3 P m: ?n: n: o: p: p: q: q: q: \r: r: .s: s: t: lt: t: wu: u: Jv: v: !w: w: ,x: x: y: ty: y: yz: {: {: W|: |: I}: }: 6~: ~: n: : : : }: : : : : : |: : : : y: : : 1: ԇ: v: : : : : : : Ϗ: ΐ: Б: : : ϔ: Ε: Ж: : (: : : .: : : m: Т: : : : s: é: 9: : ): : : K: : : : j: ̸: : g: : : y: c: -: : : : : : : `: : : 0: : : *: X: : H: : : : : N: F: A: 9: 4: ": : : : : : : : : : <: : : k: ?: : : : : L: : : : s; 8; ; ; ; G ; ; \ ; ; ; a; ; ; ; ; a; A; ; ; ; ; ; E ; ; "; $; %; y'; ); *; ,; -; </; 0; 1; G3; 4; 5; A7; 8; 9; k=; @; TD; U; /Y; \; `; G; EK; N; >R; c; f; rj; m; Sq; s; u; /y; |; (; ; ; Q; ; %; ; ; ; ; ; ; ; ; v; ; R; ; +; ; ; v; ; X; Ǎ; 7; ; &; ; *; ; 6; ; -; ; ; ~; ; [; ֔; Q; ̕; K; ʖ; 8 8 k' _8 8 }8 C h % Em' m' !n' n' -o' o' Np' p' 'q' q' Ar' r' s' rt' Gu' %v' w' w' 98 8 8 ~8 8 |8 8 E8 8 E8 F 2 ! x' (y' y' y' 7z' z' z' 8 8 8 $ r n j E8 |' }' ~' ' G' ' AB B ZB B B B ېB B B B pB [B #3 B oB B B hB B B 8B B B DB B B B B B B B 5B ӟB ;B B B B B ! ! `B =B B ФB ! ! B B .B ݦB B qB F, TG, tJ, M, P, S, V, W, ;B bB B ƭB B B B B PB B B 3B B 1B UB h, k, Im, o, yB r, fs, B JB s, @t, B B t, u, dB u, ?v, v, v, 9w, w, w, B jB B Zx, x, B !B y, 5" @6" Hy, y, !z, z, z, J{, {, |, |, |, ]}, }, ~, B ~, D, B , , , , , ", , , p, B 1B B ƃ, , BB B s, ʄ, (, NB B gB , , B {B 1, ~, ؆, B B B &, t, B B RB" B" B" IC" C" C" ZD" D" B B ]B B GB B B ZB B ͉, , , ), B DB B aB d) ) ) b) ) ) `) ) Q> P> R> S> S> CU> V> W> Y> bZ> [> \> @^> _> _> `> "b> Mc> xd> e> f> h> 0i> j> (l> m> o> .q> r> t> v> w> Py> z> B|> ~> > ?> Ă> > > ʇ> R> Ŋ> 8> > > #> > o> > > > > > > ;> ڠ> V> > > A> > Y> > > > O> > > > Z> > t> > > -> > L> > > => > a> > > > > .> +> > > d> > > > G> > > > k> => > ^> > > > > 6> > > '> > :> D5* -7* 8* :* *<* >* ?* {A* > 5? ? ^? ? k? ? ? ? ? .? ? ? ? )? ? 0? ? e? ? r ? ? ? "? #? S%? &? ?(? )? +? X,? -? /? 1? S3? (5? 6? 8? :? g<? >? ?? bA? \C? E? F? H? J? ;L? N? O? Bl* ym* n* P? (R? FS? T? U? ,W? SX? Y? y* rz* *{* Z? {* |* E}* [? \? w]? s^? -_? _? `? 1* f* fa? b? b? c? d? e? f? Pg? * * * * Z* G* >* * َ* * v* `* )h? eh? ti? ,j? j? Ak? k? `l? l? m? in? o? * -* ɔ* ]* * w* * * 7q? * * q? r? Zt? v? x? z? }? ? ? ? ? ? * '? I? _? ? ? ? ? j? ? ? p? ? ? 1? ? !? ? t? ? ? q? ? ? )? ? ? ֲ? T? ? s? ?? ? d? ? T? ? ? ? ? ? ? d? ? ? ? k? 6? ? Y? ? ? *? ? S? ? 5? ? z? ? ? b? ? ? ? ? I? B? ? ? o? k? ? ? ? @ @ 6@ @ @ Z@ S @ @ @ @ @ j@ 6@ @ [@ @ @ /@ @ Z @ @ '* * * x* * * * s* !@ "@ L$@ &@ w'@ )@ z*@ 8,@ -@ A/@ 0@ 2@ v3@ .5@ 6@ +8@ 9@ S;@ <@ V>@ ?@ A@ RB@ C@ AE@ F@ H@ I@ J@ uL@ M@ sO@ Q@ S@ T@ V@ ^X@ aZ@ \@ ]@ _@ Ra@ * * * + B+ B+ + + +4 4 U4 4 4 '4 4 a4 4 4 4 4 4 ۊ4 Ջ4 ό4 ɍ4 Î4 4 4 4 4 4 4 4 4 4 }4 x4 p4 h4 _4 V4 M4 D4 >4 84 24 ,4 &4 4 4 4 4 4 4 4 4 4 4 ۮ4 ӯ4 ˰4 ±4 4 4 4 4 4 4 4 4 4 w4 o4 g4 _4 W4 R4 M4 H4 C4 >4 64 .4 %4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 $ $ $ 4 $ $ $ !$ $$ '$ *$ x-$ d0$ m3$ 4 4 4 <4 4 n6$ 6$ 7$ c7$ 7$ 7$ T8$ 8$ 8$ C9$ 9$ 4 4 4 34 4 4 4 n4 9$ :$ 4 4 Z4 r4 4 4 4 )4 @$ xA$ B$ C$ D$ F4 4 34 5 "5 5 5 5 &5 5 ! 5 5 5 q$5 '5 _+5 .5 15 C yE$ ;35 F$ G$ H$ I$ -45 s65 85 "95 95 ;5 1>5 @5 B5 xE5 F5 H5 I5 lK5 K5 N5 P5 R5 =U5 U5 W5 Jg$ Z5 a\5 ^5 `5 g5 b5 oe5 k5 i5 ~h5 m5 o5 r5 t5 v5 x5 b{5 }5 5 5 P5 5 K5 5 (5 5 $ 5 Ͳ$ S5 5 D5 V5 5 o5 5 5 5 ڨ5 u5 "5 5 $ 5 5 -5 $ ?5 $ Q5 Z5 o5 ^$ 5 *$ $ $ 6p $$ j$ 5 35 $ $ $ $ $ $ ʹ5 J5 ǵ5 G5 Ķ5 >5 ȷ5 V5 ߸5 i5 5 _5 5 f5 5 m5 5 h5 5 d5 m5 5 5 x5 5 5 5 5 5 5 5 5 5 w5 ;$ $ $ 5 D5 5 $ $ $ $ o$ ($ $ $ $ >$ $ 5 $ m$ 5 /5 5 U5 $ $ 2$ $ 5 5 5 5 :5 5 $5 q5 5 5 5 5 ?5 e5 j5 o5 t5 y5 x5 5 5 5 5 c5 5 a5 5 ?5 5 /5 5 5 5 z$ J$ $ $ $ % }% P% 5% % % % % % x% ] % % % ( % " % % % x% % % % % x% O% 5% % % % [% % % A% !% % [ % % % !% D#% %% &% (% G*% ,% -% z/% ,1% 2% 4% l6% %8% 9% S;% <% 5 =% c>% 2?% p@% A% B% D% ME% F% G% I% J% NK% BL% M% N% O% +Q% .R% S% S% T% U% V% rW% VX% ;Y% Y% Z% [% \% ~\% v]% V^% ^% _% a% !b% .c% ;d% We% qf% g% yh% i% \j% k% ul% m% n% o% p% q% r% s% t% v% -w% Fx% 0y% @z% {% <|% "}% N~% b% ?% R% f% y% ~% % % % % % % r% % z% % % 5 _5 5 5 ?5 5 r5 J5 5 5 y5 E5 6 6 6 L6 6 6 N6 6 6 0 6 6 x6 6 q6 6 6 6 6 6 6 6 6 6 6 + 6 B 6 9 6 V!6 "6 #6 $6 %6 \'6 )6 k% % ȟ% 16 Z36 q56 66 s% §% % % % +% % Y86 % % $% % *% % 8% % *6 +6 2-6 a.6 /6 06 :6 ];6 <6 =6 ?6 \@6 A6 B6 "D6 aE6 F6 G6 I6 `J6 K6 L6 &N6 eO6 P6 Q6 "S6 dT6 U6 V6 *X6 iY6 Z6 [6 &]6 h^6 _6 `6 .b6 pc6 d6 e6 2g6 sh6 i6 j6 9l6 zm6 n6 o6 @q6 er6 s6 t6 u6 v6 w6 \y6 z6 r% |6 a}6 ~6 (6 % 6 6 u6 6 p6 6 6 % 6 y6 6 6 96 6 j6 6 e6 6 C6 6 6 }6 6 _6 ܡ6 }6 6 6 p6 6 6 66 ٮ6 6 o6 6 6 36 6 s6 D6 6 6 6 6 \6 96 6 6 % {6 C6 6 6 6 U6 '6 6 6 6 [6 6 f6 6 6 6 6 R6 6 q6 ?6 6 6 6 _6 -6 6 6 86 6 6 g6 6 G6 6 v6 (6 6 6 6 6 7 q7 6 6 . 7 7 7 7 5 7 H-& 7 7 1& 7 &7 y7 7 #7 7 7 ;& ~7 7 7 ,!7 "7 7 7 Z 7 $7 %7 K& '7 (7 0*7 +7 A-7 .7 D07 17 27 37 157 77 87 s:7 R67 ;7 _=7 >7 ?7 @7 B7 ;C7 ]D7 E7 ?G7 }H7 I7 J7 K7 0M7 N7 P7 fy& z& lQ7 }& R7 8T7 U7 +W7 ~~& X7 .Z7 [7 U]7 ^7 y`7 b7 Y& {& c7 ]e7 f7 h7 *j7 I& & k7 Am7 n7 6p7 q7 ͙& ^s7 U& & & u7 v7 Nx7 & Ĭ& z7 {7 R}7 7 & e& <& ,& & & & & 7 & & & k7 97 7 7 7 7 f7 & ?7 7 7 & & & & 77 7 ێ7 7 7 c7 >7 B& !& ~& `& 7 7 e7 7 ϙ7 7 V7 & s& & & & & Y& ~& 7 Y7 & & z& & Ρ7 & :7 ̤7 ' _7 7 7 y ' 7 7 A' .7 ԯ7 k7 7 / ' N7 7 Ҷ7 7 7 07 7 W7 87 7 7 K7 7 7 7 T7 7 ]7 7 7 7 7 7 !7 7 7 *7 "7 7 7 7 7 7 7 7 D7 7 7 57 7 7 _7 7 7 s7 7 B7 7 7 v7 7 E7 7 7 .7 v7 7 7 G7 7 7 8 8 8 8 w8 `8 U8 58 8 8 5 8 y 8 8 8 48 8 8 8 @8 8 "8 k8 8 S8 8 8 8 8 8 !8 "8 #8 $8 q%8 X&8 B'8 )(8 )8 *8 +8 -8 K/8 08 28 q48 &68 78 98 ;8 [=8 %?8 @8 B8 fD8 $F8 H8 I8 K8 M8 N8 P8 Q8 zS8 U8 V8 fX8 <Y8 Z8 Z8 [8 \8 s]8 5^8 _8 _8 a8 8c8 d8 If8 g8 i8 Hk8 m8 n8 o8 Oq8 r8 s8 Eu8 v8 w8 *y8 ~z8 {8 ?8 8 8 Z8 ˚8 98 8 8 8 s8 8 8 8 8 V8 8 8 8 8 8 p8 B' C' 9D' E' 8 z8 8 8 qG' I' J' HL' B8 8 8 8 M' N' O' P' }Q' R' P3 m3 - F/ i1 &2 3 >5 6 +: ; < 3 3 a3 3 x3 +4 3 3 3 S3 * K4 zM4 <O4 P4 Q4 S4 KU4 Z \ ^ 3 3 oq v w vx y y ,z 3 z Wq3 s3 t3 q3 83 ܠ" B < 4 4 4 4 4 " B 4 4 o4 -{ | } ~ ԕ O !# L# y# m3 7 p3 5 v3 qw3 Fy3 {3 }|3 R~3 3 3 3 3 Q3 Lj3 '3 3 3 =3 z3 3 h3 U3 ZA0 3 ,3 #3 { x3 f3 X3 3 a3 f3 3 3 3 j 4 ` 4 " " " 4 H .3 v7 4 z13 < 4 c ? > + C 3 7 3 # # >' 3 ߢ - G2 3 x4 t5 }6 7 8 : L< 4 4 e@ JC A D AP # AR iS 43 |G I *K YL {M N O >_ \ 0 3 3 IM# 4W4 4 4 54 64 W4 4 4 MY4 nZ4 [4 4 4 $4 74 84 Z4 -\4 Y]4 4 4 ]4 ^4 34 4 I_4 =`4 /a4 b4 h 4 4 94 :4 b4 {d4 e4 f4 & 4 4 g4 i4 [j4 !4 ;4 <4 'k4 l4 <m4 "4 =4 >4 m4 ?4 n4 3 @4 ^A4 #4 fB4 o4 p4 i$4 &4 (4 %4 jC4 D4 E4 q4 9s4 t4 gv4 x4 q)4 D,4 *4 Ey4 Yz4 v{4 R/4 -4 |4 }4 ! 04 G4 AH4 24 Q\3 14 Ƥ3 k]3 _3 q24 b3 V3 44 d3 !I4 I4 *3 3 # # # # # # Q# 2g3 h3 i3 ]j3 k3 k3 Kl3 " ˾" 3 ܴ Q .3 -3 # U# # B3 3 3 3 3 3 3 3 T i 3 I3 e3 3 3 xP BP P P mP P 4P P P 5Q `P P qX X X X v@Q X tX U U U X XQ PX .U U X U U X B W EX 4&W |{Q cX <X τQ X xX X X X nX AW MY LW Y MW NW OW QW S U Y Y Y U Q Y x Y U DU 2Y KY Q U IU Y #Q V Q V V rW @sW sW Q tW BT V Y Y T T Y {W V U Y V T V V Y pT T T m T H T V T T T eT Y ? V %"Y V e V "Y M$Y $Y R R HR R %Y $V %T &Y %V 2&V uT &Y T &V s'Y T W 'V (Y | T Y)Y W(V T )Y W *Y z+Y F,Y -Y (V -Y W .Y h*V R/Y \0Y +V ,V ;1Y .V 2Y /V 0V "3Y W EW rW R !R (T "R 3Y +T ,T a-T e5Y 6Y 8Y W C,R /T /T -R &0T <1T W AW W `:Y HV T JV ;Y >Y @Y ?VV PR YDY UR \V EY SIY ^R dV hV KY OY PY rtV W LTY wV UY aW ZY V V \Y _Y /aY cY dV eY W ohY >lY `X nY OqY X sY uY V wY m{Y g$X `R qV -&X ~Y V =P P P `P 23 }3 3 3 3 3 3 q3 3 3 P3 m3 - F/ i1 &2 3 >5 6 +: ; < 3 3 a3 3 x3 3 3 3 3 S3 * Z \ ^ 3 3 oq v w vx B0 y y ,z 3 z Wq3 s3 t3 q3 83 ܠ" < 4 4 4 4 4 " 4 4 o4 -{ | } ~ ԕ O !# L# y# m3 7 p3 5 v3 qw3 Fy3 {3 }|3 R~3 3 3 3 3 ݘ3 3 3 3 F3 3 Q3 Lj3 '3 3 3 =3 z3 3 "3 h3 U3 ZA0 3 ,3 #3 { x3 f3 X3 3 3 a3 f3 3 3 3 j 4 ` 4 " " " 4 H .3 v7 =03 z13 23 < 4 ^# c ? 33 P43 > + C 3 7 3 # # 3 ߢ - G2 3 x4 t5 }6 7 8 : = ? e@ A 43 |G I *K YL {M N O \ 0 3 3 IM# ı3 63 &83 63 =93 B:3 J;3 3 3 L3 0<3 =3 <3 >3 ?3 @3 y3 3 z3 b3 @A3 C3 IB3 D3 E3 'G3 3 F3 03 3 0H3 %I3 9J3 3 Ը3 3 h3 PK3 VM3 /L3 fN3 dO3 eP3 3 "3 3 3 DQ3 4S3 R3 9T3 ,U3 "V3 3 D3 V3 3 3 W3 X3 Y3 Z3 f3 k3 ! (3 [3 )3 3 Q\3 Ƥ3 k]3 _3 b3 V3 d3 e3 *3 3 # # # # # # Q# 2g3 h3 i3 ]j3 k3 k3 Kl3 " ˾" 3 ܴ Q .3 -3 # U# # 3 i3 3 ̬3 3 B3 3 3 3 3 3 3 3 $ T i 3 I3 e3 3 3 BP KS P P mP P 4P 5Q %U V&U &U ]'U (U *U X ,U .U 60U +1U 2U 2U t3U N4U 5U 5U (7U 8U ]:U <U i=U >U >U ?U ?U AU BU CU sX KEU FU `P P FU S ȧS 3S XS ְS ֳS S S jGU S NU X X yS S 8X KX SU X S bX S S ~S S S T BT X T T pT T T eT T ;T T R R R %T T uT T T | T & T T T L!T "T #T X W'T R !R (T T +T ,T a-T XU 8ZU 0.T NT /T [U /T -R <1T 1T b2T 2T X X nX X \U NCT ET IT ]aU KT NT X VT X ]T cT fT ikT mT oT qT sT !uT wT yT X X X ZX X BeU lU T T T T ]T >T T {T "pU #3 l m n [o &p p q r r ns t t xu 8v v } ĵ 2 X2 3 3 ~3 3 K3 3 3 s3 3 8 3 o 2 B U / z M k A R $ q L ' L ! O" # # $ |% P& ' ' ( ) w* d+ Q, } 8 j L n & > T x L V O H U H R ( b Z E O < h 3 g ! U a! 0# $ & ( M* , - u/ +1 54 4 2 3 6 7 5 16 -8 9 9 : ; < < = = > > ;B E DI L O jS W [ _ c g k so r tv y } ۄ ܐ ϔ ߘ s ݣ n \ ر w x 2y y y >z | ~ 1 ԅ T , : A > n ߚ z 4 R + ] * o M _ 3 ۷ ' z ` G M 2 hU V DY [ (^ ` c e qh j Io l Rq s 2 ju v x Zy z { P} ~ @ 6 N G ~ % ] ͗ = u u $ w W F ~ , f N g = ~ T# % *( * - z. / n1 2 e4 5 47 $8 9 ; < > ? C A E ,G LH dI J P V )\ b (h m r Tx } g ] % Ԣ ۣ @ J T ĭ & & I : + E _ P A [ u $3 . F _ Ų x * ܴ @ V O z < ҽ h ) S } =%3 '3 )3 ,3 < S ( ( R | 0 E i p a.3 : G< E> > H? ? z@ %A A kB C C D YE /F F SG H H I ^J K K uL "M M N 1O O Q =R bS T U V W Y 2Z Z [ [ [ x\ \ i] 8_ a b f S2 h i oj k k - . D j [ f 3 #3 / ? j 6 t q n k h h h h h W C ? j : G # + 3 6 4 2 0 V Q S V ^! ! f" " i# # g$ $ e% % c& & ' 0( ( ) ) * * |+ , , - - . . / / 0 0 1 1 2 2 33 3 4 .5 5 06 6 37 7 ;8 8 C9 9 F: : D; ; B< < @= = f> ? ? a@ @ cA A fB B nC C vD D yE E wF F uG G sH H I @J J K L L M M N N %O O -P P +Q Q )R R 'S S %T T sU V V Y [ \ \ \ ] ^ ^ 6` c f h Vi i Lj j Tk k \l l dm m bn n `o o ^p p \q r r Ss s t u u v v w w x x y y z z { { | | 6} } ~ 1 3 6 > F ʃ I Ȅ G ƅ E Ć C i d f i q y | z x v C " ( 0 . , * ( Ϟ v ʠ U ̡ K Ϣ S ף [ ߤ c a _ ާ ] ܨ [ R yh 5 Z b 7 U O / . e ! ! " o" # # $ $ % W& ' ' I( ( [) ) U* * P+ , , [- . . / / 0 1 3 @4 i5 6 7 7 8 : 5; ^< = = +> > ? ? @ @ @ C C D E F G nH ^I MJ >K 2L M N AP Q S T V bW X &Z [ \ S^ ` 7b c >e sf g j k Rm n p q r ev y K} P & Ǐ M h ڕ D 0 ; > 2 X $ ݳ ? 2 ~ T * j R : " + ^ & B 2 H # G s X , h K ) * < H l C } $ # & * - 0 G4 7 V I r T [ F ` " H @ x Y $ 2 6 U R q j 2 # 2 ϯ2 2 W2 2 ּ2 12 2 , 2 2 1/ g2 2 2 P2 :2 2 u5 2 N2 6F F G G 2 2 2 2 2 ,2 2 2 :Q Q R T U U V "W W hX Y <Z n[ \ ] ` a hc Bd e g aj k m Mo $p dq &t u v w z | # Q x h h @ c 6 ] 42 " X ĩ ܬ S ϱ ^ M ڻ g & 8 G % # O & " g 2 s % o 11 ڬ1 M1 1 i 2 2 2 2 2 72 2 :2 2 s2 2 2 C2 2 [2 * 2 2 A 2 2 2 [ 2 2 2 ]2 : 2 2 +2 > 2 2 ,2 '2 2 t1 1 1 E 2 2 nG 2 2 2 2 R 1 2 ~S 2 S 2 U 2 2 %!2 !2 "2 ~1 Wk2 "l2 $m2 m2 o2 p2 q2 q2 r2 s2 t2 u2 v2 w2 x2 y2 z2 d{2 b|2 W}2 E~2 1 1 >1 1 1 P1 1 1 L1 1 1 1 1 1 ķ1 N1 ظ1 1 p1 >1 1 1 Y1 M1 1 1 K1 &1 1 1 1 1 i 1 1 1 1 1 1 1 #2 i$2 M%2 '2 (2 )2 +2 A-2 ~2 2 :2 2 2 S2 2 2 ~2 O2 q`1 E Ga1 b1 7J b1 c1 {d1 Xe1 e1 ^f1 f1 tg1 h1 wh1 Oi1 j1 j1 Vk1 k1 {l1 !m1 /n1 o1 o1 Ap1 p1 q1 ,r1 r1 ls1 s1 t1 %u1 u1 6v1 v1 .2 12 22 32 5w1 Z1 w1 x1 ~u v m42 v 42 52 1 X62 wy1 }z1 p{1 }|1 }}1 2 2 ǔ2 81 S1 1 U1 %1 {1 1 H1 31 1 1 1 1 1 1 1 1 1 NJ1 1 i1 )1 1 N1 {72 X82 %1 1 1 1 ,1 1 ː1 ^1 1 1 1 1 1 _1 N1 ݕ & ? 2 > 1 w2 J2 2 _ I 2 2 Ţ2 \ s = 2 2 2 2 +2 2 2 2 2 2 I a2 2 02 q2 2 +2 2 ߜ2 k2 A92 1 1 12 2 2 v2 K2 2 2 G2 2 2 G2 2 2 O2 2 ސ2 :2 :2 M;2 ;2 <2 l=2 ȃ 32 1 1 1 D1 1 1 u1 1 2 c2 1 1 ]1 1 1 e1 S1 1 1 1 ?2 ?2 @2 @2 A2 A2 B2 B2 C2 C2 D2 ]E2 F2 F2 G2 H2 I2 K2 K2 L2 M SM2 ϖ N2 Q N2 ՙ uO2 \ .P2 P2 l Q2 YR2 S2 nT2 VU2 V2 W2 X2 bY2 Y2 "[2 [2 BP KS P P mP P 4P 5Q `P P S ȧS 3S XS ְS ֳS S S gS S jS X X yS S 8X KX X X S bX S S ~S S S T BT X T T pT T T eT T ;T T R R R %T T uT T T | T & T T T L!T "T #T X W'T R !R (T (T +T ,T a-T 0.T C,R /T /T -R <1T 1T b2T 2T X X nX X ?T NCT ET IT KT NT X VT X ]T cT fT ikT mT oT qT sT !uT wT yT X X X ZX X T T T T ]T >T T {T g2 '\2 \2 7]2 ]2 G^2 ^2 s_2 `2 `2 ,a2 a2 :b2 b2 Zc2 c2 ld2 0f2 f2 d2 e2 ӱ j kg2 Fh2 ` /j2 ] ۻ 11 ڬ1 M1 1 i 2 2 2 2 2 72 2 :2 2 s2 2 2 C2 2 [2 * 2 2 A 2 2 2 [ 2 2 2 ]2 : 2 2 +2 > 2 2 ,2 '2 2 t1 1 1 E 2 2 nG 2 2 2 2 R 1 2 ~S 2 S 2 U 2 2 %!2 !2 "2 ~1 Wk2 "l2 $m2 m2 o2 p2 q2 q2 r2 s2 t2 u2 v2 w2 x2 y2 z2 d{2 b|2 W}2 E~2 1 1 >1 1 1 P1 1 1 L1 1 1 1 1 1 ķ1 N1 ظ1 1 p1 >1 1 1 Y1 M1 1 1 K1 &1 1 1 1 1 i 1 1 1 1 1 1 1 #2 i$2 M%2 '2 (2 )2 +2 A-2 ~2 2 :2 2 2 S2 2 2 ~2 O2 q`1 E Ga1 b1 7J b1 c1 {d1 Xe1 e1 ^f1 f1 tg1 h1 wh1 Oi1 j1 j1 Vk1 k1 {l1 !m1 /n1 o1 o1 Ap1 p1 q1 ,r1 r1 ls1 s1 t1 %u1 u1 6v1 v1 .2 12 22 32 5w1 Z1 w1 x1 ~u v m42 v 42 52 1 X62 wy1 }z1 p{1 }|1 }}1 81 S1 1 U1 %1 {1 1 H1 31 1 1 1 1 1 1 1 1 1 NJ1 1 i1 )1 1 N1 {72 X82 %1 1 1 1 ,1 1 ː1 ^1 1 1 1 1 1 _1 N1 ݕ 1 1 1 1 1 1 ?1 1 1 1 1 o1 >1 1 1 1 1 1 1 G1 1 1 1 1 [1 1 1 !1 1 1 1 ߨ1 `1 1 1 K1 1 1 1 ͫ1 Z1 A92 1 1 12 2 2 v2 K2 2 2 G2 2 2 G2 2 2 O2 2 ސ2 :2 :2 M;2 ;2 <2 l=2 ȃ 1 1 1 1 D1 1 1 u1 1 2 c2 1 1 ]1 1 1 e1 S1 1 1 1 ?2 ?2 @2 @2 A2 A2 B2 B2 C2 C2 D2 ]E2 F2 F2 G2 H2 I2 K2 K2 L2 M SM2 ϖ N2 Q N2 ՙ uO2 \ .P2 P2 l Q2 YR2 S2 nT2 VU2 V2 W2 X2 bY2 Y2 "[2 [2 1 l1 G1 1 i1 1 1 1 1 61 1 _1 1 %1 1 w1 1 1 1 1 M 1 1 1 3 1 1 1 !1 "1 #1 $1 n%1 '1 )1 +1 ),1 ,1 -1 -1 '.1 .1 O/1 /1 r11 11 21 &31 Y01 01 31 @41 41 K51 51 q61 61 81 81 91 :1 l;1 <1 =1 ^>1 5?1 @1 A1 c0 P0 0 1 ~ 1 1 b1 1 I1 1 1 1 1 c1 1 l1 1 M1 1 21 1 1 l 1 1 . 1 1 1 b 1 1 ; 1 1 1 1 1 X1 1 "1 1 8/ / / l' f/ / y/ / / i/ / / / W/ / // / / / / N/ / &/ / / / / / D/ / s/ / m/ / ./ / / / 5/ / 9/ / 6 0 0 ,0 0 0 g0 0 m0 0 s0 0 k0 0 ڛ/ / ל/ / Q/ / ˟/ / K/ / ˢ/ d/ / / / / A/ ֦/ k/ / / u/ ,/ / / T/ / ȭ/ / ,/ ϯ/ r/ / / ^/ / / C1 D1 PE1 P/ / / 0/ ж/ s/ / / F1 \/ / / 9/ ػ/ z/ / / F1 G1 gH1 "I1 I1 J1 YK1 L1 L1 `/ / Կ/ / H/ / / / </ / / M1 2/ / / 9/ / M1 ON1 / x/ N1 / &O1 O1 O1 EP1 P1 Q1 mQ1 Q1 :R1 R1 S1 T1 T1 1U1 U1 .V1 ]/ / 2/ / / g/ V1 / 3/ W1 / ?/ / / U/ / / t/ W1 )/ / / </ / / U/ / |X1 MY1 / c/ / / U/ / / P/ / / C/ / / 5/ / / Z1 Z1 [1 x\1 A]1 ^1 ^1 _1 -/ / / / M/ / / / h' ^' X0 . )Y0 Z0 Z0 [0 . s. R. 1. . . . I]0 . . T. . . !. . M. . V. . Z. . U / / W/ o. y`0 a0 c0 -d0 ]0 / / i/ d0 / / / / t / k / b / Y / e0 sf0 lg0 eh0 P / '/ / / / / l/ ^i0 W/ Gj0 j0 k0 k0 k0 Fl0 l0 m0 Wm0 m0 "n0 n0 Y/ Z/ n0 ;/ !/ o0 / / p0 / q0 &r0 r0 Js0 s0 `t0 t0 |u0 v0 v0 w0 w0 >x0 x0 Ry0 y0 lz0 z0 F/ / 6 / / |{0 |0 |0 / / p / % x}0 0 &~0 "/ n#/ E$/ %/ %/ &/ {'/ (/ (/ t)/ #*/ */ +/ h,/ 5-/ -/ 0 0 % v0 0 C0 0 0 0 0 0 % 0 u0 0 0 0 0 0 0 Б0 0 0 )0 2/ r3/ N4/ & *5/ & 7/ 0 6/ 0 ɘ0 ҙ0 0 0 8/ z& 8/ 9/ & y:/ ܚ0 Û0 ^;/ </ >/ 0 </ =/ 0 q?/ )@/ @/ A/ +B/ B/ C/ dD/ D/ E/ MF/ F/ uG/ H/ H/ I/ J/ RK/ L/ ݠ0 0 L/ l0 0 M/ NN/ O/ .P/ P/ Q/ 0 0 TR/ R/ uS/ ;T/ T/ DU/ 0 0 U/ V0 0 0 E0 0 0 *0 Ǫ0 f0 0 0 E0 0 0 )0 ϯ0 k0 0 7V/ V/ iX/ Y/ 0 0 S0 [/ c\/ ']/ ^& 0 0 0 _/ }`/ ja/ Wb/ Kc/ d/ d/ e/ nf/ 3g/ g/ h/ i/ j/ bk/ >l/ l0 g0 & M0 {& 0 0 0 0 0 0 & տ0 0 0 0 0 "0 0 @0 l0 M0 e0 0 n/ o/ p/ & q/ & s/ 0 r/ }0 0 0 0 0 t/ & u/ v/ <& zw/ >0 ;0 ux/ Iy/ {/ '0 z/ z/ %0 |/ }/ }~/ I/ / / _/ / / c/ 7/ / (/ / ȇ/ {/ y/ R/ 0 u0 3/ &0 T0 ^/ h0 g0 9/ / Ǝ/ g/ / / H/ f0 30 0 0 0 / 80 D/ ͒/ 0 {0 X0 0 0 {0 :0 0 0 0 0 r0 0 \0 0 0 A0 0 0 0 0 w0 0 _0 0 M0 0 &0 0 0 0 :0 0 >0 0 0 0 0 0 0 L0 0 *0 / / 0 Q/ Ք/ 8/ 0 _0 / 0 / ;0 t/ 0 / / %0 0 0 ~0 0 b0 0 L0 0 S0 0 Z0 0 / _/ ɘ/ ) 0 + , f F/ i1 &2 3 >5 6 +: ; < LC F0 F G0 F ;I0 H J0 |J WL K0 M0 ;O qN0 P O0 `S T DV Z \ ] N^ ^ b %j oq v w vx B0 y y ,z z I Q d v x 3 # -{ <| | } ~ ( ď \ ԕ O !# L# y# t 7 /# # 9# # L# # # 0 0 0 !0 "0 #0 70 $0 %0 '0 )0 +0 ,0 .0 00 |20 Q40 #60 90 90 S:0 Z;0 ` P 2 ;0 =0 e ZA0 _ v x B 8 P0 X ސ $ $ Q ړ q E ~ H v H A D Χ# # 0 0 4 ^# c 9 0 A 0 > + ! I a # # >' ߢ - G2 3 x4 t5 }6 7 0 @0 8 : C; L< e@ JC A D # # ۬# F |G I *K YL {M N O U >C0 \ 0 v Pp x , S !# # # w# i# # # 8# # # R# r# E# ^# # R $ $ $ $ Y# # " c0 z [0 { } y 0 B 5 0 E0 # z Z 0 " $ 3F0 4 ى " Q0 α ֲ r ܴ Q T0 w D r $ T i ~ = U0 *( P P ,X mP %U V&U ,X V V DV V V qV nV a-X +1U t3U N4U O.X /X B0X 1X 2X u3X 4X 4X `P P i5X P 5X 7X I;X _>X ?X AX KBX CX DX FX GX HX >JX KX ILX MX MX PNX OX PX QX RX SX VUX uVX o S WX S S ~S 1S S WS S S VXX YX YX tZX 0[X [X o S \X S &]X ]X D^X _X _X `X aX qbX PcX OdX =eX S ,fX S QS S S gX gX hX biX 7jX jX kX hlX mX mX nX ^oX pX pX S 4 S S O S pqX qX rX 4 S ^sX S %!S ktX tX xuX vX vX wX xyX zX |X ~X XX X X |1Q >X X V c0 8/ / / l' f/ / y/ / / i/ / / / W/ / // / / / / N/ / &/ / / / / / D/ / s/ / m/ / ./ / / / 5/ / 9/ / 6 0 0 ,0 0 0 g0 0 m0 0 s0 0 k0 0 ڛ/ / ל/ / Q/ / ˟/ / K/ / ˢ/ d/ / / / / A/ ֦/ k/ / / u/ ,/ / / T/ / ȭ/ / ,/ ϯ/ r/ / / ^/ / / P/ / / 0/ ж/ s/ / / \/ / / 9/ ػ/ z/ / / `/ / Կ/ / H/ / / / </ / / 2/ / / 9/ / / x/ / ]/ / 2/ / / g/ / 3/ / ?/ / / U/ / / t/ )/ / / </ / / U/ / / c/ / / U/ / / P/ / / C/ / / 5/ / / -/ / / / M/ / / / . . . s. R. 1. . . . . . T. . . !. . M. . V. . Z. . U / / W/ o. / / i/ / / / / t / k / b / Y / P / '/ / / / / l/ W/ Y/ Z/ ;/ !/ / / / F/ / / 6 / / / F / / / p / 1!/ !/ "/ n#/ E$/ %/ %/ &/ {'/ (/ (/ t)/ #*/ */ +/ h,/ 5-/ -/ ./ // 0/ 1/ 2/ r3/ N4/ *5/ 7/ 6/ 8/ 8/ 9/ y:/ ^;/ </ >/ </ =/ q?/ )@/ @/ A/ +B/ B/ C/ dD/ D/ E/ MF/ F/ uG/ H/ H/ I/ J/ RK/ L/ L/ M/ NN/ O/ .P/ P/ Q/ TR/ R/ uS/ ;T/ T/ DU/ U/ 7V/ V/ W/ iX/ Y/ Y/ Z/ [/ c\/ ']/ ]/ ^/ _/ }`/ ja/ Wb/ Kc/ d/ d/ e/ nf/ 3g/ g/ h/ i/ j/ bk/ >l/ 6m/ n/ n/ o/ p/ q/ s/ r/ t/ u/ v/ zw/ ux/ Iy/ {/ z/ z/ |/ }/ }~/ I/ / / _/ / / c/ 7/ / (/ / ȇ/ {/ y/ R/ 3/ ^/ 9/ / Ǝ/ g/ / / H/ / D/ ͒/ / / Q/ Ք/ 8/ / / t/ / / / _/ ɘ/ ̴. . # U. Ͷ. . ;. =. . . Ӻ. Z. . . . @. . . ). . 6. . 2h c. . 0 0 # B# < 0 0 0 # # 0 . 0. ç. . m. . . p. .. . B. . د. . . {# & # # .0 c. l. c. &. ( G ] R ! a% G 3. . 3. . . `. e. . . . . . -. . E. S S sT U . . 2. H. \. o. . . . . ӟ. . . . H. . z. ܰ. Z. . `t q ڱ. 4w {. ! . . . Q. p =. P . . . =. n. . . . P. . . s. *. . 4 . 3. . . . . . .. . 6. . . . . Gr- s- At- 0- 0- - - - - 7- @- $- - d- W- - Mm. ؘ- - - - {- n. '- H- ao- ͡- t- - Hx. y. {. w|. }. B. . . U. - , k. - Ƈ- - u- =x- #{- o. '- q. <- p- f- (- 5. ~. Ӈ. . ˵, - - Ȯ- 1- s- J, , r. [s. h. Vj. t. v. , , l, , , , , , , , - - - , , K, , ց- ɂ- ~- , - - - - - N- - P- Q- ;- - - - - - 2- - - - - }- 6- - - - - - X- <. . . . /. ^ . v . . . ?. . . . . + . 2 . " . ". $. %. (. :*. o,. .. 0. I3. 5. R8. -:. ;. =. ?. B. C. WE. {G. I. K. YM. N. P. R. T. V. YX. Z. \. ^. `. a. d. f. . ۵- -- g- wi. {w. - Gr- s- At- 0- 0- - - - - 7- @- $- - d- W- - W- ؘ- - , - {- J- '- H- ao- ͡- t- ̲, - , - - Ƈ- - u- =x- #{- j- '- <- p- f- (- ˵, - - Ȯ- 1- s- J, , - - p- - - , , l, , , , , , , , - - - , , K, , ց- ɂ- ~- , v, , , , , , , , , , , 5, ', , ~, , M, , , ~, W, , P, 8, t, u, , - j- 1- - - - L - - - \- - @- /- ]- W - T - - $- !- }&- (- +- -- 1- /- e4- 6- 8- :- >- [<- -A- yC- F- G- oK- 5I- M- O- [Q- U- R- MW- dY- Z- ^- e\- `- b- dd- e- xg- k- h- Rm- - - - ۵- -- g- gq- - - P BP P mP 5Q %U V&U &U V V DV V V V V V V nV uV ~V `V V qV nV 60U 5uU 2U 2U vU vU 5U V V fV V =V V ?V ~U kU 9U U U >U >U ?U V V V _U lU U U %U U `P P U V V PV _V pV v@Q w W U W W U W W W W .U PW wW U U W B W #W 4&W )W 5-W \Q τQ Z0W +2W 4W 7W .;W a>W AW IFW IW LW U MW NW OW QW S U Q U QW ϯQ Q DU nTW uXW ]W aW dW jW mW Q Q V V rW @sW sW Q tW BT V uW wW T yW {W V |W V T V V >}W pT T ~W tW yW xW T uW T T eT 1W ? V W V e V EW R R "V #V HR R $V %T %V 2&V uT T T &V @ T T W 'V | T W(V `W T W W ȏW W W ڑW ԒW )V h*V W W *W +V ,V fW .V /V 0V W EW rW 5W "W R !R (T >3V .W ͟W 1W +T ,T a-T W ;V KW W .@V @V W mW /T [U W /T -R &0T <1T W AW W W 2R HW GW HV hW W zW W <W ?VV W W UR \V W ?W W <W dV hV W mW W "W mW W OW W W aW ݆R V V W W -W rW W wW W X X m X X `X iX X 2X X V X V >T X g$X `R qV -&X )X V =P P `P V &V V c) \d) Vf) 7 o Ph) t l ۪ ; 6 1 ; 7j) m) ɴ 1 r) p) t) &u) u) u) [v) v) *w) w) w) z) @}) ) ) ) ) ) ]) ) ) ) Ҏ) ;) ) >) }) ) D) ) ) ) ) ) ) ) ^) ٢) T) ) m a) K " i F ϧ) |) ެ) E) ) ) ~) ) F) ) C) ) ) Z) ) ) ) ;) ) V) ) I) ) {) 7) ) ) ) ) o) h) `) P) ) D) ) ) d) ) T) ) D) ) N) ) X) ) >) ) B) ) 2) ) ) ) ) V ) ͚, ܕ" 3" F, қ, ^, , v, ĝ, , , ȟ, ǡ, N, , ͥ, , h, , F, ҫ, ^, , , ,V) W) X) X) Y) Z) [) d\) s]) ^) _) `) a) b) G+ + i+ + + i+ + v+ + + @+ + + r+ + N+ + D+ + + + + H+ + + + + + )+ + A+ + + + @+ + n+ ?+ + y+ N+ + ~+ + + T+ ++ + + + m+ + 8 , j, , O, , , , Q, , W , , y", $, q', ^' ;' ' ' ' W' ' ' ' ' ' ' ' [' ' ' ' ' ' ' ' ' ' ' ' ' ' ' A' %' ^' ( ( .( "( p( T( ( ( ( ( ( ( @( f( ( ( ( n( ( *( K( ( s( ( H ( y ( !( %"( #( M%( &( (( /)( *( +( --( .( %0( 1( 2( 44( I5( 6( Y8( 9( :( <( ;=( ->( ,?( ?( @( A( oB( 6C( D( E( F( F( xG( fH( JI( K( yN( P( S( U( X( _[( \( m]( H^( Z_( Ip( q( s( it( u( v( x( y( ;z( L{( p|( }( ~( `( e( a( b( Kc( d( e( f( g( Zh( <i( i( tj( \k( 3l( #m( Nn( ro( ( F( 7( ( ( ( ( ( ( K( ( ( '( ( /( ( ( ގ( ( ( k( %( ( ( l( ( ( ɝ( ( V( ( ʤ( G( ( '( ( ( x( N( (( ( ܯ( ( ( H( ( ( ( 4( ( ζ( ( e( 5( ( պ( ( ( ( ( ( ( f( :( ( ( ( ( d( 8( ( ( ( Q( ( ( ( )( ( ( ( ( ( ݒ ( ( ( s( =( ( ( ( z( N( "( ( ( ( u( L( ( ( ( s( 9( ( ( ( ^( ( R( ( D( ( >( ( 6( ( 5( ( 7( ( =( ( ( ( ( ( ( A( G ) I) J) S) X) \) @) ) b ) ) ) ) ) ) h!) ") #) $) %) ') y+) /) 3) 7) ;) @) zA) B) C) E) E) "G) G) dH) I) I) GJ) J) nK) K) }L) M) M) N) tO) N) N) O) aP) P) NQ) Q) YR) R) xS) T) T) JU) + + @ + N + X + + + + + N+ + + G!+ x#+ +&+ (+ ++ D.+ 0+ 3+ 54+ 4+ ?5+ 5+ L6+ 6+ \7+ 7+ i8+ 8+ s9+ 9+ :+ ;+ ;+ <+ <+ 4=+ =+ L>+ >+ ^?+ ?+ p@+ @+ ZA+ A+ VB+ B+ dC+ C+ uD+ D+ E+ F+ F+ G+ G+ H+ H+ #I+ I+ )J+ J+ /K+ K+ =L+ L+ KM+ M+ _N+ N+ sO+ O+ P+ Q+ Q+ Q+ TR+ R+ $S+ S+ S+ \T+ T+ 6U+ U+ V+ qV+ V+ IW+ W+ 7X+ X+ 9Y+ Y+ >Z+ Z+ C[+ [+ E\+ \+ A]+ ]+ =^+ ^+ ?_+ _+ -`+ `+ -a+ a+ ?b+ b+ =c+ c+ ;d+ d+ ?e+ e+ =f+ f+ ?g+ g+ Eh+ h+ Ni+ i+ Wj+ j+ ]k+ 2l+ m+ m+ n+ o+ fp+ <q+ r+ [s+ t+ u+ 0w+ zx+ y+ {+ U|+ |+ |+ ~+ + + `' A ɂ' b' ք' i' ' ' g' ' ' ' ' ' ' ' A' ' '' ' ' ' ' x' ' ^' =' )' ' ' z' ' p' ' `' ' J' ' @' H' I' E' F' ' B' 2' ' 4' 5' 1' 2' /' ' ' ' ' ' ' ' 7' T' ̭' &' ' ' j' د' @' ' &' ' ' v' ' L' ' "' ' ' ' ' P' ' ' ' ' \' Ƹ' (' ' ܹ' B' ' ' q' û' ' ' ' y' ' ' ' U' ' ' x' ' &' ' ' k' ' ' ' >' ' ' d' ' @' ' ' {' ' <' ' ' w' ' d' ' 6' ' :' ' ,' ' ' v' ' ' ' o' ' 5' ' ' ]' ' W' ' >' ' ' ' :' (' ' i' ' ' {' ' K' ' ' c' ' [' ' U' ' /' ' ' ' ' Z' ' ^' ' j' ' `' ' + W+ + 2+ K+ څ+ g+ + + + + ى+ + I+ Ջ+ J+ + 4+ + + + + e+ @+ (+ + + m+ + [+ Ҕ+ C+ + %+ + + + + + ۚ+ + ś+ + + + + v+ e+ P+ )+ + #+ + + + զ+ A+ + + + + f+ ͩ+ + + w+ ͬ+ /+ + + e+ Ů+ -+ + + Y+ + + {+ ڱ+ ?+ + + a+ dz+ 3+ + + L+ + + V+ ¶+ '+ + + G+ + + R+ + + ]+ + '+ {+ + H+ + + a+ ̽+ "+ + + Q+ + 4+ + + e+ + a+ + K+ + + + + + + r+ + 0+ + + N+ + 0+ + + z+ + t+ + n+ + + t+ + <+ + =+ + -+ + + + n+ + B+ + + + + + + V+ + R+ + V+ + D+ + k' 6l' l' l' % Em' m' !n' n' -o' o' Np' p' 'q' q' Ar' r' s' rt' Gu' %v' w' w' F 2 ! x' (y' y' y' 7z' z' z' $ r n j [{' |' }' ~' ' G' ' *, +, ,, |-, @., 7/, /, 0, x2, =3, 4, 4, 5, 5, 86, 6, )7, 7, :8, 8, -9, 9, r:, :, =;, ;, ;, d<, =, =, >, ^?, @, @, A, A, B, YC, (D, E, F, TG, tJ, M, P, S, V, W, Y, Z, H[, O\, ], ], ^, r_, "`, `, a, Bb, Kc, c, e, e, e, Uf, g, Xg, g, bh, h, k, Im, o, r, r, fs, s, @t, t, u, }u, u, ?v, v, v, 9w, w, w, Zx, x, y, 5" @6" Hy, y, !z, z, z, J{, {, |, |, |, ]}, }, ~, |~, ~, D, , , , , , ", , , p, ƃ, , s, ʄ, (, , , 1, ~, ؆, &, t, RB" B" B" IC" C" C" ZD" D" Ç, (, , , g, ͉, , , ), c f d) ) ) b) ) ) `) ) ) _) ) ) `) ) ) a) z) ) ) ) %) t) ) ) d) ) ) Z) ) ) g) -) ) ) Z) ) ) _) ") ) C) ) * * * Q* * ^* * * * * * * O* * p* e* * * * * S!* 0#* $* &* (* a** ,* .* /* 1* T3* D5* -7* 8* :* *<* >* ?* {A* C* C* jE* F* kH* I* K* L* N* P* P* OR* S* NU* V* mX* Y* j[* \* ^* e`* -b* c* e* zg* Oi* k* Bl* ym* n* o* p* r* as* t* v* 2w* |x* y* rz* *{* {* |* E}* ~* @* <* * * u* 1* f* * ۅ* * Z* * * * * Z* G* >* * َ* * v* `* T* * -* ɔ* ]* * w* * * * * * F* @* I* +* * * * * * v* * ި* * #* * c* * * G* ȶ* l* * * +* ˾* H* * * )* * * X* .* * * * q* '* * * x* * * * s* * * P* * g* * * '* * W* * l* * * * * * * * + B+ B+ + + Kh' h' i' ti' i' Bj' j' R' S' S' S' \T' T' <U' U' V' V' V' OW' W' #X' X' X' ]Y' Y' %Z' Z' Z' ][' [' G\' \' 1]' ]' -^' ^' (_' _' %`' `' )a' a' *b' b' b' Tc' c' d' d' d' Ye' e' Sf' f' Mg' g' $ $ $ $ $ $ $ !$ $$ '$ *$ x-$ d0$ m3$ J o n6$ 6$ 7$ c7$ 7$ 7$ T8$ 8$ 8$ C9$ 9$ 9$ :$ ;$ <$ =$ =$ N>$ >$ ?$ 9@$ @$ xA$ B$ C$ D$ C yE$ E F$ G$ H$ I$ `L$ N$ P$ HS$ U$ X$ cZ$ z\$ ^$ `$ c$ 5e$ Jg$ ii$ gk$ lm$ Dr$ t$ iw$ z$ |$ @$ $ $ $ $ $ D$ ސ$ o$ s$ $ ~$ $ Ş$ H$ ţ$ $ b$ 5$ $ $ P$ Ͳ$ )$ `$ u$ $ $ $ $$ $ $ $ $ n$ j$ l$ h$ i$ G$ #$ $ $ $ $ $ $ ^$ M$ *$ '$ $ $ $ $ 6p $$ j$ $ $ $ $ $ $ ;$ $ $ $ $ $ $ $ $ $ o$ ($ $ $ $ >$ $ N$ $ m$ $ $ 2$ $ f$ $ $ $ z$ J$ $ $ $ % }% P% 5% % % % % % x% ] % % % ( % " % % % x% % % % % x% O% 5% % % % [% % % A% !% % [ % % % !% D#% %% &% (% G*% ,% -% z/% ,1% 2% 4% l6% %8% 9% S;% <% =% c>% 2?% p@% A% B% D% ME% F% G% I% J% NK% BL% M% N% O% +Q% .R% S% S% T% U% V% rW% VX% ;Y% Y% Z% [% \% ~\% v]% V^% ^% _% a% !b% .c% ;d% We% qf% g% yh% i% \j% k% ul% m% n% o% p% q% r% s% t% v% -w% Fx% 0y% @z% {% <|% "}% N~% b% ?% R% f% y% ~% % % % % % % r% % z% % % k% % ȟ% . >0 % Z5 s% §% % % % +% % ڲ% % % $% % *% % 8% % % c% % % [% % % % s% % % % % % r% 1% K% % % % % i% % % % % R% % % % % % % % % >% % % T% % % % % % % % *% % % % % % U% % % *% G% Z% % 4% % % c% % % % % a% % X% t% % b% % % [% % % S& % % & & & & & f& & & & O & & ]& & & & & ~& 3& & & z& .& & F& & & & = & & & & & W & !& && "(& "& $& v%& w)& *& i+& 1,& H-& .& X0& 1& \3& 4& 6& 87& U8& 9& :& ;& =& +?& U@& E& G& @& A& C& sH& I& K& L& uN& O& P& Q& VS& T& U& V& W& X& \Z& [& \& jY& ]& _& _& `& a& b& c& vd& Qe& f& g& i& j& h& l& l& m& n& o& p& q& r& s& t& u& w& x& fy& z& U|& }& }& & π& & ~~& e& ك& & ^& & & & & & Y& {& & & Ȏ& & t& I& & 6& & Ε& & +& ͙& & U& & & & & `& & {& c& & & & & Ĭ& & o& & & & & & g& & & e& <& ,& & & & & & & & ף& & & (& & & & & a& & & & j& & & & & B& !& ~& `& & & q& & & ^& <& & & K& /& & & & s& & & & & Y& ~& & & & & z& & M& & %' ' ' ' ' ' y ' A ' ' ' ' A' 6' ' R' ' ^' ' T ' ' / ' !' "' #' $' &' '' 6)' %' p*' +' ,' -' .' /' 0' 1' 2' 4' ,5' K7' 8' =6' :' :' ;' <' =' >' ?' "A' B' C' 9D' E' qG' I' J' HL' M' N' O' P' }Q' R' ) N) * + , , f F/ i1 &2 3 >5 6 +: ; < LC F F H |J WL ;O P `S T DV Z \ ] N^ ^ b %j oq v w vx y y ,z z I Q d v x 3 # -{ <| | } ~ ( ď \ ԕ O !# L# y# t 7 /# # 9# # L# # # 5 # / z L ` P 2 e _ v x B 8 X ސ $ $ Q ړ q E ~ H v H A D Χ# # N 4 ^# c 9 A > + ! I a # # >' ߢ - G2 3 x4 t5 }6 7 8 : C; L< e@ JC A D # # ۬# F |G I *K YL {M N O U \ 0 v Pp x , S !# # # w# i# # ְ# # # # 8# # # # R# # ƶ# # # # # # # r# E# ^# # R $ # # $ $ $ {$ # # # $ $ $ $ Y# # # # # # ## $ M $ $ a# 4# # . $ B$ B# # _$ # " # C# # $ y z B{ { } y # v# B 5 # # z Z " $ S% % n& # # # # # # Q# 4 ى " α ֲ r ܴ Q # U# # w D r $ T i ~ = *( >V V iV V V !V V V ;V mV V # # w# # d# - uo# e4 p# p# q# => ;r# r# "@ s# ,t# t# R u# fv# <# M=# t># ># ?# @# A# nB# B# " W &Y )w# ` 2h x# # Jy# # " i# # "# # B# ʉ# h# # &# # # # # # # -# |# Й# C# D# `H# # # Q j {# G {# & # # # %# N" 1" S" " " .z# 0{# 9 # S|# " " }# G ) * , M- . / W0 0 " P [" o" ," Q " gR " U V [# *# # &m " m " # L # H# uI# ]" " " " " |" # # I# J# K# R" *!# !# 9L# IM# N# " " " " '" %" "# t## N# O# P# ." x" " *" " P" H$# J%# xQ# oR# S# T# " " " <" " i" R&# '# )U# U# V# 9" " N" 4w " " '# (# uW# RX# Y# " )# c*# YZ# " 9[# \# " " " " " " 4+# ,# \# ]# ^# _# " " #" " O" T # ,# -# P`# a# a# d# @# V# )# x# s# .# _/# b# Vc# yd# y# 00# 0# 8e# 6# 1# 2# e# H3# 3# f# # 4# 5# tg# h6# h# i# # # 9 # # # # 7# 8# i# j# ! # 9# 9# *l# l# x# # # # # # N:# :# Rm# m# n# # ;# /<# }# y E# e# { # D ] D T G B d WV V V V V mV BP KS P P mP P 4P 5Q %U V&U &U pU ]'U (U rU sU ,U .U 60U 5uU 2U 2U vU vU 5U wU xU 3zU {U }U ~U kU 9U U U >U >U ?U U U _U lU U U %U U `P P U S @U U ؐU ְS U U U U U S U .U U DU U U U mU CU 5U U T MU U U 8S U VS (S QU T #U U U U S S U U U U ϯQ U DU 9U U Q U IU U V V Q V V V N V V T BT V {V V T V V V QV V T V V pT T 'V m T H T V T T T eT V ? V V V e V i!V R R "V #V HR R $V %T %V 2&V uT T T &V @ T T T 'V | T W(V T T L!T (V )V h*V +V ,V -V .V /V 0V u1V 1V W'T R !R (T >3V 4V 6V s8V +T ,T a-T Y:V ;V <V >V .@V @V AV CV EV 0.T GV /T [U /T -R &0T <1T 1T b2T 2T HV T JV LV OV uRV ?VV ET XV ZV \V ^V `V NT dV hV kV oV qV rtV T wV zV V xV V V V 9V ikT mT oT qT sT !uT wT yT dV ƔV AV ˛V ͟V áV V T V :V V V V V >T V {T `R qV V V =P P P `P V &V V ? 7 o t l ۪ ; 6 1 ; ɴ 1 i ɹ h U C 7 n v k A ; b j ) m K " i F P $ 2 e P " 2 + 0 ] C 2 R ? v >- [ I V q ܕ" 3" p" " \" җ" < S ( H" ( R " " u" " E i p " [ % P { E s = k 5 c - X % M { E w E < j j } h d Z S L b z X ) M # W / u! ]" J# # 8$ $ F% % 2& & F' ' !( !) :* + :, , . j/ j0 1 V2 3 F4 ^5 6 o7 `8 Q9 E: 9; < < .> z? @ A B !D E F (H .I J K L WN O P Q DS <T U W HX Y Z \ \ E^ _ ` a b c e df fg h i j l m n o Tq Fr s u u v {w :x x y xz !{ { | ~ Z x a L Γ F T 1 y Ե G W \ ʣ ޠ # ٤ j z ۧ < ` t x O R L N r M = 1 c 3 m a B m l J u t R 6 r v 6 .! " $ o% & & @' ' w( ) * + p- . [0 1 D3 $4 5 5 6 7 8 r9 ]: E; -< = > ? @ A B +C 6D >E FF NG VH aI lJ tK |L M N O P Q R S T U V }W "X X jY Z Z b[ \ \ ] ^ _ z` $a a vb #c c }d (e f fh j k Dm n p q zq q jr r bs s t u v w x z { | | } {~ L 4 e J / . < H Y j { ݒ 4 ٓ ~ # ƕ n d b d [ 6 إ y 5 ' m O / ܳ * A X o Y 1 ۿ R . M t = U p @ b , D Y n K k @ f . R a R ^ p % ` D ] y $ { ! m" # $ % & ( *) :* * + S, - - u. / / 0 1 y2 R3 *4 4 6 _9 < ? DC F I -M xP S W [Z ] _ a f /j $n 2r u z U{ {| t} ~ R b ͈ ΐ t < b * ! M" # # $ p% 8& ' ' ( ^) &* * + , L- . . / o0 :1 2 2 3 Z4 %5 5 6 7 H8 9 9 : r; >< = = > t? Y@ @ ,A A A !B B C D E F yG H H oI I _J J CK K 'L FM 3O Q S S T |T T jU U RV V W X Y Z [ w\ j] K^ *_ ` ` Pd g j Fn q t 6x { ~ & y ʈ ފ c } o C % 3 A v ڝ \ . \ Ѥ f ۥ P æ L ӧ _ P ! + 7 n t ί % ٰ 3 k ն m 8 ӹ k ݻ R ľ 6 n O - e N 4 : @ F L U ^ d j p v T t 4 x T } K u 3 P 2 Y C ? = < & / . # , / ` ] S ] } p _ h ; G P # u A w C ` ! " # % D& i' ( ) * + - . 6/ O0 e1 2 2 3 44 4 5 6 7 8 9 ; < ?= i> ? @ A `B 0C D D E lF 5G G H I SJ K L (N O Q R 7T U IW X \Z [ Q] ^ a` a Vc d f g i rj "k k l 8m m n =o p @r s u v x y z { | } 0 > և ! j M * s Ȫ Ԭ x C Ư I Ͱ Q ձ L ò : . h ۶ J $ j a C h % ~ ` r a A A L Y " V F 2 ! t & G $ r n j h J ' a ! ! ! Q! [ ! ]! X! ! ! ! H! ! b! ! ! ! ! 3! ! ! H! / ? j ! V! ! ! ! }! ! a! ! =! ! ! {! ! Q! ! ! e! ! A! ! ! i! ! ! ! +! ! W! ! ! W! ! ! ! ,! v! ! t q n k h h h h h p! W C ? ! K! A! G ! 6! ! ! O! ! ! x! ! >! ! ! [! ! ! x! ! 6! ! ! ! ! u! ! +! ! ! T! ! ! }! ! ;! ! ! X! ! ! u! ! _! ! L! ! ! j! ! 0! ! ! Y! ! ! z! ! 8! ! ! U! ! )! ! ! ! ! J " " " o" " 5" " " Z" " " w" " 5" " " h" " S" " 2" " " K " " " t " " : " " " W " " " t " " 2" " " " " q" " '" " " P" " " y" " 7" " " T" " " q" " [" " H" " " f" " ," " " U" " " v " " 4 " " " Q " " % " " " " " F!" !" "" k"" "" 1#" #" #" V$" $" %" s%" %" 1&" &" &" d'" '" O(" (" V +" k-" )0" 0" 0" j1" 1" ?2" 2" 3" }3" 3" 4" `4" 4" 5" u5" 5" 5" @6" 6" 6" d7" 7" E8" 8" 9" k9" 9" 0:" :" ;" l;" ;" 2<" <" *=" =" Z>" >" ?" g?" ?" @" q@" @" &A" pA" A" B" RB" B" B" IC" C" C" ZD" D" E" |E" F" \ ] ^ F" CH" K" =N" c f S" LT" T" U" eU" U" +V" V" V" TW" W" X" qX" X" /Y" Y" Y" LZ" Z" 6[" [" #\" \" \" A]" ]" ^" j^" ^" 0_" _" _" Q`" `" a" na" a" ,b" b" c" uc" c" bd" d" !e" e" e" Ff" f" g" og" g" 1h" h" h" Ni" i" j" kj" j" ?k" k" *l" l" m" `m" m" "n" n" n" Ko" o" p" pp" p" .q" q" q" Kr" r" s" ~s" s" it" t" Hu" u" u" av" v" 'w" w" w" Px" x" y" my" y" +z" z" z" H{" {" 2|" |" }" }" }" =~" ~" " f" " ," " " M" " " j" ɂ" (" " " q" " ^" ƅ" " |" ߆" B" " " k" Έ" -" " " J" " " g" Ƌ" ;" " &" " " \" " " " " G" " " l" ˑ" *" " " G" " " z" " e" yh D ! [" " # 1$ $ e% % ]& & U' ' ( ) ) A* + , - / #0 .1 2 3 4 6 7 8 p9 : ; < = > >@ TA B C D E 7H RJ |L N O P 2S NU zW Y Z [ ^^ ` c Re of g Ij l n Bq ^r zs t u w x y z a{ }| } ~ & ֆ LJ ֎ Г ו ɖ 0 Ŭ ح ( k ɮ [ 8 z U @ y * ۷ = X Ƽ } / E _ { 0 ; = Q n # E i A g H i ; ] 4 M j ? _ 5 Z & p N / \ 6 f b ! w ! ! M! ! %! ! ! n! ! J! ! *! ! ! w! ! W! ! s! ! ! t ! ! ! y ! & ! ! ! .! ! ! )! ! |! &! ! |! '! ! ~! *! ! z! "! ! s! ! ! p ! ! ! o ! ! ! n ! !! !! m"! #! #! p$! %! %! u&! "'! (! )! +! E,! c-! .! /! !1! r2! 3! 4! 5! H7! r8! 9! :! <! =! >! ?! @! &B! >C! VD! G! OI! K! M! O! P! R! U! nW! Y! Z! [! ^! Ca! c! Bf! rg! h! k! m! p! s! /t! ^u! v! w! 7y! ]z! r{! |! ~! 9! ! ʁ! J! \! |! ! ! ! *! <! ]! s! ~! ! ژ! ! ! $! ! ! ! ɢ! ! ! H! w! ! 9! r! ! γ! ! Z! ! ! P! ! ! U! ! = 9 ղ w Y Į E Ư P հ \ n ~ # Z ܸ f M Һ W ܻ \ r ͽ ( ߾ ; ÿ J + - % 7 b # l - s 7 z ; E O S ] g ( k / } B Y } Q p 2 ^ C v J o { S 7 B L > { $ R 3" ~% ( , Y/ 2 5 49 < ? A C D E F G I -J |K L ?M M N &O O AP P gQ T fV X Z c] ` ` a ta Pb 1c d d e ^f f g h i tj Wk k l m cn 9o o 6p q /r fs ,t "u v v w y z { v} ~ i 8 # $ ` + ϐ = 9 L Q V t b ؛ N 2 m ۠ F ơ F Q ԣ T Ҥ Z ڥ K j h [ # ] # U & P a Q e N 2 r @ S 1 H P V T \ : = 9 g M u + u ] x & e % ] " 7 & V y 8 c 6 w / S ; ] [ 1 v M ' e G & } 3! 6 8 R* + . >0 S2 Z5 >E G l; 9= > P@ B C " a# {$ % & ' ) H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c bd e f g h Aj k Ul l |n p }q s t )u u Yw x y z { | F~ p ̀ + I Dž $ ߆ < ψ 9 $ G Ր ` ϗ m ] 9 ˞ ( 2 ] 5 ̫ b 5 ٰ t @ Դ a & ɹ ' = [ | ' 6 H W ^ e q ? i 2 > 2 A 4 8 = $ & } 4 [ Y ) J T 8 / 2 5 9 D< h? B E ? S" % ' h* - H L GO R U Y W\ _ b !f ci l o q s t u Rw x Oz { J} # ~ " m ʅ @ ` Ƙ ( Z $ Y } 9 a I m ) Q y 9 ] A i + S ~ I } O k \ n w " < T b k m g ! 3 F k ( \ v J V * X z / _ & 6 C S l q w k - Q u 1 Y K _ s 9 l ( P P [ i! ! " # # J$ $ t% & & ' ' T( ( }) * * :+ + l, - - -. . H/ / }0 1 1 72 2 g3 4 4 55 5 a6 6 7 )8 8 S9 9 l: : {; ; < = = )> > \? ? @ %A A IB B rC D D 7E E `F F G (H H RI I wJ J K 2L L [M M N O O RP P Q R R ,S S eT T U %V V QW W X Y Y DZ Z X[ [ \ "] ] G^ ^ s_ ` ` ;a a fb b zc d d De e if f g h h 3i i >j j Ik k [l l zm n n $o o 8p p Gq q Vr r fs s }t u u v v .w ~ 3 { | | } } ~ w 3x x Ry y yz z * ƃ V w Z F 8 ܈ $ Ȋ o ^ M < + ғ d @ ї _ ~ ? כ o 6 ͞ a C Ӣ c ' > ȧ \ F ֫ f ? ԯ f 9 dz X z H { : κ e C Ӿ f , C Z p 2 ] } 3 V v : h . \ > p - U } @ l 5 e " X - tY 8Z l[ ] \ ^ _ ` a b 7 : dc Te *B pf g P ` * x R ( Bh h ui "j j p +q q r R v ~S T U i u Y [ j bv c_ / 1 [3 ĝ" " " ܠ" 6" " " 8" " " " " " h" ɮ" !" ~" -{ | } ~ v w # d # E> & ( * , 5 7 58 8 R: j; 0= D> \? @ A xC D E F k k l Xm 6n n o <p l }H I GJ J K ) p uL N O &Q R T U LW X Y [ \ |^ _ a b Re qp f Ch i x { { ~ " ó" " ~" " a" " " r" 1 1 3 6 7J v7 "8 : ; a< < = > ? ;T ? @ 3A 4B 8C C 7 $D E J v v p wG H I J }6 7 8 : KK L N N D AP Q AR iS cU V W }Y Z [ \ ^ >_ \ 0 -a b c a d e 3f f g h i 5h j Qk k hl m n m so 3p p Jq r s q Ut u u ,v w ex v 7y y z r Ft 7u `s 4v w w x ?y y { | z s} R~ ~ p B < P ? 0 ݆ R P ( n { | } { ~ V = s E ֆ X * Ί ` s E { ` đ ; U R c [ L ֍ C ֓ } s l ? % h ' ɗ d Ν c 3 c ߡ 2 y l 2 H Ѫ ; } Э d . ס I F + i ~ խ ̮ ̯ e . P 0 : a z % j n } & p * 9 ` , n Y * ղ n ڷ ) ˺ q { A 5 U 2 P 0 f 8 ; j _ = u ) 0 E C i U \ q 7 o n , K H r h " < R P x y X ; e + m ^ & \ W f V 5 ` y = c 3 K ' t - P i q H f ( b G { - b = 9 y j I Z ` 7 e m J - q : v B b F 3 K _ + e `! ! w" # $ &# g% !& & 8' ( b) ' (* * n+ - D ] ! p u O ; k + v! @" # # e$ $ + k- 5. , / / K0 0 v1 2 a3 2 4 4 35 5 6 7 H6 J8 8 k9 9 &; ; : < '= = > ^? @ > @ _A A Q W 1 [ ! b % p! " # +" $ V% % }% (& & ' ( ) /( O* * + + VB bD yE SC F G fH AI J K L J M N nO &P Q R Q S T yU 1V W X W Y Z [ <\ ^ ^ ] _ ` a o& ( ) p' * , + - . ^/ R1 W2 R0 b3 a4 %5 -6 6 7 : ; 8 .< 9= > , - . / 1 y2 0 y3 m4 +5 5 Gb d e (c f g g nh ,i j k i ll :m m sn p p 6o q r s s Lu v }t v w ex y z g{ y A| } } > @ A ? B jD C <E E F {H dI G SJ 6K K L qM _N 3P (Q CO #R S S 6 e7 98 9 : ; 9 < Z= = > H~ ǂ d ̈́ K @ ։ T I ߎ ] ' R f 0 ė [ mT -V W DU X Y Y Z ;[ [ ] y^ \ ^_ 7` ` a \b @c e e d f g ih @? @ @ A =C D nB D E UF F ٚ ޛ ܙ ^ & ̡ f Y 7 @ ĭ ' Ͱ s Q 5 i k l i m n n o p ]q -s t ?r u v v w _x Wy ?{ >| Ez C} <~ ~ G H _I JJ L L !K M N hO P Z 3 U i ν ? B r < u 4 o 2 g ? w n n \ f : ɋ q Y ʏ 7 P Q \R 9S T U T V eW X ? $ / " ] . r & ^ * D ] " j : [ 1 h - F [ 6 ͜ g + ֡ Ǣ v P A ' G ' l @ b : k G ) 8 a c! # # ." $ % e& 0' ( ) ' * f+ 2, ˭ k F ' ʲ p : ٹ j g r j a N , - . / W1 =2 v0 )3 4 4 5 f6 7 8 %7 9 `: 0; ; < A> ? r= ? @ A DB C D C E RF G G kI ?J H K K L nM O O 1N P |Q @R : v C a 9 v e 9 . I ) S S T U 5W X \V X Y Z j[ \ ] n^ \ B_ ` ` a Sb c d c e Wf g g hi :j h k k l am n o "n p eq 'r r vt Hu s v v w m > u 6 c : % t ox By z z | s} { U~ + n ' J Ά ۉ D w 5 x F ] M ȗ N v V z A G s Z , 3 ў G t ϣ ^ ߦ h : ګ C l װ n 9 ε p ; ݹ q = Ӿ h > g 1 f A u V K + " y / N F h @ q M / > g i 4 k 6 l 8 v Q 2 {! E" $ % %# % & ' ( ) * u, r- }+ u. l/ Y0 ] C | / l + f 6 G x J X q E t 7 F E1 2 3 2 4 6 N5 6 7 l8 (: ; D9 < < = > ? p@ DB 9C TA 4D #E F ; b p T \ ! Y" )# # $ `% & ' & x( <) ) * -, , h+ - . E/ / |1 F2 0 3 3 4 F hH 1I G J K J HL M M aO @P N %Q Q R S ~T cU #W X =V X Y Z M5 6 6 7 M9 !: ~8 : ; < P= > ? t@ > PA B B C D F F JE G H wI @J K L K M lN 6O O Q wR P WS +T T U \W 6X V Y Y Z [ 5] ^ a\ ^ ` _ ea .b b d e c f g jh ]i ;j 0k m n l o p p }[ X\ 3] ^ _ ` ^ a yb Mc d d nf Dg e h h i j Qk l m l n }o Gp q r s q ht <u v v mx Gy w 'z z { | ,~ W} q rs Kt r *u v u w kx 3y z { z | } ~ x m M H W I > ) M ( k I & ] Ȏ ^ ّ g 9 ݕ ` ! d & u G n Τ / r 4 p ӈ G h ( Ǒ l W - ݙ ֚ Û Ȩ { F ۭ } H l ű H y B Ѻ o 8 ־ d . o O # T . $ P ܠ { T å z Y L * ۲ u P + q E N D a 9 I N o G $ W \ ų Q " ķ Y ں y f G u X E ! n L ~ ( - : * ; ^ < O p > " ˾" T 0 ύ n Q ߤ ] G BP KS P P mP P 4P 5Q %U V&U &U ]'U (U *U w+U ,U .U 60U +1U 2U 2U t3U N4U 5U 5U (7U 8U ]:U <U i=U >U >U ?U ?U AU BU CU DU KEU FU `P P FU S ȧS 3S XS ְS ֳS S S ϼS jGU S NU S S yS S OS S SU {S S S τQ 8S S VS (S S S ~S S S T BT T T T T T pT T T m T H T T T T eT +T T ;T T R R R %T T uT T T T @ T T T | T & T T T L!T "T #T WU G&T W'T R !R (T T )T +T ,T a-T XU 8ZU 0.T NT /T [U /T -R &0T <1T 1T b2T 2T 3T 5T 9T @<T \U NCT ET IT ]aU KT NT RT VT YT ]T aT cT fT ikT mT oT qT sT !uT wT yT {T T T T T BeU lU T T T T ]T >T T {T T @T "pU >- l m n [o &p p q r r ns t t xu 8v v } ĵ Ѷ + " ; / F : o 2 B U / z M k A R $ q L ' L ! O" # # $ |% P& ' ' ( ) w* d+ Q, } 8 j L n & > T x L V O H U H R ( b U Z E O < h 3 g ! U a! 0# $ & ( M* , - u/ +1 54 4 2 3 6 7 5 16 -8 9 9 : ; < < = = > > ;B E DI L O jS W [ _ c g k so r tv y } ۄ ܐ ϔ ߘ s ݣ n \ ر w x 2y y y >z | ~ 1 ԅ ' T , : ڒ A > n ߚ M z 4 R + ] * o M _ 3 ۷ ' z ` G M DT hU V DY [ (^ ` c e qh j Io l Rq s u ju v x Zy z { P} ~ @ 6 N G ~ % ] ͗ = u u $ w W F ~ , f N g = ~ T# % *( * - z. / n1 2 e4 5 47 $8 9 ; < > ? C A E ,G LH dI J P V )\ b (h m r Tx } g ] % Ԣ ۣ @ J T ĭ & & I : + E _ P A [ u . F _ Ų x * ܴ @ V O z < ҽ h ) S } < S ( ( R | 0 E i p : G< E> > H? ? z@ %A A kB C C D YE /F F SG H H I ^J K K uL "M M N 1O O Q =R bS T U V W Y 2Z Z [ [ [ x\ \ i] 8_ a b f d h i oj k k - . D j [ f 3 / 0 0 / ? j 6 t q n k h h h h h W C ? j : G # + 3 6 4 2 0 V Q S V ^! ! f" " i# # g$ $ e% % c& & ' 0( ( ) ) * * |+ , , - - . . / / 0 0 1 1 2 2 33 3 4 .5 5 06 6 37 7 ;8 8 C9 9 F: : D; ; B< < @= = f> ? ? a@ @ cA A fB B nC C vD D yE E wF F uG G sH H I @J J K L L M M N N %O O -P P +Q Q )R R 'S S %T T sU V V Y [ \ \ \ ] ^ ^ 6` c f h Vi i Lj j Tk k \l l dm m bn n `o o ^p p \q r r Ss s t u u v v w w x x y y z z { { | | 6} } ~ 1 3 6 > F ʃ I Ȅ G ƅ E Ć C i d f i q y | z x v C " ( 0 . , * ( Ϟ v ʠ U ̡ K Ϣ S ף [ ߤ c a _ ާ ] ܨ [ R yh 5 Z b 7 U O / . e ! ! " o" # # $ $ % W& ' ' I( ( [) ) U* * P+ , , [- . . / / 0 1 3 @4 i5 6 7 7 8 : 5; ^< = = +> > ? ? @ @ @ C C D E F G nH ^I MJ >K 2L M N AP Q S T V bW X &Z [ \ S^ _ ` 7b c >e sf g \i j k Rm n p q r ev y K} P & Ǐ M h ڕ D 0 ; > A X $ ݳ ? o ~ T * j R : " + ^ & B 2 H # G s X , h K ) * < H l C } $ # & * - 0 G4 7 V I r T [ F ` " H @ x Y $ 6 U R q j 2 # % # ( = , ! Z% 1/ ( , e/ P2 8 +< u5 ? B 6F F G G H J L 2N :P zP P P :Q Q R T U U V "W W hX Y <Z n[ \ ] ` a hc Bd e g aj k m Mo $p dq &t u v w z | # Q x h h @ c 6 ] ޙ " X ĩ ܬ S ϱ ^ M ڻ g & 8 G % # O & " g 2 s % o s" 'K # g$ Q% {& M' i( b) * * ), , . . / 0 1 2 m3 R4 p5 $6 6 7 ~8 9 : |; < y= > .? ;@ @ *B C D E E F nG H =N O O R v ~S T T U )V W LX X Y bZ [ *\ ] ^ c_ "L ~ D ; V 3 o > X [ . p # L( - . 0 4 {8 ]< E> > ? 8A B C s t u v gw x y y ^P Q R S U HV W *Y Z [ ] ^ 1` a Gc e f _h i j l n qp ,q r Ws _ ~a nd e g Eh i .k 0 - E E F I 7J J K =L M M N $O O P 6Q Q TR RS S ;T U U V W W GX X Y Y Z 5[ [ \ 0] ] 'l l !q r s h^ u R_ ` ~u v v v ww Qx z y a c *e f h j l &o p q fs u | |} ~ b Ձ G , u w w (y z | } q z { E E Ԁ ܁ > V ǎ Ԑ ݓ ݕ & ? > 1 r E _ I ~ H \ s = I { @F `G M # O| | } H ] ȃ ' - Z * U b G B |H 0 ύ n D Ӑ e Q M ӕ ϖ U Q ٘ ՙ ] \ m l } n Q BP KS P P mP P 4P 5Q `P P S ȧS GT fT ְS T S S 1T T S T uT T yS T T T {S T T τQ 8S S VS (S T S T S S T BT T T T T T pT T T m T H T T T T eT +T T ;T T R R R %T T uT T T T @ T T T | T & T T T L!T "T #T ^$T G&T W'T R !R (T T )T +T ,T a-T 0.T NT /T /T -R &0T <1T 1T b2T 2T T T LT T LT NCT ET T T NT RT VT YT T T T fT T 1T QU hU U U (U U {T T U zU U U UU o U T _ U >T T @!U "U @T l m n [o &p p q r r ns t t xu 8v v w x 2y y y >z | ~ 1 ԅ ' T , : ڒ A > n ߚ M z 4 R + ] * o M _ 3 ۷ ' z ` . F _ Ų x * ܴ @ V O z < ҽ h ) S } < S ( ( R | 0 E i p : G< E> > H? ? z@ %A A kB C C D YE /F F SG H H I ^J K K uL "M M N 1O O Q =R bS T U V W Y 2Z Z [ [ [ x\ \ i] 8_ a b f d h i oj k k D j [ f 3 / ? j 6 t q n k h h h h h W C ? j : G # + 3 6 4 2 0 V Q S V ^! ! f" " i# # g$ $ e% % c& & ' 0( ( ) ) * * |+ , , - - . . / / 0 0 1 1 2 2 33 3 4 .5 5 06 6 37 7 ;8 8 C9 9 F: : D; ; B< < @= = f> ? ? a@ @ cA A fB B nC C vD D yE E wF F uG G sH H I @J J K L L M M N N %O O -P P +Q Q )R R 'S S %T T sU V V Y [ \ \ \ ] ^ ^ 6` c f h Vi i Lj j Tk k \l l dm m bn n `o o ^p p \q r r Ss s t u u v v w w x x y y z z { { | | 6} } ~ 1 3 6 > F ʃ I Ȅ G ƅ E Ć C i d f i q y | z x v C " ( 0 . , * ( Ϟ v ʠ U ̡ K Ϣ S ף [ ߤ c a _ ާ ] ܨ [ R yh 5 Z b 7 U O / . e ! ! " o" # # $ $ % W& ' ' I( ( [) ) U* * P+ , , [- . . / / 0 1 3 @4 i5 6 7 7 8 : 5; ^< = = +> > ? ? @ @ @ C C D E F G nH ^I MJ >K 2L M N AP Q S T V bW X &Z [ \ S^ _ ` 7b c >e sf g \i j k Rm n p q r ev y K} P & Ǐ M h ڕ 0 \ ] > X $ ݳ ? o ~ T * j R : " + ^ & B 2 H # G s X , h K ) * < H l C } $ # & * - 0 G4 7 ` w H @ x Y 6 U R q j 2 # # = ! Z% ( , e/ 2 5 8 +< ? B 6F F G G H J L 2N :P zP P P :Q Q R T U U V "W W hX Y <Z n[ \ ] ` a hc Bd e g aj k m Mo $p dq &t u v w z | # Q x h h @ c 6 ] ޙ " X ĩ ܬ S ϱ ^ M ڻ g & G % # O & " g 2 s % o s" 'K # g$ Q% {& M' i( b) * * ), , . . / 0 1 2 m3 R4 p5 $6 6 7 ~8 9 : |; < y= > .? ;@ @ *B C D E E F nG H =N O O R v ~S T T U )V W LX X Y bZ [ *\ ] ^ c_ "L ~ D ; V 3 o > X [ . p # L( - . 0 4 {8 ]< E> > ? 8A B C s t u v gw x y y ^P Q R S U HV W *Y Z [ ] ^ 1` a Gc e f _h i j l n qp ,q r Ws _ ~a nd e g Eh i .k 0 - E E F I 7J J K =L M M N $O O P 6Q Q TR RS S ;T U U V W W GX X Y Y Z 5[ [ \ 0] ] 'l l !q r s h^ u R_ ` ~u v v v ww Qx z y a c *e f h j l &o p q fs u | |} ~ b Ձ G , u w w (y z | } q z { E E Ԁ ܁ > V ǎ Ԑ ݓ ݕ { @F `G M # O| | } H ] ȃ ' - Z * U b G B |H 0 ύ n D Ӑ e Q M ӕ ϖ U Q ٘ ՙ ] \ m l } n Q BP KS P P mP P 4P 5Q `P P S ȧS 3S XS ְS ֳS S S ϼS gS S jS S S yS S OS S AS {S S S τQ 8S S VS (S S S ~S S S T BT T T T T T pT T T m T H T T T T eT +T T ;T T R R R %T T uT T T T @ T T T | T & T T T L!T "T #T ^$T G&T W'T R !R (T (T )T +T ,T a-T 0.T C,R /T /T -R &0T <1T 1T b2T 2T 3T 5T 9T @<T ?T NCT ET IT KT NT RT VT YT ]T aT cT fT ikT mT oT qT sT !uT wT yT {T T T T T T T T T ]T >T T {T T @T Ѵ L [ 2 ӱ j ` ; ] ۻ s" 'K # g$ Q% {& M' i( b) * * ), , . . / 0 1 2 m3 R4 p5 $6 6 7 ~8 9 : |; < y= > .? ;@ @ *B C D E E F nG H =N O O R v ~S T T U )V W LX X Y bZ [ *\ ] ^ c_ "L ~ D ; V 3 o > X [ . p # L( - . 0 4 {8 ]< E> > ? 8A B C s t u v gw x y y ^P Q R S U HV W *Y Z [ ] ^ 1` a Gc e f _h i j l n qp ,q r Ws _ ~a nd e g Eh i .k 0 - E E F I 7J J K =L M M N $O O P 6Q Q TR RS S ;T U U V W W GX X Y Y Z 5[ [ \ 0] ] 'l l !q r s h^ u R_ ` ~u v v v ww Qx z y a c *e f h j l &o p q fs u | |} ~ b Ձ G , u w w (y z | } q z { E E Ԁ ܁ > V ǎ Ԑ ݓ ݕ ט ; x S 4 Ћ s č r n N ; ݝ ~ & ɟ ^ đ $ _ ) Ɣ h U S . E ʥ e ը ? p L . ֞ x 4 m Ы h F } & & 7 Ƥ Z I г A d շ C l w : ̫ e F $ $ U Ȱ " f 5 f d > ׳ w µ m ` A # i ) N I y H ο / s V , K o N v 9 x P ( [ " ^ * + c ] y > Z k # Q } ( E g H e c > A 9 k # @ G ? O ] 7 C W j W a W S g B D ~ D ] - l G # g Y F j * G M n ( l + b r M z " y 1 ! 9 G ! m v % 9 { @F `G M # O| | } H ] ȃ K ' - Z * U b G B |H 0 ύ n D Ӑ e Q M ӕ ϖ U Q ٘ ՙ ] \ m l } n Q K W, , , S- - >. . R/ / \0 0 :1 1 &2 2 )3 3 ;4 4 >5 5 K6 T ' q j % n ) g %! ! ! a" " # q# # +$ $ $ I% % & ]& & 6 7 }7 7 [0M -' ' > ,? ? @ @ , E Q8 8 ?( ( ( I) ) ) P* * * E 8 D9 A QA A Y < ` F ) o K $ < 8 = G R + & $ x ( D F R 5 z K c = e s ) ; X l e 9 4 A 1 S o 2 , : k: B B gC C @D D M 2 6 v : ; ; ; y< c ] H r [ > > 5 | Q G+ + < ?= , = = W> e t S S GS S ԎS *S S S S xS S S S ~S TS S LSS /S S S rS S ՞S S -S S aS S S S 1S эS aS S S eS S S S eS AQS QS ƔS aS &S C\S \S RS S S fS S \S ~S *S S ^zS zS UyS |S {S |S S R] \ ` _ _ <^ X [ Z Y 2Y X T\ la ` ` m `c c g ^d Ae f f Di h j j >l k l a c b ab u Vu mx u w Mv v Uw n p ]r 7o o ,p t | ht ,n s s 0s Xy ]q q hn x y Wz y s{ z { 5 _5 3 4 {4 4 6 ^ M x 6 Q ? m ; b F $ % M ] P u I l % " ! '" !$ 3 $ # 0! ? Z| - z~ `} } | J k x a : т 2 , m ҍ 5 A h Ƒ X u ؝ Ŝ B 4 n " | X Ɔ ' ʅ 5 Z ^ ߉ ֊ . ) < շ I s > l f : Ӳ d c , x 7 $ . 3 V ߿ ] k V = M ] x g 6 y h 13 & ' , ) ( + Y' ) & D, `+ ?( ) `* y& 4- 2 / 1 . / . ?2 Y1 x/ X0 - # < n v j 8 , = a I g 6 6 N7 8 9 9 f 7 8 k8 ՟ I F N p С < \ sVS JS wOS _MS \S @S HS GS @S 2ES FS VJS ]S aS C_S cS 8?S CS BS LSS US KTS TS ZUS 5YS YS VS WS XS YWS b[S ZS -LS KS LS ^PS OS PS nNS MS NS [S ZS AQS QS RS XjS wS mS fS gS C\S \S RS pS 1tS 0hS AiS "BS IS IS `AS \S >S }S yS yS ^zS ^zS zS UyS |S {S |S }S W < ; J 3J I I D RH XG F F cE ; +R P Q N 8O O SP R dS S T 5U M N hV U V {K 8M L L L Y R И F D ~< \> '@ = c= > IA M @ A -? y? ] B B 5 _5 3 4 {4 4 6 ^ M x 6 Q ? m ; b F $ % M ] P u I l % " ! '" !$ 3 $ # 0! ? q - J k l B $ _ l Jl #k f k g d be d f 0g j i i jh Mt s fq %r o (n lm up n | F{ ]y :z lw u t Qx {v K O ~ E} ~ c b @c a }` ^ _ ta ` 9b a i^ IP 7O O M )M YK kN K 'J I :I J |L (; ; < C< H NH G zF G RE D E ] q] \ [ \ WZ Y Z \U S ~T 8 C C ? mB e? A +> K@ > @ + GD C B SD C k DS P xR Q Δ = D= nY X @X W W U U V D Շ : 13 & ' , ) ( + Y' ) & D, `+ ?( ) `* y& 4- 2 / 1 . / . ?2 Y1 x/ X0 - K # < n v j 8 , = a I 6 6 N7 8 9 9 9 A: : Q6 7 8 k8 ~ ; 7 J y p * ' s S E ܠ = 6 գ m 7 Ц i a n { * Q j 6 7 D O h ' m V A ! c ѩ i ǯ b 1 ʬ c . 1 ˲ e 6 ѵ l 2 E X F e k ~ / 9 X w , I / ѿ u s3S 5S 4S 7S 2S <S =S 4S X;S ;S >S 8S \<S 6 : C U W ~ q Q 1 y &! & & =' ) v( ^/ . , [+ 1 75 [4 3 2 1 N VN \A D o E :C D M A ;@ J SL G zG v N O >O j ݻ ֺ ) ʳ c m | . 7 % i$ U" # " : ҧ F ;: 9 j8 8 D9 ] j6 O 6 G _7 ڝ h 9 : 9 o 6 % 3 ' 5 e; / < r< + z( ) "+ 8* ' ) & ' . s/ + d- - Y, , z. 2 1 1 52 $ | [ 5 P ; [ n * L" ! " {# ! z ה W w / g 1 I 4 . } B I \ ʼn c . đ l g z% : \ 7 y> > J 8 = &? >S S }T U U aV W W P pQ R R s3S 5S 4S 7S 2S 1:S :S 4S 5S 5S 8S Z S } 4 W ڥ * y &! ? ~ ? { ] o ~ l N N VN \A D H %B E :C D M ;@ J H SL G zG N O >O j ݻ ֺ ʳ ĵ Լ ` . m | . = % i$ U" # " : ҧ ] ߜ O G # ڝ h 9 : 9 7 6 Z8 M6 3 4 >4 5 e; / < r< = + z( ) "+ 8* ' ) & ' . s/ + d- - Y, , z. 2 1 1 52 P ; 2 , \ ה w b } r a g 4 } ! I ( j 0 ~ ʼn r } đ l g B ԡ y> > &> = ? &? >S S }T U U aV W W P pQ R R s3S 5S 4S 7S 2S 6S R7S 4S 5S 5S 8S Z 4 H &! & r ? ~ 3 N VN \A D H %B E :C D M r@ %P ;@ J H SL G zG N O >O 0 ߂ 8t x v u w } { z | bs p q r Ap GX 0b _ >] Z d m k _i g = % i$ U" # " E ݕ ] ߜ O G # ڝ h 9 : 9 7 6 Z8 M6 3 4 >4 5 e; / < r< = + z( ) "+ 8* ' ) & ' . s/ + d- - Y, , z. 2 1 1 52 G / ň ה ` j ӎ ' < U d V ْ ʼn đ l g B ԡ y> > &> = ? &? >S S }T U U aV W W P pQ R R xP P BP P P mP P 4P P P `P P P KR HR R 2R kR R R R R rR sR R (R R R R 1R o S S S S ~S 1S S WS S S 6S S S o S S % S y S F S S S S S S S S jS QS 7S S S S S bS 5S S S eS S S 4 S S O S S t S 4 S S %!S !S A"S "S F#S #S %S &S (S )S E+S ,S -S /S |1Q u0S N1S X ` < n 7 5 i K } & n - / 0 2 e4 V8 5 7 8 9 ; F< = => > ~? "@ VE H WM I K M N FP R R W &Y ` 2h o Vt # Q j G & B 9 ( G ] R ! a% G ) * , M- . / W0 0 P Q gR S S sT U U V W Z B] _ b 4e g j &m m n T p ts `t q Rv 4w f ! & ! y p P { D ] 4 = D T G B d xP P BP P P mP P 4P P P `P P =P P P `P 5Q 5Q 7Q ";Q =<Q v@Q ;CQ FQ IQ fKQ LQ OQ RQ XQ ZQ _Q aQ cQ eQ 4hQ 6lQ qQ tQ "xQ |{Q Q \Q τQ ÆQ Q JQ >Q [Q xQ iQ ,Q gQ \Q dQ Q Q Q Q ˨Q Q Q =Q ϯQ Q DQ WQ ^Q Q gQ KQ Q #Q Q Q Q Q zQ 9Q Q Q Q Q Q Q Q hQ bQ HQ [Q Q Q Q Q EQ Q Q Q Q tQ 9Q 2Q %Q Q Q Q Q Q Q Q iQ |Q R R HR R R R :R R R oR NR R R R R F R R R mR AR R R R R ZR R ZR SR VR R R R R # R R R R R R !R "R "R ($R %R 7'R 'R (R )R \+R C,R ,R [-R -R \.R /R 0R 0R 1R +2R 2R 4R 7R 7;R 7=R AR DR FR yIR `MR PR SR UR )WR XR _\R ^R bR 6gR jR nR qoR pR 9tR WwR 9zR |R R R ݆R +R R R R DR R $R ޚR R }R R R ZR R 7R R *R R R R R R `R R yR R R P "P 3P 9P cP P FP P P HP P 0P P P P P JP pP P qP P ;P * Q Q Q ?Q Q Q ZQ (Q Q Q >Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q wQ HQ /Q Q Q Q `Q - Q Q " Q Q Q 6 Q Q t Q !Q !Q X"Q "Q #Q $Q y%Q *'Q (Q *Q +Q Z-Q .Q 0Q |1Q u2Q b3Q X ` < n 7 5 i K } & n ) N) * + , , f F/ i1 &2 3 >5 6 +: ; < LC F F H |J WL ;O P e `S T DV Z \ ] N^ ^ b %j oq v w vx y y ,z z I Q d v x 3 -{ <| | } ~ ( ď \ ԕ O t 7 5 # / z L ` P 2 e _ v x B 8 X ސ $ Q ړ q E ~ H v H A D N 4 c 9 A > + ! I a # # >' ߢ - G2 3 x4 t5 }6 7 8 : C; L< = ? e@ JC A D F |G I *K YL {M N O U \ 0 v Pp x , S 3 Xu r ! hx v " y z B{ { } y } ~ B 5 z Z " $ S% % n& 4 ى " α ֲ r ܴ Q w D r T i ~ = *( - / 0 2 e4 V8 5 7 8 9 ; F< = => > ~? "@ VE H WM I K M N FP R R W &Y ` 2h o Vt # Q j G & B 9 ( G ] R ! a% G ) * , M- . / W0 0 P Q gR S S sT U U V W Z B] _ b 4e g j &m m n T p ts `t q Rv 4w f ! & ! y p P { D ] 4 = D T G B d [ ~P 'P CP P gP P P P 1P P P P P yP P ( I H E ;4 e }P ;~x <~{ B<~{ j<~| <~T| <~| =~} 9>~ L>~h >~ >~ ?~@ ?~ ?~ ?~ .@~ A@~0 T@~ @~$ A~ A~Ԉ A~$ mB~, ~B~, B~ B~T B~ B~` B~h FC~ ZC~ dC~ nC~# C~# C~1 C~X1 D~1 :D~ 5 CD~6 WD~ D~ BE~ IE~ UE~ _E~h sE~ E~ E~\ E~ E~/ E~= E~= E~4 F~8 :F~ MF~ XF~L aG~ G~ H~Ы ?I~ I~ I~0 pJ~P 0K~p OL~ L~ BM~Ь M~ N~ 8O~0 R~T >R~t |R~ R~ R~ԭ R~ /S~ jS~4 S~T S~t S~ T~ 2T~Ԯ WT~ T~ T~4 T~T U~t HU~ U~ U~ԯ U~ U~ 6V~4 KV~T kW~t W~ pX~ X~ $Z~ Z~ Z~8 #\~\ \~| ]~ R^~ ^~ܱ ^~ _~ ~`~< Aa~\ b~| 0b~ ^b~ c~ܲ c~ Me~ f~< f~\ g~| Lg~ g~ g~ܳ g~ Vh~ uh~< h~\ i~| Ri~ i~ l~ܴ o~ Up~ 9q~< zq~\ q~ r~ r~ 2s~ t~ t~ =t~@ Wt~` 1u~ xu~ Xv~ wv~ v~ v~ w~@ 8w~` w~ ,x~ jx~ y~ iy~ y~ y~@ y~` {~ w}~ ~ĸ ~ ]~ ~$ ǁ~D ~d 3~ ͂~ ~Ĺ ~ ~ ]~( ~H ~l Q~ 7~ ~Ժ ~ B~ \~4 6~T }~t ]~ |~ ܍~Ի P~ ~ ~4 K~T d~t I~ r~ ~Լ ː~ ~ ~4 ]~T ~t ~ ԑ~ ~ؽ ~ ~ ܓ~8 /~X w~x $~ c~ ~ܾ 7~ l~ ~< ~\ ~| ~ ~ ~ r~ ~ @~@ ~` -~ ]~ ~ f~ ~ ~ a~@ z~` ~ ~ k~ ~ ~ 7~ x~@ ~` ~ ~ ֩~ %~ @~ W~ z~@ ~` ۪~ .~ y~ ~ v~ ~ ~@ H~` ~ !~ ~ ~ {~ ~ X~@ ~` ~ &~ ~ ~ ~ +~ ~@ z~` ÷~ ~ $~ ~ ~ )~$ [~D ~d ½~ ~ ~ *~ ~ 3~$ ~D T~d ~ ~ y~ ~ ~ ~$ X~D o~d ~ ~ ~ ~ ~ ~$ $~H ~h ~ a~ ~ 6~ ~ ~, ~L S~l ~ 4~ ~ &~ c~ b~, ~L ~l >~ ~ ~ ~ ~ ~, ~L ~l ~ ~ ~ h~ ~ ~d ~x x~ ~ 8~ ~ x~P H~ ~ ~ 8~ ~0 h~L (~ ~ x~ ~h (~ ~ ~h H~ ~ H~ ~ ~ ~, ~X ~l (~ @ xd ( X (0 XL Hp ( x* *0 *D x+ H, ,$ -@ H3 h4 h5 5 6 6@ H7\ 7 X8 89 f9 9( 9H 3;h ; m< < < = (?( 6?H D?h d? ? @ ]A tA A( AH Ah A A B @B aB B( BH Bh C .C OC pC C C( CH Dh uD D D D D D, EL El E E E F F %F, FL Gl |G G G G H H, HL Hl NI yI I I IJ vJ0 JP Jp L 4L @M N O O0 !OP 0Op AO O P Q 'Q gQ0 |SP Vp WW W Z Z @[ \0 afP fp k l m n Ks s0 tP @up eu u w 2w rw Kx0 xP 5yp 8z { | 60 P p 8 Ȍ0 0P p * 7 _ ֒ 0 P ƕp K 4 <T t 8 Z 8 X (x \ D < \ | ) D Ol " 5 , L l r v Z , L l K . J , L Cl z $ =, L l Q R , L l ] , &P o&p & ' ) ;- / /4 0T 0t 70 0 a1 3 39 98 :X ?x A D iD D F TG8 JX [Kx K kL M P GS T8 1ZX ^x f *h h i k u< v\ Dw| y z | &~ 7 < _\ 3| S 技 s < \ | ď A q G @ ` ߠ 1 W 㩀D h / c ( ߱H h ﵀ =( dH h ߹ w v ( H h ּ 2 Q g }( HH h 7 } ۿ( H 3h \ .À ŀ +ƀ ǀ, ~ȀP Qɀp ɀ ɀ ɀ ʀ ʀ Nπ0 πP Ѐp р р }Ӏ JՀ ր ׀0 =P p ـ Mـ bـ ـ ـ0 ڀP ڀp Vڀ kڀ ڀ ڀ ݀ ߀0 2߀P U߀p ' 0 0 P fp p 0 DP p } 4 T t C s 14 T t J 4 kT t C f 68 \ N _ $ D d 7$ D d n ` ! ! ["( "L a#p % ' ' * 0 80 7<P =p @ mA kB %D F F0 HP Jp J <L *O MO vO O0 OP Pp Q Q -R ]R R >U0 WP Yp ] K] ` a 8b d0 AeP gp g h k Qm n v0 xP pxp x Uy ly y Xz z0 h{P |p C ꂁ ܃ 0 눁T Ct q 十 Z 4 5T Wt x 2 @ o 4 T vt W Ɩ t [ F4 T t ݣ Ȥ O % 4 T t K X 4 T t / Z T 4 .ÁT Át Ɓ ǁ ˁ ́ ́ ́4 ,́T Ẃt p ρ ρ Ё с4 ҁT ;ҁt "Ӂ PӁ ~Ӂ Ӂ Ӂ 0Ձ4 ՁT t 6ځ ځ ہ ݁ (݁! ?݁4! ݁T! ݁t! ݁! 7߁! J߁! ! " G8" [X" ix" w" " " " # 8# "X# Cx# d# # # # $ #8$ DX$ x$ $ $ $ -$ ?% Q8% cX% ux% % % % % & 8& X& x& & & & '& c ' q<' \' I|' ' ' l' ( ( @( `( ( ( v( ( ) $) D) d) 7) ) ) ) ?* $* D* d* A* * * * + $+ {D+ Sd+ + + + + l, $, D, d, , , 9, 9, l- $- D- d- - - - - . 6$. KD. gd. . n. & . . / (/ H/ h/ q / N!/ !/ "/ "0 R#,0 #L0 %l0 d&0 &0 &+0 ,0 - 1 -,1 .L1 .l1 01 01 11 J11 y1 2 302 4P2 +5p2 72 <72 82 92 93 :43 6:T3 f:t3 :3 h;3 )<3 =3 >4 ?44 AT4 CBt4 ?E4 E4 ?F4 F4 .H5 H85 IX5 Jx5 L5 L5 M5 N5 N6 O86 (OX6 ?Ox6 `O6 Q6 R6 S6 ;U7 U87 UX7 =Vx7 V7 V7 TW7 W7 kX8 X88 9YX8 Yx8 Z8 [8 [8 \8 \ 9 V]<9 ^\9 _|9 d9 d9 d9 e : e : e@: ef`: g: l: 'n: ]p: p ; w0; xP; )yp; wz; E{; ~; z~; < z0< ꂂP< bp< ņ< < u< q< = Ώ4= T= ct= = = = = 쒂> 4> T> Ót> > > > 6> H? j4? SX? x? ͕? ? /? ? 헂@ 8@ X@ Ox@ G@ @ @ 㟂@ A 58A HXA xA ߨA $A A !A aB 8B XB ;xB 7B B ۯB =B C DC dC DC C ZC ÂC 7łD Ƃ(D &ƂHD ǂhD ǂD ȂD ̂D `͂D VςE dЂ(E ԂHE ]ԂhE ւE *ւE hւE ւE ւF ւ(F mׂHF ׂhF F F F F JقG ڂ,G yۂLG ݂pG QނG Z߂G h߂G ߂G ߂H ߂8H ߂XH xH &H GH hH H I 8I .XI OxI pI I I I J 8J XJ gxJ J J J J EK 8K 3XK kxK K 0K NK K L 8L XL xL L L #L L M 8M XM xM pM cM M M \ N @N `N N DN N uN O $O DO dO l O a O O ` O 8P )$P DP IhP wP P P P Q (Q HQ hhQ - Q Q , Q X"Q /$R I%4R _'XR )|R g*R ,R .R /S }1(S 4HS a8hS :S ;S K;S ;S <T <(T 3AHT AhT CT CT bHT IT IU J(U JHU JhU KU LU LU MU "MV sM(V MHV #NhV pNV 9QV URV RV SW /S(W wVHW VhW =XW KXW kXW XW XX 0Y(X YHX *[hX z[X [X [X [X \Y ](Y ]HY ]hY ]Y ^Y (^Y I^Y j^Z ^(Z ^HZ ^hZ ^Z ^Z ^Z _Z _[ _([ _H[ _h[ `[ `[ `[ Ub[ jc\ d(\ eH\ lh\ m\ 1n\ ]o\ Yp\ v] z(] ~H] ʂh] ] X] ] R] 9^ (^ H^ 2h^ /^ ^ ދ^ ^ U_ (_ HH_ h_ ?_ _ _ E_ ` S,` L` $l` R` ` ` S` g a ,a La la Ka Ńa Sȃa Ƀa '̓ b ̓,b ӃLb ԃlb xԃb ԃb Ճb qփb փ c ׃,c ۃXc ܃xc y܃c ܃c ;݃c qރ d (d BLd xd (d d d e 4e `e e ve e e f ,f 'Lf Mpf f Uf f g ;$g vPg \|g g 0 g N g ] h K@h `h @h h h Th 8i <i !\i "|i #i #i +#i L#i m# j #<j #\j #|j $j H$j $j $ k $ k $@k %`k %k H%k Z%k %k & l *& l U&@l k&`l &l 'l 'l 'l (m +(m 1Hm 3hm `6m H;m @m Am An 1E,n ELn Fln `Fn Ln Rn Zn P[o \4o '^To bxo bo co $co bco cp Pd8p ndXp dxp ep fp gp hp iq Gk8q oXq pxq pq ,{q |q } r <} r n}@r dr r r r ir s $s ِDs ᑄds ms ꓄s $s rs ەt 5$t ΘDt dt t Ԝt t t u $u ʤDu \du u ܩu Ju u ͬv (v ~Hv hv tv &v شv v Xw ˶(w }Hw !hw %w w w w wx Ą(x ȄHx ʄhx ʄx τx aӄx xӄx ӄy ք(y 8Hy Ohy fy y y y ~لz ڄ(z ڄHz (܄hz z z Qz z { H{ x{ { ($| t| X| | } D} p} 8 } h } ~ H8~ Hd~ h~ ~ x~ H P ( ( X 8 & & h'Ȁ H- -8 (.X .x 7ȁ H7 8 @` @  8H H< I` hJ L OP Y ZĄ \ fD 8gd i 8ną xn p Hp4 td u xv x y Xz8 {\ x X h 0 T h hD Ht 8 x 8 @ p 8 X ȼ ޅD x ( ċ ( 0 h` x܌ h@ Hd Ѝ x 8 \ Ȏ 4 X xx ( 8 H ( < H!l " (# # $ )4 )\ 2 3 H5ؑ X6 8$ 89H 9h 9 H: <ܒ = x?( 8DX D XE Eē XF F XG$ J\ J K L xM HR4 W` \ xf 8k o t< xyh h Ė X < h x 8 @ p 8 薆 ؘ( ȚL p ܙ $ ȥH 覆l ؚ H Xt xЛ x͆L φx І І̜ 8ц ҆ ؆L 8نt ن H܆ȝ ( hX x Ȟ H x 8 ԟ 8 0 x ` " % + (. 0D X1l 4 5ġ 6 9 (:H :x (; (AȢ HD H( IT (J L M O (Q0 V\ \ xg Xi k sD ut y Ȁԥ 0 d Ħ ؗ X$ ؚT X Ч H 8D xp ܨ H , 8\ 趇ة h 蹇0 X` 轇 HЪ ć XŇ( xƇt χī Ӈ ԇ ԇ< Hl HȬ x< x ح h h4 d 4 7 8 : <8 G H hIد XK L8 Mh N (P Qܰ S V( xYP Zt X[ (^ ^ܱ _ ` `D cp d Xe f q u< hl (ȳ x Ț < ` X Ĵ h $ xH (p е 諈 Ȯ( h\ X ж xÈ0 (ˈ` h xۈ ܈ 8ވ xވ@ ވ` ( Hĸ D Hd H< d X h 8 ` , T x 8 ļ x 8 , T !t H! ! 0"ܽ o" " #< #\ #| V$ $ %ܾ F% % @&< H'X ( + +ؿ x, - .< h/` 1 3 5 6 X8 x9@ ;p < > B HF, FL Gl HG XM O O P8 8QX Q| R HR R R S HS@ Sh T T (U U 8V V< XWd W 8X X Y XZ$ ZD H[d [ [ \ H\ \ \$ ]D H]d ] ] ^ h^ _ _, `P ap a 8f 8g Hk HoL Hs| Hw H{ ȃ< ȇl ȋ ȏ h 4 XT t H 蒉 8 4 ؓT (t x Ȕ ȕ h< l 蚉 H $ P ȟx ؠ x h, T 8 8 x h D t 8 hՉ H؉ ى8 h ( X < ` ( ( 8 hd X 8D t x x @ Xh X H, \ 0 \ X | 80 \ ( X(8 (X ) (+ h+ /0 /X 1 : : (; h; ;8 ;X (<x h< < < 8= = >@ ?l ? 8@ @ @ (A A0 B` C E F XG G$ GH Ht J K L N( QX Qx R xU ] d4 gd xk l xq z L ( H 8 x L Hx X h 0 \ ȡ X إ h ȰH Xl x ز ӊ Xي8 ڊd ۊ (ފ ފ H @ p H H (h < X Xt H H, T H 8 4 ` h H( H h H H $ D d H 8 4 (d h h! #P $t 2 3 6 H7 7T 8 9 X: ; ;< x<h < (= @ (C 8I< I` J K XL L HM4 M\ HO O P R X( [X (\| x\ \ x] ] (a8 a\ Hg l l m 8n oL px r r s t$ (uD hud v Xv x h 肋4 ` h 8 ȋD h 8 ؏ (< d h ؓ H 4 d ؖ Ȝ 8 ؞0 8` 8 ( H (< h\ X Ȯ H 8t h x X hP Ƌ 8Nj Nj ȋ ɋ hɋ0 (ʋT ʋ| ˋ x̋ ͋ (0 P p ϋ Ћ ы ԋ ԋ8 8ՋX xՋx Ջ ( 8 ؋` x؋ ً hڋ ڋ hۋ@ ܋l ܋ ދ ߋ $ xT h $ XD d ( h H ( H h@ xh h X H 8 ` ( 8 h ( L hx ( h , X\ ( h l X (! !@ !d 8" x" " " x% &H (t x) * + = =8 >d ? ? X@ @ A( HBT Bt C xC HD E FL HGt G H 8I I 8M8 Od hP P (Q Q HS8 Td U hV V W XD Xh X Y hZ [ (\, h\L \l \ (] h] ] ] (^, h^L ^l ^ (_ _ 8a a$ bL bl c xc c c d d4 8eT Hfx f g h j j8 lh m n n hr r8 (s` s s (t ht t Xu8 uX (v hv xw x x$ xyP hz| z X{ { H| |L h}t ~ H X 0 ` Ȉ X @ 苌` ( x ( x x( XP Ht X, hX ( h$! D! l! X! 虌! H! ! 蚌" D" l" " Ȝ" H" " $# (L# 8# ȣ# 8$ ؤ4$ Xd$ $ ($ ($ % 8% d% (% % X% Ȯ& (,& 8\& & & ȳ& ' x(' P' 躌' X' 8' 8' $( (H( Ìx( Ì( 8Č( Č( Ō) ƌ@) Ȍt) ʌ) ˌ) 8̌) ̌ * (ΌH* Όt* Ό* (ό* xό* Ќ + ь$+ hԌT+ + hڌ+ ڌ+ Xی+ ی, ܌<, x܌`, 8, , ތ, hߌ, ߌ - (D- hp- H- (- - H . D. d. . X. . / h$/ T/ t/ H/ / / 0 X40 T0 x0 (0 x0 (0 1 xx1 H1 1 h$2 L2 (p2 h2 (2 H2 2 3 8<3 `3 h3 3 h3 H4 ( <4 h \4 (4 4 4 (,5 \5 85 5 H5 6 6 &P6 36 X46 46 (57 h>H7 >h7 >7 (?7 ?7 ?7 h@8 AD8 Ad8 D8 I8 xK9 i49 jT9 j9 k9 l9 Xm9 hn: xo4: pX: s: Xt: t: t: u; Xu4; uT; v|; |; }; ~< ~,< hP< < < 臍< h= x8= Xh= = = x= > ,> H\> |> X> > ؛ ? h(? 蜍T? ? ؞? ? X @ xL@ جp@ 8@ ح@ X@ A 8A XhA hA A سA B 8<B hB B HB ȷB 8 C x,C h\C C xC xC čD hƍPD ͍D ЍD ӍD ՍE ؍HE ܍xE hE E H F <F (tF HF F F (G h(G HG hG G xG H |H xH H H XI $I DI HhI I I (I hI J 0J 8PJ xpJ J J J hJ K 8K h\K |K K K K H L h (L HL 8 lL L 8L L M x,M hXM xM XM (M M ( N TN xN N !N !N X"O "<O X#`O #O x$O $O h%O % P &DP 'hP 'P H(P *P + Q ,0Q .`Q X/Q /Q 0Q H1Q 1R (28R x2\R 3R 3R (4R 4R 85 S 5LS 6pS 7S 8S 8S x9T :DT =tT >T (?T h?T ?T H@$U ATU B|U BU XCU DU D V EHV EhV FV FV (GV hGV J$W hJLW JlW KW hLW (NW hU X xZPX ]X x^X bX fY g@Y ihY hiY oY oY pY hp Z p<Z q\Z uZ uZ vZ w[ (x4[ zd[ {[ {[ [ \ 8\ XX\ h\ x\ \ \ Ȋ ] @] ؋t] (] 茎] 8] ^ ,^ 莎T^ x^ (^ ^ H_ ȓ0_ 8P_ xp_ _ _ _ H_ (` xL` t` h` ` x` a @a 8pa a 8a a ȟ b b Pb b 袎b xb ȣb H$c xPc ȥtc hc xc بc ȩ$d Pd d d 謎d Hd e 譎8e HXe xe e دe e f Hf سxf f Xf f 8 g 0g `g g 8g Ȼg H h (8h hXh Ŏh Ǝh ǎh 8Ȏi Ȏ0i 8ɎXi Ɏ|i Hʎi ʎi ʎi ˎi hˎ j ̎Lj ͎xj Ύj xώj (юj h֎(k ؎Xk xێk ێk Hݎk Xގl Hl (pl l l l m X0m Tm xxm m m m Xn 4n XXn xn n n n X o Po to Xo o 8o p Dp lp p ( p p H q $q Tq xq q H q r 8r dr hr Hr r s h,Hs ,hs -s -s h/s h0t 7Dt 8pt 9t 8:t :t ;u (>8u h>Xu >xu >u Au XBu Bv (C8v C\v hDv Dv Ev XEv H$w hHDw Hdw Iw XIw Iw (Jw xJ x J,x KLx Kxx xLx Mx N y HP,y Q`y XRy Sy Ty Uz V@z V`z xXz Yz [z \{ \<{ H^h{ ^{ _{ `{ c| (d0| h`| xj| 8k| l| m } n4} td} u} Xv} v} 8w~ w0~ xX~ x~ hz~ |~ x (8 xh X ؆ D p h ț̀ ȡ h, \ ȫ (ā x ȳ $ 8T 赏| ȶ Ԃ x ( hH t 8 hЃ ŏ$ (ƏD Ət Ǐ (ɏԄ xʏ ˏ4 (͏d xΏ Ώ Ϗ HЏ Џ0 hҏ` ԏ x ُ ڏ ڏ4 ۏT ۏ ݏ ޏ܇ , L Hp h @ p X ȉ 8 H x (Ȋ D Xd 8 H @ p 0 ` H " 8#؍ & &( 'H 'p ) +Ў H+ + h-@ .l / H1 1 X8 8< h9d ; < H= = (>4 >\ ? @ (Aܑ A B( CX G HNĒ P P@ Q` Q XR SГ hT 8U xV@ hWd XX X YԔ (Z Z 8[@ [d (\ h] ]ؕ ] H^ xbL cx c hЖ xk 8p0 X}` X ԗ h 8D t ȇ (Ș (L (x ؍̙ H 萐x H ؒȚ ( x ؓ( 8H h x ș0 h` ( x X 0 8X h Н X ء$ 8H xh 裐 Ȟ x8 تh x ( خ (D hd زؠ X L 贐p H xȐġ ʐ xʐ( ̐T ͐| ͐ ΐȢ Xΐ Ӑ (ՐL x Hِ Hڐ8 ڐ\ ڐ| Xݐ ݐĤ ސ X D Xh 8 x̥ H 8 \ h h 8( L t ȧ x h4 T t Ш ( < h` Hԩ 8 x< d ( 8X xx 8ث x D x x Ȭ @ p x H h< h @ ( d x ȯ h @ H ` H "0 H#P #p ($ $ %б x% % 8&0 &T &t X' ' (ܲ x( ( )@ )h * * H, , 804 1d 2 X4 5ش 5 (6( 6P h7| X8 9ܵ X9 9 X;L ;t 8< < 8= = 8>4 >` (? CԷ C E0 H` N P Pи 8Q Q h[D 8c xd d Xf gH Hgh i jĺ Hm ho o< p` ( X xL l X ȇ ȋL Ht 8 ؍Ľ ( T H о X hD d X Hܿ 觑 (0 hP 8| x ȱ H H< h 趑 H X@ ` ظ X 躑 ػ4 \ 輑| ( X@ d (ő Ƒ 8ȑH ȑl ɑ hɑ ɑ ʑ xʑ 8ˑP ˑp (̑ (͑ ͑ XΑ Α< xϑh ϑ hё ё hґ, ӑ\ ԑ x֑ ב Xؑ ؑ< (ّ\ hّ| ّ xڑ ۑ ݑ4 ݑd hޑ 8ߑ ( h x8 h , \ h x D p H 0 (P hp H H @ ` H , HL l 8 8 h 4 H\ | 8 X .L .t 4 X5 Z Z@ \p \ \ ] 8^ x^4 8_` _ _ 8` a ha (c8 ch hd d e e Xf$ hT j Hj j xk (l$ (mL 8nt hq q r hs$ tL Xu| u { X{ H|( |L 8}t } ~ ( h < d ȉ ؏< (` 蔒 8 Ț X< țd 蜒 ؝ Ȣ ȥD (p 0 8T | 豒 $ (X X 8 躒 8 d h H ؿ xD d H $ (ÒD hÒd Ò Ò HĒ Ē Ē (Œ$ hŒD Œd Œ (ƒ hƒ hǒ hȒ ɒH ɒh ʒ ˒ h͒ HΒ8 (Вd xВ Ғ HҒ Ғ Ӓ$ ԒH Ԓh H 8 p X@ x H D | x! # % '@ H+p 8. . x3 x6$ 88P H; < h< H (I$ IL Il J hJ J (K K K, 8LP M| M N XO (P, xPP 8Q Q xS (U U0 VX 8W W W X X ]@ ^p h_ _ _ a c< dh hm m (n xn n o8 XoX ox o (p hp p hq qD (rh r s s t Ht t8 tX 8u| u u 8v v w, XwL wp Xx x (y y y {D {t | h| | } } }< 8~\ ~| ( x ( @ 8` 8 ȃ X( ȄH h h 膓 H( P xt H x$ (L hl H t $ P x Ȗ 蘓( 8H Ț H h$ 螓H hl ؟ x 蠓 X $ D 8d ȧ 8$ L Xt ة x , 8X x ( 8 H ر$ L xt 8 x 8 h\ H 8 8 8 X$ xL œ hǓ ɓ, ˓| ϓ xғ xӓ, ԓ\ Փ (֓ ד ד Hؓ ؓ@ ٓh ٓ (ړ hړ ړ 8ۓ ۓD (ܓl ܓ ܓ Hݓ ݓ ޓ hޓD ޓh ߓ ߓ ( ( hL (p 8 H ( L l h H 0 P ht X < ` ( 8 8X xx H 8 4 $h ' ) ) (* +H ,t 1 1 4 H5 5< 6` 6 (9 9 ; >8 ?d A xE (F F hPL Pl Q 8U W HX X4 XT (Yt Y (Z (\ \ ]D ^t _ ` 8a xa a4 hb\ hc c d e hf0 hh hi k l 8m n8 8sh s Xt u Xu u$ (vD Hxp x y y z z$ {H x{l | | } ~ ~0 T ht 肔 ȃ 8 HD 8l 8 4 X (| ȑ h 8 X Xx h ! H8! ș`! X! ! 8! ! " 8" 8h" " h" (" ء# h<# آd# 8# # # H$ ,$ ت\$ ȫ$ X$ $ Ȯ % H,% T% H% ȴ% H% 8& (4& ع\& غ& h& (& ȼ' ((' ؽ\' X' H' Ŕ' Ɣ( Xǔ<( ǔh( Ȕ( (˔( (Δ( (ϔ) ϔ4) Дd) є) hҔ) Ҕ) Ҕ) 8Ӕ * ӔD* Ԕp* Ԕ* Ԕ* 8Ք* xՔ* Ք+ Ք8+ H֔`+ ֔+ ֔+ ה+ ؔ+ ؔ , XٔL, (ݔ|, ݔ, xޔ, ޔ, Hߔ - ߔ@- h- - - - - . 4. T. . X. . X/ ,/ hT/ / x/ 0 h00 `0 0 x0 0 1 h81 8h1 x1 1 1 2 hX2 H 2 2 2 3 HH3 x3 3 3 H4 ,4 hX4 (4 4 h 4 4 5 L5 5 5 H!5 "6 $<6 -6 - 7 /87 0d7 17 37 x57 (78 9@8 ;8 ;8 xF8 K9 xL@9 8bp9 c9 e9 Hg : h0: iX: xj|: (l: m: p ; 8r4; xs`; Ht; v; ; 8 < ȓD< H|< H< < < <= x\= (= = ؛ > $> (D> ȝp> > X> 裕> ? HD? t? ? X? 8? X(@ hT@ @ @ XÕ@ ĕ A Hŕ@A ͕pA ΕA ϕA ѕA ҕ B Hҕ<B ԕtB ՕB וB ؕC ؕ(C XٕHC ەtC ܕC 8C C D H8D xD D D D (E XXE xE E xE F h<F lF F F (F h$G LG pG XG (G G $H HTH H xH H HH (I LI |I X I I I J x 8J \J J J HJ J (K xHK lK K K HK L ,L HTL |L L L L $M ( TM H"M (&M &M ) N +8N (-`N .N 2N X3N 3O F\O (G|O hHO HO HO 8I P xI,P ILP IlP 8JP xJP JP (MP O,Q hPXQ RQ (SQ TQ UR V(R W\R XR YR xZR [S X\0S ``S aS XcS (eS xf T f@T xghT 8hT hT 8iT HjU j,U kPU HlxU lU mU xmU mV 8n@V nhV nV (rV rV s W XwLW wtW 8xW xW yW zX }HX ~hX ~X X X H Y $Y HY HxY ȄY Y hY H Z HZ tZ hZ HZ 8Z ȋ[ (<[ h\[ 蓖[ 8[ Ȕ[ 8[ \ <\ H\\ |\ X\ \ ؗ\ ] xL] p] x] ț] X] 蟖^ @^ hh^ ا^ 8^ ^ _ X0_ h`_ _ (_ x_ ` 辖(` 8H` ȿl` X` ` x` Ŗa Ȗ,a ɖTa Hʖxa ʖa ̖a ϖa ϖb Ж,b ԖXb (Ֆxb (֖b h֖b Hזb ז c ז<c ؖlc ږc Hږc ږc ږc Hۖd ܖ8d ޖhd ߖd d Hd e <e he He he e f XLf tf (f f f ,g `g g g g % h ?dh Bh Bh Ch Dh j$i pTi ti Xti xui xvi {,j h~\j j j 8j Xk (k (Xk 臗k k k xl (8l (hl l ؖl hl m Hm ȟpm Xm m hn (8n hn (n شn hn $o xTo 8o ėo ȗo H̗p ЗDp ӗtp Hp p xq 8q hq !q "q "q # r #(r %Xr (r X)r *r 0 s 18s 3ls 84s 6s 7s ; t X;<t 8<ht <t 8=t >t XAu HCDu Dpu Eu Gu Iu O,v Q\v Sv (Uv HVv h` w cLw 8exw xew hw sw sx s0x w`x wx (xx hxx xx x y z0y {Xy |y (y hy y z Dz 肘lz ȃz 脘z Hz h({ ؘT{ 螘{ { { 蠘{ (| hH| h| 裘| | X| 覘 } X(} اX} } } ج} 識} h ~ hD~ 8l~ H~ x~ ~ 蹘( hX ػ| h ȿ 8 (X 8Ø| Ø (Ę xĘ Ę HŘ( ƘX xǘ Ș ʘ x̘ (Ϙ@ Xјp Ҙ ҘЂ Ԙ ؘ( x٘L ٘p ژ ژ 8ۘ ܘ ݘ, ݘT Hޘx ޘ ߘ x H x ( h8 \ h| H ؆ 8 HX x ( h؇ H8 X x ( h ؈ ( h8 hh h ܉ T h H (؊ x ( HH t ܋ X X4 0d H1 1 82̌ 2 X3 3D (5p h5 H6 6 7 7, 8X 8| 9 :̎ : ;( h=X H> > >ď A B C@ XDd E 8F Fܐ x[ a@ bd e f fؑ h h( kX l 8n n̒ 8o o 8p8 Xq` r 8s sГ 8t t uD vl w x hxܔ } ~8 h ĕ ( 脙 (@ p ؗ ̖ ( , L Hl ؞ H H0 x` ص ę ș Hș8 Ιh ϙ Й hЙؙ ҙ ՙ8 ֙` ؙ hڙ ܙ ݙ ߙD ߙd ( hD p Ȝ ( X X (@ h` ( (8 d H X h L x 4 hd x ԡ 8 4 x T # $آ $ ', X4\ 85 5 9 X; <@ >l @ BȤ C D FP H Q R XR U0 8Z` ` ha Hb c d8 xh xħ X HP p 螚̨ ȟ 8 أL | (ԩ ( T 8 H < (l Úȫ Ě ƚ ƚH ǚp ǚ (Ț Ț ɚ ɚ4 HʚX ʚ| x˚ ̚ԭ h̚ ̚ x͚L 8Ϛt К ҚȮ ؚ Xٚ ٚ@ ښh ۚ ܚ hݚ ޚ hߚ8 Hd X ( < l H 8 84 d h x̲ 8 h ( h L t ȴ h L l 8 hD xp Ķ X( X ( X ( D hOt P 8Rи [ 8\$ x\D \d ] h] ]Ĺ a (b$ hbD bd c 8f f g k8 md (n n Ho 8q$ xrP s| t uԼ v x0 X~` H X Ȓ H Hx x ľ L | 8 ؿ أ 88 d h 8 H خ@ xt h 88 l 8 Ǜ ћX 8 h ( 8P h XL t H 8L x t H x% h, CT Dx D E hF H IL Kx (M hT T V h[P X]t H_ x` (a Hd d8 Xe\ f g Hi j (k0 8lT 8m| m m Xn n 8o4 o` p p q r hv4 vT wx w xx x z X{4 h|d } x} } X~ ~ ȀD p X x 8 80 ` ȉ 8 @ xh ( ؔ x ( 8L l ( Ȝ0 P x 8 蟜 D Xl ( ز h, P (Ĝx hĜ Ĝ (Ŝ xǜ Ȝ8 Ȝ` (ɜ Hʜ hϜ М ќ4 ҜX xӜ Ԝ Ԝ ՜ ֜$ לH 8l ٜ ڜ ݜ Hޜ$ T H h 0 h\ h H 4 HT x h 8D h ( 8 , L xp X ( ( x( L t H 8@ d X 8 X Xx X 8 X Xx zR x $ | FJ w ?;*3$" D }x \ ɛ}L EC C | }+ EC " }g EC ^ G}D EC { k}+ EC b v} EC } EC < } EC \ }4 EC k | ˟} EC j}_ AC Z }@ AC ; ɡ}W AC R } AC H }% EC \ @ ¤}> EC u ` }; EC r } EC L }% EC \ }> EC u }; EC r .} EC L #}% EC \ @ (}> EC u ` F}; EC r a} EC L V}% EC \ [}> EC u y}; EC r } EC L }% EC \ @ }> EC u ` }; EC r ǥ} EC L }% EC \ }> EC u ߥ}; EC r } EC L } EC @ }| EC s ` K} EC }D EC { ا}p EC Eb $} EC } EC M }3 EC E% ( } EC H g} EC h } EC }. EC e }. EC e } EC } EC :} EC ( ݮ} EC H ~}. EC e h }. EC e } EC /} EC Ұ}w EC n )} EC } EC ( ^}H EC H }B EC y h }B EC y ʳ}1 EC h ۳}) EC ` }n EC e 2} EC V 1}n EC e ( } EC V H ~}P EC G h }o EC f }A EC 8 } EC } EC 1} EC }A EC x ( }i EC ` L [}6 EC m l q} EC 7}3 EC j J} AC } AC R }# AC ^ } AC U , } AC L }G AC B l о} AC } AC Z } AC I }} EC S y}e EC \ }2 EC i , п} EC L k}9 EC p l }> EC u } EC '}Z EC Q a}) EC ` j}2 EC i |} EC V , {}7 EC E) P }] EC T p } EC ~ 2} EC L '}J EC A Q}, EC c ]}> EC u {}V EC M 0 } EC M P } EC p !}, EC c -} EC E }> EC u }r EC i -}K EC B X} EC E 8 :} EC E \ } EC E {} AC ,} AC R #}# AC ^ &} AC U } AC }G AC B @ } AC ` } AC Z }` EC W }t EC k T}/ EC f c}- EC d p} EC } EC P @ } EC ` }) EC ` }6 EC m }# EC Z }( EC _ }" AC ] }H AC C }S AC N @ 4} AC M ` &} AC M } EC E }C EC z } EC V } EC }S EC J $ }H EC D } EC d }? EC E1 } EC }J EC A 3}5 EC l H}= EC t e}9 EC p ( ~}/ EC & H } EC E l w} EC } EC } EC j} EC \} EC }} EC t , U}p EC g L }0 EC g l } EC 9}e EC \ ~}0 EC g }e EC \ }f EC ] } EC P , } EC P L } EC M l } EC }U EC L }U EC L }" AC ] }A AC | 0}. AC i , >} AC L }) AC d l }' AC b }O AC J =} AC V 8} AC R /}# AC ^ 2} AC T , +}H AC C L S}S AC N l }K EC B } EC x }| EC s n}k EC b }4 EC k }3 EC j , }V EC M L } EC z l y}w EC n }X EC O } EC s} EC }T EC K }R EC I , B}R EC I L t}* EC a l ~} EC }< EC s 8} EC }q EC h } EC } EC z , }I EC @ L ;}7 EC n l R}* EC a \} EC } EC E s} EC }2 EC i }> EC u 0 -}) EC P 6} EC p }X EC O }S EC J >}y EC p } EC } EC }F EC } 0 }l EC c P 4}D EC { p X}u EC l }S EC J } AC } AC [} AC } AC R 0 }# AC ^ P } AC U p } AC }G AC B } AC ~ AC Z ~X AC AR ~j EC a 4 ~' EC ^ T %~ EC E x ~ EC ?~# EC Z B~{ EC r ~) AC d ~! EC X ~X EC O 8 ~r EC i X 1~o EC f x ~ EC ~9 EC p 2~= EC t O~ EC .~ EC ! ~' EC ^ 8! ~ EC V X! ~~ EC u x! ~# EC Z ! ~- EC d ! ~ EC ! ~G EC ~ ! ~ EC V " ~ EC 8" q~0 EC g X" ~ EC ~ x" ~0 EC g " ~~ ATb AA " l~ AAG P " ~ BBA A(G L"P (D ABBN ^ (A ABBD 0# <~+ D# X~ H c E W E < h# ~ EAD } DAD F DAE bDA # $~# # @~F Y_ H D 8 # l~ FBA A(D@ (A ABBA 8 $ ~ FBA A(D0 (F ABBH X$ ~ K' F x$ 4 ~ H $ @ ~) BEB B(A0A8Dp 8A0A(B BBBA $ $ ~~ ATb AA $ ~ AAG < % !~ FEE E(A0 (A BBBA L X% !~ BBB B(A0A8J 8A0A(B BBBF ( % 4#~_ FDA PAB \ % h#~ FBB B(A0A8D@ 8I0I(B BBBL v8A0A(B BBBH 4& $~ FBB B(A0D8D` 8A0A(B BBBD H & l%~ FBE L(D0A8DP 8G0A(B BBBL d & &~ FBB E(D0D8DP 8F0A(B BBBH 8A0A(B BBBF H 4' h(~m FBA A(D0~ (F ABBI D(C ABB ' (~J H} ' (~ K A ' X)~T LC ' )~ ' )~ ( ' )~ EAD0 AAF $( h+~ 8( d+~L Hh H S L X( +~ FBE D(A0x (A BBBG { (A EBIL ` ( $,~ BBA A(G0\ (A ABBA (C HGNJ j (J FBBJ ) .~~ ATb AA 0) /~ AAG H L) /~( BBB E(A0A8Dp 8D0A(B BBBF ) 3~i L ) 3~Q BBE B(A0D8Ja 8D0A(B BBBH ) ?~" EAD * @~ FAD JH <* @~ FBB B(D0A8GPX 8F0A(B BBBA \ * dB~P FBB B(D0A8KZ 8C0A(B BBBF O GOA * TT~ * `T~7 P + T~ UEE D(E0n (A BBBC p(A BBBA d d+ T~ REE E(D0A8G@| 8A0A(B BBBE J8A0A(B BBBA + @U~ A]] AA + U~ AAG D , @V~ FBB A(C0G 0A(A BBBJ ( T, [~ EAG AAF ( , \~ EAG CAF , ]~! EM F D , ]~{ H`m A , ]~~ ATb AA - P^~ AAG 8 (- ^~ BID A(Q0n (A ABBA d- X_~X E{ A F A ( - _~ EAG IAE - H`~. AC i - V`~. AC i - d`~_ AC Z . `~@ AC ; 4. a~W AC R T. a~ AC t. b~< EC s . b~? EC v . b~0 EC g . c~ EC . d~ AC I / d~ AC I 4/ d~ AC [ T/ d~> AC y t/ d~ AC / e~ AC / mf~ AC R / df~ AC L / Uf~ AC R 0 Lf~ AC [ 40 Lf~! AC \ T0 Mf~! AC \ t0 Nf~! AC \ 0 Of~! AC \ 0 Pf~! AC \ 0 Qf~! AC \ 0 Rf~! AC \ 1 Sf~I AC D 41 |f~! AC \ T1 }f~! AC \ t1 ~f~! AC \ 1 f~! AC \ 1 f~! AC \ 1 f~! AC \ 1 f~! AC \ 2 f~= AC x 42 f~e AC E[ X2 f~ AC U x2 f~ AC O 2 f~ AC M 2 f~ AC M 2 f~ AC M 2 f~4 AC o 3 f~ AC M 83 f~a AC \ X3 f~] AC X x3 )g~ AC M 3 g~ AC M 3 g~ AC M 3 f~ AC M 3 f~i AC d 4 :g~y AC t 84 g~u AC p X4 g~ AC X x4 g~" AC ] 4 g~8 AC s 4 g~ AC 4 h~" AC ] 4 h~! AC \ 5 h~ AC Y 85 h~W AC EM \5 h~+ AC f |5 h~ AC Q 5 h~1 AC l 5 h~ AC 5 1i~- AC h 5 >i~M AC H 6 ki~1 AC l <6 |i~ EC \6 {j~! EC X |6 |j~ EC 6 hk~ EC 6 l~ AC I 6 l~ EC I 6 l~ EC F 7 l~ EC F <7 l~ EC H \7 l~ EC |7 m~ EC 7 m~ EC x 7 n~ EC Q 7 n~@ EC w 7 /n~ EC 8 $p~o EC f <8 ss~l EC c \8 s~ EC | |8 $t~ EC 8 v~ EC R 8 v~y EC p 8 (w~ EC 8 x~ EC 9 ~ EC <9 ~ EC \9 ~ EC |9 ˇ~] EC T 9 ~ EC 9 ~| EC s 9 3~W EC N 9 j~ EC : +~ EC <: ȏ~% EC \ \: ͏~y EC p |: &~& EC : ,~. EC e : :~@ EC w : Z~ EC : ~ EC ; |~a EC X <; ~ EC \; ~y EC p |; ~ EC ; Ε~ EC ; ~ EC ; ~ EC w ; ~ EC < ~ EC << q~O EC F \< ~ EC |< [~} EC t < ~ EC { < ~ EC < ݢ~ EC < ~h EC _ = إ~ EC <= ~ EC \= ~ EC | |= r~ EC = _~( EC _ = g~w EC n = ~ EC = _~o EC f > ~ EC <> N~Q EC H \> ~ EC |> ~5 EC l > ~[ EC R > S~I EC @ > |~ EC Hn ? ~) EC ? ~| EC s @? <~ EC `? ~_ EC V ? 4~/ EC f ? C~ EC ? <~" EC E ? :~H EC @ b~ EC P $@ [~m EC d D@ ~4 EC k d@ ~- EC E @ ~ EC @ `~\ EC S @ ~ EC U @ ~S EC J A ~ EC (A v~ EC HA m~ EC hA ~ EC A K~ EC { A ~ EC A %~ EC G A ~ EC G $ B <~ EC I 8B ~d EC [ XB ~= EC t xB <~2 EC i B N~ EC B A~{ EC r B ~ EC B ~Y EC P C ~~ EC u 8C ~ EC XC ~ EC xC ~ EC C ~ EC C f~u EC l C ~3 EC * C ~ EC D 8 , EC c 8D D EC XD H EC xD ! EC X D z EC q D : EC D 6 H EC D ^ 9 EC 0 E w x EC o 8E EC XE k{ EC r xE EC P E H EC E I EC @ E EC P E R EC I F ; EC L 8F 0A EC x XF Ql EC c xF H EC ? F V EC M F c EC Z F > EC F EC G EC 8G !> EC u XG :! EC xG ' EC G ) EC G i+ EC G + EC G \,{ EC Jh H 2d EC [ <H 2_ EC V \H 637 EC n |H M3 EC E H C5 EC H ?9O EC F H n;8 EC o I ;> EC u I ; EC M @I ;! EC X `I ; EC I 2<s EC j I < EC H I >7 EC . I D EC J D EC $J .E EC v DJ I EC dJ La EC X J SNV EC M J NR EC I J NT EC K J OE EC < K QP EC G $K DT EC DK T EC dK DU EC ~ K U EC K $V EC K Y EC K '\ EC L ]5 EC , $L b EC DL f EC Hw hL n EC L fp EC { L p EC L q EC L ys EC M v}W EC N (M }3 EC * HM ~ EC hM c EC M Ӂ EC ~ M : EC M " EC M EC N D EC ; (N EC HN S EC J hN # EC Z N EC N o EC N EC N O EC O Ē EC | (O )( EC _ HO 1 EC hO } EC Gm O y0 EC ' O EC O y EC O EC P Ơ EC ,P 7@ EC 7 LP W( EC _ lP _* EC ! P ir EC i P EC P O EC P EC H Q EC E 4Q u EC l TQ m EC P tQ f EC P Q _4 EC k Q s$ EC Q w EC { Q ۲ EC R 1 EC ( 4R ~ EC u TR k EC b tR I EC R EC R ) EC ` R # EC Z R ' EC ^ S < EC s 4S 0? EC v TS O EC tS ǻG EC > S \ EC S S *\ EC S S f EC V S e EC L T Z EC M 4T P EC M TT FF EC } tT l EC M T b EC V T a EC M T W EC M T M EC U C EC z 4U EC O TU | EC s tU o EC O U gF EC } U EC O U F EC } U EC L V C EC z 4V þ) EC ` TV ̾{ EC r tV 'W EC N V ^ EC E V % EC V EC V l EC E^ W & EC <W 0 EC g \W 0 EC g |W 0 EC g W 0 EC g W EC W EC W EC X EC <X <f AC a \X EC |X EC X EC X R EC X EC X F EC } Y y EC p <Y >B EC y \Y ` EC L |Y U@ EC w Y u EC L Y j@ EC w Y EC P Y F EC } Z EC L <Z @ EC w \Z EC L |Z @ EC w Z EC L Z EC Z W EC N Z # EC Z [ # EC Z <[ EC \[ EC |[ EC Q [ EC L [ @ EC w [ EC [ ( EC \ F EC } <\ y EC p \\ G EC |\ 1 EC h \ , EC \ n EC e \ Xn EC e \ f EC ] ] n EC e <] :f EC ] \] e EC EW ] EC } ] ' EC N ] EC ] EC L ^ EC M ^ ' EC ^ @^ EC `^ s4 EC k ^ 0 EC ' ^ EC ^ EC ^ ? EC v _ EC _ x+ EC b @_ EC `_ / EC f _ / EC f _ / EC f _ / EC f _ . EC ` EC z ` L EC C @` ;# EC Z `` ># EC Z ` A# EC Z ` D# EC Z ` G# EC Z ` J EC E a EC G~ (a `X EC EJ La EC H pa " EC w a EC H a sK EC B a [ EC R a EC b _ EC 0b F EC Pb !/ EC f pb 0 EC b > EC 5 b " EC Y b + EC " b EC c EC 0c \ EC S Pc EC pc EC c /# EC c 2 EC c AC G~ c +T AC EJ d [ EC H <d 7 EC . \d S EC J |d 3 EC H d $ EC d EC d EC d (^ EC U e + EC <e , EC \e /S EC J |e 0 EC e 1 EC e -3 EC x e 53 EC j e 5A EC 8 f 6 EC v <f !9. EC e \f /9u EC l |f : EC f R=# EC Z f U=) EC ` f ^=# EC Z f a=< EC s g }=< EC s <g = EC \g 5?0 EC g |g E?0 EC g g U?0 EC g g e?0 EC g g u? EC g B EC h D EC <h vF EC \h rIA EC x |h Iq EC h h L EC h M| EC s h N EC h O, EC # i P EC <i R EC \i IS EC |i T EC i V EC i YXV EC M i Y( EC i a3 EC * j bn EC e <j b EC L \j b EC |j c EC N j ce EC \ j c EC ~ j @dq EC h j d EC k e EC <k ~fM EC D \k h EC |k :j EC k l EC k l EC k m} EC t k n EC E l qX EC O @l q EC `l vr EC x l t EC l ut EC k l uu AC p l >v8 AC s m Vv AC m v" AC ] @m v! AC \ `m v1 AC l m v AC m Vw AC I m Dw/ AC j m Sw5 AC p n hwN EC E n w EC { @n x9 EC p `n y EC n yo EC f n | EC n x} EC n ? EC o EC o EC @o EC `o A EC o EC o EC o S EC o EC p EC p NM EC D @p {T EC K `p T EC K p ㎀R EC I p g EC ^ p \+ EC b p g# EC Z q jU EC L q EC @q b EC Y `q b1 EC ( q s+ EC b q ~, EC c q EC q 8 EC r > EC 5 r ҥ EC @r N EC `r ꨀM EC D r EC r EC r + EC b r + EC b s Ů+ EC b s Ю+ EC b @s ۮ EC `s ԯ EC W s ԯ EC s Ͱ EC W s Ͱ EC s Ʊ EC W t Ʊ EC t EC W @t EC `t . EC e t . EC e t . EC e t . EC e t V EC M u EC u h EC @u Vd EC [ `u EC u + EC " u ! EC u AC M u AC R v C EC z v &? EC v @v E EC S `v AZ EC Q v { AC N v nP EC G v W EC EI v ѾV EC M w AC O $w AC I Dw 鿀 AC I dw AC I w ſ AC [ w ſ> AC y w 㿀 AC R w ڿ AC L x ˿ AC R $x ¿! AC \ Dx ÿ! AC \ dx Ŀ! AC \ x ſ; AC v x ࿀! AC \ x ῀! AC \ x ⿀! AC \ y 㿀! AC \ $y 俀I AC D Dy ! AC \ dy ! AC \ y ! AC \ y = AC x y - AC M y AC M z AC M $z AC M Dz ] AC X dz 2 AC M z $ AC M z AC M z AC M z y AC t { S" AC ] ${ U8 AC s D{ m AC d{ " AC ] { AC Y { W AC EM { #< AC w { ? AC I | -Y EC P (| f EC v H| I EC @ h| F EC } | À EC | À? EC E1 | ŀ EC | lƀ* EC ! } vǀP EC G ,} ǀ EC G{ P} ˀn EC e p} [̀o EC f } ̀c EC Z } ̀< EC 3 } рw EC n } `р EC W ~ `р EC M 0~ Vрu EC l P~ рO EC F p~ р# EC ~ ҀK EC B ~ ӀK EC B ~ 3ӀB EC y ~ UӀ EC F DӀ6 EC m 0 ZӀ{ EC r P Ӏ> EC u p Ӏ8 EC o Ӏ EC Հ} EC t ׀ EC EC /ـ EC 0 ـ3 EC j P ـ1 EC h p ڀ# EC Z ڀ EC ڀ EC Ѐ `܀ EC S \܀& EC ] b܀ EC 0 +ހ3 EC j P >ހ6 EC m p Tހ9 EC 0 m EC M3 EC j Ё `6 EC m v EC U+ EC b 0 `1 EC h P q EC p 3 EC j 6 EC m EC Ђ 3 EC j EC L EC S 0 9 EC p P EC E t EC V EC & EC ] ԃ EC Ze EC \ EC W 4 b EC Y T EC t EC EC M EC D Ԅ a EC GQ EC & EC 8 M EC D X m EC d x U EC L RZ EC Q " EC % EC \ EC w0 EC g 8 EC X m EC x 41 EC h E1 EC h V/ EC f ؆ eb EC GR EC 7 EC n < EC E ` e; EC r { EC r EC O EC F 0 EC g 0 EC g 0 EC g @ O EC F ` EC EC M{ EC r F EC = EC J EC A # EC @ EC ` EC w EC w c EC w o EC Ea p EC g ^= EC 4 $ {& EC ] D EC d * EC a A EC x & EC Ċ q EC h c EC EC M $ EC N D ! EC X d m EC d , EC # EC ċ U EC L g EC ^ b U EC L $ F EC } D T EC K d / EC f EC t EC Č q EC h K > AC y i EC $ EC D R! EC d ! EC P" EC "_ EC EQ ȍ # EC }# EC $ EC ( $ EC H & EC G l u*b EC Y *& AC a *[ AC V ̎ * EC +* AC e + EC , +b EC ET P ;- EC E t 1 EC W36 EC G& i5b EC Y ؏ 5 EC G j<~ EC u < EC < =N EC E \ > EC | ? EC :Bh EC _ BJ EC A ܐ C EC BFp EC g Fx EC o < Gc EC Z \ -J EC | K EC N EC yOG EC H6 R EC M RL EC C RI EC @ @ R" AC ] ` R! AC \ R\ EC S &T EC T8 AC s T AC SU" AC ] UU AC M @ GU AC X ` DU AC X AU AC W =U AC X :U AC M ,U" AC ] .U AC E $ UN AC I D !V, AC g d -VF EC = SW EC S OWa EC X Ĕ W] EC T W EC lZ EC $ D[ EC D [ EC d \ EC I^ EC ^. EC e ĕ ^ EC _| EC s ` EC $ a8 EC / D f_ EC V d ?gE EC | dg EC gp EC g Ė !h@ EC 7 Ai( EC _ Ii( EC _ $ Qi EC D i EC d j EC H @l EC lb EC Y ȗ 9nG EC H6 \s" EC H ZwN EC E 0 wP EC H? T { EC t C}g EC ^ } EC H EC ? Ԙ ' EC ԁ" AC ] ց EC 4 EC T < EC t EC ɇ EC p EC ԙ F EC 4 EC Ύ? EC v 4 펁 EC T AC I t z> AC y < AC w - EC d Ԛ . EC e ϐn EC e Y EC P 4 V EC T = EC t t EC M EC M W EC N ԛ :b EC ET x EC % EC E < EC E ` EC E AC I AC [ Ĝ > AC y AC R AC L $ AC R D ! AC \ d ! AC \ ! AC \ ; AC v ĝ ! AC \ ! AC \ I AC D $ Η! AC \ D ϗ! AC \ d З AC U ʗ AC M AC M Ğ AC M 4 AC o AC M $ a AC \ D 痁] AC X d $ AC M AC M AC M ğ K AC F %y AC t ~u AC p $ Ә8 AC s D 똁 AC d n" AC ] p AC Y n< EC s Ġ " EC Y 2 EC i ) EC ` $ EC D j EC d EC 霁z EC q C EC ġ EC Ҟ EC ʠ EC $ EC D l EC c d Х EC EC J EC H9 Ȣ Ů EC G 4 EC EC , ?I EC @ L hT EC EF p Y EC P ѵ EC EC v У 跁 EC p EC ? EC 0 3 EC P ແ EC p EC y } EC t t EC Ф ,ā EC ā EC ŁI EC E; 4 ǁ. EC e T ǁ. EC e t ǁ= EC t ȁ- EC d ȁ EC w ԥ ȁH EC ȁ EC Ɂ EC 4 Ɂ EC E X ʁ EC x ˁX EC O Xˁ, EC E `Ё EC E ҁ EC Ӂ EC E $ ԁ EC E H ց[ EC EM l ׁ EC Uف EC G ہ? EC G/ ԧ ܁ EC | Mށo EC f u EC l 4 9 EC 0 T y AC t t c8 AC s { AC " AC ] Ԩ EC } EC } EC 4 g* EC ! T q AC Y t oC EC : EC EC ԩ EC f EC L [H EC 4 EC T F EC t : EC q # EC Q EC L Ԫ Q EC H C# EC Z F EC 4 M EC D T EC t EC | EC s / EC f ԫ / EC f H EC ? '^ EC U 4 eh EC _ T AC I t AC [ > AC y K AC F Ԭ < EC s ^ EC U > EC 4 P EC G T EC M t EC L L EC C EC ԭ EC w AC R n AC L 4 _ AC R T V! AC \ t W! AC \ X! AC \ Y! AC \ Ԯ Z! AC \ [! AC \ \ AC M 4 N AC M T @ AC M t 2 AC M $ AC M y AC t ԯ o AC X l" AC ] n8 AC s 4 AC T " AC ] t 1 AC l i EC ` e EC ZA EC 8 {3 EC * @ EC 7 4 EC T o2 EC i t , EC # EC i EC Ա EC EC q! EC 4 Z%E EC Ew T %I EC @ t %Q EC H & EC b' EC Բ ))w EC n ) EC r*p EC g 4 * EC T ,j EC a t ,E EC | - EC /` EC W Գ E0^ EC U 0 EC 0 EC 4 1F EC G6 X : EC x B> EC @ EC QBc EC Z ش B EC Em EC d lEd EC [ 8 F. EC e X F1 EC h x F> EC u F EC _M EC ص SQ EC LRm EC d T EC 8 2] EC X ] EC x HdW EC N fJ EC A g EC ض k EC k EC 6qy AC t 8 qu AC p X q% EC \ x q EC r EC }sQ EC H ط sA EC x ( s EC M $ w EC D x_ EC V d xn EC e 'yT EC K $ [y6 EC I$ $ ̸ iz EC K {/ EC G ( | EC M $ D ]~K EC K7 l EC G ( 4 EC M EC T ܹ EC G ( w EC P , K EC L EC l Ά EC G [ EC R EC E Ժ ~Q EC GA H EC ӊ& EC H $ < Ռd EC NM d EC ( ~ EC Mh 瓂 EC л EC ( ; EC M% ( EC M ( H ؚA EC P( t EC G $ \ EC K R EC F ( A EC M EC , z^ EC GN P ` EC W p G EC ~ m EC d ( h EC P ( ܽ EC P EC ( W1 EC ( H h AC R h _ AC L P AC R G! AC \ Ⱦ H! AC \ I! AC \ J; AC v ( e! AC \ H f! AC \ h g= AC x e AC E[ Ź AC U ̿ AC R AC M AC M , AC M L 4 AC o l AC M a AC \ ӹ] AC X AC M + AC f AC Q , t EC Ef P S EC p 꺂 EC V 麂- EC d $ EC [ EC G EC } VĂ EC 4 Ƃ EC T Ȃ EC t ͂ EC P҂ EC ӂ EC ӂ3 EC G# ւ EC w ]ׂ[ EC R 8 ׂT EC K X ׂO EC F x ݂L EC G< # EC J EC 4 EC I EC @ EC G D h AC I d V AC I D AC [ D> AC y by AC t u AC p AC Y $ K AC F D 9 EC d 4A EC x U EC . EC % A EC x 0 EC ' c EC Z $ Ja EC X D x EC o d EC H h EC E O EC F " EC Y 2 EC i & 4 EC E& 0 6 EC P EC p EC EC } EC w AC I e H EC EC 0 u EC P } EC t p > : EC q X N EC E i EC ` !Z EC Q # EC $9 EC p 0 $ EC P %C EC : p (( EC ) EC * EC +, EC c + EC ~/ EC 0 /? EC v P 0A EC 8 p 04n EC H] z6u AC p 6 AC I 6, EC c 6 EC | .8| EC s 4 <z EC q T < EC t v= EC > EC > EC H?s EC j ? EC -@ EC 4 @ EC T A EC t UC EC E EC I EC gJ? EC 6 L EC dP EC 4 Rs EC j T mR EC t UV\ EC S Z AC R Z AC L yZ[ EC R ]T EC K ^ AC R 4 ^ AC R T ^; AC v t ^ AC U ^ AC M ^ EC n_ EC | _ EC [`} EC t 4 a EC H X i EC x MjP EC EB yk EC $ n AC G E , n+ AC HH A , o EJ HH D $ D tr EC G] A l `|: AJ ~|( AO ( (t EC P A ^|+ , t} EO PS A 9|+ , @ ,v EQ P A p | , ~ AC Y K $ EC I B $ EC I A ( EX L H , < EQ DIQp D l | $ p* ET I B $ x2 ET I H $ ET I D ( ET I G ( 0 ܔ EF FM H , \ Е! EC FHJ E , Ж EC HG A , EF DI A , 4 AF FIH L , 0, AF M F L 0n EC ` A p |t EC f A ؞ EE Ek A ( 4. EC G F | , & EF HH* K 4 ܽ|9 T 8 EC j A t EC G , EF FM F |9 (8 EC j A H EC G $ Ȭ EC G , D h EF FM I t |_ 88 EC j A $ X EC G C , . EF FM D ռ|m , EE Ek A ( P > EC BN H | Ҽ|2 , f EF FM D |9 ŃB EH o A DŃ EE Ek A , , Ń[ AC M E \ ]|9 , | ƃD EC MF E F| , ȃ EC M A | , `˃ EF FM I L ̻| l ԃ EE Ek A , LՃv EC IN A , ׃X EF FM) I | : EC j C , 0 S AG P5 A , ` EC HH A l3 EC c C , t EC HHK A : AC p A , Q EC HH A $ 0 < EC I A $ X EC _ A , AC Y G $ AC X A ( t AC W A AC A , ( ] AN BV A ( X EC BMD A $ X5 AC I F , p EC h I P> EC n C pc EC EP A , M EH M- A P |, , p EF HHz K |B , f EF FIU G Ӹ|n , EC FIU A ( @ AQ M C l 8 EC h C 8 EC h C 8 EC h C 8 EC h C 8 EC h C , @ AC FFc E < EC Y G ` EC Y G ( x AC M J , l i EC P A , 1! AX P A 0 lS EJ FLM A D HVS EC E@ A $ h V EJ C K 8 ,W. AC FD J J y O , Y AG FMr C , ]u AC DEED A , , _ EV BIHV A $ \ pm AC S A n EV E A 0 n- AC \_ A y E , p AE FM\ K u EC Eb A 0 u EC | A P \v EC D $ t w EC I P H w EC y A x EC G |z_ EC t A { EC N A ( | EC N A L p} EC N A p L~ EC D EC N A Ԃ EC N A EC N A EC N A $ h EC y A D EC y A $ d EC I P H $ p EC G A X EC E A , čM EC DEK H , 䎄 AC \ E $ 8 ԐC AC I G ` AW Ak A $ h| EC MZ A AC Es D , |{ EC M K $ ̗ EC GO B , ( EC MK H X 4# EC E H $ | @K EC M P H h EC EZ I $ T EC G I ܥ( EC En E 覄A EC s A 4 A EC s A $ T Hh EC u S P C ( | EC K F $ $ EC I P H [ EC E H , H EC h3 E ( $ ذ EJ Es I I A P L} EJ q A p } EJ q A } EJ q A l} EJ q A ̲} EJ q A 4 , EC M E A ( ( EX DIIf G , T H EC BEIJ A , EC BEIJ A AC u G ( h EC K F ( e EC I D ( , P EC K H ( X DDŽ EC K B ( Є EC K H ( LՄ EC K H ( ل EC K H ( tބ EC K H , 4 EC M B ( d F EC K F ( F EC K F O EC h H $ <4 EC I E ( T EC P H @ F ( 4 8h EC j N D F ( ` |h EC j N D F , EC I K i G $ EC v J P H $ EC v J P H , EC G A ^ J < EC E E $ ` EC I A D EC E G EC E G EC E G EC E G t EC E G < @ EC E G ` EC E G EC E G EC EF E EC EF E | EC EU F x EC EU F 8 t EC C \ EC E G EC E G $ AC S A ( AJ I A 9| ( h EC P C , @ N EC HO H ( p AE DJM G , EC DS E ( # AC \N B J|* ( $1I EC gb G D H3O EC A A , h t3 EC DEEDJ D 4W EC m K , D4e EC DL F , 5 EH FJL G $ T; EC GO B $ @ ; EC BHa E ( h T<H EC f A , x> EC h A , B EH DV B , FV AO I! F $ J7 EC c G D (J: EC c J , d HJ EV PD A , 8P ET IE I | , Zp EC DIM F , 8_ AC DEEHX F ( D (`3 EL BS D , p <bO EH M B ( \l EH I H , 0rE EC HH J , P} EC M[ H $ , EC G I , T x EC Y E , 脅 AC h B ( EC f_ C , EC e K $ j EC CY A , 8 䏅_ EG BNV F $ h EC Gw J ( ̓k EC Az E Y E , AP M. D $ X EC n J P C , ؗ EC DL^ J ^ J D h= EC k E , d EC U G , X EC FJ A , H AC HHd A ( 褅 EC M A , EJ HD A , P EC \ E ( ' EC I B ( EQ M A AC E G ( AC K A ( ( EC P H ( T ] EC P H ( EC P G 0 pą AH BIIIK^ A , Ņr EJ FJ G , L΅D EJ FJ G , @ lЅ EJ FJ G , p <ԅ EC FJq G , څ EJ FJr G ( EC P F 0 P AH BIIIH E , 0 , AC FEF D , ` AC FEF D , 1 Es PILD A , q EJ DIIN8 A , ,q EM DIIN5 A , | E] DIIGd A P Ed Is K $ t EC u C G E $ A AK BU A HO AC E| E $ t EC u C G E ( 1 EH S E < 8 EC j A \ 6 EC h A ( | @ EH _ A $3 EC c C , D AC DIQ! A , 2 AC P D 4 ( EH MQ@ E E ` 6 EC c F < AJ H E ( y EC M J ( \ EC M J , k EC DEM G , ; EC m A L E EC w A , l @W ES P A , p AJ W' A $ W EC l D P J ( ( EV K H ]| , @ EX M, J p |) , <# EC Ps E '6 EC h A $ ' AE G A , (k EL FT B , 8 86 AC M A ( h 9 EH DT I x=3 EC e A = AC ^ A , > AC i H 4T EC n J , | , D U AC DEH K , t _l AC \ A , (g^ EC DHK D ( Xh EC X A , ,j AG BIEJ H ( 0 k EO DQV A ( \ 0 EO BQD E $ EV Gx F $ 쉆 EC I D ( 䋆 EC I) F , EC \V F 4 |K ( T AC BM A ܘ EJ E A , EC MN E , H? AC DH B , X EO BO F \ A $ 4 H EC G J $ \ @M EC G G h EC E F EC E J $ 7 EC I D $ ؤd EC G[ F 4 EC k A @ < EC u A ` EH B h EO ] A E[ H A ES m A EC D A ( # EC L7 E $ < EG G D d EC H A EC E A , 0 EC P] K ( AC K D , EC P H , 8 AC FFP A ( h t EH FH D XP EO q F $ H OH BD F ( : AC P K EC E A , P@ EC i J L pZ EO $ h EO Cw B , LJ EC DS% A , l EH KS G c EC S C $ ( EC IR E , < Q AC FFk E , l EZ P F ( @ AM DDy A ( AC Z E 0 EJ BIIIR E $ ( EC U A P | , l AC BIK F , AC Y G , AC Y A , @ AC Yk H , , 8 AC \5 K , \ EC BEIM E , #k EC DHL A , $A EC DEG D &6 EC c F 0&6 EC c F , , P&m AG FEK E 0 \ ) EM BLLIH| G |16 EC c F , 1 AH MX A , l5o EC M A 93 EC c C , 0 9] EH FT A ` @U EC EB A ( H@ AC X J , A: AC i G $ KW EC l D P J $ L EC BMy A 0 |L EC A , T M EO BRIO C , R EC BIIQ A xWC EC u A , WF AC M/ A $ X EC IY F , , 0Y EC YX G ( \ \ EO K: G $ ] EC G J ^7 EC i A $ _| AC S_ A $ d_3 EH C B ( |` EC GC F L `r EV Q A p La6 EC h A la6 EC h A $ at EC I J b; EC m A $ c EC Cx A lc; EC m A @ c@ EC r A ` c5 EC e C $ c EC C A Ld? EC v kdR EC I d? EC v d EC ( 4e? EC v H Se EC v h e EC ~ f2 EC i +f7 EC n Bf EC y fx EC o fc EC , $ g EC HM D , T Xi AO D] B k5 EC c E k EC x A xl_ EC t A m EC x A Dn EC L A , o EC E H $ P |px EC G G x r~ EC E K 0tu EC E K u EC E D $ 8w EE I H , 0x EC M C ( < zK AC P E , h 4{ AK P A , | EC M J , EC BIK G T EV q C TT EV q C 8 ; AO , T EC M G , EC PV B K EJ t C , Ȍ EC Gy H r N X EC t L $ ؍_ EC HI A H b EC HL A l `1 EC c A 1 EC c A 3 EC c C ? EC p B @ EC q B $ EF CU E 4 h EC A X C EC El E | 0@ EC q B P EC A A 1 EC c A $ EC ^ J P A $ EI c G P A $ 0 쑇V EC t D P A $ X $z EH Eb A $ | EC Io A 䒇 EC A EC A ,T EC z F lT EC | D 0 ܔ3 EC e A P 3 EC e A p 3 EC e A <3 EC e A \3 EC e A |9 EC k A 5 EC g A 3 EC e A 0 ܕ3 EC e A P 3 EC e A p 3 EC c C <\ EE n H | EC H A EC H A ė EC E F p3 EC e A < EC x H , ` ,a AF BN E $ l EF I G , D EC BN G , $ EC BN G , EC BN G , H ĩ EC BN G , x EC BN G , d EC BN G , ĵ EC BN G , EC BN G , 8 T EC BN G , h $ EC BN G $ ć ER W J ] E lŇM EX j A ŇM EX j A ŇM EX j A ŇM EX j A @ ,ƇM EX j A ` \ƇM EX j A ƇM EQ q A ƇM EX j A ƇM EQ q A LJM EX j A ! LLJM EQ q A ! |LJM EX j A @! LJM EQ q A `! LJM EX j A ! ȇM EQ q A $ ! <ȇ EC j N \ E ! ȇM EX j A ! ȇM EQ q A , " $ɇ- EC G I ` H 8" $͇P EH } A X" T͇T EL } A x" ͇U EL ~ A ( " ͇ EC M A ( " · EC DK E ( " χ EC K H $ # @Ї+ EC G A ( D# Hч EC M D ( p# ,҇ EC M A , # ҇ EC Cs B ] K ( # pӇ EC M A $ # 4ԇ EC Iu A , $ ԇ2 EC Mr I , P$ և AC BLGH A , $ |ׇ= AC HK G , $ ه AC FEK E , $ L܇ AC DEED6 D , % ߇ AC P G , @% <w AC P] A , p% & AC BJ| D 0 % AF Mn N { A , % 8 EC FF I , & EO BX$ A , 4& EC FF B , d& / EC FF A & ` EC R A ( & EH FH A & D EC Eq A ' q EC _ E ,' C EC k K L' P J EC s J 0 l' ~ AC M L ] K ' !: EC c J ' !; EC c K ' " EC A ( ( "u EC K J $ 0( # EC En E $ X( $ EC Is D ( %= EE m A ( ,%A EG n B $ ( \%f EC CQ E $ ( %d EC EM E , ) %m EC BGD K $ @) ,'i EC GP E $ h) t'] EC GH A ) 'h EC EQ E , ) ' EC HD( D $ ) X)Z EC BHB A $ * ) EC BHg A 4* )J EC { B ( T* */ EC BEN A ( * - EC K J * .o EC y G ( * P. EC M H , * /~ EC BEJLO E (+ d/M EH Eq E , L+ /p EC BIDT E 0 |+ 1 EC Me F _ I ( + ,3 EJ _ J P A + 4E EC w A ( + 4 EC DF G (, 55 EC c E H, 5 EC A l, p6 EC l G , 65 EC c E , 69 EC c I ( , 7 EC M K ( , :d AC G I ( (- D<< AC W D , T- X= AC MR ] , - > AC MR ] , - 8@$ EC h} C - :j| . O5 EC c E ( $. 8Oq EC BEHP E 8 P. O AC \2 F h H v J . i| . @Q5 EC c E , . `Q EF BN E $ . T AC I A , $/ xU AC BIDp E , T/ V EK KU A / _8 EC j A / `3 EC c C / (`3 EC e A / H`3 EC e A 0 h`3 EC e A $0 `3 EC e A D0 `3 EC e A d0 `9 EC k A 0 `3 EC c C 0 aH EC z A 0 8a EC Ed G 0 a AC E B ( 1 Pb EC DF A 81 $cM EQ q A X1 TcM EQ q A x1 cM EQ q A 1 cM EQ q A 1 cM EQ q A 1 dQ EC Ez E , 1 PdP EF FF! H ( ,2 pe EE H K $ X2 Tf, EC C D ( 2 \g EC M E 2 iX EC EE A 2 Li: EC j C 2 liQ EC A C ( 3 i EC G A , @3 j- EC HD G ( p3 l% AC MW H $ 3 m EC I{ D , 3 m AC DEED C , 3 xo AC \W A $4 (rT EC | D $ D4 hr AH BW{ C , l4 @s AC HEI F , 4 u AC BEH H 0 4 }k AC BEEEOO E , 5 AC Py A , 05 , AS P6 F $ `5 ܊] AC C B ( 5 EC K< A 0 5 / AC BEFHK F , 5 EC M G 0 6 4 AC BEEED B $ L6 AC I F $ t6 AG BH E $ 6 `[ EC I D 6 EC E A , 6 T% AC C K W A ( 7 T AG I R , D7 ȫ= AC M K , t7 خ AG M L $ 7 x EC G G , 7 `7 AG BN D ( 7 pl AC M A 0 (8 AC K G r N ( \8 0 AC K, E , 8 v AC M. A ( 8 EC K% H , 8 HĈU EC BGED! E 9 ẍ E_ ] E 89 ̈ EY L $ \9 ͈\ EC GG A 9 Έ5 EC c E , 9 8Έa AC h H , 9 x EF BGM F ( : D EC BGJ F , 0: < EC BD H _ E ( `: EK Ev E , : ` EC BN H $ : N EC Cd A $ : ( EM C I , ; EH KOT` E ( <; EF G A ( h; ( EO U H , ; ~ EC C@ E d E ; H> EC c N , ; hU EC FFm G < ; EC m A , 4< EC BL` J c E ( d< x EC EX K T A ( < EC G H $ < P EC G F < EC Z N = d8 EC E $= j EC H$ @= c EC BDK E $ h= $C EK J H , = L* EC FED B 4 = L EC FED K C E $ = k EC ET E , > \ EC FEDa E $ P> EF Ek E $ x> d EF Ek E > H EC c X > <C EC c S > l1 EC c A ( ? EC DJ J ,? 0z EE Ea E P? K EC r L p? a EH N A , ? EC G I W A , ? EC P) G ? @ EJ k A @ 8 E EC u C ( 4@ h a ER DHf G `@ ^ EG L A @ h EC EU A $ @ 4 EC C A @ < EC n A @ 7 EC i A A < 1 EC c A 0A \ 3 EC c C PA | 3 EC c C pA E EC w A $ A AC E F A EC V R A ! EC A , B !" AC Q G ( 0B %> AC FHu I 0 \B &} AM I% A v E ( B ( EC DK A , B + AC BELa H , B @3- AC BEGD G C @5i EC Et G , @C 5 AG BJ I $ pC D EC GK F , C D EC M E C GY EC F B 0 C H EC Kk J ] A 0 D H EC Ks J ] A 0 TD (I EC K G [ A ( D I EJ En N T A ( D hJ EJ En N T A $ D J EC C E ( E K EJ En N V A 4E LK EH x A TE 8LY EC G A , xE tLu EF M G , E Os EG I D , E R EC P; E F W\ EJ A G , ,F 0X EC HD A $ \F X~ EC Ig A , F HYB EC M H $ F hZ EC Gj A F Zn EC L D $ G [| EC G[ F ( (G d[} EC e F TG \L EC ~ A tG \k EC ] A , G 4] EC I E ( G _x EC M~ E , G he EC h F $H Xhi EL R A HH hL EC Eu E lH hC EC q E $ H i EC Gu D H ih EE v C , H i7 EC FHHJ H I l EI E , (I tma EC P< D , XI r EC DHJ F I w5 EC g A I w EF s B I xX EC ~ M , I yS EC BEM1 A ( J Dz& EJ X Y P X ( DJ H{@ EC DH J $ pJ \| EC Q O g H ( J | EJ y X P Q ( J }0 EC DH D J ~: EC c J K ~5 EC c E $ 0K ~ EJ Gq I XK ; EC c K , xK 4 EC M A , K EF FJH\ A $ K Tz EC I_ E ( L EC Ez I _ I ,L 0 EG q C LL i EC L D , pL , EC DL H L ܑ EC p H L EC m K $ L EF Es A M | AC K 4M Hs EG Et K ( XM EC BF A , M H EC M, G ( M 薉 EC M} F $ M l EC U{ A $ N 䗉W EC CF A , 0N EQ BKEI K $ `N ̘ EJ BD_ D $ N 4 EC S F , N 왉b EC DH H N ,G EC m M , O \ EJ BN A 0O ,8 EC j A , PO L EC P D ( O 젉 EC M H $ O ࡉo EC C F $ O ( EH Gb J , O ` EC \ F , ,P Ъ EC BEEED E , \P | EC HD G $ P h EE BHN A $ P 8 EC I G ( P 0 EC Kw F Q 䯉> EC c N ( (Q EC BNv A ( TQ x EC BEHB G Q 찉T EC q G Q ,O EC k E $ Q \j EC BHu I ( Q 1 EC K F ( R , EC Kp E ( @R , EC Kp E $ lR EC G I 4 R EH C C O O R PZ EC m K , R EC M| G , S c AC I H LS Pȉ` EC EM A pS ȉ` EC EM A $ S ȉ AC V G S ɉ_ EC v B S ʉF EF k K S 0ʉ EC EY A $ T ʉh EC GS A , HT ˉH EC e A , xT 4̉ EC C@ E p A 0 T ̉Q EC M E ] A T ͉F EC x A T ͉S EC r F U 0ΉP EJ v F <U `Ή EC E` K `U <ω EC A , U ω EC FJH D , U Љ AC DKN E U Ӊ= EC c M V Ӊ7 EC c G $V Ӊ: EC c J DV Ӊ` EJ I C hV 4ԉH EC Eu A $ V `ԉp EC H H P C $ V ԉp EC I G P C $ V ԉ EC [ M P C $ W XՉp EC I G P C $ ,W Չh EC I P C , TW Չ EC Gf K Y A 4 W X։L AC BIDV G I $ W px EC O I P C $ W x EF S B P C ( X ؉! AC M C $ 8X $ىP EC j F P C , `X Lى+ EJ FIH A , X Lډo EC J C l D , X ۉ EG BEEEK J , X | EC DD L Y A , Y EC DEEH[ G PY ; EC k C pY F EC v C Y LL EC | C Y |L EC | C Y L EC | C Y L EC | C Z L EC | C 0Z <1 EC c A PZ \; EC i E pZ |; EC i E Z Q EI y E Z EO L H Z 8N EC c ^ Z hc EL | K 4 [ EC FEDI H Z E , L[ P EG IS H , |[ EG I E , [ _ EG HD C , [ o EG DH K $ \ EC G C $ 4\ EC G I , \\ EG I$ G $ \ EC Gr G $ \ h EC Gr G $ \ 0 EC GW J $ ] EC I^ A ,] EC E~ A 4 P] EL J ] P ` ` P ^ K 4 ] t. AF HH J A $ ] l EC I K , ] Q EC DL I ( ^ 4 EC DJ K $ D^ EC G E ( l^ EC DEDJ A , ^ D J EC DL A , ^ dI EC DL F , ^ EK DIIH G , (_ w EK FIH A , X_ D EC HH G , _ Z EC HH E , _ 4 3 EC HH C , _ D' EC HH E ` ;|H EC c X ( 8` $ EC M E d` > EC p A $ ` EL q V ` J 4 ` p EC FEDw B u E $ ` X EC q G P C a @^ EQ B A 0a |O EQ s A Pa = EC o A pa = EC o A a = EC o A 0 a ~ EC M F z F , a X0 EC DEJ A ( b X EC M C @b < EC E E $ db EK o Y ` H $ b @ EH Ep F , b EC h4 A b x/6 EC c F ( c / EC DO} A 0c 0 AC Hl H Tc x0 EJ E F ( xc 41i EC BJO A ( c x1 EC BJj B c 1 EC A B ( c 2i EC BJO A d 2_ EC } K ( @d ,3k EC BJQ A ld p3Z EC EG A ( d 3 EC DF A ( d P42 EC M| G , d d5* EC HD A $ e d6 EH DO| D @e 6[ EC E{ H $ de 7> EC Gp A e 8O EC Er A e L8Q EC Ez E , e 8 EJ Mn E ( f ; EC I I ( 0f l> EC Gv K z A $ \f >W EC Gp A $ f ?W EC Gp A $ f @?b EC Gs F , f ? EC FJ^ A ( g A EC M F , 0g A EC Md G ( `g LC} EC DEG_ A $ g C[ EC CJ A 4 g C EC P X P ` P ` P C g DX EC J A h Dg EC EM A 4h Eg EC EM A ( Xh dE EC K E h 8Fl EX G C , h F] EJ HK5 A h GR EQ t C h G8 EC c H i H8 EC c H 8i 4H8 EC c H Xi TH8 EC c H xi tH8 EC c H i H8 EC c H i H8 EC c H i H8 EC c H i H8 EC c H j I8 EC c H 8j 4I8 EC c H Xj TI8 EC c H xj tIv EF c C ( j I EC G D $ j 4K EC Ih G $ j K EG Ih C k DL8 EC c H 8k dL8 EC c H Xk LY EF F C |k L8 EC c H k L8 EC c H k M E[ h C k lMQ EM w C l MN EM t C l M EC p H Dl Na EJ J C hl OW EM } C , l TOq EC DFLID A ( l P EC BH A l xR8 EC c H , m R EC BIH% H 4 4m xT EC DKDk J ` A lm Uk EG EG H m LUk EG EG H , m U EC I E m HYO EC o I $ n xYf EC B F P A $ ,n Yz EC Ci A Tn Z5 EC c E tn 8Z5 EC c E n XZ@ EC d O ( n xZ EC DDl A n ZU EC EB A o [@ EC r A , $o 8[ EC BHJ D Z E To [@ EC n E ( to [ EC M A o \ EH Au A ( o ] EH BER A ( o ] EJ DOv A ( p ^ EC I A , Hp ^ EC BELc E $ xp D_R EC h H P E p |_a EC K E $ p _y EC I\ C ( p ` EC K| A $ q `| EC C\ I @q ` EC E D ( dq xa EC DD G q <b8 EC j A ( q \b AC FH7 G q @d7 EC c G , q `d AC BID* C ,r 0g7 EC c G Lr Pg: EC c J , lr pg EC HK A r j: EC c J , r kM EC FMQ D r 0mN EC s E s `m? EC c O ,s m8 EC c H Ls mB EC c R ls m5 EC c E s md EC V A s <nI EC v B s ln EC H $ s Ho EC I E t p EJ ] D @t po EC r F ( `t q EC LU G t r9 EC g E ( t s E_ BF A t sD EM l A ( t $t EE BL H $ $u u EC Iq F $ Lu u EC Ie J $ tu u EC Ie J ( u Pv EC K D $ u vc EC BKH A u <w@ EC r A $ v \wc EC BKH A 8v w@ EC r A Xv w EC r F |v 0x\ EC K D v lx@ EC n E v xU EE B D ( v x EC M A $ w \yZ EC l L P E 8w y{ EC m A \w y< EC n A $ |w zs EC G^ A w hz8 EC j A ( w zh EC L D $ w {( EC I C 0 x | EC BEEED F Lx |o $ lx EC Gw J x | x d EC EQ A ( x ( EC DD\ D , y s EC CA E \ A , 0y 쀊 EC DEK~ F , `y \' EC DEJU[ E ( y \ EC M A y 0m EC \ D y |o EC S E ( z Ȅ EC DHV F $ 0z <u EC I^ A $ Xz EC G\ E ( z LI EC M` K z pc EC U A $ z [ EC Gp A , z EC DEJ A , ({ ԉI EC BGF H ( X{ n EC Eh K d E $ { 8 EC Ib E { : EC l A $ { p EC G[ A $ { H EC BHN H , | EC BEOm E ( L| `k EC MB I x| EC E K $ | ` EC IV I ( | 8r EC E L T A | b EC EK E , } ؙ EC I N Y A $ D} EC G D l} a EC E D } la EC H H ( } 2 EC M A ( } ̜ EC M A 0 ~ EC P H ] A ( @~ < EH M C , l~ ` EC ME A ( ~ EC BGDd G ~ 4 EC | A $ ~ _ EC I E ( أz EC EF M T A @ ,3 EC c C ` L1 EC c A lI EC c Y ( W AC W% H Х AC K , AC FF J , q AC FLGr A , P \{ AC HK G F EF u A ܮ EJ EW E Ā X1 EC c A xg EC R A įp EM X A , EC G $ P ` EE j D ^ E $ x 䰊b EC i G ` E $ ,T AC G J ȁ dl EC EH K N EC @ A ( ܲ; EC DD% A ( < EC BJT H ( h EC K A , Xs EC DIED G $ Ă EC IX G o EP G N lN EP s A $ 0 EU M I { E ( X 4 EC PK E L EC Ey A $ Ļk EC m K a E Ѓ D EJ o A , <5 EC DGD C LX EL ~ D @ : EC c J ` 1 EC c A $ ̽h EC BHK A ( EC Ak D W I ( Ԅ EC Ak D W I 5 EC c E <G EC Et A D h5 EC c E d G EC Et A $ EC I A < EC A ԅ | 4 EC DGD L E $ | , D Ŋ EC BEL> G t g|# , xNJ~ EC MN E ( Ć Ȋ EC FD A $ <ʊn EC E F ϊC EC El E < ϊ6 EC h A \ ϊ NU A lЊ EC H^ B hъo EC a A ȇ ъ< EC j E ъ< EC j E ъ EC AP G , `Ҋ EC l D , P Ҋ EC BDE M Y A , ,ӊ EC BDE M Y A ( |ӊ EC BJH E ( ܈ 0Ԋ EC Ma J Պ3 EC c C , ( ֊ EC DEF D X ڊU EC G A ( | ڊd EC Mu F , ݊& EC DL A ؉ &| , ݊ EC I} E Y A ( ( ފE EC E H [ E ( T ߊb EC Es H T A $ ߊ EC G~ A dL EC Ey A ̊ 6 EC h A , EC BEGH I , 0f AC FM A L | ( l P` EC DGC E : EC c J ( EC Er Q n E , 8 EG FED H ; EC m A 4 88 EC c H T X8 EC j A t xt EE b C 3 EC c C $ u EC C| I , L AC BEEK D < H EC d W , 0 l EC DEJG F 4 ` 1 EH BJ F H H 4 EC FGDH O a G , Ѝ l EC BEH K L0 EC x H ( 0 EC DDi A L `1 EF G p 2 EC G 2 EC F d3 EF D P4 EC D <5 EF D , $ h6 EC BGJ A ( T (9 EH DHw A 95 EC c E 93 EC c C 91 EC c A 91 EC c A :1 EC c A $ <:6 EC G J , H T; EC FEH I , x @- EC BEL J ( A EC DHt A Ԑ xBV EC H A Bi EC [ A , C AF DH D ( L E AC M J 4 x HC AC P E J J| EC O I , ԑ XK EC DEF G , 8M EC I A 4 PQ EC y G T (Q8 EC j A 0 t HQ| EH BELEK F $ R EC GM D $ В S EC I K , S0 EG DIHO B ( T; EC m A 0 H U EC BEJb E T L , | V@ EG FJ F \= EL f A $ ̓ \ EC Il A ( 8]| EC DDf A 0 ] EC BL} E P H ( T x^ AC c A , _) AC DEED H 4 `B AC FEH D { E , 4b AQ HD C $lY EC @ L < `lV EC } L ( \ l EC K A $ mq EC IV A ( lm EC DIk H $ ܕ n EC IF I , nW EC M A $ 4 o EC I G \ p< EC k D , | p0 EG BEGD C , q EG DEF A ( ܖ r EC DEDa E ( rc EC DH H 4 8t` EC Ew L X tt= EL f A $ x ty EC Ib A ( tb EC Es H T A ( ̗ 0u9 EC M C , Dv EC FJ H $ ( x AC E A , P z AC D\ E , | EC HD A , }@ EC DEFy H 8 AC DFS O K E C M , ; AC FEH= D , L 2 EC YI F , | 0 EC DGD B , Ў EC DEED F 4 ܙ EC DGD" G J F , XG EC P@ H 8 D xj EC P L P E { E ( EM BT F ( EC P H , ؚ 4 EC DIIHm A 4 > EC BID I t E $ @ EK C E h EC Qk D $ EC I A 6 EC c F ԛ 3 EC c C 83 EC c C X8 EC c H $ 4 x EC BH H \ EL J ` > EJ E A X H X H X H X H X H T L T L T L T E ` > EJ E A X H X H X H X H X H T L T L T L T E H ty EC L D l Ъ6 EC c F 6 EC c F ` EC \ D Н L6 EC c F l6 EC c F a EC L D 4 ح6 EC c F T 6 EC c F t ` EC \ D T3 EC c C t6 EC c F ؞ A EC \ D 3 EC c C ಋ6 EC c F < EC \ D ` 춋6 EC c F 6 EC c F ,` EC \ D ğ h3 EC c C 6 EC c F EC \ D ( 6 EC c F H $6 EC c F h D EC L D 6 EC c F 6 EC c F $ ̠ @ EC BD J 8W EJ o T xj EJ U A 8 Y EC K A \ EC T| A | EC T A , EC M F ԡ ċ EC m K ( Dŋ EC M G $ Ƌ3 EC c C D (Ƌ EH Eq E ( h Ƌ EC Kq D $ XNjm EC GT E ( Njq EC BL K 4 ɋ EC DH A C ˋ EF E D 8͋ EC H 0 h Ћ EF BL C J ҋY EC D D ҋY EC D D 8Ӌr EC D D Ӌr EC D D , Ӌ EF t A P lԋw EC @ H t ԋb EC M D ( Ջ EC BEM] A $ Ĥ hՋc EC BKH A Ջ EC x H lT EC F A ( 4 EC Ep K W A ` ,} EC Y G EF I L , ڋ EC BEMl H إ ڋ EN A , Pۋr EC I@ G , ܋I EC I P EE P F t Hދ EE S C ދ ES B Pߋj EC Y D ߋc EC R D ߋO EC A A ( OC | D L EC s E , l EC BHn H n E $ P EC Gl E $ ħ b EG v F P E ( o EC Ei J e E TX EC AI A ( < AC DD C $ h m EC C\ A ( < EC BKA J EC A , \ EH BIH E , <Y AC DEED) A @ l EC C d H9 EC c I h< EC c L < EC c L ( ĩ EC DJt F , 8 EC FF G $ , EC C| A ( H EC M I t HZ EF | I , H EC FI E Ī P EC Em F ( EC BOD C 89 EC g E 4 X5 EC c E ( T x EC DM K ,5 EC c E L5 EC c E , l EC HMw D $ N EC h H P A 5 EC c E 8 4 AC E^ I , \ AC CN K Y G ( AC K K 0 43 AC M L a G , @ AC M H 0 S EC M K a G ( P L EC BO^ I ( | 3 EC M K ( 3 EC M K 4 ԭ EC GY H Y G E K $ EC I D 4 ` EG N A , X EC DH K C EO EC $ R EC CA A D\ EC I O EH z C ( ( x EC e A T @ EC r A , t ( EF HD B , EC CO F \ A ( ԯ x EC DEDh C , r EC BJ J $ 0 < EC BH{ C X L EC Eu E ( | AC I G , $ AJ BEGD H ( ذ t) AC FH G *< EC n A $ $ * EC BL@ J ( L + EC K A x ,< EC c L ,S EE A C ( - EC EB I A -P EC E} A 0 - EC Ms H d A @ \.O EO q E 0 ` . EC Mp K d A /O EO q E H/\ EC } K Բ /R EC D A $ / EC C} H 0 EH A 0 D 81l EC K F V J 0 x t2l EC K F V J 3 EC Ef M ( г <4x EC BJ^ A 4d EC | D 48 EC j A < 58 EC j A \ 58 EC j A ( | @5 EC FHt F $77 EC c G ( ȴ D7 EC KO N 8d EC S D $ $9~ EC T D T E $ @ |9c EC BHK A h 9O EC A A ( 9 EC BLA I $ : EC Sv G ( : EC W A , ;T EJ DEO' A $ < <] EC BHE A $ d < EC Cg F p=F EM n A =8 EC j A ̶ =: EC j C , = EC GB G ~ E 0 P>o AC M E o A $ P ? AC Mk D ( x 4@ EC BJv A @E EC Er A $ ȷ @x EC Gq H ( A& EC I[ D BP EC E} A $ @ LB EC G} E , h B EC M) B $ D] EC CL A , D EC DEJ E ( E EC BGHf A , @FV EC BJ J , L pG EC BGJj K | GM EC A HX EC J A LHQ EC C A H> EC c N HM EJ x A $ HC EC i M ( D I EC BEO F p I> EC p A , J EC DJEH| A $ JR EC i G P E ( J EC GA H , K AC \d D D XM4 EC c D d xM5 EC c E M7 EC c G $ M EC BI` E , ̻ 0N EC M& E , O EC DH A $ , Px EC GG J ( T Q EC Mu F $ |S EC Ix A , Sr EC HK H ( ؼ 4V EF M A V7 EC c G , $ W| AC Y# H , T X] EC Ef M _ E , ]M AC FEH A ^G EC y A $ Խ (_{ EE Ch A $ _t EC BHE I $ _ EC V B H T`n EC I h `3 EC e A `9 EC c I `5 EC c E Ⱦ aQ EC y G , Da EH DDE F l E ( a EC KC J , D b EC Y E $ t Hd~ EC GE D ( d AC W J ( ȿ $f1 AC \ F , 8ka EC DL E 4 $ xm EC DEF J ' I \ o7 EC c G , | p EC \ E 4 `q EJ HM A P E , 8r2 EC t+ I $ H EC GP A $ < { EC GC A d m EC A ( Xp EC MB I $ + EC Iy F EF E} C EC EX A } EL f A , D EC DGHe H t 菌? EC c O = EC c M (> EC c N ( H EC Mx A W EC ED A $ 5 EC c E , D T EC DEEH H , t H EC FEDk F EC A EC A , 0$ EC DEJ D 0d EC V A $ @ |` EC CK E ( h j EC DDP E o EC a A ( D EC DED A ( EC BF F $ ̗p EC C@ E 8 I EC p H X DG EG El E ( | p EC DKv E 䘌q EH EY A @t EH E\ A , EC BEI A <i EC EQ B 0 D EC Kx E ] A , x } EC CH M W A , d} EC BHA M W A ( AC DJ C ( EQ Gt G , 0 < AG FED A , ` ̦ EC FM J ( | EQ Gz I $ EG It G , AC I A 5 EC c E , 4 8 EC DEN A d 6 EC c F , 8a AC DGD G ( x EQ FH H , LV AC DH A ( |Ì EC M F ( < pČ EC I A h 4ŌQ EI } A $ tŌk EC BHS A ŌZ EC L A , Ō EF M G Ȍ3 EC c C $ Ɍ3 EC e A D (Ɍ4 EC f A ( d HɌ AC h I ( ˌ EK G A `̌o EM E S ̌W EC E E ̌W EC E E , ( $͌ EK BU A X ͌I EC c Y x ΌI EC c Y 4ΌI EC c Y 4 dΌ EC BN G E ЌI EC c Y ьP EC ~ E 0 LьP EC ~ E P |ьP EC ~ E $ p ьw EJ BHT E ҌP EC ~ E 4ҌP EC ~ E dҌP EC ~ E ҌP EC ~ E ( Ҍ EC M E ( D Xӌ EC M E , p ӌ' EJ FP A ( Ԍ EH DI F ( Ռ EC M G 0 ; EC M I Q E ( , ، EC M A , X ،I EK M E , ٌ4 EC BEEF D ( ڌ EG DF H $ ی EH G^ F p܌? EE o A ( , ܌x AC P E 0 X EC M J u E 0 ތ EC P G q O p EC E| G EC ED G ( t AC DED F $ 4 EC m K t F \ 03 EC c C , | P AC I2 A , AC hT H k EC x H , o AC e, K 4 , 0 EC M I E d EC E] F $ t EC G` A $ EC Gx I $ EC G D , l EC M> E ( 0 <> AC K G $ \ Pk EC GO A $ k EC GO A $ k EC GO A $ (k EC GO A $ pk EC GO A $ $ k EC GO A , L EC M< G , | ` EC M G , AC DEJ H $ ` EC Gi H , C EC M< G , 4 EC M G d y EC E E $ EC G% D , EC M D , EC M H ( \V EC Ip G , < T EC M F ( l \ EC K G , EC M| G , AC M H , 4'F EC M A 4 ( T( EC BN A B E , ` ,*V EH MU A \1E EO k A 1G EQ k A 1F EO l A , 1 EC BGJ D $ 2 EH C A ( H d3 EH E{ C p L ( t 4 EC M A ( 4 EC M A $ p5 EC q W z F 5D EC k L ( 64 EC Id K , @ ,8 EH BHF K W A ( p 8$ EJ M K 9 EC Ed G , 9 AG FID B A9 EC g E , A EC DDy G i E , @ <B EC HD C , p C` EC M4 G , LDP EC M( C , lEY EH I8 B , FN EC M, A , 0 GI EC FM" C ` Hg EH IK A $ (I EC L D $ I EC L D $ 8J EC L D , Ji EC Y> A ( , L EJ M H ( X M EC M I , PE EC HH C R3 EC c C ( R EH DEi A S6 EC c F ( S EH DIn H ( L 0TC E\ DOS I , x TU EC M= F ( V( EC M C Y EL IX F TZ; EC c K tZx EH e A < Z= EC c M , \ Z) EC HIM J , \ EC HD= G p`e EH R A ( ` EC DF G , b EC IA F ( < h EG K1 H ( h if EJ BK~ F ( j EC M B $ ko EC C B ( m EC e G , n EJ P" G $ D p AC G C $ l pq AC I H , Xrj AC BIM K W{ ( xtB AC BM) A ud EJ q A , 0 u AC DL D $ ` w] EC BLA A ( wD AC I J $ xS EC BD A , 0y{ AG DEF A , { AC FM A , < l AC M I l M{M 4 0 AC BEO H E 4 EC DGH| I m E , p[ EC HH A , 5 EC c E 0 L S EH E E I 씍 EC B F , X^ AC MB E 7 EC c G : EC c J $ Ș EC Gv K , < 0[ EF DEF A , l ` AC DEK A 0= EC c M P EF o F ( EC DEH G ( J EC DED F 8 D8 EF Aw E , \ `C EC W a A O P ` l EC \ C , ̡ EC DH G $ <^ EC n J P I $ t EC Is D , 0 r EC HR A ` L EJ EC I , 諍 EC GT M _ A Xl EC EY A $ e EC GL E $ 쬍 EC BH A ( EC X H , L @ EC DFJd H ( | Ю EC DH| A Dm EJ U D $ 3 EC G G , EC G N W A , $ x EC BGEH6 D 8 T ( EC DL J J < |: EC Ig H n J W A R N 6{ `8 EC j A 9 EC k A , EC A P , EC m K ( p 8 EC P J EC A l EC A $ < EC BDv D 0 EC H A 0 EC I $ T Íw EC m K m E | č EC EY J č EC C (ōS EC p V $ hō EH L A ōV EJ Ex E 0 <ƍy EC b F , T ƍ& EC FN} G ǍD EC s D Ǎ@ EC n E ǍE EC Er A , $ȍ* AG DEFG D ( $̍ EC BOb A $ D ̍ EC CN G , l ͍ AQ HDc G , э EC I K , pԍ AC \H H , ٍ AC i A , , AC DO D \ 9 EC c I | Z EC EG A j EC W A $ hh EC IQ A [ EC EH A , Q EC BFJJv F , @ ! EC DED} F p S EO Et A , XR EC DIK H $ + EC U C ( c EC En E Y E ( AC BEHs J $ D EC BD{ G ( l EC Kz C ( EC G G $ EG Gl A $ pZ EF j K P E , EC FF J $ D h] EC E E $ l EC BHO G G EJ p C 8J EJ s C hY EC m K Y EC m K Y EC m K 4 (Y EC m K , T h EC DL J , z EC BEL E $ EC Eq A p< EC c L , EC DEF} A ( , , EC Y K $ X EF G N ` E , lL AC Y B ( EC DJ A @3 EC c C $ ` EC I A ( $ EC E M T A ( P lb EC Es H T A | 5 EC c E ( EC K A $ Tu EH IY A R EC E A 3 EC c C , 4 g EC HD K , d H0 EC M I H EC Ed G i EC EF E $ X EC p E P F , 8 _ EC Y G 4 h 9 EC c I , T Z EC DH F ( EC BJc I , < EC I A , D EC P& A 9 EC c I $ 0 EC BLm A ( X d EC FDy A ? EC c O $ z EC Ic A P\ EC } K ( EC M D 4Z EC EG A < pZ EC EG A , ` . AC BQ G 8 & EC M O T D x E $ (X EC o I P C ( H( EC Ps E $ ,* OC GF A ( H * EC BL_ K t (+< EC c L H+7 EC c G 4 h+ AC FIK O C ( / EC FD G ( 1 EC DD A D x3M EC L L T L T L T L T L T L T L T L T L T L T L T L P P P P P H P H P H ( 45 EC FHu E 6T EC F A ( D6< EC j E $ H d6e EC E E p 8< EC c L 8c EC AT A , 9J EC \6 F ( 8@ EC BOh A @e EH R A 4 @ EH E[ C X TAF EE t C x A= EC o A AJ EC Es E $ Av EC I G T E (BC EC u A XBQ EC E~ A $ ( Bj EC IG H ( P Co EC C~ G Y A , | D EC DDN J [ A D8 EC j A $ D EH Go A Ea EF N C $ TE EF I D , @ LF EC MI B p HC EC Ep A I EC F B I EF U H IS EC C C ,JL EC ~ A \JF EC v C ( @ J EC G G , l @K EC IS L c A $ K EC Iz A (Lh EC Es H tLb EC v B L] EC EJ A , Mu EC @ H $ P \M EC Gf K $ x M EC C A $ lN EJ BD] F N3 EC e A O2 EC d A $ 4Ol AC C_ A , 0 |O AC FJV F ( ` lQ AC BHx J , `RV AC I D , Tc AC FEH B 4 V7 AC FJ N ; E $ Z5 EC c E D Z3 EC e A d [5 EC g A 8[3 EC e A X[5 EC g A $ x[ EC G A [l EC EY A 0 <\+ EC Kd I E $ D 8]] EC CL A $ l p]V EC CA E $ ]Z EC GE A ]7 EC i A , ^ EC DGH A , ^ EC DGDs F < @_U EC G A ` |_Q EC C A $ _] EC CL A , _k EC DH D ( 0b EC BJ D ( $c EC DH\ H 4 c EF Em C ( X $d EC I K $ f EC E A $ g EC G O 4 h EC FJ I . B plc EC Ex K 0 lO EF Ey A T l5 EC c E t m8 EC j A ( (m EC An I \ D $ m EC I k E Dny EC B F nI EC u C , n? EJ h C L o? EJ h C l o? EJ h C @o? EJ h C `o? EJ h C , oF EC HDC I qi EC { M qi EC { M < @ri EC { M \ ri EC { M | ri EC { M 0si EC { M si EC { M sE EC w A td EC V A Lt: EC l A @ ltk EC ] A d th EC Z A u7 EC i A $uk EC Ex K puE EC l L uF EC m L $ u EC I G k K $ 4 Hv EC E _ G \ v@ EC k H , | wy AC FG H `x5 EC c E 0 x AC K G H , {a AC DJHD N 0 <}m EC _ A ( T }6 EC V B D L EC A $ (u EC } K X H $ EC e C X H $ EC b F X H ( p EC Gy H | E , H 䁎 EC C G y E , x EC GZ G | E 4? EJ h C T? EJ h C , t AJ HHj K $ AC Ug A @ lE EC w A $ ` EC BKV E $ e EC v B X H $ Lu EC G A X H $ u EC G A X H ( EC Gt E | E , `Q EC Ez E , P ] AK DIEDb D { ( i EC Et G W E , EC I I Y G , Ќ EC BEGI G , 0 EC F P EC A $ t 藎_ EC BIB E < EC c L @] EC E@ C , | AC HD E H AC BEEED F ] C E C , \ 1 AC DGD H R EC } H 4 q EC HD I F , 8 EC HDz B ? EC q A , 4 ج EC FED H ( d x EC f D ( L$ AC M C ( P AC M D DC EC c S tS EJ Ey A , , EC P D \ Ǝ~ EC p A ( Ǝ EC BGMs A pǎ< EC c L ǎ< EC c L ( ǎ EC BJy A $Ȏ< EC c L ( 8 DȎ EC K A d ȎY EC E C , Ȏ` EH HD G , $ʎ EC Iw H Y A , ʎ EC M A $ tΎ EC Gj A $ @ Ύ EC I G $ h ώ EC If I D ЎE EC Mu F E K \ L D ؎Y EC PA G J E E , , EC M J P = EC k E ( p } EC KW A 0G EC Ep E \G EC y A , EC BN~ J L EC t D ( 0 L EC M} A \ ; EC i E ( | AJ DJ$ C d EG Es D , ; AC Mf I 7 EC c G ( EC M J H = EC c M h I EG m G y EC k A , `c EC MH A ( EC BJi E ( S AC M C 4 8J EC | A $ T h EC Id K | 5 EC c E Y EC H D ( L EC EP C k E 5 EC g A 5 EC g A , 02 EC d A L P2 EC d A l p1 EC c A ( EC dE G $ EC Gy H |5 EC g A $ EC I A ( D5 EC g A ( H d7 EC WQ H t x EC E| G $ Dc EC CR A ( i EC DHO A T EJ A _ EC Q A 0 0 L AC Mu J Q O d { , AC BN D , 8 Z EC HI; A , h EC DGOW G EC EW L 8 D6 EC h A X t\ EC IE A | 8 EC j A Y EC H D ( l EC DGS A , P EC DGE A C EG q A < EG ] G , ` EC BIEFw K $ \ EY C| C $ q EC BLU A $ < EC Ir E ( x EC DH^ A , 4 x EE BHs I ^ E 0 d Xj EC FD A f J , EC DIF^ A , u EC n J P H P H , 4 \ EC BID K , ( d / EC M A , X d v EC MW E , Y EC FO H $ v EC I G T E $ < EC Cz A 4 EC c D ( 7 EC i A ( H EC DILd A ( t Hw EC BIHV A , 7 EH DEJ I , I EC HD H , EC HI A $ 0 g EC GR A ( X EC I C , x EJ FFH F 8; EC j D , X AH Pm J , 8l AG W A ( 4 x+ EW DF A $ ` |j EH GP A : EC c J 5 EC c E , z EC r N P H P E , T 7 EG M G 4 (! d EC v R P H P H P G , `! EQ DIK A , ! C EC M( A ( ! EC K A ! p ` EC R A ( " EC Kz A <" P!? AO X" t! EC g A |" !2 EC d A " "Q EC z F " P"Q EC z F " "3 EC e A " "3 EC e A # "2 EC d A , <# " AF FLHt A l# `#6 EC h A # #4 EC f A # #T EC z A # #T EC z A # $5 EC g A $ @$5 EC g A ,$ `$2 EC d A L$ $4 EC f A l$ $6 EC h A ( $ $ AC I| G $ %8 EC j A $ %6 EC h A $ %8 EC j A % %5 EC c E , 8% & EC FJK A $ h% & EC G D ( % ': EC DID I % (5 EC c E $ % ) AC G~ G , & )H EC FJ K 4& s{ ( T& *| EC BJ G ( & + EC K D ( & , EC FDn H $ & T.P EC C{ E $ ' |. EC I H (' /5 EC c E ( H' 0 EC EK H | A t' 0 EC E A $ ' 1$ EC E G ' 26 EC c F 4 ' <2( EC M A ) E $ ( Z AC Gl E D @( ,[ AC Ii J ` H u C p H 0 H ( ( a EC Gr G s E , ( ha$ EC \ I $ ( 腏 AC E H , ) ( AC HH H , <) y EC C@ E b B l) < EC n A ( ) EC BGO} A $ ) EC GT E ) 7 EC c G ( * < EH DEg C ,* ЉH EC c X $ L* ^ EC j V P A t* 8E EC w A $ * h EC G A * C EC s C $ * P EC Ib E , + 茏 EC BEGPp J ( 4+ xq EC DIV A `+ ̍5 EC g A + 썏R EC n J $ + , EC E A $ + EC GB G , + ,~ EI HD D , , |, EH BIL A P, |9 EC k A , p, EC BHC K Y A $ , 쒏 AC UJ E $ , t AC UJ E $ , AC UN I $ - Ԕ AC XN F , @- + EC HH G p- EC Q\ A 4 - ( EC DEFk F w E - AC Qs H $ - < AC Ss F , . 4 EC I L Y A ( H. ԛ EC Kg F , t. 8 EG M A . (B EC m H , . X EC BFGHg J . i AC QN A $ / d~ EJ BKF F @/ EC Qe A $ d/ ( EC BK F / j EC QK A $ / <1 AC az A , / T AC DGED` H $ 0 ĩ EC GJ G , 00 < AC FJ F $ `0 AC Ss F $ 0 Ĭ EC GG J $ 0 , AC Uy F , 0 EC \i C 1 O EC A A , ,1 EH P F $ \1 P EC GH I , 1 ȸ EC DL\ D ( 1 H EC \} G $ 1 EC U^ A $ 2 h EH q R P C ( 02 \ AC \ A $ \2 P EC BK E , 2 EC BEEJ( J , 2 ď EC DM E ( 2 xƏ EC P I ( 3 |ǏS EC K E , <3 ȏS EC FEE A ( l3 ɏ AC BN E , 3 ʏs EC GF K J 0 3 ̏v AC M; D ! 3 `Ώ EC O I $ 4 Ώ EC G A ( H4 tϏ EC M D , t4 Џ EC DL B 4 яY EJ @ E $ 4 я' EC G A 0 4 ҏ EC K F I ( $5 ӏ EC DL] K P5 ,Տ EC B F , t5 Տ EC BIL A , 5 X֏ EF Iq K , 5 ُ EF M} A ( 6 Hۏl EC Et O V A 06 ۏb EC T A T6 ۏ EC As A x6 DI EJ t A 0 6 tF EJ G{ O B f E 6 ݏ7 EC c G 6 ݏ EC Em F 7 ,ޏF EC c V 07 \ޏ? AO L7 ޏ EC g A p7 ޏ2 EC d A 7 ߏQ EC z F 7 \ߏQ EC z F 7 ߏ3 EC e A 7 ߏ3 EC e A 8 ߏ2 EC d A 08 ߏ6 EC h A P8 4 EC f A p8 <T EC z A 8 |T EC z A 8 5 EC g A 8 5 EC g A 8 2 EC d A 9 4 EC f A 09 <6 EC h A P9 \8 EC j A p9 |5 EC c E , 9 EC FJK A $ 9 l EC G H ( 9 D EC DID E : 85 EC c E $ 4: X AC G~ G , \: H EC FJ K : _{ ( : | EC BJ G ( : T EC K D ( ; EC FD~ H $ 0; P EC C{ E $ X; EC I H ; L5 EC c E ( ; l EC EK H | A ; EC E A ; | EC E B < H6 EC c F , 4< hS EC M A , d< EU BREDH A 4 < 8 EC BEELH J [ 4 < EI DEED L A G 4 = H EI DEED H I G 4 <= EI DEED L A G ( t= [ EF J P H 0 = EC M3 H ] C 4 = EC M F K 4 > . EF M J G , D> { EC PT D 4 t> X v EC M F K , > # EC P: F 0 > 0'~ EC KE H A 4 ? |+ EC M L G 0 H? D4 EC K L E 0 |? 6s EC I I i G ( ? 9 EC c X A , ? : EC Gz G W A , @ <} EC GL E W A , <@ ? EC M< G l@ Bh EC Z A , @ B EH HK A , @ |G AC Y, G ( @ LJ AC e C , A K AC HKw B $ LA N EC G D tA XO` EC R A , A OK EC WB G $ A [p EC DHz B $ A [_ EJ p E P F B 4\3 EC c C 8B T\1 EC c A XB t\T ET p F xB \T ET p F B \T ET p F B 4]T ET p F B t]3 EC c C B ]j EC \ A ( C ] EC Ea J C A ( HC ^ EC Ea J C A ( tC (_ AC Y F $ C `l EC GG J , C T` EC DH~ N ^ A C `J EC Es E , D a EC DHw E ` A , LD a EC Gw J ^ A ( |D @b AC KQ H ( D c AC KP A $ D e EC IZ E $ D e EC IZ E $ $E (f EC IZ E LE fV EC EC A pE f8 EC f E ( E g EG DJ A E g? EC m E , E g EC M A , F @l EC DFQ A , <F m EC FFO A lF m< EC c L F m5 EC c E , F n EC EO A F E ( F o AC M A ( G py AC c K ( 4G r EC f I `G zE EC u C G zo EC L D G H{E EC w A G x{E EC w A G {= EC m C H {M EC A $H {= EC o A DH |= EC m C dH 8|L EC ~ A H h|= EC o A H || EC O I H || EC U C H @}V EE F A I |}V EE F A 4I }i EH V A XI ~q EH ^ A |I `~r EH _ A I ~o EH \ A I = EC o A I (= EC o A J H= EC o A $J hi EH V A HJ V EE F A lJ V EE F A J ,= EC o A J Ll EC L D J l EC L D J 䀐= EC o A K ~ EC ^ J <K `v EC \ D `K ~ EC V B K D EI o B K HS EI t F K S EI t F ( K Ȃ& AC DL D , L ̃ EC BEEH{ A @L <L EI t E `L lV EF A E L V EF A E L 䄐L EI t E L a EI } Q L dO EI w E M S EI { E (M ԅP EI x E HM EI I Y lM L EI t E M T EI | E M L EI t E M T EI | E M `L EI t E N T EI | E , ,N Ї EC FER A \N EF N W N 숐 EF N W $ N X EF A L P X $ N EF w ^ ` H N (n EF } X O xP EI x E ( 4O l EC BEHK E $ `O 슐e EC GP A O 4l EC K E O q EC K E O ܋_ EC Er A $ O EC Ej I P _ EC Er A $ @P EC Ej I 0 hP EC FD I E ( P 0 EQ DQIW A $ P AC I K $ P L EC CN G Q Ԑ5 EC c E ( 8Q EJ BJD I ( dQ h EC DFIg F ( Q ܑ AG DL F ( Q EC K] H ( Q | EC DFD` A ( R H| EC DFD` A ( @R | EC DFD` A ( lR | EC DFD` A ( R D| EC DFD` A ( R t EC DD^ A ( R 앐p EC DDZ A $ S 0 EC CR K ( DS EC DDS E pS U EC k E ( S < EC FHZ H 4 S З EC HH D I S L EC ~ A 4 T 虐 EF G V P X P X P Q LT EF ] X , pT EF @ ] P X P X T EC EX K ( T H EC FD C T <v EC h A U v EC h A 8U f EC X A $ \U @ EI O K d N U b EC T A U b EC T A U PY EC K A U 5 EC c E V 5 EC c E ( 0V ̠ EC BS K ` P 0 \V p EC HD E } K 4 V , EC HDf F } K $ V ĥe EC GP A $ V e EC GP A $ W T EC CN G @W ܦ EC Em F $ dW 8 EC BHb D W ~ EC V B W EM M Y W x EM V X ( W 䨐 EC FHk G $ $X ة4 AC BM A LX EF ] X ( pX | EC KV G ( X ` EC KV G $ X D EC Gn C $ X EC Ej I $ Y T EC Ej I $ @Y EC IU J $ hY l AC Iu F Y ܰ EC G Y EC A ( Y t EC Kx E Z H EC G (Z EC G 0 LZ EC HD E } K Z | EC E Z X EC E $ Z 4 EC G D $ Z , EC G D 0 [ $q AC Kh I E ( L[ p EC Y J , x[ dO EC HDi C , [ ? EC ME F [ s>{ , [ t? EC ME F (\ ->{ , H\ dĐ EC M E x\ ={ 4 \ ǐ EC HDf F } K $ \ lʐ EC C G , \ Dːb EC G F c E $ (] ̐ EC F J h H $ P] ̐ EC F J h H $ x] t͐h EC E D ] ΐJ EC x E ] ΐV EC Em F $ ] (ϐ EC CN G $ ^ ϐ EC CN G 4^ 8А6 EC c F T^ XА3 EC c C t^ xА4 EC c D ^ А= EC o A ( ^ А EC Cw F p E , ^ ѐ} EC CJ K W A $ _ lѐm EC Cy D 8_ ѐQ EC E~ A \_ ѐQ EC E~ A _ ,ҐQ EC E~ A _ hҐQ EC E~ A _ ҐQ EC E~ A _ ҐQ EC E~ A ` ӐQ EC E~ A ( 4` XӐ EC M G `` ӐB EJ m A ` ,Ԑ= EC o A $ ` LԐm EC Cy D ( ` Ԑ EC FJz F ` Ր EC E\ G a EI Ew F , <a a EC e A ( la EC Kq D ( a d EC K- H , a H EC FHH E a EC A b < EC n A , 8b P EC P D hb k EG EP E , b S EC BMI- A b P3 EC c C b p5 EC c E b < EC c L c U EC EB A @c d EC EQ A , dc 8 u AC I F c R EC Ex A $ c EC IB E $ c n EC GR A d z EC E` A , ,d 0 EC CQ L Y A ( \d AC M A , d 4 AG FJ# E d 3 EC c C ( d ' AC K E e 3 EC c C $e 3 EC c C $ De AC BH D le ; EE k A e ; EE k A ( e j EC BEHv C $ e $ a EC CP A 0 f l > EC Kx E E , 4f x AG M F ( df V AE E d E ( f L EC BEJr A $ f o EC GZ A , f EC DEED[ K ( g x EC K A , @g p AC DEHH D pg \ } EK g A , g R AC FEH D g !` ER Ez E g $"@ EC r A h D" EC En A ,h "l EK EJ A , Ph " EH DGH E ( h l% EC K A $ h & EC G H , h ' AH M/ K ( i X*F EC M G , 0i |+ EC FN C , `i - EC M G , i 0 EF GI E F E ( i ,1q EC DLS A ( i 1 EC ME A j ;@ EG n A 8j 4;T EC F A , \j p;. AC DH[ E , j p?s AC HD B j A EI H J j ,B9 EC c I k LBE EC s E k |BF EC t E @k Bh EC z F `k B EC Ew A , k hC AG DGH A ( k 8Eq EC E@ C W E , k E EC GE L W I , l lF EC GB O W I , @l LG EC GH I W I , pl <H EC GH I W I l I< EE l A l <I8 EC j A l \ID EC v A $ m I EC Gz A $ (m J EC I A , Pm J EC G\ E Y A ( m <K EK M A m K7 EC i A , m LG EC I A E 4 m 0Md EC M) B E 4n hO EC u C 0 Xn O3 EC I[ D I , n Q: EC M F n RI EC { A $ n SE EC G H , o HT EC DND F 4o X EC ED G ( Xo TYm EC Ev E [ E $ o Y EC BD A o ZF EJ o C o PZw EO Eu B o ZL EL u A ( p Z AC \ F <p \ AC Q A $ `p \] EC BLq A p ]9 EC k A p ]9 EC k A $ p ^ EJ Ge A p l^x EC Ew D q ^V EC H A ( 8q _ EC P A dq _< EC c L q `8 EC j A , q 8` EC DL D $ q ` EV I A q aP EC B A r aM EJ x A @r ag EC Ev E , dr 8b EC FJD K $ r e EC Gg J r ei EI E} H , r f EC I K H H $ s f EC U A , 8s g; EC DEM H $ hs hz AC S] A $ s <i AC K I $ s j5 AC S G s k} EC w A t |k AC Q D $t 8l EE @ F $ Ht lc EC GN A 0 pt l0 EC Ko F E t qF EJ q A t rF EJ q A t HrF EJ q A u xrF EJ q A $u rJ EC k E Du rL EC s E du sL EC s E u 8sh EC s E , u s EC e I , u u6 EC BJHD A $ v xq EH C[ A , ,v `x EC BEL. G \v yS EC m K |v z EC i G v `zp EC h H v zF EG q D $ v z EJ Im A , w H{ EC DL F $ 4w |m EC C\ A ( \w } EC DF A ( w } EC DF A ( w 8~ EC FD A $ w ~ EC Cz A $ x $m EC C\ A 0x l[ EC EH A $ Tx EC I A ( |x @ EC DDV J ( x Ā EC EB I T D x 8 AC TO I , x 䁑 AC Y] F , (y t EC G O W A $ Xy 4 EC Im A ( y * EC M F ( y 8 EC M K y t EC m K $ y k EC IP E , z \ EC h H ( Pz u EC DD[ E , |z h EC M A $ z ` AC a F ( z ( AC Y E $ { 쒑 EC Io H ( ({ t EC c E T{ H EC TA C ( x{ EC DM] J ( { H EC EP C p E { Y EC H D 0 { EC Ke H h A ( (| t~ EC DHG E , T| Ȗ EC M= F , | Q EC P A , | D EC BEEIO A | ؞[ EC D D ( } EC BJl H ( 4} EC BP~ E ( `} x EC YW H } ` EC , D ( } < EC P I } EK ^ B , ~ AC DHED D , 0~ \ EC FJ A $ `~ Ls EC CM H ~ 7 EC c G ~ Ĩ: EC c J ~ 䨑D EC v A $ ~ m EC IV A ( \b EC Es H T A < i EC EO D ` 쩑D EH o C R EH Ez A X8 EC c H x5 EC c E 5 EC c E $ P EC h H P C $ , ઑP EC h H P C $ T N EC h H P A $ | 0 EC I A 5 EC c E Ā y EC Ex K , t EC GQ H O A , EC BQ I $ H EJ BKM G ( p EC DM A ( r EC E@ K T A ȁ H EC Eq E < EC j E $ @~ EC I` A 4 N EC E{ A X 1 EC c A x 8 EC j A 4 EC C г6 EC h A ܂ EG u O ~ lW EG k I , EC DEEHo A $ P EC I A , x T EC FJ A $ Է EC G A $ Ѓ L EC Gc F $ w EC GQ H , \ EC MA A P { ( p EC K A , % EC FMk J , ̄ EC M G , 0 EC P A ( , őX EC K G ( X TƑ EJ DIm A Ƒc EM K A $ Ǒ EK L A 0 Ѕ Ǒ EC BGD G s M , (ɑ EC BKD B , 4 ɑ4 AF M_ E $ d ̑R AC E H , ё AC BNQ K , ӑ1 EC C J r F 4 ԑ EC DGI L ] C , $ ֑ EC BRy K p B , T ֑1 EC C J r F , ב1 EC C J r F , ؑ1 EC C J r F , ّ1 EC C J r F , ڑ1 EC C J r F , D ܑ1 EC C J r F , t ݑ1 EC C J r F , (ޑ1 EC C J r F Ԉ 8ߑc EG Q A ( ߑ EC DHt H , $ EC BEO( J , T EC BGED K 8j EC @ H 5 EC g A ȉ 1 EC c A , EO E_ H a E 0 D- EC K F s E 4 L @ AC CF C I l E ( g EC BHa E ( \ EC EZ Y a L ( ܊ AG JK K tJ AF HDX E b N W I K L l L D L @ H K O ] K | L x H E y E $ ( EH BOv A 4 ̋ 3 AF v C R f f R | d ( EC BO A ( 0 <" EC DJ G ( \ @ EC M E ( EC P] K ( EC P` H ( EC PZ F @ AC BEF L i G r F m K $ P EC G A 4 x $ AC BEH& G z F , AC HK C ( EC Kg A , 0 EJ BGED B , < ( EC Mz A , l @* EC Mz A , + EC Mz A , ̎ @- EC Mz A $ . EH Q A $ x/ EV e H , H / EC Mz A , x t1 EC Mz A , 3 EC DH H $ ؏ 5 EC G B ( 6@ EC DEH F $ , 8 EC G] D 0 T 8 AC BEEED? H , T: AC HD E , K AG FEDG B $ W EC GO B 4 |Wy EC DEED C L ( H Y EC K D t ZW EC ED A ZB EJ m A ( [ EC DI F {* ` E [k EC I $ ( \ EC I A , P \ EC FEH D !{ ( ,] EC BM E ̒ ] EC S ^k EC I ( ^ EC Kx A , < P_% EC I B l `dA EC p D $ d AU Ce A , d AC M G ( fJ AC K I , g AC Y: I @ k EN A , d l AC BGF A , n EC FJ@ H , Ĕ 8p EG FF H ( (q EC MN E , rO EC h F , P ,} AC HD A 4 } AC \ K E , d AC HH^ A ă_ EC O C , 8 AC Y; H ( < " EC eH K $ h EH G A , ̍ EC I A $ a EC o I P L 䏒3 EC c C 4 f EC DHg E A , @ <$ EC HH A , p < EG BJ] K , EC DEJH A З |p EQ T A ȕS OF x A ( a EF BEH F @ L6 EC h A , ` l- EF HD. K l EF A , EC M B 蠒8 EC c H < o EC BGEDt J Y E o A D 8Q EG A , d x EC DL A , ( EC BGO A , ę EC DL A , h EG It G , $ EC M A , T 角8 EI BGIH H ( EC M A ( EC \ E ( ܚ EC W@ A , $3 EC BEGH F , 8 4 EG DGH A , h F EC BIH C , = EC M E $ ț $6 AC VK K $ < AC L~ B AC HH D $ < P EC It E , d EC Ml A , X EC \ A ( Ĝ EC N J , Y EC BK B J ( 컒 EC E} F W I , L @ EC BKJ A y E | 8 EC f E ( ༒ EF EM C [ E ( ȝ DP EC K K he EC T D , EC Gf K \ A $ H 4 EC G A p EC k E EC n J $ EC Gn A V EE F A 8t EF c A ( EC A ( L P, EC W D x TÒ3 EC c C ( tÒ< EJ DK D , ğ Ē AH KLQ G ƒn EC s E (ǒi EC [ A $ 8 tǒ EC I{ E , ` ǒy EC BGEH B <ʒ7 EC c G \ʒ5 EC c E $ Р |ʒZ EC m K P E $ ʒZ EC m K P E $ ʒZ EC m K P E $ H $˒Z EC m K P E p \˒ AT F , H̒ AC BEHn G ( ġ ϒ AC DH4 D , |ђt AC BEEH# E , Ғ EC DO H , P Ԓ EC DEJ\ I $ lؒ EC G I , ْ EC M H ( آ ڒ EF I5 G $ ܒ EF G) E 0 , ޒi EC K A J ( ` ߒ* EF M G ( EC BON I ( dj EC Ev M T A @ EF BEEEK J L 3 M ( $ EC I , H 2 EC M D x 3 EC c C 6 EC c F M EL q F ؤ $1 EC c A D1 EC c A d1 EC c A 8 1 EC c A X 1 EC c A x 1 EC c A , S AC FJDZ F , ȥ $ AC BELK B ( EC Kd E , $ ] EC M F T 8Y EC F B ( x t EC M A , (n EC BELH E Ԧ x AC E 0 X EC FDW G B ( ( 4 AC FHu I , T AC BEELH F AC Q C $ EC BKf E ( Ч 2 AC K G , AC BEGD J , , z EC BHED G , \ EC FEDe D , AG BIEJ E ( 0J EC BED D TO EC E| A $ EF { J X A ( 4 EC BGDv E $ ` EC G C 4: EC c J ( T EC BH A ԩ 8D EC Eq A dO EC * F $ X EC l L P C $ D j EC l B i F $ l V EC l L P A $ HX EC q G P C $ ` EC w I P C $ X EC q G P C $ X EC o I P C $ 4 (X EC l L P C , \ `' AC \] C $ ` EC C E R F 0 EC G F \ A Z E , EC FF C $ EC Is D @ | 9 EC i C $ ` m EC IV A ( EC DFp F , ! EC FJ} K , " EC DIEH I X%Q EC r F 4 %q EC ES H X % EC t A ( | `& EC KA D &r EC E_ A ̭ @'d EC Eo D 'C EC El E , '> AC BEKh B D *v EN ] A ( h $+ AC dh H ( + EC M A ( l, EC DS H $ - EC I A ( - Eg K I @ .G EC y A , ` . EC BPM A $ |/ EC BHN H D0 EC l D ( ܯ 0R EC M F 69 EC g E , ( 7{ EJ DI A X T8F EC x A ( x 8 EC Aa F T A 8a EC v J İ 89f EC U D 9\ EF } H 9; EC c K ( 9> EC c N , H : EC BID A x :9 EC g E :8 EC c H , :& EC I E Y A , ;l EC FEHq D $= EC X H < =g EC U A ` =D EL m A ( > EC Ku A , p> EC FID H , ܲ A EC DO] H $ HX EC p H P C $ 4 Hn EC H H P A $ \ @IX EC q G P C $ xIV EC q G P A $ IV EC q G P A $ Գ IX EC v B P C , J EC FJ A , L> EE n A L L} EC X H $ p |LD EJ E0 D 8 Z! EC BJ D s M G I Դ ^? EG m A ^I EG w A ^ EI L F 8 T_ EF _ F \ _ EC [ E ,` EP p A ( ` EC M| G $ е d EC It K $ TgH EC Gr G |hh EC Ek H D h EC Ek H h Ti EC Eo D Pjb EC Eo D m^ EC Ei J Զ m EC EQ B ( TnE EC DLH G $ xrM EC A , D r EC DIEJ A t xs> EE n A 0 s EC G D t E ȷ DtC EF r A tt8 EC h C , t EC FJ A $ 8 $uk AC IF E ` lv6 EC h A vF EC x A vJ EC | A vV EH s Q ,wu EC C , xJ EC BGEK} B ( 4 y EC FJ~ J $ ` <{3 EC BJv F ( T|( EC FK J ( X~? AG DD B $ l$ AC J E ( t AC I C 4 4 8 AC M/ A U E , l AC G6 G H $ c AC [ T D ĺ ؈ AC J , AC FF F $ AE K H $ @ AE A D ( h AC DII G ( Hp EO I E 4 [ AC P{ A L 0 AC K K B F , , AC DP H , \ ` AC M G , AC DP A , R AC P A @ ༓ AC DKLH+ F E L $ 0 Lד EC G D X $ړ8 EC j A x Dړ EC E J ړV EI @ C , ۓ& EC HH A , EC DELG D , l EC FJ E P | B EC t A ( p EC M J ( EC K E , Ⱦ t ] A` BGF A , AC DPT D ( ( EF M D $ T AC I G $ | AE G E , X AC FJp D Կ H> EC l E , h AC \^ B , $ EC IS L C E ( T X EC BMN K $ t EC C@ E ( 4 [ AT I F , h$ EC FJ, D , & AM BGEO G 4 (S EH Ew E ( X (C EC K@ E , * AH BEFP J , x, AC DH| L | D , h-t EC BIH; J $ 0 AC G E , < P2 EC BGF I 4 l :T EC HH D E E , < AH DLl K , X> AH DLs D , ? AH DLv A , 4 A AH DEQl A , d C AC DL H , F AH HH H ( hG AH DJ C , Jc AH DLv A , N AH DLv A , P Q AH DLv A , ,U AH DLv A , X AH DLv A , ,\ AH DLv A , _ AH DLv A , @ lcS AC IK H , p pU AC M A , q EC P| D 0 l6 EC Mo L E , x AC P F ( 4 h EC M H ` ,B EC t A ( \ EC K{ J ఔ> EC l E $ AC Sr G , AC \z F ( $ + AC P F , P 4 AC DH A $ AC Sj G , $ AC FM4 E ( AC M H 0 x EC M H q G $ 8 $ EC L L R F , ` EC M: A ( Ô EC M L ( Ô EC My B ƔB EC t A ( ǔ EC M I ( 4 ǔ AC BJ` H ` \Ȕ> EC l E , |Ȕ AC BGJH A , ɔe AM DKDi F , <̔ AM BGEO A ( ͔C EC K@ E ( < ϔ EC FH E , h Д AM DLy I , є% AR DL E , Ӕ AC BN H , ٔI AC M D 4 ( ڔ EC Mr I 4 L ( ` ,ݔT EC K F ( `ޔ EC M L , Tߔ AC P" J , D EC DLQ G ( 4 AC BED I D > EE n A d { EG D , 4 EC DL E $i EC EI J p5 EC c E , EG DIN C , @3 EC c C L `3 EC c C l 1 EC c A ? EC q A H EC s H , EC FJ A $ p EC G A , $ h AC BIH E , T 8U EC M H h1 EC c A 3 EC c C B EC t A ( AC ZX J $ EC BRw E $ 8 t AC V G , ` , EC BN E ( ] EC I G 4 P EC MJ A q E ( 8c EC M E ( | EC Mv E , L `#! EC FJ A $ | `$ EC t L R A $D EC o H $3 EC c C , %: AC M2 A '; EC i E 4 8'> EC l E , T X' EC M D ( EC E F t){ EF Ee A $ )b EC u C P M , (*~ EC C@ E d E , $ x*5 EG HEq F T .e EC } K t .I EC q G $ / AC UD C ( /z EC ED O T A $ D0 EC Ij E $ 1 EC I G , 8 1 EC M E ( h 3* EC KE H , 5* EC P F , 8: EC ME F , :z EC BJO# A $ <d EC EQ A ( H T< EC E\ G T A , t <2 EF DND E $ > EC U E 4 ? AC M3 L k A XA EC S $ A AC Et C H B AC Tg A l CQ EC { E `CP EC D CT EC EA A Ca EC I G , DP EC BIK A ( $ 8E EC MT G , P E; EC BIIJ C , F EC BJ A ( H EG M E , `J EG M5 B , L. EC HHH H , < N EC | T P X P N , l `O EG GX E ` H , P EC BLEHc J $ Q EF E D U EC A $Vd EC S D ( < pV EC ES H l E h VH EC z A WZ EK AC A PW EC A A $ X EC BD A $ X EC I A lYt EC G A D Y EF J K h 4Z EL p N , ZW AC DJF A , \ EH FKg K $ P^ EC Iz E , _ EC HD B $ D hf EC Io H l f\ EC I $ g EC } K S H , g EC DH' E k8 EC c H (k EC v A ( kl EC v i , H k EC DKN F ( x ls AC M F n? AO o EC g A o2 EC d A oQ EC z F $ oQ EC z F D (p3 EC e A d Hp3 EC e A hp2 EC d A p6 EC h A p4 EC f A pT EC z A qT EC z A $ Hq5 EC g A D hq5 EC g A d q2 EC d A q4 EC f A q6 EC h A q8 EC j A r5 EC c E , (r EC FJK A $ 4 r EC G H ( \ s EC DID E t5 EC c E $ t AC G~ G , uH EC FJ K z ( v| EC BJ G ( L w EC K D ( x x EC FD~ H $ HzP EC C{ E $ pz EC I H {5 EC c E ( { EC EK H | A @ || EC E A d } EC E B }6 EC c F , }z EC ML A $ D AC Ib A , e EX MEH G 0 \s EE ` D T ; EC m A t ؤ AC QH C dU ES Er A , EC I E Y A 0p EJ MN A ( |Z EC M C < 8 EC f E , \ Ч EC BGGM K : EC c J ( EC BQ B ? EC q A ( EC Mu F $ (c EC U A $ H t EH G\ H $ p ܪ EC Is E , D EC I E Y A ( 䫕 EF BK A , EC DH F ( $ EF BJJ A P 5 EC g A p ܮ: EG h A $ EC C{ J ( V EC DHO E $ Ȳ EC Ga H @ EC | D 0 쳕 EC A T x' EC A , x EC w Q P P T L 0 EC K D v E , `ʕx EC FJt D Еv EC h A , 0 ѕ: EG M` G ` ,ԕ9 EC c I Lԕj EC A G ( ԕq EC K E Օ~ EJ S N , X֕+ EC M A $ $ Xٕ EC C A $ L PڕY EC CH A t ەs EC e A ەs EC e A @ܕs EC e A ܕ EC q A $ ܕ EC C A $ , ݕY EC CH A T (ߕs EC e A x ߕs EC e A ߕs EC e A <s EC e A ( EC K E $ <w EC E` E , 8 EC FJ+ E h $I EH t C TB EC r C , AC Y H ( t^ EC BFo A , AC BEEJp F ( 4 EC DFHq E , ` EC BEEHD E ( AC FK A , 0 EC DEO A 3 EC c C , EQ ^b J , < EC G~ C o I ( l 0 EC Y E , o EC e A , $ EC BEGM J O EC r F < EC n A 8 L EC Eu E \ ? EC q A , | & EC BID E 1 EC c A , @ AC DO A , $ EC BEGD E , , EC FGM G $ \ EH GU G , EC i E , +, EE Ih E .9 EC c I , / EC P[ E ( 4 h5 EC K E ` 6a EC H H X6: EC c J , 6 AC Y$ G , 8 AC Y! B $ h; EC UZ I , , 0< AC BN` D ( \ = EC BVI G ( ?@ EC P B ( AA EC W D , B AJ FER F \D7 EC c G ( 0 |D EC DK| E ( \ pE EC M G , dF EC P+ E ( H EC BLc A ( hH EC K A ( I EC BK A ( < Iz EC Ey J d A ( h I EC DMr E , J EC HK D , L EC HI I , L# EC M A , $ O EC P B , T xVA EG P6 F , YY EC FN7 A , Z EC P G $ \d EC r F X G \: EC c J , ]: EC c J L ]: EC c J l @]: EC c J `]: EC c J ( ] AH DI E ( _ AE BM F ( _ EC Gh I ( 0 |` AC DEH E , \ `aL AC HD C ( d AC BJ A , de AC DGD K , Df AC DEIH E ( g AC DH B , D Hi AC HHI C 4 t k AC DEJ E { M m EC A I , |nx AC DGGk G , pX AC Y K $ 0 r EC I] B X sJ EC x E $ x tD EC I H , <u AC M= B , v\ AG FFC I {1 EC c A , | EC DEELk A , P | EC FEK+ G 쀖b EC EK E 8g EG EI A , EC M I , t EC MO D ( ( EC Mo D $ T h EC j N ^ E , | > EM DH G , i EH HI F , @T EH DM F ( p1 EH DKr B ( 8 EC K E , d h EC MI A $ ȝ EC I A , R AC FJ C , П AC I= F , 0 EJ HLH B , L k AK I G , | ` EC G E Z N 01 EC c A , P EC BL G , EC DJ< F , , гZ EC P I $ \ EC I A $ EC I G , ` EC BID F $ ༖ EC BHj D , X EC P I ( 4 ޖ EC DH[ A , ` lޖp AC BHEF K , ߖ AC BEFJH E ( \! EC FH` J , ` AF DJEy E L EC y F , < q EC P D ( l p EC BEHK F $ EC BH A ( g AC M D ( EC Iq F , EC BEEH C ( H 4 EC Iq F ( t EG I F L EJ EK A , P EF DEEHQ F ( EC Mw D , L EC DIFP E , P EH FLK F ( EC I H , AG P I ( EC IJ E , D AC DN H ( 8 AC BO B , d h EH DEF E $ . EH BK C , EC BJ{ I c A $ k EC C} H $ 8y EC C} H $ < EC Cz K $ d EC CB C $ ` EC BHz D $ EC I F p R EH Ez A R EH Ez A $ S EC E@ A $ H $ EC EW D , p EC C\ I W A , ` EH EA A $ h i EC CT A ( EC BIb K $ $ EC EK H $ @ V EC EF E ( h ! EC PM K ( #? EC PL D )y EH EZ D $ 8* EC G| E $ * EC G{ F 4 (+{ EC Ew D ( X +i EC G{ F $ , EC CR C ( - EC GE D ( t. EH FL A ( (/ EH FL A $ 0 / EC ER A , X 0 EC DEM A , d1 EC HH K $ $2c EE CP A $ l2c EE CP A , 2 EC FF_ E , 8 $5 EC DHKw A h 5F EC x A ( 5 EC DJOo A $ H6q EC CY D 6 EE Ah A , 6 EC BQ J 0 ;I EC { A P ;B EC c R $ p < EC EL G ( < EC DHEh G < = EC DH J x H } K h H , > EC BHG G K A , 4 8?r EC BGMS G d Bt EG Aa A Bg EG IL A 0CB EC t A `CB EC t A ( C: EC BF H $ D EC C^ G , @ <E EC BJX D p Fa EG IF A ( HGM EC I G ( lH EC DFk A ( H EC k E E dJ6 EC c F $ 8 J EC Gj G $ ` KJ AC I A ( DL/ EC W F ( HMj EC E| G T A , M EC I I ( O AC DD D ( < Q> AC I A $ h SQ AC I D ( LT EC IM B 4 Um AG C K g I s E , (W~ AC FED| E 0 $ xYA AC BIL A | , X Z AF DIEH H , \ AC Pp A , d` AF I0 H $ e} EC Gh A , \e1 EC P C , @ 얗- EC M A ( p 엗 EC M A , ` EC BNg A / AF @ I 6 EC c F ,M EL q F 0 \M EL q F P M EL q F p L EC z E , 죗 AC P D , EC BEGDr D = EC k E A EC k I ( 0 L EC K A , \ @Q EC DEEH A $ p EE GU A ثP EC j F , EC HHR F ( EC M| G ( 0 Lb EC Eu F T A ( \ b EC Eu F T A 4 Բ EC DEED] I _ A , L AC BIKH J ( ? AC BED H ( / AC BED E $ H $ AC BD A , p 췗 AC BEEK A ( ̸ AC BEK A , AJ FGM? L , p EC FM K , , EK HR8 A \ ʗ3 EC c C , | ʗ EC Y, C pԗ? EF d K ԗ( AJ ( ԗ AC DMo D , 8 AF My C D ֗/ AC , ` ֗( EC DL A , ٗ^ AC P A ( ޗ EC DJH H ( ޗ EC BO J , ߗ EC BEGM K ( H EC BO H , t F EC DEJH D , N EC BGJ F , ^ EC DFLK F ( F EC DJH E , 0 v EC BGJH' F $ ` lW EC I A , EC DEJHv G D EC E F , 0 AC BJ E 0 EJ FH@ C ^ J , @ AC IA B \ L , p lF EC BEJ H 4 AJ BEGL K ` H ( 1 AC K A 0 V EC M H x H < 8 $ EC HDQ K I ` H ( x EC BO F , 8 AC HDt D , EC Y H Ăz6 , $ x6 AC FM H , T AC h D < x)* EF BGED| G H i G , h+= EC iS D $ x- EE G^ A , - EC i E $ L p1 EE Gu J t 2= EG i C (2c EC EP A , t2C EC BGED H , 4 EC DGH A $ 6 EC Gj A @ [6f EC ] ( ` 6 EO M I , 8 AF BIH J ( < EC M D , = AC FEDi A $ => EC G B ( @ D EC K A , l H. EC \ J , ^ EC HD E 2z 0 @e| EG BEEEK G | EC t D D (}L EC m A ( d X} EC BGHq F $ } EC GA H , t~ EC FES^ D , n AC BJF, F ( 4< EC MK H ( D HX EC I[ D ( p |8 EC I] B ER n A ( EC PD D , q EO HD` H EC D @ ܓ EC D ( d ! AC Y E ( AC W A $ 0 EC Ie J (J EC | A EG Ep A ( ( $ EC DE I $ T $ EC G C , | EC DH" J , ` AQ M4 A П? EC n D EC Ex K $ ܠ EJ G J H \ EJ C E l \ EJ C E ,[ EJ B E h5 EC c E ( EC BNHx H ( ! EC BNHx H , ,! p EC FEH} H \! 5 EC c E , |! 0 EC FEH} H $ ! Ф EC BH^ H ( ! x EG I C " ,8 EC c H " L EH A F D" (6 EC c F d" H EC s E " K EC Ex A ( " 䪘; EC FD D ( " O EC Yv I , # EC HH A 0# EC Em A T# Y EC K A x# Įa EC S A # l EJ ER A # \e EJ EK A ( # EC M} F ( $ |B EC IO H <$ : EC c J $ \$ t EJ u L P O $ $ EC GW J $ $ EM i U P T $ $ ( EC Iv I , $ EC BF[ E E $ ,% AC E A , T% AC P% G , % EC FJ: F ( % EC P H ( % EC M A $ & z EC Ic A 4& EC v B , X& EC r V P ` P V & Ø EC B & etz , & xĘ EC BEGD E & XŘ EH AF D ' ŘG EC y A $ 8' Ƙt EC CX E ( `' lƘ EC Km H ' Ƙd EC t A $ ' @ǘ EC Eb A $ ' ɘ EC L{ A ' ɘ5 EC c E $ ( ɘ EC BHX F $ D( ʘ EC U K P F $ l( pʘ EC U K P F $ ( ʘ EC Gk E ( @˘ EC Ei J , ( ˘ AC BLEEK D $ ) ΘG AJ BHt G , 8) Ϙ EC BEJM B , h) dԘ AC BIS D , ) Tؘ EG P E , ) ݘ EC DH I ) 4j EC Ex K $ * I EC G J D* 6 EC c F d* 5 EC c E $ * EC BHX F , * @M EC BJEM' C $ * ` EC U K P F $ + EC U K P F $ ,+ 0 EC Gk E $ T+ EG I C , |+ EC BJ E $ + I EC G J ( + 6 EZ DL A , EW Mp G $ $, x EZ J W P C $ L, EZ J W P C $ t, h EZ J W P C ( , EZ I E [ M $ , EZ C E , |a EJ EG A - AS A ( 8- T AC M F , d- ` EC BEEK C , - ( EC P A ( - EC M~ E , - EC P A ( . EC K F ( L. EC K F ( x. EC DOf A ( . EC DOf A ( . \ v EC BJ\ A ( . t EC BJZ A (/ R EM Eu A L/ @ D EC c T l/ p B EC c R , / EH BJID D / P 3 EC e A / p | EJ A_ A 0 < EC l C , 0 EC BHN H Y A $ P0 L EC j V P C x0 O EC E{ B 0 EJ A| D 0 l < EC l C , 0 EC BHN H Y A 1 O EC E{ B 41 EO Ej E X1 w EO ID G |1 EO IU F 1 \ EO Is H 0 1 EC IH G D 1 J EC x E 2 h EJ F N <2 z EJ e A `2 \Q EC x L $ 2 EU C G $ 2 D EJ C G 2 O EC E{ B 2 H EC Ap G $ 3 EC G{ F @3 , EJ Ak E d3 O EC E{ B , 3 EJ PU| A 0 3 EC M I j E 3 h EG | H 4 EJ Av J 04 | EW f F , T4 F EJ M$ A 4 !3 EC c C 4 8!3 EC c C 4 X!3 EC c C 4 x!3 EC c C 5 !1 EC c A $5 !6 EC c F D5 !1 EC c A d5 !1 EC c A 5 "6 EC c F 5 8"3 EC c C 5 X"3 EC c C 5 x"1 EC c A 6 "6 EC c F $6 "3 EC c C D6 "3 EC c C d6 "3 EC c C 6 #6 EC c F 6 8# I H PI & & #& 5& <& P& j& s& & ( ( "( :( J( _( u( ( ( ( ( ( ( ( ( "( 6( A( P( ^( r( ( ( ( ( ( ( ( ( ( ( #( <( U( `( y( ( ( ( ( ( ( ( ( ( ( ( !( ,( ?( S( g( {( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( )( 0( ( 8( =( C( N( _( k( x( ( ( ( ( ( ( ( 0( ( ( ( ( ( ( %( +( 1( <( ( H( P( ^( k( x( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( u( ( ( ( #( 6( 1( A( P( >( V( ( ( e( i( ( m( ( .) k .) ( k 1( ' k .) k 9 .) k ; .) k ; .) k 9 .) k ; .) k ; .) * k .) * k /) 8 k /) 0 k 3! +/) 0 k 3! </) 0 k 3! L/) 0 k 3! _/) k J i/) k J v/) k RB |/) ( k RB /) . k /) / k /) . k /) / k /) k /) k /) k /) 6 k /) 7 k /) k I /) k I /) k L 0) k L 0) k L 0) k L $0) k Q ,0) k Q 40) k Q >0) k Q E0) k Q O0) k Q [0) k Q d0) k Q n0) k R s0) k R z0) + k 0) k B_ 0) k B_ m( k 0) ! k 0) ! k 0) # k 0) # k 0) % k ( % k ( k ( k ( k ( k #( k 0) k 0) k 0) k 1) & k ( k ( k 6( k A( k 1) k +1) k =1) k H1) k [1) " k o1) k {1) k 1) k 1) k 1) k 1) k 1) k 1) 1 k 1) k 1) k 2) 2 k !2) k 12) k A2) 3 k U2) k i2) k }2) 4 k 2) k 2) k 2) 5 k 2) k 2) k 2) k 3) k 3) k 3) k ( $ k ( - k Y) ( Y) Y) k) k) l) l) l) 'l) 9l) Kl) ]l) ol) l) K' Q' p ң& _ Q' t ܒ& _ R' g & X #& l #& X PR' @S' l & X $& T $& 0_ `S' G @& $& S' T' l & X $& s %& 1_ T' %& l & 4_ $& V' 0V' s $& \ && V' f & \ & HW' l #& X W' c +A& _ W' 8Y' t L& X '& r ;0& X ''& f '& X XY' s D'& X Y' S && X Y' m && X Y' Z' t L& Y '& w K'& Y Z' s D'& Y Y' S && Y Y' m && Y Y' @\' t L& b '& w n'& b p\' s D'& b Y' S && b Y' m && b Y' ]' t L& ,Y '& q '& 8Y ]' s D'& Y Y' S && !Y Y' m && "Y Y' B '& %Y '& p !& $Y ^' _' t L& LY '& r ;0& HY ''& M '& CY '& s D'& @Y Y' S && AY Y' m && BY Y' `' t L& g '& r ;0& `Y ''& f (& \Y a' n (& pg (& R (& g Xa' v (& g (& m )& hg a' B )& g a' N )& lg a' S )& ig #)& E >)& jg (b' c' t L& h '& r ;0& hY ''& f (& dY a' n (& h (& N )& h a' R (& h d' v (& h (& @f' s '& h )& t )& h )& m )& xY pf' M )& tY f' i )& pY f' I )& lY g' g' i )& |Y g' h' i *& Y h' j *& Y h' (j' (l' e & \ & `l' n +& Z l' i )& Z m' a +& Y Pm' C s& Y s& xm' p n& Y n& m' t G' Y G' m' u & Y 8& +& +& Y +& o' o' Pq' i )& Z g' U-& l & Z $& v' 4& U& (& 7& 7& 7& & <& ~' p; (' p; 8 X' p; ' < G =& =& >& p; >& p; ' p; pF 8>& p; @' p; p J>& p; 0 ]>& p; p p>& p; h' p; O ' p; Y ' p; h ' p; pm ' p; 0r 0' p; v X' p; { ' p; & >& p; ' p; >& p; P >& p; >& p; Х >& p; >& p; Ј ' p; >& p; ?& p; ?& 7 4?& 5 ??& < C?& $& G?& p Ψ& e?& y?& ?& ?& ?& ?& ?& 06 ?& @> ?& ` ?& 0 ?& @ ?& K=& Т A=& 6=& +=& 0' 0 ?& p @& @& 0 W=& $@& O X' T x' , @@& Y Ђ' _ ]@& I a@& h {@& pm @& 0r @& v ' { 8' & @& X' @& 0 @& 0 @& @& P A& A& @+ 2A& I JA& H ]A& H ' pF s<& ; G ' G vA& Х A& A& Ј ' A& A& A& A& A& B& B& 7B& QB& 0 lB& @ B& 0 B& Ъ B& 0 B& 0 B& ' @: C& 7 H& lI& H& yI& I& .' I& I& I& I& I& I& I& I& I& J& J& H& +J& BJ& TJ& cJ& tJ& J& J& J& L& & U& U& U& U& V& $V& >V& XV& rV& V& V& V& V& V& W& (W& BW& OW& \W& iW& vW& W& W& W& W& W& W& W& W& W& W& X& X& &X& 4X& BX& PX& ^X& lX& zX& X& X& X& X& X& X& X& X& R& R& S& S& AS& US& lS& tS& S& ' `' ' ' ' [& [& [& (' [& [& \& (' [& \& [& 7\& C\& [& Y\& 7\& C\& k[& l\& h[& \& \& [& \& \& \& T[& \& \& \& [& \& \& \& \& G[& p' \& ]& [& ]& ]& \& ]& -[& -]& J]& R]& [& R]& b]& p]& R]& [& z]& ]& ]& [& ]& ]& ]& ]& [& ]& ]& ]& [& ]& ]& ]& ]& [& ' ]& ' [& ' ]& ]& ' [& ]& ^& ^& [& ^& %^& 4^& ^& Z& >^& J^& U^& & ' NZ& J^& ' k^& v^& @' ^& NZ& ^& @' ^& ' ' ^& NZ& ' ' ^& ' H' ^& NZ& p' H' ^& ^& ^& x& NZ& ^& ^& <Z& _& _& x& NZ& _& _& .H& `ڎ 9_& ڎ M& `َ >_& َ d @ .H& d P M& d >_& @ .H& P M& >_& , @ 9_& , P M& , >_& d .H& .H& , 9_& | x M& .H& >_& 9_& +A& _& Ey& s& |& Ⱥ' (' ' X' & {' 1& 8& G[& \& ?& 3& L& f& & & & & ډ& r& 0 ' 8 & @7 & 5 ' @3 ??& : & 0 8' . ˋ& . p' 1 _& j& v& & P P `- `C _& j& v& & @ ͘& ݘ& & & & F & p u& & P' & & C & E ś& & ۛ& ! & c & & ,& & 8& A& & Q& ,F' 8F' DF' 6' nF' lF' ~F' H& F' F' 4& F' F' F' F' W& b& j& t& {& & WH& & & & & Ƣ& Ϣ& ݢ& & & & & & & $& 1& ;& C& N& `v |& & $& & ]& s& I& ' f^& I' ' "& & !& ,& =& N& X& S=& ]& e& o& t& x& & & & & & & & & x& & & & Ũ& ' _& _& ɨ& ը& & & & & & +& +A& $& 1& =& & ;& B& M& e& |& Y& & & ^& 8& d9& r9& 9& x;& <9& z& k& Y9& w& & & & & s& & & & & ű& б& & ' & Υ& _& (' _& (' ɨ& Ψ& ը& 5& & & & (' & (' & (' & (' +& (' & (' & (' & +A& $& (' 1& (' =& (' & & ;& (' B& (' M& 1& e& F& |& (' Y& (' & (' & (' C& R& t& Ȳ& & /& G ( b& s& & & & S& & ȷ& & ( & ( 0( ( J& e& y& & & Ǹ& ݸ& & ` X & X e & M Pz & L y & `L py & L y & K & @K x & P J x & p J l $& 0 T z .& 6& G A& S N& `@ @G & R | \& ` P i& @^ F ] ݢ& a F & E 5& O Po t& N p & P `E pm & E @n & й N & PM @ & D C& Z & p [ & ` C & j ` & & & & : , 9 7 ? ? 7 `8 , 9 p? ? , @7 @7 + p@ P+ , R ( * , + ) 6 p( P4 * ) > ( 3 (' R& h& & & & & & (' .( .( & & .( & (/( !& =& S& j& H/( & & f^& "& ~D& \!& ru& & & * & & L& e& & & & & & & & & & & & ң& & & & & & a& & & & & & #& u& )& 3& 9& C& J& ' S& [& b& i& r& z& & & & & & & & & & & & !& D& & & YO& & & & & & & & & & & & %& 0& /& 9& B& J& I& P& W& ]& c& !' & i& q& {& z& & & & ?& & (& & & v& & & & & & & & & & L& & & & & & & %& /& 9& C& !& M& V& L& _& f& m& {& & & & & & & & & & & =& & & & & & +& >& U& l& & & && & & & & & & & & (& & *& & & & & & & & & & && +& 2& & @& N& ^& k& t& & & & & & & & & & & & & & & & & & & & & Y9& & & 1M& -& =& F& Q& ^& h& r& & '& & & & & & & & & & & & (& 9& F& T& b& o& & (& '& & & & & & & & & & & & & & & & #& /& 6& A& L& Y& k& |& -?& & & & & & & & & & & & & & & & & & ?& )& -& =& F& Q& [& g& p& (& & & & & & & & & & & & & & __& & & #& 1& ;& M& _& m& t& }& & & & & & & & & & & & & & & !& -& 8& ?& O& W& `& n& y& & & & & & & & & & & & & & & & '& .& :& B& N& Y& i& v& & & & & & & & & & & '& 8& v'& C& Q& [& e& w& & & & & & & & & ~& & & n& 8& F& f& V& s& & & & & & & Y9& & *& <& M& & & & & & ű& W& =& & & & & & & & & & & & & P 0f 8 P8 0 e p d @ 7 0 d nk& c& ' k& & & Q( & Q( & & & 0& M& Q( /tmp/perf-vdso.so-XXXXXX M& /tmp/perf-vdso.so-XXXXXX gn& & /tmp/perf-vdso.so-XXXXXX pn& & @ @ s& (' ' & & & ,& & ' & (' & & & & & & & " Yg& & & & & & & & & & & & & & ' Ȅ& ' & & & & ' & x' & {' & & & & & & & & & f<' & & %& )& ' ' ' ' -& *& ' ' ' ' q( ' ' C' 8q( ' ' ' ' (' C' ^' z' ' ' ' ' ' ' :' U' ' +' ` w ' ' ' ' ' ' 3! 5! 9! PS! V! `W! & / ' u& 3 ' 6 ' & ~' & yE' + ' : ' B ' J ' Q ' y! z! z! ! ! ! ' , ' @ ' ] ' w ' ' ' ' ' ' ( ( ' , ' @ ' ] ' w ' ' ' ' ' ' ' ' , ' @ ' ( ' > ' Y ' q ' ' ( ' & >& "9& ^& ' ' ' @ ' k& ' ' ' & ' @ ' ' & ' ' ' ! ! P! ! ! ! ! p! ! y' ' ' ' ' y' ' ' ' ' ' & ' ' ' ' -' 6' :' >' H' _' P' y' y' U' E' ' H' & ' Y' c' v' ' ' :' -' y' U' E' ' & ' ' ' ' ' ' y' ' :' +' ' !' & & ' ' ' ' ' ' ' ' ' & )' (' (' (' .' (' 3' 8' (' <' @' (' E' (' (' (' J' ' & & & & & ó& dz& ˳& ϳ& ӳ& س& ݳ& & & & & & & & & & & & & & #& (& -& 2& 7& <& ' A& D& G& J& M& P& S& V& Y& \& `& d& h& l& p& t& x& |& & & & & & & & ' ' & ' & & ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' $ ' ) ' . ' ' ' ' ' ' ' ' ' ' ' ' ' ' $ ' ( ' , ' 0 ' 4 ' 8 ' < ' @ ' D ' H ' L ' P ' T ' X ' \ ' ` ' d ' h ' l ' p ' t ' x ' | ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' $ ' ) ' . ' 3 ' 8 ' = ' B ' G ' L ' Q ' V ' [ ' ` ' e ' j ' o ' t ' y ' ~ ' ' ' ' ' ' ' ' ' & & & & & ó& dz& ˳& ϳ& ӳ& س& ݳ& & & & p ' x ' ' ' t ' | ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' # ' ( ' - ' 2 ' 8 ' > ' D ' J ' P ' V ' \ ' b ' h ' n ' t ' z ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' !' !' !' !' !' $!' )!' 0!' ' & & & & & ij& ȳ& ̳& г& Գ& ٳ& & & & & !' z& 5!' 9!' =!' A!' E!' I!' M!' Q!' U!' Y!' ]!' b!' g!' l!' q!' v!' {!' !' !' !' !' !' !' !' !' !' !' !' !' !' !' ( ' ' & & & & & ó& dz& ˳& ϳ& ӳ& h ' !' ( ' !' !' !' !' !' !' !' !' !' ( ' ˳& ϳ& ӳ& س& ݳ& & & & !' !' !' !' !' !' !' !' .' Y ' .' .' \& }& .' .' H1' `1' v1' 1' 1' 1' 1' 1' 1' 2' 2' /2' B2' U2' i2' }2' 2' 2' 2' 2' 2' 2' 3' 3' +3' F3' ]3' p3' 3' 3' 3' 3' 3' 4' 4' ,4' C4' V4' `4' w4' 4' 4' 4' 4' 4' 4' 4' 5' 5' `( ! <' !' <' !' <' !' <' !' <' !' <' !' <' !' <' !' <' !' <' !' <' !' <' !' <' !' <' !' <' !' <' !' <' !' =' !' =' !' =' !' =' !' =' !' =' !' =' !' %=' !' *=' ( ' /=' ( ' 4=' ( ' 9=' ˳& >=' ˳& C=' ˳& H=' ϳ& M=' ϳ& R=' ϳ& W=' ӳ& ]=' ӳ& c=' ӳ& i=' س& o=' س& u=' س& {=' ݳ& =' ݳ& =' ݳ& =' & =' & =' & =' & =' & =' & =' & =' & =' & & & & & & & && @ & Y ' & z' ' B& E& H& L& P& T& X& @ \& Ƶ& ˵& е& 0 յ& ڵ& ߵ& & 0 & & & & 0 & & & & 0& >' >' >' >' <' <' !' <' <' <' !' <' <' <' !' <' <' <' !' <' =' <' !' =' =' =' !' =' !=' =' !' &=' +=' 0=' ) ' 5=' ̳& D=' ?=' :=' г& S=' N=' I=' Գ& d=' ^=' X=' ٳ& v=' p=' j=' & =' =' |=' & =' =' =' & =' =' =' & =' =' =' >' !' P !' ` !' X !' ( !' h !' p !' ( ' ˳& H ϳ& @ ӳ& 8 س& 0 ݳ& & & & % `% P% % % `% @% `% C " @ + 3 7 @7 47 (7 m 7 ; ; c 1 @W 2 P P L) O > dO x @N I : D b < + < ; l h h h 2 @ L : y o l N `o o l l 4 ô Ć Æ O ؑ/ Æ 0 Æ v0 Æ 0 ` H 2 @ . < R' 8 >h' 1 : !V) B `dž ) 2 1 R' >h' ` L) ކ ݆ 6 : ۆ + ؆ Ն + І D N `φ B :+ φ !V) Ά Ά l ̆ z B ` S ` ) . ` P ` < 5Q L H 0 0L ( /L m " . P " ( 5Q * x $ 2 # K # =K # K # K `# + 0 E : b 9 a @7 l + `6 3 5 $ : 5 ' 3 T G 3 $ |w 2 ? 1 l @@ `S d P M + J J % : H J E G D = |w B `B l Y [ > [ [ ` ࣇ i W 2 L) Ĉ x I : @| s & + h N g g l e S ` P ʇ @LJ Ç + E 7 : > ` G ` ; |w O q l @Ї v ҇ x ҇ ҇ ҇ ô ҇ Y O ؑ/ 0 v0 0 އ h 2 އ . ݇ R' ݇ >h' `ۇ ڇ 1 `ڇ : ه % !V) ه ؇ B @ ؑ/ 2 . x 1 : ` ( $ 2 1 R' >h' @ L) 6 : + + ` D N @ B :+ !V) l z * + 1 0 0 / j ( W 2 Q I @H L : @A 7 l N 7 6 l `4 @ ঈ w + ` F 7 : 9 G > |w ` R q l ` X @ + B @ 7 : @ 9 @ > |w l `ň @ň ň Ĉ ô ш @Ո ? ۈ = ۈ I6 @ֈ N ܈ K @ P = I6 `݈ P ` @ P = P = @ @ P = ] t m Q P @ 5Q P 5 5Q ` T m H : x & U& @& -& & & & h& D' & D' Ҫ& & & & (& ?& X& q& & & D' D' D' ( ( & ߫& ū& E' & & l& )E' CE' X& ]E' gE' t& rE' ~E' E' E' @ E' E' E' E' E' E' F' F' %F' 1F' =F' IF' UF' eF' wF' F' F' F' F' F' F' F' F' G' V G N `R J J `R C @@ < < f & ^ & L' r & M' S & U' && U' && U' i )& Y Xj' m *& Y j' n *& Y j' v (& k' p i,& 0o' a >& Xo' b ,& q,& p ,& ,& t L& '& p 4& 4& t 4& 4& G 4& && 4& P 5& && 5& L 5& && v' T ,5& && 65& l #& w' s K5& 8w' u S5& hw' R Z5& w' W e5& w' B q5& x' Z 5& (x' r *1& Px' z 5& 5& I 5& x' 0 5& x' x 5& x' d 5& 5& a & 5& H !1& y' c 6& Hy' m "6& 66& q R6& y' S X6& j6& C v& 6& y' M 6& 6& @z' P 8n& & 0 SY& tY& lY& j& ( j& FA' j& ( j& XA' j& oA' j& A' j& ( j& A' j& A' j& A' j& A' j& A' j& A' j& B' j& "B' j& 4B' j& IB' j& ^B' j& pB' j& B' j& B' j& B' j& B' j& B' j& B' j& B' j& C' j& C' j& 0C' j& (( j& H( j& BC' j& \C' j& nC' j& C' j& C' j& C' j& p( j& C' j& ( j& C' j& C' n x % 2 E L & o H q V X ȡ o p o o o T 6 F V f v Ơ ֠ & 6 F V f v ơ ֡ & 6 F V f v Ƣ ֢ & 6 F V f v ƣ ֣ & 6 F V f v Ƥ ֤ & 6 F V f v ƥ ֥ & 6 F V f v Ʀ ֦ & 6 F V f v Ƨ ֧ & 6 F V f v ƨ ֨ & 6 F V f v Ʃ ֩ & 6 F V f v ƪ ֪ & 6 F V f v ƫ ֫ & 6 F V f v Ƭ ֬ & 6 F V f v ƭ ֭ & 6 F V f v Ʈ ֮ & 6 F V f v Ư ֯ & 6 F V f v ư ְ & 6 F V f v Ʊ ֱ & 6 F V f v Ʋ ֲ & 6 F V f v Ƴ ֳ & 6 F V f v ƴ ִ & 6 F V f v Ƶ ֵ & 6 F V f v ƶ ֶ & 6 F V f v Ʒ ַ & 6 F V f v Ƹ ָ & 6 F V f v ƹ ֹ & 6 F V f v ƺ ֺ & 6 F V f v ƻ ֻ & 6 F V f v Ƽ ּ & 6 F V f v ƽ ֽ & 6 F V f v ƾ ־ & 6 F V f v ƿ ֿ & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v & 6 F V f v ! ! &! 6! F! V! f! v! ! ! ! ! ! ! ! ! " " &" 6" F" V" f" v" " " " " " " " " # # &# 6# F# V# f# v# # # # # # # # # $ $ &$ 6$ F$ V$ f$ v$ $ $ $ $ $ $ $ $ % % &% 6% F% V% f% v% % % % % % % % % & & && 6& F& V& f& v& & & & & & & & & ' ' &' 6' F' V' f' v' ' ' ' ' ' ' ' ' ( ( &( 6( F( V( f( v( ( ( ( ( ( ( ( ( ) ) &) 6) F) V) f) v) ) ) ) ) ) ) ) ) * * &* 6* F* V* f* v* * * * * * * * * + + &+ 6+ F+ V+ f+ v+ + + + + + + + + , , &, 6, F, V, f, v, , , , , , , , , - - &- 6- F- V- f- v- - - - - - - - - . . &. 6. F. V. f. v. . . . . . . . . / / &/ 6/ F/ V/ f/ v/ / / / / / / / / 0 0 &0 60 F0 V0 f0 v0 0 0 0 0 0 0 0 0 1 1 &1 61 F1 V1 f1 v1 1 1 1 1 1 1 1 1 2 2 &2 62 F2 V2 f2 v2 2 2 2 2 2 2 2 2 3 3 &3 63 F3 V3 f3 v3 3 3 3 3 3 3 3 3 4 4 &4 64 F4 V4 f4 v4 4 4 4 4 4 4 4 4 5 5 &5 65 F5 V5 f5 v5 5 5 5 5 5 5 5 5 6 6 &6 66 F6 V6 f6 v6 6 6 6 6 6 6 6 6 7 7 &7 67 F7 V7 f7 v7 7 7 7 7 7 7 7 7 8 8 &8 68 F8 V8 f8 v8 8 8 8 8 8 8 8 8 9 9 &9 69 F9 V9 f9 v9 9 9 9 9 9 9 9 9 : : &: 6: F: V: f: v: : : : : : : : : ; ; &; 6; F; V; f; v; ; ; ; ; ; ; ; ; < < &< 6< F< V< f< v< < < < < < < < < = = &= 6= F= V= f= v= = = = = ? /sys/kernel/tracing & reeb & & gbd & cart & & X & J r r t 8& & pK' pK' pK' pK' pK' ,M ) 3 ) = ) F ) T ) ` ) 3 ) k ) 3 ) 3 ) 3 ) 3 ) ~ ) ) ) ) 3 ) 3 ) ) ) ) 3 ) ) 3 ) ) 8Y) l) l) l) l) m) m) 0m) Wm) gm) m) m) m) m) _s) is) ws) s) s) s) s) s) () c) g) ) ) k) o) s) v) P y) }) ) ) ( ) ) ) ) X ) ) ) ) ` ) ) ) ) h ) ) ) ) p ) Ű) ɰ) ̰) а) ) ذ) ۰) ߰) ) ) ) H ) ) ) ) @ ) ) ) ) 8 ) ) ) ) 0 #) ') ,) 1) 6) :) ?) D) I) M) R) W) \) `) e) j) ) 1 ) %) 2 1) ?) ]) ^ q) Y ) ] ) = ) ſ ) ) ) 1) K) e) * ) ) ) ˶) ) 5 ) з d @B @B @ @ ' d d d d d d & & ` & & ' & @ & 8M' & & ) & / & J & T & 8& n & & & & & [ [ [ [ & && +& 0& ' 1& cy& 1& cy& 1& 1& 1& Ey& 1& Ey& 1& & 1& 1& by& %1& 91& ' 1& cy& 1& cy& 1& 1& 1& Ey& 1& Ey& 1& & 1& 1& by& %1& 1& ' M1& ' 1& cy& 1& cy& 1& 1& 1& Ey& 1& cy& 1& & 1& 1& by& %1& \1& ' 1& dR& 1& cy& 1& 1& 1& m1& 1& :^& 1& & 1& 1& by& %1& q1& ' 1& dR& 1& cy& 1& 1& 1& m1& 1& 1& 1& & 1& 1& by& %1& 1& ' 1& dR& 1& cy& 1& 1& 1& 1& 1& 1& 1& & 1& 1& by& %1& 1& ' 1& cy& 1& nh& 1& %3& 1& Tx& 1& 1& by& 1& ' 1& cy& 1& zh& 1& %3& 1& Tx& 1& 1& by& 1& ' 1& cy& 1& Q& 1& 1& 1& Tx& 1& 1& by& 1& ' 1& dR& 1& nh& 1& 1& 1& Tx& 1& 1& by& 1& ' 1& nh& 1& nh& 1& 1& 1& Tx& 1& 1& by& 2& ' 1& zh& 1& zh& 1& %3& 1& Tx& 1& 1& by& 2& ' 1& zh& 1& zh& 1& %3& 1& Tx& 1& 1& by& 1& ' .2& ' 1& zh& 1& Q& 1& 1& 1& Tx& 1& 1& by& @2& ' 1& zh& 1& W& 1& %3& 1& Tx& 1& 1& by& R2& ' 1& W& 1& zh& 1& %3& 1& Tx& 1& 1& by& d2& ' 1& W& 1& zh& 1& %3& 1& Tx& 1& 1& by& 1& ' |2& ' 1& nh& 1& cy& 1& %3& 1& Tx& 1& 1& by& 2& ' 1& zh& 1& cy& 1& %3& 1& Tx& 1& 1& by& 2& ' 1& W& 1& cy& 1& %3& 1& Tx& 1& 1& by& 2& ' 1& u& 1& cy& 1& s& 1& Tx& 1& 1& by& 2& ' 1& ' 1& cy& 1& 2& 1& Tx& 1& 1& by& 2& ' 1& dR& 1& cy& 1& 1& 1& & 2& 1& by& 2& ' 1& nh& 1& cy& 1& 1& 1& & 2& 1& by& 3& ' 1& zh& 1& cy& 1& 1& 1& & 2& 1& by& 3& ' 1& W& 1& cy& 1& $3& 1& & 2& 1& by& )3& ' 1& W& 1& cy& 1& $3& 1& & 2& 1& by& 1& ' @3& ' 1& u& 1& cy& 1& s& 1& & 2& 1& by& Q3& ' 1& cy& 1& zh& a3& s& 1& & 2& 1& by& d3& ' 1& cy& 1& W& a3& s& 1& & 2& 1& by& t3& ' 1& cy& 1& u& a3& 2& 1& & 2& 1& by& 3& ' 1& cy& 1& ' a3& Ơ& 1& & 2& 1& by& 3& ' 1& dR& 1& nh& 1& %3& 1& & 2& 1& by& 3& ' 1& zh& 1& zh& 1& %3& 1& & 2& 1& by& 3& ' 1& zh& 1& Q& 1& %3& 1& & 2& 1& by& 3& ' 1& zh& 1& W& 1& %3& 1& & 2& 1& by& 3& ' 1& zh& 1& W& 1& %3& 1& & 2& 1& by& 1& ' 3& ' 1& nh& 1& nh& 1& %3& 1& & 2& 1& by& 4& ' 1& N& 1& N& 1& %3& 1& & 2& 1& by& 4& ' 1& dR& 1& u& 1& %3& 1& & 2& 1& by& "4& ' 1& cy& 1& ' 1& 34& 1& & 2& 1& by& 84& ' 1& cy& 1& ' a3& ' 1& & 2& 1& by& C4& ' 1& cy& 1& ' a3& ' 1& & 2& 1& by& 1& ' T4& ' 1& dR& 1& u& a3& f4& 1& & 2& 1& by& j4& ' 1& dR& 1& u& a3& f4& 1& & 2& 1& by& 1& ' ,& `M' l& M' & M' & M' & 8N' ܒ& xN' & N' & & o& N' & !& #!& 3!& P!& N' b!& O' (& 8O' (& `O' & k!& !& O' >& O' !& O' I& O' !& P' & k!& !& @P' 5& hP' !& P' & P' !& P' !& Q' & !& !& !& & !& "& (Q' ң& PQ' #"& Q' & 2"& ' O"& & l"& S & PV' && xV' && V' ? ? ? d @ d P d , P P , P , @ , P , d @ @ , @ , P d d @ d P @ @ , @ , @ , P , d d @ d @ d P d P @ , @ , @ , X .H& .H& w_& .H& .H& _& 9_& 9_& w_& .H& .H& _& 9_& M& }_& 9_& >_& P_& 9_& 9_& |_& .H& >_& [_& .H& >_& P_& .H& >_& G_& .H& M& ~& .H& M& }_& .H& .H& w_& 9_& >_& P_& 9_& 9_& w_& 9_& 9_& |_& .H& >_& P_& .H& >_& G_& .H& M& ~& .H& M& }_& .H& .H& _& X .H& .H& w_& .H& .H& _& 9_& 9_& w_& .H& .H& _& 9_& M& }_& 9_& >_& P_& 9_& 9_& |_& .H& >_& P_& .H& >_& G_& .H& M& ~& .H& M& }_& .H& >_& [_& @ @ @ @ @ @ P @ @ @ P @ @ @ @ @ @ @ @ P @ P @ @ P @ d d @ d @ d P d P @ , @ , @ , * ̀ ` mH& 8' ؇' N& ' (' P' _& Aa& a& Tb& b& ' -c& c& Х' Ȧ' ff& f& ki& ' k& & p' m& o& o& p& {r& s& ;u& gu& u& v& v& z& z& ){& U{& {& {& {& z|& ]}& ~& ~& & & \& & B& ,& O& & G& & & & & & +& 2& K& V& k& V& & & & & & & NJ& ܊& & ' 6& 8~' `Ŏ =& c=& v=& M =& X~' v=& A =& ~' v=& M =& ~' =& `% =& =& =& ~' @L E& `Ǝ E& f^& 'E& & 6E& ?E& r& mH& J& 8' K& ǎ $K& K& v=& 0 `' ǎ ' `' v=& K& ؇' L& Ȏ L& ' v=& L& (' v=& L& X' v=& ' Ɏ M& ' v=& @ ' N& P N& ' :O& (' p GO& P' T& ʎ U& ' - =& U& `0 -U& =U& @$ MU& VU& " iU& rU& U& U& p yZ& ˎ Z& Z& 6 Z& Z& `= & ' Z& 3 Z& ' `< Z& ' 7 Z& `P [& P O @O [& N -[& N G[& N T[& h[& M k[& [& `M [& [& M [& [& M [& [& M [& [& M M `M M `P P O @O N N N R @R Q Q Q P d G_& d P_& d [_& d }_& d ~& d o_& d }_& d ~& d o_& d w_& d |_& d _& d w_& d _& d _& _& _& 0Y Ua& Aa& P^ b& a& i pb& Tb& b& b& c& ' p Jc& -c& 0 c& c& p d& td& zd& d& d& d& d& d& d& d& d& d& d& Ie& Х' ze& Ȧ' 0 yf& ff& f& f& @ i& ki& i& ' k& k& & & @ m& p' m& m& @ o& o& 0= o& o& 9 Go& p& 7 r& {r& 0? ' s& J 3t& ` ;t& Nt& Q at& ot& @X }t& t& O t& t& N t& t& K Qu& ;u& a wu& gu& a u& u& `` /v& v& c v& v& Ph z& z& x {& z& P :{& ){& ` U{& U{& {& {& @ {& {& |& {& P z|& z|& ]}& ]}& ~& ~& ~& ~& & & & & k& \& z& & ' & p & & & 5& & ` R& B& H& ,& t& @ & & H' @ & & p' ^& O& & & T& G& & & & & & p" & # ÿ) 8% ̿) & տ) ( ݿ) x( '& `Î & Ď @T T T 0X Y pZ & ph 0b ` ` pi @` & ph 0b ` ` ` @` !& ph 0b p ` ` @` & ph 0b Д ` ` @` & ph 0b 0 ` ` @` %& ph 0b P ` ` @c @` .& ph 0b ` ` } @` 6& ph 0b ` ` y @` =& ph 0b @ ` ` u @` E& ph 0b ` ` q @` M& ph 0b ` ` m @` & && S & 2 ,& 3& S & 3 9& S & S & 4 @& I& O& 5 & V& S & 6 H' [& S & 7 &$& c& V& 8 P B K M G @ ? ? - .text .shstrtab .symtab .strtab .note.gnu.build-id .debug_line .debug_info .debug_abbrev .eh_frame_hdr .eh_frame 8 4 p h x l x& & p (& & & 0 & & & & & & & & & & 5& <9& & & & && & & & & & & ' & & #& 0& ;& 4& & & J& V& `& s& k& +A& q& ~& & & & n& n& kD& & S& s& ' *A' & & & [& & & & f& & & Y9& & & && & & H' & & & :& & ;-' & & & & & 0 8& 0' 0' 6' & H& & & & # j& m & # %($ & & @ p& # & # & P # 0 ` & (O& & |& & & ۜ& & Þ& S5' & p Ǟ& Ξ& Ԟ& nU& ۞& & 5& |& P & & `& & & P & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 !& 0 $& 0 ' 0 (& 0 ,& 0 1& 0 5& 0 :& 0 >& 0 B& 0 F& 0 K& 0 O& 0 T& 0 X& 0 \& 0 `& 0 d& 0 g& 0 j& 0 n& 0 r& 0 x& 0 {& 0 ~& _& & & & & & & & & & & & & & ß& ɟ& && ϟ& \& & Y& & ՟& ۟& & & & & & x& 3& 8& & :& & & & & & & %& ,& 2& 9& B& G& 0 & N& R& X& @ ` ' " @ P ` 0( ( (' +& m& Z& :& ?& `M K M L M 3& b& L K M L @L y' y' y' & P P 0 2 & p ` 1 & z / & z & )& y p % 5& Py Q& x g& px P y& 0x P & w Е & pw p & w P ( & u Д & Pu P & t Г & `t P & & v , & v + /& v ` * )& v ) C& @v =& @v ` J& r ^& s ! q& . & p @ - & & 0 & p P & p & p $ & `r @ & q p r & q & @q & q & P & %& @ ' %& ' :& p ~ P # I& `p @~ " N& 0 } Z& ` 3 & 0 x& p P h& o p 0 p& o P} & & & ?& R& D& H& L& Q& V& Z& b& i& q& w& ' ' ' ' ' ' ' ' ' ' ' ' @ ph$ d$ `d$ c$ Pi$ _$ p^$ f$ d$ P_$ _$ ^$ 3& b& $ $ p$ p$ м$ p$ $ @$ $ $ 5' 5' ! 5' !' 5' 5' 5' }5' q5' p% r% po% 5' pq% p% o% 5' r% s% 0p% 5' 5' 5' 5' 6' 6' 6' )6' 26' ;6' D6' N6' X6' b6' l6' v6' ! 6' " 6' # 6' $ 6' % 6' & 6' ' 6' 0 6' 1 6' 2 6' 3 6' 4 6' 5 6' 6 6' 7 7' @ 7' A 7' C 7' D &7' E .7' F 67' G >7' H F7' J N7' K V7' L ^7' M f7' N n7' P v7' Q ~7' R 7' S 7' ` & a 7' b 7' c ' d 7' e 7' f 7' g 7' h 7' i 7' j 7' k 7' l 7' m 7' n 8' o 8' p 8' q 8' r w& s 8' t 8' u "8' v 8' w #& x (8' y ,8' z 38' { & | !' } ;8' ~ G8' & S8' Y8' c8' j8' q8' v8' {8' 8' 8' 8' 8' ' 8' 8' 8' 8' 8' 8' 8' 8' 9' 9' $9' 69' I9' ^9' r9' 9' 9' 9' 9' 9' :' :' #:' 6:' C:' O:' [:' l:' w:' & 5' <' :' :' :' :' :' :' :' :' :' :' :' :' :' :' :' :' ;' ;' ! ;' " %;' $ 3;' % E;' ' W;' ( k;' ) };' + ;' , ;' - ;' . ;' / ;' 0 ;' 1 ;' 2 ;' 3 ;' 4 ;' 5 <' 6 <' 7 <' 8 <' 9 *<' : 1<' ; 9<' < @<' = F<' > M<' ? V<' @ ]<' C e<' D l<' J s<' K |<' =' & ' ( ' ' ' ' ' ' ' ' ' ' *' (' . @' P% ( V& % ( D& % ( @' % H( @' 0% A' A' % p( 2A' % ( perf event selector list object. perf event selector list object. thread map object. cpu map object. perf context_switch event object. perf sample event object. perf read event object. perf lost event object. perf throttle event object. perf comm event object. perf task (fork/exit) event object. perf mmap event object. & x;& & & 5& s& m& v& L& & & :& 8& & 9& 9& z& g& & 9& :& 8& 9& 9& & L& & n& z& & & #& & +9& & m& QD' 9& _D' 9& n& G' & gD' .H& (' 3 U& % nD' G' % `5 / 5 % % % L& p% ( ~D& % %G' * & % 0( @G' % P( (O& @% x( KG' % WG' gG' `% `/ @8 % ~D& `% ( rG' p% : / % % % G' % < / % @% % G' % / > G' G' G' G' G' $ G' G' ( G' H' 0 H' H' 8 #H' ,H' @ =H' 9& H MH' ZH' p eH' :& oH' zH' H' H' H' H' `% % / A G' G' G' G' G' $ G' G' ( G' H' 0 H' H' 8 #H' ,H' @ =H' 9& H MH' ZH' p eH' :& oH' H' % 0 @E G' G' G' G' G' $ G' G' ( G' H' 0 H' H' 8 #H' ,H' @ =H' 9& H MH' ZH' p eH' n& G' G' G' H' % 00 H G' G' G' G' G' $ G' G' ( G' H' 0 H' H' 8 #H' ,H' @ =H' 9& H MH' ZH' p eH' & #H' H' H' H' @% P0 @L G' G' G' G' G' $ G' G' ( G' H' 0 H' H' 8 #H' ,H' @ =H' 9& H MH' ZH' p eH' :& oH' Y9& & & #H' 3H' =H' I' 0% p0 P G' G' G' G' G' $ G' G' ( G' H' 0 H' H' 8 #H' ,H' @ =H' 9& H MH' ZH' p eH' :& oH' n& G' G' G' n& n& #I' % 0 T G' G' G' G' G' $ G' G' ( G' H' 0 H' H' 8 #H' ,H' @ =H' 9& H MH' ZH' p eH' :& oH' n& G' 9I' 3I' G' G' DI' >I' Y9& & II' p% 0 X G' G' G' G' G' $ G' G' ( G' H' 0 H' H' 8 #H' ,H' @ =H' 9& H MH' ZH' p eH' :& oH' _I' YI' n& G' G' G' 0' dI' RU& uI' I' I' I' I' GCC: (Ubuntu 14.2.0-4ubuntu2) 14.2.0 , I , zO , &" h @ , ' :n , , q , 3. r % , C2 s i , |3 t O , = ju , X o , e + " , u M , , P , * D , / = , , ] ] , , ( ` - , s . , P8 , p; , h$ h , % E , ' c , n x( c , % I _E > 4 l int 8 q d q s 1( ߂ 3j 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ DA `+ FF h Hj p Ij tУ J x xl MU N\ !F OK Q[ =@ Y s [e \o e ]F ^ L )o _t B `j by - + o < [ > 4 s ` j F > ( idx j ptr L p E ! nr j }G j & j Z4 T p Y 7 $T fd & j 'c { (c ! 4 E ! L !> DT e j X7 6 j T j s L > > c =L L j > ) L + L E L > ;T j N fda & Xfp 1 P fd j h j l Q j N 4 fda # h ,j d $ lj hM T fda l% X{ l0c Ty mi Harg n L @ fd pj h nr p j l i j L T [j L fda [- Xpos [6j T [K H1 ]T h ^j d Lj K = fda L" Xfd L+j T{ L5c P LQ^ L pos Nj l (, FK + h fda F& h ?wK D fda ?$ h Ŵ / K g }G /"j \& /0j X fda 1 h )Q j I + d fda # nr ,j p Y h}G j Li 2 P 2 XZ4 T ` I L fda $ h& -j d & zO I 4 l 'int 8 c c d c ( \ G ) G G U c c s _E G 1 ߂ 3\ 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ D `+ F h H\ p I\ tУ J o xl M9 NN !F O Q =@ Y { s [ \ e ] ^ )o _ B `\ b *- + o G s G N 3G 5#G 58 6#G 7 i ( \ . @ \ @ Y \ " U # U $L g 5 \ +( C E X F G c G ' u H & , x # 5 $ e % ) & ( ' 0 ) 8z * @ + Hg , P - X G -@ 0 + m j v !G 7 $j fd & \ 'U { (U io ( fd \ @ buf end < \ eof $ e G \ 1 + 6 ( G H ?( S G C JS ~ G n { R~ & V fs H[ a \ G ] 9X ^ _ `j @ O H O O @P 5 P Q 9 z \ ! n m \ X7 6 \ * \ 6 + G . ! / % - \ Ӗ R % \ / f \ i \ i \ T, s \ !2 Ԩ \ \ C \ \ G ! \ _ \ ? G 0' E ` @ w + ! G } \ \ ! # \ ' " \ ; \ 3 \ N " m \ 1 8 \ :h 1 " _A -\ _9X _ _ #G \ g i - " _A /- _9X _L _ \ f w 1 " _A / _ io j _ bf _ ret \ _9X _ _ G \ Ke 1 ! _buf / _ < _9X _ _ \ d 1 ! _A -- _9X _ _ G \ hd . ' 1 ! hA <' ` \ :d . l 1 ! hA <' ` \ yc 1 - _A ' _ $\ _9X _ _ \ b Q 1 " _buf 0 _ = _9X _L _ q\ b q% A q3\ fd s\ err s%\ buf t G ? T \\ ` R \$ ~buf \5 ~ \B ~ io ^ j ~ bf _R ~ err `\ ~ b G W\ ` . W$ hA WB' ` M\ ` . M$ hA MB' ` j 6 \ _ d 60 A 7 ' 7'\ ~ 9 fd :\ err :%\ n %\ #_ %$ A %3- ' fd (\ err (%\ [^ & fs )& X h2out _ (] 3 | fs .& r @ | P $G H 3 ] fs 4 h \\ fs && h4 0& G Z p z fs )& A Pr z H $G @ Z D f h len ) ` J Z fs )& Xptr h = \ Y | Y fs ( ~ 1c ~{ ' ~ > X fs (& ^5 ^fp ^9X _ G c #G nX 3X ; 5 `fs & h W > z [ fs & h # W % fs & h W W ; `fs & h # BW > E [ fs & h " W % q fs & h W V ; `fs & h V > [ fs & h X jV % < fs & h UV V ; `fs & h U > [ fs & h U % fs & h U 4 gU ; a `fs & h )U > [ fs & h U % fs & h T T ; , `fs & h vT > q [ fs & h 1 QT % fs & h pQ n io /n ~ : ~ L ~ ^\ ~buf R ~ \ ~ ~h ~ ~ch \ ~5_ T j 1 V\ Q W io V+n X%:Q ret Y\ l /\ O @ $ io /.n Hn 1 X%P 7$ ` 6 4 G 6v "zO _ io "(n h fd "0\ d buf # X # @ ` i U h @ { _E > 4 l int 8 ~ > d q s ,! x U N ! # > DIR / E > 4 ? z j 2 j > $ e # L\ j j - j - 2 j F \ \ # t L m j # $ _ j > j k A N err (j ^buf 3 ^ ?2 ^sys ^a % ^ N ^ 4 _ ^ > { oj k o o8 X9X q hret rj d b\ :k P dir d\ `9X e h " ]k ] h S j n Q a S# X U ` Nj | N h D j n a D$ X F ` ?i ) ?# h u 2 i 1 mnt 4 h % i B D mnt ' h i Bi B s mnt h h H , h A ` ^ :n & 4 l int 8 c d c c s _E G G 1R ߂ 3\ 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ Dk `+ Fp h H\ p I\ tУ J j xl M9 NN !F Ou Q =@ Y v s [ \ e ]p ^ )o _ B `\ b - + o f G ^ s p G R @" 9" G % [ 1" E G s a G G ; \ w \" d" ^ \ G U" \ , ! G ^ \ y ! \ :n buf $ _" 0 _9" D _ fp _ _ len _ p _ 9X _ _ B q 2 4 l int 8 o s o v G 8\ { _ \ j 2 { 7\ { \ " \ q 8 t1 + _ 1 8 _ cpu \ _ o 2 r % S / " (E .# N ^ ^ 2 " @# " J# \# 4 l int 8 d s 1Y ߂ 3 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ Dr `+ Fw h H p I tУ J xl M N !F O| Q =@ Y s [ \ e ]w ^ )o _ B ` b - + o m 2 e s w 2 59 Y R " " " " HQ PQ ([ %$ t r r ^ {# qs A wY ) h> `" X " r 8 " ~ 6V ~err ~ 5 < s i f _E > 4 int _ s X l 8 X _ L > S ;$ 5$ L L 2 s i .$ L \ buf % PR$ 12 Herr L l $ t O " (A .# J Z Z . " @# " J# \# 4 l int 8 d s 1U ߂ 3 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ Dn `+ Fs h H p I tУ J xl M N !F Ox Q =@ Y s [ \ e ]s ^ )o _ B ` b - + o i . a s s . 55 U R H i m 7 kZ I c eA c K ld U d K Z - V ` U { !GE "h #y $W % & '[ (/ ) *H +3 ,_\ - .z /b 0 1¬ 2d 3{ 40J 5 6qM 758 8 k 9 :`K ;s <e <Ж = > ?B @!E AEQ B Cm D E/ FN| G H3 Ib3 J K, Lp M_ NN6 O P5q Qij ROD Su T U V`4 Wڕ X`# Yk Zn [ - \ي ]fO ^p _Uj ` aU b, c8 d"^ e| f gS hy i je' kp9 l m n?1 oDy pб qJ ri s\ t% u v3 w] x@? yF z} {? |D }B ~ h 8 nJ Q j b D & l_ ( > ~ Ho 5] p/ -j ) < Y g + Y ! =4 L! . 4 9 +z ,s E *3 Υ @I # > b vN 2 ` _ . t A J 6 l ^ V , >r ( Oi p] - . $ $ I $ % $ Y$ $ $ g$ U Z s s Z z$ I XQ % %$ t s $ "7u 3 fn "&I h $ Qt G - ~8 @ ~ 6V ~ " t 6 / l8 Q `6V s X -$ ju ./$ 5 u $ % $ Y$ $ $ 0int u ) s _E . 4 l 8 @' -. d 1{ ߂ 3u 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ D `+ F h Hu p Iu tУ J xl M N !F O Q =@ Y s [ \ e ] ^ < )o _ B `u b 1- +! o . !s ! . { 2R q) "cpu u 3 & ( - 4u A A A F 5F $ B' % % *& 5 u64 !S u32 $w u16 'k u8 *_ 6M C Nu : O ( / i' . x& .5 #) . ( 45 ) 5 R& 6 5 8& z h( 5 "nr u "map F 7. ) *5 H i m 7 kZ I c eA c K ld U d K Z - V ` U { !GE "h #y $W % & '[ (/ ) *H +3 ,_\ - .z /b 0 1¬ 2d 3{ 40J 5 6qM 758 8 k 9 :`K ;s <e <Ж = > ?B @!E AEQ B Cm D E/ FN| G H3 Ib3 J K, Lp M_ NN6 O P5q Qij ROD Su T U V`4 Wڕ X`# Yk Zn [ - \ي ]fO ^p _Uj ` aU b, c8 d"^ e| f gS hy i je' kp9 l m n?1 oDy pб qJ ri s\ t% u v3 w] x@? yF z} {? |D }B ~ h 8 nJ Q j b D & l_ ( > ~ Ho 5] p/ -j ) < Y g + Y ! =4 L! . 4 9 +z ,s E *3 Υ @I # > b vN 2 ` _ . t A J 6 l ^ V , >r ( Oi p] - . *5 / ' `) ( ) ' ) & @% ( ' ' K' #x . = u 8' O#I + < j < . DT e u $ 9 u $ +( < # +< < A . #; u :$ 2 > $ % I u ;' E j 5 + { < 1) < . & ] ] % C] & ] T' b P' u D i u j u k u @q& ] H ) ]' u c' u F ]& ] % ?] & ] T' b P' u L i u @ j u D k u Hq& ] X ! & ! . * a 9 P b W H? i u ` j u d e z z( K map > XRz l ) # r ; map > X cpu dRz h idx u l f* > m map ; h ) n 1 lhs n5 P rhs nU H nr pu d D idx | u ` H( i , }. i3 h cpu iI d ) Pu k }. P2 X cpu PH T low Ru d& R u h R idx Zu l) [ ` <9* K U map K8 h ) C V map CF h z) > > D map >G h % 9u , v }. 91 h (' - K J }. -> X idx -Hu TRz / l =% ( u 6 }. (: h * ] & 6 4 }. ] @$( . H* . Pp i u 0& u T' b Xtmp %b `' u >out $ ?( " & ( u 8[ ' u F P & u & ] R} ] T / }. ] P0& u T' b Xtmp %b `' u n u @cpu u u sep @E& A i) u D} ( u 4[ ' u H~ P & u L & ] | 7 0& 3u T' S & P}. ] Xi u Hj u L & . %&' { 8 }. G hidx Qu d %% | u { 2 a | A Xb |/A P' ~ `( ~% h ' q] { ) }. s] h .( d ] G{ Z }. f] `:' g h % J ] z k }. L] h0& Mu `% Mu d{ & i [u \ B& @dz > map @-] h ' 6] +z 9 map 6=] XRz 8] h & - py Z map -2] Xy ( 0u 0[ ' 0u hy P & 0u l ( #] >y 2 }. %] h ( ] x e 0& .u \}. ] `Rz ] h C8) x map 0] h0& 9u d %Z( "B x B map "E] h 5 P* x w r (B h #* y w r i y)5 r y8B old {5 Hnew {5 Dval {5 @ & '6 Cx - G `Q L] P i Cx , j \s T| X Ox h . r &' kiw G r k-B h X& . ( L v r L(B old N5 Hnew N5 Dval N5 @ p& '6 v - YG `Q L] P i v , j \s T| X v h w' ? 5 uv r ?< h A &M) :Rv # 6 r :-B hn :=5 d D) E u v E5 old E<u new EEu ,& u Z) u J- u ( & ( & ( & ,& Eo( ';v v ') hi '0u d ( u ju v / Fu __u d' u P X L G H | I__c J& p C res L< K Uu G e $ o " !"int > V s O 4 l 8 @' -. w d w }+ > O + a _E . # $ B' ~ % [ % b *& 5 u64 ! u32 $ & u16 ' 6 u8 * F $ M l C N> : OU l ( /[ i' .b x& .5 #) . 14 ߂ 3> 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ DM `+ FR h H> p I> tУ J xl Mb Ni !F OW Qg =@ Y s [q \{ e ]R ^ < )o _ B `> b %- + o H O g . @ s l v R O . 4 &R ( 4 ) 5 l R& 6 * pid * * 8 h( nr > * > map 8 G '. (' E h J J 5 J ) { < * + < < . +c =< < > . * b ( map b4 hidx b=> d + ]> # , . ]1 h ,+ W 6 Z map W3 h + P ) map PF h * C + . C= X i F> d ( H> <[ ' H> hݑ P & H> l -W+ > + - r+ -8> \ -K P . / hi 0> d * ( - map (5 hidx (>> d .>+ # / 2 map #7 hidx #@> dpid #K ` + t map J Xnr S> T h @ > d '+ ` map < X@ E> Tnr P> P h P* r ( h e #* y i y)5 r y8 old {5 Hnew {5 Dval {5 @ + & H - ` L P H , \ T % XL T Q h V + . ' kn G o r k- h & V . o ( L q r L( old N5 Hnew N5 Dval N5 @ + & - Y ` L P , \ T % XL Q h w' ? 5 z r ?< h M) :W # r :- hn :=5 d /) E > h v E5h old E<> new EE> & > Z) > J- > = & m L & r [ & w & | l P A 1 ! 0o( '@ v ')h hi '0> d ( > o ^ v /^ 1 ? __u ? d c p Pz X L 2 3 E 4__c W x 5& p C res L< 6 U> ($ + " N& 4 l )int 8 @' -C }+ X * _ s % _E C ++ r B' f $ j3 J % 5 Z1 X *& < - * u64 ! u32 $ s8 + , M [ C NX : OD =8 Y 78 Z Z g -( val ena run id >: .( / 0W3 1C K3 ( q) 8 cpu X 210 < jp R. + / - 3 0 :. m1 P- / 0 1 . . 1 0 , . 33 c 5 V p 8 . @ A1 BH. C`1 DH0 Ef, F2 G, H* It1 J92 K/ L. M/ N. O0 Q^- R1 S#0 T2 U1 Vz= Wq, X, Y. Z2 [@ \< ]< ^2 _= `W0 a9 b, c. d3 eY, f 0]2 4 8 @2 H- P/ X, \0 `1 h/ lo3 n, p|3 t0 x. ( 4~ ) 5 [ R& 6c 8& h( ~ nr X map % C 0 ) v *g , + }. - 0 4 . 5 fd 6\ , 7\ b8 8\ id 9 a ids : / ; . > X 5 E f .3 J f - L f idx M X * h( ~ nr X * X map 4a0 (\ ?, 1 Z4 - - 5y1 m ( $ e | C / 6 - `` ~ q X fd X cpu h( ~ $ @ $ end $ (9 ! f 0 " $ 87- #| @0 $ ~ H2 % P78 & X 3 ) 0 *X q +X * pid * C 7 < 0 ~ 0 * X X C & - :X c =~ = ~ X C A ] X ~ !s ~ y C C 0 2X X ` , 0 f | . 4 ;3 \ !/ f X X " % X (' 3 ( ( X % ;X C ( "W+ % "( " !_n C_ s _ & . \ X X 8 ~ {, ~ 9- U 0 ; X- f T12 H22 : o :- U L - h l- X - h+ 8X d 2 CX ` , ˧ = h . @ h q. 7 : h + X 3 f 1 X$ D Perr X hi X l .1 X Φ e , Xi X herr X l B1 X 0 # 0 h^3 ;X d T/ X 9 e q + Xi X herr X l / X 2 X+/ =X Tcpu didx X herr X l 2 X e 0 / h^3 :X d #g/ X p 5 Xioc X Targ ~ H^3 X P+/ X h * err X l #0 X x } ) 1 Xioc <X Targ G~ H^3 X P+/ X Dfd h H, X ) ^3 4X +/ EX 0 # fd 8 $ buf @ ;e2 n 3 n: Xbuf nFa P0 o& H8 q$ hn rX d #F2 AX ҟ A6 ^3 AAX +/ B X 0 B. D Pfd E X8 F$ `< Ga hidx HX L ), $X L $. H8 &$ h1 'X \ (X `nr )X d i0 ~ W 0 X^3 ;X T+/ LX Pfd h , X I e ) * 4X ret X idx X +/ X mp ` P fd @map Hcpu 1 / , X idx X `+/ X dg { fd h 1 9 / h^3 :X d }/ Τ = 3 + h #- o 5 _ - h ?/ % J . X5 6 idx X l <1 9 X^3 DX T+/ X d N fd h 2 qX \ ? 6 q) }. qE . r cpu t idx uX @+/ u X D err uX H=out l ' 9 , x @[ 'җ 9 ). " H[ ># fd X L6/ X (2 P 2/ W X W, X^3 W7X T+/ WHX P6/ WU H Y ` fd Z h 2 PX g H , P- hpid Q dcpu Q" `6/ Q+X \ RC P / H X S n H6 h+ HAX d 2 HLX ` , 4X P 4- X+ 48X T 2 4CX P a idx 9X `+/ 9 X d 7 fd = h 0 )1 6 ), h @- C u , < X ! h / * `, I Xidx X T $- &X xy &2\ h $- !X xy !2\ h 1 ~ S j xy 4\ hx ? `y I X $ 1 ~ M H xy 6\ hx >X dy EX ` ?- + " 5 h ) 7$ 0 M T/ 8.$ 5 r $ % $ Y$ $ $ 9int s ~ 4 l 8 @' -. }+ r ~ B' _E . $ % Z1 r *& 5 - *, /u64 ! /u32 $ :M ` C Nr : OI =8 Y 78 Z Z l l <8 ] E7 ^ b6 a 78 b 6 b ( / i' . x& .5 #) ., ~ + . N + a ;e $idx r $ptr < p C 5 nr r }G r & r Z4 p 7 $ fd & r ' { ( e .4 5 !4 L ( 4O ) 5 ` R& 64 q) v cpu r 8& h( O nr r map v [ %. <10 5 j R. + / - 3 0 ! :. m1 !4 P- / !i 0 1 . . ! 1 0 , . =3 5 V 8 . @ A1 BH. C`1 DH0 Ef, F2 G, H* It1 J92 K/ L. M/ N. O0 Q^- R1 S#0 T2 U1 Vz= Wq, X, Y. Z2 [@ \< ]< ^2 _= `W0 a9 b, c. d3 eY, f 0]2 4 4 8 i @2 H- P/ X, \0 `1 h/ lo3 n, p|3 t0 x. ]8 @k v id 3 G idx r cpu [ $ tid 7 (5 " 7 ,K #[ 0A. & 3 8 0 )G v *l , + }. -L 0 4L . 5 fd 6 , 7 b8 8 id 9 ids : > ;G . > r 5 E .3 J - L idx M r k v * h( O nr r * r map Q >a0 ( ?, 1 Z4 - - ?y1 ( 3 e @7 Z4 l 4 r 5 =6 *4 L >4 L . ("7 r 0A= 87 @x4 ! `", " `"4 # h"5 $ p"8 % x . - ` < q r fd r cpu [ h( O 3 @ 3 end 3 (9 ! 0 " 3 87- # @0 $ < H2 % P78 & X 4 ) & G r 3 ) 0 *r q +r ~8 , 0 3 r f5 .? D 0r b r [ (6 0 idx 1 get 2 , 3 3 ~ %. / & * pid 7 * %. A "5 0 < . 4. l- Xr N G r r z) ? d d W5 5{ $ > y ' ) r d [ 0 2r r [ * 7 r (' 3 [ d r , 0* Q /r E E r $ 0r o E o < t & E r < 8 6 8 r r r ' -r E r )Q 3r E r + r % ;r # d BT, s+ D r < ( !% P r 0 * r q r . ' .1 *r G T/ 'r G }/ G 2 r G L C < ( E 0 G {, < ]& *"L 7 L L + % M (W+ % + k ' )"L L f* W d 9* H d & ,"L L L (' !"L & . L ' E r #5 S 9 7 6 h QG ` 4 r < u 7 0 X G h 5 r d #6 D 7 2 X & E7 G h 8 ` 16 l 2 H KG @ G X n r T ~ 8 ` 8 h D6 F F 7 , hmap F `9 \ #9 k - 7 . X i r l 6 r 7 + * 7r mp H ops b P ~4 r b y E 7 / Hops #E @mp }. d X G P " 8 ` X 8 h b 7 | r S 7 |6 X"7 ~r l +7 ]r X w 7 ]" ops ]GE mp ^ r+ `r `0& ar d"7 br L cpu cr X+/ c r \29 & 3M5 w 4P U hr P 9 ir T . w 6 3r 7 3% ops 3JE mp 4 r+ 6r `0& 7r d cpu 8r T+/ 8 r X idx 8r \"7 9r H29 & 3M5 W E: U @r L 9 Ar P 4E U Jr L 9 Kr P . 4 r Ѽ ) e 7 $ ops IE idx r mp * 8 2r +/ r T P 8 (P "7 @P 6 [ G H7 r @ 8 X $ B 9 s4 D map `U P P fd r cpu r ҿ 8 h 55 > 7 = hmap W `9 \ 3 r a 2 map - hmp J `U r \cpu "[ X 6 u 7 . X9 ; Tidx Jr PG9 h )8 ( 8G Hidx Cr Dcpu Lr @+/ Ur sid X 3 \ e 7 F H9 S D i r \ map ` d h K7 r 2 * 7 + h 7r d 5 ~r 7 7 ~4 hb4 ~B d ) 8 u I A fda u:E Xfd uCr Targ v < H map x h 3 hr / 7 h1 Xfd h=r Tptr i< H7 i P i4 D pos kr l 7 Sr c x 7 S3 0& Ur Pr+ Vr T4 Wr L XG X U 8 Z ` ָ 8 Z h 65 'r q ; 7 '0 (G ^3 ) r +/ ) r fd )(r 6 +; @8 ,r id -3 ret .r Fadd N+ 3 K . #5 X 7 . h G `^3 r \+/ r Xid &3 P 17 < 7 5 X i r l )]7 ^ 7 6 H G @^3 r +/ r id '3 m7 r X sid `G& ͵ " & h & \ *7 3 4 * 7 2 XE7 G h 7 R e 7 / H G X C 8 ` 8 h m6 R 7 . H G X 8 ` 8 h 4 < T g 7 - H G XL E 8 ` n 8 h *3 r ! 7 + H G X err r TH4 + ó 8 ` 8 h G8 ( V! 7 0 h}. L `. X 4 в X ! 7 . h 5 Y w ! 7 , h 5 ֱ d" 7 4 pos G H n G P " 8 X B" 8 ` . 8 h I*8 G V " 7 ' H BG @ 78 G X " 8 h 8 ` *6 { M 3 +# 7 } h r7 t 4 f# 7 t. h uG ` %5 i k # 7 i+ h j G ` 09 _ 2 | W$ 7 _= aG H n a G PJ $ 8 e X ] 5$ 8 e ` 8 e h .9 $ $ 7 $? X %G Pv k 78 8G `Į 8 = h 3 f K % 7 , h J 1 < S M% xy 4 hx ? `y I X + 1 < ˬ H % xy 6 hx >r dy Er ` +87 s"G % 7 sI X 8 u h M) : # $& r :-$& hn :=5 d O ,o( 'x a& v ')a& hi '0r d ` +G4 6r ] & fda 6>E h K8 J > & -val J03 6v JB5 5S6 O ' n 6 Xh L' PE7 h 6 ' A' 1 4 h 7 d ) o' 1 d7 h 4 Wު "( W2 78 WK ( __u Z( `L( ( Z ( P ( X ( L MZN Z $__c Z 4 K . _( new K4 h ? KK ` ,8 &o A ( new &1 h ' `78 ( X ,- M " ( 5 h Ol8 ) -p >) -res G< 6 Pr ) P 2 i D$ X: 4 l Eint X > ,p 8 @' -C p d p }+ X F s _E C > d B' w $ % . % 5 Z1 X *& < 3@ , - *4 )u64 ! *; )s64 " )u32 $ *V )u16 ' *f )u8 * *v G M C NX : O ( /. i' .5 x& .< #) .4 C 1t ߂ 3X 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ D `+ F h HX p IX tУ J xl M5 NJ !F O Q =@ Y s [ \ e ] ^ )o _ B `X b H- +1 o C 1s 1 C t ;R :. ( m1 ( 3 P- / q 0 ( 1 ( . ( . ( 1 ( 0 ( , ( . ( 3 5 V ( ( 8 ( . ( @ ( A1 ( BH. ( C`1 ( DH0 ( Ef, ( F2 ( G, ( H* ( It1 ( J92 ( K/ ( L. ( M/ ( N. ( O0 ( Q^- ( R1 ( S#0 ( T2 ( U1 ( Vz= ( Wq, ( X, ( Y. ( Z2 ( [@ ( \< ( ]< ( ^2 ( _= ( `W0 ( a9 ( b, ( c. ( d3 ( eY, ( f 0]2 43 8q @2 ( H- ( P/ X, \0 ( `1 h/ lo3 n, p|3 t0 ( x. ( C 2i $C: j ( $,A k( $c: m( $h; n( $9 o( $> p( $< q( : g > h ( & I= @; $> < > = b b c >@ d L; e( < f( (@ ~ 0= 2? 4< ( 89 ( @ HY, Lu9 ( P*< ( X!= `!? ( ! > ( !9@ ( ! < ( !#A ( !@ ( (!-? ( 0!= ( 8 ' 3C ]A /_ 5 0 ? 1 2 z> 5 dev 6( ino 7( J$ < '$ '% '$ 'Y$ '$ '$ C C C C ( C + a -? ( M ' pid tid @ ( len ( : ( ( 3C 4 maj min ino ( : ! ( 4# `= $ Y, % o3 & 9 ' C 5 1 & & -n= H M ' pid tid @ ( len ( : ( (0 * @ + D , H > / M 0' pid 1 tid 1 * 2 @ 5J M 6' pid 7 tid 7 U> 8 ( > 9J _ Y C ? < M =' pid > = > tid ? ; ? @ ( 2: C M D' id E ( >: F ( d< K M L' >: M ( > 8Y M Z' pid [ tid [ A \ ( L; ] ( < ^ ( id _ ( (>: ` ( 0 : c M d' e ( id f ( ,= g ( -< n" M o' 0 p ( len q %; r s a t " 3 3C < w M x' 5 y z id { tag ~ -= M ' id ( 9X ; M ' 0 ( ; ? J z@ + M ' + ( : C 9 o M ' : g9 ; M ' , > nr cpu C r: nr SA q I< B nr SA = q + @ x* = $( * 5 "#? "; % ": % "Y; $B : 5 9 M ' < # @ " }. # E@ > - > $ - )" = a }. ( <C <C H? ( M ' 5 ( id ( E = H ; ( a C ? ? P B M ' = : #l M $' % 2/ < 0 1 < 2 }< 3 - 9 . &l C 9 $* M +' pid , 6 $ ' C ; 9l id : ( idx ; ( cpu < ( tid = ( 4< E M F' nr G ( Z4 H ' C > K M L' 5 M c> N p O + : 0Rv M S' T ( >@ U ( 9 V ( idx W tid X $ cpu Y (c> Z , 9 x_+ M `' 5 a y b cpu c pid d tid e fmt f ip g ( h ( ( msg i 05 j pK k t CA nq M o' -? p ( = q ( r ( @ u M v' pid w tid x ; { M |' } ( /; pid ( * L: 4 M ' nr ( Z4 '4 C C A m tag ( val ( ? M ' nr ( < ( C C 2 val ( ena ( run ( & W3 v; 0N M ' id ( cpu +/ a? M ' 5 ( ( d@ 8 M ' = ( ? ( 9 ( u9 ( *< ( (9 0> 1#= 2 L9 J M ' ; ( < = t M ' < K$ HX M ' , z= 1 * @ ! = @ Y >: p< # T, : @ bpf 3 < W0 % , "o T? # = ' %: )B 9 % @< l > # : 9 $v aux + @ #q ; & . : X: ! 9 ? "m I m? !N p@ @ $ ; !J 4( val ena run id >: 5( &X "W3 C K3 ( L* ( 4 ) 5 R& 6 q) 1 cpu X / = B MM M R - ` q X fd X cpu h( ; @ ; end ; (9 ! 0 " ; 87- #1 @0 $ H2 % P78 &M X e 3 )D 0 *X q +X ; < 6 + p C N + C =$ O P' E < 6'1 L X =0 6, 9 $ X X X >- X v ~ #% ?map ,M }@0 L#% }pc (% ~seq V }idx V }? V }= V }cnt ; ~cyc ; }< ; }u9 %; }*< 6; } ^ __u ^ `S2 G ]2 ~g2 ~s2 } __c __u `S2 1 ]2 ~g2 ~s2 } ( __c X __u X `S2 ! ]2 ~g2 ~s2 } | ( __c # __u `S2 K ]2 ~g2 ~s2 } __c R! __u R! `S2 ]2 ~g2 ~s2 } v! __c ! __u ! `S2 ]2 ~g2 ~s2 } ! ( __c L" __u L" `S2 ]2 g2 s2 } p" ( __c " __u " `S2 ]2 g2 s2 } " ( __c f F# __u F# `S2 ]2 g2 s2 } j# __c + # __u # `S2 T ]2 g2 s2 } # __c p$ = K ~@ f } - __u p$ `S2 T ]2 @g2 Hs2 } $ __c Qg $ __u $ `RS2 X r ]2 Pg2 Xs2 } % __c ( @ ; ~ A< 0; W m% low 2< h& 2< l AC> '; 0 ' % @C '+< \low )< h& )< l >J= % % ?map ;M XZ= % h t 8? % %' map <M = %' end ; < *' XZ= % H> X @ } ` >@ < len < cpy < Ddst P ' n> < t> < ; . (@ ^ = [' map -M h 7.> X % 9 ' map ,M h ,> X l Q( md 5M ? ; Pold ; X< *' ` C h X y ( X T[ ' X H n P & X L ? p X o $) buf p* Hq p3X D@ p>%' end pJ%' 9 r $) h > s; ` tX \+9 9) @& .( X P[ ' X . & X ' 9) C )) (< d r ) map d+M X old g; h ; ] 3 X ) map ]0M Xpc _ (% h 7 = X; ! ) map X,M h /x? S ) 6* md S<M h> SD; ` (8 Kn { u* map K'M h+ * & * C u* (W5 FK # * map F'M h (. 5 * map 5*M h 70 $X =+ map $'M Xmp $D=+ Pfd % X Lcpu % H S6= ' t+ map .M h (, \ j + map (M h ?M `9 \7- +1 P T> ; X , a '; Xb .V T= >< P P* I, r (I, h #* y J- i y)< r y8I, old {< Hnew {< Dval {< @+ Z- & , / - / `(/ L4/ P0@/ , #A/ \#M/ T#Y/ X0/ #/ h Z- C J- /' k G - r k-I, h+ - & - C - ( L . r L(I, old N< Hnew N< Dval N< @+ Z- & , / E - Y / `(/ L4/ P0@/ E , #A/ \#M/ T#Y/ X0/ Q #/ h w' ? < . r ?<. h /M) : # / r :-I, hn :=< d U) E X / %v E5/ %old E<X %new EEX . & G X Z) G X J- G X 8w/ & G / 8/ & G / 8/ & G / . & G / q a F Vo( ' / v ')/ hi '0X d ( X 0 v /0 0 __u 0 d,S2 ]2 Pg2 Xs2 L 9 " _ :__c /: D Y1 DH(% > E ; :1 __u G:1 `,!2 ) G+2 P52 XA2 L 9G" G( :__c G < 3; !2 3F(% 2 ? ; ( H __u ; 2 `,S2 D ; ]2 Pg2 Xs2 D 9; " ; ( :__c ; Bl8 M2 %p >M2 %res G C PX R2 WB& 2 %p C2 %res L C UX $ $ P TE _E : int 8 4 l s $ y s y : : 0 - ptr h y {, y # . h % $ D E 8 _E A int $ 4 l s a0 ( ?, 5 1 5 Z4 5 - 5 - 5 y1 ( A c = & H A {, < 5 ;3 f xy &f h oA G xy %f Xn 5 h . f D " "H \ ,H X1 95 P?, 5 `xy f h U & $ = sF 4 l int 8 _ _ s t _E C f $ < X[ A X r f ' E 3 < % ? X 9 z c X T, s X r A @ 0 fd @X lbuf @$ `n @0 X A ) M M fd )X \buf ) r Pn )* H A )3 @O + ` r U ret . h A $ 0 fd $X lbuf $ r `n $) X ion = < ~A < Lfd &X Hbuf 0r @n < A r `O X S & k i ret h e S C C M( 3dL G h 8 _E E 4int 4 l [ E (M a ^ a ` E NP a R E 2 d 2 V 2 5W 2 &N 2 E !2 * s * 1 'T b ʤ \ I 2 <] v v` $ E , R - QD / E 0 \ 2 L $/] 4 v (D 9 0D = 8 _ ? @I J; H<b K; XF L; h$[ Y2 x B E B " (X 6.# a q q E 7" @# a " a J# \# 1, ߂ 3L 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ DE `+ FJ h HL p IL tУ J xl MZ Nh !F OO Q_ =@ Y s [i \s e ]J ^ )o _x B `L b} 8- +% o @ _ E 8 %s d % n J E 5L , +R V ( _ 1 1 S 1 \b 1 B 1 +V S 1 h[ 3X 1 `[ 1) L E W W L h 1 h A f 9 9 jY jA 9 9 $O h^ 9 I LU L 6 b L 1 1 W TQ 9 8 1 9 I 9 ] 1 9 9 t 1 T 1 E 9 1 @P 1 L L 1 9l L O E L G L 6 : $ 1 L E 1 1 L }` L < ,cmd 1 7] L R @ < }arg 1 3 } s T2Q I' RU L . U} 1 L E B L - - _ - 2 c A c M V D X 5 r 5 U@ I L U} T| Q U| 1 /` - d 3- !7] L !_ - &Y O 1 TZ @-tmp y A C C A A E` Z U| T2Q ې& .y A * ( " U S & ;y X # # X " < . E # # g Us ] 7 U} b U| Ts z U| # Us x $ U} Q1 'R out B 9X .1 /buf 0E =S w - env y &M l@ # w S l%1 8 2 1c $ TUQ1 +X Y 1 E Y,1 ] Q 5[ [1 Uv t Uv Ts v R M C 9X M 1 >buf O `?- -tmp T 6 6 ( T 7 5 ^ U`T2Q & R (' YU U S & 4 4 Q J H @ 5 UU R 91 buf 90 sz 9<9 9X 9L1 /cwd ?1 R '1 buf '& sz '29 pwd ) !_ *b !0C *b a " L 9X ")1 &Y + y _ 1 X R 71 v r S 1 \b )1 1 $ U & TTQ1 '{a A out A#B add A41 tmp C Adie + ,err /1 S ~; T~B8 & E U 'X i '1 err ;1 S Hi msg n q 0E m L & G D 6 DT mL 'S m D m<6 _ ]L __s ] __n ]9 D ]6 D ]i ^ o 9 *_ o o9 TQ 9 m oX S 6 __n 9 |a oX S 6 (+ ~ D P $\ wC8 & I g $ " 3 - L F V UwT Q2R XUYT V c _ q o } T2Q x' R & Xw ( P > D $ _ C 8 ^ R 9 1 i a Y Eu v ~ ? $ ]$ ^ +0 , U| T 9 3 H T ` U| T} Q ] U & U} T| K U| T] [ U} T^ m GW | , * 6 4 m H | E C O M ( U| } "#Ts R } U| Us U I' U & T<Qs .y ( ( ? Y W g a O E V Uv T2Q| Rs (' s 0.( X_ g Us g Fy g E Uv T2Q| Rs (' s 0.( X ' ) y 0 ' # 8 6 B @ " E N J _ ] " Uv T2Q| R} (' } 0.( Xs y A r p | z " U S & 3 U} ( p F 8 w 8 " ) ) ] GSI SI 2^ ^ H/ 2X X > , 6dL 6 ] Q 0n _E > " (Q 7.# Z j j > 8" @# " J# \# 9 4 l :int 8 [ > (M ^ ` > ~ > NP R > d V W &N E ! } s s ;} 1 ߂ 3 6 s F 7 s 6f 8 s j 9 s 6 : s ( ; s 0!} < s 8lg = s @{C @ s H# A s PkX B s Xޮ D) `+ F. h H p I tУ J + xl M N !F O3 QC =@ Y 7 s [M \W e ]. ^ )o _\ B ` ba <- + o $ } C > s H R . } q > q 5E 'r 'R 'T ʤ C \ g = & > ?.h N f k dk Zk I <] v` $ E , R - QD / E 0 \ 2 $/] 4 (D 9 + 0D =O 8 _ ?[ @I J H<b K XF L h$[ Y x g / > s / @ ,! 7 ! } > ADIR ;d (len 2 a } B> j ( 2 (cnt 2 j y d : %d d ^ v 4 0 * z > c 4 q _c @ > %I LU v N q q > O E 4 v j 6 6 %2l *c U U 6 9 2 q q 6 q U" s q s q )( 2 2 CS s s q q q ) ' @P 1 H q Dl [ + w > 1) > Eh m *c $ *s 3q +i T Us Vj "f q $e 8 J > b { +i ,g F8 ,S s 3 + - W c T R ^ z U2T = & Q} R ^ ^ C g e q z U2T & r % z x . U- U: L U: = y Z q U} Z U U| Ts U z U2T J' Q} h z U2T ( r % . . , U- , : 8 U: - S e E C /5 U: Z } U} Uv Ts e ` $q V N $e v b l q S s H wi s ! 9X s N B i s y m Us Us Tv U| Ts Q} ! Us T: 4 Us Tv F U| Ts Q} P ) U h H Q8R p ` U| x Us U| Q} U T: U| T Q} U ' % U~ Tv Q} D Q8R \ U~ x t Uv / 1 UQTT 0c ` d 3 9X q q 1:l dir 6 D < de U g a 2buf s ~ tmp s W % f r U} T2Q 7 & R (' Xs H U S & e j = ! 3 ~y T} Z Uv + Us Tv / / ; { W T # Ef f r Y U} T2Q ې& R (' 0.( Xs j U , * ; 9 E C O M Z Us U~T~ $ &s " q - Us Z E Uv ; ] U| ; u U| U| M "k &q ext <q len 2 1f 2 "h a &q st N 0e @ ) d 7 h X g A "j !g ) - ) 2win j ? ; i j d j B n G z U2T s& m o ! ! 7 z z o I ! : T0Q: 7 r I ) ' : T0Q: r - U & L U & ^ U1T TQ @ 2 0 V z U2T & E C U: i #1f j , ws j1, s ls d H d H$ V N i H; ~ v ci J 2 cj J 2 ei J2 cmp K 2 . < r 5 Hlh 0 d 0 i 2 j 2 I.e ) $a_ )! E A $b_ )1 W S a + k e b , ~ J7 j P _ d & i y 7d r d # a 5q $len B2 + # ent Q K " o g * & UvT~ Q} R#| 8| #*( 8 ] ! # [ V U & w U| #e c #} num 3 #{a A out A#/ add A4q tmp Cs "(f 1 ptr 1$ 102 ret 3 Kdie ~ $err /q LS { ~ $ i T~M & H U #X 'q err ;q S H msg j } N> "f ( str (*q (;q e 7 oX S h 2 O W Peh q m & 4 D v ET t D t v DT m 'S m D m<v _ ] __s ]x __n ]2 D ]v D ] Qc R $ __c R 4~ p ~ l 3 wR & 4 . R P c ] | / UwT Q2R XUYT ^ ' T2Q x' R & Xw 4 5 5 S 3 0T !3 ] S T Uq 8 T0 U V.exe WSI SI &X X &^ ^ &c c 1 dL d` t 4 l !int 8 c d c }+ \ V c r c " s y ʤ .s q 1c #; v @ G Yz F & & + a 1 ߂ 3\ 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ D `+ F h H\ p I\ tУ J j xl M9 NN !F O Q =@ Y v s [ \ e ] ^ )o _ B `\ b H $- + o H G s / G r / R / Q %\ \ &\ b .h f 9 k 9 dk 9 Zk 9 ~ @ } } pid 5 in '\ out (\ err )\ dir *& env + Kz ,\ ( t -@ ` kt .@ a p /@ b 7` 0@ c Ax 1@ d b 2@ e u 3 ] 0| 5 8 & + '\ il L V ( _ & & S & \b & B & V ko \ [ w \ [ { & [ & U G 9| 3E `Q xq 4 [ (d d c 0 g \ \ & & \ u f \ \ q c c kx c . c } { \ D \ ~ \ Z \ { :\ p Lr \ / Wq \ ] )s / f \ \ } + \ \ \ 8\ \ & & Ao \ / & \ 0 * \ K \ G * wm ) \ b \ y & +u x\ L s z ,z H H ~ - W T0Q: $ b U & . s\ ~ G + #{ I& sz Jl P ( b B K U1 V / U1T TQP y Us T & U [ K U1 / 4 U1T TQP 9 b S U z & Y p Us T1 u Us T1 T1 K U2 U U T2 ` @ T / @'\ 0 B p p U1 U2 Z U [ D Us . UU 16s 6 w ! & in ' } r ( ~ z x __i *@ H{ * & __i +@ 2H{ + __d ,c __d -c B U1T}Q0R~X0 W U X & T S & Q0 w { P #{ & U p z B & U 3 \ 4eh & 5 J p p U1 U2 Z U [ 6SI SI J >5 UdL " ` - Se z 8 _E E Vint "L 4 l x )L "{ @' -E 2 d 2 W# # s " B' ~ L2 Xu64 ! # " " ( Y.# # '3 3 *E Z" h +@# f +" f +J# +\# , 1 ߂ 3L 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ D `+ F h HL p IL tУ J xl M_ Nm !F O Q! =@ Y s [+ \5 e ] ^ )o _: B `L b? h [- +6 o h ' ! *E 6s & 6 0 ' O *E 5 #[ 7r [ 7R [ \ & CL # ]8 f ړ t ޑ ɘ 8| f D E c Y 8 f & X ` : Ӈ @ D4 D 4 CL L p ,m `ap 5 b cL v d A e s f · g ʗ h ( jL 0 ku 8 l @9set mz H< n Pח o X " e ^L _ ޗ t ف , 0 9out 7] L L 9opt L ( " ,V (q _ S \b B 7V # ` [ H L L # 3 O E L L (y d L L [ c 4 L L U" ; L ( | W aQ Qc h E( 9 9 } ( + E (x c L L [ b ~ :Ӗ ʖ L :x o E L :d d 2 6 L @P 1 L W [ L L w E ( 9 L cl L E F - ( Q K p 2L v j E ʗ ) ! opt K I - [ S x . T| >. T| F - % p /L E E B 6 L s opt - V- T| - T| h p &L E < -p L , 7 r Gopt 1 UGarg T L G A ; r b ` L - L - r j Hopt U; Q D d; p; 6 T2Q & U; \ d; p; 6 T2Q} U; 1 l d; ( & p; 3 1 G 6 T2Q} < l < F D ,< Y W W W U} T| Q!v 4v #,( B w U| < < c a ,< m k w U| W U~ T| Qv < R < y u ,< w = Uv W Tv ] i U: $ $ Us T0 : $ Us T0 Z $ Us T0 I 1 <fmt / Jap O ~tmp : 5 F : : ; : U [ T2QQR~ Y G G 3 i v $ " . , . , [ C Us Tv Q0R0 G K U| e c U s 9 U R & I} ` " Y - ; 7 Q M Y f ; D i g c v } y ; x C UUTTQ0R0 U s L s< t! M t+L ctx u$ w 5 T opt T2 ctx TU i VL =arg Y s ) ); , +L +L ԗ +!L len +0L o , p ," opt - - W2 -( Hout P d L ` $ <va $ <vb 4 a " b _ Q sa L sb #L ret @L ; = L # KW __c L : v : 9 5 W ; = (L L D K __c (L : (: l f W la ! ~ lb " L >j b 4 M >L pos 9 pad L -b L , 7] L * h E (L $, UUTTQQR0XRYX -\ xL ` P ( 7] x"L " x5 x h h xP y # y1 L D yAL m ctx { Jbuf | ~ tmp b+ ^+ ; ! ! 5 e ; w+ s+ *; + + ! U} T2Q g & Rv " 9 U S & ( i L + + 9 ! % ] 9 + + 9 + + % 9 + + ; " 0 EG ; + + *; + + " U} T2Q~ R | v | 0.( )" U| 9 S" ; 9 + + 9 , , ; 9 , , ; _" K E ; %, #, *; /, -, f" U} T2Q~ R | v | 0.( X I& s" U| M# 7 i L F, @, 8; # v G; u, s, # U2Tv [ tmp , , e; " " ; , , *; , , " T2Q & M}# ( tmp , , ; }# }# ; , , *; , , # U [ T2Q & Rs (' s 0.( # Us ( y ( , , ( - - ( - - ( 3- -- m< ] |< O- M- < \- Z- < g- e- , 9 U J' 5( + % E( - q- Q( . . ^( =/ %/ k( / / w( L0 00 ( 0 0 .( ? /( )) ? ) ) 1 1 /) b ) Uv Q1 ) Q - ) 1 1 *) 2 n2 6) $3 2 C) 3 3 O) #4 4 [) 4 4 g) 5 5 s) O6 +6 .) .) /) f) E ) 7 6 ) 7 ~7 L9 / } ]9 !8 8 i9 +8 )8 u9 98 38 w q U} W Us T} Q~ < < Q8 O8 ,< ]8 Y8 w U~ W U} T~ < S% S% J < p8 n8 ,< z8 x8 L9 x% x% 3 ]9 8 8 i9 8 8 u9 8 8 % w U~ % W Us T~Q~ < & & # P < 8 8 ,< 8 8 & w . Us & W U c & Ts L9 & ]9 8 8 i9 8 8 u9 8 8 & W U~T} Q~ < U' U' / < 9 9 ,< 9 9 ]' w Us m' W U~Ts u& W X U} Ts Q~s * H Uv T & Q0 U; ( d; (9 $9 p; :9 89 L( 6 T2Q 0K' Rs Us T= 6 ) UTv P& w Us ( &! ( Q9 K9 ) k9 g9 < < ~9 |9 ,< 9 9 < 9 9 < 9 9 ,< 9 9 D W Ts Q~ U; o, o, d! d; 9 9 p; 9 9 , 6 T2Q J' Rs w |! Us , U )) + ! ) ) 9 9 /) '! ) Uv Q1 Y ~$ ~$ r L b" i 9 9 v 9 9 : 9 : : $ C U~T~Q0R g( % ) " N( ~?% w U0T~Q~R1 Y ( ( 6# i .: ,: v :: 8: F: D: U: O: /) C U~T~Q0R Y * * l J # i s: q: v : }: : : : : + C U~T~Q1R Y 6+ 6+ [ ) I$ i : : v : : : : : : + C U~T~Q0Rv n$ Us T & $ Us T & w $ U~T~Qs R0 w $ U0T~R0 ?# w % U~T~Qs A$ 1% Us T } & l$ V% Us T Z& % w % U~T~Qs R1 )& % U~ 8' w U~T~Q~ R1 ( O& (( : : < s< : : < +; ); < oJ U $ &3$| "T} Qv 9 " " < #' 9 5; 3; 9 ?; =; 9 R; P; ; " k E' ; \; Z; *; f; d; " U} T2Q~ R v 0.( X & " U ; $ $ j' < y; w; $ U: 8; + ' G; ; ; + U2Ts ' U # ' U~T~ #$ ( U , xJ # q L 5( ctx q6 ܖ L ( ctx 7 h Ň L њ L arg %k ]%H. e=opt i > ( ctx 9 7] L &L >V ) arg % h ? k L ) p k3 arg kB h l0 Æ n o ) o. pL * pL % u% %t = w xL Y L ) p Y4 h YL % [ h E L Q 8 ?p E. < ; ?opt F = = i F&L > = Os H ~@arg H > > P I S @ ? @err JL @ `@ - Omsg U 8 ~; h Y + ; @ @ ; A A ; A A m J U} TQ2RX @J' 9 r _, 9 0A ,A 9 IA ?A 9 qA mA 9 1 + 9 9 A A 9 A A !U; 1 1 d; A A p; A A J 6 T2Q & X} U; C, d; A A p; A A 6 T2Q + & X} !U; d; A A p; A A , 6 T2Q E & &; \; A A ; B B ; B B J U} TQ2RX & ( 1 Q× 8 ~Pi -B B ; G - ; |B xB ; B B ; B B J U} TQ2R 9 $ \ . '9 B B 39 B B ?9 B B U; : v +>. d; B B p; C C Z 6 T2Q & X} U; -. d; C C p; 2C 0C 6 T2Q & X} &U; )d; GC CC p; YC WC 6 T2Q & X} 9 B }0 9 nC jC 9 C }C 9 C C 9 @ / 9 9 C C 9 C C !U; @ @ d; C C p; C C Y 6 T2Q & X} U; !0 d; C C p; C C 6 T2Q + & !U; e e d; C C p; D C x 6 T2Q E & 8 0 8 D D 8 (D $D 8 ;D 7D 9 ND JD 9 &9< H< cD _D T< vD rD `< D D ' 21 @val D D 9 i o 1 9 D D 9 D D 9 D D jU; t d; p; 9 M 62 9 D D 9 D D 9 E D &U; d; E E p; &E $E * 6 T2Q + & X & 8 2 8 =E 7E 8 YE SE 8 uE oE 9 E E 9 E E / H Us T & Q| 8 2 !3 8 E E 8 E E 8 E E 9 F F 2 9 AF ?F 8 G (3 8 OF IF 8 kF eF 8 F F 9 F F G 9 F F 8 F \ 83 8 F F 8 F F 8 G G 9 ,G &G \ 9 SG QG 8 q G4 8 aG [G 8 }G wG 8 G G 9 G G q 9 G G 8 H4 8 G G 8 H H 8 "H H 9 >H 8H 9 eH cH 9 Q b6 9 sH mH 9 H H 9 H H 0U; & W5 d; H H p; I I ( 6 T2Q E & X & 09 " 6 9 9 I I 9 )I 'I !U; " d; <I :I p; GI EI 6 T2Q & X & &U; d; \I XI p; nI lI 6 T2Q + & X & 8 0 6 8 I I 8 I I 8 I I 9 I I 9 %J J F H Us T & Q| 09 O O - O 7 9 =J ;J 9 GJ EJ 9 \J XJ &U; O 0 d; oJ kJ p; J J w 6 T2Q + & X & R6 7 Us Q0 7 T~Q: 3 H 7 Us T 8 & Q| y 8 T~Q: 38 T~Q: ! H ^8 Us T `J' Q| |8 T~Q: R 8 Us T0 xJ 9 U J' ' 8 *E 1 0 L 9 p 0, opt 0D 1 L arg 1 2res 3 AM & L9 opt &- × &> &JL 1 9 str , = 2len " 9 1Ց L 9 opt * × ; GL A{a A9 out A# add A4 2tmp C kdie j: ?err / J J QS O ~K wB U: T~lw: & U U AX : ' err ; S H 2msg : ' : mE S L : __c L nl L ; & D D m L 8; & D ET tL U; D t DT mL ~; 'S m` D m< _ ]L ; __s ] __n ]9 D ] D ] _ AL ; __s A __n A9 D A Sc RL < __c RL 1f ( 9< str (* (; 1" ` m< oX ` S ` h `9 c 9 < oX 9 L 9L h 99 " " < oX " S " h "9 = oX S h 9 3$ @ wB / J J < K J I U $ p B < @K :K / dK \K I K K U K K U; p ( = d; K K p; K K 6 T2Q} U; C> d; K K p; K K 6 T2Q} U; > d; K K p; L K 6 T2Q & 4U; > d; p; 4U; > d; p; )U; 3 ? d; p; 8 6 T2 U; N N " ? d; L L p; L L p 6 T2Q & X (' U; z > ? d; 1L /L p; <L :L $ 6 T2Q & RJX (' U; V@ d; OL ML p; ZL XL 6 T2Q & )U; ] @ d; p; p 6 T2 4U; [ @ d; p; U; A d; mL kL p; xL vL 6 T2Q H& U; MA d; L L p; L L U; A d; L L p; L L 4U; A d; p; U; ! ! A d; L L Bp; & U: U; h cB d; L L p; L L $3 6 T2Q o& U: 3j: 0 ~ C : L L : M M N: wBw: & ~; Y } JC ; ;M 5M ; YM WM ; jM dM ; M M f J UwT Q2R XUYT U; f C d; M M p; M M 6 T2Q x' R & Xw xJ 3Y ` ( H i M M v N M _N [N tN pN N N U; ~D d; N N p; N N 6 T2Q & U; D d; N N p; N N 6 T2Q & U; !E d; O O p; O O 6 T2Q} U; < oE d; !O O p; ,O *O R 6 T2Q} ) G IO =O O uO ) O O 5 O O A /P !P K qP eP U P P a Q P m MQ ;Q .y V < =F < Q Q < Q Q < Q Q J Uv $ &3 5$| "TQ~ v $ &3 5$RIv $ &3 5$#v $ &3 5$#*( v $ &3 5$ < 5 BG < Q Q < R R < R R 8G U T m VG Q`R~ @ m tG Q`R~ { m U| T0Q`R ` EH !R R CR =R [R YR o jR dR H T~ ; .H T~ T~ t vH U: I H U: L_ p $ H U|T $ U|T 39 i oJ 9 R R 9 R R 9 'S S 9 I 9 9 _S [S 9 wS qS !U; d; Bp; & $ 6 T2Q & XT 0U; J d; S S p; S S $ 6 T2Q + & XT !U; d; p; S S $ 6 T2Q E & 5" pSI SI 5 Tis not available Tis being ignored 5^ ^ 5X X 0 ;< /dL f . 4 l 0int 8 c d c }+ \ \ G 1 ! s _E G 2+ ! 3 " ( 4.# G 5" Q @# @ " @ J# \# g % 1 ߂ 3\ 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ D `+ F h H\ p I\ tУ J j xl M9 NN !F O Q =@ Y v s [ \* e ] ^ )o _/ B `\ b4 ] 6- +" o ] G "s " % D G !D 7R D 8@ p ' '˨ ' 'Y 'U ' ' %~ @ j j pid in '\ out (\ err )\ dir * env +o Kz ,\ (t -@ `kt .@ a p /@ b7` 0@ cAx 1@ db 2@ e u 3 0| 5 8 9\ t j \ \ @P 1 \ D \ & \ \ & \ \ ' ''' %W W\ 5 5 B \ P j :l c \ \ y \ U" \ \ ; % X \ } +\ \ \ < @ Lr \ * D / f\ @ \ 6 \ V I \ 7 { T = $j S S opt .\ T S >cmd T 7 s - a !T T m 9T 3T y VT PT ? 7 ~ sT oT T T T T 18 F U K8 A cmd = j opt \ \ 7 ! cmd ' T T y \ T T 7 Us @7 UU { \ 6 z cmd * T T 6 M l U U +U 'U (M # DU <U / yU sU ); X < ~ H U U T U U *` 6 4 ? a ~ r 7 c # U U U U 7 T2Q & 6 T~Q 6 \ Tv Q0 6 7 Q \ 5 cmd 5 U U 5 V V ,V (V ( # GV =V / V ~V ); 2 < ~ H V V T V V *` 5 4 a ~ r 5 = V V V V 6 T2Q & 5 T~Q 5 Tv Q1 5 6 A \ p cmd 0 :p b p Rz \ +l \ y \ H + w e G B \ / cmd ) W V P \ $W W \ ;W 5W y \ \W TW u ~ ~ ī ~ !w ~C ] Derr \ W }W h4 h4 W W q4 * z4 * 4 4 W W 4 * 4 * 4 4 5 W W 4 * 4 * e3 4 * 4 * N2 N2 j W W W2 * `2 * 2 2 % Tp W W W W 2 > $ W W 0 W W 2 U b& T2 2 [ Uv T0 2 * Uv 2 2 ( ^6 X X X X 2 $ X X 0 3X 1X 2 U b& T2 2 ! Uv T2 3 * Uv 3 3 3 e >X <X KX GX 3 $ \X ZX 0 oX mX 3 U b& T2 .3 Uv T1 53 * Uv 3 W> zX xX 3 * 3 * 4 a X X '4 * 04 * ;5 8 X X 4 * D5 * 5 5 H X X 5 * 5 * '5 '5 D\ X X 05 * 95 * 0 s U0 %0 0 T1 0 * 0 0 y 0 Uv T= 1 c Uv %1 @ U~ 1 @ & U~ 1 @ ? U~ 2 * %2 * 52 * N2 } T1 o2 T0 w2 * E2 Us 2 P U3 : _3 P U 3 * 3 * 3 T0 4 / T2 O4 K U2T1 `4 5 * '5 O5 `5 T~Q {5 U & 7 to $\ ,fd \ 6 fd # Fdie err / S Q X \ ' err ; S H\ ,msg a r GG #DT m\ 'S mI D m< #_ ]\ __s ] __n ] D ] D ]\ #c 9 oX 9 L 9\ h 9 H2 + \ > + ʫ + \ - . C X X O w$7 & $+ & . X X X X X X Y Y . ( UwT Q2R X & YU r . (Y $Y 6Y 4Y . T2Q x' R & Xw / - / IY EY ~$ & / > U~.+ & .7 & / P U ISI SI J^ ^ 7 @ dL P8 c 4 l !int 8 c d c " s # H $ \ _E G " ( %.# G &" * @# @ " @ J# \# g 6 1 ߂ 3\ 6 F 7 6f 8 j 9 6 : ( ; 0!} < 8lg = @{C @ H# A PkX B Xޮ D `+ F h H\ p I\ tУ J j xl M9 NN !F O Q =@ Y v s [ \ e ] ^ )o _ B `\ b @ '- + o @ G s ' G ' (R ' il y old y n \ ( \ = I G ~ [ ) + G @P 1 \ ' \ 6 *l \ X \ +s /: ~ f /(= qY gY X : 1 i Y Y u Y Y Y Y : Y Y Y Y 5Z 1Z : p; U & ; U2Ts 5; [ ) U1Ts B; [ F U?Ts O; [ c U3Ts ,b; [ U=TU -~ "\ 0: X S sig "\ NZ DZ .s $S Z xZ F: %= Z Z / x: x: Z Z : U & TU c: UU I Ү \ sig \ f 0= s S sig \ (f 1 ptr 1$ 10 ret 3 0die 8 Z err /6 [ [ S * ~k9 E T~1g & u9 U X '6 err ;6 S H msg 2G DT m\ 'S m, D m<; _ ]\ __s ] __n ] D ]; D ] Z P8 ~ [ s 3[ -[ L[ F[ 3 w4g & y8 e[ _[ }[ {[ [ [ [ [ 8 & UwT Q2R XUYT 8 M [ [ [ [ 8 T2Q x' R & Xw 8 1 X 9 & i [ [ u \ [ (\ \ 9 j\ h\ y\ s\ \ \ 9 $: U & 9 Uv T| 5^ ^ 6SI SI C dL Ѣ V (g _ g g S g \b g B g t s m V " y Q 5D e p; 2 4 l int 8 @' -L h s B' o _E L $ % 2 - * u64 ! u8 * 9 z !L 7 $P fd & a 'Z { (Z l} io ( fd a E buf end < a eof $ e / f a a 2 a \ a T, sP % a { % 1 a X7 6 a V V a a P? 9 !\ arg 1{ W io # a bf $\ err %a @ 0 ch 1a i 2 @ 3 4m л a W { \ 9 m L ~ L ? 0 io $ Xch a l a > ? @ ! l > < 5 l fa = io f* Xhex f5 P h k= ch la l 1 Va k= W io V+ X= ret Ya l /a +< @ ? io /. Hn 1 P Xk< 7? ` O !L "v "; _ io "( hfd "0a dbuf # X # E ` # 9 2 ; . c 952 l $ 2 2 p; . c 252 l k xF l r + h$ h 4 l int X 8 s k 4 X 6 w H X r $ R X X 9 a 1 C a _ k @ k . f < w < X X i X M X 8% 7] X \ , Psec !X d ח $ ? b #_ \ a $ R E b !_ \ G h$ ? sig X \ G V + % E 4 l int 8 }+ X s r 4 X ? $ 6 ~ H X y $ R X X 9 / a 1 @ k / - 7 Sf x x X @ f i X 1 6 = X f < < X X ( X & ? 7] X \ , Psec X d & X & n sec X \ G % ? sig X \ YI V + ' c m int 5 8 4 b s [ l R 5 5 V 9 a V 1 q cnt < k ( i 5 # V { 5 ( x n 7] 5 \ + P 5 d c ~' ; ` W G' 7 K ' 2 J V + x( c 8 int $ 4 l s t { R < < 9 a 1 +_ 9 t #= t 8 t / 5 6 buf @ / ( 0 < x( c 7] < \ : P K m + % ) _E . nint oA )8 ) )4 s Ib )s 8l ) ) )l ) x )A * > ,M @' -. (M M d M }+ A V M r M A pI M E !M l *M O W + a l z > y ʤ .s ) | 8 i u + ! A !A { " 'i ! *. (ނ - 0 x y . . l . X 88 : ; M l . 7 > Y8V X" Y Z M , [ l . * I q 1 ߂ 3A 6 7 F 7 7 6f 8 7 j 9 7 6 : 7 ( ; 7 0!} < 7 8lg = 7 @{C @ 7 H# A 7 PkX B 7 Xޮ D `+ F h HA p IA tУ J xl M[ N !F O Q =@ Y s [ \ e ] ^ )o _ B `A b + r- + o + l . s l . 7 I Z HE i m 7 kZ I c eA c K ld U d K Z - V ` U { !GE "h #y $W % & '[ (/ ) *H +3 ,_\ - .z /b 0 1¬ 2d 3{ 40J 5 6qM 758 8 k 9 :`K ;s <e <Ж = > ?B @!E AEQ B Cm D E/ FN| G H3 Ib3 J K, Lp M_ NN6 O P5q Qij ROD Su T U V`4 Wڕ X`# Yk Zn [ - \ي ]fO ^p _Uj ` aU b, c8 d"^ e| f gS hy i je' kp9 l m n?1 oDy pб qJ ri s\ t% u v3 w] x@? yF z} {? |D }B ~ h 8 nJ Q j b D & l_ ( > ~ Ho 5] p/ -j ) < Y g + Y ! =4 L! . 4 9 +z ,s E *3 Υ @I # > b vN 2 ` _ . t A J 6 l ^ V , >r ( Oi p] - . B' O ` ] )? )$ 7 . )$ j3 % x % [ Z1 A *& - * 9u64 !Q 9s64 " 9u32 $ 9s32 % 9u16 ' 9u8 * 9s8 + &M D C NA : O- =8 Yx 78 Z} Z} 8P P <8 ] E7 ^ b6 a 78 b 6 b hb^ c db (M eb 0 f] 8 g @ h H ib P j X X k ` $ !j $ J K A A L 6 7b Q 8K S 9A ;b ( ; a b get set doc b _ G () a *b 5 + A >@ ,] - A doc .b L Q %S { B b ] ] (L 0z ] 8 @ H P 2 Xw ` hS pZ ? x - 2 w w % % . b b X V ` ] ; w . [ X ] ( 0\ 8 @ X H P/ X `D h7 p` x 5 x &P buf obj len ] ] R A v A $8 7 (P 0; 8 @Ջ H 8 ] !{ #; @ A Y Y A # p $j o ' Y r ] K E . & ] 8 0 1 - r 2: ? X 3e j A y w 4 ] 5 ] 7 A ] 9 A \ ;# ( A < C <I N A b =o t A < @ ' A ' B 7 q C h D A % 7 E F GL Q i ` Hm r A I J J @ K: c L M N J O ] R* / M M 5 s1 J [A h t= Q c l_ u ; p % @ A . B C G D C E- (o F 0 G 8d H @A I X H J P K X L ` M h] N p O xW P Q < R . T U V W , X- Y ! Z [ ) \ * ] 8 _ a ` a k b _ d f \ g h &Pj E k y [ l m n o p (9 q 0 r 8 t @ u H v| &x E y y z { | ~] b { { & 3 Q & / ^ w p E ; l 3 \. Jf ^ Ju _ | (, - 4 9] > ] ?W ^ A ]A 7 $A fd & A ' { ( q) \ cpu A "m ~ w z " # 7 $ len % = & '\ @ \ ts >@ T !A "A < # cpu $A ( %A ,Z &A 0p ' 8 4h m A ~ T ` % tep % a 7 id A A 8 X 0 7 H]} \ P+ X * "D {v P r J @ 2 @ 78 Z= 5 7 a 7 7 >@ A ( A , 0 4 . 8 v M A A L h Z 7 7 >@ A Q ' 5 7 >@ A Q C a 7 Q / 78 / A 7 str 7 $ \ 5 7 R 0 78 5 Z \ Q 7 / Q / Q I Q 0 J q Q b . op 7 A O 1 6V "S Z i ' a = { Z M Q 2 !4 Khex " 1 h 5 Kop q X !I T 5! 8 7 6V $ :! 5! ( !4Z! ) !5 D R& !6?! "! Sidx " A Sptr " p " ! f! " "! nr " A }G " A & " A Z4 "! p " ! ! 8& #5" h( # Z! nr #A map #:" 8" A I" +. " $ " y " $<" p , z "h $U# V a " $a=# g "8 $i_# "z $v# z m 1 m t " $$ H N . X @ 2 2 2t 2 2a 2 2: @2, 0 0 0{ 0* 0/ 0; 0_ @ 0 0K 0 " $ % [ < Y ` _ Z $% a " V , k r _ [ $% E Z 5 H [ T10 $j & R. + / - 3 0 :$.& :. $ m1 $ :$R& P- $ / $ :$& 0 $ 1 $ . $ . $ :$& 1 $ 0 $ , $ . $ 3 $** 5 $ $ V $ & $ 8 $ . @ A1 BH. C`1 DH0 Ef, F2 G, H* It1 J92 K/ L. M/ N. O0 Q^- R1 S#0 T2 U1 Vz= Wq, X, Y. Z2 [@ \< ]< ^2 _= `W0 a9 b, c. d3 eY, f.& 0]2 $ 4R& 8& @2 $ H- $ P/ $ X, $ \0 $ `1 $ h/ $ lo3 $ n, $ p|3 $ t0 $ x. $ 9* +. ]A $/q* 5 $0 ? $1 $2 z> $5* dev $6 ino $7 Te $F0+ i p D 5 { ; * U p 0 %) , v %*P , %+& }. %-, 0 %4, . %5, fd %6{, , %7{, b8 %8{, id %9 , ids %: %; , . %> A 5 %E , .3 %J , - %L , idx %M A 0+ " * , Ba0 (&{, ?, & 5 1 & 5 Z4 & 5 - & 5 - & 5 Uy1 &s7 ( , )e %7 'a- Z4 'P 4 ' A 5 ' , =6 ' , *4 ', >4 ' , . ' , ("7 ' A 0A= ' 5 87 ' ! @x4 '!a- `, '"4. `4 '#4. h5 '$4. p8 '%4. x q- . - `(4. ( q ( A fd ( A cpu ( A h( ( Z! ( @ ( end ( (9 (! , 0 (" 87- (# Z @0 ($ H2 (% 5 P78 (&4. X q- H. +. l X. . h. . x. . . . %? () . M )9* pid ) tid ) @ ) len ) : ) ) . ( l / \. C) @/ maj ) min ) ino ) : )! C)#~/ `= )$ Y, )% o3 )& 9 )' ~/ / . ) / @/ @@/ %n= H)+0 M )9* pid ) tid ) @ ) len ) : ) / (0 )* @ )+ D ), . H > )/m0 M )09* pid )1 tid )1 * )2 H. @ )50 M )69* pid )7 tid )7 U> )8 > )90 q* 0 +. ? )<'1 M )=9* pid )> = )> tid )? ; )? )@ 2: )C[1 M )D9* id )E >: )F d< )K1 M )L9* >: )M > 8)Y1 M )Z9* pid )[ tid )[ A )\ L; )] < )^ id )_ (>: )` 0 : )c92 M )d9* )e id )f ,= )g %< )n2 M )o9* 0 )p len )q %; )r )s a )t " < )w2 M )x9* 5 )y )z id ){ tag )~ X. %= )3 M )9* id ) 9X ) . ; )f3 M )9* 0 ) ; ) ? ) J ) 9. z@ )3 M )9* ) 3 3 +. 9 )3 M )9* : ) g9 ) ; )3 M )9* , )& > )!4 nr ) cpu ) !4 04 +. r: )d4 nr ) SA ) q ) ** I< )4 nr ) SA ) = ) q ) 3 @ )4 x* ) = ) $( ) * ) )!5 #? )3 ; )%04 : )%d4 Y; )$4 : )B5 5 ) 4 9 )j5 M ) 9* < )#!5 @ )5 }. ) #!5 E@ )5 - ) | :) 5 - ) )5 = )5 a )5 }. )(j5 l 5 ^. l 5 ^. H? ();6 M )9* 5 ) id ) 5 = H)e6 ; ) a ) e6 l u6 . ? ? P) 6 M ) 9* = ) ;6 : )#6 M )$9* )% _/ 7 < )0 ~/ )1 < )2 }< )3 :)-%7 9 ). %7 @6 57 . 9 $)*s7 M )+9* pid ), T 7 )6 s7 $ l 7 +. ; )97 id ): idx ); cpu )< tid )= 4< )E7 M )F9* nr )G Z4 )H7 7 8 +. > )KS8 M )L9* 5 )M c> )N p )O 3 : 0)R8 M )S9* )T >@ )U 9 )V idx )W tid )X $cpu )Y (c> )Z , 9 x)_9 M )`9* 5 )a y )b cpu )c pid )d tid )e fmt )f ip )g )h (msg )i e6 05 )j pK )k t CA )n9 M )o9* -? )p = )q )r @ )u: M )v9* pid )w tid )x ; ){.: M )|9* )} /; )X: pid ) * ) H. L: ): M ) 9* nr ) Z4 )': .: : +. A ): tag ) val ) ? ): M ) 9* nr ) < )(: : ; +. _@; val ) ena ) run ) :)\; @; W3 ) x. v; 0); M )9* id ) cpu ) +/ ) @; a? ); M )9* 5 ) ) d@ 8)k< M )9* = ) ? ) 9 ) u9 ) *< ) (9 ) 0> ) 1#= ) h. 2 L9 )< M )9* ; ) < ) s7 = )< M )9* < ) s7 T )\= @> @ A B C D E Ff G H I Jj K L: M N O8 P Q) RC S v$ H)@? M ) 9* , ) . z= ) / * ) +0 @ )!m0 = ) 2 @ ) 0 >: ) '1 p< )#[1 T, ) 1 : ) 1 @ ) f3 Kbpf ) 2 < ) 92 W0 )%3 , )"3 T? )#5 = )'u6 %: ))6 9 )%57 @< ) 7 > )# 8 : ) S8 9 )$8 Kaux )9 @ )#9 ; )&: . ) 3 X: )!X: 9 ) B5 ? )": I ) \; m? )!; p@ ) ; @ )$k< ; )!< " *$\? r . + ? @ + end + ? \= ? %I h,QA ip ,R pid ,S tid ,S ,T 0 ,U id ,V ,= ,W (A. ,X 0k ,Y 87 ,Z @X ,[ H ,\ P cpu ,] X ,^ \W ,_ `3 ,` h ,a p ,b x= ,c ,d 5 ,e K ,f ,g ,h ? ,i Y ,j c ,o, $ ,pH. l ,q ,rc ,sc ,t, ,ub ,vb ,wdb T, ,xc ( ,yEc P5 ,zmc ` A %p @-+ D @ -,_ T, --_ , -. ` z= -/` * -0` @ -1` (= -2` 0 @ -3` 8l -4` @>: -5` Hp< -6` P aux -7` X@ -8` `; -9` h. -:` p: -;` xd -<` < -=` bpf ->` W0 -?` , -A7` T? -B7` %: -C f` -D ` 9 -E f` @< -Ff` > -Gf` 9 -Hf` p@ -If` X: -Jf` 9 -Kf` ? -Lf` I -Mf` m? -Nf` _9 -Of` -Pf` = -Q ` : -R ` (U -S, 0. -T, 1 -U, 2 -V, 3h -W, 4( -X, 5^ -Ya 8 D % .;F - .<0+ 7 .= G h .> H .?A .@A , .A VM .nO .o D ]} .q 4 .r$P Z .s$P .t. .ukP p .v .w .x , .y , .z , . .{ , I .| , ? .} , .~ , . , E . , ! . , 8 . , 6 . , J . , . , o . , .uP Derr .A h .^O { . .P .P ( .P 8 .A H .A LVO P .. X .A `Dpmu .K hVO p ., x 8D 8*Q G *R *S q *T 5 len *U 5 *V idx *WA (tid *X T ,cpu *YA 0 G %7 /6H - /7, Q; /8 , /9A /:A /; /<nQ > /@Q , /AK /BK /C D /DL Denv /ET ` J /F T h /I p /J x +/ /NQ /SQ Deet /T T 0K 0j 92 0 , @ 0 , A 0 , B5 0 , C 0 , D 0 , E 0 , F, 0 , G 0 , H 0 , Id 0 , J 0 , K 0 , L 0 , M 0 , NA. 0 , O1 0 , P 0! , Qt 0" , R 0# , S 0$ , T3 0% , U@ 0& , V= 0' , W 0( , X 0) , Y 0* , Z~ 0+ , [D 0, , \ 0- , ] 0. , ^9 0/ , _ 00 , `M 01 , ab8 02 , b 03 , c 04 , dW0 05 , e9 06 , ft1 07 h% 08 l 09 p< 0: t 0; x 0< 0= 0> 0? 0@5 ~ 0Ab 0Bb 0 0C , , 0D , , 0El 0F t 0G A { 0H A 0I A , 0J 0K 0L A ! 0M A 0N , 0O A 0P A 0Qb K K , 1 L - 1 q- 1 F ` aio 1&[ 1(g[ < 1) 1*[ 1+([ %3 2 L 2 2 b 2 E 2 p 2! [ 2" (. 2#L 0 2$ |R 2% 2& 2' 2( 2)L 2* L . R L . C(3=M val 3 Q ena 3 Q run 3 Q id 3 Q >: 3 Q (3XM @L W3 3 XM Q hM . K3 (3|M =M ) |M .M A M ? " . M A 0 C.HJO a .I 7 .J 7 .Kb { .Lb .N $ .P 7 ( .Q. 0- .R | 8= .Sb @? .TOO H .Ub P .VM Xa .X A \H .Y A ` .Z , d- .[ , eI .\ , f .] , g .^ , h+ ._ , i .` , j .a , k .b , l .c , m .d , n .e A p0 .fYO x .gP = JO N TO &.O cb .O < . M .O . O Q . O l . ` O M O .O b . .{, D / 4 $P 22 4 # W3 4{, 4{, O @5#kP u 5%g D 5' A (G 5)h 0 5+ , 8 )P pP zP Xv 6P ~ 6A r 6 6 P &7$P o 7& P P 7'P 'P P P Y07 Q = 7 Q s 7" y 7(P A ,Q . @7nQ 7P 7 A 4 7 A G 7) P " /-Q &/=Q />A pid /? T &/KQ th /Ly @ /MH & /O R fd /PA ack /QA pos /RA %r 8=T 8> 7 8? 7 $> 8@ 7 V 8A 7 8BA 8CA $& 8D 7 ( 8E 7 0 8F 8 8G @ 8H D 8I H 8J L 8KA P 8MA T 8NA X 8OA \ 8PA ` 8QA d 8RA h8 8SA l 5 8TA p 8UA tO 8VA x 8WA | 8X 7 8Y V 8Z 7 8[ 7 8\ 7 ; 8] 7 8^ cpu 8__ C 8`_ 8a A 8b L 8c { 8d , 8e 8f 8g_ 8h_ g 8i R 8j_ 8k_ 8w^ 8}=_ `w 8 _ t 8 A 8a_ T 8 _ R 'T G ? ? T T /W U a /Xb ]} /Y 8T 9.6U nr 9/ ips 906U EU +. `[U a \b 8 ]b ^V ` a b V (; g V 0| j W 8 l Y @U n Y H o V Pg rY X A V b A V ? b U '6V ? ? D 6V 6V ;V @: V +/ : j G9 ::a map :Da sym :a :b 0 : ( : l 0!8 : 1 : 2 cpu : 4 : 8 V 'V ? ? V V V 'W ? ? W '+W +W D 0W % p5CY 1 5Dh 5E - 5F , 5G , 5H , 5I , P 5J , a 5K , F 5L , 5M , 5N , 5O , 5P , @ 5Q , 5R , ~ 5S , 5T , 5U , 5V , 5W , 5X , 5Y , 5Z , 9 5[ , 5\ , ' 5] 7 5 5^ , (U 5_ 0 5` 8 5a <# 5b @ 5c D 5d A HP 5e A L 5f A P 5g A TU 5hb X 5i#i `. 5jf h 5k(i 5l-i 5mh 5n-i 5o , 5pWg 5q A P! 5r A T 5s , X 5tb ` 5u h W 'Y Y A Y % b Y Jn u / (Z Z '(Z 4. ;"Z ;$A W ;%A ;&A ;'Z E ;( 5 ;),Q ;,Z ` ;-A h ;.A lq ;/A p ;0 x* ;6 $[ ;8 Z w(Z B < Z < [ <Z _ <pZ =][ =][ =b[ , =A [ [ 1[ v 1\? 1 5 & 1![ < 1" [ w 1#Z 1$[ t 1% A Z [ B >\ h >. >\ L >\ [ > 5\ > \ >w]\ >x\ U >y\ $? \ ? A v ?A ?A die ?A ?A a ?A ? A - ? A cpu ?"A ?&] nr ?(A map ?*] ]\ ] +. 8@ 1] @ 8 s] 8 A 8A 8A W 8A (8] 8 8 8 8 5 87 87 map 87 q 8 ^ v 8 8 8 map 8!, d 8$S^ v 8% 8& set 8'\? 8*{^ 8+7 }. 8,7 8/^ 80A 81 82 83 85 867 89^ b ^ A &X8q=_ 8r] 8s\ 8 8t @ 8u\ H 8v P &@8za_ 8{] 8|\ 8 & 8_ [ 8 8 8 , 8A Q; 8, 1] s] ] ^ S^ {^ A ^ -_ _ A ` A ? ? D V J -` ` A 7` A ? ? V -C` H` A a` A ? a` G - r` w` A ` ? ? - ` ` ` ? ? - ` ` A ` ? ? b -"` ` A a A ? a a U "@ -%5a ( M G9 5a xmap ?a B 0A0a U A1[ @ A3 end A4 | A6 (;5 8 P;l : T;2 < X;S > Y; @ Z;S B [; D \ AF ,a AHs7 - Ia % , Tb abi , q , ,, ,Tb - , db . ? ,b >@ , , < ,7 5 ,b A , id , >: , &,%b nr ,& W3 ,' b b ,$c W2 ,(b Sone ,) b H (,!Ec L; ," < ,# b ,@mc ,A < ,B 5 ,Ec ,V ,F ,B ,G ,kc ,l ,m U B/c nr B0 B1 Z4 B2d c CBd ,? B , B , B , B ,z9 B ,5 B , B , B ,p B ,#= B ! Bd A B @c Bd d B)d B* to B+ B,d d d +. C(!e C* M C++ C/Ce C1 M - C2+ C5ee C7 M C8+ C;e C= M C>+ CBe CD M CE+ CHe CJ M CK+ CNe CP M CQ+ CUf CW M CX+ C[1f A C] M C^+ CaSf 8 Cc M < Cd+ Cguf Ci M Cj+ Cmf Co M Cp+ Cuf , Cw M Cx+ C|f C~ M c C+ C!Wg C$ M C& d !e (Ce 0ee 8e @e He Pe Xf `1f hSf puf xf f e 0Dg Z4 D5\ 4 D ! Dg Dg D g ( A g \ g \ g g Wg g 'g g \ g (5>h n 5 | m 5 | M2 5| max 5 min 5 = 05h 4 5 hM nr 5 A ( 5 , , 5 , - >h "1 5.h k Q \ " ' P5<h p 5=g ; 5>g ( 5A i i ]\ #i +W A g h \ " E$j : . 5 ~ - w ] / ' # b !h "n #U $ % &D ' (" ) * + ,k -w .1 / 0H 1 26 3< 4 +/ j @FAk pid F b tid F b 6 F b F b F b uid F < (5 F , ,N F , - F , .6 F , /; F , 0@ F A 4 Fb 8 Gvk key G > GA G k Z GKk GL. × GMb vk %8 GPl u GQA GRH @7 GS G 8 GT? @J GVb HH GWb PV GXb XE GYA `Dal G\;V h G^ k Z G_b ( Gam Gc Gd ] Ge Gf GhM # GjA ӿ Gk i Gl, Gm, Gn, k G8m G9 *m a G<b '%m D ? %m Ak m $ (G?~m G@ m ? GC m : GEm GF m a GHb , m D ? %m ~m l 'm l %m 7 m /m " Hm f "} Hn b q C " H >n & 6 [ B Hb4o Uv Hf[ Hgo id Hl cpu HmA (a Hn7 0 Hs 8 Hto @ Hy p= Hz xg H{ J H| O H $ H H 3 H [ H H H, PHo HP a Hb 5 Hm H H"o H5\ ( Ho 8 H q @ H q H 4o P o . U A o o ? o 'p p o q n D ? V p % PHƻq u HA HP @5 HP P HP `I H P pz H5\ ! H$r G Hb 6 Hb O Hr ! Hb H a? H, 6 Hb X Hm H, l Hb H, / H ; H, C H H . H. h H. Z H. h H ^ H Hr (% Hr H >n o 'q q 7 A q T H!r HIr HIr HIr HIr 8q A Ir p o D ? V &r (Hr B H 2 H irq H ' H H % Hr Hr H r . r . Nr !r r . I s I! I" B Is I yrb I[ 0 I (a I 7 0 I , 8 I @ I D I H I Lr Pt I$ TF I' X I( `+ I) h I* p I,A x I-A | J J % JDt K L D @ M? Z= N\= l Tt . * \ Dt 0 ; yt . * ^it X * ~ V l t . # * t 0 ; t . * t T * `R * Dt p0 ; 'u . * u P *7 N l au . * Qu P0 *Y u @L *N J *S Dt 00 ; u . *! u H R G Dt 0 u @E C l Bv . D ( 2v / ; hv . *Xv A } @@ l v . ! v / ; v . @ v > g < w . % v @Í Fw }. , < < W A H. / f C : Tw U . W, : l w . w / 8 ` .x D >x . A 4.x @8 l dx . > Tx `/ ) @ 6 `[ Qx R 7 TG x . x 5 _ `5 U d Tx / f 3 zzIy a {b A | A "y Yy . C }Iy .x 3 { Z T / & y b b L% by -t A y - y <5 /az G 6 /A +z G 3 /A Az G P7 /A \z G A K"A wz L z A b b A b b b A < K z ] <*5 /dz G D M z { b = - .A 0{ D ? ? << N B{ 4. - / D ^{ G ? J= N ? t{ 4. .> N A { 4. <3 /_{ G , , OA { b = Le . { D { -2 .UA | D , , L/ . )| D )| A & & P E| b = Q [| . R v| b ] S#A | 7 - | % A -N | b z ( | A - Tsb | - } -I .} O UE A O} A g = L V b} P x} b a6 <+ W} , * WT } , A + WA } , X, } T T < <& .} , _ O$ ~ b = (' 3 A )~ )~ A 5" % ;A D~ )~ * '", Z~ b O A ~ b = <m ~ b aM Y:A ~ b Q ~ M ~ r O3A b -% ZM $ A v O ? ? A . A & 6 7] A \ \ 5 V \ \ F& . & 3 0 ) \ \ a Jb ] ] A ] ] & s . & 3 Q 0 & 6] 2] & . , P& 3 -V L] H] J, b] ^] & .T A & 6 $ x] t] (str @7 ] ] (sz 5 ] ] F& b & 1 { @ ,? ] ] +/ j ] ] V ] ] & . q & 3 ;p ] ] o ^ ^ (key q (^ $^ & . _ P& 3 + V Ib >^ :^ & . A & 6 &b T^ P^ (ops Q j^ f^ F& EU b & 1 ǂ (set !A ^ |^ & c | 3set |(A . vA P& 6 ` @ v ^ ^ v? ^ ^ (num wA ^ ^ w A ^ ^ & c o 3kvm o2l 3key p%m m q 7 d h, ǃ h# D @ i? 3key j%m | a, a% D @ b ? 3key c%m . \, P& 3 C \# D ^ ^ & d W, _ W$ D . % F Ɏ 1obj _ _ 1i A $_ _ !1 _ }_ 6 3 ! _ _ e9 H& % % # _ _ } % M% y M U| a% y l U G u% y U `R % y U N % y Ʌ U J % y U C % y U @@ #% y U < O % % _ #% y U} % % # & y U~ s & & ކ #0 & y U 8 0 8 & 8 & ! #K & y U : o f & f & p z ` _ ` ` 2` .` o & & z P` N` e` a` ` ~` o & & z ` ` ` ` ` ` o & & ] z ` ` a a "a a o & & ! z @a >a Ua Qa ra na o & & $ z a a a a a a o G& G& 'J z a a a a b b o n& n& * z 0b .b Eb Ab bb ^b o & & - z b ~b b b b b o & & 07 z b b b b c b o & & 3 z c c 5c 1c Rc Nc o & & 6Պ z pc nc c c c c o -& -& 9$ z c c c c c c W & & E b d d & & d d #& y U| % $ ȋ U 3 T ] & ߋ UN & ~ Us T N& Q} & ~ 5 Us T 4L& Q~ & ~ ` Us T NI' Q| & ~ Us T H' Q G & ~ Č Us T I' Q N G& ~ Us T| Q `R n& ~ ! Us T I' Q J & ~ L Us T| Q `R & ~ ~ Us T H' Q C & ~ Us T H' Q @@ & ~ Us T G' Q < -& ~ Us T Go& Q 8 T& ~ F Us T G' Q : \& ~ ^ Us & ~ & ~ U~ T Q| & ~ & ~ T >D' & 4t : 6: 6V a ! ? 1 6sys 7 a 7 x 7 O . M rA $# O % b (obj O. ,d "d (i O>] bd Xd S Qb 1pos R D d d f2% !8 Wg d d f`% !8 Wg d d W 5 !8 \ l d d >% } T U <' % x x F $ H] % 3 (obj H1 d d S Jb % 4 S 8b 6V a " 7 G $T % S ?b d d 6V e e a " ;e 5e !7 G \e Te !Z= ? e e ^- A ?cpu A ? P1 1md K e e 1err A e e ~end % W ! e e ! f f ! D (f f % % V ɦ Pf Lf զ cf _f tf rf ٰ % % f f f f f f #% U T~ % z W %% %% b f f %% %% k f f #B% y U} /W % b f f % % ݓ f f #% y U} o % % + 5z 7 E P % B{ I U|T~ % 0{ a Us % { U| T Q} ]% z T ( % x} / /% f f f f N f f # p% $ 7g 1g o % % e 5z Tg Pg jg fg % Z~ UTTQQ 2D' R P1 XY }% t{ ŕ Us % ^{ ݕ Us % t 4 K 1 7 + G 3cpu 7A 6i A g6md K $ @% S 7b g g 6V g g a g g !7 G g g P! D h h /o % z ,h *h N 8h 4h Nh Jh t% { ; UTT <' QP % z S U| % } r U x& % $h % j S >b oh ch 6V h h a h h !7 G h h ! i i 1i A Qi Ci e@ % W 7 ! i i /W % b i i / % i i #% y U~ /W w% b i i #% y U~ Y% wz T .H& Q R X0Y0 #n% \z U} T~ % z N U0 % x} % $ % S 8b i i 6V j j a " *j $j !7 G Mj Cj @1 A T1n A j |j #% Z~ S UTTQQ 3D' R @1 XT 3% Az k Us G% } U x& o% { x% 4= m S m8b 6V n a n" 7 p G q? 1 * rA 9 rA O g% O S g5b j j % % j} Ͱ j j % y Us P% UU % $ W A % S W2b j j 6V X k k a X# 'k #k T Z H Z P!}. [, ;k 9k !. \, Ik Gk % { UTT Aw& QHRP % { Us <% M KA $\ `% k 6: ]k Uk 6V k }k a ! k k ! D k k !}. , l k !. , l l T H P W2 A @ A D k 1 o % % 0 5z 'l %l 4l 0l % Z~ 8 UTTQQ ,D' R 1 XHYP % { P U| O% { X% 7 { . O8 `% O 3: Sl Il % % Ͱ |l zl % { Us P% UU % $ A % c 0: l l 6V l l a " l l , & ~ c 1 :. ~ . } } 1 ~ H. ~ `1 ~ H0 ~ f, ~ 2 ~ , ~ . ~ * ~ t1 ~ 92 ~ / ~ . ~ / ~ . ~ 0 ~ ^- ~?idx A ~% Z~ 7 UTTQQ ( R 1 X| Y~ (% | U UsT| T% 7 s . Mp A $ w % % (obj w2 l l (i wB] 3m 'm y% % } % } Ts >E% } U x& g% w $ p] % < (obj p5 hm dm r% % } % O jp% O j=% m zm % % m Ͱ m m % } P% UU % $k Z A % Z:% m m 6V [ m m a [ n m ] 2 ?pid ^A L?tid ^A P?uid ^A TZ% Z~ UTTQQ D' R 2 XLYP n% } % 7 0 . M NA $ 2 % (obj 2/ 'n n (i 2?] dn Xn T 4 % .~ % ~ Ts >% } Ԥ U x& % w $} +] @% < E (obj +2 n n T - d% .~ |% O %% O ۥ T %7 n n % % ( Ͱ n n % } P% ͥ UU % $ A % | T 4 n n 6V o o a $ -o 'o 2 7 P% Z~ UTTQQ D' R 2 XP % D~ <% 4 Z= 4? 4_ A 6err A out $ % E Go Co 1ret co Yo ?s 7 P/ % ʧ o o ( o o #% .} UPT1Q ( % b} ,% O} M% x} W% $ % 0 o o B p p 1obj `p Xp /ի L% [ p p / % f ժ p p p p Nf + p p 7 p p D p p /a % q 0 q q q } :q 2q Nq ]q Wq yq sq q q q q r q ȫ :r 0r % % U `r ^r % v| © U~ T % [| U~ T G% | [% ~ e% E| % | #% b} U~ Q p% 0 R jr hr |% |% x - tr rr y% | % | U| % | #% | T} >~% } UUTT % 4N n a n) n; 6str pb q D Q r g u 4R E ի 3pe E% Q EB G% < H 6ret I 6val J >@ K 6len K 4+ ? , ?. $e 0 `% w ڬ 0= r |r 1ret 2 r r ?s 37 P/ % + 5 r r ( r r #% .} UPT1Q D' % b} % O} % x} % $ % J = ; r r >5% .| / U ( :% F % G ; s s hret 3s )s is 7 Pj ; ̭ 5 5( #"% .} UPT1Q ( /% b} ;% O} ]% x} g% F/ @% h m G ? _s Ws te m >% .| _ U ( % 1 F 0% Q ܮ G ; s s >|% .| ή U P( RU# % Fe % z < G ; s s % .| . U ( *% Fn k p% G k; s s hret m s s is n7 Pj K p˯ 5 5( #% .} UPT1Q H( % b} % O} % x} % H9 , A 8. HU 2!, : Qptr 2D HL -!, W Qptr -< kK o 3op 9 k p 3op p9 E - E H $A Qop = H ٰ Qob / l AoX AS % Ah 5 lm A 6 A& AD g = R % h V Ґ t t ސ 8t 4t Nt Jt dt `t o (% (% ̱ 5z zt xt t t P% P% - Ґ t t ސ t t t t 7 _% { $% +z H UU# h% R p% г t t t t ͚ u u ٚ /u )u E PE T % % mW Pu Nu Zu Xu ͚ gu eu 7ٚ 7 7 o % % }5z tu ru u }u % Z~ UTTQQ 6D' R 1 XPYT % z Us % { % RɎ % D َ u u u u u u u u E XE, `: % % d J u u Ɏ % % ִ َ v v v v #v !v 7 7 7, #% ~ U l% Z~ UTTQQ :D' R 1 XXY` % y % ~ % Rǃ & 3 ك 2v .v Hv Dv ^v Zv & SI SI [ : ; 9 I8 I :!; 9 I !I $ > :!; 9 I 4 :!; 9 I .?:!; 9 'I@| : ; 9 I 4 :!; 9 I : ; 9 < ( .?: ;9 'I< I ! I/ :!; 9 I : ; 9 I8! .?: ; 9 'I< .?:!; 9!'@| % y $ > & I : ; 9 : ; 9 I8 > I: ; 9 .?: ;9 '< ' .?: ; 9 '@z : ; 9 I8 I 4 : ; 9 I :!;9 I !I 4 : ; 9 I I 4 :!;9 I ! I/ : ; 9 I : ; 9 I .?:!;9!'I@| 4 :!;9 I .?: ;9 'I< .?:!; 9!'I@| $ > & I ( .?: ; 9 'I< .:!; 9 '@| .: ; 9 'I@| . ?:!; 9!'I@| : ; 9 : ; 9 I8 :!;9 I : ; 9 I .:!;9 'I@| < :! ; 9 I 7 I : ; 9! !.?: ; 9! n'I< ".?:!;9 n'I< #! I/ $! I/ % &% y '$ > ( : ; 9 ) * : ; 9 + : ; 9 ,& -> I: ; 9 ..?: ;9 '< /. ?: ; 9 'I< 0.?: ; 9 '< 1 ' 2 : ;9 3.: ; 9 'I@z 44 I4 5 : ; 9 6.: ; 9 '@z I $ > !I :!; 9 I 4 :!; 9 I .?:!; 9 'I@| :!; 9 I8 4 :!; 9 I . ?:!; 9!'I< : ; 9 I 7 I I .?: ; 9 'I< :!; 9 I .?:!; 9!'@| & I ! I/ .?:!;9! n'I< 'I .?:! ;9! 'I< .:!; 9!'I@| % y $ > : ; 9 : ; 9 I < ! I/ .?: ;9 '< .: ; 9 '@| : ; 9 I8 I !I $ > .?: ; 9 'I< : ; 9 I I 7 I 4 :!; 9 I .?: ;9 'I< ! I/ < 4 :!; 9 I :!;!9 I % y $ > & I : ; 9 : ; 9 : ; 9 ! I/ .?: ;9 '< .?: ;9 n'I< .?: ; 9 'I@| : ; 9 I $ > I !I .?:!; 9!'I< % y $ > & I .?: ;9 'I< .?: ; 9 'I@| : ; 9 I 4 : ; 9 I 4 : ; 9 I I ! I/ :!; 9 I8 !I $ > : ; 9 I :!;! I8 4 : ; 9 I?< I :!; 9 I I ! I/ < 4 G:!; 9! % y I : ; $ > & I : ; 9 : ; 9 'I .?: ;9 'I< .?: ; 9 '@z .: ; 9 'I@| 4 : ; 9 I 4 : ; 9 I $ > I !I :!;!9 I % y : ; 9 I $ > & I .?: ;9 'I< .?: ;9 n'I< .?: ; 9 'I@| : ; 9 I 4 : ; 9 I ( :!; 9 I8 $ > !I I : ; 9 I :!; 9 I :!;! I8 I ! I/ < 4 : ; 9 I?< 4 :!; 9 I .?: ;9 'I< .?:!; 9!'@| % I : ; $ > & I : ; 9 : ; 9 > I: ; 9 > I: ; 9 'I : ; 9 I .: ; 9 'I@| ( : ; 9 I8 4 :!; 9 I I !I : ; 9 I 4 : ; 9 I 4 :!;9 I : ; 9 I 4 :!;9 I .?:!;9 'I@| :!;9 I $ > & I :!;9 I 1 ( .: ; 9 'I@| 4 1 I :!; 9 I 4 :!;! 9! I ! I/ .?:!; 9!'I@| 5 I .?: ;9 'I< 4 I4 : ; 9 I : ; 9 :!; 9 I 1 ! < " : ; 9 I8 #.?: ; 9 'I< $ %.: ; 9 'I@z &.: ; 9 '@| ' 1X Y W! ( )7 I *>! !I: ; 9 +.?:! ;9! '< , -% . /> I: ; 9 0$ > 1 : ; 9 24 : ; 9 I?< 3 : ;9 I 4'I 5& 6 : ; 9 7! I 8. ?: ; 9 'I< 9.?: ;9 n'I< :.?: ; 9 '< ;.?: ; 9 '< <.?: ;9 'I@z =.: ;9 'I@z > : ;9 ? : ;9 @ : ; 9 A U B.?: ; 9 '@| C.?: ; 9 '@z D.: ; 9 'I E.: ; 9 '@z F G : ; 9 H : ; 9 I I : ; 9 I J.: ; 9 ' K : ; 9 I : ; 9 I8 : ; 9 I !I : ; 9 I $ > I 4 : ; 9 I 1 4 1 4 :!; 9 I 4 :!;! 9! I & I 5 I I :!; 9 I .: ; 9 'I@| : ; 9 I :! ; 9 I : ; 9 ! I/ .: ; 9 '@| 1 < :! ; 9 I8 .?:!; 9 'I@z .?:!; 9!'I@| 4 I4 1X Y W! % ! "$ > #& $ : ; 9 % : ; 9 &4 : ; 9 I?< '! I (.?: ; 9 '< ).?: ;9 '< *.?: ;9 'I< +.?: ; 9 'I< ,.?: ; 9 '@| -. ?: ; 9 'I@| ..?: ; 9 '@z /.: ; 9 'I 0.: ; 9 '@z 1 2 : ; 9 3 : ; 9 I 4 : ; 9 I 5.: ; 9 ' 6 : ; 9 I : ; 9 I8 :!;9 I :! ;9 I k I : ; 9 I 4 :!;9 I :! ;9 I8 !I : ; 9 I8 : ; 9 I 4 :!; 9 I $ > :! ;9! I 4 :!;9 I 4 :!; 9 I : ; 9 I : ; 9 .?: ; 9 'I< .?:!;9 'I@| .?:!; 9!'@| ( I8 :!;9 I I :! ;9! .?: ; 9!'< .?:!;9 'I@z .?:!; 9 'I@| .: ; 9 'I@| :! ; 9 I ! I !.?: ;9 'I< ". ?: ; 9 'I< #.:!;9! 'I@| $.:!; 9 'I@z %& I & ' (% )$ > * + : ;9 I , : ; 9 - : ; 9 . : ; 9 / I 0 : ; 9 I 1! I/ 2> I: ;9 3 : ;9 4 : ; 9 5 : ; 9 I 8 6' 74 : ; 9 I?< 8.?: ;9 '< 9.?: ;9 '@z :.?: ;9 '@| ;.: ;9 '@z <.: ; 9 '@| = : ; 9 > U ?.: ; 9 '@z I : ; 9 I8 :!;9 I 4 : ;9 I :!;9 I k !I : ; 9 I : ;9 I 4 : ; 9 I .?: ; 9 'I< : ; 9 I : ; 9 I8 4 :!;9 I :!;9 I8 : ; 9 ( : ; 9 I $ > :!;9! I .?: ; 9 '< .?:!; 9!'@| I .?:!;9!'I@| .: ; 9 '@| .:!;9 'I@| & I ! I/ I8 1 4 : ; 9 I ! :!;9! " :!; 9!I8 #.?:!;9!'@| $ : ; 9 I %! I &' ' (. ?: ; 9 'I< ).:!;9! '@| *.?:!; 9 'I@| +.: ; 9 'I@z ,.: ; 9!'@z - : ; 9 I .>! !I: ; 9! / :!; 9 I 0'I 1.?:!;9!'@z 24 I4 3 :!;9! 4 U 5.: ;9 '@z 6 : ; 9 I 7% 8 9$ > : : ; 9 ; : ; 9 <> I: ;9 = : ;9 > : ; 9 ? : ; 9 I 8 @ : ; 9 A4 : ; 9 I?< B.?: ;9 'I< C.?: ;9 '< D.?: ;9 'I@z E U F : ;9 G 1X YW H : ; 9 I.?: ; 9 'I@z J.: ; 9 'I@| K.: ; 9 'I L 1X Y W M : ; 9 N : ; 9 I O.: ; 9 ' P5 : ; 9 I8 : ;9 I8 : ;9 I 1 :!;9 I k : ; 9 I8 : ; 9 I !I : ;9 I8 I : ;9! : ; 9 : ; 9 I I 4 :!;9 I 4 : ; 9 I ! I/ 4 : ; 9 I : ;9 I $ > :!;9 I8 4 :!;9 I 1X!YW : ; 9 I .: ; 9 'I@| ! I 4 : ; 9 I & I : ;9! ! :!;9 I8 " : ; 9 I #4 1 $ :!;9 I k % : ; 9 I & I '( (.?:!; 9!'@| ) :! ; 9 I *5 I +4 I4 , 1X Y W - :!; 9! . /.: ; 9!'@| 0 1 1 < 2 : ;9! 3! I/ 4 : ; 9! 5 : ; 9! 6.?: ; 9 'I< 7.?:!; 9!'I@| 8 9 : ; 9 : : ; 9 I ;4 : ; 9 I?< <! I7! =.?: ; 9!'< >.?:!;9 'I@| ? :!;9 I @ :!;9 I A.:!;9! 'I@z B.:!; 9! ' ! C :!; 9 I D% E$ > F G : ; 9 H : ; 9 I : ;9 J> I: ; 9 K : ;9 L& M' N.?: ;9 'I< O P.?: ; 9 '< Q U R 1RUX YW S.?: ; 9 'I@z T.: ; 9 'I@z U.: ; 9 'I V.: ; 9 '@z W5 $ > I % : ; 9 I $ > .?: ;9 '< .?: ;9 'I< .?: ; 9 '@| : ; 9 I I .?: ; 9 'I@| : ; 9 I $ > :!; 9! I8 I :!;!9 I .?: ; 9 'I< .?:!; 9!'@| :!; 9 I 4 :!; 9 I % : ; 9 I $ > : ; 9 : ; 9 I 8 I ! I .?: ;9 '< I .?: ; 9 'I@| 4 : ; 9 I I $ > :!; 9 I : ; 9 I !I .?:!;9!'I< .?:!; 9! 'I@| 4 :!; 9 I & I :!; 9 I 4 :!; 9! I % $ > & 4 : ; 9 I?< 4 G: ; 9 .?: ; 9 '< . ?: ; 9 'I< .: ; 9 'I@| 4 I4 I ! I/ I ~ 1B : ; 9 I8 I H} : ; 9 I : ; 9 I H} !I 1RB UX Y W : ; 9 I $ > H } 4 1B :!; 9 IB 1RB X Y W I .?: ; 9 'I< 4 : ; 9 I U 4 : ; 9 I .?: ; 9!'I !4 7 I ! I/ .?: ;9 'I< : ; 9! :! ;! I8 .?: ; 9 n'I< .?:!; 9 'I@z 4 :!; 9 IB .:!; 9 'I ! !4 :!; 9 I "4 1 # 1 $4 1 % < &.?:!; 9!'@z '.: ; 9 ' (.1@z )H } *& I +4 : ; 9 I?< , : ; 9 IB -4 :!; 9 IB . 1RB X Y W / 0! I/ 1H} 2. ?<n:! ;! 3% y 4$ > 5 6 I 7 : ; 8 : ; 9 9.?: ;9 '< :.?: ;9 '< ; 1UX Y W < 1X Y W =.?: ; 9 'I >4 : ; 9 I ? U @H} A.: ; 9 '@z BI ~ C 1 D 1U E 1U F 1RB UX Y W G. ?<n H6 I ~ : ; 9 I8 1B I H} H} !I : ; 9 I : ; 9 I :!; 9 IB 4 :!; 9 IB H } : ; 9 I $ > .?: ; 9 'I< 4 :!; 9 IB 1RB X!YW! 1RB UX Y W 4 : ; 9 I I 7 I 1RB X!Y W 4 1B : ; 9 ! I/ .?: ;9 'I< .?:!; 9!'@z .?: ; 9!'I !4 :! ;! I8 < U ! U ".: ; 9 'I #.: ; 9 ' $ : ; 9 IB %.?: ; 9 n'I< &. ?<n:! ;! '4 :!; 9!I?< ( :!; 9 I8 ).?:!;9! '< * :!;!9 IB +4 :!;9!IB ,4 :!;9 IB - 1RB UX!YW! . 1RB X!Y!W! /H} 0.:!; 9! '@z 14 :!; 9 I 24 :!; 9 I 34 1 4.1@z 54 1 6% y 7 I 8 : ; 9 :$ > ;& I < : ; 9 = : ;9 I >'I ?& @ : ; 9 A : ; 9 I B! I C. ?: ; 9 'I< D.?: ;9 '< E.?: ;9 'I@z F G 1RB UX Y W H.?: ; 9 ' I.?: ; 9 'I@z JH } K.: ; 9 '@z L4 : ; 9 I MI ~ N! I/ O.?: ;9 'I P : ;9 I Q.?: ; 9 'I R 1 S 1UX Y W T 1 UH} V6 W. ?<n : ; 9 I8 I ~ I H} !I $ > : ; 9 I .?: ; 9 'I< H } .?: ;9 'I< :! ; 9 I8 :! ; 9! I !k 4 :!; 9 I : ; 9! I ! I/ 7 I < 4 : ; 9 I?< H} .?:!; 9!'@z 4 :!; 9!I & I 4 :!; 9 IB 4 :!; 9 IB 4 :!; 9 I .:!; 9! '@z H} U :!; 9 I % y !$ > " # : ; 9 $ : ; 9 %' & ' ''I (.?: ; 9 n'I< ).?: ; 9 '< * +.?: ; 9 'I@z , 1RB X Y W - 1B .. ?: ; 9 'I@z / : ; 9 IB 0 1RB UX Y W 1. : ; 9 ' 24 : ; 9 I 3.?: ;9 'I 4 : ;9 I 5.1@z 6. ?<n I ~ 1B H} : ; 9 I8 I H} 4 1B ( 1RBUX!YW :!;9 IB 1RBX!YW : ; 9 I !I 1 1RBUX Y W : ;9 I U 4 :!;9 IB : ; 9 I 4 :!;9 I 4 :!;9 I $ > : ; 9 I :!;9 I 4 1 .?: ; 9!'I !4 .?: ; 9 'I< .:!;9 'I ! U H } 1RBUX!YW ! 1RBX!Y W! "& I #7 I $H} % :!;9! & 1RBUX!Y W 'I (.?: ;9 'I< ) 1UX!YW *! I/ + :! ;! I8 , : ; 9! -.?:!;9!'I@z . 1 / 1 0 1RBX!Y W 1.: ; 9 'I 24 : ; 9 I 3.1@z 4 1X!YW 5. ?<n:! ;! 6 < 74 : ; 9 I?< 8>! !I:!; 9! 9 :!; 9 I8 :.?:!; 9 n'I< ;4 :!;9 IB < :!;9 IB = >.:!;9! ' ! ? : ; 9 IB @4 :!; 9 IB A.: ; 9 ' B 1 C'I D( E.?:!;9! '< F.?:!;9!'@z G :!;9 I H :!;9! I.?:!;9!'@z J4 :!;9 I K LH } M N4 1 O4 :!; 9 I P4 :!; 9 IB Q4 : ; 9 I RH} S.?: ; 9!'I ! T6 U% y V$ > W X : ; 9 I Y I Z : ; [ : ; 9 \ : ;9 I ]& ^> I: ; 9 _( `4 : ; 9 I? a. ?: ; 9 'I< b. ?: ; 9 '< c.?: ;9 '< d.: ;9 'I@z e 1RBX YW f 1U g 1 h.: ; 9 'I@z i : ; 9 IB j 1X Y W k.: ; 9 '@z lI ~ m! I/ n.?: ;9 'I 4 o 1U p. ?<n I ~ H } 1B : ; 9 I8 I H} !I H} 1RBUX Y W : ; 9 I $ > 4 1B : ; 9 I 1RBX!Y W : ; 9 I ( .?: ;9! 'I< 4 : ; 9 I I :! ; 9 I8 :! ; 9! I !k .?: ; 9 'I< 4 1 ! I/ :!; 9 IB :! ;! I8 .?:!; 9!'I@z .: ; 9 ' 4 :!; 9 IB 4 :!; 9 I & I !7 I " < #.?: ; 9!'I !4 $ 1 % : ; 9! &.?:!; 9! n'I< '. ?:!; 9!'< ( U ) 1U * 1 + ,4 : ; 9 I -.1@z .I ~ /% y 0$ > 1 2 : ;9 I 3 ' 4 I 5 : ; 6 : ; 9 74 : ; 9 I?< 8> I: ; 9 9'I :.?: ;9 '< ;. ?: ; 9 'I< <. ?: ;9 'I< = : ; 9 IB >4 : ; 9 I ? 1RBUX Y W @H} A.: ; 9 'I B.?: ; 9 'I@| C U D4 : ; 9 IB EH} F.: ; 9 ' G! I/ H.?: ; 9 n'I 4 I. ?<n J. ?<n: ; : ; 9 I8 I ~ 1B !I $ > I H} : ; 9 I : ; 9 I : ; 9 I 1RB UX Y W! I ! I/ :!;! I8 4 1B H} 7 I < : ; 9 IB U H } 4 : ; 9 I : ; 9! :!; 9 I8 4 : ; 9 I .?: ; 9 'I< .: ; 9 'I .: ; 9 ' .?:!; 9!'I !4 .1@z % y !$ > " #& I $' % I & : ; ' : ; 9 (4 : ; 9 I?< ).?: ;9 'I< *.?: ;9 '< +.?: ; 9 '@z ,H} -.?: ; 9 'I@z .4 : ; 9 IB / 1RB X Y W 0.: ; 9 '@z 1I ~ 2! I/ 34 1 4 1 5. ?<n: ; 6. ?<n :!; 9!I8 % y : ; 9 I $ > & I 4 : ; 9 I?< 4 G: ; 9 I $ > : ; 9 I 4 : ; 9 I : ; 9 I !I : ; 9 I8 : ; 9 I8 : ; 9 I 4 : ; 9 I I & I .?:!; 9 'I@| .:!; 9!'I@| :!; 9 I .?:! ;9 'I< ! I/ % y $ > ! 4 : ; 9 I?< : ; 9 : ; 9 .?: ; 9 n'I< . ?: ; 9 'I< .?: ; 9 'I< U 'I .: ; 9 '@| !! I/ ".: ; 9 '@z #.: ; 9 'I@z $.: ; 9 'I@z $ > I : ; 9 I !I :!; 9 I 5 I :!; 9 I8 4 :!; 9 I .?: ; 9 'I< :!;! 9 I .?:!; 9!'@| % $ > & I ' 'I : ; 9 4 : ; 9 I?< 4 : ; 9 I 4 G: ; .?: ;9 'I< .: ; 9 'I@| .: ; 9 '@| $ > I : ; 9 I !I .?: ; 9 'I< :!; 9 I8 . ?: ;9 'I< .:!; 9! 'I@| :!;!9 I :!; 9 I % $ > & I 5 I ' 'I : ; 9 4 : ; 9 I?< 4 : ; 9 I 4 G: ; .?: ;9 'I< 4 : ; 9 I .: ; 9 '@| $ > !I I :!; 9 I8 :!;!9 I 4 :!; 9 I . :!; 9! '@| % $ > 5 I & I : ; 9 I 'I : ; 9 4 : ; 9 I?< 4 : ; 9 I 4 G: ; .?: ; 9 'I< .: ; 9 'I@| .: ; 9 '@| ' $ > : ; 9 I8 !I I : ; 9 :!;!9 I % $ > & I : ; 9 I 'I 4 : ; 9 I?< I ! I/ : ; 9 I 4 : ; 9 I 4 G: ; .: ; 9 'I@z : ; 9 I8 ( I I ~ !I : ; 9 I8 : ;9 I8 : ; 9 : ; 9 I8 H } : ; 9 I 4 :!;9 I 1B I : ;9 I H} : ; 9 I :!;9 IB 4 1B ! I/ 'I 1RBX YW :!$;9 I k : ;9 I8 : ;9 I .?: ; 9 'I< I8 : ;9! : ; 9 < 4 : ;9 I :!;9 I !4 :!;9 IB ">! !I: ; 9! #H} $.:!;9 'I@z % : ; 9! & : ; 9 '' ( :!;9 IB )$ > *4 :!; 9 I +! I , : ; 9 I k -.?: ;9 'I< ..?:!;9 'I@z / 1RBUX YW 0( 14 :!;9 IB 2( 3 : ;9 I 4.:!;9 'I ! 5 1 64 :!;9 I 74 1 8& I 9 :!; 9 I : : ;9! ; :! ; 9!I k <.?: ; 9 '< = >H} ?4 :!;9 I @ I A : ; 9 I B !: ; 9! C : ; 9 D : ; 9 I8 E4 1 F.:!; 9!'I@z G :!; 9 IB H.: ; 9 'I ! I7 I J4 : ; 9 I?< K : ;9 I L.?: ;9 '< M. :!;9! 'I ! N U O.:!;9! '@z PH} Q : ; 9 I R.1@z S : ; 9 I T>! !I: ;9! U : ; 9 I!8 V I8 W U X : ; 9! Y : ; 9 Z>! !I: ; 9 [> !I: ;9 \! I/ ] 'I ^! I7! _ !:!);9! ` :!;9! a. ?:! ; 9!'I< b.?:!;9!'@z c.?:!;9!' d.?:!;9!'I e :!;9! f g h4 :!; 9! IB i4 :!; 9!I j 1UX!Y W! k.:!;9!%' ! l.?: ; 9!'I !4 m% n$ > o5 I p q& r : ; 9 s4 : ;9 I?< t( u : ; 9 v : ;9 w5 x < y : ; 9 I 8 z : ;9 {4 G: ;9 |.?: ;9 'I } 1 ~ : ;9 1 H } : ;9 1 4 : ; 9 I 1RBX YW . ?<n . ?<n: ; U ~ . P R i r \ ( 4 ? M Z c { j # - 9 C Q \ m m x v # / > I X f u s I tg?0t& X' X&0 u /u t ttʟ Y1!0u K K1 ?? ftK I Lv tY t tg f=1jf Y9v?D+< ug =3 vf Kt YJ JJYu"h+7f/ JK 1 <<Kuf J f =1 / f1= $t5/> t ; J f[ Y h ~ U . P A i r \ ( u s * 4 ? M Z c { # - 9 C Q \ m m x v 4 j j : : B W a a h t # / > I X f + < M zO # ! @ Kt d tgu Xg t" J JK Xg u wt.> u v t Y\ Y g Z g:.' !YL ' f q@ . !. = o < uR $. X .. Xf/ $. X .. Xf/ $. X .. Xf/ $. X .. Xf/ $. X .. Xf/ $. X .. Xf1" K z) Y[ X Ku J vY[ / K Y uv yX Y1=/t Y UyR Lt }t//h u v Y u <K ;L ;L ( (? 1 Kt$:}t 0 " X gw t $K6 L y <! K1< % v gv X Y gw =\f % v gv X Y <utgw =_ =u6 =u1$ gf K X ..Y "g! g[. % w gZ Xgv =[- v 4\, v 4[ =u1 =u1& v 4[- v 4[& 4 gf K X ..Z 2 20 gZ& v 4[% v 4 u vg M U ~ . P A eX X i g g ( 4 ? M Z \ r c { u s # - 9 C Q \ m m x v * + p # / > I X f z h =1? uv Zu1 uv Zu1 uh K1Y? " K vK[? " K vK[?0 u K11 u w" =2=2t X t- X J X K NS6Z,Z 90 % #Y ~ U L i r \ ( # - 9 C Q \ m m x v j j 4 ? M Z c { u s * # / > I X f :n - t X K ! |ZY ? L\ </ X. <[`.BB <@ _ " &t Y vtYg#t J vY 1 ~ U & i ( 4 ? M Z \ r c { * # / > I X f q Kv ( U ~ r \ M < i ( 4 ? M Z c { r ]$- )g = z J U ~ . P A 2 i u s ( 4 ? M Z \ r c { * C + s gug .K t U ~ > r \ _ > t g4\#t[- %% 9 U ~ > P d m x i r \ > B _ ju #&!tBf#/!tBt#/!fBf#/!tBt0 ~ = X <? .+ J ? g Y n< < =tf X% f (Y . , <+ J ? Y ( w@< < =sf X %u2 . Kj.? g v u K1 #u K1 J X & X L?u K1u K? = gv = ) wt$/ J K1 u K1 u hY2%ff ./1!1 = X / Xh ut/g$ / :N -' J (KiuxKv# <h % & X M / W u v Y f J Ku f J_JZ# ggf <<! K[ uv u X tY t J t& J# ttK t- J* t Z % & X M Zt/< .J J u J)s. XtK V X-' g g tK QD<B H : K[ u1/x t Y 0=1) t) .Y15 t5 XX . X=1 u v& ) X& XX . X=1 11 uv u/ > << KZ<< K v Y1 /& g1M t uv Y vt/$ , . K! r J Yi t XX . X=1y g , t \=1 y I .=2K u t$ K tt/ ' . Ku ( . K K Y5 zt J Y fP . K .K ' YK u tfgY# + . K$ , . KK " z& - X& / [/ Z (K KjJ . K . K =K u tfgY# * . K g( / . KhK y& - X& gK K ] ~ U P d m x i r \ o #&!tBf#/!tBt#/!fBf#/!tBt0 ~ = X <? .+ J ? g Y n< < =tf X% f (Y . , <+ J ? Y ( w@< < =sf X %u2 ~.Y t=? / t X>ju >K3!?1$/1 u vt/5 t < J X J K1 1 J X & X Lt / ! J tZ?u K1 t K? tt .Y1g ~ U P > O i x ' + y< ft,t0f,(J <1 = f g u1 1 o.uw u vK1 <Y < [t/t/& u. J! J XX .Y1Y <! XX .Y4 )1 { Yv& t f Yv f hY2vwtY Xut YwtY Xut Y Y J Lt[& uu [ 5 g X .Y10 j$ J t tJr. g =1t /& t fK7 J .`M t/8 J .ZM /? [$1 /[,#1 tYt/& t fM X $ X> J .4 J . /r 1<v : A X Y J J K tYtY1& f $ XK g xX> z J .4 J . Y Y& t f J X@ " Y v $) X=1uuvtYtYt Yt YtYt ==3 g&v t f K K u tY X .._tY tY utY tY Y6=v vtY tY tY tY @ g&Z t f Kt Y ' "Y' s Z X ' X; Lv t Y X ..0 gY\ & t f K v3t / g= T J . _Y1 /13 $$ g U zY1 vt /6 J, . X h=1 /1 vt /6 J, . X h=1= vt /: ( J 0 X j=111 1Y f g < Yv Y/ wY1/ !@KL YK $Kt1-*>175/x u 9 ~ U P > #0 O m d x 0 i _ ' B M < < < *&(tBf*/(tBt*/(fBf*/(tBt0 f)<< uJ J{< tf ./o. <7< . ft,t0f,(J <1 = f g u,K@ =L/ X + # / # h0 / .z X ' X K7 ;<K R/ /! ]/ .f K/ X/ ? ( - N= t/t K/@=t? u K2 u jN vK1( ? ?wz'3|g! g ? K( d . q& =1Y <MK .MK .M 5 & ~.& ='? t/+ W JO "[ $3x " Y X . Y' < Y <Y2 W hv <YK <YLif Y['/w K K t 8 . Y9 I L vY2 "g u =2 g#vu? Y1 /K1N u t,/$ f, f X JJX% t J t XK1 &$ = tux&w f L uY uvg Xu5 Y2Kg-B7# u J g u g "Zf LtYtM & f Kfg, K thg K w <Y Luf@ u . Y3t*/uv.t/uv ;. ~5 J J t/uv 8" F) J J t<K ' pt < Y]t*/w .t/uvt/ 6/ I J" ~ J t<K ' yt Y[$ 2 L > M=3 u t X Y * Xv vK < Y2 :Z>J(.,J L .( X% Kv K g1. #! g[ Yt /#.& J t \ Yt /'.& J t\!!AK u, f .1vK H .? t KM0?v l& f Y yJ f t=1 =<K K0 ~ U P > m d x i C r \ ) B ' _ 3 %#&!tBf#/!tBt#/!fBf#/!tBt0 J\ %*&(tBf*/(tBt*/(fBf*/(tBt0 Tf #&!tBf#/!tBt#/!fBf#/!tBt0 ~ = X <? .+ J ? g Y n< < =tf X% f (Y . , <+ J ? Y ( w@< < =sf X %u2 .%*&=b Ku? t!2 tu vt g w Yi tY ! LYu 1? <( K?t?" t1 ) 0 6 X0 XX . X=1 <K1 * X' K?047t t tXYt tXY K : Y w KoX4 !tw# J f J J f J < Y u t'.J < % & X L { # K wY1 K v . M #3t"tuftf>%2t- <v. t$ J Yt <)1t>t9<t= u g u '=#< tXt gu g h t KX Kw<K #<K K2 << J=1 << J=. %6 K }.#8!B#/!B#/!B#/!B0$ <g}/#8!B#/!B#/!B#/!B0$ J}/#8!B#/!B#/!B#/!B0$ J! / }(#8!tBf#/!tBt#/!fBf#/!tBt0 <g}-#8!B#/!B#/!B#/!B0$ J}/#8!B#/!B#/!B#/!B0$ Jv})#8!tBf#/!tBt#/!fBf#/!tBt0 Ju})#8!tBf#/!tBt#/!fBf#/!tBt0 J x}(#8!tBf#/!tBt#/!fBf#/!tBt0 < g})#8!tBf#/!tBt#/!fBf#/!tBt0 Ju u}'#8!tBf#/!tBt#/!fBf#/!tBt0 Jv "z }( }#/!tBf#/!tBt#/!fBf#/!tBt0 < < , K M Y l @ U i 1 S U ' i D Y X1u K1 =? X ~ U i = /0 fg IM t tZ uh z t < (K4 gg1 / t tZ uhz tK4 hg { ~ U . P A o @ N W i r \ j z j m * ( C + u s # - 9 Q \ m m x v j j # / > I X f z 4 ? M Z c { + Jt> < X X tX#];Y J/ f h X < X X < <" X X wL ~f tt ~X < ~<J t ~ = L ~ t ~tt t ~ ft < J w(> t ~ t t ~f *!0 XQKpNSK MX 1 9 Q -1 X K} 3 E] UKi XZ<tI X[^ tJ .%<%<< Xu! XNKpx AX p Kt ]z& XxX K ?N8=Zd>Y L t ~t tY < ~X[ XX "fKo " y p@ 8 ! t t(< < > g! I J XZJo X Z > <%z#Y Y\f< YVYIJY<< tY[] XYt YV t <.X y ~ U . P A 6 6 N @ W = i r \ g j g + ( 4 ? M Z c { u s # - 9 C Q \ m m x v * + D D N _ n j j # / > I X z f z m )K <<JJX @ 0: itK b Z} sYYY } eY t J. X<0 !d d<X Z V < <z YW XFZ$$ \J dJ f d< YJXf<< < ; J. dX$ vX <~ Jt> < X X tX#];YzJKI.=<Y = X . rh J gJX=Ze IK IJK X. < Z:= Y J< X tb ~<~J Xf < X M~Z ~ t ~tt X ~ U K # Y \ f >Ȑ r it [ ~K whJ . .u fv X HYJ .K J) s X X2J0JJ I f\ . . J/JYM.H% 9 f` .Y LI <et V X f [K J fIut J 6 JKKV X$KxJR W$J'<xXf Y Iu " J f> Kfk; YYI X Ku# HL : KsX=X> <i = K xJ Z KvIg....-lY Xi = FZ x ZtK i M GU 0 . .$J$. =# d f [ I . .K%J%. =$ d f\ ~ X~ . }<!> J.~ ~ < ~JX J ~J ~X ~ .X~ ." <" < ~< J> J.~ ~ f.. i 3K JY s < t tY M HZ X I/ ~ ~ U . P r m r \ j ( m x v i u s # - 9 C Q \ 4 ? M Z c { N W . = I V e v K # / > I X z f z 6KK柟uIe \t<3 = < + <K)K t t w.<Y柟u/ X RK%Ku)Xt <K X Mxxtvquv X ] XL <K < <. L)tKKM[. f X} , E ~ U . P A e" " N @ W i r \ 2 j m * ( C + u s 4 ? M Z c { # - 9 Q \ m m x v B K W ^ Q ` K J{( {JDt ( {D' D X f( 9 JJ.' {& XD < < ( {D <( KYMJ/Y" Iz" z.B." z. KA )K xJ( wJ Kv.N < JL JX f{ {t= H={ .> J X{ f .> .vJ {tg {Xt {f .<tz "z zJ. z t z X z. z.{ . . <> Y J{ J zJ z X zJ < K; {tK {Xt {. . <dt <k{ f I .= tz { zt zXtiz Jt> < X X tX#];Y J w Zus<Yy X w y-JyJ X yJt y,fyJ J X f yt yJfy. < yJX tY t J < tg ' JK' I Q < g= y<8J<yJ 8J yJ<< yJ X q J Yy y<f y< 5( ! ( J <f.t H! y Q: y<( J > < L KWY J X)< )X JPG?Jca)qM)U N X X X 2)qM)U W J! t X+ ( [Y: ( ! M =( * X [ X y q>;Z3 IK <tX.X <tX <Xt XO7.=J f < JL ."Y B< > B >J . < ~3o J t <X <"<} <K JL;Z$ ~ ; <6 JJG I =W= t 3t Jt< X^% ~ t<XtV :+ 3 J< XvD tfXq :+f JY> ~J% ~X X/ <Mt" J. X \/ . X <g'.4 X J J= igJ r6 JY?K)J>\ < ~J% ~ gX ~J% ~ J KX ~J% ~ "J KXS ~J% ~ <JJ.^J<J= J ~J% } J KX JY> .X1 <~ G t .X X8+ X mX Xh XX 3 J< . x<9 I m Xe XXX C X }X .t Gf ~ J* ~ ~ ; <6 JJG I Ig J J ~ ; <6 JJG I Ig J J } ; <6 JJG I Ig J J ~ ; <6 JJG I Ig J J } ; <6 JJG I Ig J J ~ ; <6 JJG I g JJ J MX eX ~ ; <6 JJG I Ig J J u Xo Ju + ~XD XX X` E t .X X JXJXJXJXJX Z tXXb C t .XXKJXJXVt}t X X~<fg O*VJ,y_L z>z X Z <=z K<K y<-.yJ tX yJt y,<yJ < XK I . yt yJy. < yJX xJ t J[x < X x KxX J< < X )rJ )< JJ<tmX)V )< JKY xX}Jt' X ~|/G |<JW/M |./ |</ |</> |. |. < ~# 5#yJu | K</JKJ YZ D{ {<f {J X#<9 ~0 X K ~J .- Jm JX(<%J K;KtK z* J X3WK< X ~1 J J JJ} = X* . X J < D䂺 =4 #~| Ȃ < X -Jh$ . tK <X<䂺 ~ X ~ X <i| f X JZ| - -< J . J J~ f- -J JY$ . tK 5t ~ ~t| tXft X < { <~ t t ~ <{JX$ J {X <~{ ~Xt t ~[{J| f ] { t ~ t t ~[X < 6X X : s Kt <s| f f. /{ {JX% J X{ < "< X! #9 };g& uȐ~ } X }J = * o: JK] JJX K =& 1f~ <)X2 X2f < t| . |X f|J * < t < X Zt< XJ~} < X -X t0O-K/JYOsX XvX -N t } F }t t J . }t. }f< Y-M < J-5Ȃ-K );X X|XKI=/0=;JX~#X-K t5-KJ XX_X-Pt5J} \ EX|JXd 7X-{ t5J-K.5J {tJY{ {JX ?G~~XJX XXX#} t<X\dK f.X , KKLM3 z e .uf .Kr <w Jv J # 'H '< JJ <.. q<JX Y# 'H '< JK fKJ.. Kf k- J # 'H '< J JX<... bXJX Y# 'H '< JK f -K-I JJ. q 5 ~ U . P A f @ N f t W i r \ } + # / ( > I X z f z # - 9 C Q \ m m x v j j j * + u s p . = I V e v K 4 ? M Z c { m . Xt> < X tX /];YQ v. vJ= J < < Ju X=J < <YM J X X J V J J ;[ wJ f ? f < < / sJ f\ yJ X 7@K .N u JY/ J tVBb. ..but Jb. X.but Jb. X.buu ; X= < < t wf J J t f~ X L <L Z < dJ <hJY.# L < fvH.XL.$Xf W < = L M f X .[ < tXX XKZx< Mt( J a W Z KW. f L W[ = `= F J X .[ < tXX XK> Ht W Z KW. f L W[ = `XK =YM e = X 7 z ~.J r~ ~< < ~ K)A/);-< Y j ~ U . P A w @ N i r \ ( . x v = I V e v K # / > I X z f z u s # - 9 C Q \ m m 4 ? M Z c { m * + P8 Jt> < X X tX#];Y H 0 r&J= O t< J J < g <JX=Z d = IJ J ;KX<0gX .<nK&!<&tJ= j<XJM hK 4 [ b X : K eXjJ t J J < g <JX=Z d u sJ t sKX<0I X @ 8 j a ~ U P . A i i % ( C m * + # - 9 Q \ m m x v u s # / > I X f 4 ? M Z \ r c { j j p; 2fK KK1fK KKf. ! @ Kt d tgu Xg t" J JK Xg u wt.> u v t Y\ Y g Z g6L g f gt t < f gt#t < f gt#t < gvYqJX. 1= f1 fX .Y1 = f fX . X=1 fe0"3< hf K_ YZ g Y Z /K ) >/ g t# g \ + ~ . h$ i/< ii.v g"== Y j + ~ . } % i=/ XeY[.v g " X v Y @ + ' hY!h "KYYgi.vg #ZV/ #Y w 7 + x( t tJtt o ( + h ~ U P H ` \_ _ \ N # W i - C r \ 1 : G V e \ s > ~ x ) j I ) # + 4 = M V ] f q y % X % {\pF@pJ XN IK1. z.z G Y #G X .[ I . X.. [J J < JYj Jt.{XJY } J= Iu .4f\pJ,ttv Xj IK1. zXz G Y #G X .[ I . X..lJY | J= Iu .~f ~X ~f~ ~J<. P I=ZXzf 4~ X JJ J X M I=ZXz 4 ]X# ]J#J ]J 'tO I=ZXzt 4~4 X tX JJ J8 t I=ZXz 4!t J j/ Ig . sqa <Y I= t [CK{IyJ= JK = ;Kf* W X3t.O-&< J> JL K XZ X=!} JV+J<Y == HK~ . X7 $ y XX @% [q w 2 t t X % Ys u > $ tXX % YW<fDt;tDt%V;<E qt tYxnrmkf<Y /< _!t `xtxJw pu jY L JYL77A XO%~vX1(.<z qJ[JY { J= Iu . foJ XM LK /. zz EkoJ XM%}X1(. }J ;L;gZ < xR]oEAoJv XMy<QX/O Y.at JVJY z J= Iu . f`xt|x<(xtJu X hXd< &* tX |0/;0Y; = X|t e X^L K%}$| J M J gfX< k%}$| J %|vt1(J } J g%|.J .X= * Ju ) i z <O%~ M J Y < ~JX* t.v%~$| M JX X... ;~X tYIt XO%|vX1(.ttP~]oEAJtv XNx<R XuJ%}vX1(..z J wt <wttX 0 ,N!v kX .Xnt y# yt|#;)s!s sssss|Y ~ $ | % { su $X z su )X %z1(n"%z1(n"%z1(n"%z1(nZ%z1(nZ%z1(n%z1(nZ%z1(n"%z1(nZ%z1(nZ%z1(nZ%z1(nZ%z1(nZ 0 & & J JY Z%z$| J M J g XY\f @t & t@ @@X & P& t & t & X & P& t & t & t & _SC_MAPPED_FILES _SC_MAPPED_FILES __S_TYPEISSEM(buf) ((buf)->st_mode - (buf)->st_mode) _SC_XOPEN_LEGACY _SC_XOPEN_LEGACY __ldiv_t_defined 1 _POSIX_THREADS 200809L __S_IFDIR 0040000 __FLT64X_HAS_QUIET_NAN__ 1 __FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__ __UINT16_MAX__ 0xffff __SIZEOF_PTHREAD_CONDATTR_T 4 __ILP32_OFF32_CFLAGS "-m32" __OPEN_NEEDS_MODE(oflag) (((oflag) & O_CREAT) != 0 || ((oflag) & __O_TMPFILE) == __O_TMPFILE) __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 _unused2 _CS_POSIX_V7_ILP32_OFFBIG_LINTFLAGS _CS_POSIX_V7_ILP32_OFFBIG_LINTFLAGS _SC_SIGSTKSZ _SC_SIGSTKSZ _SC_LINE_MAX _SC_LINE_MAX _SC_XOPEN_XCU_VERSION _SC_XOPEN_XCU_VERSION __FLT32_DIG__ 6 _WCHAR_T_DEFINED ESPIPE 29 _fileno __glibc_has_attribute(attr) __has_attribute (attr) _SC_CLK_TCK _SC_CLK_TCK _SC_ARG_MAX _SC_ARG_MAX _SC_V7_ILP32_OFFBIG _SC_V7_ILP32_OFFBIG __ASMNAME(cname) __ASMNAME2 (__USER_LABEL_PREFIX__, cname) EMEDIUMTYPE 124 __FLT64_MANT_DIG__ 53 __GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION _SC_BC_SCALE_MAX _SC_BC_SCALE_MAX __FLT_MAX_10_EXP__ 38 __SQUAD_TYPE long int __USE_MISC 1 __LITTLE_ENDIAN 1234 _POSIX_MESSAGE_PASSING 200809L F_SHLCK 8 _XOPEN_XPG2 1 __INT32_C(c) c __INT_LEAST64_WIDTH__ 64 _SC_XBS5_LPBIG_OFFBIG _SC_XBS5_LPBIG_OFFBIG R_OK 4 _POSIX_ASYNC_IO 1 _BITS_ENDIAN_H 1 _SC_GETGR_R_SIZE_MAX _SC_GETGR_R_SIZE_MAX __fortify_function __extern_always_inline __attribute_artificial__ __DEC64_MIN_EXP__ (-382) __FLT64_MIN_10_EXP__ (-307) WNOWAIT 0x01000000 __ATOMIC_HLE_RELEASE 131072 __PTRDIFF_MAX__ 0x7fffffffffffffffL ETOOMANYREFS 109 _SC_PII_INTERNET_DGRAM _SC_PII_INTERNET_DGRAM __WCHAR_TYPE__ int __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 __STDC__ 1 _STATBUF_ST_RDEV __LDBL_REDIR(name,proto) name proto _SC_PAGE_SIZE _SC_PAGESIZE __UINT_FAST16_MAX__ 0xffffffffffffffffUL __DEC128_MIN_EXP__ (-6142) ERFKILL 132 __LEAF_ATTR __attribute__ ((__leaf__)) POLLHUP 0x010 __DBL_MAX_10_EXP__ 308 __attribute_warn_unused_result__ __attribute__ ((__warn_unused_result__)) _SC_NETWORKING _SC_NETWORKING _SC_LEVEL4_CACHE_LINESIZE _SC_LEVEL4_CACHE_LINESIZE __API_FD_ARRAY__ _SC_RTSIG_MAX _SC_RTSIG_MAX __getc_unlocked_body(_fp) (__glibc_unlikely ((_fp)->_IO_read_ptr >= (_fp)->_IO_read_end) ? __uflow (_fp) : *(unsigned char *) (_fp)->_IO_read_ptr++) _SC_PII_XTI _SC_PII_XTI __GLIBC_USE_DEPRECATED_GETS 1 __ELF__ 1 __LDBL_DIG__ 18 ENOTSUP EOPNOTSUPP __USE_DYNAMIC_STACK_SIZE _POSIX_SPAWN 200809L EWOULDBLOCK EAGAIN _XOPEN_VERSION 700 priv ENOBUFS 105 __WCHAR_T__ EBADE 52 _STDLIB_H 1 _SC_SYSTEM_DATABASE_R _SC_SYSTEM_DATABASE_R __need___va_list EMULTIHOP 72 EMFILE 24 _ASM_GENERIC_ERRNO_BASE_H fdarray_flag__non_perf_event __putc_unlocked_body(_ch,_fp) (__glibc_unlikely ((_fp)->_IO_write_ptr >= (_fp)->_IO_write_end) ? __overflow (_fp, (unsigned char) (_ch)) : (unsigned char) (*(_fp)->_IO_write_ptr++ = (_ch))) _SC_2_PBS_CHECKPOINT _SC_2_PBS_CHECKPOINT __DBL_HAS_INFINITY__ 1 __REDIRECT_NTH(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __THROW _CS_XBS5_LP64_OFF64_LINTFLAGS _CS_XBS5_LP64_OFF64_LINTFLAGS _SC_PRIORITIZED_IO _SC_PRIORITIZED_IO __FLT_HAS_INFINITY__ 1 __FLT16_MAX__ 6.55040000000000000000000000000000000e+4F16 __FLT128_MIN_10_EXP__ (-4931) _XOPEN_SHM 1 _BITS_BYTESWAP_H 1 __FD_SETSIZE 1024 __STD_TYPE typedef __THROWNL __attribute__ ((__nothrow__)) __FLT16_EPSILON__ 9.76562500000000000000000000000000000e-4F16 _SC_POLL _SC_POLL EILSEQ 84 __BFLT16_DENORM_MIN__ 9.18354961579912115600575419704879436e-41BF16 _SC_SIGNALS _SC_SIGNALS calloc EXDEV 18 fdarray__dup_entry_from __off_t _PC_PATH_MAX _PC_PATH_MAX ENFILE 23 S_IXGRP (S_IXUSR >> 3) __U32_TYPE unsigned int __struct_FILE_defined 1 _IO_USER_LOCK 0x8000 _CS_POSIX_V7_LPBIG_OFFBIG_LIBS _CS_POSIX_V7_LPBIG_OFFBIG_LIBS S_IRGRP (S_IRUSR >> 3) EADV 68 __DEV_T_TYPE __UQUAD_TYPE _POSIX_RAW_SOCKETS 200809L SEEK_SET 0 EISNAM 120 __GLIBC_USE_IEC_60559_BFP_EXT_C23 0 __USE_MISC __UINT_FAST64_MAX__ 0xffffffffffffffffUL __FLT16_HAS_DENORM__ 1 __BFLT16_HAS_INFINITY__ 1 _PC_NO_TRUNC _PC_NO_TRUNC _SC_BC_STRING_MAX _SC_BC_STRING_MAX _VA_LIST_DEFINED __DEC128_MANT_DIG__ 34 __nlink_t_defined __SHRT_MAX__ 0x7fff _POSIX_SHELL 1 _POSIX_VDISABLE '\0' __INTPTR_TYPE__ long int __FLT_IS_IEC_60559__ 1 __wchar_t__ __FLT32_DENORM_MIN__ 1.40129846432481707092372958328991613e-45F32 ETXTBSY 26 O_SYNC 04010000 __USE_XOPEN_EXTENDED _POSIX_THREAD_PRIO_INHERIT 200809L _POSIX_V6_LPBIG_OFFBIG -1 POLLWRBAND 0x200 L_tmpnam 20 __MODE_T_TYPE __U32_TYPE __f64x(x) x ##f64x __INT_LEAST64_TYPE__ long int __INT32_MAX__ 0x7fffffff __FLT128_MIN__ 3.36210314311209350626267781732175260e-4932F128 __attribute_overloadable__ O_EXCL 0200 _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS _SC_EQUIV_CLASS_MAX _SC_EQUIV_CLASS_MAX __GCC_ATOMIC_CHAR_LOCK_FREE 2 POSIX_FADV_DONTNEED __POSIX_FADV_DONTNEED __FLT128_MANT_DIG__ 113 __UINT_FAST32_TYPE__ long unsigned int O_RDONLY 00 _SC_SINGLE_PROCESS _SC_SINGLE_PROCESS _CS_POSIX_V6_ILP32_OFF32_CFLAGS _CS_POSIX_V6_ILP32_OFF32_CFLAGS __INO_T_MATCHES_INO64_T 1 __SIZEOF_INT__ 4 O_NOFOLLOW __O_NOFOLLOW __glibc_c99_flexarr_available 1 __FLT32X_MAX_10_EXP__ 308 POSIX_FADV_RANDOM 1 S_IWOTH (S_IWGRP >> 3) __SIG_ATOMIC_TYPE__ int _BSD_SIZE_T_DEFINED_ __BIGGEST_ALIGNMENT__ 16 __FLT16_NORM_MAX__ 6.55040000000000000000000000000000000e+4F16 __INT_FAST16_WIDTH__ 64 __BFLT16_MAX__ 3.38953138925153547590470800371487867e+38BF16 _SC_V6_ILP32_OFFBIG _SC_V6_ILP32_OFFBIG __UINT16_C(c) c __F_GETSIG 11 F_SETFL 4 _SYS_SELECT_H 1 ENOTEMPTY 39 __HAVE_DISTINCT_FLOAT128 1 __pic__ 2 __NFDBITS (8 * (int) sizeof (__fd_mask)) __S_IFLNK 0120000 __DADDR_T_TYPE __S32_TYPE __SCHAR_MAX__ 0x7f _XOPEN_XPG3 1 F_GETFL 3 ___int_wchar_t_h __HAVE_SPECULATION_SAFE_VALUE 1 L_SET SEEK_SET _SC_THREAD_DESTRUCTOR_ITERATIONS _SC_THREAD_DESTRUCTOR_ITERATIONS __FLT16_DENORM_MIN__ 5.96046447753906250000000000000000000e-8F16 __UINTPTR_TYPE__ long unsigned int _BITS_STAT_H 1 _SC_TIMEOUTS _SC_TIMEOUTS __DBL_EPSILON__ ((double)2.22044604925031308084726333618164062e-16L) __bswap_constant_32(x) ((((x) & 0xff000000u) >> 24) | (((x) & 0x00ff0000u) >> 8) | (((x) & 0x0000ff00u) << 8) | (((x) & 0x000000ffu) << 24)) _POSIX_VERSION 200809L __SIZE_MAX__ 0xffffffffffffffffUL S_IXOTH (S_IXGRP >> 3) __FLT32X_MAX__ 1.79769313486231570814527423731704357e+308F32x _POSIX2_C_BIND __POSIX2_THIS_VERSION __always_inline __UINT8_TYPE__ unsigned char __HAVE_FLOAT16 0 S_IROTH (S_IRGRP >> 3) __USE_LARGEFILE64 1 __FLT32_MIN_10_EXP__ (-37) EBADRQC 56 _POSIX_PRIORITY_SCHEDULING 200809L __FLT128_MIN_EXP__ (-16381) __SIZEOF_PTHREAD_MUTEX_T 40 __INT_LEAST16_MAX__ 0x7fff _LFS_LARGEFILE 1 S_IRWXO (S_IRWXG >> 3) _PC_SOCK_MAXBUF _PC_SOCK_MAXBUF __LDBL_DECIMAL_DIG__ 21 _SC_THREADS _SC_THREADS _IO_write_end _POSIX_THREAD_PROCESS_SHARED 200809L _SC_TRACE_SYS_MAX _SC_TRACE_SYS_MAX __UINT16_TYPE__ short unsigned int __F_SETSIG 10 _CS_LFS_LINTFLAGS _CS_LFS_LINTFLAGS _SC_TTY_NAME_MAX _SC_TTY_NAME_MAX _CS_POSIX_V7_LPBIG_OFFBIG_LINTFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_LINTFLAGS le32toh(x) __uint32_identity (x) __STDC_IEC_559__ 1 _BITS_UINTN_IDENTITY_H 1 __attribute_malloc__ __attribute__ ((__malloc__)) __UWORD_TYPE unsigned long int EREMOTE 66 _T_SIZE_ _SC_V7_LPBIG_OFFBIG _SC_V7_LPBIG_OFFBIG _SC_ADVISORY_INFO _SC_ADVISORY_INFO htobe64(x) __bswap_64 (x) __FLT32X_HAS_INFINITY__ 1 O_FSYNC O_SYNC ENETDOWN 100 __FD_ISSET(d,s) ((__FDS_BITS (s)[__FD_ELT (d)] & __FD_MASK (d)) != 0) _SC_LEVEL1_ICACHE_SIZE _SC_LEVEL1_ICACHE_SIZE __glibc_objsize(__o) __bos (__o) __FLT16_IS_IEC_60559__ 1 __UINT64_MAX__ 0xffffffffffffffffUL __INT8_C(c) c __stub_chflags __FLT16_MAX_EXP__ 16 __FLT32_HAS_INFINITY__ 1 ____mbstate_t_defined 1 EINVAL 22 __WCOREDUMP(status) ((status) & __WCOREFLAG) _SC_LEVEL1_DCACHE_ASSOC _SC_LEVEL1_DCACHE_ASSOC __FLT_MAX_EXP__ 128 __ATOMIC_SEQ_CST 5 EIDRM 43 _GCC_SIZE_T __stub_setlogin __HAVE_FLOAT128X 0 _IO_read_end _SC_PAGESIZE _SC_PAGESIZE LOCK_SH 1 _CS_V6_WIDTH_RESTRICTED_ENVS _CS_V6_WIDTH_RESTRICTED_ENVS _SC_2_PBS_LOCATE _SC_2_PBS_LOCATE st_ctime st_ctim.tv_sec __FLT32_MANT_DIG__ 24 __stub_stty __WORDSIZE 64 __GLIBC_USE_LIB_EXT2 __FLT64X_IS_IEC_60559__ 1 __attr_access(x) __attribute__ ((__access__ x)) _CS_LFS_LDFLAGS _CS_LFS_LDFLAGS _POSIX_SPORADIC_SERVER -1 ELIBEXEC 83 _SC_LEVEL1_ICACHE_ASSOC _SC_LEVEL1_ICACHE_ASSOC __INT_LEAST8_WIDTH__ 8 __uid_t_defined ENOTNAM 118 LOCK_NB 4 ESRCH 3 ECONNRESET 104 _XBS5_LPBIG_OFFBIG -1 _POSIX_SYNCHRONIZED_IO 200809L revents S_IFMT __S_IFMT _SC_2_FORT_DEV _SC_2_FORT_DEV __WIFSIGNALED(status) (((signed char) (((status) & 0x7f) + 1) >> 1) > 0) __GCC_IEC_559_COMPLEX 2 F_SETLK F_SETLK64 __S32_TYPE int _SC_TYPED_MEMORY_OBJECTS _SC_TYPED_MEMORY_OBJECTS __FLT16_HAS_QUIET_NAN__ 1 __O_TMPFILE (020000000 | __O_DIRECTORY) __USER_LABEL_PREFIX__ S_IFLNK __S_IFLNK _SIZE_T_DECLARED __BITINT_MAXWIDTH__ 65535 __DECIMAL_DIG__ 21 __GLIBC_USE_LIB_EXT2 0 __UINT_LEAST32_MAX__ 0xffffffffU _BITS_TYPESIZES_H 1 _CS_POSIX_V6_ILP32_OFFBIG_LDFLAGS _CS_POSIX_V6_ILP32_OFFBIG_LDFLAGS __FLT16_MIN_10_EXP__ (-4) __USE_TIME_BITS64 1 P_tmpdir "/tmp" _POSIX2_VERSION __POSIX2_THIS_VERSION __attribute_format_arg__(x) __attribute__ ((__format_arg__ (x))) EL2HLT 51 _SC_XOPEN_VERSION _SC_XOPEN_VERSION __ino_t_defined __BFLT16_DECIMAL_DIG__ 4 BYTE_ORDER __BYTE_ORDER _SC_TRACE _SC_TRACE __GLIBC_USE_C23_STRTOL 0 __DEC_EVAL_METHOD__ 2 __GLIBC_USE_IEC_60559_TYPES_EXT EBADF 9 __LP64_OFF64_LDFLAGS "-m64" __FLT32_MIN_EXP__ (-125) _POSIX_JOB_CONTROL 1 F_ULOCK 0 _BITS_ENDIANNESS_H 1 POLLWRNORM 0x100 fdarray__filter __O_LARGEFILE 0 alloca MB_CUR_MAX (__ctype_get_mb_cur_max ()) _BITS_STRUCT_STAT_H 1 __timeval_defined 1 _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS _CS_V7_WIDTH_RESTRICTED_ENVS __FLT32X_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F32x __FLT_MIN_10_EXP__ (-37) _CS_POSIX_V6_LP64_OFF64_CFLAGS _CS_POSIX_V6_LP64_OFF64_CFLAGS _CS_XBS5_LPBIG_OFFBIG_LDFLAGS _CS_XBS5_LPBIG_OFFBIG_LDFLAGS F_SETLKW F_SETLKW64 _POSIX_SPIN_LOCKS 200809L __CFLOAT32X _Complex _Float32x __INT_FAST64_MAX__ 0x7fffffffffffffffL _POSIX2_CHAR_TERM 200809L __DBL_MANT_DIG__ 53 _SC_THREAD_CPUTIME _SC_THREAD_CPUTIME __WCHAR_MIN__ (-__WCHAR_MAX__ - 1) ENOSR 63 _UNISTD_H 1 __k8 1 __USE_POSIX 1 _XOPEN_XPG4 1 __USE_POSIX _SC_WORD_BIT _SC_WORD_BIT __INT_WCHAR_T_H __gid_t_defined __LDBL_NORM_MAX__ 1.18973149535723176502126385303097021e+4932L ENODEV 19 __DEC32_EPSILON__ 1E-6DF __O_PATH 010000000 __INTPTR_MAX__ 0x7fffffffffffffffL _CS_POSIX_V6_WIDTH_RESTRICTED_ENVS _CS_V6_WIDTH_RESTRICTED_ENVS _SC_DEVICE_SPECIFIC _SC_DEVICE_SPECIFIC __glibc_macro_warning(message) __glibc_macro_warning1 (GCC warning message) __USE_ISOC99 1 __FD_ZERO(s) do { unsigned int __i; fd_set *__arr = (s); for (__i = 0; __i < sizeof (fd_set) / sizeof (__fd_mask); ++__i) __FDS_BITS (__arr)[__i] = 0; } while (0) _POSIX_SOURCE __size_t __WINT_MAX__ 0xffffffffU EBADFD 77 _SC_SPIN_LOCKS _SC_SPIN_LOCKS FD_SET(fd,fdsetp) __FD_SET (fd, fdsetp) __FLT_EPSILON__ 1.19209289550781250000000000000000000e-7F AT_FDCWD -100 __BFLT16_HAS_QUIET_NAN__ 1 _CS_POSIX_V6_LPBIG_OFFBIG_LIBS _CS_POSIX_V6_LPBIG_OFFBIG_LIBS __errordecl(name,msg) extern void name (void) __attribute__((__error__ (msg))) _CS_POSIX_V6_ILP32_OFFBIG_LIBS _CS_POSIX_V6_ILP32_OFFBIG_LIBS WIFSTOPPED(status) __WIFSTOPPED (status) __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 __CET__ 3 __UINT_LEAST64_MAX__ 0xffffffffffffffffUL __GLIBC_USE_IEC_60559_BFP_EXT _chain __glibc_likely(cond) __builtin_expect ((cond), 1) __UINT8_C(c) c fdarray__delete __mode_t_defined O_RDWR 02 __FLT32_MAX__ 3.40282346638528859811704183484516925e+38F32 __f32x(x) x ##f32x _SC_XOPEN_XPG3 _SC_XOPEN_XPG3 ERESTART 85 _SC_THREAD_THREADS_MAX _SC_THREAD_THREADS_MAX _SC_XOPEN_CRYPT _SC_XOPEN_CRYPT __INTMAX_TYPE__ long int S_ISUID __S_ISUID __amd64 1 __SEG_GS 1 __HAVE_GENERIC_SELECTION 1 _SC_THREAD_ROBUST_PRIO_PROTECT _SC_THREAD_ROBUST_PRIO_PROTECT __ORDER_LITTLE_ENDIAN__ 1234 _SC_MQ_PRIO_MAX _SC_MQ_PRIO_MAX _IO_lock_t _SC_LEVEL2_CACHE_ASSOC _SC_LEVEL2_CACHE_ASSOC __FLT_DIG__ 6 E2BIG 7 __S_ISVTX 01000 _CS_POSIX_V7_ILP32_OFFBIG_LIBS _CS_POSIX_V7_ILP32_OFFBIG_LIBS POLLIN 0x001 __DBL_MAX_EXP__ 1024 _STATBUF_ST_NSEC __USE_ISOC95 __USE_ISOC99 __UINT_LEAST16_MAX__ 0xffff _PC_CHOWN_RESTRICTED _PC_CHOWN_RESTRICTED _POSIX_THREAD_SAFE_FUNCTIONS 200809L __FLT32X_MAX_EXP__ 1024 _SC_MULTI_PROCESS _SC_MULTI_PROCESS __SIG_ATOMIC_MAX__ 0x7fffffff ENXIO 6 __SIZEOF_SIZE_T__ 8 __DEC128_MAX__ 9.999999999999999999999999999999999E6144DL __SIZEOF_PTHREAD_RWLOCKATTR_T 8 _BITS_STDINT_INTN_H 1 __x86_64__ 1 _CS_GNU_LIBC_VERSION _CS_GNU_LIBC_VERSION __REDIRECT_LDBL(name,proto,alias) __REDIRECT (name, proto, alias) __PTRDIFF_WIDTH__ 64 BIG_ENDIAN __BIG_ENDIAN __USE_XOPEN2K __USE_POSIX199506 __NTH(fct) __attribute__ ((__nothrow__ __LEAF)) fct __unix__ 1 _SC_SCHAR_MAX _SC_SCHAR_MAX __LDBL_MIN__ 3.36210314311209350626267781732175260e-4932L EDESTADDRREQ 89 be64toh(x) __bswap_64 (x) F_DUPFD_CLOEXEC 1030 _PC_SYNC_IO _PC_SYNC_IO _BITS_POSIX_OPT_H 1 __UINT_LEAST64_TYPE__ long unsigned int _CS_XBS5_ILP32_OFF32_LDFLAGS _CS_XBS5_ILP32_OFF32_LDFLAGS __wur __DBL_DECIMAL_DIG__ 17 __SIZEOF_LONG_LONG__ 8 __NTHNL(fct) __attribute__ ((__nothrow__)) fct __WIFCONTINUED(status) ((status) == __W_CONTINUED) __FLT64X_MAX_10_EXP__ 4932 __FLT32_DECIMAL_DIG__ 9 _SC_STREAMS _SC_STREAMS _POSIX_THREAD_CPUTIME 0 _SC_THREAD_KEYS_MAX _SC_THREAD_KEYS_MAX __clock_t_defined 1 _DEFAULT_SOURCE 1 _WCHAR_T_DEFINED_ _SC_NL_ARGMAX _SC_NL_ARGMAX __FSWORD_T_TYPE __SYSCALL_SLONG_TYPE _SC_RE_DUP_MAX _SC_RE_DUP_MAX __FLT128_MAX_10_EXP__ 4932 _SC_SYSTEM_DATABASE _SC_SYSTEM_DATABASE _SC_ATEXIT_MAX _SC_ATEXIT_MAX _POSIX_V6_LP64_OFF64 1 fdarray_flags _POSIX_MEMLOCK 200809L __THROW __attribute__ ((__nothrow__ __LEAF)) __intptr_t_defined __INT16_MAX__ 0x7fff __LDBL_REDIR1(name,proto,alias) name proto __FLT_MANT_DIG__ 24 __W_STOPCODE(sig) ((sig) << 8 | 0x7f) __glibc_objsize0(__o) __bos0 (__o) _POSIX2_C_VERSION __POSIX2_THIS_VERSION ENOTSOCK 88 __FLT64_HAS_QUIET_NAN__ 1 __UQUAD_TYPE unsigned long int AT_REMOVEDIR 0x200 __USE_XOPEN2K8XSI __timer_t_defined 1 _SC_THREAD_PRIORITY_SCHEDULING _SC_THREAD_PRIORITY_SCHEDULING EDEADLK 35 __SIZE_WIDTH__ 64 __need___va_list ELIBSCN 81 __HAVE_DISTINCT_FLOAT16 __HAVE_FLOAT16 __TIMESIZE __WORDSIZE __INT_LEAST8_MAX__ 0x7f _IO_write_ptr __FLT_MIN_EXP__ (-125) __FLT64X_EPSILON__ 1.08420217248550443400745280086994171e-19F64x __dev_t_defined _LARGEFILE64_SOURCE 1 __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ ____sigset_t_defined __FLT_RADIX__ 2 __BFLT16_MIN_EXP__ (-125) EPROTO 71 __LDBL_IS_IEC_60559__ 1 __FLT32X_DIG__ 15 _SC_PII_INTERNET _SC_PII_INTERNET __LDBL_REDIR1_NTH(name,proto,alias) name proto __THROW _POSIX_FSYNC 200809L __FLT_EVAL_METHOD_TS_18661_3__ 0 _SC_XOPEN_REALTIME _SC_XOPEN_REALTIME _SC_XOPEN_XPG4 _SC_XOPEN_XPG4 ECHILD 10 EBADR 53 __DEC128_MAX_EXP__ 6145 _POSIX2_SW_DEV __POSIX2_THIS_VERSION __HAVE_DISTINCT_FLOAT64 0 _SC_MB_LEN_MAX _SC_MB_LEN_MAX __FLT128_MAX__ 1.18973149535723176508575932662800702e+4932F128 __O_CLOEXEC 02000000 _SC_2_PBS_ACCOUNTING _SC_2_PBS_ACCOUNTING __DEC32_SUBNORMAL_MIN__ 0.000001E-95DF __KERNEL_STRICT_NAMES __COMPAR_FN_T __UINTMAX_TYPE__ long unsigned int __U64_TYPE unsigned long int __FLT32X_MANT_DIG__ 53 _BITS_TIME64_H 1 __ONCE_ALIGNMENT POLLOUT 0x004 __UINT_FAST8_TYPE__ unsigned char __CHAR32_TYPE__ unsigned int __ID_T_TYPE __U32_TYPE __INT_WIDTH__ 32 FFSYNC O_FSYNC __UINT64_TYPE__ long unsigned int __WEXITSTATUS(status) (((status) & 0xff00) >> 8) POSIX_FADV_WILLNEED 3 FAPPEND O_APPEND __attr_dealloc_fclose __USE_LARGEFILE64 _POSIX_TIMEOUTS 200809L __FLT32_IS_IEC_60559__ 1 __BIT_TYPES_DEFINED__ 1 __always_inline __inline __attribute__ ((__always_inline__)) __LP64__ 1 F_SETFD 2 __U16_TYPE unsigned short int htobe32(x) __bswap_32 (x) __nonnull(params) __attribute_nonnull__ (params) _SC_REGEXP _SC_REGEXP _CS_XBS5_ILP32_OFF32_LIBS _CS_XBS5_ILP32_OFF32_LIBS __POSIX_FADV_DONTNEED 4 __attr_dealloc_free __attr_dealloc (__builtin_free, 1) __LDBL_DENORM_MIN__ 3.64519953188247460252840593361941982e-4951L __SEG_FS 1 __attribute_pure__ __attribute__ ((__pure__)) __FLT32X_DECIMAL_DIG__ 17 __LONG_MAX__ 0x7fffffffffffffffL __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 __INT16_TYPE__ short int __FLT128_DIG__ 33 ENETUNREACH 101 _SC_FIFO _SC_FIFO __KERNEL_STRICT_NAMES __HAVE_FLOAT64 1 _SC_TRACE_EVENT_FILTER _SC_TRACE_EVENT_FILTER _SC_NL_TEXTMAX _SC_NL_TEXTMAX POSIX_FADV_NORMAL 0 _SC_NL_MSGMAX _SC_NL_MSGMAX __pid_t_defined UTIME_OMIT ((1l << 30) - 2l) __INTMAX_MAX__ 0x7fffffffffffffffL __BFLT16_NORM_MAX__ 3.38953138925153547590470800371487867e+38BF16 __GCC_ATOMIC_LONG_LOCK_FREE 2 PDP_ENDIAN __PDP_ENDIAN _CS_POSIX_V6_LP64_OFF64_LDFLAGS _CS_POSIX_V6_LP64_OFF64_LDFLAGS O_ASYNC 020000 ETIME 62 ERANGE 34 EAFNOSUPPORT 97 __TIME_T_TYPE __SYSCALL_SLONG_TYPE __WINT_MIN__ 0U __S_IFREG 0100000 _PC_2_SYMLINKS _PC_2_SYMLINKS _SC_LEVEL3_CACHE_ASSOC _SC_LEVEL3_CACHE_ASSOC __stub_fchflags L_ctermid 9 __ULONGWORD_TYPE unsigned long int _SC_TIMERS _SC_TIMERS __INT_MAX__ 0x7fffffff _BITS_ATOMIC_WIDE_COUNTER_H __USE_XOPEN __amd64__ 1 _DEFAULT_SOURCE __GLIBC_USE(F) __GLIBC_USE_ ## F __BFLT16_HAS_DENORM__ 1 __UINT_LEAST32_TYPE__ unsigned int __WORDSIZE_TIME64_COMPAT32 1 _LFS64_ASYNCHRONOUS_IO 1 __attr_access_none(argno) __attribute__ ((__access__ (__none__, argno))) _GCC_WCHAR_T __attribute_copy__(arg) __attribute__ ((__copy__ (arg))) _SC_PII_OSI_CLTS _SC_PII_OSI_CLTS ___int_size_t_h POLLERR 0x008 O_LARGEFILE __O_LARGEFILE EPERM 1 EKEYREVOKED 128 __DBL_MIN_10_EXP__ (-307) _IO_save_base __LDBL_REDIR_DECL(name) ENETRESET 102 __need_size_t _THREAD_MUTEX_INTERNAL_H 1 O_ACCMODE 0003 _LFS64_LARGEFILE 1 __LDBL_MIN_EXP__ (-16381) __clockid_t_defined 1 _BSD_WCHAR_T_ _SC_NPROCESSORS_CONF _SC_NPROCESSORS_CONF __GCC_HAVE_DWARF2_CFI_ASM 1 __CFLOAT128 _Complex _Float128 _SC_XBS5_ILP32_OFF32 _SC_XBS5_ILP32_OFF32 __BFLT16_MAX_10_EXP__ 38 __FLT16_MAX_10_EXP__ 4 _POSIX_CHOWN_RESTRICTED 0 _SC_PII_OSI_M _SC_PII_OSI_M W_OK 2 _SC_SIGQUEUE_MAX _SC_SIGQUEUE_MAX __need_size_t __FLT64X_MAX_EXP__ 16384 _SC_SYMLOOP_MAX _SC_SYMLOOP_MAX __bswap_constant_16(x) ((__uint16_t) ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8))) __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 0 EL3HLT 46 _shortbuf _CS_XBS5_LP64_OFF64_CFLAGS _CS_XBS5_LP64_OFF64_CFLAGS _CS_XBS5_LPBIG_OFFBIG_LINTFLAGS _CS_XBS5_LPBIG_OFFBIG_LINTFLAGS UTIME_NOW ((1l << 30) - 1l) __DEC128_MIN__ 1E-6143DL _SC_NL_NMAX _SC_NL_NMAX __INT64_TYPE__ long int __DEC64_MANT_DIG__ 16 __DEC32_MIN__ 1E-95DF __FLT_HAS_QUIET_NAN__ 1 __REDIRECT_FORTIFY_NTH __REDIRECT_NTH __USE_UNIX98 nr_alloc __INT_LEAST16_TYPE__ short int __CONCAT(x,y) x ## y EDEADLOCK EDEADLK _CS_POSIX_V5_WIDTH_RESTRICTED_ENVS _CS_V5_WIDTH_RESTRICTED_ENVS WSTOPSIG(status) __WSTOPSIG (status) F_DUPFD 0 __SCHAR_WIDTH__ 8 __stub_gtty _POSIX_MEMORY_PROTECTION 200809L __ORDER_PDP_ENDIAN__ 3412 __OFF_T_MATCHES_OFF64_T 1 __FD_CLR(d,s) ((void) (__FDS_BITS (s)[__FD_ELT(d)] &= ~__FD_MASK(d))) _POSIX_V7_LPBIG_OFFBIG -1 _POSIX_ASYNCHRONOUS_IO 200809L _SC_HOST_NAME_MAX _SC_HOST_NAME_MAX _BITS_FLOATN_COMMON_H S_ISVTX __S_ISVTX __BIG_ENDIAN 4321 __SSE2__ 1 _SC_REALTIME_SIGNALS _SC_REALTIME_SIGNALS _CS_XBS5_ILP32_OFF32_CFLAGS _CS_XBS5_ILP32_OFF32_CFLAGS __WINT_WIDTH__ 32 __RLIM_T_MATCHES_RLIM64_T 1 _SC_PII _SC_PII __f128(x) x ##f128 __fsblkcnt_t_defined _SC_BARRIERS _SC_BARRIERS __FLT16_MANT_DIG__ 11 _SC_SHRT_MIN _SC_SHRT_MIN _LFS64_STDIO 1 __INTMAX_WIDTH__ 64 LITTLE_ENDIAN __LITTLE_ENDIAN __GNUC_VA_LIST F_RDLCK 0 __FLT64X_MIN_10_EXP__ (-4931) _BITS_TYPES___LOCALE_T_H 1 __fsfilcnt_t_defined _SC_SELECT _SC_SELECT WNOHANG 1 _CS_POSIX_V6_ILP32_OFFBIG_CFLAGS _CS_POSIX_V6_ILP32_OFFBIG_CFLAGS _SC_AIO_PRIO_DELTA_MAX _SC_AIO_PRIO_DELTA_MAX O_APPEND 02000 __SIZEOF_PTHREAD_COND_T 48 __ATOMIC_RELAXED 0 __UINTMAX_MAX__ 0xffffffffffffffffUL _CS_POSIX_V6_ILP32_OFF32_LIBS _CS_POSIX_V6_ILP32_OFF32_LIBS __STDC_IEC_60559_COMPLEX__ 201404L _XOPEN_UNIX 1 fdarray_flag__nonfilterable __GNU_LIBRARY__ _CS_V7_WIDTH_RESTRICTED_ENVS _CS_V7_WIDTH_RESTRICTED_ENVS __USE_ATFILE 1 _CS_PATH _CS_PATH _POSIX_MEMLOCK_RANGE 200809L ENOSTR 60 _SC_PII_SOCKET _SC_PII_SOCKET _IONBF 2 ENOSYS 38 S_IFBLK __S_IFBLK __DBL_DENORM_MIN__ ((double)4.94065645841246544176568792868221372e-324L) __socklen_t_defined __GCC_IEC_559 2 __REDIRECT_NTHNL(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __THROWNL _SC_TRACE_LOG _SC_TRACE_LOG TMP_MAX 238328 __GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION F_OK 0 WSTOPPED 2 __BFLT16_IS_IEC_60559__ 0 ENOTCONN 107 __UINTPTR_MAX__ 0xffffffffffffffffUL __blksize_t_defined __have_pthread_attr_t 1 WEXITED 4 _SC_XOPEN_SHM _SC_XOPEN_SHM __INT_FAST16_MAX__ 0x7fffffffffffffffL ENOMEDIUM 123 EPROTONOSUPPORT 93 _POSIX_SEMAPHORES 200809L _PC_FILESIZEBITS _PC_FILESIZEBITS _WCHAR_T_DECLARED __GLIBC_USE_IEC_60559_FUNCS_EXT _PC_PIPE_BUF _PC_PIPE_BUF __ATOMIC_RELEASE 3 __INT64_MAX__ 0x7fffffffffffffffL __LOCK_ALIGNMENT __SSE_MATH__ 1 ENOMEM 12 __GNUC__ 14 _POSIX_MAPPED_FILES 200809L __FLT64X_MAX__ 1.18973149535723176502126385303097021e+4932F64x ENOPROTOOPT 92 fdarray__poll fdarray__grow _SC_T_IOV_MAX _SC_T_IOV_MAX __FDS_BITS(set) ((set)->__fds_bits) __INT_LEAST32_WIDTH__ 32 __BFLT16_MIN__ 1.17549435082228750796873653722224568e-38BF16 _SC_BASE _SC_BASE ENOEXEC 8 __FLT32X_NORM_MAX__ 1.79769313486231570814527423731704357e+308F32x _POSIX_TIMERS 200809L __DBL_IS_IEC_60559__ 1 __FLT128_HAS_DENORM__ 1 _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS _CS_POSIX_V7_LP64_OFF64_LINTFLAGS _CS_POSIX_V7_LP64_OFF64_LINTFLAGS __SIZEOF_WINT_T__ 4 __S_IFBLK 0060000 __FLT64_MAX_10_EXP__ 308 __HAVE_FLOAT64X 1 __FLT64X_MIN__ 3.36210314311209350626267781732175260e-4932F64x __off_t_defined EADDRNOTAVAIL 99 __va_arg_pack() __builtin_va_arg_pack () _SC_INT_MAX _SC_INT_MAX le16toh(x) __uint16_identity (x) F_WRLCK 1 __GXX_ABI_VERSION 1019 WCONTINUED 8 fdarray__fprintf _POSIX_THREAD_ROBUST_PRIO_INHERIT 200809L _CS_POSIX_V6_LP64_OFF64_LINTFLAGS _CS_POSIX_V6_LP64_OFF64_LINTFLAGS __SLONGWORD_TYPE long int ENOLCK 37 ESTRPIPE 86 __FLT64_IS_IEC_60559__ 1 _SC_AIO_LISTIO_MAX _SC_AIO_LISTIO_MAX _PC_SYMLINK_MAX _PC_SYMLINK_MAX __SIZEOF_WCHAR_T__ 4 __FLT_EVAL_METHOD__ 0 __GLIBC__ 2 _SC_XOPEN_XPG2 _SC_XOPEN_XPG2 __INT8_MAX__ 0x7f __ATOMIC_ACQUIRE 2 _SC_SEM_NSEMS_MAX _SC_SEM_NSEMS_MAX __SIZEOF_PTHREAD_MUTEXATTR_T 4 _SC_V7_ILP32_OFF32 _SC_V7_ILP32_OFF32 __P(args) args __HAVE_FLOAT128_UNLIKE_LDBL (__HAVE_DISTINCT_FLOAT128 && __LDBL_MANT_DIG__ != 113) __PIC__ 2 _SC_VERSION _SC_VERSION _SYS_SIZE_T_H __RLIM_T_TYPE __SYSCALL_ULONG_TYPE ESOCKTNOSUPPORT 94 __useconds_t_defined _CS_V6_ENV _CS_V6_ENV __FLT64_MAX__ 1.79769313486231570814527423731704357e+308F64 _CS_POSIX_V7_LP64_OFF64_LIBS _CS_POSIX_V7_LP64_OFF64_LIBS _IO_EOF_SEEN 0x0010 __x86_64 1 _SC_BC_DIM_MAX _SC_BC_DIM_MAX EMSGSIZE 90 _PC_MAX_CANON _PC_MAX_CANON _CS_POSIX_V6_LPBIG_OFFBIG_CFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_CFLAGS __USE_FORTIFY_LEVEL F_GETLK64 5 __USE_ISOC11 _IO_save_end __suseconds_t_defined __attribute_alloc_align__(param) __attribute__ ((__alloc_align__ param)) ESHUTDOWN 108 __USECONDS_T_TYPE __U32_TYPE _THREAD_SHARED_TYPES_H 1 ENOKEY 126 FD_CLR(fd,fdsetp) __FD_CLR (fd, fdsetp) POSIX_FADV_NOREUSE __POSIX_FADV_NOREUSE _SC_REGEX_VERSION _SC_REGEX_VERSION __USE_XOPEN2K8 EPFNOSUPPORT 96 _SC_SPORADIC_SERVER _SC_SPORADIC_SERVER __FD_SET(d,s) ((void) (__FDS_BITS (s)[__FD_ELT(d)] |= __FD_MASK(d))) __SUSECONDS_T_TYPE __SYSCALL_SLONG_TYPE __need_NULL _SC_JOB_CONTROL _SC_JOB_CONTROL __GLIBC_USE_DEPRECATED_SCANF _SC_DELAYTIMER_MAX _SC_DELAYTIMER_MAX __SYSCALL_WORDSIZE 64 __USE_LARGEFILE __DEC32_MIN_EXP__ (-94) __SWORD_TYPE long int _POSIX_SAVED_IDS 1 __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 ECONNABORTED 103 __ILP32_OFFBIG_CFLAGS "-m32 -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64" __USE_POSIX199309 1 __UINT32_TYPE__ unsigned int _SC_COLL_WEIGHTS_MAX _SC_COLL_WEIGHTS_MAX __attribute_maybe_unused__ __attribute__ ((__unused__)) __FLT64X_DIG__ 18 _SC_CHARCLASS_NAME_MAX _SC_CHARCLASS_NAME_MAX O_DSYNC __O_DSYNC _____fpos64_t_defined 1 __LDBL_MAX_10_EXP__ 4932 O_DIRECTORY __O_DIRECTORY EDOM 33 __DEC64_EPSILON__ 1E-15DD FILENAME_MAX 4096 _SC_NL_LANGMAX _SC_NL_LANGMAX _SC_FILE_SYSTEM _SC_FILE_SYSTEM _STRING_H 1 _SC_THREAD_ROBUST_PRIO_INHERIT _SC_THREAD_ROBUST_PRIO_INHERIT __DEC32_MAX_EXP__ 97 _GETOPT_CORE_H 1 __OFF_T_TYPE __SYSCALL_SLONG_TYPE __FLT32X_IS_IEC_60559__ 1 _POSIX_BARRIERS 200809L EISCONN 106 _SC_CHAR_BIT _SC_CHAR_BIT _LFS_ASYNCHRONOUS_IO 1 __glibc_macro_warning1(message) _Pragma (#message) __FLT128_EPSILON__ 1.92592994438723585305597794258492732e-34F128 __SIZEOF_INT128__ 16 _SC_IPV6 _SC_IPV6 __FLT128_IS_IEC_60559__ 1 __HAVE_FLOATN_NOT_TYPEDEF 1 __DBL_NORM_MAX__ ((double)1.79769313486231570814527423731704357e+308L) _SC_DEVICE_IO _SC_DEVICE_IO ELNRNG 48 _STATBUF_ST_BLKSIZE __SIZEOF_FLOAT128__ 16 __size_t__ __USE_XOPEN2K 1 _SC_LEVEL1_DCACHE_LINESIZE _SC_LEVEL1_DCACHE_LINESIZE _SC_LEVEL1_DCACHE_SIZE _SC_LEVEL1_DCACHE_SIZE __FLT64X_HAS_INFINITY__ 1 __attribute_used__ __attribute__ ((__used__)) __CHAR_BIT__ 8 __time_t_defined 1 be32toh(x) __bswap_32 (x) __bswap_constant_64(x) ((((x) & 0xff00000000000000ull) >> 56) | (((x) & 0x00ff000000000000ull) >> 40) | (((x) & 0x0000ff0000000000ull) >> 24) | (((x) & 0x000000ff00000000ull) >> 8) | (((x) & 0x00000000ff000000ull) << 8) | (((x) & 0x0000000000ff0000ull) << 24) | (((x) & 0x000000000000ff00ull) << 40) | (((x) & 0x00000000000000ffull) << 56)) EOF (-1) __GLIBC_USE_IEC_60559_TYPES_EXT 0 _XOPEN_REALTIME_THREADS 1 __stub___compat_bdflush __BFLT16_MIN_10_EXP__ (-37) _SC_TRACE_INHERIT _SC_TRACE_INHERIT _SC_2_C_DEV _SC_2_C_DEV _SC_C_LANG_SUPPORT_R _SC_C_LANG_SUPPORT_R __ONCE_FLAG_INIT { 0 } _SC_PRIORITY_SCHEDULING _SC_PRIORITY_SCHEDULING _FEATURES_H 1 __f64(x) x ##f64 __FLT64X_DENORM_MIN__ 3.64519953188247460252840593361941982e-4951F64x _BSD_SIZE_T_ __va_arg_pack_len() __builtin_va_arg_pack_len () _SC_ASYNCHRONOUS_IO _SC_ASYNCHRONOUS_IO _SYS_POLL_H 1 __attribute_deprecated__ __attribute__ ((__deprecated__)) _POSIX_TRACE_LOG -1 _SC_MESSAGE_PASSING _SC_MESSAGE_PASSING _BITS_PTHREADTYPES_COMMON_H 1 _PC_REC_XFER_ALIGN _PC_REC_XFER_ALIGN __WCLONE 0x80000000 __off64_t _SC_2_SW_DEV _SC_2_SW_DEV __GLIBC_USE_C23_STRTOL _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS O_NOCTTY 0400 _CS_POSIX_V7_ILP32_OFF32_LDFLAGS _CS_POSIX_V7_ILP32_OFF32_LDFLAGS AT_SYMLINK_FOLLOW 0x400 __GCC_ATOMIC_POINTER_LOCK_FREE 2 FD_ZERO(fdsetp) __FD_ZERO (fdsetp) __S_TYPEISSHM(buf) ((buf)->st_mode - (buf)->st_mode) _IO_read_base WIFEXITED(status) __WIFEXITED (status) __OFF64_T_TYPE __SQUAD_TYPE _ASM_GENERIC_ERRNO_H __HAVE_FLOAT32X 1 __FLT32_MAX_10_EXP__ 38 POSIX_FADV_SEQUENTIAL 2 _PC_REC_MAX_XFER_SIZE _PC_REC_MAX_XFER_SIZE __fortified_attr_access(a,o,s) __attr_access ((a, o, s)) S_IXUSR __S_IEXEC __DEC64_MAX_EXP__ 385 _IO_buf_end __PRAGMA_REDEFINE_EXTNAME 1 O_RSYNC O_SYNC __UID_T_TYPE __U32_TYPE F_LOCK 1 __LDBL_HAS_DENORM__ 1 __LEAF , __leaf__ _CS_POSIX_V6_LP64_OFF64_LIBS _CS_POSIX_V6_LP64_OFF64_LIBS __REDIRECT_FORTIFY __REDIRECT __GCC_ATOMIC_INT_LOCK_FREE 2 __UINT32_C(c) c ## U _SC_TIMER_MAX _SC_TIMER_MAX AT_EACCESS 0x200 __INT_FAST32_MAX__ 0x7fffffffffffffffL F_SETOWN __F_SETOWN S_IFSOCK __S_IFSOCK _SC_NGROUPS_MAX _SC_NGROUPS_MAX psize EL2NSYNC 45 S_IRUSR __S_IREAD _SC_TRACE_USER_EVENT_MAX _SC_TRACE_USER_EVENT_MAX STDIN_FILENO 0 __REDIRECT_NTH_LDBL(name,proto,alias) __REDIRECT_NTH (name, proto, alias) _XOPEN_ENH_I18N 1 _POSIX_V7_LP64_OFF64 1 _SC_UCHAR_MAX _SC_UCHAR_MAX _IO_write_base _SC_READER_WRITER_LOCKS _SC_READER_WRITER_LOCKS _SC_2_C_VERSION _SC_2_C_VERSION __SSIZE_T_TYPE __SWORD_TYPE O_NONBLOCK 04000 __key_t_defined __f32(x) x ##f32 L_XTND SEEK_END ETIMEDOUT 110 __INO_T_TYPE __SYSCALL_ULONG_TYPE _SC_PII_OSI _SC_PII_OSI SEEK_CUR 1 htole16(x) __uint16_identity (x) __GID_T_TYPE __U32_TYPE __LONG_LONG_PAIR(HI,LO) LO, HI __INT_LEAST16_WIDTH__ 16 __S_IFIFO 0010000 __linux__ 1 ECONNREFUSED 111 _CS_XBS5_ILP32_OFFBIG_LINTFLAGS _CS_XBS5_ILP32_OFFBIG_LINTFLAGS _SC_LEVEL4_CACHE_ASSOC _SC_LEVEL4_CACHE_ASSOC __ptr_t void * FOPEN_MAX 16 __SLONG32_TYPE int O_TRUNC 01000 _POSIX2_C_DEV __POSIX2_THIS_VERSION __O_NOATIME 01000000 __STDC_HOSTED__ 1 __DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD __INT_FAST32_TYPE__ long int __k8__ 1 __SIZEOF_FLOAT80__ 16 __USE_POSIX_IMPLICITLY 1 __INT_LEAST32_MAX__ 0x7fffffff __FLT32_MAX_EXP__ 128 __USE_ISOCXX11 _SC_THREAD_SAFE_FUNCTIONS _SC_THREAD_SAFE_FUNCTIONS _SC_OPEN_MAX _SC_OPEN_MAX _IO_ERR_SEEN 0x0020 __DBL_HAS_DENORM__ 1 __REGISTER_PREFIX__ __UINT32_MAX__ 0xffffffffU _PC_ALLOC_SIZE_MIN _PC_ALLOC_SIZE_MIN __FLT16_DECIMAL_DIG__ 5 _CS_XBS5_ILP32_OFFBIG_LIBS _CS_XBS5_ILP32_OFFBIG_LIBS __glibc_clang_prereq(maj,min) 0 __INTMAX_C(c) c ## L S_IWGRP (S_IWUSR >> 3) _SC_XOPEN_UNIX _SC_XOPEN_UNIX __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 _IO_marker _prevchain _SC_FILE_ATTRIBUTES _SC_FILE_ATTRIBUTES __GNUC_STDC_INLINE__ 1 stdin stdin __FLT32X_EPSILON__ 2.22044604925031308084726333618164062e-16F32x ELIBACC 79 __SIZEOF_PTHREAD_RWLOCK_T 56 ECHRNG 44 __PMT(args) args _CS_POSIX_V7_ILP32_OFF32_CFLAGS _CS_POSIX_V7_ILP32_OFF32_CFLAGS _POSIX_TYPED_MEMORY_OBJECTS -1 __WCHAR_WIDTH__ 32 __STDC_UTF_32__ 1 FOPEN_MAX __FLT64_MIN__ 2.22507385850720138309023271733240406e-308F64 FNDELAY O_NDELAY _SC_THREAD_ATTR_STACKADDR _SC_THREAD_ATTR_STACKADDR _FCNTL_H 1 _SC_THREAD_PRIO_PROTECT _SC_THREAD_PRIO_PROTECT _STRUCT_TIMESPEC 1 __STDC_IEC_60559_BFP__ 201404L EXIT_SUCCESS 0 _CS_GNU_LIBPTHREAD_VERSION _CS_GNU_LIBPTHREAD_VERSION EBFONT 59 __WCHAR_MAX__ 0x7fffffff _POSIX_THREAD_ATTR_STACKADDR 200809L F_TEST 3 __FLT32_HAS_DENORM__ 1 _SC_V7_LP64_OFF64 _SC_V7_LP64_OFF64 _SYS_CDEFS_H 1 __bos(ptr) __builtin_object_size (ptr, __USE_FORTIFY_LEVEL > 1) stdout stdout __SSP_STRONG__ 3 __SIZE_T __FSID_T_TYPE struct { int __val[2]; } _SYS_TYPES_H 1 __SHRT_WIDTH__ 16 _IO_codecvt _SC_2_PBS_TRACK _SC_2_PBS_TRACK __CFLOAT32 _Complex _Float32 __GCC_ATOMIC_SHORT_LOCK_FREE 2 F_GETFD 1 __ferror_unlocked_body(_fp) (((_fp)->_flags & _IO_ERR_SEEN) != 0) __F_SETOWN 8 __BLKCNT_T_TYPE __SYSCALL_SLONG_TYPE __GCC_ASM_FLAG_OUTPUTS__ 1 __BLKSIZE_T_TYPE __SYSCALL_SLONG_TYPE __SIZEOF_POINTER__ 8 __FLT128_NORM_MAX__ 1.18973149535723176508575932662800702e+4932F128 _FILE_OFFSET_BITS 64 _SC_LEVEL2_CACHE_LINESIZE _SC_LEVEL2_CACHE_LINESIZE _PC_REC_MIN_XFER_SIZE _PC_REC_MIN_XFER_SIZE _T_SIZE __FLT64X_MANT_DIG__ 64 __CFLOAT64 _Complex _Float64 __FD_ELT(d) ((d) / __NFDBITS) _CS_V5_WIDTH_RESTRICTED_ENVS _CS_V5_WIDTH_RESTRICTED_ENVS _SC_NPROCESSORS_ONLN _SC_NPROCESSORS_ONLN __code_model_small__ 1 __USE_POSIX2 1 _POSIX_TRACE_INHERIT -1 __DEFINED_wchar_t __cookie_io_functions_t_defined 1 __flexarr [] __CFLOAT64X _Complex _Float64x __GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min)) __ASMNAME2(prefix,cname) __STRING (prefix) cname _BITS_TYPES_H 1 __FLT64_HAS_INFINITY__ 1 __GCC_DESTRUCTIVE_SIZE 64 POLLRDBAND 0x080 F_TLOCK 2 __REDIRECT(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __LONG_LONG_MAX__ 0x7fffffffffffffffLL _SIGSET_NWORDS (1024 / (8 * sizeof (unsigned long int))) EBUSY 16 _T_WCHAR_ __GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE" S_ISGID __S_ISGID __STDC_VERSION__ 199901L _POSIX_C_SOURCE __POSIX2_THIS_VERSION 200809L _CS_POSIX_V6_ILP32_OFF32_LINTFLAGS _CS_POSIX_V6_ILP32_OFF32_LINTFLAGS RAND_MAX 2147483647 __BFLT16_EPSILON__ 7.81250000000000000000000000000000000e-3BF16 F_UNLCK 2 O_WRONLY 01 _SC_SCHAR_MIN _SC_SCHAR_MIN __GLIBC_USE_ISOC23 0 _CS_XBS5_LP64_OFF64_LDFLAGS _CS_XBS5_LP64_OFF64_LDFLAGS __INT_FAST32_WIDTH__ 64 _PC_ASYNC_IO _PC_ASYNC_IO _SC_BC_BASE_MAX _SC_BC_BASE_MAX _POSIX2_LOCALEDEF __POSIX2_THIS_VERSION _SC_2_PBS_MESSAGE _SC_2_PBS_MESSAGE __FLT_MAX__ 3.40282346638528859811704183484516925e+38F _POSIX_REALTIME_SIGNALS 200809L __LONG_LONG_WIDTH__ 64 _SC_2_C_BIND _SC_2_C_BIND _PC_REC_INCR_XFER_SIZE _PC_REC_INCR_XFER_SIZE _SC_SEM_VALUE_MAX _SC_SEM_VALUE_MAX __SIZEOF_PTHREAD_BARRIER_T 32 S_IFDIR __S_IFDIR _CS_LFS64_LIBS _CS_LFS64_LIBS __INO64_T_TYPE __UQUAD_TYPE __stub_sigreturn _SC_2_LOCALEDEF _SC_2_LOCALEDEF __HAVE_DISTINCT_FLOAT32 0 WIFSIGNALED(status) __WIFSIGNALED (status) __GLIBC_USE_IEC_60559_EXT __UINT_LEAST16_TYPE__ short unsigned int _SC_LOGIN_NAME_MAX _SC_LOGIN_NAME_MAX __LDBL_HAS_QUIET_NAN__ 1 O_CLOEXEC __O_CLOEXEC _SC_CHAR_MAX _SC_CHAR_MAX __NO_INLINE__ 1 __FLT64_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F64 __KEY_T_TYPE __S32_TYPE WUNTRACED 2 _IO_buf_base _XOPEN_XCU_VERSION 4 htole64(x) __uint64_identity (x) _POSIX_C_SOURCE 200809L __attribute_nonnull__(params) __attribute__ ((__nonnull__ params)) EDQUOT 122 EUNATCH 49 _SC_NL_SETMAX _SC_NL_SETMAX _CS_POSIX_V6_ILP32_OFFBIG_LINTFLAGS _CS_POSIX_V6_ILP32_OFFBIG_LINTFLAGS __attribute_artificial__ __attribute__ ((__artificial__)) EISDIR 21 _POSIX_IPV6 200809L _SC_PIPE _SC_PIPE _CS_POSIX_V7_ILP32_OFF32_LINTFLAGS _CS_POSIX_V7_ILP32_OFF32_LINTFLAGS STDERR_FILENO 2 _POSIX_CLOCK_SELECTION 200809L __FSBLKCNT64_T_TYPE __UQUAD_TYPE _SIZE_T_DEFINED __LDBL_EPSILON__ 1.08420217248550443400745280086994171e-19L ENAMETOOLONG 36 AT_SYMLINK_NOFOLLOW 0x100 _SC_NZERO _SC_NZERO __SIG_ATOMIC_WIDTH__ 32 __STD_TYPE _SC_CHAR_MIN _SC_CHAR_MIN __USE_FILE_OFFSET64 1 __CLOCKID_T_TYPE __S32_TYPE F_SETLKW64 7 WTERMSIG(status) __WTERMSIG (status) __SYSCALL_ULONG_TYPE __ULONGWORD_TYPE __ULONG32_TYPE unsigned int __HAVE_FLOAT32 1 _IO_FILE __INT_FAST64_TYPE__ long int __need_NULL F_GETOWN __F_GETOWN fdarray__add _IO_wide_data LOCK_UN 8 _POSIX_THREAD_PRIORITY_SCHEDULING 200809L __SIZEOF_LONG__ 8 __LDBL_MANT_DIG__ 64 S_IRWXU (__S_IREAD|__S_IWRITE|__S_IEXEC) _BITS_STDIO_LIM_H 1 ELIBMAX 82 __UINT_FAST64_TYPE__ long unsigned int _SC_MEMLOCK_RANGE _SC_MEMLOCK_RANGE NULL ((void *)0) __INTPTR_WIDTH__ 64 __ORDER_BIG_ENDIAN__ 4321 __gnu_linux__ 1 _SC_C_LANG_SUPPORT _SC_C_LANG_SUPPORT __PTHREAD_RWLOCK_INITIALIZER(__flags) 0, 0, 0, 0, 0, 0, 0, 0, __PTHREAD_RWLOCK_ELISION_EXTRA, 0, __flags __S_IREAD 0400 _CS_POSIX_V6_ILP32_OFF32_LDFLAGS _CS_POSIX_V6_ILP32_OFF32_LDFLAGS __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 __FLT64X_HAS_DENORM__ 1 _SC_MONOTONIC_CLOCK _SC_MONOTONIC_CLOCK _BITS_ERRNO_H 1 _SC_LONG_BIT _SC_LONG_BIT __SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1) _SC_EXPR_NEST_MAX _SC_EXPR_NEST_MAX _SC_LEVEL1_ICACHE_LINESIZE _SC_LEVEL1_ICACHE_LINESIZE __attr_dealloc(dealloc,argno) __attribute__ ((__malloc__ (dealloc, argno))) _SC_THREAD_PRIO_INHERIT _SC_THREAD_PRIO_INHERIT _CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS __STDC_IEC_559_COMPLEX__ 1 _SC_STREAM_MAX _SC_STREAM_MAX __sigset_t_defined 1 __INT_LEAST8_TYPE__ signed char _CS_XBS5_ILP32_OFFBIG_CFLAGS _CS_XBS5_ILP32_OFFBIG_CFLAGS __LDBL_REDIR_NTH(name,proto) name proto __THROW __extern_inline extern __inline __attribute__ ((__gnu_inline__)) __need_wchar_t __FLT_DECIMAL_DIG__ 9 O_NDELAY O_NONBLOCK __glibc_has_builtin(name) __has_builtin (name) EOVERFLOW 75 _SC_TRACE_EVENT_NAME_MAX _SC_TRACE_EVENT_NAME_MAX ENOANO 55 __GLIBC_USE_IEC_60559_BFP_EXT 0 ENOTTY 25 EOWNERDEAD 130 __linux 1 _XOPEN_LEGACY 1 __GLIBC_PREREQ(maj,min) ((__GLIBC__ << 16) + __GLIBC_MINOR__ >= ((maj) << 16) + (min)) EXFULL 54 __FLT128_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966F128 __FINITE_MATH_ONLY__ 0 __attribute_returns_twice__ __attribute__ ((__returns_twice__)) __HAVE_DISTINCT_FLOAT64X 0 __id_t_defined EUCLEAN 117 _CS_POSIX_V7_LP64_OFF64_LDFLAGS _CS_POSIX_V7_LP64_OFF64_LDFLAGS _SC_XOPEN_REALTIME_THREADS _SC_XOPEN_REALTIME_THREADS _RWLOCK_INTERNAL_H __W_EXITCODE(ret,sig) ((ret) << 8 | (sig)) EADDRINUSE 98 __FLT32X_MIN__ 2.22507385850720138309023271733240406e-308F32x _SC_2_CHAR_TERM _SC_2_CHAR_TERM __INT_LEAST64_MAX__ 0x7fffffffffffffffL EAGAIN 11 _SC_SHELL _SC_SHELL __PTHREAD_MUTEX_INITIALIZER(__kind) 0, 0, 0, 0, __kind, 0, 0, { 0, 0 } _STDC_PREDEF_H 1 _SC_USER_GROUPS _SC_USER_GROUPS EFAULT 14 __daddr_t_defined __extern_always_inline extern __always_inline __attribute__ ((__gnu_inline__)) EL3RST 47 _XOPEN_REALTIME 1 _SC_XOPEN_ENH_I18N _SC_XOPEN_ENH_I18N __BFLT16_DIG__ 2 __WALL 0x40000000 __INT32_TYPE__ int _SC_USER_GROUPS_R _SC_USER_GROUPS_R __S_IFCHR 0020000 __bos0(ptr) __builtin_object_size (ptr, 0) __FLT64X_DECIMAL_DIG__ 21 __BYTE_ORDER __LITTLE_ENDIAN be16toh(x) __bswap_16 (x) _CS_V7_ENV _CS_V7_ENV __GLIBC_USE_DEPRECATED_GETS __FLT64_DIG__ 15 _SC_ULONG_MAX _SC_ULONG_MAX __GCC_ATOMIC_BOOL_LOCK_FREE 2 __DEC64_MAX__ 9.999999999999999E384DD _POSIX_MONOTONIC_CLOCK 0 _SC_TRACE_NAME_MAX _SC_TRACE_NAME_MAX __USE_FILE_OFFSET64 __W_CONTINUED 0xffff __DBL_MIN__ ((double)2.22507385850720138309023271733240406e-308L) F_SETLK64 6 __ILP32_OFFBIG_LDFLAGS "-m32" stderr stderr _SC_IOV_MAX _SC_IOV_MAX _SC_SHARED_MEMORY_OBJECTS _SC_SHARED_MEMORY_OBJECTS _SC_DEVICE_SPECIFIC_R _SC_DEVICE_SPECIFIC_R _SC_THREAD_STACK_MIN _SC_THREAD_STACK_MIN EKEYEXPIRED 127 __FLT16_HAS_INFINITY__ 1 htole32(x) __uint32_identity (x) _SC_THREAD_ATTR_STACKSIZE _SC_THREAD_ATTR_STACKSIZE entry_destructor __BLKCNT64_T_TYPE __SQUAD_TYPE L_INCR SEEK_CUR __PDP_ENDIAN 3412 _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS __GCC_CONSTRUCTIVE_SIZE 64 __WIFEXITED(status) (__WTERMSIG(status) == 0) __SIZEOF_DOUBLE__ 8 __FLOAT_WORD_ORDER __BYTE_ORDER __LP64_OFF64_CFLAGS "-m64" __POSIX_FADV_NOREUSE 5 __SUSECONDS64_T_TYPE __SQUAD_TYPE _ATFILE_SOURCE 1 FD_CLOEXEC 1 __FLT128_MAX_EXP__ 16384 __FLT32_MIN__ 1.17549435082228750796873653722224568e-38F32 _BSD_WCHAR_T_ __attr_dealloc_fclose __attr_dealloc (fclose, 1) __lldiv_t_defined 1 __attribute_noinline__ __attribute__ ((__noinline__)) _SC_V6_ILP32_OFF32 _SC_V6_ILP32_OFF32 __GCC_ATOMIC_LLONG_LOCK_FREE 2 __BFLT16_MAX_EXP__ 128 S_IFCHR __S_IFCHR __S_TYPEISMQ(buf) ((buf)->st_mode - (buf)->st_mode) EROFS 30 ENOTRECOVERABLE 131 _PC_LINK_MAX _PC_LINK_MAX __USE_GNU __FLT64_NORM_MAX__ 1.79769313486231570814527423731704357e+308F64 __WIFSTOPPED(status) (((status) & 0xff) == 0x7f) __USE_POSIX2 __ino64_t_defined errno (*__errno_location ()) EUSERS 87 _SC_2_UPE _SC_2_UPE S_IRWXG (S_IRWXU >> 3) _SC_MQ_OPEN_MAX _SC_MQ_OPEN_MAX EDOTDOT 73 POLLNVAL 0x020 EREMCHG 78 _SC_XBS5_LP64_OFF64 _SC_XBS5_LP64_OFF64 _SC_RAW_SOCKETS _SC_RAW_SOCKETS _SC_CLOCK_SELECTION _SC_CLOCK_SELECTION _SC_AIO_MAX _SC_AIO_MAX EOPNOTSUPP 95 __S_ISGID 02000 __need_wchar_t __USE_XOPEN2KXSI POLLRDNORM 0x040 __S_ISUID 04000 __O_DSYNC 010000 __blkcnt_t_defined __ATOMIC_ACQ_REL 4 _SC_MEMORY_PROTECTION _SC_MEMORY_PROTECTION __WNOTHREAD 0x20000000 _T_WCHAR _SIZET_ __INT8_TYPE__ signed char __SSE2_MATH__ 1 EFBIG 27 __MMX__ 1 __CPU_MASK_TYPE __SYSCALL_ULONG_TYPE X_OK 1 __TIME64_T_TYPE __TIME_T_TYPE _IOLBF 1 __ILP32_OFF32_LDFLAGS "-m32" ENOCSI 50 ENOLINK 67 _SC_LEVEL4_CACHE_SIZE _SC_LEVEL4_CACHE_SIZE __FLT64_MIN_EXP__ (-1021) __F_SETOWN_EX 15 __off64_t_defined __STATFS_MATCHES_STATFS64 1 __SIZEOF_PTHREAD_ATTR_T 56 _ALLOCA_H 1 _SC_PASS_MAX _SC_PASS_MAX EBADSLT 57 __attribute_struct_may_alias__ __attribute__ ((__may_alias__)) _____fpos_t_defined 1 __FXSR__ 1 __INT_FAST8_TYPE__ signed char __USE_POSIX199309 EEXIST 17 _POSIX_TRACE_EVENT_FILTER -1 EPROTOTYPE 91 _SC_PII_INTERNET_STREAM _SC_PII_INTERNET_STREAM __FLT32X_MIN_EXP__ (-1021) _CS_POSIX_V7_ILP32_OFF32_LIBS _CS_POSIX_V7_ILP32_OFF32_LIBS __WCHAR_T _PC_NAME_MAX _PC_NAME_MAX _GETOPT_POSIX_H 1 __F_GETOWN_EX 16 __u_char_defined _POSIX_REENTRANT_FUNCTIONS 1 _freeres_buf __ATOMIC_HLE_ACQUIRE 65536 __DEC64_MIN__ 1E-383DD __INT16_C(c) c __FD_MASK(d) ((__fd_mask) (1UL << ((d) % __NFDBITS))) __WINT_TYPE__ unsigned int __INT_FAST8_MAX__ 0x7f __HAVE_DISTINCT_FLOAT32X 0 __FLT16_DIG__ 3 _SC_2_VERSION _SC_2_VERSION __FLT128_HAS_INFINITY__ 1 _POSIX_THREAD_ROBUST_PRIO_PROTECT -1 long long unsigned int __SIZEOF_SHORT__ 2 __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 1 __UINT_FAST16_TYPE__ long unsigned int _cur_column __LONG_WIDTH__ 64 _SC_LEVEL3_CACHE_SIZE _SC_LEVEL3_CACHE_SIZE S_IFIFO __S_IFIFO __UINT8_MAX__ 0xff _SC_CHILD_MAX _SC_CHILD_MAX __HAVE_FLOAT128 1 EREMOTEIO 121 __DECIMAL_BID_FORMAT__ 1 _SC_LEVEL3_CACHE_LINESIZE _SC_LEVEL3_CACHE_LINESIZE __GLIBC_USE_IEC_60559_FUNCS_EXT 0 _SC_TZNAME_MAX _SC_TZNAME_MAX __UINT_FAST8_MAX__ 0xff __FLT64_EPSILON__ 2.22044604925031308084726333618164062e-16F64 __FLT64_MAX_EXP__ 1024 __BEGIN_DECLS _SC_SPAWN _SC_SPAWN __restrict_arr __restrict _SC_UINT_MAX _SC_UINT_MAX _CS_POSIX_V7_LP64_OFF64_CFLAGS _CS_POSIX_V7_LP64_OFF64_CFLAGS __O_DIRECT 040000 ECOMM 70 _BITS_FLOATN_H __FLT64_DECIMAL_DIG__ 17 _POSIX_NO_TRUNC 1 nfds_t ENAVAIL 119 __USE_POSIX199506 1 __GLIBC_USE_IEC_60559_BFP_EXT_C23 __HAVE_FLOAT64X_LONG_DOUBLE 1 _SC_UIO_MAXIOV _SC_UIO_MAXIOV __FLT32_EPSILON__ 1.19209289550781250000000000000000000e-7F32 __UINT64_C(c) c ## UL __SIZEOF_PTHREAD_BARRIERATTR_T 4 __ATOMIC_CONSUME 1 __attribute_copy__ __stub_revoke _SC_XBS5_ILP32_OFFBIG _SC_XBS5_ILP32_OFFBIG __glibc_unlikely(cond) __builtin_expect ((cond), 0) EIO 5 _SC_FILE_LOCKING _SC_FILE_LOCKING __WTERMSIG(status) ((status) & 0x7f) EINPROGRESS 115 _CS_LFS64_LDFLAGS _CS_LFS64_LDFLAGS __BFLT16_MANT_DIG__ 8 _IO_backup_base __USE_XOPEN2K8 1 __RLIM64_T_TYPE __UQUAD_TYPE _POSIX_TRACE -1 __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 _SC_CPUTIME _SC_CPUTIME _IO_read_ptr fdarray_flag__default __INT_LEAST32_TYPE__ int BUFSIZ 8192 EMLINK 31 __SIZEOF_PTRDIFF_T__ 8 POLLPRI 0x002 _PC_PRIO_IO _PC_PRIO_IO _POSIX_REGEXP 1 _FORTIFY_SOURCE WIFCONTINUED(status) __WIFCONTINUED (status) O_CREAT 0100 _STRINGS_H 1 _SC_V6_LPBIG_OFFBIG _SC_V6_LPBIG_OFFBIG STDOUT_FILENO 1 __ssize_t_defined __FLT32X_HAS_QUIET_NAN__ 1 _SC_SSIZE_MAX _SC_SSIZE_MAX __GNUC_EXECUTION_CHARSET_NAME "UTF-8" _ATFILE_SOURCE EHWPOISON 133 _freeres_list ____FILE_defined 1 GNU C99 14.2.0 -mtune=generic -march=x86-64 -ggdb3 -std=gnu99 -fPIC -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection __DBL_MIN_EXP__ (-1021) __GLIBC_USE_DEPRECATED_SCANF 0 FD_ISSET(fd,fdsetp) __FD_ISSET (fd, fdsetp) ENOTBLK 15 _SC_SAVED_IDS _SC_SAVED_IDS __WCOREFLAG 0x80 __HAVE_DISTINCT_FLOAT128X __HAVE_FLOAT128X FNONBLOCK O_NONBLOCK _SC_LEVEL2_CACHE_SIZE _SC_LEVEL2_CACHE_SIZE S_IWUSR __S_IWRITE __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 __attribute_alloc_size__(params) __attribute__ ((__alloc_size__ params)) _SC_SEMAPHORES _SC_SEMAPHORES _POSIX_SHARED_MEMORY_OBJECTS 200809L _POSIX_SOURCE 1 _SC_FD_MGMT _SC_FD_MGMT ENOSPC 28 _BITS_PTHREADTYPES_ARCH_H 1 __S_IWRITE 0200 _POSIX_ADVISORY_INFO 200809L alloca(size) __builtin_alloca (size) __DEC32_MAX__ 9.999999E96DF _SC_SS_REPL_MAX _SC_SS_REPL_MAX _old_offset __F_GETOWN 9 __FLT64X_NORM_MAX__ 1.18973149535723176502126385303097021e+4932F64x __FLT128_HAS_QUIET_NAN__ 1 _POSIX_THREAD_PRIO_PROTECT 200809L __attribute_nonstring__ __attribute__ ((__nonstring__)) __TIMER_T_TYPE void * st_atime st_atim.tv_sec ENOTDIR 20 ELOOP 40 __FLT32X_HAS_DENORM__ 1 ENOTUNIQ 76 __COLD __attribute__ ((__cold__)) htobe16(x) __bswap_16 (x) __FLT32_HAS_QUIET_NAN__ 1 __GNU_LIBRARY__ 6 NFDBITS __NFDBITS long long int ENONET 64 __FSFILCNT64_T_TYPE __UQUAD_TYPE _SC_V6_LP64_OFF64 _SC_V6_LP64_OFF64 _CS_LFS_CFLAGS _CS_LFS_CFLAGS _flags2 _SC_2_PBS _SC_2_PBS _SC_GETPW_R_SIZE_MAX _SC_GETPW_R_SIZE_MAX EXIT_FAILURE 1 EHOSTDOWN 112 WEXITSTATUS(status) __WEXITSTATUS (status) __DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DL __END_DECLS _CS_LFS64_LINTFLAGS _CS_LFS64_LINTFLAGS _SC_THREAD_SPORADIC_SERVER _SC_THREAD_SPORADIC_SERVER __FLT16_MIN_EXP__ (-13) _POSIX_CPUTIME 0 __feof_unlocked_body(_fp) (((_fp)->_flags & _IO_EOF_SEEN) != 0) __DEFINED_size_t _CS_XBS5_LPBIG_OFFBIG_LIBS _CS_XBS5_LPBIG_OFFBIG_LIBS ELIBBAD 80 _SC_PHYS_PAGES _SC_PHYS_PAGES __PTHREAD_MUTEX_HAVE_PREV 1 S_IFREG __S_IFREG __WSTOPSIG(status) __WEXITSTATUS(status) _SC_INT_MIN _SC_INT_MIN __attribute_deprecated_msg__(msg) __attribute__ ((__deprecated__ (msg))) EBADMSG 74 __DBL_MAX__ ((double)1.79769313486231570814527423731704357e+308L) EINTR 4 ENOPKG 65 __PMT __glibc_has_extension(ext) __has_extension (ext) __FSBLKCNT_T_TYPE __SYSCALL_ULONG_TYPE __SSE__ 1 __DBL_HAS_QUIET_NAN__ 1 __GLIBC_USE_ISOC23 __DEC32_MANT_DIG__ 7 __USE_ATFILE _SC_MINSIGSTKSZ _SC_MINSIGSTKSZ __FLT_DENORM_MIN__ 1.40129846432481707092372958328991613e-45F ESRMNT 69 EKEYREJECTED 129 st_mtime st_mtim.tv_sec __FLT32X_MIN_10_EXP__ (-307) _SC_AVPHYS_PAGES _SC_AVPHYS_PAGES __PTHREAD_RWLOCK_ELISION_EXTRA 0, { 0, 0, 0, 0, 0, 0, 0 } __unix 1 __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI 0 _CS_XBS5_LP64_OFF64_LIBS _CS_XBS5_LP64_OFF64_LIBS __LDBL_HAS_INFINITY__ 1 _CS_LFS64_CFLAGS _CS_LFS64_CFLAGS _SC_MEMLOCK _SC_MEMLOCK ENOENT 2 __attribute_format_strfmon__(a,b) __attribute__ ((__format__ (__strfmon__, a, b))) __S_IEXEC 0100 _IOFBF 0 __FLT16_MIN__ 6.10351562500000000000000000000000000e-5F16 __GLIBC_USE_IEC_60559_EXT 0 ECANCELED 125 __FLT_NORM_MAX__ 3.40282346638528859811704183484516925e+38F _SC_2_FORT_RUN _SC_2_FORT_RUN __CLOCK_T_TYPE __SYSCALL_SLONG_TYPE __FLT64X_MIN_EXP__ (-16381) _CS_POSIX_V6_LPBIG_OFFBIG_LINTFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_LINTFLAGS _CS_XBS5_ILP32_OFF32_LINTFLAGS _CS_XBS5_ILP32_OFF32_LINTFLAGS __SIZEOF_LONG_DOUBLE__ 16 _PC_MAX_INPUT _PC_MAX_INPUT __INT_FAST16_TYPE__ long int _BITS_TYPES_LOCALE_T_H 1 fdarray__init __FSFILCNT_T_TYPE __SYSCALL_ULONG_TYPE BUILD_STR(s) #s __S_IFSOCK 0140000 __FLT64_HAS_DENORM__ 1 _POSIX_READER_WRITER_LOCKS 200809L __FLT128_DECIMAL_DIG__ 36 __FLT_HAS_DENORM__ 1 _PC_VDISABLE _PC_VDISABLE _markers SEEK_END 2 __PID_T_TYPE __S32_TYPE _XBS5_LP64_OFF64 1 FASYNC O_ASYNC __O_NOFOLLOW 0400000 _SC_FSYNC _SC_FSYNC __LDBL_MAX__ 1.18973149535723176502126385303097021e+4932L __SIZEOF_FLOAT__ 4 _CS_LFS_LIBS _CS_LFS_LIBS EPIPE 32 __DEC128_EPSILON__ 1E-33DL __SIZE_T__ _SC_PII_OSI_COTS _SC_PII_OSI_COTS _POSIX_PRIORITIZED_IO 200809L __UINT_LEAST8_TYPE__ unsigned char __NLINK_T_TYPE __SYSCALL_ULONG_TYPE __STDC_ISO_10646__ 201706L __LDBL_MIN_10_EXP__ (-4931) F_EXLCK 4 __warnattr(msg) __attribute__((__warning__ (msg))) __STRING(x) #x LOCK_EX 2 _SC_XOPEN_STREAMS _SC_XOPEN_STREAMS __CHAR16_TYPE__ short unsigned int __USE_FORTIFY_LEVEL 0 _POSIX_THREAD_ATTR_STACKSIZE 200809L EALREADY 114 fdarray le64toh(x) __uint64_identity (x) ENODATA 61 _SC_SHRT_MAX _SC_SHRT_MAX _CS_XBS5_LPBIG_OFFBIG_CFLAGS _CS_XBS5_LPBIG_OFFBIG_CFLAGS __attribute_const__ __attribute__ ((__const__)) __S_IFMT 0170000 __returns_nonnull __attribute__ ((__returns_nonnull__)) __FLT_MIN__ 1.17549435082228750796873653722224568e-38F __SYSCALL_SLONG_TYPE __SLONGWORD_TYPE __LDBL_REDIR2_DECL(name) __SIZE_TYPE__ long unsigned int __LDBL_MAX_EXP__ 16384 _POSIX_THREAD_SPORADIC_SERVER -1 F_GETLK F_GETLK64 __MMX_WITH_SSE__ 1 __S16_TYPE short int __GNUC_MINOR__ 2 _SC_THREAD_PROCESS_SHARED _SC_THREAD_PROCESS_SHARED __STDC_UTF_16__ 1 fdarray__exit __INT_FAST64_WIDTH__ 64 _LP64 1 _vtable_offset __S64_TYPE long int FD_SETSIZE __FD_SETSIZE __UINT_FAST32_MAX__ 0xffffffffffffffffUL __O_DIRECTORY 0200000 npos _SC_SYNCHRONIZED_IO _SC_SYNCHRONIZED_IO fdarray__new __INT_FAST8_WIDTH__ 8 __UINTMAX_C(c) c ## UL __GLIBC_MINOR__ 40 __PTRDIFF_TYPE__ long int EHOSTUNREACH 113 _CS_XBS5_ILP32_OFFBIG_LDFLAGS _CS_XBS5_ILP32_OFFBIG_LDFLAGS __UINT_LEAST8_MAX__ 0xff __FLT32_NORM_MAX__ 3.40282346638528859811704183484516925e+38F32 __USE_ISOC95 1 ESTALE 116 _SC_USHRT_MAX _SC_USHRT_MAX __INT64_C(c) c ## L EACCES 13 nr_autogrow __VERSION__ "14.2.0" __GNUC_PATCHLEVEL__ 0 __DBL_DIG__ 15 ENOMSG 42 TIOCM_RTS 0x004 SIOCSIFNETMASK 0x891c MS_RMT_MASK (MS_RDONLY|MS_SYNCHRONOUS|MS_MANDLOCK|MS_I_VERSION| MS_LAZYTIME) __CPU_SET_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? (((__cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] |= __CPUMASK (__cpu)) : 0; })) f_ffree __align N_PROFIBUS_FDL 10 TIOCM_CD TIOCM_CAR _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) __pthread_mutex_s SHRT_MAX __SHRT_MAX__ _POSIX_LOGIN_NAME_MAX 9 sysfs__read_str TCSETX 0x5433 INT_LEAST8_MAX (127) STATMOUNT_MNT_ROOT 0x00000008U MOVE_MOUNT_F_AUTOMOUNTS 0x00000002 MS_RDONLY 1 TIOCSLCKTRMIOS 0x5457 __isprint_l(c,l) __isctype_l((c), _ISprint, (l)) TIOCPKT_START 8 FSPICK_SYMLINK_NOFOLLOW 0x00000002 PTHREAD_MUTEX_NORMAL _POSIX_THREAD_KEYS_MAX 128 _POSIX_THREAD_DESTRUCTOR_ITERATIONS 4 TIOCGSOFTCAR 0x5419 _BITS_POSIX1_LIM_H 1 XATTR_SIZE_MAX 65536 UCHAR_MAX (SCHAR_MAX * 2 + 1) _BITS_POSIX2_LIM_H 1 ispunct(c) __isctype((c), _ISpunct) _LINUX_LIMITS_H __CPU_SETSIZE 1024 CLOCK_REALTIME_COARSE 5 __BITS_PER_LONG 64 N_SLIP 1 NCC 8 TIMER_ABSTIME 1 N_R3964 9 isalnum_l(c,l) __isalnum_l ((c), (l)) MOUNT_ATTR_NOSUID 0x00000002 fs__check_mounts _POSIX2_LINE_MAX 2048 _GCC_NEXT_LIMITS_H MS_SILENT 32768 MS_RDONLY MS_RDONLY CWERASE CTRL('w') MOUNT_ATTR_RDONLY 0x00000001 _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) PIPE_BUF 4096 _POSIX2_BC_BASE_MAX 99 _STDBOOL_H SCHAR_MAX __SCHAR_MAX__ UINT_MAX (INT_MAX * 2U + 1U) SIOCSIFMEM 0x8920 MNT_FORCE MNT_FORCE SIOCGIFENCAP 0x8925 MS_RMT_MASK _POSIX_TIMER_MAX 32 N_HCI 15 __CPU_ZERO_S(setsize,cpusetp) do __builtin_memset (cpusetp, '\0', setsize); while (0) INT_MIN (-INT_MAX - 1) fs__hugetlbfs MS_KERNMOUNT MS_KERNMOUNT __isupper_l(c,l) __isctype_l((c), _ISupper, (l)) PTHREAD_KEYS_MAX 1024 __isctype(c,type) ((*__ctype_b_loc ())[(int) (c)] & (unsigned short int) type) SIOCGIFMTU 0x8921 INT_LEAST16_MIN (-32767-1) _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) sysfs__read_ull BLKRASET _IO(0x12, 98) FSOPEN_CLOEXEC 0x00000001 __fsid_t INT32_MIN (-2147483647-1) MS_UNBINDABLE (1<<17) UINT64_MAX (__UINT64_C(18446744073709551615)) __user WCHAR_MIN __WCHAR_MIN MS_REMOUNT MS_REMOUNT bpf_fs_init_once procfs__mount _BITS_TYPES_STRUCT_SCHED_PARAM 1 BLKSECTGET __ASM_GENERIC_POSIX_TYPES_H LLONG_MIN (-LLONG_MAX-1) _POSIX_STREAM_MAX 8 MNT_ID_REQ_SIZE_VER0 24 INT16_MAX (32767) _POSIX_ARG_MAX 4096 __ispunct_l(c,l) __isctype_l((c), _ISpunct, (l)) _POSIX2_EXPR_NEST_MAX 32 BLKFLSBUF _IO(0x12, 97) _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) PTHREAD_MUTEX_TIMED_NP XATTR_NAME_MAX 255 TIOCSERSETMULTI 0x545B atoi f_frsize _BITS_CPU_SET_H 1 CLNEXT CTRL('v') _T_PTRDIFF_ MS_LAZYTIME MS_LAZYTIME _SYS_MOUNT_H 1 ACCESSPERMS (S_IRWXU|S_IRWXG|S_IRWXO) SIOCDARP 0x8953 UINT_FAST8_MAX (255) STATMOUNT_MNT_NS_ID 0x00000040U _POSIX_THREAD_THREADS_MAX 64 SEM_VALUE_MAX (2147483647) filename__read_xll _POSIX_PATH_MAX 256 SIOCGIFBR 0x8940 SIOCSIFSLAVE 0x8930 _IOC_NRSHIFT 0 _POSIX_LINK_MAX 8 MS_NOEXEC MS_NOEXEC N_SYNC_PPP 14 INT_FAST64_MAX (__INT64_C(9223372036854775807)) LINK_MAX 127 TIOCM_CAR 0x040 pthread_once FSPICK_EMPTY_PATH 0x00000008 PTHREAD_DESTRUCTOR_ITERATIONS _POSIX_THREAD_DESTRUCTOR_ITERATIONS MS_REC MS_REC sysctl __BITS_PER_LONG_LONG 64 BLKSECTSET MS_NOATIME MS_NOATIME _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) _GCC_NEXT_LIMITS_H CSUSP CTRL('z') BLKBSZSET _IOW(0x12,113,size_t) __owner LLONG_MIN (-LLONG_MAX - 1LL) __isspace_l(c,l) __isctype_l((c), _ISspace, (l)) __isxdigit_l(c,l) __isctype_l((c), _ISxdigit, (l)) name_len st_fs tracefs__configured filename__write_int _SYS_TTYDEFAULTS_H_ BLOCK_SIZE_BITS 10 SCHED_RR 2 __struct_tm_defined 1 TIOCSCTTY 0x540E SIOCSIFNAME 0x8923 _POSIX_NAME_MAX 14 STATMOUNT_MNT_BASIC 0x00000002U _ISbit(bit) ((bit) < 8 ? ((1 << (bit)) << 8) : ((1 << (bit)) >> 8)) _IOC_TYPECHECK(t) (sizeof(t)) __CPUMASK(cpu) ((__cpu_mask) 1 << ((cpu) % __NCPUBITS)) CDISCARD CTRL('o') __lock sysfs__mountpoint MS_MANDLOCK MS_MANDLOCK UINT_FAST32_MAX (18446744073709551615UL) COLL_WEIGHTS_MAX 255 __undef_OPEN_MAX PTHREAD_MUTEX_DEFAULT __pthread_list_t fopen SIOCSIFBR 0x8941 MS_NOSYMFOLLOW MS_NOSYMFOLLOW __fsfilcnt64_t procfs_init_once strdup _POSIX2_BC_STRING_MAX 1000 TIOCCBRK 0x5428 TIOCSERCONFIG 0x5453 TIOCGEXCL _IOR('T', 0x40, int) BLKRRPART BPF_FS_MAGIC 0xcafe4a11 _SYS_STATFS_H 1 ULLONG_MAX __WCHAR_MAX __WCHAR_MAX__ TIOCSSERIAL 0x541F MOVE_MOUNT_T_SYMLINKS 0x00000010 _IOC_DIRBITS 2 isprint(c) __isctype((c), _ISprint) MS_NODIRATIME 2048 __toascii(c) ((c) & 0x7f) BLKROSET SIOCSIFMAP 0x8971 DEBUGFS_MAGIC 0x64626720 CQUIT 034 CLOCK_BOOTTIME 7 __API_DEBUG_H__ MS_ACTIVE MS_ACTIVE _IOC_SIZEBITS 14 strlen SIOCDELMULTI 0x8932 __S_ISTYPE(mode,mask) (((mode) & __S_IFMT) == (mask)) _POSIX_NGROUPS_MAX 8 UINT_FAST16_MAX (18446744073709551615UL) XATTR_LIST_MAX 65536 MS_SYNCHRONOUS MS_SYNCHRONOUS MS_LAZYTIME (1<<25) RE_DUP_MAX (0x7fff) CHAR_BIT __CHAR_BIT__ false 0 timeout_ms CLOCK_REALTIME 0 PTHREAD_MUTEX_INITIALIZER { { __PTHREAD_MUTEX_INITIALIZER (PTHREAD_MUTEX_TIMED_NP) } } FIONBIO 0x5421 SIOCSIFBRDADDR 0x891a temp TIOCPKT_NOSTOP 16 BLKGETSIZE64 _IOR(0x12,114,size_t) pr_warn(fmt,...) __pr(__pr_warn, fmt, ##__VA_ARGS__) __data FSPICK_NO_AUTOMOUNT 0x00000004 TIOCMBIC 0x5417 MS_STRICTATIME (1<<24) TIOCGSID 0x5429 __isdigit_l(c,l) __isctype_l((c), _ISdigit, (l)) isblank_l(c,l) __isblank_l ((c), (l)) INT_FAST8_MIN (-128) hugetlbfs__configured SIOCSIFPFLAGS 0x8934 CLOCK_PROCESS_CPUTIME_ID 2 _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) __isblank_l(c,l) __isctype_l((c), _ISblank, (l)) tracefs_init_once PTHREAD_CANCEL_ASYNCHRONOUS PTHREAD_CANCEL_ASYNCHRONOUS _BITS_STDINT_UINTN_H 1 INT_FAST16_MIN (-9223372036854775807L-1) MS_SLAVE (1<<19) ALLPERMS (S_ISUID|S_ISGID|S_ISVTX|S_IRWXU|S_IRWXG|S_IRWXO) ARG_MAX 131072 CREPRINT CTRL('r') CRPRNT CREPRINT _PTRDIFF_T_DECLARED pthread_mutex_t MS_SHARED (1<<20) TCSETSF2 _IOW('T', 0x2D, struct termios2) _LINUX_IOCTL_H __API_FS__ N_PPP 3 _IOC_NONE 0U pthread_mutex_lock PTHREAD_CANCEL_ENABLE PTHREAD_CANCEL_ENABLE SIOCDELRT 0x890C TTYDEF_SPEED (B9600) iscntrl_l(c,l) __iscntrl_l ((c), (l)) TIOCPKT_STOP 4 __API_IO__ SIOCGIFBRDADDR 0x8919 TIOCSERGWILD 0x5454 SHRT_MIN (-SHRT_MAX - 1) _GCC_PTRDIFF_T STATMOUNT_PROPAGATE_FROM 0x00000004U SIOCDIFADDR 0x8936 _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) BC_BASE_MAX _POSIX2_BC_BASE_MAX SIOCSIFENCAP 0x8926 HOST_NAME_MAX 64 PTHREAD_EXPLICIT_SCHED PTHREAD_EXPLICIT_SCHED _SYS_IOCTL_H 1 UINT_LEAST8_MAX (255) procfs__mountpoint MNT_ID_REQ_SIZE_VER1 32 FS(lower_name,fs_name,upper_name) static struct fs fs__ ##lower_name = { .name = #fs_name, .mounts = lower_name ##__known_mountpoints, .magic = upper_name ##_MAGIC, .mount_mutex = PTHREAD_MUTEX_INITIALIZER, }; static void lower_name ##_init_once(void) { struct fs *fs = &fs__ ##lower_name; fs__init_once(fs); } const char *lower_name ##__mountpoint(void) { static pthread_once_t init_once = PTHREAD_ONCE_INIT; struct fs *fs = &fs__ ##lower_name; pthread_once(&init_once, lower_name ##_init_once); return fs__mountpoint(fs); } const char *lower_name ##__mount(void) { const char *mountpoint = lower_name ##__mountpoint(); struct fs *fs = &fs__ ##lower_name; if (mountpoint) return mountpoint; return fs__mount(fs); } bool lower_name ##__configured(void) { return lower_name ##__mountpoint() != NULL; } __kind PTHREAD_SCOPE_PROCESS PTHREAD_SCOPE_PROCESS TCSETSW2 _IOW('T', 0x2C, struct termios2) MS_NOEXEC 8 __ASM_GENERIC_IOCTLS_H MOUNT_ATTR_NOATIME 0x00000010 CEOL _POSIX_VDISABLE TIOCSWINSZ 0x5414 AIO_PRIO_DELTA_MAX 20 INT_LEAST32_MAX (2147483647) STATMOUNT_MNT_OPTS 0x00000080U TIOCGPKT _IOR('T', 0x38, int) _POSIX_CHILD_MAX 25 TTYDEF_IFLAG (BRKINT | ISTRIP | ICRNL | IMAXBEL | IXON | IXANY) _toupper(c) ((int) (*__ctype_toupper_loc ())[(int) (c)]) SIOCGIFHWADDR 0x8927 __cold TIOCPKT_DATA 0 fs__procfs S_TYPEISSEM(buf) __S_TYPEISSEM(buf) UINT_FAST64_MAX (__UINT64_C(18446744073709551615)) STR(x) _STR(x) INT_FAST8_MAX (127) INT64_MAX (__INT64_C(9223372036854775807)) INTPTR_MIN (-9223372036854775807L-1) HUGETLBFS_MAGIC 0x958458f6 sysfs__write_int MS_I_VERSION (1<<23) TIOCGETD 0x5424 isxdigit_l(c,l) __isxdigit_l ((c), (l)) CLOCKS_PER_SEC ((__clock_t) 1000000) TIOCOUTQ 0x5411 _IOC_NRBITS 8 __ASSERT_VOID_CAST (void) TCSBRK 0x5409 bpf_fs__known_mountpoints S_BLKSIZE 512 f_files _PTHREAD_H 1 fs__read_mounts isalpha_l(c,l) __isalpha_l ((c), (l)) MS_BIND MS_BIND pr_debug(fmt,...) __pr(__pr_debug, fmt, ##__VA_ARGS__) MS_POSIXACL (1<<16) CHARCLASS_NAME_MAX 2048 CEOF CTRL('d') procfs__read_str TIOCPKT_FLUSHREAD 1 EXPR_NEST_MAX _POSIX2_EXPR_NEST_MAX STATMOUNT_MNT_POINT 0x00000010U BLKGETSIZE INT_FAST32_MAX (9223372036854775807L) tracefs__known_mountpoints ULONG_MAX (LONG_MAX * 2UL + 1UL) __size MOVE_MOUNT_BENEATH 0x00000200 isspace_l(c,l) __isspace_l ((c), (l)) BC_DIM_MAX _POSIX2_BC_DIM_MAX f_bfree fs__valid_mount DEFFILEMODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) MS_DIRSYNC 128 PTHREAD_MUTEX_ERRORCHECK_NP TCGETX 0x5432 __bool_true_false_are_defined 1 MS_NOUSER (1<<31) line_out _POSIX_SEM_NSEMS_MAX 256 _IOC_READ 2U PTHREAD_COND_INITIALIZER { { {0}, {0}, {0, 0}, {0, 0}, 0, 0, {0, 0} } } PTHREAD_MUTEX_RECURSIVE CLOCK_REALTIME_ALARM 8 assert(expr) ((void) sizeof ((expr) ? 1 : 0), __extension__ ({ if (expr) ; else __assert_fail (#expr, __FILE__, __LINE__, __ASSERT_FUNCTION); })) __count TTYDEF_OFLAG (OPOST | ONLCR | XTABS) TCSETXW 0x5435 MS_MOVE MS_MOVE _LIBC_LIMITS_H_ 1 isprint_l(c,l) __isprint_l ((c), (l)) TIOCSERGETMULTI 0x545A _POSIX_CLOCKRES_MIN 20000000 sysfs__read_xll MS_NOSUID 2 MS_NOSUID MS_NOSUID S_ISFIFO(mode) __S_ISTYPE((mode), __S_IFIFO) NR_OPEN 1024 __kernel_old_dev_t __kernel_old_dev_t _POSIX_PIPE_BUF 512 _UAPI__ASM_GENERIC_BITS_PER_LONG LSMT_ROOT 0xffffffffffffffff OPEN_TREE_CLOEXEC O_CLOEXEC MOUNT_ATTR_IDMAP 0x00100000 TIOCM_ST 0x008 TIOCGWINSZ 0x5413 hugetlbfs_init_once _IOC_WRITE 1U __need_ptrdiff_t SIOCGIFNETMASK 0x891b MOUNT_ATTR_NODEV 0x00000004 TIOCSBRK 0x5427 INT_MAX __INT_MAX__ TIOCLINUX 0x541C IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) PTHREAD_ONCE_INIT 0 SIOCSIFLINK 0x8911 _GCC_WRAP_STDINT_H __isascii(c) (((c) & ~0x7f) == 0) debugfs__known_mountpoints MOVE_MOUNT_SET_GROUP 0x00000100 BLKSSZGET BLKROSET _IO(0x12, 93) __undef_LINK_MAX _ASM_GENERIC_TYPES_H _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) SIOCGIFTXQLEN 0x8942 PTHREAD_THREADS_MAX SIOCGIFMEM 0x891f __isgraph_l(c,l) __isctype_l((c), _ISgraph, (l)) SIOCADDRT 0x890B __undef_LINK_MAX __pthread_internal_list INT_LEAST8_MIN (-128) __prev MS_NOSYMFOLLOW 256 CKILL CTRL('u') _ASM_X86_POSIX_TYPES_64_H pthread_cleanup_push(routine,arg) do { __pthread_unwind_buf_t __cancel_buf; void (*__cancel_routine) (void *) = (routine); void *__cancel_arg = (arg); int __not_first_call = __sigsetjmp_cancel (__cancel_buf.__cancel_jmp_buf, 0); if (__glibc_unlikely (__not_first_call)) { __cancel_routine (__cancel_arg); __pthread_unwind_next (&__cancel_buf); } __pthread_register_cancel (&__cancel_buf); do { TCSETS2 _IOW('T', 0x2B, struct termios2) TIOCSERSWILD 0x5455 mount_mutex hugetlbfs__mount N_6PACK 7 __isalpha_l(c,l) __isctype_l((c), _ISalpha, (l)) ULLONG_MAX (LLONG_MAX * 2ULL + 1) CLOCK_MONOTONIC_COARSE 6 _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) SCHED_OTHER 0 _POSIX2_COLL_WEIGHTS_MAX 2 fopen64 TIOCPKT_DOSTOP 32 SIOCGIFNAME 0x8910 __aligned_u64 __u64 __attribute__((aligned(8))) TIOCMSET 0x5418 sizep tracefs__mount small_const_nbits(nbits) (__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG && (nbits) > 0) bpf_fs__configured CTIME 0 isgraph_l(c,l) __isgraph_l ((c), (l)) __ssize_t islower_l(c,l) __islower_l ((c), (l)) IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) LONG_MIN (-LONG_MAX - 1L) INT_LEAST64_MIN (-__INT64_C(9223372036854775807)-1) SIOCGIFPFLAGS 0x8935 CHAR_MIN SCHAR_MIN TIOCGSERIAL 0x541E __kernel_old_uid_t __kernel_old_uid_t TIOCMBIS 0x5416 _STATFS_F_FRSIZE f_spare __undef_ARG_MAX MS_KERNMOUNT (1<<22) MQ_PRIO_MAX 32768 DEBUGFS_DEFAULT_PATH "/sys/kernel/debug" _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) TCGETA 0x5405 BLKGETSIZE64 debugfs__configured LISTMOUNT_REVERSE (1 << 0) MS_DIRSYNC MS_DIRSYNC MS_MOVE 8192 S_IEXEC S_IXUSR N_MOUSE 2 line_len_out _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) LLONG_MIN _POSIX2_RE_DUP_MAX 255 INTMAX_MIN (-__INT64_C(9223372036854775807)-1) _POSIX2_BC_SCALE_MAX 99 INT32_MAX (2147483647) MOUNT_ATTR_NOEXEC 0x00000008 __undef_OPEN_MAX S_ISDIR(mode) __S_ISTYPE((mode), __S_IFDIR) CLOCK_BOOTTIME_ALARM 9 BLKBSZGET _IOR(0x12,112,size_t) SIOCSARP 0x8955 MS_POSIXACL MS_POSIXACL MS_I_VERSION MS_I_VERSION TIOCSERGSTRUCT 0x5458 _POSIX_AIO_MAX 1 buf_pos mem_toupper magic islower(c) __isctype((c), _ISlower) f_bsize NGROUPS_MAX 65536 isdigit_l(c,l) __isdigit_l ((c), (l)) _POSIX_OPEN_MAX 20 LONG_MAX __LONG_MAX__ PTRDIFF_MIN (-9223372036854775807L-1) isalnum(c) __isctype((c), _ISalnum) MOVE_MOUNT__MASK 0x00000377 PTHREAD_PROCESS_PRIVATE PTHREAD_PROCESS_PRIVATE __pr(func,fmt,...) do { if ((func)) (func)("libapi: " fmt, ##__VA_ARGS__); } while (0) S_ISBLK(mode) __S_ISTYPE((mode), __S_IFBLK) TIOCGRS485 0x542E _POSIX_AIO_LISTIO_MAX 2 PTRDIFF_MAX (9223372036854775807L) INT8_MAX (127) TTYDEF_LFLAG (ECHO | ICANON | ISIG | IEXTEN | ECHOE|ECHOKE|ECHOCTL) __assert_fail offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) isspace(c) __isctype((c), _ISspace) mount_overload TRACEFS_MAGIC 0x74726163 TIOCGLCKTRMIOS 0x5456 TIOCEXCL 0x540C N_MASC 8 INT64_MIN (-__INT64_C(9223372036854775807)-1) S_TYPEISMQ(buf) __S_TYPEISMQ(buf) _POSIX_MAX_CANON 255 CLOCK_MONOTONIC 1 err_out pthread_once_t UINT_LEAST32_MAX (4294967295U) CSTATUS _POSIX_VDISABLE TIOCSRS485 0x542F N_HDLC 13 f_fsid __elision __NCPUBITS (8 * sizeof (__cpu_mask)) _IOC_NRMASK ((1 << _IOC_NRBITS)-1) TIOCSTI 0x5412 sysfs_init_once override_path BC_SCALE_MAX _POSIX2_BC_SCALE_MAX CERASE 0177 TIOCSSOFTCAR 0x541A MS_NOATIME 1024 _POSIX_TZNAME_MAX 6 IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) PTHREAD_SCOPE_SYSTEM PTHREAD_SCOPE_SYSTEM BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__) __SANE_USERSPACE_TYPES__ __force MS_RELATIME (1<<21) filename__read_ull_base MS_RELATIME MS_RELATIME filename CSTART CTRL('q') INTMAX_MAX (__INT64_C(9223372036854775807)) TIOCGPTPEER _IO('T', 0x41) PTHREAD_CANCEL_DEFERRED PTHREAD_CANCEL_DEFERRED procfs__known_mountpoints __cleanup_fct_attribute MOUNT_ATTR__ATIME 0x00000070 TCSBRKP 0x5425 BLKROGET _IO(0x12, 94) TIOCSER_TEMT 0x01 pfds TCSETAW 0x5407 SIOCGIFADDR 0x8915 __isleap(year) ((year) % 4 == 0 && ((year) % 100 != 0 || (year) % 400 == 0)) TCSETSF 0x5404 CLOCK_MONOTONIC_RAW 4 SIOCSIFDSTADDR 0x8918 _ASM_GENERIC_INT_LL64_H MOVE_MOUNT_F_SYMLINKS 0x00000001 CSTOP CTRL('s') IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) pthread_cleanup_pop(execute) do { } while (0); } while (0); __pthread_unregister_cancel (&__cancel_buf); if (execute) __cancel_routine (__cancel_arg); } while (0) isdigit(c) __isctype((c), _ISdigit) _ANSI_STDDEF_H statfs64 _IOC(dir,type,nr,size) (((dir) << _IOC_DIRSHIFT) | ((type) << _IOC_TYPESHIFT) | ((nr) << _IOC_NRSHIFT) | ((size) << _IOC_SIZESHIFT)) RTSIG_MAX 32 MOUNT_ATTR_NOSYMFOLLOW 0x00200000 PTHREAD_PROCESS_SHARED PTHREAD_PROCESS_SHARED TIOCM_RNG 0x080 _POSIX_MQ_OPEN_MAX 8 TIOCPKT_IOCTL 64 MS_SYNCHRONOUS 16 BLKSECTSET _IO(0x12,102) __undef_NR_OPEN INT_FAST64_MIN (-__INT64_C(9223372036854775807)-1) TCGETS2 _IOR('T', 0x2A, struct termios2) TIOCNOTTY 0x5422 TIOCSETD 0x5423 isupper(c) __isctype((c), _ISupper) SIOCADDDLCI 0x8980 isascii(c) __isascii (c) TIOCM_DTR 0x002 isupper_l(c,l) __isupper_l ((c), (l)) TIOCSISO7816 _IOWR('T', 0x43, struct serial_iso7816) MS_NOSEC (1<<28) _POSIX_SSIZE_MAX 32767 TCSETS 0x5402 __CPU_CLR_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? (((__cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] &= ~__CPUMASK (__cpu)) : 0; })) UINTPTR_MAX (18446744073709551615UL) PTHREAD_CREATE_JOINABLE PTHREAD_CREATE_JOINABLE __exctype_l(name) extern int name (int, locale_t) __THROW BLOCK_SIZE (1<<BLOCK_SIZE_BITS) _POSIX2_CHARCLASS_NAME_MAX 14 UINT32_MAX (4294967295U) N_X25 6 tracefs__mountpoint SIOCRTMSG 0x890D CFLUSH CDISCARD N_SMSBLOCK 12 INT8_MIN (-128) UINT8_MAX (255) BLKFRAGET _IO(0x12,101) _STATFS_F_FLAGS __CPU_OP_S(setsize,destset,srcset1,srcset2,op) (__extension__ ({ cpu_set_t *__dest = (destset); const __cpu_mask *__arr1 = (srcset1)->__bits; const __cpu_mask *__arr2 = (srcset2)->__bits; size_t __imax = (setsize) / sizeof (__cpu_mask); size_t __i; for (__i = 0; __i < __imax; ++__i) ((__cpu_mask *) __dest->__bits)[__i] = __arr1[__i] op __arr2[__i]; __dest; })) __bitwise SIOCDELDLCI 0x8981 __CPU_EQUAL_S(setsize,cpusetp1,cpusetp2) (__builtin_memcmp (cpusetp1, cpusetp2, setsize) == 0) _IOC_TYPEBITS 8 TCSETXF 0x5434 sysfs__read_bool _POSIX_RTSIG_MAX 8 __jmp_buf_tag_defined 1 TIOCINQ FIONREAD SIOCGIFINDEX 0x8933 BLKRAGET _BITS_WCHAR_H 1 MS_VERBOSE 32768 MS_MGC_VAL 0xc0ed0000 CDSUSP CTRL('y') MS_NOUSER MS_NOUSER S_TYPEISSHM(buf) __S_TYPEISSHM(buf) CBRK CEOL TTY_NAME_MAX 32 _GCC_LIMITS_H_ FIONCLEX 0x5450 TCSETA 0x5406 PTHREAD_RWLOCK_INITIALIZER { { __PTHREAD_RWLOCK_INITIALIZER (PTHREAD_RWLOCK_DEFAULT_NP) } } iscntrl(c) __isctype((c), _IScntrl) BLKFRASET _IO(0x12,100) FIOCLEX 0x5451 TIOCMIWAIT 0x545C sysfs__read_ull_base f_blocks TIOCCONS 0x541D TIOCM_RI TIOCM_RNG __undef_ARG_MAX CLOCK_THREAD_CPUTIME_ID 3 UINT_LEAST16_MAX (65535) MS_REMOUNT 32 TCGETS 0x5401 CTRL(x) (x&037) PTHREAD_INHERIT_SCHED PTHREAD_INHERIT_SCHED MOVE_MOUNT_T_EMPTY_PATH 0x00000040 INT_LEAST32_MIN (-2147483647-1) S_ISLNK(mode) __S_ISTYPE((mode), __S_IFLNK) FIOASYNC 0x5452 LOGIN_NAME_MAX 256 __errno_location debugfs__mountpoint isblank(c) __isctype((c), _ISblank) INT_FAST16_MAX (9223372036854775807L) io__init io__fill_buffer TIOCSPTLCK _IOW('T', 0x31, int) _LINUX_MOUNT_H SIOCGIFMETRIC 0x891d __PTRDIFF_T __spins __isalnum_l(c,l) __isctype_l((c), _ISalnum, (l)) __nusers hugetlbfs__mountpoint __WCHAR_MIN __WCHAR_MIN__ _CTYPE_H 1 true 1 f_bavail filename__read_int PTHREAD_CANCELED ((void *) -1) SIOCGIFDSTADDR 0x8917 sysfs__configured debugfs_init_once fs__env_override MOUNT_ATTR_RELATIME 0x00000000 N_TTY 0 SIOCSIFMTU 0x8922 CLOCK_TAI 11 io__get_char TRACEFS_DEFAULT_PATH "/sys/kernel/tracing" __CPU_COUNT_S(setsize,cpusetp) __sched_cpucount (setsize, cpusetp) WCHAR_MAX __WCHAR_MAX N_IRDA 11 fs__debugfs SIOCGIFSLAVE 0x8929 BLKBSZGET MS_MANDLOCK 64 INTPTR_MAX (9223372036854775807L) _T_PTRDIFF BLKSSZGET _IO(0x12,104) _BITS_SETJMP_H 1 __API_DEBUG_INTERNAL_H__ BLKRASET __exctype(name) extern int name (int) __THROW MOUNT_ATTR_STRICTATIME 0x00000020 SIOCGRARP 0x8961 FSPICK_CLOEXEC 0x00000001 bpf_fs__mount MS_REC 16384 __itimerspec_defined 1 __tobody(c,f,a,args) (__extension__ ({ int __res; if (sizeof (c) > 1) { if (__builtin_constant_p (c)) { int __c = (c); __res = __c < -128 || __c > 255 ? __c : (a)[__c]; } else __res = f args; } else __res = (a)[(int) (c)]; __res; })) CINTR CTRL('c') BLKRRPART _IO(0x12, 95) __islower_l(c,l) __isctype_l((c), _ISlower, (l)) SIZE_MAX (18446744073709551615UL) PTHREAD_MUTEX_RECURSIVE_NP FIONREAD 0x541B TIOCMGET 0x5415 SIG_ATOMIC_MIN (-2147483647-1) SIOCPROTOPRIVATE 0x89E0 _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) SIOCDRARP 0x8960 filename__read_str SSIZE_MAX LONG_MAX f_namelen io__getdelim _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) isgraph(c) __isctype((c), _ISgraph) TIOCVHANGUP 0x5437 __isoc99_fscanf isascii_l(c,l) __isascii_l ((c), (l)) _POSIX_SIGQUEUE_MAX 32 TIOCGICOUNT 0x545D UMOUNT_NOFOLLOW UMOUNT_NOFOLLOW TIOCPKT_FLUSHWRITE 2 _POSIX2_BC_DIM_MAX 2048 MS_NODIRATIME MS_NODIRATIME statfs __fsblkcnt64_t TIOCM_LE 0x001 _ASSERT_H 1 UINT_LEAST64_MAX (__UINT64_C(18446744073709551615)) _POSIX_HOST_NAME_MAX 255 _LIMITS_H___ _tolower(c) ((int) (*__ctype_tolower_loc ())[(int) (c)]) SCHAR_MIN (-SCHAR_MAX - 1) MNT_EXPIRE MNT_EXPIRE pr_info(fmt,...) __pr(__pr_info, fmt, ##__VA_ARGS__) fs__init_once S_IWRITE S_IWUSR line_len TIOCSERGETLSR 0x5459 SIOCSIFHWBROADCAST 0x8937 _POSIX_MAX_INPUT 255 _BITS_SCHED_H 1 _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) __toascii_l(c,l) ((l), __toascii (c)) TIOCNXCL 0x540D UINT16_MAX (65535) INT_LEAST16_MAX (32767) TIOCGISO7816 _IOR('T', 0x42, struct serial_iso7816) _STDDEF_H_ __must_check CMIN 1 _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) _POSIX_RE_DUP_MAX 255 SIOCADDMULTI 0x8931 MS_PRIVATE (1<<18) SIOCSIFHWADDR 0x8924 _BITS_STDINT_LEAST_H 1 MS_SLAVE MS_SLAVE procfs__configured sysfs__mount TIOCGDEV _IOR('T', 0x32, unsigned int) __isascii_l(c,l) ((l), __isascii (c)) TIOCM_DSR 0x100 PATH_MAX 4096 MS_BIND 4096 filename__read_ull __undef_NR_OPEN _BSD_PTRDIFF_T_ debugfs__mount TIOCSIG _IOW('T', 0x36, int) __CPUELT(cpu) ((cpu) / __NCPUBITS) BLKFRAGET OPEN_TREE_CLONE 1 MS_SHARED MS_SHARED CHAR_MAX SCHAR_MAX FSMOUNT_CLOEXEC 0x00000001 TIOCGPGRP 0x540F SIOCDEVPRIVATE 0x89F0 PTHREAD_CANCEL_DISABLE PTHREAD_CANCEL_DISABLE __list SYSFS_MAGIC 0x62656572 PTHREAD_STACK_MIN 16384 _STDINT_H 1 ULLONG_MAX (LLONG_MAX * 2ULL + 1ULL) _STR(x) #x S_ISREG(mode) __S_ISTYPE((mode), __S_IFREG) _ASSERT_H_DECLS isalpha(c) __isctype((c), _ISalpha) MS_PRIVATE MS_PRIVATE TCSETAF 0x5408 PTHREAD_CREATE_DETACHED PTHREAD_CREATE_DETACHED toascii(c) __toascii (c) CEOT CEOF TIOCSPGRP 0x5410 SIOCSIFFLAGS 0x8914 INT_FAST32_MIN (-9223372036854775807L-1) PTHREAD_MUTEX_ERRORCHECK TIOCGPTLCK _IOR('T', 0x39, int) _POSIX_DELAYTIMER_MAX 32 BLKRAGET _IO(0x12, 99) N_STRIP 4 getenv fs__sysfs SIOCSIFMETRIC 0x891e _BITS_TIME_H 1 pthread_mutex_unlock TIOCGPTN _IOR('T', 0x30, unsigned int) STATMOUNT_FS_TYPE 0x00000020U SIOCGIFCOUNT 0x8938 SCHED_FIFO 1 __CPU_ALLOC(count) __sched_cpualloc (count) __CPU_FREE(cpuset) __sched_cpufree (cpuset) __ASSERT_FUNCTION __extension__ __PRETTY_FUNCTION__ MS_NOREMOTELOCK (1<<27) UINTMAX_MAX (__UINT64_C(18446744073709551615)) bool _Bool ___int_ptrdiff_t_h FS(name) const char *name ##__mountpoint(void); const char *name ##__mount(void); bool name ##__configured(void); __isctype_l(c,type,locale) ((locale)->__ctype_b[(int) (c)] & (unsigned short int) type) SIOCSIFADDR 0x8916 SIOCGIFCONF 0x8912 MOUNT_ATTR_NODIRATIME 0x00000080 BLKFRASET MS_NODEV 4 __CPU_ISSET_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? ((((const __cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] & __CPUMASK (__cpu))) != 0 : 0; })) FIOQSIZE 0x5460 hugetlbfs__known_mountpoints PROC_SUPER_MAGIC 0x9fa0 bpf_fs__mountpoint WINT_MIN (0u) TCFLSH 0x540B BLKBSZSET isxdigit(c) __isctype((c), _ISxdigit) _ASM_GENERIC_IOCTL_H S_ISCHR(mode) __S_ISTYPE((mode), __S_IFCHR) SIOGIFINDEX SIOCGIFINDEX offsetof __iscntrl_l(c,l) __isctype_l((c), _IScntrl, (l)) MS_UNBINDABLE MS_UNBINDABLE MS_MGC_VAL MS_STRICTATIME MS_STRICTATIME MS_RMT_MASK (MS_RDONLY|MS_SYNCHRONOUS|MS_MANDLOCK|MS_I_VERSION |MS_LAZYTIME) _POSIX_SYMLOOP_MAX 8 SIG_ATOMIC_MAX (2147483647) ispunct_l(c,l) __ispunct_l ((c), (l)) LLONG_MAX __LONG_LONG_MAX__ _SYS_STAT_H 1 MOVE_MOUNT_T_AUTOMOUNTS 0x00000020 BLKFLSBUF toascii_l(c,l) __toascii_l ((c), (l)) LINE_MAX _POSIX2_LINE_MAX MS_ACTIVE (1<<30) MOUNT_ATTR_SIZE_VER0 32 WINT_MAX (4294967295u) PTHREAD_BARRIER_SERIAL_THREAD -1 buf_len MS_SILENT MS_SILENT INT16_MIN (-32767-1) fs__tracefs BLKSECTGET _IO(0x12,103) sysfs__read_int TIOCPKT 0x5420 MS_BORN (1<<29) __sched_priority sched_priority PTHREAD_MUTEX_ADAPTIVE_NP MS_SUBMOUNT (1<<26) _POSIX_SYMLINK_MAX 255 TCSETSW 0x5403 _POSIX_TTY_NAME_MAX 9 S_ISSOCK(mode) __S_ISTYPE((mode), __S_IFSOCK) __val fs__bpf_fs SIOCSRARP 0x8962 TIOCM_SR 0x010 MOVE_MOUNT_F_EMPTY_PATH 0x00000004 BLKGETSIZE _IO(0x12, 96) BLKROGET N_AX25 5 USHRT_MAX (SHRT_MAX * 2 + 1) MNT_DETACH MNT_DETACH S_IREAD S_IRUSR MS_NODEV MS_NODEV strcmp _POSIX_MQ_PRIO_MAX 32 _POSIX_SEM_VALUE_MAX 32767 __CPU_ALLOC_SIZE(count) ((((count) + __NCPUBITS - 1) / __NCPUBITS) * sizeof (__cpu_mask)) MS_MGC_MSK 0xffff0000 MS_MGC_VAL 0xC0ED0000 __fsword_t IOCSIZE_SHIFT (_IOC_SIZESHIFT) INT_LEAST64_MAX (__INT64_C(9223372036854775807)) __ASM_X86_BITSPERLONG_H DELAYTIMER_MAX 2147483647 _TOOLS_LINUX_TYPES_H_ upper_name SIOCGIFFLAGS 0x8913 _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) SIOCGIFMAP 0x8970 TIOCM_CTS 0x020 STATMOUNT_SB_BASIC 0x00000001U _STATFS_F_NAMELEN __DEFINED_ptrdiff_t BC_STRING_MAX _POSIX2_BC_STRING_MAX sysctl__read_int TTYDEF_CFLAG (CREAD | CS7 | PARENB | HUPCL) TCXONC 0x540A SIOCSIFTXQLEN 0x8943 SIOCGARP 0x8954 sysfs__known_mountpoints tracing_path_mount _DYNAMIC_STACK_SIZE_SOURCE 1 CLOSE_RANGE_UNSHARE (1U << 1) tracing _ISOC95_SOURCE RENAME_WHITEOUT (1 << 2) __GLIBC_USE_IEC_60559_BFP_EXT_C23 1 IFTODT(mode) (((mode) & 0170000) >> 12) RENAME_NOREPLACE (1 << 0) DT_UNKNOWN DT_UNKNOWN _DIRENT_HAVE_D_NAMLEN UINTMAX_WIDTH 64 mntpt _LINUX_CLOSE_RANGE_H tracing_path_debugfs_mount _POSIX_FD_SETSIZE _POSIX_OPEN_MAX _ISOC99_SOURCE _PRINTF_NAN_LEN_MAX 4 __GLIBC_USE_LIB_EXT2 1 _DIRENT_HAVE_D_RECLEN __GLIBC_USE_C23_STRTOL 1 DT_CHR DT_CHR tracing_path_tracefs_mount MAXNAMLEN NAME_MAX __GLIBC_USE_ISOC23 1 strncmp DT_WHT DT_WHT _GNU_SOURCE DT_SOCK DT_SOCK UINT_LEAST16_WIDTH 16 str_error_r put_tracing_file SEEK_DATA 3 tracing_path__strerror_open_tp _DIRENT_MATCHES_DIRENT64 1 __USE_DYNAMIC_STACK_SIZE 1 __FDS_BITS(set) ((set)->fds_bits) _ISOC23_SOURCE 1 d_reclen namelist get_events_file __USE_XOPEN2K8XSI 1 __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 1 _ISOC99_SOURCE 1 PTHREAD_STACK_MIN __sysconf (__SC_THREAD_STACK_MIN_VALUE) __USE_XOPEN2KXSI 1 UINT_FAST16_WIDTH __WORDSIZE DT_BLK DT_BLK __USE_GNU 1 d_off __GLIBC_USE_IEC_60559_EXT 1 _POSIX_HIWAT _POSIX_PIPE_BUF _DIRENT_H 1 UINT32_WIDTH 32 __tracing_path_set DTTOIF(dirtype) ((dirtype) << 12) _XOPEN_SOURCE_EXTENDED 1 WINT_WIDTH 32 DT_DIR DT_DIR alphasort64 _ISOC11_SOURCE TEMP_FAILURE_RETRY(expression) (__extension__ ({ long int __result; do __result = (long int) (expression); while (__result == -1L && errno == EINTR); __result; })) _XOPEN_SOURCE_EXTENDED UINT8_WIDTH 8 __GLIBC_USE_IEC_60559_TYPES_EXT 1 __API_FS_TRACING_PATH_H tracing_events__scandir_alphasort d_type _XOPEN_SOURCE 700 __error_t_defined 1 _ISOC23_SOURCE sbuf __dirstream SEEK_HOLE 4 UINT_LEAST8_WIDTH 8 scandir UINT64_WIDTH 64 put_events_file _TOOLS_LINUX_STRING_H_ UINT_FAST8_WIDTH 8 PTRDIFF_WIDTH __WORDSIZE __USE_XOPEN_EXTENDED 1 UINT_LEAST32_WIDTH 32 __GLIBC_USE_DEPRECATED_GETS 0 UINT_FAST64_WIDTH 64 _DYNAMIC_STACK_SIZE_SOURCE _D_EXACT_NAMLEN(d) (strlen ((d)->d_name)) __SC_THREAD_STACK_MIN_VALUE 75 __USE_LARGEFILE 1 __GLIBC_USE_IEC_60559_BFP_EXT 1 _LARGEFILE64_SOURCE __USE_ISOC11 1 DT_REG DT_REG _LARGEFILE_SOURCE scandir64 dirent _XOPEN_SOURCE _DIRENT_HAVE_D_TYPE get_tracing_file DT_LNK DT_LNK RENAME_EXCHANGE (1 << 1) tracing_path L_cuserid 9 _POSIX_QLIMIT 1 UINT16_WIDTH 16 _LARGEFILE_SOURCE 1 UINT_LEAST64_WIDTH 64 __ino64_t strdupa(s) (__extension__ ({ const char *__old = (s); size_t __len = strlen (__old) + 1; char *__new = (char *) __builtin_alloca (__len); (char *) memcpy (__new, __old, __len); })) CLOSE_RANGE_CLOEXEC (1U << 2) UINTPTR_WIDTH __WORDSIZE _DIRENT_HAVE_D_OFF tracing_events__opendir SIG_ATOMIC_WIDTH 32 _ISOC11_SOURCE 1 strndupa(s,n) (__extension__ ({ const char *__old = (s); size_t __len = strnlen (__old, (n)); char *__new = (char *) __builtin_alloca (__len + 1); __new[__len] = '\0'; (char *) memcpy (__new, __old, __len); })) zput_events_file(ptr) ({ free(*ptr); *ptr = NULL; }) DT_FIFO DT_FIFO _POSIX_UIO_MAXIOV 16 WCHAR_WIDTH 32 __GLIBC_USE_IEC_60559_FUNCS_EXT 1 d_fileno d_ino SIZE_WIDTH __WORDSIZE __USE_UNIX98 1 __USE_XOPEN 1 UINT_FAST32_WIDTH __WORDSIZE _ISOC95_SOURCE 1 _D_ALLOC_NAMLEN(d) (((char *) (d) + (d)->d_reclen) - &(d)->d_name[0]) strcpy cgroupfs_find_mountpoint __stringify(x...) __stringify_1(x) __LINUX_STRINGIFY_H strncpy subsys cgroupfs_cache_entry strchr getline strstr __stringify_1(x...) #x maxlen __API_CPU__ cpu__get_max_freq __base_pr __pr_debug __pr_warn __gnuc_va_list __pr_info fp_offset libapi_print_fn_t __va_list_tag _VA_LIST_ _STDARG_H _VA_LIST_T_H __builtin_va_list gp_offset overflow_arg_area reg_save_area _ANSI_STDARG_H_ libapi_set_print __va_copy(d,s) __builtin_va_copy(d,s) va_arg(v,l) __builtin_va_arg(v,l) va_end(v) __builtin_va_end(v) __va_list__ va_start(v,l) __builtin_va_start(v,l) vfprintf errnum __xpg_strerror_r _GNU_SOURCE buflen LIBPERF_DEBUG libperf_print_fn_t __libperf_pr LIBPERF_ERR LIBPERF_DEBUG2 LIBPERF_DEBUG3 libperf_init long double libperf_print LIBPERF_INFO libperf_print_level GNU C17 14.2.0 -mtune=generic -march=x86-64 -g -fPIC -fvisibility=hidden -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection LIBPERF_WARN _ISgraph nr_cpus_conf cpu_map__new_sysconf __u16 __u8 orig __perf_cpu_map__nr cmp_cpu perf_cpu_map__intersect __compar_fn_t __u32 nr_cpus perf_cpu_map out_free_tmp refcount_t perf_cpu_map__merge merged __u32_alias_t _ISprint __ret high payload_size perf_cpu_map__put perf_cpu_map__read __ret_warn_on __ptr cpu_map__trim_new other __read_once_size _ISpunct tmp_len max_entries __perf_cpu_map__cpu onlnf __uint64_t _ISalnum tmp_cpus _max1 _max2 __u16_alias_t refcount_read perf_cpu_map__new_online_cpus _ISxdigit _ISupper __ctype_b_loc _IScntrl perf_cpu_map__get __ret_warn_once refcount_inc cpu_a cpu_b atomic_read refcount_struct start_cpu cpu_map__new_sysfs_online perf_cpu_map__has perf_cpu_map__refcnt atomic_set perf_cpu_map__max perf_cpu_map__alloc __u8_alias_t qsort invalid perf_cpu_map__new_any_cpu _ISalpha __warned refcount_inc_not_zero _ISblank atomic_cmpxchg _ISspace refs __u64_alias_t malloc perf_cpu_map__set_nr refcount_set __old _ISlower new_max perf_cpu perf_cpu_map__has_any_cpu_or_is_empty perf_cpu_map__min perf_cpu_map__equal cpu_at_idx perf_cpu_map__idx _ISdigit perf_cpu_map__is_any_cpu_or_is_empty perf_cpu_map__new refcount_sub_and_test perf_cpu_map__is_empty refcount_dec_and_test perf_cpu_map__has_any_cpu perf_cpu_map__is_subset end_cpu perf_thread_map__comm thread_map_data perf_thread_map perf_thread_map__delete err_thread perf_thread_map__pid perf_thread_map__realloc perf_thread_map__reset perf_thread_map__set_pid perf_thread_map__new_dummy nr_threads __pid_t perf_thread_map__new_array perf_thread_map__put perf_thread_map__get perf_thread_map__nr ncpus perf_evsel__apply_filter PERF_FORMAT_TOTAL_TIME_RUNNING probe_offset perf_evsel__read_size row_size perf_evsel__read __reserved_1 exclude_hv comm_exec zalloc perf_mmap__init aux_sample_size perf_evsel__alloc_fd empty_cpu_map perf_evsel__attr perf_evsel__mmap inherit_thread use_clockid is_pmu_core perf_mmap__read_self perf_evsel__free_fd unmap_cb perf_evsel__new wakeup_events sample_id_all perf_evsel__alloc_id sample_regs_user PERF_FORMAT_GROUP INIT_LIST_HEAD perf_counts_values__scale __u64 perf_mmap xyarray__max_x xyarray__max_y perf_evsel__free_id precise_ip remove_on_exec empty_thread_map sample_period exclusive PERF_FORMAT_TOTAL_TIME_ENABLED perf_evsel__cpus task perf_mmap__munmap config1 config2 config3 perf_evsel__threads xyarray__new disabled uprobe_path context_switch nr_members perf_evsel__alloc_mmap perf_evsel__enable_thread get_group_fd perf_evsel__close_fd perf_evsel__enable perf_evsel__run_ioctl perf_evsel__close sample_stack_user perf_evsel__init PERF_FORMAT_ID libperf_unmap_cb_t enable_on_exec sample_max_stack wakeup_watermark own_cpus kprobe_addr sig_data exclude_guest perf_event_read_format exclude_kernel text_poke xyarray perf_evsel__mmap_base mmap_data __zfree sample_regs_intr event_copy PERF_FORMAT_MAX prot bp_addr perf_evsel__delete perf_evsel perf_evsel__ioctl perf_mmap__mmap __xyarray__entry perf_evsel__munmap perf_evsel__disable perf_evsel__disable_cpu __s32 exclude_user sample_freq contents exclude_callchain_user aux_watermark pinned kprobe_func perf_evsel__close_fd_cpu perf_evsel__close_cpu bp_len exclude_host entry_size perf_evsel__enable_cpu nthreads evsel_fd pscaled inherit_stat perf_evsel__read_group bp_type perf_evsel__adjust_values perf_evsel__open exclude_callchain_kernel exclude_idle sys_perf_event_open write_backward event_copy_sz branch_sample_type aux_output perf_mmap_param sigtrap PERF_FORMAT_LOST requires_cpu xyarray__delete perf_counts_values cpu_map_idx __s8 __reserved_2 __reserved_3 perf_event_attr perf_evlist__alloc_mmap perf_evlist__open perf_evlist__mmap_cb_mmap perf_evlist__add_pollfd perf_evlist__init perf_evlist__delete mmap_per_evsel user_requested_cpus all_cpus fdarray__available_entries revents_and_mask flgs heads perf_evlist__mmap_ops __list_del nfds nr_entries mmap_ovw perf_evlist_mmap__cb_idx_t list_add_tail out_err perf_evlist__close perf_evlist__nr_groups perf_evlist__exit perf_evlist__add perf_evlist__id_add_fd out_unmap perf_mmap__get perf_evlist_mmap__cb_mmap_t perf_evlist__purge machine_pid perf_evlist__set_mmap_first has_user_cpus perf_evlist__id_add perf_evlist__go_system_wide perf_evlist__filter_pollfd perf_evlist__mmap perf_evlist_mmap_ops needs_map_propagation hlist_add_head hlist_node perf_evlist__enable list_del_init read_data perf_evlist__new pprev perf_evlist__mmap_cb_get __perf_evlist__set_leader evlist_cpu mmap_per_thread perf_evlist__next_mmap perf_evlist__nr_mmaps mmap_per_cpu perf_evlist__first perf_evlist__poll perf_evlist__id_hash perf_evlist__remove __list_del_entry perf_evlist__reset_id_hash perf_evlist perf_evlist__alloc_pollfd revent perf_evlist__disable perf_evlist__read_format perf_evlist__munmap_filtered perf_evlist__next hlist_head perf_evlist__set_maps perf_sample_id __write_once_size perf_evlist_mmap__cb_get_t mmap_ovw_first fcntl perf_mmap__put cpu_idx __list_add hash_64_generic perf_evsel__set_sid_idx __mptr _output_overwrite __func__ perf_evlist__munmap __perf_evlist__propagate_maps perf_record_header_feature next_prev_tid time_cycles pheader perf_record_header_build_id perf_record_switch perf_record_cpu_map cap_user_time_zero perf_record_auxtrace_error reference next_prev_pid perf_record_header_tracing_data perf_record_lost cap_bit0 perf_record_thread_map cap_user_rdpmc perf_record_mask_cpu_map32 ino_generation perf_record_throttle ring_buffer_write_tail pgoff mask64_data perf_record_auxtrace perf_record_cpu_map_data ptid perf_record_header_attr ksym_type perf_record_thread_map_entry time_enabled range_cpu_data cap_user_time perf_record_stat perf_record_aux_output_hw_id pack old_len perf_mmap__empty id_index_entry event_id feat_id perf_record_text_poke_event mask32_data perf_record_bpf_event data_size time_mask perf_record_id_index perf_record_mask_cpu_map64 perf_record_lost_samples reserved2__ perf_record_ksymbol perf_mmap__consume time_offset reserved1__ read_timestamp ring_buffer_read_head time_running cap_____res evcnt perf_mmap__read_head __reserved stream_id perf_mmap__mmap_len perf_mmap__read_event build_id_size perf_record_mmap2 perf_record_compressed perf_record_cgroup perf_event_mmap_page time_shift perf_trace_event_type __pad aux_size startp ppid unit evt_head data_tail __int64_t compat_version __perf_mmap__read_init read_perf_counter nr_namespaces reserved__ _min1 _min2 perf_ns_link_info perf_record_auxtrace_info mul_u64_u32_shr perf_record_read capabilities perf_record_comm diff cap_user_time_short cpu_map_entries ___p1 misc data_head cpus_data aux_offset perf_mmap__read perf_record_event_update perf_record_stat_round perf_mmap__write_tail time_mult overwrite_rb_find_range new_len perf_record_stat_config perf_record_mmap perf_record_header_event_type perf_record_fork aux_tail perf_record_range_cpu_map __s64 data_offset perf_record_event_update_scale perf_record_time_conv perf_record_sample pmc_width perf_record_itrace_start delta perf_record_event_update_cpus feat perf_mmap__read_done perf_record_namespaces perf_record_stat_config_entry aux_head cap_bit0_is_deprecated perf_record_aux long_size perf_event_header xyarray__reset is_read writen pread offs preadn buf_start STATX__RESERVED 0x80000000U __getcwd_chk STATX_UID 0x00000008U _TOOLS_LINUX_COMPILER_H_ _compiletime_assert(condition,msg,prefix,suffix) __compiletime_assert(condition, msg, prefix, suffix) __SUBCMD_UTIL_H __glibc_unsigned_or_positive(__l) ((__typeof (__l)) 0 < (__typeof (__l)) -1 || (__builtin_constant_p (__l) && (__l) > 0)) pager_env execv_cmd __aligned(x) __attribute__((aligned(x))) pwd_stat __acquires(x) __glibc_fortify_n(f,__l,__s,__osz,...) (__glibc_safe_or_unknown_len (__l, __s, __osz) ? __ ## f ## _alias (__VA_ARGS__) : (__glibc_unsafe_len (__l, __s, __osz) ? __ ## f ## _chk_warn (__VA_ARGS__, (__osz) / (__s)) : __ ## f ## _chk (__VA_ARGS__, (__osz) / (__s)))) st_uid __same_type(a,b) __builtin_types_compatible_p(typeof(a), typeof(b)) st_size __always_inline inline __attribute__((always_inline)) __statx_defined 1 __ap st_blksize __fmt STATX_MODE 0x00000002U WRITE_ONCE(x,val) ({ union { typeof(x) __val; char __c[1]; } __u = { .__val = (val) }; __write_once_size(&(x), __u.__c, sizeof(x)); __u.__val; }) st_gid argv0 __syscall_slong_t st_nlink __PERF_SUBCMD_CONFIG_H __fortify_clang_warning(__c,__msg) st_ctim STATX_BLOCKS 0x00000400U _BITS_STDIO2_DEC_H 1 __scanf(a,b) __attribute__((format(scanf, a, b))) fread_unlocked(ptr,size,n,stream) (__extension__ ((__builtin_constant_p (size) && __builtin_constant_p (n) && (size_t) (size) * (size_t) (n) <= 8 && (size_t) (size) != 0) ? ({ char *__ptr = (char *) (ptr); FILE *__stream = (stream); size_t __cnt; for (__cnt = (size_t) (size) * (size_t) (n); __cnt > 0; --__cnt) { int __c = getc_unlocked (__stream); if (__c == EOF) break; *__ptr++ = __c; } ((size_t) (size) * (size_t) (n) - __cnt) / (size_t) (size); }) : (((__builtin_constant_p (size) && (size_t) (size) == 0) || (__builtin_constant_p (n) && (size_t) (n) == 0)) ? ((void) (ptr), (void) (stream), (void) (size), (void) (n), (size_t) 0) : fread_unlocked (ptr, size, n, stream)))) __strlcpy_chk STATX_WRITE_ATOMIC 0x00010000U __rcu __stack_chk_fail STATX_BASIC_STATS 0x000007ffU st_atim __compiletime_error(message) __attribute__((error(message))) fwrite_unlocked(ptr,size,n,stream) (__extension__ ((__builtin_constant_p (size) && __builtin_constant_p (n) && (size_t) (size) * (size_t) (n) <= 8 && (size_t) (size) != 0) ? ({ const char *__ptr = (const char *) (ptr); FILE *__stream = (stream); size_t __cnt; for (__cnt = (size_t) (size) * (size_t) (n); __cnt > 0; --__cnt) if (putc_unlocked (*__ptr++, __stream) == EOF) break; ((size_t) (size) * (size_t) (n) - __cnt) / (size_t) (size); }) : (((__builtin_constant_p (size) && (size_t) (size) == 0) || (__builtin_constant_p (n) && (size_t) (n) == 0)) ? ((void) (ptr), (void) (stream), (void) (size), (void) (n), (size_t) 0) : fwrite_unlocked (ptr, size, n, stream)))) GNU C99 14.2.0 -mtune=generic -march=x86-64 -ggdb3 -O6 -std=gnu99 -fPIC -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection STATX_ATTR_APPEND 0x00000020 __uid_t ALLOC_GROW(x,nr,alloc) do { if ((nr) > alloc) { if (alloc_nr(alloc) < (nr)) alloc = (nr); else alloc = alloc_nr(alloc); x = xrealloc((x), alloc * sizeof(*(x))); } } while(0) set_argv_exec_path __fortify_clang_warn_if_src_too_large(__dest,__src) __blkcnt_t __glibc_fortify(f,__l,__s,__osz,...) (__glibc_safe_or_unknown_len (__l, __s, __osz) ? __ ## f ## _alias (__VA_ARGS__) : (__glibc_unsafe_len (__l, __s, __osz) ? __ ## f ## _chk_warn (__VA_ARGS__, __osz) : __ ## f ## _chk (__VA_ARGS__, __osz))) __getcwd_alias READ_ONCE(x) ({ union { typeof(x) __val; char __c[1]; } __u = { .__c = { 0 } }; __read_once_size(&(x), __u.__c, sizeof(x)); __u.__val; }) __asprintf_chk old_path __fortify_clang_warning_only_if_bos_lt2(__n,__buf,div,__complaint) __wur __attribute_warn_unused_result__ __fprintf_chk __mode_t __glibc_objsize0(__o) __builtin_dynamic_object_size (__o, 0) __SUBCMD_EXEC_CMD_H STATX_ATTR_ENCRYPTED 0x00000800 __FD_ELT noinline __attribute__((noinline)) __maybe_unused __attribute__((unused)) STATX_ATTR_AUTOMOUNT 0x00001000 STATX_BTIME 0x00000800U strlcpy STATX_SIZE 0x00000200U __PASTE(a,b) ___PASTE(a, b) __nocf_check __attribute__((nocf_check)) GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) add_path __fortify_clang_warning_only_if_bos0_lt(__n,__buf,__complaint) fallthrough __attribute__((__fallthrough__)) __releases(x) make_nonrelative_path _BITS_STDIO2_H 1 STATX_TYPE 0x00000001U get_pwd_cwd system_path __acquire(x) (void)0 __nlink_t st_mode STATX_ATTR_MOUNT_ROOT 0x00002000 __stream _BITS_SELECT_DECL_H 1 STATX_SUBVOL 0x00008000U STATX_MNT_ID 0x00001000U __fortify_clang_overload_arg0(__type,__attr,__name) __fortify_clang_overload_arg (__type, __attr, __name) params get_argv_exec_path __src __noreturn __attribute__((noreturn)) timespec STATX_ATTR_NODUMP 0x00000040 OPTIMIZER_HIDE_VAR(var) __asm__ ("" : "=r" (var) : "0" (var)) is_dir_sep(c) ((c) == '/') __glibc_safe_len_cond(__l,__s,__osz) ((__l) <= (__osz) / (__s)) strndup STATX_ATTR_IMMUTABLE 0x00000010 asm_goto_output(x...) asm goto(x) __statx_timestamp_defined 1 stat64 __FD_ELT(d) __extension__ ({ long int __d = (d); (__builtin_constant_p (__d) ? (0 <= __d && __d < __FD_SETSIZE ? (__d / __NFDBITS) : __fdelt_warn (__d)) : __fdelt_chk (__d)); }) subcmd_config __time_t astrcatf(out,fmt,...) ({ char *tmp = *(out); if (asprintf((out), "%s" fmt, tmp ?: "", ## __VA_ARGS__) == -1) die("asprintf failed"); free(tmp); }) STATX_MNT_ID_UNIQUE 0x00004000U _GNU_SOURCE 1 likely(x) __builtin_expect(!!(x), 1) __blksize_t STATX_NLINK 0x00000004U __read_mostly compiletime_assert(condition,msg) _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) MAX_ARGS 32 execvp __strlcpy_alias __fortify_clang_warn_if_dest_too_small(__dest,__len) __USE_EXTERN_INLINES 1 report __attribute_const__ extract_argv0_path _FORTIFY_SOURCE 3 _BITS_STDIO_H 1 _LINUX_STAT_H __dest unreachable() __builtin_unreachable() __STDIO_INLINE __glibc_objsize(__o) __builtin_dynamic_object_size (__o, 1) __builtin___memcpy_chk STATX_ALL 0x00000fffU STATX_INO 0x00000100U __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) __getcwd_chk_warn __must_hold(x) setup_path exec_cmd_init __fortified_attr_access(a,o,s) __printf(a,b) __attribute__((format(printf, a, b))) __STRINGS_FORTIFIED 1 STATX_GID 0x00000010U unlikely(x) __builtin_expect(!!(x), 0) __init new_path __LINUX_COMPILER_TYPES_H ___PASTE(a,b) a ##b zfree(ptr) ({ free(*ptr); *ptr = NULL; }) fread_unlocked __is_constexpr(x) (sizeof(int) == sizeof(*(8 ? ((void *)((long)(x) * 0l)) : (int *)8))) __dev_t __glibc_reserved slash __weak __attribute__((weak)) __glibc_safe_or_unknown_len(__l,__s,__osz) ((__builtin_constant_p (__osz) && (__osz) == (__SIZE_TYPE__) -1) || (__glibc_unsigned_or_positive (__l) && __builtin_constant_p (__glibc_safe_len_cond ((__SIZE_TYPE__) (__l), (__s), (__osz))) && __glibc_safe_len_cond ((__SIZE_TYPE__) (__l), (__s), (__osz)))) __pad0 tv_nsec barrier() __asm__ __volatile__("": : :"memory") STATX_ATIME 0x00000020U STATX_DIOALIGN 0x00002000U STATX_CTIME 0x00000080U __STDIO_INLINE __extern_inline st_rdev argc st_dev __OPTIMIZE__ 1 __fortify_clang_warn_if_dest_too_small0(__dest,__len) __fortify_clang_warning_only_if_bos_lt(__n,__buf,__complaint) __pure __attribute__((pure)) __glibc_unsafe_len(__l,__s,__osz) (__glibc_unsigned_or_positive (__l) && __builtin_constant_p (__glibc_safe_len_cond ((__SIZE_TYPE__) (__l), __s, __osz)) && !__glibc_safe_len_cond ((__SIZE_TYPE__) (__l), __s, __osz)) STATX_ATTR_VERITY 0x00100000 __gid_t getcwd __builtin___vsnprintf_chk __fortify_use_clang 0 nargv st_blocks __buf STATX_ATTR_COMPRESSED 0x00000004 __STDLIB_MB_LEN_MAX 16 _BITS_UNISTD_DECL_H 1 __always_unused __attribute__((__unused__)) exec_name cwd_stat __used __attribute__((__unused__)) vsnprintf __fortify_clang_warning_only_if_bos0_lt2(__n,__buf,__div,complaint) prepare_exec_cmd __packed __attribute__((packed)) __cond_lock(x,c) (c) st_ino execl_cmd STATX_ATTR_WRITE_ATOMIC 0x00400000 __naked __attribute__((__naked__)) __ino_t __compiletime_assert(condition,msg,prefix,suffix) do { extern void prefix ## suffix(void) __compiletime_error(msg); if (!(condition)) prefix ## suffix(); } while (0) astrcat __release(x) (void)0 alloc_nr(x) (((x)+16)*3/2) __fortify_clang_overload_arg(__type,__attr,__name) __type __attr __name is_absolute_path __USE_FORTIFY_LEVEL 3 STATX_ATTR_DAX 0x00200000 st_mtim STATX_MTIME 0x00000040U exec_path_env _BITS_STRING_FORTIFIED_H 1 CR0 0000000 other_cmds B300 0000007 ONLCR 0000004 B200 0000006 ECHOPRT 0002000 IEXTEN 0100000 NCCS 32 FF1 0100000 B150 0000005 list_commands_in_dir B4000000 0010017 readdir64 TCSADRAIN 1 FLUSHO 0010000 B460800 0010004 memcmp INLCR 0000100 ECHOKE 0004000 XTABS 0014000 NL0 0000000 IUTF8 0040000 putchar B1000000 0010010 CREAD 0000200 __printf_chk VMIN 6 __builtin_memset ONLRET 0000040 __isoc23_strtol TCIFLUSH 0 TCIOFF 2 ECHO 0000010 add_cmdname B1500000 0010012 __SUBCMD_HELP_H TAB2 0010000 IXANY 0004000 PARENB 0000400 B57600 0010001 exclude_cmds OFILL 0000100 VT1 0040000 VEOL2 16 TCSAFLUSH 2 ISIG 0000001 ICRNL 0000400 B3000000 0010015 B50 0000001 load_command_list main_cmds cmdname_compare B1800 0000012 _HAVE_STRUCT_TERMIOS_C_ISPEED 1 ICANON 0000002 B75 0000002 B600 0000010 CMSPAR 010000000000 entlen mput_char pretty_print_string_list VQUIT 1 CEOL '\0' ECHOE 0000020 B3500000 0010016 _TERMIOS_H 1 strstarts TCOON 1 title xrealloc get_term_dimensions TCOOFF 0 BS0 0000000 ECHOK 0000040 B110 0000003 B1152000 0010011 VEOF 4 HUPCL 0002000 OPOST 0000001 B500000 0010005 ws_row TCIOFLUSH 2 VERASE 2 B2000000 0010013 VKILL 3 extlen B19200 0000016 ECHONL 0000100 CSIZE 0000060 rows CIBAUD 002003600000 OFDEL 0000200 ECHOCTL 0001000 TAB0 0000000 TCION 3 TABDLY 0014000 PENDIN 0040000 NLDLY 0000400 VSTOP 9 IMAXBEL 0020000 B2500000 0010014 CBAUD 000000010017 IXOFF 0010000 OCRNL 0000010 BSDLY 0020000 longest CR3 0003000 B230400 0010003 VWERASE 14 winsize EXTA B19200 NL1 0000400 VEOL 11 CLOCAL 0004000 __nptr uniq IGNBRK 0000001 NOFLSH 0000200 BRKINT 0000002 B4800 0000014 __len XCASE 0000004 is_executable is_in_cmdlist FF0 0000000 VSUSP 10 ISTRIP 0000040 FFDLY 0100000 INPCK 0000020 PARODD 0001000 TAB3 0014000 __MAX_BAUD B4000000 B9600 0000015 VTDLY 0040000 PARMRK 0000010 paths B38400 0000017 CR1 0001000 colon EXTPROC 0200000 B134 0000004 TAB1 0004000 B1200 0000011 excludes B115200 0010002 CSTATUS '\0' TCOFLUSH 1 B2400 0000013 VSTART 8 max_cols IUCLC 0001000 CRTSCTS 020000000000 CS5 0000000 list_commands CSTOPB 0000100 B576000 0010006 closedir clean_cmdnames CBAUDEX 000000010000 CS6 0000020 _HAVE_STRUCT_TERMIOS_C_OSPEED 1 ONOCR 0000020 ADDRB 04000000000 VREPRINT 12 IGNPAR 0000004 EXTB B38400 CCEQ(val,c) ((c) == (val) && (val) != _POSIX_VDISABLE) ws_ypixel ws_xpixel CS8 0000060 CS7 0000040 CRDLY 0003000 ws_col has_extension TCSANOW 0 IXON 0002000 VSWTC 7 BS1 0020000 VTIME 5 VT0 0000000 IGNCR 0000200 OLCUC 0000002 TOSTOP 0000400 env_path VLNEXT 15 VDISCARD 13 readdir prefix_len VINTR 0 CR2 0002000 B921600 0010007 sigchain_fun si_status _sifields._sigchld.si_status SIGALRM 14 __stack_t_defined 1 si_call_addr _sifields._sigsys._call_addr POLL_OUT POLL_OUT SIGCLD SIGCHLD BUS_MCEERR_AR BUS_MCEERR_AR SIGRTMIN (__libc_current_sigrtmin ()) __SUBCMD_RUN_COMMAND_H ILL_PRVOPC ILL_PRVOPC isatty si_lower _sifields._sigfault._bounds._addr_bnd._lower _BITS_SIGINFO_CONSTS_ARCH_H 1 POLL_PRI POLL_PRI SA_NOCLDWAIT 2 SEGV_MTEAERR SEGV_MTEAERR SIGPWR 30 SEGV_ACCADI SEGV_ACCADI SI_QUEUE SI_QUEUE si_syscall _sifields._sigsys._syscall BUS_MCEERR_AO BUS_MCEERR_AO si_upper _sifields._sigfault._bounds._addr_bnd._upper SIGEV_NONE SIGEV_NONE _BITS_SIGSTACK_H 1 SIGINT 2 _NSIG (__SIGRTMAX + 1) REG_CR2 REG_CR2 SIGPROF 27 REG_RDI REG_RDI SA_STACK SA_ONSTACK access REG_RIP REG_RIP _BITS_SS_FLAGS_H 1 spawned_pager sa_sigaction __sigaction_handler.sa_sigaction sigev_notify_function _sigev_un._sigev_thread._function _SIGNAL_H FPE_INTDIV FPE_INTDIV no_stderr __SI_ASYNCIO_AFTER_SIGIO 1 __SI_CLOCK_T __clock_t SEGV_MAPERR SEGV_MAPERR REG_RDX REG_RDX SEGV_ACCERR SEGV_ACCERR __SUBCMD_PAGER_H pager_init SI_USER SI_USER FPE_INTOVF FPE_INTOVF SIGURG 23 SIGBUS 7 SIGCHLD 17 REG_R11 REG_R11 FPE_FLTUNK FPE_FLTUNK REG_R12 REG_R12 REG_R13 REG_R13 si_addr _sifields._sigfault.si_addr REG_R14 REG_R14 atexit SIGSYS 31 REG_R15 REG_R15 pager_process SEGV_PKUERR SEGV_PKUERR __fd_mask __sigevent_t_defined 1 __fdelt_chk REG_R10 REG_R10 SIGIOT SIGABRT FPE_FLTINV FPE_FLTINV TRAP_HWBKPT TRAP_HWBKPT exception SI_KERNEL SI_KERNEL _BITS_SIGNUM_ARCH_H 1 fflush __SI_ERRNO_THEN_CODE 1 MINSIGSTKSZ 2048 ILL_PRVREG ILL_PRVREG __SIGRTMIN 32 si_ptr _sifields._rt.si_sigval.sival_ptr REG_TRAPNO REG_TRAPNO _SYS_UCONTEXT_H 1 __suseconds_t SEGV_ADIPERR SEGV_ADIPERR ILL_ILLTRP ILL_ILLTRP tv_usec wait_for_pager SIGXCPU 24 __SI_MAX_SIZE 128 SI_TKILL SI_TKILL SA_RESETHAND 0x80000000 sigchain_push_common REG_RSI REG_RSI si_stime _sifields._sigchld.si_stime si_timerid _sifields._timer.si_tid SEGV_ADIDERR SEGV_ADIDERR SIGILL 4 SIGTTIN 21 TRAP_BRKPT TRAP_BRKPT _BITS_SIGCONTEXT_H 1 _BITS_SIGNUM_GENERIC_H 1 no_stdout FPE_CONDTRAP FPE_CONDTRAP no_stdin SA_SIGINFO 4 __SUBCMD_SIGCHAIN_H si_overrun _sifields._timer.si_overrun __SIGEV_MAX_SIZE 64 SIGSEGV 11 preexec_cb select __SI_BAND_TYPE long int MINSIGSTKSZ SIGSTKSZ _BITS_SIGINFO_CONSTS_H 1 SA_INTERRUPT 0x20000000 SI_ASYNCIO SI_ASYNCIO si_uid _sifields._kill.si_uid _BITS_SIGACTION_H 1 pager_get_columns REG_OLDMASK REG_OLDMASK REG_R8 REG_R8 CLD_CONTINUED CLD_CONTINUED _BITS_SIGTHREAD_H 1 sigmask(sig) __glibc_macro_warning ("sigmask is deprecated") ((int)(1u << ((sig) - 1))) REG_CSGSFS REG_CSGSFS __ctx(fld) fld fds_bits IS_RUN_COMMAND_ERR(x) (-(x) >= ERR_RUN_COMMAND_FORK) si_value _sifields._rt.si_sigval REG_R9 REG_R9 FPE_FLTUND FPE_FLTUND pager_columns __NGREG 23 FPE_FLTRES FPE_FLTRES CLD_EXITED CLD_EXITED SEGV_MTESERR SEGV_MTESERR CLD_DUMPED CLD_DUMPED pager_preexec ____sigval_t_defined __SIGEV_PAD_SIZE ((__SIGEV_MAX_SIZE / sizeof (int)) - 4) FPE_FLTSUB FPE_FLTSUB si_band _sifields._sigpoll.si_band SIGUSR1 10 SIGUSR2 12 stdout_to_stderr __sig_atomic_t_defined 1 __fdelt_warn SA_ONSTACK 0x08000000 SIG_ERR ((__sighandler_t) -1) SS_DISABLE SS_DISABLE SA_ONESHOT SA_RESETHAND SIGKILL 9 SI_MESGQ SI_MESGQ SA_NOCLDSTOP 1 REG_RAX REG_RAX si_pid _sifields._kill.si_pid SIGXFSZ 25 __SI_SIGFAULT_ADDL FP_XSTATE_MAGIC2 0x46505845U POLL_HUP POLL_HUP ILL_COPROC ILL_COPROC timeval SEGV_BNDERR SEGV_BNDERR SIGTTOU 22 SIGSTKSZ 8192 ILL_ILLOPN ILL_ILLOPN SIG_IGN ((__sighandler_t) 1) SIG_BLOCK 0 __siginfo_t_defined 1 SIGRTMAX (__libc_current_sigrtmax ()) finish_result fd_set __sigstack_defined 1 SIGTRAP 5 CLD_KILLED CLD_KILLED REG_RSP REG_RSP __SIGRTMAX 64 FP_XSTATE_MAGIC2_SIZE sizeof (FP_XSTATE_MAGIC2) ILL_ILLADR ILL_ILLADR SIGFPE 8 finish_command SIGPOLL 29 forced_pager si_fd _sifields._sigpoll.si_fd __arr SIGWINCH 28 SIGQUIT 3 TRAP_UNK TRAP_UNK SIGTERM 15 REG_ERR REG_ERR force_pager SIGIO SIGPOLL NSIG _NSIG SA_NODEFER 0x40000000 SI_SIGIO SI_SIGIO SEGV_CPERR SEGV_CPERR si_utime _sifields._sigchld.si_utime __SI_ALIGNMENT REG_RBP REG_RBP pager_argv ILL_BADSTK ILL_BADSTK SIGHUP 1 SIGSTKFLT 16 REG_RBX REG_RBX REG_EFL REG_EFL SIGTSTP 20 TRAP_BRANCH TRAP_BRANCH ILL_BADIADDR ILL_BADIADDR no_exec_cmd SIG_DFL ((__sighandler_t) 0) SI_ASYNCNL SI_ASYNCNL SIGEV_THREAD SIGEV_THREAD SA_NOMASK SA_NODEFER sa_handler __sigaction_handler.sa_handler _BITS_SIGINFO_ARCH_H 1 SIGPIPE 13 dup2 SIG_HOLD ((__sighandler_t) 2) FPE_FLTDIV FPE_FLTDIV SIGEV_SIGNAL SIGEV_SIGNAL raise __SI_HAVE_SIGSYS 1 si_int _sifields._rt.si_sigval.sival_int setup_pager FPE_FLTOVF FPE_FLTOVF POLL_IN POLL_IN RUN_COMMAND_NO_STDIN 1 RUN_COMMAND_STDOUT_TO_STDERR 4 sigchain_pop SIGEV_THREAD_ID SIGEV_THREAD_ID FP_XSTATE_MAGIC1 0x46505853U child_process SIGABRT 6 SIG_SETMASK 2 TRAP_TRACE TRAP_TRACE BUS_ADRERR BUS_ADRERR sigev_notify_attributes _sigev_un._sigev_thread._attribute SIGSTKSZ sysconf (_SC_SIGSTKSZ) _BITS_SIGEVENT_CONSTS_H 1 si_addr_lsb _sifields._sigfault.si_addr_lsb pager_in_use BUS_OBJERR BUS_OBJERR __ctx start_command CLD_STOPPED CLD_STOPPED SIG_UNBLOCK 1 POLL_MSG POLL_MSG SIGCONT 18 RUN_EXEC_CMD 2 BUS_ADRALN BUS_ADRALN wait_for_pager_signal SA_RESTART 0x10000000 SI_DETHREAD SI_DETHREAD SS_ONSTACK SS_ONSTACK SIGVTALRM 26 si_pkey _sifields._sigfault._bounds._pkey POLL_ERR POLL_ERR ILL_ILLOPC ILL_ILLOPC SI_TIMER SI_TIMER REG_RCX REG_RCX si_arch _sifields._sigsys._arch SIGSTOP 19 __SI_PAD_SIZE ((__SI_MAX_SIZE / sizeof (int)) - 4) CLD_TRAPPED CLD_TRAPPED NGREG __NGREG PARSE_OPT_LASTARG_DEFAULT PARSE_OPT_LIST_SUBCMDS cpu_to_le16 max(x,y) ({ typeof(x) _max1 = (x); typeof(y) _max2 = (y); (void) (&_max1 == &_max2); _max1 > _max2 ? _max1 : _max2; }) is_abbreviated PARSE_OPT_KEEP_DASHDASH roundup(x,y) ( { const typeof(y) __y = y; (((x) + (__y - 1)) / __y) * __y; } ) toupper(c) __tobody (c, toupper, *__ctype_toupper_loc (), (c)) ambiguous_option __PERF_ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) unknown options__order error_buf OPT_CALLBACK_OPTARG(s,l,v,d,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .flags = PARSE_OPT_OPTARG, .data = (d) } BUILD_BUG_ON_INVALID(e) ((void)(sizeof((__force long)(e)))) parse_opt_type excl_opt be64_to_cpu bswap_64 check_vtype(v,type) ( BUILD_BUG_ON_ZERO(!__builtin_types_compatible_p(typeof(v), type)) + v ) __builtin_memmove ambiguous_flags PARSE_OPT_DISABLED optwarning PARSE_OPT_OPTARG __SUBCMD_PARSE_OPTIONS_H PARSE_OPT_NOEMPTY subcommands strcasestr match OPTION_SET_PTR OPTION_BOOLEAN OPT__VERBOSITY(var) { OPTION_CALLBACK, 'v', "verbose", (var), NULL, "be more verbose", PARSE_OPT_NOARG, &parse_opt_verbosity_cb, 0 }, { OPTION_CALLBACK, 'q', "quiet", (var), NULL, "be more quiet", PARSE_OPT_NOARG, &parse_opt_verbosity_cb, 0 } arg_end OPT_ULONG(s,l,v,h) { .type = OPTION_ULONG, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned long *), .help = (h) } cpu_to_le32 PARSE_OPT_NONEG shortopt round_down(x,y) ((x) & ~__round_mask(x, y)) __builtin___snprintf_chk defval internal_help PARSE_OPT_EXCLUSIVE parse_short_opt OPTION_GROUP get_arg PARSE_OPT_NOARG __TOOLS_LINUX_KERNEL_H PARSE_OPT_NOBUILD static_assert _TOOLS_MATH_H PARSE_OPT_KEEP_UNKNOWN OPT_CALLBACK_DEFAULT_NOOPT(s,l,v,a,h,f,d) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .arg = (a), .help = (h), .callback = (f), .defval = (intptr_t)d, .flags = PARSE_OPT_LASTARG_DEFAULT | PARSE_OPT_NOARG} toupper_l(c,locale) __toupper_l ((c), (locale)) le64_to_cpu __tolower_l(c,locale) __tobody (c, __tolower_l, (locale)->__ctype_tolower, (c, locale)) BUILD_BUG_ON(condition) BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition) check_typos bswap_64(x) __bswap_64 (x) usage_with_options can_skip be16_to_cpu bswap_16 PARSE_OPT_KEEP_ARGV0 _LINUX_BUILD_BUG_H parse_options_usage assert_perror(errnum) (!(errnum) ? __ASSERT_VOID_CAST (0) : __assert_perror_fail ((errnum), __FILE__, __LINE__, __ASSERT_FUNCTION)) __isoc23_strtoul cpu_to_be64 bswap_64 BUG_ON(cond) assert(!(cond)) __vasprintf_chk usage_with_options_internal min_t(type,x,y) min((type)x, (type)y) parse_options_start option__cmp BUG() BUG_ON(1) OPT_BOOLEAN(s,l,v,h) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h) } rest ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) USAGE_OPTS_WIDTH 24 OPTION_BIT parse_options_end option__in_argv PARSE_OPT_STOP_AT_NON_OPTION __round_mask(x,y) ((__typeof__(x))((y)-1)) set_option_flag parse_long_opt bswap_16(x) __bswap_16 (x) be32_to_cpu bswap_32 OPT_STRING_OPTARG(s,l,v,a,h,d) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh =(a), .help = (h), .flags = PARSE_OPT_OPTARG, .defval = (intptr_t)(d) } BUILD_BUG_ON_MSG(cond,msg) compiletime_assert(!(cond), msg) OPT_CALLBACK(s,l,v,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f) } usage_with_options_msg max_t(type,x,y) max((type)x, (type)y) parse_opt_ctx_t USAGE_GAP 2 cpu_to_le64 OPT__QUIET(var) OPT_BOOLEAN('q', "quiet", (var), "be quiet") ASSERT_STRUCT_OFFSET(type,field,expected_offset) BUILD_BUG_ON_MSG(offsetof(type, field) != (expected_offset), "Offset of " #field " in " #type " has changed.") PARSE_OPT_HIDDEN clamp(val,lo,hi) min((typeof(val))max(val, lo), hi) tolower_l(c,locale) __tolower_l ((c), (locale)) container_of(ptr,type,member) ({ const typeof(((type *)0)->member) * __mptr = (ptr); (type *)((char *)__mptr - offsetof(type, member)); }) synchronize_rcu() opterror OPTION_STRING OPT_STRING_OPTARG_SET(s,l,v,os,a,h,d) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h), .flags = PARSE_OPT_OPTARG, .defval = (intptr_t)(d), .set = check_vtype(os, bool *)} parse_opt_cb static_assert _Static_assert OPT_UINTEGER_OPTARG(s,l,v,d,h) { .type = OPTION_UINTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h), .flags = PARSE_OPT_OPTARG, .defval = (intptr_t)(d) } OPTION_END min(x,y) ({ typeof(x) _min1 = (x); typeof(y) _min2 = (y); (void) (&_min1 == &_min2); _min1 < _min2 ? _min1 : _min2; }) parse_options_subcommand OPT_SET_UINT(s,l,v,h,i) { .type = OPTION_SET_UINT, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h), .defval = (i) } PARSE_OPT_HELP OPT_LONG(s,l,v,h) { .type = OPTION_LONG, .short_name = (s), .long_name = (l), .value = check_vtype(v, long *), .help = (h) } OPT_CALLBACK_DEFAULT(s,l,v,a,h,f,d) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .defval = (intptr_t)d, .flags = PARSE_OPT_LASTARG_DEFAULT } BUILD_BUG_ON_NOT_POWER_OF_2(n) BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0)) __isoc23_strtoull parse_options_step parse_opt_option_flags BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); }))) longopt full __toupper_l(c,locale) __tobody (c, __toupper_l, (locale)->__ctype_toupper, (c, locale)) OPTION_CALLBACK nr_group reason build_opt nr_parent PARSE_OPT_DONE callback ordered OPT_GROUP(h) { .type = OPTION_GROUP, .help = (h) } OPT_BOOLEAN_FLAG(s,l,v,h,f) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h), .flags = (f) } OPTION_LONG OPT_UINTEGER(s,l,v,h) { .type = OPTION_UINTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h) } parse_options parse_opt_verbosity_cb DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) OPTION_ULONG OPT_CALLBACK_SET(s,l,v,os,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .set = check_vtype(os, bool *)} fputc intptr_t OPTION_U64 tolower(c) __tobody (c, tolower, *__ctype_tolower_loc (), (c)) excl_short_opt cpidx cpu_to_be32 bswap_32 round_up(x,y) ((((x)-1) | __round_mask(x, y))+1) nr_opts OPT_SET_PTR(s,l,v,h,p) { .type = OPTION_SET_PTR, .short_name = (s), .long_name = (l), .value = (v), .help = (h), .defval = (p) } abbrev_flags _RET_IP_ ((unsigned long)__builtin_return_address(0)) OPT_CALLBACK_NOOPT(s,l,v,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .flags = PARSE_OPT_NOARG } short_name OPT_INTEGER(s,l,v,h) { .type = OPTION_INTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h) } cpu_to_be16 bswap_16 current_gfp_context(k) 0 OPT_SHORT 1 argh __int32_t unset PARSE_OPT_CANSKIP _TOOLS_LINUX_PANIC_H OPT_STRING_NOEMPTY(s,l,v,a,h) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h), .flags = PARSE_OPT_NOEMPTY} print_option_help parse_opt_flags skip_prefix retry target OPTION_UINTEGER le16_to_cpu bswap_32(x) __bswap_32 (x) OPT_BIT(s,l,v,h,b) { .type = OPTION_BIT, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h), .defval = (b) } find_option PARSE_OPT_LIST_OPTS OPT_U64(s,l,v,h) { .type = OPTION_U64, .short_name = (s), .long_name = (l), .value = check_vtype(v, u64 *), .help = (h) } set_option_nobuild le32_to_cpu OPT_INCR(s,l,v,h) { .type = OPTION_INCR, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h) } OPTION_INCR usagestr PERF_ALIGN(x,a) __PERF_ALIGN_MASK(x, (typeof(x))(a)-1) OPTION_ARGUMENT PARSE_OPT_UNKNOWN OPT__DRY_RUN(var) OPT_BOOLEAN('n', "dry-run", (var), "dry run") __ch __ctype_tolower_loc UINT_MAX (~0U) OPTION_SET_UINT OPT_PARENT(p) { .type = OPTION_END, .parent = (p) } OPT_END() { .type = OPTION_END } OPT_ARGUMENT(l,h) { .type = OPTION_ARGUMENT, .long_name = (l), .help = (h) } OPT__VERBOSE(var) OPT_BOOLEAN('v', "verbose", (var), "be verbose") noarg OPT__ABBREV(var) { OPTION_CALLBACK, 0, "abbrev", (var), "n", "use <n> digits to display SHA-1s", PARSE_OPT_OPTARG, &parse_opt_abbrev_cb, 0 } optstr get_value OPT_STRING(s,l,v,a,h) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h) } OPT_BOOLEAN_SET(s,l,v,os,h) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h), .set = check_vtype(os, bool *)} OPT_UNSET 2 PARSE_OPT_NO_INTERNAL_HELP __BUILD_BUG_ON_NOT_POWER_OF_2(n) BUILD_BUG_ON(((n) & ((n) - 1)) != 0) abbrev_option OPT_DATE(s,l,v,h) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = "time", .help = (h), .callback = parse_opt_approxidate_cb } vasprintf long_name OPTION_INTEGER BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed") O_DIRECT __O_DIRECT F_SEAL_WRITE 0x0008 __path WAIT_ANY (-1) AT_NO_AUTOMOUNT 0x800 waitpid RWH_WRITE_LIFE_MEDIUM 3 close_pair prepare_run_command_v_opt DN_CREATE 0x00000004 ERR_RUN_COMMAND_FORK putenv O_NOATIME __O_NOATIME STRERR_BUFSIZE 128 SPLICE_F_MOVE 1 RWH_WRITE_LIFE_NOT_SET 0 F_OFD_SETLK 37 WCOREFLAG __WCOREFLAG LOCK_READ 64 RWH_WRITE_LIFE_SHORT 2 SPLICE_F_MORE 4 dup_devnull MAX_HANDLE_SZ 128 ERR_RUN_COMMAND_WAITPID_SIGNAL DN_MODIFY 0x00000002 AT_STATX_FORCE_SYNC 0x2000 ERR_RUN_COMMAND_EXEC __open_2 RWF_WRITE_LIFE_NOT_SET RWH_WRITE_LIFE_NOT_SET FALLOC_FL_COLLAPSE_RANGE 0x08 F_SETPIPE_SZ 1031 W_STOPCODE(sig) __W_STOPCODE (sig) LOCK_WRITE 128 AT_STATX_SYNC_TYPE 0x6000 O_TMPFILE __O_TMPFILE __iovec_defined 1 __open_alias SYNC_FILE_RANGE_WAIT_BEFORE 1 run_command ERR_RUN_COMMAND_PIPE F_SEAL_SHRINK 0x0002 FALLOC_FL_KEEP_SIZE 0x01 __idtype_t_defined AT_RECURSIVE 0x8000 pipe F_GETLEASE 1025 SPLICE_F_GIFT 8 AT_STATX_DONT_SYNC 0x4000 F_SETSIG __F_SETSIG F_SET_FILE_RW_HINT 1038 FALLOC_FL_UNSHARE_RANGE 0x40 ERR_RUN_COMMAND_WAITPID_NOEXIT WAIT_MYPGRP 0 F_OFD_SETLKW 38 O_PATH __O_PATH LOCK_MAND 32 ERR_RUN_COMMAND_WAITPID DN_MULTISHOT 0x80000000 waiting need_in chdir F_SEAL_FUTURE_WRITE 0x0010 need_err DN_ACCESS 0x00000001 need_out DN_DELETE 0x00000008 AT_STATX_SYNC_AS_STAT 0x0000 F_SET_RW_HINT 1036 SYNC_FILE_RANGE_WAIT_AFTER 4 F_GET_SEALS 1034 __open_missing_mode __open_too_many_args DN_RENAME 0x00000010 check_if_command_finished AT_EMPTY_PATH 0x1000 RWH_WRITE_LIFE_LONG 4 LOCK_RW 192 F_GETSIG __F_GETSIG wait_or_whine fderr __oflag SYNC_FILE_RANGE_WRITE 2 fdout WCOREDUMP(status) __WCOREDUMP (status) __open64_2 F_SETOWN_EX __F_SETOWN_EX _SYS_WAIT_H 1 F_OFD_GETLK 36 ERR_RUN_COMMAND_WAITPID_WRONG_PID DN_ATTRIB 0x00000020 F_GET_RW_HINT 1035 F_SETLEASE 1024 F_ADD_SEALS 1033 _FALLOC_H_ F_SEAL_SEAL 0x0001 RWH_WRITE_LIFE_EXTREME 5 FALLOC_FL_ZERO_RANGE 0x10 F_SEAL_GROW 0x0004 FALLOC_FL_INSERT_RANGE 0x20 F_SEAL_EXEC 0x0020 FALLOC_FL_NO_HIDE_STALE 0x04 fdin RWH_WRITE_LIFE_NONE 1 unsetenv F_GET_FILE_RW_HINT 1037 F_NOTIFY 1026 FALLOC_FL_PUNCH_HOLE 0x02 AT_HANDLE_FID AT_REMOVEDIR F_GETPIPE_SZ 1032 W_EXITCODE(ret,sig) __W_EXITCODE (ret, sig) F_GETOWN_EX __F_GETOWN_EX SYNC_FILE_RANGE_WRITE_AND_WAIT (SYNC_FILE_RANGE_WRITE | SYNC_FILE_RANGE_WAIT_BEFORE | SYNC_FILE_RANGE_WAIT_AFTER) SPLICE_F_NONBLOCK 2 sigchain_push SIGCHAIN_MAX_SIGNALS 32 sigchain_signal __sighandler_t check_signum UNDEFINED "SUBCMD_HAS_NOT_BEEN_INITIALIZED" LL_DELTA (1 << 5) ET_CORE 4 EF_SPARCV9_MM 3 R_MIPS_CALL16 11 R_TILEGX_HW0 9 DT_PPC_NUM 2 AT_SYSINFO 32 EM_SLE9X 179 isascii(c) (((unsigned char)(c))<=0x7f) R_386_TLS_LDM_CALL 30 R_MN10300_NUM 35 R_TILEGX_IMM8_Y0_TLS_GD_ADD 115 EF_ARM_HASENTRY 0x02 R_METAG_LO16_GOTOFF 33 R_METAG_TLS_DTPOFF 58 R_SPARC_16 2 R_SH_CODE 30 DT_MIPS_RLD_MAP_REL 0x70000035 ELF_NOTE_OS_FREEBSD 3 _X 0x40 R_MICROBLAZE_TLS 22 MIPS_AFL_ASE_MASK 0x00001fff PF_IA_64_NORECOV 0x80000000 MIPS_AFL_EXT_XLR 1 R_68K_TLS_GD8 27 R_68K_32 1 R_TILEGX_TLS_TPOFF32 111 NT_GNU_PROPERTY_TYPE_0 5 R_AARCH64_P32_COPY 180 R_PPC64_JMP_SLOT R_PPC_JMP_SLOT R_PARISC_LTOFF_TP14WR 227 DT_PROCNUM DT_MIPS_NUM islower(c) ((__ismask(c)&(_L)) != 0) EF_ARM_VFP_FLOAT 0x400 R_TILEPRO_IMM8_Y1 20 R_IA64_DTPMOD64LSB 0xa7 R_X86_64_GOT32 3 R_PPC64_PLT16_HI R_PPC_PLT16_HI AT_EUID 12 AT_CLKTCK 17 GNU_PROPERTY_HIUSER 0xffffffff STT_NOTYPE 0 R_PPC_NONE 0 R_PPC_EMB_NADDR16_HI 104 R_SPARC_GOTDATA_OP_HIX22 82 R_386_GOTOFF 9 PPC64_OPT_MULTI_TOC 2 R_METAG_RELBRANCH 4 R_TILEGX_IMM16_X1_HW2_PCREL 55 SHT_HIUSER 0x8fffffff R_SPARC_GOTDATA_OP_LOX10 83 R_RISCV_RVC_JUMP 45 DT_GNU_LIBLISTSZ 0x6ffffdf7 DF_1_NODELETE 0x00000008 R_PPC64_GOT_TLSGD16_LO 80 R_386_GOT32 3 R_TILEPRO_TLS_TPOFF32 84 EM_ARC 45 R_TILEPRO_DEST_IMM8_X1 55 SHF_ARM_COMDEF 0x80000000 DT_AUDIT 0x6ffffefc DT_MIPS_INTERFACE 0x7000002a EM_NORC 218 EM_R32C 162 R_AARCH64_LDST16_ABS_LO12_NC 284 GNU_PROPERTY_X86_ISA_1_USED 0xc0010002 EF_MIPS_ABI_EABI32 0x00003000 EM_PDP10 64 MIPS_AFL_ASE_EVA 0x00000004 R_AARCH64_TLS_DTPREL 1029 EM_M16C 117 R_ARM_ME_TOO 128 DT_MIPS_TIME_STAMP 0x70000002 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC 546 NT_ARM_HW_BREAK 0x402 SHN_HIPROC 0xff1f R_METAG_HIADDR16 0 R_IA64_DTPREL64LSB 0xb7 R_TILEPRO_IMM16_X0_TLS_GD_HI 70 R_CKCORE_TLS_LE32 51 EF_CSKY_ABIV2 0X20000000 SHF_LINK_ORDER (1 << 7) R_MIPS16_TLS_DTPREL_HI16 108 R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 R_CKCORE_PCREL_IMM26BY2 19 EM_UNICORE 110 PN_XNUM 0xffff EM_SPARC32PLUS 18 R_390_JMP_SLOT 11 R_LARCH_TLS_IE_HI20 91 R_MIPS_HI16 5 R_PARISC_LORESERVE 128 R_ARC_S21H_PCREL_PLT 0x4D R_ARC_24 0x3 R_ARM_TLS_LE32 108 R_MIPS_26 4 R_PARISC_GNU_VTINHERIT 233 R_ARM_TLS_DTPOFF32 18 R_SPARC_HI22 9 EF_ARM_EABI_UNKNOWN 0x00000000 R_CKCORE_TLS_TPOFF32 58 R_LARCH_ADD6 105 R_OR1K_TLS_IE_HI16 28 ispunct(c) ((__ismask(c)&(_P)) != 0) R_CKCORE_GOTPC_HI16 26 R_BPF_64_64 1 R_PPC_SDAREL16 32 R_LARCH_SOP_PUSH_PLT_PCREL 29 DT_BIND_NOW 24 MIPS_AFL_ASE_DSP 0x00000001 R_SPARC_SIZE64 87 EM_INTELGT 205 R_TILEPRO_IMM16_X1_HI 28 R_68K_TLS_DTPMOD32 40 R_MN10300_TLS_LE 29 EM_ECOG16 176 R_AARCH64_RELATIVE 1027 R_IA64_DTPREL14 0xb1 R_BPF_64_32 10 DT_ENCODING 32 R_MIPS_CALL_HI16 30 SHT_REL 9 R_AARCH64_ABS32 258 R_ARM_THM_JUMP24 30 AT_UCACHEBSIZE 21 R_ARM_ALU_SB_G1_NC 72 R_IA64_SUB 0x85 EF_MIPS_MACH_IAMR2 0x00930000 EF_MIPS_MACH_3900 0x00810000 NT_PPC_SPE 0x101 R_PARISC_TPREL14R 158 R_PARISC_PCREL17R 11 R_ARC_SDA16_LD1 0x17 R_X86_64_GOTPC32 26 PT_PARISC_UNWIND 0x70000001 R_MICROMIPS_HIGHER 151 EM_68HC16 69 NT_PSINFO 13 R_PARISC_PLTOFF16DF 119 R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 EM_H8_300H 47 OHW_R8KPFETCH 0x2 R_ARM_ABS12 6 _GCC_MAX_ALIGN_T DF_1_GLOBAUDIT 0x01000000 R_386_TLS_LDO_32 32 R_PARISC_TPREL64 216 R_ARM_ALU_SB_G1 73 R_ARC_PLT32 0x34 R_ALPHA_REFQUAD 2 EM_KM32 210 R_MICROMIPS_HI0_LO16 157 EF_SPARCV9_TSO 0 AT_NOTELF 10 R_OR1K_TLS_GD_HI16 22 SHN_XINDEX 0xffff R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 R_METAG_TLS_GD 47 R_ALPHA_DTPREL64 33 EF_PPC_RELOCATABLE_LIB 0x00008000 R_M32R_RELA_GNU_VTENTRY 44 EI_ABIVERSION 8 R_PPC64_TPREL16_HIGHESTA 100 EM_ST9PLUS 67 toascii(c) (((unsigned char)(c))&0x7f) R_IA64_FPTR64LSB 0x47 LL_DELAY_LOAD (1 << 4) R_AARCH64_NONE 0 DT_PLTGOT 3 R_CKCORE_GLOB_DAT 11 R_AARCH64_MOVW_SABS_G1 271 R_IA64_PCREL64I 0x7b symbol_name R_X86_64_GOTTPOFF 22 R_SPARC_WDISP10 88 VER_DEF_CURRENT 1 MIPS_AFL_REG_32 0x01 R_IA64_LTOFF22 0x32 R_TILEPRO_IMM16_X1_TLS_GD_LO 69 R_TILEGX_IMM16_X1_HW0_GOT 65 R_ARM_RSBREL32 250 R_TILEGX_IMM16_X1_HW0 37 EF_MIPS_XGOT 8 R_PPC_GOT_DTPREL16_HI 93 R_PPC_ADDR16_LO 4 NT_VMCOREDD 0x700 NT_ARM_FPMR 0x40e R_M32R_NONE 0 R_ARM_THM_MOVT_BREL 88 R_MN10300_PCREL8 6 R_AARCH64_MOVW_GOTOFF_G3 306 R_PARISC_TLS_DTPOFF64 245 R_PPC64_TPREL16_LO_DS 96 R_MICROMIPS_GOT_HI16 148 ELF64_R_SYM(i) ((i) >> 32) DF_STATIC_TLS 0x00000010 R_SPARC_TLS_LDO_ADD 66 EF_ARM_EABI_VER1 0x01000000 EM_M32 1 R_RISCV_BRANCH 16 R_68K_GOT16O 11 MIPS_AFL_EXT_3900 10 NT_PPC_TM_CTAR 0x10d DF_1_EDITED 0x00200000 R_68K_PLT8 15 R_386_TLS_DESC_CALL 40 R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63 EM_XIMO16 170 R_PARISC_PCREL14DR 76 NT_ARM_PACG_KEYS 0x408 R_PARISC_SEGREL32 49 R_TILEGX_IMM16_X0_HW0_PCREL 50 DT_GNU_HASH 0x6ffffef5 R_TILEPRO_IMM16_X1_PCREL 32 PPC64_LOCAL_ENTRY_OFFSET(other) (((1 << (((other) & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT)) >> 2) << 2) NT_X86_XSTATE 0x202 R_PPC_EMB_RELST_HI 113 R_NDS32_32_RELA 20 ELFOSABI_NONE 0 R_LARCH_PCALA64_LO20 73 R_OR1K_TLS_TPOFF 32 DT_MIPS_OPTIONS 0x70000029 ELF64_ST_BIND(val) ELF32_ST_BIND (val) R_M32R_SDA16 10 R_TILEGX_HW3 12 R_ARC_S21W_PCREL 0xF R_AARCH64_TLSLE_LDST64_TPREL_LO12 558 R_PPC_RELATIVE 22 R_PARISC_DIR16F 85 R_PPC_GOT_TLSGD16_HA 82 R_MIPS_HIGHEST 29 R_PPC_GOT_TLSGD16 79 R_ALPHA_DTPMOD64 31 R_PPC_EMB_MRKREF 110 tolower(c) __tolower(c) SHT_PARISC_DOC 0x70000002 EF_ARM_NEW_ABI 0x80 R_NIOS2_TLS_DTPREL 34 R_AARCH64_TLSLE_ADD_TPREL_HI12 549 R_LARCH_JUMP_SLOT 5 EM_SE_C33 107 R_NIOS2_IMM6 7 DT_MIPS_DELTA_SYM 0x7000001d R_PPC64_PLT64 45 STT_OBJECT 1 R_68K_GOT32O 10 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 531 AT_L1I_CACHESIZE 40 SHF_ARM_ENTRYSECT 0x10000000 MIPS_AFL_FLAGS1_ODDSPREG 1 R_M32R_GOTPC_HI_SLO 60 GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS (1U << 0) R_BPF_NONE 0 SHF_PARISC_SHORT 0x20000000 R_PPC64_PLTREL64 46 R_RISCV_SET16 55 R_ARC_S25H_PCREL_PLT 0x3D ODK_HWOR 8 R_LARCH_B21 65 R_MICROBLAZE_NONE 0 SHT_GNU_ATTRIBUTES 0x6ffffff5 R_ARM_GOT_ABS 95 R_TILEGX_IMM16_X1_HW0_TLS_GD 79 EM_XCORE 203 R_RISCV_PLT32 59 R_PARISC_PLABEL14R 70 DT_FILTER 0x7fffffff R_NIOS2_CALL26 4 R_SPARC_TLS_LDM_HI22 60 R_ARC_S21H_PCREL 0xE R_TILEGX_NUM 130 EF_MIPS_ARCH_32R2 0x70000000 R_ARM_TLS_DTPMOD32 17 R_AARCH64_MOVW_PREL_G0_NC 288 EM_SE_C17 139 PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) R_X86_64_TLSGD 19 R_TILEPRO_IMM8_X1 19 R_PPC64_GOT_TLSGD16_HI 81 EM_AARCH64 183 R_TILEGX_DEST_IMM8_X1 27 R_LARCH_SOP_SL 33 R_IA64_SECREL32LSB 0x65 EF_SH3E 0x8 LL_EXPORTS (1 << 3) R_ARM_ALU_SB_G0_NC 70 R_PPC_REL14 11 DT_MIPS_ICHECKSUM 0x70000003 R_PPC_ADDR32 1 PT_GNU_RELRO 0x6474e552 R_IA64_FPTR64I 0x43 R_RISCV_TLS_DTPREL32 8 R_ARM_ABS32_NOI 55 R_RISCV_32 1 R_PPC64_DTPREL64 78 EM_SPARCV9 43 R_TILEPRO_IMM16_X1 24 EF_ARM_ALIGN8 0x40 DT_PPC64_OPT (DT_LOPROC + 3) VER_DEF_NONE 0 NT_PPC_DEXCR 0x111 R_ARM_THM_PC22 10 MIPS_AFL_ASE_XPA 0x00001000 DT_MIPS_NUM 0x37 NT_S390_VXRS_LOW 0x309 R_ARM_MOVW_ABS_NC 43 R_LARCH_SUB32 55 OEX_FPU_DIV0 0x08 R_M32R_26_PCREL 6 R_MIPS16_TLS_TPREL_LO16 112 NT_LOONGARCH_HW_WATCH 0xa06 __toupper OHW_R4KEOP 0x1 R_PARISC_LTOFF_TP16F 229 R_CRIS_16 2 R_SPARC_NUM 253 DT_SYMINENT 0x6ffffdff EF_MIPS_MACH_4100 0x00830000 EF_RISCV_FLOAT_ABI_SOFT 0x0000 R_X86_64_PC8 15 R_PARISC_GPREL21L 26 R_X86_64_TLSDESC 36 kallsyms__is_function OEX_FPU_MAX 0x1f00 R_MIPS16_PC16_S1 113 R_ARM_SWI24 13 R_MN10300_PCREL32 4 R_MIPS16_HI16 104 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 525 R_PPC64_REL32 R_PPC_REL32 DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 R_PPC_PLTREL32 28 R_PPC_REL14_BRNTAKEN 13 R_MICROBLAZE_TLSTPREL32 29 RHF_PIXIE (1 << 8) R_ARC_NONE 0x0 R_390_TLS_GOTIE12 42 DT_ALPHA_PLTRO (DT_LOPROC + 0) STT_PARISC_MILLICODE 13 R_MICROMIPS_TLS_TPREL_HI16 169 R_CKCORE_ADDR_LO16 25 EV_NONE 0 R_CKCORE_DOFFSET_IMM18 44 R_PARISC_TPREL21L 154 PF_HP_NEAR_SHARED 0x00400000 DT_MIPS_DELTA_CLASS_NO 0x70000018 R_MICROBLAZE_64_PCREL 3 kallsyms__parse ELFCOMPRESS_ZSTD 2 R_PPC64_DTPREL16_HIGHERA 104 EM_VPP500 17 _L 0x02 R_METAG_GETSET_GOT 35 R_PPC64_GOT16_LO_DS 59 STT_NUM 7 R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 98 EM_FT32 222 AT_L2_CACHESIZE 44 R_ARM_MOVW_PREL_NC 45 R_AARCH64_TLSLD_MOVW_DTPREL_G1 524 OEX_FPU_MIN 0x1f R_MICROMIPS_GOT_PAGE 146 R_MIPS_TLS_DTPREL64 41 R_AARCH64_LD64_GOTPAGE_LO15 313 R_PPC_REL14_BRTAKEN 12 R_CRIS_8 1 SHF_MIPS_ADDR 0x40000000 NT_ARM_SVE 0x405 R_IA64_TPREL64LSB 0x97 R_ARC_NPS_CMEM16 0x4E PF_PARISC_SBP 0x08000000 EM_OPEN8 196 R_IA64_PLTOFF22 0x3a EF_ARM_EABI_VER3 0x03000000 EF_SPARC_SUN_US1 0x000200 AT_HWCAP 16 R_TILEPRO_IMM16_X0_LO_PCREL 33 R_METAG_TLS_IENONPIC 53 STB_GLOBAL 1 R_PARISC_PCREL21L 10 ELFCOMPRESS_LOPROC 0x70000000 R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 543 R_390_GOTPLT16 30 R_IA64_PCREL21B 0x49 SHF_OS_NONCONFORMING (1 << 8) AT_FPUCW 18 DT_MIPS_DELTA_CLASSSYM 0x70000020 R_PPC64_ADDR16_LO_DS 57 R_TILEPRO_TLS_GD_CALL 60 R_CRIS_16_GOT 13 R_390_GOT64 24 NT_ARM_HW_WATCH 0x403 R_ARM_ALU_PC_G1 60 R_AC_SECTOFF_U8_2 0x25 R_IA64_LTOFF_FPTR64LSB 0x57 R_MIPS_PJUMP 35 R_TILEGX_COPY 16 NT_GWINDOWS 7 SHT_LOPROC 0x70000000 EM_MAX 102 R_PPC64_REL14 R_PPC_REL14 R_SPARC_PLT64 47 R_AARCH64_CONDBR19 280 R_TILEPRO_MMEND_X0 48 R_MICROBLAZE_JUMP_SLOT 17 R_RISCV_CALL_PLT 19 R_ARC_TLS_GD_GOT 0x45 R_ARM_BASE_ABS 31 R_LARCH_GOT64_PC_LO20 77 ELFOSABI_GNU 3 R_ARM_THM_MOVW_ABS_NC 47 STT_SECTION 3 R_X86_64_GOTPLT64 30 R_SH_DATA 31 R_68K_8 3 MIPS_AFL_EXT_4650 7 SHT_ALPHA_DEBUG 0x70000001 RHF_GUARANTEE_INIT (1 << 5) R_TILEGX_32_PCREL 6 R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 539 EF_MIPS_ARCH_ASE_M16 0x04000000 R_ARM_TARGET1 38 DT_VALRNGHI 0x6ffffdff SHT_SHLIB 10 EM_88K 5 R_M32R_GOTPC_LO 61 R_ARM_ALU_PCREL_15_8 33 DF_1_SINGLETON 0x02000000 R_PPC_TPREL16 69 R_OR1K_TLS_DTPMOD 34 EM_OPENRISC 92 NT_PRXFPREG 0x46e62b7f R_CKCORE_TLS_GD32 53 R_M32R_24 3 NT_PPC_PMU 0x107 R_X86_64_NUM 43 MIPS_AFL_ASE_MIPS3D 0x00000020 NT_X86_SHSTK 0x204 R_TILEPRO_IMM16_X1_TLS_GD 67 R_PPC_DTPREL16_HA 77 R_CKCORE_TLS_DTPMOD32 56 R_CKCORE_PCREL32 5 R_68K_TLS_LE8 39 R_68K_RELATIVE 22 R_ARM_XPC25 15 R_PPC64_TPREL16_LO 70 R_ARM_AMP_VCALL9 12 R_PPC64_DTPREL16_HA 77 R_MIPS_PC16 10 EF_SH2 0x2 R_SH_TLS_DTPMOD32 149 R_CKCORE_TLS_LDM32 54 SHT_X86_64_UNWIND 0x70000001 R_PPC_GOT16 14 R_LARCH_SUB8 52 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 536 R_PARISC_LTOFF16F 101 DT_PREINIT_ARRAYSZ 33 R_TILEPRO_IMM16_X1_TLS_IE 75 R_ALPHA_SREL64 11 EM_CLOUDSHIELD 192 R_METAG_GLOB_DAT 46 R_M32R_GOTOFF_HI_SLO 63 SHF_STRINGS (1 << 5) R_MIPS16_CALL16 103 R_68K_GOT8O 12 R_386_TLS_TPOFF 14 AT_L1I_CACHESHAPE 34 R_TILEPRO_IMM16_X1_GOT 40 MIPS_AFL_EXT_SB1 12 R_ARC_COPY 0x35 R_NIOS2_GOTOFF_HA 25 R_ARM_THM_GOT_BREL12 131 EM_VAX 75 SHT_GNU_verneed 0x6ffffffe R_MICROBLAZE_GOT_64 14 R_PPC64_TPREL16_HIGHER 97 R_PARISC_GPREL64 88 R_PPC64_TPREL16_HIGHERA 98 R_AC_SECTOFF_S9_2 0x28 DF_P1_GROUPPERM 0x00000002 R_LARCH_64_PCREL 109 R_TILEGX_JMP_SLOT 18 SHT_MIPS_DWARF 0x7000001e SHT_GNU_LIBLIST 0x6ffffff7 R_ARM_LDC_SB_G1 82 R_MIPS_GNU_VTINHERIT 253 R_TILEGX_IMM16_X0_HW0_PLT_PCREL 66 R_LARCH_TLS_GD_PC_HI20 97 R_TILEGX_IMM8_Y1_TLS_GD_ADD 116 EM_VIDEOCORE 95 R_PPC64_ADDR16_HIGHER 39 R_CRIS_RELATIVE 12 STT_FILE 4 R_MN10300_TLS_TPOFF 32 R_ARM_ALU_PCREL_23_15 34 NT_S390_TIMER 0x301 R_TILEGX_HW1_LAST 14 NT_VERSION 1 R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45 R_PARISC_EPLT 130 PT_HP_CORE_KERNEL (PT_LOOS + 0x3) R_PPC_DIAB_RELSDA_LO 183 R_68K_PC8 6 R_PPC64_TOC16_LO_DS 64 EF_SH2A_SH4_NOFPU 0x15 R_AARCH64_TLSLE_MOVW_TPREL_G1 545 R_TILEPRO_RELATIVE 13 R_390_TLS_TPOFF 56 R_MICROBLAZE_64 5 SHT_MIPS_LOCSTR 0x70000018 R_ARC_H30_ME 0x20 R_PARISC_DPREL21L 18 STN_UNDEF 0 R_ARM_CALL 28 ELF64_ST_INFO(bind,type) ELF32_ST_INFO ((bind), (type)) _LINUX_CTYPE_H PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 2) R_ARC_SDA32 0x12 R_LARCH_ABS64_HI12 70 EF_SH2A 0xd R_METAG_TLS_IENONPIC_LO16 55 R_PPC_DTPREL16 74 EF_ARM_EABI_VER5 0x05000000 R_PPC_REL16_HA 252 R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 542 EI_MAG3 3 R_LARCH_GOT_PC_LO12 76 R_RISCV_RELAX 51 R_IA64_DTPREL64I 0xb3 SHN_UNDEF 0 STT_COMMON 5 R_68K_PC32 4 EM_56800EX 200 R_PPC64_GOT_TPREL16_HA 90 EF_MIPS_MACH_OCTEON 0x008b0000 EF_CSKY_OTHER 0X0FFF0000 NT_PRPSINFO 3 R_TILEGX_IMM16_X1_HW0_PLT_PCREL 67 R_PPC_GOT_TLSLD16_HA 86 R_PPC_TLSGD 95 EM_68HC05 72 SHT_MIPS_PACKAGE 0x70000007 R_AARCH64_PREL16 262 R_CKCORE_ADDRPLT_LO16 39 EF_MIPS_MACH_SB1 0x008a0000 R_68K_TLS_LDO16 32 PT_HP_HSL_ANNOT (PT_LOOS + 0x13) EM_MAXQ30 169 R_METAG_LO16_GOTPC 37 GNU_PROPERTY_HIPROC 0xdfffffff R_AARCH64_MOVW_PREL_G0 287 R_PARISC_LTOFF14DR 100 R_CKCORE_PCRELJSR_IMM11BY2 6 GNU_PROPERTY_X86_ISA_1_V3 (1U << 2) DT_PLTREL 20 R_PARISC_PLTOFF16F 117 R_LARCH_32 1 PPC_OPT_TLS 1 R_MICROMIPS_CALL_LO16 154 R_MN10300_ALIGN 34 R_LARCH_TLS_DTPREL64 9 EM_NUM 259 MIPS_AFL_ASE_VIRT 0x00000100 R_ARM_JUMP_SLOT 22 R_PPC_EMB_NADDR16_LO 103 EM_SNP1K 99 NT_ARM_PACA_KEYS 0x407 DT_MIPS_SYMTABNO 0x70000011 EF_PPC64_ABI 3 LL_EXACT_MATCH (1 << 0) EF_MIPS_ABI_ON32 64 EM_RX 173 R_LARCH_ADD_ULEB128 107 EF_PARISC_TRAPNIL 0x00010000 R_IA64_PLTOFF64LSB 0x3f R_X86_64_SIZE64 33 R_390_GOT20 58 RHF_NOTPOT (1 << 1) R_PPC64_TOC16_LO 48 R_AARCH64_MOVW_UABS_G2_NC 268 R_LARCH_CFA 104 R_CKCORE_PCRELIMM8BY4 2 R_MIPS_SHIFT5 16 R_AARCH64_PREL32 261 R_RISCV_64 2 DF_1_NORELOC 0x00400000 R_CKCORE_ADDRPLT 18 R_SPARC_WDISP22 8 SHT_INIT_ARRAY 14 EF_ARM_DYNSYMSUSESEGIDX 0x08 R_PPC_TLS 67 R_CKCORE_PCREL_IMM16BY4 21 EF_MIPS_FP64 512 R_SPARC_PC22 17 R_ALPHA_NONE 0 AT_MINSIGSTKSZ 51 R_TILEPRO_8 3 R_PPC_GOT_DTPREL16 91 R_ALPHA_GOTTPREL 37 R_ARC_GOTPC32 0x33 DT_GNU_PRELINKED 0x6ffffdf5 R_AARCH64_MOVW_GOTOFF_G1_NC 303 DF_SYMBOLIC 0x00000002 EF_LARCH_ABI_SOFT_FLOAT 0x01 R_ARM_LDR_SB_G2 77 R_NIOS2_TLS_LDM16 29 R_PARISC_LTOFF_TP21L 162 ODK_NULL 0 R_SPARC_GOTDATA_OP 84 R_NIOS2_GOT_LO 42 DT_MIPS_RLD_VERSION 0x70000001 R_PPC64_TPREL16_HIGH 112 DT_FINI_ARRAY 26 R_MN10300_GOTOFF32 12 R_OR1K_32_PCREL 9 SHT_MIPS_DENSE 0x70000013 PT_HIPROC 0x7fffffff R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 527 EI_NIDENT (16) ODK_HWPATCH 4 SHT_MIPS_PDR_EXCEPTION 0x70000029 EF_RISCV_RVC 0x0001 R_IA64_SECREL64MSB 0x66 R_MIPS_LO16 6 R_AARCH64_LD64_GOT_LO12_NC 312 SHN_BEFORE 0xff00 EM_ARM 40 R_X86_64_DTPOFF64 17 R_M32R_COPY 50 R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 ELFMAG "\177ELF" SHT_IA_64_EXT (SHT_LOPROC + 0) R_TILEGX_HW2_LAST 15 DF_1_NOW 0x00000001 R_RISCV_ADD16 34 R_ARM_TARGET2 41 R_PPC64_TOCSAVE 109 R_SPARC_L44 52 EM_METAG 174 R_MIPS_TLS_DTPREL32 39 LL_NONE 0 R_RISCV_SUB32 39 PT_GNU_EH_FRAME 0x6474e550 R_ARM_TLS_IE32 107 NT_ARM_ZT 0x40d RHF_NO_LIBRARY_REPLACEMENT (1 << 2) EF_PARISC_LSB 0x00040000 R_ALPHA_DTPRELLO 35 EF_MIPS_MACH_LS2F 0x00A10000 DT_PLTPAD 0x6ffffefd R_68K_NONE 0 R_X86_64_TLSDESC_CALL 35 R_IA64_PCREL64MSB 0x4e R_MICROBLAZE_GOTPC_64 13 DT_VALNUM 12 R_MN10300_TLS_GOTIE 27 EM_ARC_A5 EM_ARC_COMPACT R_SPARC_PLT32 24 R_IA64_REL64MSB 0x6e R_METAG_JMP_SLOT 44 R_LARCH_TLS_DTPMOD32 6 R_LARCH_ADD16 48 R_PPC64_TPREL16_HI 71 R_PPC64_ADDR30 37 EM_CRX 114 VER_FLG_BASE 0x1 R_PPC_TPREL16_LO 70 R_SPARC_TLS_LDM_LO10 61 DT_CONFIG 0x6ffffefa PF_HP_SBP 0x08000000 DF_1_IGNMULDEF 0x00040000 SHT_MIPS_CONFLICT 0x70000002 R_AARCH64_P32_TLS_DTPREL 185 R_ARM_THM_TLS_CALL 93 R_M32R_GOTPC24 55 R_TILEGX_IMM16_X1_HW3 43 R_TILEGX_IMM8_X1 25 R_TILEPRO_IMM16_X1_GOT_LO 42 R_68K_GOT8 9 DF_1_NODIRECT 0x00020000 EM_STM8 186 R_ARC_N24 0xA R_IA64_SEGREL64LSB 0x5f R_RISCV_SET6 53 R_ALPHA_GPRELHIGH 17 EM_FX66 66 NT_PPC_PPR 0x104 R_TILEPRO_IMM8_X1_TLS_GD_ADD 62 STO_MIPS_DEFAULT 0x0 R_TILEPRO_32_PCREL 4 R_PPC64_SECTOFF_DS 61 R_IA64_LTOFF_TPREL22 0x9a R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 R_TILEGX_IMM16_X0_HW2 40 EF_SH4_NOFPU 0x10 NT_S390_PV_CPU_DATA 0x30e R_SPARC_UA64 54 SHF_EXECINSTR (1 << 2) R_LARCH_TLS_IE64_LO20 93 OEX_FPU_INVAL 0x10 R_MIPS_COPY 126 R_TILEPRO_JOFFLONG_X1_PLT 16 R_ARC_TLS_DTPOFF_S9 0x49 R_390_PLTOFF64 36 R_PPC_DIAB_RELSDA_HA 185 EF_SPARCV9_RMO 2 NT_386_IOPERM 0x201 EF_PPC_EMB 0x80000000 DT_RELA 7 MIPS_AFL_ASE_MSA 0x00000200 R_LARCH_GOT_LO12 80 R_X86_64_PC32 2 DT_NUM 38 R_TILEGX_IMM16_X1_HW1_LAST 47 R_TILEPRO_IMM16_X1_LO 26 SYMINFO_FLG_DIRECT 0x0001 EF_SPARCV9_PSO 1 R_MICROBLAZE_64_NONE 9 R_RISCV_LO12_I 27 SHT_GNU_versym 0x6fffffff R_TILEPRO_IMM16_X0_GOT_HA 45 DT_MIPS_DELTA_INSTANCE_NO 0x7000001a R_390_12 2 MIPS_AFL_REG_64 0x02 R_MIPS_GPREL16 7 EM_AMDGPU 224 R_CKCORE_PCREL_JSR_IMM26BY2 40 R_M32R_GOT16_HI_ULO 56 DT_VERSYM 0x6ffffff0 R_ARM_ABS16 5 R_386_TLS_TPOFF32 37 R_X86_64_COPY 5 EF_RISCV_FLOAT_ABI 0x0006 R_PPC_EMB_RELSEC16 111 R_MIPS_GLOB_DAT 51 R_PPC64_GOT16 R_PPC_GOT16 DT_TLSDESC_GOT 0x6ffffef7 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 534 R_CKCORE_GOTOFF_HI16 28 R_X86_64_PLTOFF64 31 R_ARM_LDC_PC_G1 68 R_SH_NONE 0 R_METAG_GNU_VTENTRY 31 PF_HP_PAGE_SIZE 0x00100000 R_390_GOTPLT12 29 R_PPC_GOT_TPREL16_LO 88 R_ALPHA_SREL16 9 R_TILEPRO_32 1 R_ARC_SECTOFF_ME_1 0x29 EM_MICROBLAZE 189 ODK_TAGS 6 EF_ARM_MAPSYMSFIRST 0x10 DT_RELAENT 9 R_CKCORE_GOT32 15 R_PPC_REL24 10 DT_AARCH64_PAC_PLT (DT_LOPROC + 3) R_PPC_EMB_SDA21 109 R_LARCH_NONE 0 EM_TMM_GPP 96 R_TILEGX_TLS_TPOFF64 108 R_MN10300_PLT16 16 R_PPC64_DTPREL16_HIGHESTA 106 EM_SPU 23 R_ARM_LDC_PC_G2 69 __TOOLS_KALLSYMS_H_ 1 R_CKCORE_PLT_IMM18BY4 49 R_68K_GOT16 8 EM_IP2K 101 EM_CDP 215 AT_NULL 0 R_ARC_SECTOFF_1 0x2B EI_VERSION 6 R_PPC_GLOB_DAT 20 R_METAG_REG16OP1 9 R_TILEPRO_IMM16_X1_LO_PCREL 34 R_ARC_TLS_GD_CALL 0x47 EF_MIPS_ABI_EABI64 0x00004000 R_RISCV_RELATIVE 3 R_PPC64_REL24 R_PPC_REL24 R_ALPHA_SREL32 10 R_TILEGX_IMM16_X1_HW0_LAST 45 R_AARCH64_TLSLD_ADD_LO12_NC 519 R_PPC64_GOT_TPREL16_HI 89 R_ARM_THM_MOVT_ABS 48 R_ARM_TLS_DESCSEQ 92 EF_MIPS_CPIC 4 R_CKCORE_DOFFSET_LO16 42 R_AC_SECTOFF_U8_1 0x24 R_TILEPRO_JOFFLONG_X1 15 AT_HWCAP2 26 R_TILEGX_NONE 0 EM_ST19 74 R_TILEPRO_IMM16_X0_GOT 39 R_LARCH_TLS_DESC_PC_HI20 111 R_RISCV_JUMP_SLOT 5 R_CRIS_COPY 9 R_390_TLS_DTPMOD 54 R_ARM_THM_ALU_PREL_11_0 53 R_MICROMIPS_LO16 135 R_MIPS_GOT_LO16 23 NT_S390_SYSTEM_CALL 0x307 R_PPC64_ADDR16_DS 56 STV_HIDDEN 2 EM_NCPU 56 R_PARISC_IPLT 129 R_TILEGX_GNU_VTENTRY 129 R_TILEPRO_GNU_VTENTRY 129 R_PARISC_TLS_LDM14R 238 R_PPC64_REL16 249 R_386_TLS_DESC 41 ELFOSABI_AIX 7 R_LARCH_TLS_DESC_LO12 116 R_PPC64_TOC16_HI 49 R_IA64_REL32LSB 0x6d NT_SIGINFO 0x53494749 SHF_ALLOC (1 << 1) R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC 573 R_LARCH_ADD32 50 SHT_MIPS_EXTSYM 0x70000012 R_ARC_S25W_PCREL 0x11 R_SH_IND12W 4 R_MN10300_GNU_VTINHERIT 7 R_AARCH64_TLSLE_LDST16_TPREL_LO12 554 R_ARM_MOVT_PREL 46 R_X86_64_DTPMOD64 16 R_TILEGX_IMM16_X0_HW0_TLS_GD 78 PT_GNU_PROPERTY 0x6474e553 R_CKCORE_PCREL_IMM10BY2 22 PT_SHLIB 5 KSYM_NAME_LEN 512 NT_PPC_EBB 0x106 R_AARCH64_TLSLD_MOVW_DTPREL_G2 523 R_MIPS_TLS_GOTTPREL 46 R_LARCH_TLS_IE64_PC_HI12 90 R_ARC_GOTOFF 0x39 R_AC_SECTOFF_U8 0x23 R_ARM_GOTOFF12 98 R_LARCH_SOP_ASSERT 30 EM_C166 116 MIPS_AFL_EXT_10000 11 R_PPC64_ADDR14 R_PPC_ADDR14 R_PARISC_TLS_GDCALL 236 R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO R_OR1K_NONE 0 EM_PDSP 63 R_TILEGX_IMM16_X0_HW1_PLT_PCREL 68 R_SH_SWITCH8 33 EF_MIPS_MACH 0x00FF0000 R_TILEPRO_SHAMT_X0 51 R_TILEPRO_IMM16_X0_TLS_GD_HA 72 NT_FILE 0x46494c45 SHF_EXCLUDE (1U << 31) R_390_20 57 R_MN10300_GOTPC32 10 R_CKCORE_ADDRGOT_LO16 37 isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) R_RISCV_COPY 4 NT_PLATFORM 5 R_68K_TLS_LDM8 30 R_METAG_TLS_IENONPIC_HI16 54 R_68K_TLS_LE32 37 R_ARM_LDR_PC_G2 63 SHF_ORDERED (1 << 30) R_CKCORE_TLS_IE32 52 EM_ALPHA 0x9026 R_CKCORE_JUMP_SLOT 12 R_ARM_THM_TLS_DESCSEQ16 129 R_TILEPRO_16_PCREL 5 R_ARC_TLS_DTPOFF 0x43 R_AC_SECTOFF_S9_1 0x27 R_MICROMIPS_TLS_GOTTPREL 166 R_AARCH64_GOTREL64 307 STO_PPC64_LOCAL_BIT 5 OEX_FPU_OFLO 0x04 __ismask(x) (_ctype[(int)(unsigned char)(x)]) R_ARM_THM_MOVW_BREL 89 R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ELFDATANUM 3 R_PPC64_TOC16 47 R_PPC64_PLTREL32 R_PPC_PLTREL32 EF_MIPS_ARCH_5 0x40000000 DT_FLAGS_1 0x6ffffffb DT_REL 17 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 553 R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 R_MN10300_GOT16 19 R_ARC_JMP_SLOT 0x37 R_IA64_DTPMOD64MSB 0xa6 R_PARISC_TPREL32 153 R_TILEPRO_HA16 9 R_X86_64_PLT32 4 GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1) R_LARCH_TLS_LE64_LO20 85 DF_1_SYMINTPOSE 0x00800000 R_ALPHA_NUM 46 R_PPC64_ADDR16_HIGH 110 R_ARM_GOTOFF 24 R_NDS32_GLOB_DAT 40 DT_MIPS_INTERFACE_SIZE 0x7000002c R_PARISC_DIR32 1 EF_MIPS_ARCH_ASE_MDMX 0x08000000 RHF_DEFAULT_DELAY_LOAD (1 << 9) R_MIPS_PC32 248 STB_WEAK 2 R_AARCH64_TLS_DTPMOD 1028 R_LARCH_TLS_DESC64_PC_LO20 113 io__get_hex PF_MASKPROC 0xf0000000 SHT_RELA 4 R_ARM_THM_TLS_DESCSEQ32 130 EF_RISCV_RVE 0x0008 R_OR1K_GOT16 14 SHT_MIPS_FDESC 0x70000011 R_TILEPRO_IMM16_X1_HI_PCREL 36 DT_VALRNGLO 0x6ffffd00 DT_ALPHA_NUM 1 R_SPARC_TLS_IE_LDX 70 PF_ARM_ABS 0x40000000 EM_8051 165 EM_VIDEOCORE3 137 SHT_FINI_ARRAY 15 R_OR1K_LO_16_IN_INSN 4 OPAD_PREFIX 0x1 R_NIOS2_CALL_HA 45 R_SPARC_REGISTER 53 NT_FDO_PACKAGING_METADATA 0xcafe1a7e R_ARM_RREL32 252 R_IA64_DTPREL64MSB 0xb6 R_AARCH64_TSTBR14 279 R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 R_IA64_DIR64LSB 0x27 R_PPC64_PLTGOT16_LO 53 EF_SH3 0x3 DT_RELRENT 37 R_ARM_MOVW_BREL_NC 84 R_390_PC32 5 EF_MIPS_MACH_5500 0x00980000 R_MICROBLAZE_TLSDTPREL64 27 R_SPARC_UA32 23 SHT_SYMTAB_SHNDX 18 SHT_MIPS_PIXIE 0x70000023 DT_NIOS2_GP 0x70000002 R_CKCORE_DOFFSET_IMM18BY2 45 R_AARCH64_TLSLE_MOVW_TPREL_G2 544 R_TILEGX_IMM16_X0_HW3_PLT_PCREL 76 R_SPARC_JMP_SLOT 21 R_MN10300_24 9 DF_ORIGIN 0x00000001 R_PPC64_TPREL64 73 NT_PPC_TM_CVSX 0x10b R_390_COPY 9 R_LARCH_TLS_LE_LO12 84 PT_INTERP 3 R_PPC_EMB_NADDR16 102 R_SPARC_IRELATIVE 249 R_PARISC_GPREL16F 93 R_SPARC_TLS_TPOFF64 79 R_MICROMIPS_TLS_DTPREL_LO16 165 EM_D10V 85 R_LARCH_SOP_POP_32_S_10_16 41 EF_CSKY_PROCESSOR 0X0000FFFF R_LARCH_SUB16 53 R_RISCV_ADD8 33 R_RISCV_TPREL_I 49 R_MIPS_16 1 STB_MIPS_SPLIT_COMMON 13 EF_PARISC_EXT 0x00020000 R_SH_ALIGN 29 R_IA64_PCREL60B 0x48 R_M32R_GNU_VTENTRY 12 R_X86_64_DTPOFF32 21 R_ARM_LDR_SBREL_11_0 35 R_AARCH64_TLSDESC_ADR_PAGE21 562 R_PPC_GOT_TPREL16_HI 89 R_386_TLS_LE 17 NT_ARM_TAGGED_ADDR_CTRL 0x409 DT_INIT_ARRAY 25 EF_MIPS_ARCH_ASE 0x0f000000 NT_PRSTATUS 1 R_M32R_GOT16_LO 58 PT_HP_TLS (PT_LOOS + 0x0) R_386_TLS_GD_32 24 DT_RELR 36 R_390_GOTOFF64 28 R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L R_ARM_IRELATIVE 160 R_PARISC_LTOFF_FPTR32 57 R_PPC_PLT32 27 R_PPC_TPREL16_HI 71 R_MIPS_TLS_DTPREL_LO16 45 R_NIOS2_TLS_LE16 32 R_TILEPRO_IMM16_X0_LO 25 R_TILEPRO_IMM16_X0_TLS_LE 85 R_ARC_TLS_LE_32 0x4B MIPS_AFL_EXT_5900 6 R_M32R_JMP_SLOT 52 R_PARISC_LTOFF_TP16WF 230 R_ALPHA_TLS_LDM 30 R_LARCH_B16 64 OEX_PAGE0 0x10000 EM_PPC64 21 R_390_GOTPCDBL 21 ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) VER_DEF_NUM 2 R_MIPS_HIGHER 28 R_ARM_THM_RPC22 251 R_68K_GLOB_DAT 20 R_MICROMIPS_PC23_S2 173 R_PPC_EMB_RELSDA 116 R_SPARC_TLS_GD_CALL 59 R_386_GOTPC 10 R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC 571 STB_LOOS 10 R_SPARC_GOT22 15 R_390_TLS_GD32 40 iscntrl(c) ((__ismask(c)&(_C)) != 0) R_SH_TLS_DTPOFF32 150 R_ARC_S25H_PCREL 0x10 R_LARCH_SUB24 54 R_X86_64_GOTOFF64 25 NT_ASRS 8 SHT_MIPS_DEBUG 0x70000005 R_LARCH_TLS_LE_HI20_R 121 R_M32R_HI16_SLO 8 EM_CUDA 190 PF_X (1 << 0) R_IA64_FPTR64MSB 0x46 R_ARM_ALU_SB_G0 71 R_LARCH_PCALA64_HI12 74 LITUSE_ALPHA_BASE 1 R_TILEGX_GNU_VTINHERIT 128 MIPS_AFL_EXT_5400 15 R_RISCV_RVC_BRANCH 44 R_LARCH_TLS_LD_PC_HI20 95 SHT_MIPS_PDESC 0x70000014 R_MIPS_TLS_TPREL64 48 EM_TRIMEDIA 163 R_TILEGX_IMM8_X1_TLS_ADD 119 R_SH_DIR8WPZ 6 NT_PPC_VMX 0x100 STO_ALPHA_NOPV 0x80 R_MICROMIPS_HIGHEST 152 EF_SH2A_SH3E 0x18 R_386_TLS_LDM_PUSH 29 DT_HIPROC 0x7fffffff SHT_MIPS_LINE 0x70000019 R_ARM_TLS_LDO12 109 NT_S390_TDB 0x308 EM_ST7 68 R_RISCV_JAL 17 EM_68HC08 71 ELFDATA2LSB 1 R_ARC_TLS_DTPMOD 0x42 R_LARCH_TLS_TPREL64 11 DT_SPARC_REGISTER 0x70000001 R_M32R_10_PCREL_RELA 36 R_PPC_ADDR14_BRNTAKEN 9 R_AARCH64_MOVW_PREL_G1 289 R_NIOS2_CALL16 23 R_390_NONE 0 MIPS_AFL_EXT_4010 8 R_IA64_DTPREL32LSB 0xb5 R_RISCV_GPREL_I 47 R_PPC64_GOT_TLSGD16_HA 82 R_MIPS_REL16 33 R_RISCV_GNU_VTINHERIT 41 E_MIPS_ARCH_1 EF_MIPS_ARCH_1 R_CRIS_GLOB_DAT 10 R_68K_NUM 43 R_CKCORE_PLT_HI16 34 R_ARM_PREL31 42 SHF_GNU_RETAIN (1 << 21) R_LARCH_TLS_IE_PC_LO12 88 R_PARISC_PLABEL32 65 R_ARC_GOTPC 0x3A R_MICROBLAZE_32_SYM_OP_SYM 10 NT_ARM_SSVE 0x40b EM_ZSP 79 R_RISCV_TLS_DTPREL64 9 R_NIOS2_ALIGN 21 R_SH_SWITCH16 25 R_SPARC_22 10 R_390_PLTOFF32 35 R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 R_ARC_TLS_TPOFF 0x44 E_MIPS_ARCH_3 EF_MIPS_ARCH_3 AT_L2_CACHEGEOMETRY 45 SHT_HASH 5 R_AARCH64_TLSDESC_OFF_G0_NC 566 R_METAG_GETSETOFF 5 ELFOSABI_FREEBSD 9 PT_NOTE 4 R_PPC64_DTPREL16_HIGHEST 105 ELF_NOTE_ABI NT_GNU_ABI_TAG R_PPC_ADDR16_HI 5 R_ARM_THM_MOVW_PREL_NC 49 R_M32R_SDA16_RELA 42 DT_MIPS_FLAGS 0x70000005 STT_FUNC 2 MIPS_AFL_EXT_4111 13 R_LARCH_TLS_LE_ADD_R 122 STB_HIOS 12 R_LARCH_ALIGN 102 R_TILEGX_HW2 11 AT_EXECFN 31 R_X86_64_64 1 EF_MIPS_MACH_ALLEGREX 0x00840000 R_SPARC_HIPLT22 25 SHT_MIPS_AUXSYM 0x70000016 R_SH_LABEL 32 E_MIPS_ARCH_5 EF_MIPS_ARCH_5 STB_LOCAL 0 R_AARCH64_MOVW_PREL_G2_NC 292 R_TILEPRO_LO16 7 SHT_MIPS_DELTADECL 0x7000001f R_PPC64_DTPMOD64 68 DT_JMPREL 23 R_SPARC_LOPLT10 26 R_LARCH_TLS_TPREL32 10 SHN_MIPS_ACOMMON 0xff00 DT_SYMBOLIC 16 R_IA64_SECREL32MSB 0x64 R_TILEGX_IMM8_Y1 26 STO_MIPS_PROTECTED 0x3 R_MICROBLAZE_GNU_VTINHERIT 11 PT_NULL 0 R_SPARC_TLS_DTPOFF64 77 GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002 R_SPARC_H44 50 NT_S390_RI_CB 0x30d R_OR1K_HI_16_IN_INSN 5 DT_HASH 4 ELF_NOTE_SOLARIS "SUNW Solaris" R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN R_ARC_32_PCREL 0x31 _P 0x10 R_METAG_TLS_LDO 51 R_M32R_26_PCREL_RELA 38 R_NIOS2_UJMP 18 R_OR1K_PLT26 15 R_OR1K_INSN_REL_26 6 R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 R_SPARC_PCPLT32 27 R_ARM_TLS_TPOFF32 19 R_OR1K_TLS_LDM_HI16 24 R_PARISC_LTOFF21L 34 R_M32R_10_PCREL 4 R_AARCH64_TLSDESC_LD_PREL19 560 R_LARCH_SOP_PUSH_ABSOLUTE 23 R_METAG_NONE 3 EM_SVX 73 R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN R_TILEPRO_IMM16_X1_TLS_LE_LO 88 SHT_MIPS_WHIRL 0x70000026 R_M32R_LO16 9 R_PPC64_UADDR64 43 SHT_MIPS_XLATE_DEBUG 0x70000025 SHT_SUNW_COMDAT 0x6ffffffb EF_PARISC_NO_KABP 0x00100000 R_PPC_GOT_TPREL16 87 PT_IA_64_ARCHEXT (PT_LOPROC + 0) R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN R_RISCV_PCREL_HI20 23 R_PARISC_HIRESERVE 255 ELF32_ST_VISIBILITY(o) ((o) & 0x03) R_AARCH64_TLSGD_ADD_LO12_NC 514 R_AARCH64_TLSLD_MOVW_G0_NC 521 R_MICROMIPS_TLS_GD 162 EF_PARISC_LAZYSWAP 0x00400000 EM_PPC 20 R_390_8 1 R_RISCV_NONE 0 R_METAG_REG16OP2 10 R_TILEPRO_IMM16_X0 23 R_AARCH64_TLSDESC_OFF_G1 565 R_SPARC_6 45 R_IA64_FPTR32LSB 0x45 R_MICROMIPS_TLS_TPREL_LO16 170 NT_S390_HIGH_GPRS 0x300 PT_HP_CORE_NONE (PT_LOOS + 0x1) R_TILEPRO_NONE 0 R_SPARC_TLS_GD_ADD 58 EF_SH4_NOMMU_NOFPU 0x12 R_PPC64_GOT_DTPREL16_HI 93 R_386_RELATIVE 8 DT_PLTRELSZ 2 R_LARCH_GOT_HI20 79 R_NIOS2_U16 2 R_68K_TLS_GD32 25 R_AARCH64_GOTREL32 308 R_IA64_PCREL21F 0x4b R_PPC64_ADDR32 R_PPC_ADDR32 EI_DATA 5 R_PPC64_PLTGOT16 52 R_68K_TLS_TPREL32 42 R_MICROBLAZE_GOTOFF_64 19 R_SPARC_LOX10 49 DT_INIT_ARRAYSZ 27 EM_CRIS 76 R_68K_PLT32 13 R_PARISC_LTOFF64 96 DT_GNU_CONFLICTSZ 0x6ffffdf6 SHF_INFO_LINK (1 << 6) R_M32R_GOTOFF 54 R_ARC_W_ME 0x1F R_METAG_REG32OP2 7 DT_VERNEEDNUM 0x6fffffff R_SPARC_HIX22 48 NT_GNU_GOLD_VERSION 4 R_390_PC16 16 R_X86_64_IRELATIVE 37 R_SH_JMP_SLOT 164 R_TILEPRO_IMM16_X1_TLS_GD_HA 73 R_OR1K_RELATIVE 21 R_RISCV_TLS_GOT_HI20 21 R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 R_ARC_SECTOFF_2 0x2C R_PARISC_LTOFF_TP16DF 231 R_MIPS_REL32 3 R_LARCH_TLS_DESC_HI20 115 R_PPC64_COPY R_PPC_COPY R_TILEPRO_IMM16_X0_HI 27 EF_LARCH_ABI_DOUBLE_FLOAT 0x03 R_ARM_ALU_PC_G1_NC 59 SHT_SUNW_move 0x6ffffffa R_IA64_TPREL64MSB 0x96 NOTE_GNU_PROPERTY_SECTION_NAME ".note.gnu.property" R_ARC_N8 0x8 EM_SH 42 R_LARCH_TLS_DESC64_HI12 118 R_MIPS_TLS_DTPMOD64 40 R_M32R_GOTOFF_LO 64 R_MIPS_NUM 255 SHT_GNU_HASH 0x6ffffff6 R_MN10300_RELATIVE 23 EF_ARM_INTERWORK 0x04 EF_RISCV_FLOAT_ABI_SINGLE 0x0002 DF_1_ORIGIN 0x00000080 GNU_PROPERTY_X86_ISA_1_BASELINE (1U << 0) SYMINFO_NONE 0 ELF32_ST_TYPE(val) ((val) & 0xf) EF_MIPS_ARCH_4 0x30000000 ELFOSABI_NETBSD 2 EM_TSK3000 131 R_MIPS_JALR 37 R_ARM_THM_PC8 11 EF_MIPS_ARCH_ASE_MICROMIPS 0x02000000 ELFCLASSNONE 0 NT_FPREGSET 2 R_PARISC_LTOFF_TP14DR 228 PT_HISUNW 0x6fffffff R_PPC_UADDR16 25 EF_MIPS_ABI_O32 0x00001000 R_TILEGX_32 2 EM_FR20 37 DT_SPARC_NUM 2 R_ARM_ALU_PC_G0 58 DT_RELRSZ 35 R_PPC_REL16 249 EF_IA_64_MASKOS 0x0000000f read_to_eol EM_STARCORE 58 ELFMAG1 'E' ELF64_R_TYPE(i) ((i) & 0xffffffff) R_PARISC_DIR14R 6 R_PPC_REL16_HI 251 R_TILEPRO_IMM8_X0 17 EF_SH_DSP 0x4 R_ALPHA_LITUSE 5 EM_HUANY 81 SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) R_CRIS_32_PCREL 6 R_CRIS_32_PLT_PCREL 19 R_PARISC_DIR16WF 86 R_ARM_THM_XPC22 16 R_LARCH_SOP_SUB 32 PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) R_390_GOTOFF32 13 DT_MIPS_PLTGOT 0x70000032 DT_FINI 13 EM_PJ 91 R_PPC64_TLSLD 108 R_SPARC_TLS_TPOFF32 78 R_PARISC_DIR14WR 83 R_NIOS2_COPY 36 R_PPC64_GOT_TLSLD16 83 R_NIOS2_CALLR 20 EM_XTENSA 94 R_MIPS_DELETE 27 R_CKCORE_ADDRPLT_HI16 38 R_IA64_LTV64LSB 0x77 STV_INTERNAL 1 EI_CLASS 4 SHT_MIPS_SYMBOL_LIB 0x70000020 R_SPARC_TLS_DTPMOD64 75 R_PPC64_PLTGOT16_LO_DS 66 R_386_TLS_LDM 19 R_MIPS_PC26_S2 61 GNU_PROPERTY_LOUSER 0xe0000000 SHT_MIPS_GPTAB 0x70000003 RHF_RLD_ORDER_SAFE (1 << 14) R_SPARC_64 32 R_ARM_TLS_LE12 110 R_LARCH_SOP_POP_32_S_10_12 40 R_RISCV_TLS_DTPMOD32 6 R_LARCH_SOP_POP_32_S_10_16_S2 42 AT_PHDR 3 R_386_PC8 23 EFA_PARISC_1_1 0x0210 PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) R_MIPS_GNU_VTENTRY 254 EM_V850 87 EM_ST100 60 R_PPC64_GOT16_HA R_PPC_GOT16_HA R_PARISC_PCREL17F 12 R_TILEPRO_IMM16_X0_TLS_IE_LO 76 R_SPARC_GNU_VTENTRY 251 SHF_WRITE (1 << 0) EF_MIPS_ABI2 32 R_ARM_ALU_SBREL_19_12 36 R_METAG_ADDR32 2 R_NIOS2_TLS_GD16 28 DT_RELACOUNT 0x6ffffff9 R_RISCV_LO12_S 28 R_NIOS2_GNU_VTENTRY 17 LITUSE_ALPHA_JSR 3 R_X86_64_GOTPC64 29 R_RISCV_NUM 62 R_PPC_PLT16_LO 29 R_390_GOT12 6 R_IA64_LTOFF_FPTR64I 0x53 DT_VERDEFNUM 0x6ffffffd R_ARM_THM_JUMP6 52 R_RISCV_TPREL_LO12_I 30 R_TILEPRO_IMM16_X1_GOT_HA 46 SHT_MIPS_DELTASYM 0x7000001b R_PPC64_DTPREL16_DS 101 SHN_ABS 0xfff1 R_SH_DIR8BP 7 AT_BASE_PLATFORM 24 R_390_16 3 EF_MIPS_ARCH_32R6 0x90000000 DT_SYMTAB_SHNDX 34 EM_TI_C6000 140 R_ARM_REL32_NOI 56 R_TILEPRO_SHAMT_Y0 53 R_ARM_THM_TLS_DESCSEQ 129 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 530 R_LARCH_TLS_DESC_CALL 120 EM_SPARC 2 R_IA64_PCREL22 0x7a R_IA64_LTOFF_DTPREL22 0xba R_LARCH_SOP_PUSH_TLS_GOT 27 EF_ARM_SYMSARESORTED 0x04 ET_REL 1 R_X86_64_32 10 R_NIOS2_HI16 9 ELFOSABI_STANDALONE 255 R_MIPS_TLS_TPREL32 47 EF_MIPS_MACH_OCTEON3 0x008e0000 GNU_PROPERTY_UINT32_AND_LO 0xb0000000 RHF_NO_MOVE (1 << 3) STV_DEFAULT 0 isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) R_M32R_HI16_ULO_RELA 39 R_TILEPRO_COPY 10 SHT_MIPS_EH_REGION 0x70000027 R_MICROMIPS_GOT16 138 GNU_PROPERTY_NO_COPY_ON_PROTECTED 2 EF_ARC_OSABI_MSK 0x00000f00 R_MIPS_GOT16 9 R_MICROBLAZE_TLSDTPMOD32 25 STO_AARCH64_VARIANT_PCS 0x80 R_OR1K_TLS_LE_LO16 31 DT_MIPS_HIPAGENO 0x70000014 PT_HP_PARALLEL (PT_LOOS + 0x10) R_IA64_GPREL64LSB 0x2f R_CKCORE_GOT_HI16 31 R_OR1K_16_PCREL 10 R_PARISC_DIR17R 3 R_PARISC_SECREL32 41 R_AARCH64_PREL64 260 R_AARCH64_ADR_PREL_PG_HI21 275 EF_MIPS_MACH_LS2E 0x00A00000 EF_SH3_DSP 0x5 R_AARCH64_MOVW_UABS_G3 269 R_PPC_DIAB_SDA21_HA 182 R_TILEPRO_HI16 8 R_ARC_N16 0x9 R_X86_64_GOTPCREL 9 R_ARM_LDRS_SB_G2 80 R_ARM_LDC_SB_G0 81 DT_MOVESZ 0x6ffffdfb EF_ARM_APCS_26 0x08 R_ALPHA_TPREL16 41 R_ARM_GNU_VTENTRY 100 R_RISCV_SUB_ULEB128 61 R_TILEGX_IMM16_X1_HW1_PLT_PCREL 69 R_LARCH_RELATIVE 3 EM_IA_64 50 R_390_NUM 62 R_TILEGX_IMM16_X0_HW0_GOT 64 R_MN10300_PLT32 15 OEX_FPU_INEX 0x01 SHN_MIPS_TEXT 0xff01 R_TILEPRO_IMM16_X1_TLS_LE_HI 90 EM_AVR 83 R_RISCV_SUB6 52 R_ALPHA_GPRELLOW 18 EM_RCE 39 R_PPC64_GOT16_HI R_PPC_GOT16_HI DF_1_GLOBAL 0x00000002 SHT_NOTE 7 R_M32R_32_RELA 34 AT_RSEQ_FEATURE_SIZE 27 R_AARCH64_LDST8_ABS_LO12_NC 278 R_IA64_LTOFF_FPTR32LSB 0x55 R_MN10300_GOTOFF24 13 PT_IA_64_UNWIND (PT_LOPROC + 1) R_MIPS_TLS_GD 42 EM_COOL 217 STT_SPARC_REGISTER 13 ELFCOMPRESS_HIPROC 0x7fffffff R_LARCH_SOP_POP_32_U 46 RHF_CORD (1 << 12) MIPS_AFL_ASE_MIPS16 0x00000400 SHT_STRTAB 3 R_LARCH_TLS_DESC64 14 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 541 EF_MIPS_MACH_5400 0x00910000 EF_LARCH_ABI_SINGLE_FLOAT 0x02 R_X86_64_GOTPCREL64 28 R_LARCH_ABS_LO12 68 R_390_GOTPLT64 32 EF_SH4 0x9 LITUSE_ALPHA_TLS_LDM 5 R_CKCORE_PCREL_IMM7BY4 50 R_PARISC_LTOFF14R 38 NT_PSTATUS 10 R_SH_PLT32 161 R_PPC_EMB_RELST_LO 112 R_SPARC_HH22 34 R_TILEGX_RELATIVE 19 R_IA64_PLTOFF64I 0x3b EM_68HC11 70 STO_MIPS_SC_ALIGN_UNUSED 0xff R_SPARC_TLS_DTPOFF32 76 SHT_NULL 0 R_LARCH_PCREL20_S2 103 EM_ECOG2 134 R_PPC_COPY 19 R_LARCH_TLS_GD_PCREL20_S2 125 R_RISCV_PCREL_LO12_S 25 SHT_HIPROC 0x7fffffff R_PPC_DIAB_RELSDA_HI 184 R_NDS32_TLS_DESC 119 AT_L3_CACHESIZE 46 R_TILEGX_JUMPOFF_X1_PLT 22 R_PPC64_GOT_TLSLD16_LO 84 SHT_SYMTAB 2 R_PARISC_TLS_LDMCALL 239 R_PPC64_SECTOFF_LO_DS 62 R_IA64_PLTOFF64MSB 0x3e R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 559 DT_EXTRANUM 3 AT_L3_CACHESHAPE 37 R_LARCH_SOP_AND 36 ELFOSABI_SOLARIS 6 R_MN10300_GLOB_DAT 21 R_LARCH_ABS_HI20 67 DT_MIPS_GOTSYM 0x70000013 DT_MIPS_RLD_MAP 0x70000016 R_MICROMIPS_GOT_OFST 147 R_PPC64_TPREL16_HA 72 R_386_TLS_GD_CALL 26 R_PPC_ADDR24 2 R_X86_64_JUMP_SLOT 7 EF_PARISC_ARCH 0x0000ffff ELFOSABI_LINUX ELFOSABI_GNU EM_L10M 180 R_LARCH_SOP_POP_32_S_5_20 43 MIPS_AFL_ASE_MT 0x00000040 VER_NDX_ELIMINATE 0xff01 DT_VERSIONTAGNUM 16 R_X86_64_NONE 0 DT_NULL 0 R_X86_64_GOT64 27 R_386_JMP_SLOT 7 MIPS_AFL_REG_NONE 0x00 R_PPC64_UADDR16 R_PPC_UADDR16 R_ARM_RPC24 254 R_AARCH64_MOVW_GOTOFF_G2_NC 305 R_LARCH_B26 66 EM_LATTICEMICO32 138 R_M32R_16_RELA 33 R_M32R_GOT24 48 R_TILEGX_IMM16_X1_HW1_PCREL 53 R_LARCH_TLS_LE_LO12_R 123 R_ARM_ALU_PC_G0_NC 57 EM_MN10200 90 R_METAG_LO16_PLT 39 NT_PPC_TM_CFPR 0x109 R_PARISC_GPREL16WF 94 STT_GNU_IFUNC 10 R_LARCH_TLS_LD_HI20 96 STV_PROTECTED 3 EM_F2MC16 104 R_M32R_HI16_SLO_RELA 40 LL_IGNORE_INT_VER (1 << 1) isspace(c) ((__ismask(c)&(_S)) != 0) R_TILEPRO_GNU_VTINHERIT 128 VER_NEED_NONE 0 ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) R_ARM_LDR_SB_G1 76 R_TILEPRO_IMM16_X1_HA 30 R_MIPS_TLS_DTPREL_HI16 44 R_METAG_TLS_LDO_LO16 50 R_ARC_GLOB_DAT 0x36 R_CKCORE_TLS_DTPOFF32 57 R_ARM_ABS32 2 R_PARISC_DIR16DF 87 R_CKCORE_PCRELIMM11BY2 3 R_NIOS2_TLS_TPREL 35 R_SPARC_TLS_IE_ADD 71 R_METAG_RELBRANCH_PLT 40 EM_DSPIC30F 118 R_LARCH_IRELATIVE 12 __compiletime_assert(condition,msg,prefix,suffix) do { } while (0) DT_ADDRRNGLO 0x6ffffe00 SYMINFO_BT_SELF 0xffff DT_VERNEED 0x6ffffffe R_PARISC_DIR14DR 84 DT_X86_64_NUM 4 R_MN10300_GOTPC16 11 DT_FINI_ARRAYSZ 28 R_METAG_TLS_TPOFF 56 R_MIPS_TLS_DTPMOD32 38 SHT_MIPS_SHDR 0x70000010 DT_MIPS_PROTECTED_GOTIDX 0x70000028 R_OR1K_GOTPC_HI16 12 R_ARM_MOVT_BREL 85 R_SPARC_11 31 EM_DSP24 136 ELFDATA2MSB 2 R_MICROBLAZE_GOTOFF_32 20 R_PPC64_GOT_TPREL16_DS 87 R_SPARC_8 1 R_ARC_N32 0xB R_LARCH_TLS_LE_HI20 83 R_68K_GOT32 7 EM_NS32K 97 R_MICROBLAZE_SRO32 7 GNU_PROPERTY_X86_ISA_1_V4 (1U << 3) toupper(c) __toupper(c) DT_MIPS_DELTA_SYM_NO 0x7000001e R_NIOS2_GOTOFF_LO 24 STT_LOOS 10 R_NIOS2_PCREL_HA 27 VER_NEED_CURRENT 1 R_MN10300_NONE 0 DT_RELSZ 18 AT_ENTRY 9 R_390_TLS_LDM64 46 R_PPC64_ADDR16 R_PPC_ADDR16 AT_DCACHEBSIZE 19 R_IA64_LTOFF_FPTR64MSB 0x56 R_AARCH64_MOVW_PREL_G2 291 EF_MIPS_32BITMODE 0x00000100 _SP 0x80 R_IA64_SEGREL64MSB 0x5e NT_S390_GS_BC 0x30c R_METAG_HI16_PLT 38 R_NIOS2_S16 1 R_TILEPRO_IMM16_X0_TLS_IE_HI 78 EF_MIPS_MACH_GS264E 0x00A40000 R_AARCH64_TLSLD_MOVW_G1 520 DT_PPC64_GLINK (DT_LOPROC + 0) R_MICROMIPS_LITERAL 137 R_TILEGX_IMM16_X0_HW1 38 SHT_MIPS_LIBLIST 0x70000000 R_MICROBLAZE_32_LO 6 R_PPC_PLT16_HI 30 R_ARM_COPY 20 R_TILEGX_IMM16_X1_HW2 41 R_TILEGX_IMM8_X0 23 R_CRIS_32_PLT_GOTREL 18 R_MIPS_GPREL32 12 R_TILEGX_SHAMT_Y1 35 EM_PRISM 82 R_AARCH64_MOVW_UABS_G0 263 OEX_PRECISEFP OEX_FPDBUG R_PARISC_LTOFF_FPTR21L 58 R_386_8 22 R_PPC64_PLT16_LO R_PPC_PLT16_LO AT_L1D_CACHESIZE 42 SHT_CHECKSUM 0x6ffffff8 R_ARM_THM_ABS5 7 EM_MIPS 8 EM_PDP11 65 EM_X86_64 62 R_AARCH64_TLSDESC_ADD_LO12 564 R_390_GOTENT 26 R_OR1K_GLOB_DAT 19 EF_MIPS_ARCH_3 0x20000000 R_AARCH64_COPY 1024 R_TILEGX_16_PCREL 7 R_PARISC_TLS_LE14R R_PARISC_TPREL14R EF_SPARC_HAL_R1 0x000400 SHT_MIPS_UCODE 0x70000004 R_TILEGX_IMM16_X0_HW2_LAST 48 R_PPC_GOT16_LO 15 R_X86_64_TPOFF64 18 DT_VERDEF 0x6ffffffc R_LARCH_TLS_IE64_PC_LO20 89 R_PPC_ADDR16_HA 6 EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) R_ARM_LDRS_PC_G2 66 R_68K_TLS_IE16 35 R_MIPS16_TLS_TPREL_HI16 111 ODK_PAD 3 R_RISCV_SET32 56 MIPS_AFL_EXT_LOONGSON_2F 18 R_SPARC_TLS_DTPMOD32 74 R_CKCORE_DOFFSET_IMM18BY4 46 NT_S390_TODCMP 0x302 R_AARCH64_MOVW_PREL_G1_NC 290 STT_TLS 6 R_METAG_TLS_IE 52 R_PARISC_LTOFF16WF 102 R_SPARC_DISP16 5 R_LARCH_TLS_IE_LO12 92 R_M32R_GNU_VTINHERIT 11 MIPS_AFL_EXT_LOONGSON_2E 17 R_PPC_ADDR14_BRTAKEN 8 R_PPC64_TOC16_HA 50 DT_FEATURE_1 0x6ffffdfc R_ARM_LDC_PC_G0 67 SHN_MIPS_DATA 0xff02 PT_LOAD 1 R_SPARC_M44 51 R_ARM_NONE 0 PT_IA_64_HP_STACK (PT_LOOS + 0x14) OEX_FPDBUG 0x40000 DF_1_INTERPOSE 0x00000400 R_NIOS2_GOT_HA 43 R_LARCH_SOP_POP_32_S_10_5 38 R_AARCH64_JUMP_SLOT 1026 R_NIOS2_NONE 0 R_MIPS_PCLO16 65 SHT_ARC_ATTRIBUTES (SHT_LOPROC + 1) PT_PHDR 6 R_PPC64_PLT32 R_PPC_PLT32 R_CRIS_GNU_VTINHERIT 7 ELFOSABI_TRU64 10 R_RISCV_TLS_TPREL64 11 R_MIPS_RELATIVE 128 STT_LOPROC 13 R_AARCH64_IRELATIVE 1032 ELF_NOTE_OS_GNU 1 EF_MIPS_OPTIONS_FIRST 0x00000080 EF_MIPS_MACH_GS464E 0x00A30000 SHN_HIRESERVE 0xffff EI_MAG0 0 AT_PHNUM 5 R_MICROMIPS_SCN_DISP 155 R_LARCH_TLS_DESC32 13 R_MICROBLAZE_GLOB_DAT 18 R_OR1K_GOTOFF_HI16 16 PT_HP_OPT_ANNOT (PT_LOOS + 0x12) EF_SH_UNKNOWN 0x0 R_SPARC_HM10 35 AT_RANDOM 25 R_TILEPRO_IMM16_X0_TLS_LE_HI 89 STO_ALPHA_STD_GPLOAD 0x88 EF_ARM_EABIMASK 0XFF000000 MIPS_AFL_ASE_DSPR2 0x00000002 R_LARCH_GOT64_LO20 81 DT_MOVEENT 0x6ffffdfa NT_LOONGARCH_CPUCFG 0xa00 EM_960 19 R_PPC64_GOT_TLSLD16_HI 85 ELF32_M_SIZE(info) ((unsigned char) (info)) R_ARM_SBREL31 39 R_CRIS_32_GOT 14 R_IA64_PCREL32MSB 0x4c R_AARCH64_P32_TLS_DTPMOD 184 EFA_PARISC_2_0 0x0214 R_AARCH64_TLSLD_ADR_PREL21 517 R_IA64_PCREL32LSB 0x4d R_METAG_PLT 42 NT_386_TLS 0x200 R_IA64_REL32MSB 0x6c EM_IAMCU 6 R_PPC64_REL16_HI 251 EF_MIPS_MACH_9000 0x00990000 EM_ARC_COMPACT 93 DT_PREINIT_ARRAY 32 PF_MIPS_LOCAL 0x10000000 R_RISCV_ADD64 36 DT_AUXILIARY 0x7ffffffd SHF_MASKPROC 0xf0000000 R_PPC_TPREL16_HA 72 PT_MIPS_RTPROC 0x70000001 OHWA0_R4KEOP_CHECKED 0x00000001 R_MICROMIPS_PC16_S1 141 R_68K_TLS_IE32 34 EM_MMDSP_PLUS 160 EM_COLDFIRE 52 R_X86_64_PC16 13 symbol_type R_AARCH64_TLSGD_MOVW_G0_NC 516 R_MIPS_RELGOT 36 NT_PPC_PKEY 0x110 SHT_MIPS_MSYM 0x70000001 R_ARM_THM_PC9 103 R_386_COPY 5 R_IA64_SEGREL32LSB 0x5d MIPS_AFL_ASE_MICROMIPS 0x00000800 AT_EXECFD 2 PT_DYNAMIC 2 R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 DT_MIPS_IVERSION 0x70000004 PT_ARM_EXIDX (PT_LOPROC + 1) R_PPC_EMB_SDAI16 106 R_CRIS_32_GOTREL 17 EF_SPARC_EXT_MASK 0xFFFF00 R_TILEPRO_IMM16_X0_GOT_HI 43 R_386_PC16 21 SHN_MIPS_SUNDEFINED 0xff04 EM_78KOR 199 R_CKCORE_NONE 0 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 538 R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN DF_1_NOOPEN 0x00000040 SHT_SUNW_syminfo 0x6ffffffc R_CRIS_32 3 STT_HIPROC 15 R_68K_TLS_LDM16 29 DT_MIPS_DYNSTR_ALIGN 0x7000002b SHT_DYNAMIC 6 R_CRIS_NONE 0 EF_SH2A_SH3_NOFPU 0x16 NT_PPC_TM_CPPR 0x10e R_METAG_TLS_LE_LO16 61 R_PPC64_ADDR64 38 R_PARISC_PCREL64 72 STT_ARM_TFUNC STT_LOPROC ET_NONE 0 R_390_GOTPLT32 31 DF_1_DIRECT 0x00000100 SHF_IA_64_SHORT 0x10000000 R_PPC64_ADDR16_HIGHEST 41 SHT_MIPS_XHASH 0x7000002b R_MIPS_32 2 DT_MIPS_LIBLISTNO 0x70000010 EF_ALPHA_CANRELAX 2 EM_H8_500 49 R_ARC_SECTOFF_ME_2 0x2A R_ARM_GOTPC 25 EM_TILEPRO 188 R_X86_64_REX_GOTPCRELX 42 R_SH_TLS_GD_32 144 R_PPC_DTPREL16_LO 75 R_ARM_LDR_PC_G1 62 R_PARISC_GPREL16DF 95 OPAD_SYMBOL 0x4 R_ARM_THM_PC11 102 R_METAG_LOOG 14 R_LARCH_64 2 R_M32R_GOTOFF_HI_ULO 62 PF_HP_CODE 0x01000000 R_CKCORE_COPY 10 R_PPC64_GOT16_LO R_PPC_GOT16_LO EM_MMA 54 R_AARCH64_GOT_LD_PREL19 309 EM_BPF 247 STO_MIPS_PLT 0x8 R_AARCH64_TLSDESC_LD64_LO12 563 RHF_SGI_ONLY (1 << 4) R_SH_DIR8L 9 R_OR1K_TLS_IE_LO16 29 R_TILEPRO_IMM8_X0_TLS_GD_ADD 61 R_CKCORE_GOTPC_LO16 27 R_CKCORE_ADDRGOT 17 AT_SECURE 23 R_IA64_PCREL21M 0x4a R_AARCH64_TLSLD_LD_PREL19 522 R_TILEGX_IMM8_X0_TLS_ADD 118 R_ALPHA_TPRELLO 40 R_PARISC_TLS_LDM21L 237 DT_LOPROC 0x70000000 R_SPARC_PC_LM22 39 LL_REQUIRE_MINOR (1 << 2) ET_EXEC 2 EM_MMIX 80 R_ALPHA_TLS_GD_HI 28 R_PPC64_ADDR16_HA R_PPC_ADDR16_HA ELFCOMPRESS_LOOS 0x60000000 R_IA64_COPY 0x84 R_PPC64_ADDR16_HIGHESTA 42 R_TILEPRO_MMSTART_X0 47 R_PPC_GOT_TPREL16_HA 90 R_LARCH_TLS_DTPMOD64 7 R_M32R_NUM 256 R_MIPS_CALL_LO16 31 R_TILEGX_IMM16_X1_HW2_PLT_PCREL 71 R_MICROMIPS_GOT_DISP 145 SHT_CSKY_ATTRIBUTES (SHT_LOPROC + 1) _ELF_H 1 R_NIOS2_TLS_IE16 31 NT_RISCV_VECTOR 0x901 DF_1_LOADFLTR 0x00000010 R_LARCH_TLS_LD_PCREL20_S2 124 EF_CSKY_ABIV1 0X10000000 R_IA64_DIR64MSB 0x26 R_NIOS2_GOT16 22 R_PARISC_GPREL14R 30 R_390_PC32DBL 19 GNU_PROPERTY_LOPROC 0xc0000000 NT_ARM_TLS 0x401 R_MN10300_COPY 20 R_RISCV_SUB16 38 R_TILEGX_8 4 R_PPC_REL16_LO 250 R_ARC_S21W_PCREL_PLT 0x3C EF_ARM_APCS_FLOAT 0x10 DT_RUNPATH 29 R_MICROBLAZE_COPY 21 ELFCOMPRESS_ZLIB 1 R_ARM_TLS_LDO32 106 R_SH_SWITCH32 26 AT_L3_CACHEGEOMETRY 47 PF_ARM_SB 0x10000000 OEX_SMM 0x20000 R_PPC_TPREL32 73 EF_MIPS_PIC 2 R_PPC_GOT16_HI 16 R_PARISC_PCREL14R 14 R_OR1K_TLS_GD_LO16 23 VER_NEED_NUM 2 EM_KMX32 211 R_ARM_ALU_SBREL_27_20 37 R_390_GOTPLTENT 33 EM_FIREPATH 78 SHT_MIPS_DELTACLASS 0x7000001d R_TILEPRO_IMM16_X0_TLS_LE_HA 91 R_386_NONE 0 R_RISCV_GOT_HI20 20 R_68K_TLS_LDO8 33 R_ARC_JLI_SECTOFF 0x3F R_390_RELATIVE 12 R_RISCV_IRELATIVE 58 R_PPC64_IRELATIVE 248 R_MIPS_GOT_HI16 22 GNU_PROPERTY_1_NEEDED GNU_PROPERTY_UINT32_OR_LO R_PARISC_LTOFF16DF 103 R_PPC_EMB_SDA2REL 108 SHT_MIPS_XLATE 0x70000024 R_68K_JMP_SLOT 21 EF_ALPHA_32BIT 1 R_TILEPRO_BROFF_X1 14 EF_PPC_RELOCATABLE 0x00010000 R_METAG_TLS_DTPMOD 57 R_ARM_LDRS_PC_G0 64 R_390_PLT32DBL 20 R_ARM_V4BX 40 EF_ARM_EABI_VER2 0x02000000 EF_ARC_ALL_MSK (EF_ARC_MACH_MSK | EF_ARC_OSABI_MSK) R_PPC_TOC16 255 EM_AVR32 185 R_IA64_LTV32MSB 0x74 R_AARCH64_P32_IRELATIVE 188 ELFDATANONE 0 EM_FR30 84 R_SH_TLS_LD_32 145 PT_PARISC_ARCHEXT 0x70000000 NT_FDO_DLOPEN_METADATA 0x407c0c0a R_386_TLS_LDM_POP 31 R_PARISC_TPREL16F 221 DF_P1_LAZYLOAD 0x00000001 NT_ARM_SYSTEM_CALL 0x404 R_ARM_PC13 4 R_AARCH64_MOVW_GOTOFF_G0 300 R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 R_390_TLS_IEENT 49 R_ARC_S25W_PCREL_PLT 0x4C NT_PPC_TM_CDSCR 0x10f EM_M32R 88 RHF_REQUICKSTART (1 << 10) EF_MIPS_ABI 0x0000F000 R_MICROMIPS_CALL_HI16 153 EM_ECOG1X 168 R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 R_PPC64_GOT_TLSGD16 79 R_OR1K_GNU_VTENTRY 7 R_ARM_PLT32 27 R_TILEPRO_IMM16_X1_TLS_IE_HI 79 R_LARCH_SOP_ADD 35 R_SH_REL32 2 R_SPARC_PC10 16 R_TILEPRO_GLOB_DAT 11 R_TILEPRO_MT_IMM15_X1 21 SHN_HIOS 0xff3f R_PARISC_TLS_DTPOFF32 244 R_AARCH64_TLSDESC_CALL 569 R_PPC_DTPREL32 78 R_SPARC_TLS_IE_LD 69 R_SPARC_WDISP16 40 EM_TILEGX 191 R_M32R_GOT16_HI_SLO 57 EM_V800 36 PT_HP_CORE_SHM (PT_LOOS + 0x8) R_SPARC_GLOB_DAT 20 SHF_MIPS_NAMES 0x02000000 EM_M32C 120 _D 0x04 R_CKCORE_GOT_IMM18BY4 48 R_TILEPRO_JMP_SLOT 12 R_386_TLS_LE_32 34 R_SH_NUM 256 DT_MIPS_LOCAL_GOTNO 0x7000000a R_TILEPRO_IMM16_X1_TLS_IE_LO 77 R_PARISC_TLS_LE21L R_PARISC_TPREL21L R_METAG_TLS_LE_HI16 60 OHW_R5KEOP 0x4 R_AARCH64_TLSLE_LDST8_TPREL_LO12 552 R_RISCV_TPREL_LO12_S 31 R_IA64_LTOFF_FPTR22 0x52 EF_MIPS_MACH_4111 0x00880000 R_TILEGX_IMM16_X1_HW0_PCREL 51 R_IA64_DTPREL32MSB 0xb4 R_68K_TLS_LDO32 31 R_PPC_SECTOFF 33 R_PPC64_PLT16_LO_DS 60 STO_MIPS_HIDDEN 0x2 R_NIOS2_IMM8 8 R_METAG_LOADDR16 1 EM_BA1 201 R_PARISC_PLABEL21L 66 R_TILEPRO_8_PCREL 6 R_LARCH_TLS_DESC_PCREL20_S2 126 R_ARC_SECTOFF_U8 0x21 R_SPARC_PCPLT10 29 DT_MIPS_GP_VALUE 0x70000030 R_X86_64_TPOFF32 23 PF_R (1 << 2) EF_MIPS_ARCH_2 0x10000000 R_AARCH64_LDST32_ABS_LO12_NC 285 R_390_TLS_IE32 47 ELFOSABI_ARM 97 NT_LOONGARCH_HW_BREAK 0xa05 DT_DEBUG 21 R_TILEPRO_IMM16_X1_TLS_LE 86 PF_HP_FAR_SHARED 0x00200000 PT_HP_CORE_PROC (PT_LOOS + 0x5) R_SPARC_LM22 36 AT_BASE 7 EF_ARM_OLD_ABI 0x100 R_MIPS_SUB 24 R_ALPHA_HINT 8 R_IA64_DIR32LSB 0x25 R_386_16 20 R_PPC64_PLTGOT16_HA 55 DT_CHECKSUM 0x6ffffdf8 DT_GNU_CONFLICT 0x6ffffef8 EM_Z80 220 R_TILEGX_8_PCREL 8 R_M32R_18_PCREL 5 R_PPC_SECTOFF_LO 34 NT_MIPS_MSA 0x802 R_NIOS2_CALL26_NOAT 41 EI_MAG2 2 DT_SONAME 14 R_ALPHA_GPDISP 6 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 532 R_PARISC_PLTOFF14R 54 NT_PRXREG 4 MIPS_AFL_ASE_MCU 0x00000008 E_MIPS_ARCH_32 EF_MIPS_ARCH_32 ET_LOPROC 0xff00 R_PPC64_GOT_DTPREL16_HA 94 R_TILEGX_TLS_DTPMOD32 109 DF_1_PIE 0x08000000 R_CRIS_NUM 20 R_AARCH64_JUMP26 282 R_386_32 1 R_MIPS_JUMP_SLOT 127 PT_NUM 8 DT_ADDRNUM 11 PT_TLS 7 R_PPC_DTPREL16_HI 76 R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 97 R_TILEGX_SHAMT_X0 32 R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 R_ALPHA_TPRELHI 39 R_NIOS2_HIADJ16 11 EM_MIPS_RS3_LE 10 EM_NONE 0 ELFCOMPRESS_HIOS 0x6fffffff EF_MIPS_ARCH_64R6 0xa0000000 R_M32R_HI16_ULO 7 DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) R_TILEGX_JUMPOFF_X1 21 R_X86_64_RELATIVE64 38 R_AARCH64_GLOB_DAT 1025 R_LARCH_PCALA_HI20 71 R_TILEGX_64 1 R_MICROBLAZE_GNU_VTENTRY 12 R_ARM_TLS_DESC 13 VER_NDX_GLOBAL 1 SHT_ARM_EXIDX (SHT_LOPROC + 1) R_390_PLT32 8 R_ARM_RABS22 253 R_PPC_GOT_DTPREL16_LO 92 R_MIPS_ADD_IMMEDIATE 34 DT_STRTAB 5 R_TILEGX_IMM16_X0_HW0_TLS_LE 80 SHF_MIPS_STRINGS 0x80000000 EM_SEP 108 R_RISCV_ADD32 35 R_AARCH64_TLSDESC_ADR_PREL21 561 SHN_PARISC_HUGE_COMMON 0xff01 R_390_TLS_LE64 51 R_TILEPRO_IMM16_X0_HA 29 DT_MIPS_LOCAL_GOTIDX 0x70000026 R_MICROBLAZE_TLSGD 23 R_LARCH_GNU_VTENTRY 58 R_RISCV_PCREL_LO12_I 24 R_PPC64_REL16_HA 252 R_AARCH64_ADR_PREL_LO21 274 R_PPC_GOT_TLSGD16_HI 81 EM_CSR_KALIMBA 219 MIPS_AFL_EXT_5500 16 EM_ARCA 109 DT_SYMENT 11 R_OR1K_JMP_SLOT 20 R_SPARC_OLO10 33 PT_MIPS_REGINFO 0x70000000 R_RISCV_TPREL_HI20 29 R_PARISC_DPREL14R 22 EF_ARM_EABI_VER4 0x04000000 DT_MIPS_DELTA_INSTANCE 0x70000019 R_PARISC_TLS_DTPMOD32 242 R_MIPS_INSERT_B 26 R_AARCH64_MOVW_UABS_G0_NC 264 AT_EGID 14 R_MICROMIPS_GOT_LO16 149 R_RISCV_SUB64 40 EF_SH2A_NOFPU 0x13 R_SH_TLS_IE_32 147 R_PPC64_RELATIVE R_PPC_RELATIVE R_TILEGX_IMM16_X1_HW0_TLS_LE 81 R_TILEGX_IMM16_X0_HW2_PCREL 54 DT_MIPS_PIXIE_INIT 0x70000023 R_METAG_GETSET_GOTOFF 34 NT_AUXV 6 R_IA64_FPTR32MSB 0x44 R_PPC_IRELATIVE 248 R_ALPHA_RELATIVE 27 R_SPARC_JMP_IREL 248 R_AARCH64_MOVW_PREL_G3 293 R_M32R_18_PCREL_RELA 37 DT_MIPS_AUX_DYNAMIC 0x70000031 EM_VIDEOCORE5 198 R_IA64_DTPREL22 0xb2 R_M32R_GLOB_DAT 51 ELFOSABI_MODESTO 11 PPC64_OPT_TLS 1 R_ARM_TLS_GOTDESC 90 R_390_GOTPLT20 59 R_TILEGX_IMM16_X0_HW2_PLT_PCREL 70 EM_68HC12 53 R_IA64_IMM14 0x21 PF_W (1 << 1) R_SPARC_5 44 R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 96 EM_PARISC 15 EF_MIPS_MACH_4650 0x00850000 R_386_32PLT 11 R_SH_GOTPC 167 R_SH_DIR8WPL 5 R_AARCH64_P32_GLOB_DAT 181 R_AARCH64_MOVW_UABS_G1 265 R_ARM_ALU_PCREL_7_0 32 R_MIPS_LITERAL 8 R_METAG_REL8 15 R_MICROMIPS_SUB 150 SHT_LOOS 0x60000000 NT_PPC_TM_CVMX 0x10a R_RISCV_SET8 54 DT_MIPS_DELTA_RELOC_NO 0x7000001c R_SPARC_TLS_LDM_ADD 62 R_MICROMIPS_JALR 156 R_AARCH64_ABS16 259 R_ARC_TLS_LE_S9 0x4A ODK_REGINFO 1 NT_PRCRED 14 AT_ICACHEBSIZE 20 EF_MIPS_MACH_OCTEON2 0x008d0000 R_TILEPRO_IMM16_X0_HI_PCREL 35 ODK_HWAND 7 DT_MIPS_UNREFEXTNO 0x70000012 SHT_HISUNW 0x6fffffff AT_GID 13 R_PARISC_PCREL16F 77 R_MIPS16_TLS_LDM 107 EF_IA_64_ABI64 0x00000010 GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 R_RISCV_TLS_DTPMOD64 7 SHT_RISCV_ATTRIBUTES (SHT_LOPROC + 3) DT_MIPS_XHASH 0x70000036 R_MN10300_GNU_VTENTRY 8 R_PPC_DIAB_SDA21_HI 181 R_MICROMIPS_GPREL16 136 R_OR1K_8_PCREL 11 R_AARCH64_TLSDESC 1031 R_AARCH64_LDST64_ABS_LO12_NC 286 R_MICROMIPS_HI16 134 R_390_32 4 R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 R_PARISC_LTOFF14WR 99 EM_S390 22 GNU_PROPERTY_X86_FEATURE_1_SHSTK (1U << 1) R_PPC64_DTPREL16_LO_DS 102 R_ALPHA_GPREL16 19 R_M32R_26_PLTREL 49 ELFCLASS32 1 DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) R_PARISC_TLS_GD14R 235 AT_PLATFORM 15 R_386_NUM 44 NT_MIPS_DSP 0x800 R_X86_64_GOTPC32_TLSDESC 34 SHT_PREINIT_ARRAY 16 DT_MIPS_RWPLT 0x70000034 R_METAG_REG16OP3 11 DT_PLTPADSZ 0x6ffffdf9 DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d DT_RELCOUNT 0x6ffffffa RHF_REQUICKSTARTED (1 << 11) R_PARISC_GPREL14DR 92 R_AARCH64_TLSDESC_ADD 568 R_AARCH64_TLSLD_LDST128_DTPREL_LO12 572 R_ARM_RXPC25 249 R_ARC_S13_PCREL 0x19 R_CKCORE_PLT12 33 R_ARM_TLS_IE12GP 111 EM_TINYJ 61 EF_MIPS_MACH_XLR 0x008c0000 EF_RISCV_TSO 0x0010 EM_TPC 98 SHF_IA_64_NORECOV 0x20000000 R_MN10300_16 2 R_RISCV_SET_ULEB128 60 AT_L1I_CACHEGEOMETRY 41 R_MN10300_TLS_LDO 26 R_TILEGX_IMM16_X1_HW3_PLT_PCREL 77 R_MIPS_PC18_S3 62 R_TILEPRO_IMM8_Y0 18 R_MIPS16_LO16 105 EV_CURRENT 1 R_IA64_LTV64MSB 0x76 R_SPARC_LO10 12 R_IA64_IPLTLSB 0x81 EI_MAG1 1 R_PARISC_PLTOFF21L 50 EM_TRICORE 44 R_390_TLS_LDO32 52 R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 R_CRIS_32_GOTPLT 16 R_PARISC_SEGBASE 48 EV_NUM 2 SHT_LOUSER 0x80000000 R_ARC_SDA 0xC R_MIPS_EH 249 R_NIOS2_LO16 10 R_RISCV_TPREL_ADD 32 EF_ARM_ABI_FLOAT_HARD 0x400 R_OR1K_TLS_LDM_LO16 25 EF_ARM_SOFT_FLOAT 0x200 R_TILEGX_IMM16_X0_HW0_LAST 44 _U 0x01 R_PPC_SECTOFF_HI 35 R_386_GOT32X 43 R_TILEPRO_IMM16_X1_TLS_LE_HA 92 NT_UTSNAME 15 DT_X86_64_PLT (DT_LOPROC + 0) R_ARM_RELATIVE 23 R_CRIS_16_GOTPLT 15 DT_PPC_OPT (DT_LOPROC + 1) R_SPARC_TLS_IE_LO10 68 ELF64_M_SIZE(info) ELF32_M_SIZE (info) OPAD_POSTFIX 0x2 NT_GNU_HWCAP 2 STT_ARM_16BIT STT_HIPROC R_LARCH_TLS_DESC64_PC_HI12 114 AT_HWCAP4 30 R_TILEGX_64_PCREL 5 R_IA64_IMM64 0x23 R_SPARC_TLS_GD_LO10 57 R_OR1K_TLS_DTPOFF 33 R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 94 R_TILEPRO_MF_IMM15_X1 22 R_SPARC_COPY 19 EM_H8S 48 DT_PPC_GOT (DT_LOPROC + 0) R_AARCH64_LDST128_ABS_LO12_NC 299 SHF_COMPRESSED (1 << 11) EM_ALTERA_NIOS2 113 DT_ADDRRNGHI 0x6ffffeff R_AARCH64_TLSLD_LDST32_DTPREL_LO12 535 R_METAG_REG32OP4 12 E_MIPS_ARCH_64 EF_MIPS_ARCH_64 R_NIOS2_TLS_DTPMOD 33 R_AARCH64_ADD_ABS_LO12_NC 277 EF_CPU32 0x00810000 R_PPC64_REL16_LO 250 R_CKCORE_PCREL_IMM10BY4 23 R_SPARC_TLS_LDM_CALL 63 MIPS_AFL_EXT_OCTEON2 2 R_NIOS2_GPREL 15 DT_PPC64_OPDSZ (DT_LOPROC + 2) EM_ARCV2 195 LITUSE_ALPHA_TLS_GD 4 R_386_TLS_GOTDESC 39 R_PPC_LOCAL24PC 23 MIPS_AFL_EXT_OCTEONP 3 R_NDS32_JMP_SLOT 41 DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) NT_LOONGARCH_LBT 0xa04 RHF_NO_UNRES_UNDEF (1 << 13) STB_HIPROC 15 R_386_GLOB_DAT 6 R_ARM_MOVW_BREL 86 R_IA64_GPREL64MSB 0x2e R_PARISC_COPY 128 DT_MIPS_LIBLIST 0x70000009 R_MICROBLAZE_32_PCREL 2 SELFMAG 4 R_RISCV_TPREL_S 50 R_ARM_RBASE 255 R_LARCH_RELAX 100 R_ARM_LDRS_SB_G1 79 ELF32_M_SYM(info) ((info) >> 8) EF_MIPS_ARCH_64 0x60000000 NT_S390_PREFIX 0x305 R_ARC_H30 0x7 R_TILEGX_IMM16_X1_HW3_PCREL 57 R_METAG_HI16_GOTOFF 32 EM_EMX16 212 R_IA64_GPREL32MSB 0x2c R_AARCH64_TLSGD_ADR_PREL21 512 R_M32R_REL32 45 R_LARCH_SOP_PUSH_PCREL 22 R_MN10300_GOT32 17 R_LARCH_ADD8 47 R_ALPHA_DTPREL16 36 EM_NDS32 167 R_TILEGX_GLOB_DAT 17 R_LARCH_CALL36 110 DT_POSFLAG_1 0x6ffffdfd R_TILEGX_IMM16_X0_HW1_LAST 46 ELFMAG3 'F' R_PPC64_GOT_DTPREL16_LO_DS 92 AT_RSEQ_ALIGN 28 DT_MIPS_COMPACT_SIZE 0x7000002f R_390_TLS_DTPOFF 55 EM_CRAYNV2 172 DT_MIPS_DELTA_RELOC 0x7000001b R_IA64_TPREL14 0x91 R_ALPHA_COPY 24 R_IA64_TPREL64I 0x93 R_LARCH_SOP_PUSH_TLS_TPREL 26 EF_PARISC_WIDE 0x00080000 NT_GNU_ABI_TAG 1 ODK_EXCEPTIONS 2 EF_MIPS_ARCH_1 0x00000000 R_MICROMIPS_TLS_DTPREL_HI16 164 SHT_MIPS_IFACE 0x7000000b R_MICROBLAZE_SRW32 8 SHT_HIOS 0x6fffffff OEX_FPU_UFLO 0x02 EM_XGATE 115 R_M32R_RELA_GNU_VTINHERIT 43 R_IA64_LTOFF_FPTR32MSB 0x54 R_SPARC_PCPLT22 28 GNU_PROPERTY_STACK_SIZE 1 R_390_PC64 23 EM_MCHP_PIC 204 R_METAG_COPY 43 R_SH_GOTOFF 166 EM_TI_C5500 142 R_METAG_TLS_LE 59 PT_HP_CORE_COMM (PT_LOOS + 0x4) R_PPC64_ADDR16_HI R_PPC_ADDR16_HI PPC64_OPT_LOCALENTRY 4 R_RISCV_ALIGN 43 R_PPC64_REL64 44 R_MN10300_TLS_LD 25 GNU_PROPERTY_UINT32_AND_HI 0xb0007fff R_PARISC_TLS_GD21L 234 R_PPC_EMB_NADDR32 101 R_ARC_SECTOFF_S9 0x22 EM_QDSP6 164 DT_MIPS_CONFLICTNO 0x7000000b PT_MIPS_OPTIONS 0x70000002 DF_1_INITFIRST 0x00000020 R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64 SHT_MIPS_EVENTS 0x70000021 R_NIOS2_PCREL16 3 NT_GNU_BUILD_ID 3 RHF_GUARANTEE_START_INIT (1 << 7) DT_SYMINSZ 0x6ffffdfe NT_PPC_TAR 0x103 R_IA64_LTV32LSB 0x75 R_ARM_THM_MOVW_BREL_NC 87 NT_PPC_VSX 0x102 R_LARCH_GOT_PC_HI20 75 R_NIOS2_PCREL_LO 26 SHF_MIPS_MERGE 0x20000000 EF_IA_64_ARCH 0xff000000 R_M32R_GOTPC_HI_ULO 59 SHT_LOSUNW 0x6ffffffa R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 R_CRIS_16_PCREL 5 PT_RISCV_ATTRIBUTES (PT_LOPROC + 3) R_CKCORE_GOTOFF 13 EM_PCP 55 R_390_64 22 PF_MASKOS 0x0ff00000 R_390_TLS_LE32 50 R_SH_COUNT 28 SHF_MIPS_LOCAL 0x04000000 EM_TI_C2000 141 R_390_TLS_GD64 41 R_CKCORE_ADDRGOT_HI16 36 R_SPARC_DISP8 4 R_ARM_TLS_GD32 104 R_MICROMIPS_TLS_LDM 163 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 533 SHT_MIPS_CONTENT 0x7000000c ET_DYN 3 R_SPARC_GOT10 13 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC 548 ELF32_R_TYPE(val) ((val) & 0xff) R_PPC64_ADDR16_HIGHERA 40 R_PARISC_SECREL64 104 MIPS_AFL_ASE_SMARTMIPS 0x00000080 R_OR1K_16 2 R_MN10300_SYM_DIFF 33 R_SH_GLOB_DAT 163 R_TILEPRO_IMM16_X0_TLS_IE_HA 80 R_386_TLS_DTPOFF32 36 STB_GNU_UNIQUE 10 R_ARM_TLS_LDM32 105 PF_ARM_PI 0x20000000 R_IA64_GPREL32LSB 0x2d R_MIPS_GOT_PAGE 20 R_PPC_ADDR14 7 R_TILEGX_IMM8_X1_TLS_GD_ADD 114 EFA_PARISC_1_0 0x020b EF_SH2A_SH4 0x17 EF_MIPS_ABI_O64 0x00002000 EF_RISCV_FLOAT_ABI_DOUBLE 0x0004 R_PPC_PLT16_HA 31 DT_RISCV_VARIANT_CC (DT_LOPROC + 1) isupper(c) ((__ismask(c)&(_U)) != 0) R_CKCORE_ADDR32 1 R_SH_DIR8WPN 3 R_IA64_LTOFF22X 0x86 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 537 R_RISCV_RVC_LUI 46 SYMINFO_CURRENT 1 R_AC_SECTOFF_S9 0x26 SHN_COMMON 0xfff2 EM_TILE64 187 SHF_MIPS_NOSTRIP 0x08000000 R_CKCORE_PCREL_IMM16BY2 20 R_SPARC_TLS_IE_HI22 67 SHT_MIPS_REGINFO 0x70000006 R_390_GLOB_DAT 10 R_68K_TLS_DTPREL32 41 PT_HP_FASTBIND (PT_LOOS + 0x11) _ctype R_PPC64_DTPREL16 74 R_390_TLS_LDCALL 39 R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44 R_ARM_LDR_SB_G0 75 R_ARC_SDA16_LD 0x16 R_OR1K_TLS_LE_HI16 30 R_ARC_SDA_12 0x2D SHT_MIPS_XLATE_OLD 0x70000028 EM_MANIK 171 R_PPC64_TPREL16 69 R_TILEPRO_SHAMT_Y1 54 MIPS_AFL_EXT_OCTEON 5 R_SPARC_WDISP19 41 R_68K_16 2 R_AARCH64_CALL26 283 ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) R_SPARC_DISP32 6 R_LARCH_SOP_SR 34 DT_SYMINFO 0x6ffffeff DF_BIND_NOW 0x00000008 R_M32R_32 2 R_PPC64_GOT16_DS 58 R_TILEGX_TLS_IE_LOAD 117 R_ARM_ALU_SB_G2 74 SHN_PARISC_ANSI_COMMON 0xff00 R_IA64_SECREL64LSB 0x67 R_PPC64_DTPREL16_HIGH 114 R_SPARC_TLS_GD_HI22 56 R_AARCH64_TLSLD_ADR_PAGE21 518 EM_CR 103 R_ALPHA_TPREL64 38 R_MN10300_GOTOFF16 14 EF_CSKY_ABIMASK 0XF0000000 DF_1_DISPRELPND 0x00010000 EM_68K 4 R_OR1K_32 1 R_NDS32_TLS_TPOFF 102 EM_BA2 202 R_CKCORE_GOTOFF_LO16 29 R_PARISC_TPREL14DR 220 R_ARC_PC32 0x32 R_PARISC_TLS_DTPMOD64 243 EM_ETPU 178 R_LARCH_MARK_LA 20 MIPS_AFL_EXT_4100 9 DT_MIPS_CXX_FLAGS 0x70000022 R_AARCH64_TLSLE_LDST32_TPREL_LO12 556 R_SPARC_DISP64 46 DT_LOOS 0x6000000d R_MN10300_TLS_DTPOFF 31 R_MIPS16_GOT16 102 R_PPC64_PLT16_HA R_PPC_PLT16_HA NT_LOONGARCH_LASX 0xa03 EM_RL78 197 R_TILEGX_16 3 R_CKCORE_TLS_LDO32 55 R_TILEGX_IMM16_X1_HW1 39 NT_PPC_DSCR 0x105 R_METAG_GOTOFF 41 EF_MIPS_UCODE 16 ELFOSABI_OPENBSD 12 R_AARCH64_P32_JUMP_SLOT 182 R_OR1K_TLS_LDO_LO16 27 R_SPARC_NONE 0 R_ARC_TLS_GD_LD 0x46 NT_PRFPREG 2 R_TILEGX_BROFF_X1 20 R_TILEPRO_IMM16_X0_PCREL 31 R_MICROBLAZE_TLSLD 24 EM_STXP7X 166 PT_HP_CORE_MMF (PT_LOOS + 0x9) R_PPC_EMB_NADDR16_HA 105 EF_RISCV_FLOAT_ABI_QUAD 0x0006 DF_1_TRANS 0x00000200 R_TILEGX_IMM16_X0_HW0 36 R_386_TLS_IE_32 33 EM_MN10300 89 SHF_MIPS_GPREL 0x10000000 EM_SHARC 133 R_390_TLS_GOTIE64 44 R_PPC64_GOT_TLSLD16_HA 86 R_MIPS16_26 100 R_TILEGX_SHAMT_Y0 34 R_ALPHA_REFLONG 1 MIPS_AFL_EXT_4120 14 R_390_GOT16 15 PT_LOSUNW 0x6ffffffa SHT_MIPS_LOCSYM 0x70000015 RHF_QUICKSTART (1 << 0) ELFOSABI_IRIX 8 R_AARCH64_P32_RELATIVE 183 R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R EF_SH2E 0xb EF_ARM_LE8 0x00400000 ELFOSABI_HPUX 1 R_ARC_GOT32 0x3B R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 555 R_RISCV_TLS_GD_HI20 22 LITUSE_ALPHA_ADDR 0 EM_COREA_2ND 194 DT_HIOS 0x6ffff000 R_PARISC_TPREL16WF 222 R_68K_TLS_IE8 36 SHT_NOBITS 8 EF_SH3_NOMMU 0x14 ELF64_M_SYM(info) ELF32_M_SYM (info) kallsyms2elf_type SHT_GNU_verdef 0x6ffffffd R_SPARC_TLS_LDO_LOX10 65 R_ARM_LDRS_PC_G1 65 R_LARCH_SOP_POP_32_U_10_12 39 EF_SH4A 0xc R_LARCH_SOP_PUSH_DUP 24 MIPS_AFL_REG_128 0x03 R_LARCH_32_PCREL 99 R_AARCH64_ADR_PREL_PG_HI21_NC 276 R_TILEPRO_IMM16_X0_TLS_LE_LO 87 SHT_MIPS_DELTAINST 0x7000001c R_TILEGX_IMM8_X0_TLS_GD_ADD 113 EF_ARM_MAVERICK_FLOAT 0x800 GRP_COMDAT 0x1 SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) R_NIOS2_JUMP_SLOT 38 EM_ST200 100 R_X86_64_GOTPCRELX 41 AT_L2_CACHESHAPE 36 R_ARC_SDA16_LD2 0x18 R_MIPS_64 18 R_SPARC_TLS_LDO_HIX22 64 DT_AARCH64_VARIANT_PCS (DT_LOPROC + 5) R_PARISC_TPREL14WR 219 R_390_IRELATIVE 61 R_PARISC_LTOFF_TP14R 166 R_TILEGX_TLS_DTPMOD64 106 isdigit(c) __builtin_isdigit(c) R_MIPS_SCN_DISP 32 R_OR1K_COPY 18 R_68K_COPY 19 EF_SPARC_32PLUS 0x000100 EM_K10M 181 EF_ARM_ABI_FLOAT_SOFT 0x200 ELF32_M_INFO(sym,size) (((sym) << 8) + (unsigned char) (size)) R_386_TLS_GD_PUSH 25 AT_L1D_CACHEGEOMETRY 43 R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 99 EF_MIPS_ARCH_32 0x50000000 R_MN10300_8 3 R_PPC64_TPREL16_DS 95 R_NIOS2_GLOB_DAT 37 EI_PAD 9 PT_GNU_STACK 0x6474e551 DT_GNU_LIBLIST 0x6ffffef9 PF_HP_LAZYSWAP 0x04000000 R_ARM_GNU_VTINHERIT 101 R_390_PLT16DBL 18 R_PARISC_LTOFF_FPTR16WF 126 R_386_IRELATIVE 42 R_TILEPRO_IMM16_X0_HA_PCREL 37 isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) R_MN10300_PCREL16 5 R_CRIS_JUMP_SLOT 11 _C 0x08 R_386_TLS_DTPMOD32 35 DF_1_NOCOMMON 0x40000000 R_LARCH_SOP_IF_ELSE 37 DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) R_MICROMIPS_PC7_S1 139 R_AARCH64_MOVW_UABS_G2 267 NT_ARM_PAC_MASK 0x406 R_LARCH_TLS_IE_PC_HI20 87 R_NIOS2_GOTOFF 40 R_MICROMIPS_CALL16 142 R_ARC_16 0x2 R_ALPHA_GPREL32 3 ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) R_MIPS_TLS_TPREL_HI16 49 R_SPARC_WDISP30 7 SYMINFO_BT_LOWRESERVE 0xff00 EF_ARM_PIC 0x20 SHF_TLS (1 << 10) EM_TI_ARP32 143 VER_FLG_WEAK 0x2 DF_1_NODUMP 0x00001000 R_PPC64_JMP_IREL 247 R_386_TLS_GD_POP 27 R_LARCH_TLS_LE64_HI12 86 SHF_GROUP (1 << 9) R_PARISC_TLS_LDO14R 241 R_LARCH_SUB_ULEB128 108 R_PARISC_PCREL22F 74 R_390_TLS_LDO64 53 EM_TI_PRU 144 R_IA64_SEGREL32MSB 0x5c R_METAG_GNU_VTINHERIT 30 MIPS_AFL_EXT_LOONGSON_3A 4 R_MIPS_GNU_REL16_S2 250 DT_DEPAUDIT 0x6ffffefb R_PPC64_DTPREL16_LO 75 SHF_PARISC_HUGE 0x40000000 AT_IGNOREPPC 22 R_AARCH64_LD_PREL_LO19 273 EM_MSP430 105 R_386_TLS_GD 18 DT_RELENT 19 R_SPARC_GOTDATA_LOX10 81 STO_MIPS_INTERNAL 0x1 R_LARCH_GOT64_HI12 82 R_ARM_PLT32_ABS 94 R_PARISC_LTOFF_FPTR14WR 123 R_SH_GNU_VTENTRY 35 R_AARCH64_P32_TLS_TPREL 186 R_NIOS2_TLS_LDO16 30 R_TILEGX_IMM8_Y0_TLS_ADD 120 SHT_GROUP 17 R_PARISC_LTOFF_TP64 224 R_ARM_GOTRELAX 99 R_SPARC_H34 85 R_ALPHA_GLOB_DAT 25 R_MN10300_JMP_SLOT 22 __tolower EF_MIPS_ARCH 0xf0000000 R_METAG_REL16 16 R_386_TLS_LDM_32 28 EM_EXCESS 111 R_RISCV_GNU_VTENTRY 42 R_SPARC_GOTDATA_HIX22 80 R_PPC_GOT16_HA 17 R_PPC_UADDR32 24 R_MICROBLAZE_TLSGOTTPREL32 28 EF_LARCH_ABI_MODIFIER_MASK 0x07 ELF_NOTE_OS_LINUX 0 R_X86_64_32S 11 R_LARCH_TLS_DESC_PC_LO12 112 R_68K_PLT16 14 DF_1_WEAKFILTER 0x20000000 R_LARCH_DELETE 101 R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 NT_LWPSTATUS 16 R_AARCH64_TLSLE_LDST128_TPREL_LO12 570 ELFMAG0 0x7f R_METAG_REG32OP1 6 R_ARM_THM_MOVT_PREL 50 R_PPC_EMB_RELST_HA 114 EF_MIPS_MACH_5900 0x00920000 R_RISCV_HI20 26 OHWA1_R4KEOP_CLEAN 0x00000002 R_MIPS_PC21_S2 60 R_MIPS_GOT_DISP 19 R_PPC_JMP_SLOT 21 EM_SCORE7 135 NT_ARM_ZA 0x40c R_ARC_B22_PCREL 0x6 EM_RH32 38 R_PPC64_UADDR32 R_PPC_UADDR32 R_ARC_SDA_LDST1 0x14 R_MIPS_GOT_OFST 21 R_PARISC_DIR64 80 R_PPC_DIAB_SDA21_LO 180 AT_L1D_CACHESHAPE 35 R_PPC64_TLSGD 107 R_TILEGX_IMM16_X1_HW2_LAST 49 R_68K_TLS_LE16 38 SHF_PARISC_SBP 0x80000000 R_MIPS16_GPREL 101 R_ARM_ALU_PC_G2 61 R_PPC_ADDR16 3 SHT_PARISC_EXT 0x70000000 ELFCLASSNUM 3 R_SH_GNU_VTINHERIT 34 R_SH_TLS_LDO_32 146 E_MIPS_ARCH_2 EF_MIPS_ARCH_2 R_TILEGX_TLS_GD_CALL 112 DT_INIT 12 R_METAG_TLS_LDO_HI16 49 R_TILEGX_MT_IMM14_X1 28 R_AARCH64_TLSLE_ADD_TPREL_LO12 550 R_SH_DIR8W 8 NT_LOONGARCH_LSX 0xa02 R_PPC64_SECTOFF R_PPC_SECTOFF EF_ARC_MACH_MSK 0x000000ff DT_PPC64_OPD (DT_LOPROC + 1) R_PPC64_TOC16_DS 63 SHF_ALPHA_GPREL 0x10000000 EM_S370 9 SHT_MIPS_OPTIONS 0x7000000d R_386_PLT32 4 OEX_DISMISS 0x80000 R_386_TLS_IE 15 R_TILEPRO_IMM16_X0_TLS_GD 66 R_RISCV_CALL 18 EM_LOONGARCH 258 first_read DT_TLSDESC_PLT 0x6ffffef6 R_AARCH64_TLSLD_ADD_DTPREL_LO12 529 R_SH_COPY 162 R_TILEGX_IMM16_X1_HW0_TLS_IE 93 NT_S390_GS_CB 0x30b R_LARCH_TLS_IE64_HI12 94 R_PPC64_TOC 51 R_ALPHA_JMP_SLOT 26 R_PPC64_TPREL16_HIGHA 113 E_MIPS_ARCH_4 EF_MIPS_ARCH_4 R_390_PLT64 25 SHT_MIPS_TRANSLATE 0x70000022 AT_FLAGS 8 R_LARCH_SOP_NOT 31 R_NIOS2_RELATIVE 39 R_PPC_GOT_TLSLD16_LO 84 R_ARM_SBREL32 9 R_LARCH_PCALA_LO12 72 R_MIPS_TLS_TPREL_LO16 50 SHT_DYNSYM 11 NT_RISCV_CSR 0x900 R_TILEPRO_MMEND_X1 50 R_MIPS16_TLS_GD 106 GNU_PROPERTY_UINT32_OR_HI 0xb000ffff R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 R_ALPHA_BRADDR 7 ODK_FILL 5 R_IA64_LTOFF_DTPMOD22 0xaa R_TILEPRO_IMM16_X1_TLS_GD_HI 71 R_PARISC_DIR17F 4 R_PPC_PLTREL24 18 R_PARISC_TPREL16DF 223 R_METAG_HIOG 13 EM_386 3 EM_DXP 112 R_390_GOT32 7 DF_1_DISPRELDNE 0x00008000 R_IA64_GPREL22 0x2a R_TILEPRO_IMM16_X1_TLS_IE_HA 81 ET_NUM 5 R_AARCH64_MOVW_GOTOFF_G1 302 ELF_NOTE_PAGESIZE_HINT 1 AT_PAGESZ 6 R_MICROBLAZE_TLSDTPREL32 26 NT_S390_LAST_BREAK 0x306 SHT_MIPS_ABIFLAGS 0x7000002a R_SPARC_RELATIVE 22 AT_UID 11 DT_IA_64_NUM 1 R_ARM_PC24 1 SHT_MIPS_PACKSYM 0x70000008 GNU_PROPERTY_X86_ISA_1_V2 (1U << 1) SYMINFO_FLG_LAZYLOAD 0x0008 R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 SHT_MIPS_OPTSYM 0x70000017 R_RISCV_SUB8 37 DT_MIPS_CONFLICT 0x70000008 ELF32_R_SYM(val) ((val) >> 8) PT_HP_CORE_VERSION (PT_LOOS + 0x2) PT_LOOS 0x60000000 SHF_MIPS_NODUPE 0x01000000 R_SH_TLS_LE_32 148 R_PARISC_PCREL14WR 75 R_NIOS2_GNU_VTINHERIT 16 PT_LOPROC 0x70000000 EF_MIPS_NOREORDER 1 R_TILEPRO_IMM16_X0_TLS_GD_LO 68 R_CKCORE_GOT_LO16 32 EM_COGE 216 R_NIOS2_BFD_RELOC_8 14 R_CKCORE_PLT_LO16 35 R_TILEGX_TLS_DTPOFF32 110 EI_OSABI 7 DT_X86_64_PLTENT (DT_LOPROC + 3) DF_1_ENDFILTEE 0x00004000 VER_NDX_LORESERVE 0xff00 SHN_LOPROC 0xff00 DF_1_NODEFLIB 0x00000800 R_PARISC_TLS_LDO21L 240 ET_HIOS 0xfeff R_ARM_GOT32 26 R_ARM_GLOB_DAT 21 R_SH_RELATIVE 165 R_PPC_DTPMOD32 68 LITUSE_ALPHA_BYTOFF 2 R_CKCORE_RELATIVE 9 R_M32R_RELATIVE 53 ELF_NOTE_GNU "GNU" R_SPARC_GNU_VTINHERIT 250 R_390_TLS_LDM32 45 R_PARISC_LTOFF_FPTR64 120 R_ARM_LDC_SB_G2 83 R_NDS32_COPY 39 R_PARISC_LTOFF_FPTR16DF 127 R_CKCORE_TOFFSET_LO16 41 DF_1_CONFALT 0x00002000 isalpha(c) ((__ismask(c)&(_U|_L)) != 0) R_386_SIZE32 38 R_TILEPRO_TLS_DTPOFF32 83 R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 R_68K_PLT8O 18 ET_LOOS 0xfe00 R_PARISC_PLTOFF16WF 118 R_AARCH64_MOVW_SABS_G2 272 ET_HIPROC 0xffff SHN_LOOS 0xff20 DT_SYMTAB 6 R_CKCORE_PCREL_IMM18BY2 43 R_LARCH_ADD64 51 R_MIPS_PC19_S2 63 NT_PPC_TM_CGPR 0x108 NT_LOONGARCH_CSR 0xa01 PT_HP_CORE_STACK (PT_LOOS + 0x7) R_ARC_W 0x1A R_390_TLS_GOTIE32 43 PT_HP_STACK (PT_LOOS + 0x14) R_X86_64_PC64 24 R_390_TLS_GDCALL 38 DF_1_NOHDR 0x00100000 R_390_PC16DBL 17 R_OR1K_GOTOFF_LO16 17 GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0) EM_CSKY 252 R_LARCH_SOP_PUSH_TLS_GD 28 R_MIPS_NONE 0 SHT_ALPHA_REGINFO 0x70000002 R_ARM_REL32 3 R_390_TLS_IE64 48 R_390_TLS_GOTIE20 60 R_SPARC_GOT13 14 R_TILEPRO_NUM 130 R_ARC_RELATIVE 0x38 EF_MIPS_MACH_GS464 0x00A20000 R_ARC_SECTOFF_ME 0x1D R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 R_ARC_SDA16_ST2 0x30 R_AARCH64_TLSDESC_LDR 567 SYMINFO_NUM 2 R_MIPS16_TLS_DTPREL_LO16 109 DT_X86_64_PLTSZ (DT_LOPROC + 1) PT_MIPS_ABIFLAGS 0x70000003 R_ARM_NUM 256 STO_PPC64_LOCAL_MASK (7 << STO_PPC64_LOCAL_BIT) __STDC_VERSION__ 201112L R_SPARC_7 43 R_ARM_THM_JUMP19 51 R_PARISC_LTOFF_FPTR16F 125 EF_ARM_BE8 0x00800000 DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) R_PARISC_LTOFF_FPTR14DR 124 R_SPARC_UA16 55 R_PPC64_DTPREL16_HI 76 DT_MIPS_PERF_SUFFIX 0x7000002e EF_ARM_RELEXEC 0x01 R_390_PLTOFF16 34 R_MICROMIPS_PC10_S1 140 R_IA64_TPREL22 0x92 R_LARCH_SUB6 106 R_ARC_SDA_LDST2 0x15 R_IA64_DIR32MSB 0x24 R_IA64_GPREL64I 0x2b EM_MIPS_X 51 STT_HP_STUB (STT_LOOS + 0x2) R_NIOS2_CJMP 19 R_X86_64_GLOB_DAT 6 R_AARCH64_MOVW_SABS_G0 270 R_PPC64_TLS 67 EM_KVARC 214 R_LARCH_TLS_DTPREL32 8 EM_EMX8 213 R_390_GOTPC 14 EF_SPARC_LEDATA 0x800000 EM_COREA_1ST 193 R_SPARC_GLOB_JMP 42 isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) STO_RISCV_VARIANT_CC 0x80 NT_PPC_HASHKEYR 0x112 R_ARM_MOVT_ABS 44 ELF_NOTE_OS_SOLARIS2 2 ELFMAG2 'L' RHF_DELTA_C_PLUS_PLUS (1 << 6) R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 95 EM_860 7 DT_FLAGS 30 ELFOSABI_ARM_AEABI 64 EF_LARCH_OBJABI_V1 0x40 R_MICROMIPS_GPREL7_S2 172 R_AARCH64_MOVW_GOTOFF_G2 304 R_SPARC_PC_HM10 38 SYMINFO_FLG_COPY 0x0004 EM_RISCV 243 DT_MIPS_BASE_ADDRESS 0x70000006 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC 551 R_PPC64_ADDR16_HIGHA 111 SYMINFO_BT_PARENT 0xfffe R_NIOS2_BFD_RELOC_16 13 R_SPARC_13 11 R_PARISC_NONE 0 R_CKCORE_ADDR_HI16 24 R_CRIS_GNU_VTENTRY 8 R_68K_PLT16O 17 R_TILEGX_IMM8_Y0 24 R_PPC64_DTPREL16_HIGHER 103 DF_1_KMOD 0x10000000 R_MIPS_SHIFT6 17 R_TILEPRO_IMM16_X0_GOT_LO 41 NT_PPC_TM_SPR 0x10c DF_TEXTREL 0x00000004 R_TILEGX_MMEND_X0 31 DT_TEXTREL 22 R_LARCH_TLS_DESC_LD 119 EM_ME16 59 R_NDS32_NONE 0 EF_MIPS_ARCH_64R2 0x80000000 DT_MIPS_SYMBOL_LIB 0x70000024 R_ALPHA_DTPRELHI 34 R_NIOS2_CACHE_OPX 6 R_68K_PLT32O 16 R_MICROBLAZE_32 1 R_RISCV_GPREL_S 48 R_METAG_TLS_LDM 48 R_IA64_NONE 0x00 DT_AARCH64_BTI_PLT (DT_LOPROC + 1) R_TILEGX_MF_IMM14_X1 29 EF_SH4A_NOFPU 0x11 R_MICROMIPS_26_S1 133 SHN_LORESERVE 0xff00 DT_MIPS_DELTA_CLASS 0x70000017 R_AARCH64_ABS64 257 R_SPARC_32 3 R_PPC_GOT_TLSLD16 83 R_AARCH64_TLSGD_MOVW_G1 515 NT_TASKSTRUCT 4 R_LARCH_MARK_PCREL 21 AT_IGNORE 1 R_AARCH64_MOVW_GOTOFF_G0_NC 301 EF_S390_HIGH_GPRS 0x00000001 R_AARCH64_MOVW_UABS_G1_NC 266 VER_NDX_LOCAL 0 NT_PRFPXREG 20 R_IA64_LDXMOV 0x87 EM_FAKE_ALPHA 41 R_TILEPRO_MMSTART_X1 49 R_CKCORE_GOTPC 14 R_SPARC_WPLT30 18 R_X86_64_RELATIVE 8 ELFCLASS64 2 PT_HIOS 0x6fffffff SYMINFO_FLG_PASSTHRU 0x0002 R_SH_USES 27 R_PPC_EMB_SDA2I16 107 R_MIPS_INSERT_A 25 R_PPC_GOT_TLSLD16_HI 85 R_MN10300_32 1 R_CRIS_8_PCREL 4 EF_SH_MACH_MASK 0x1f DF_1_GROUP 0x00000004 EM_CE 119 EM_D30V 86 R_68K_PC16 5 R_ARM_THM_SWI8 14 ELF32_ST_INFO(bind,type) (((bind) << 4) + ((type) & 0xf)) EM_BLACKFIN 106 R_ARM_GOT_BREL12 97 R_ARM_ABS8 8 R_ARC_32_ME 0x1B R_METAG_REG32OP3 8 R_PPC64_DTPREL16_HIGHA 115 R_TILEPRO_TLS_DTPMOD32 82 EM_VISIUM 221 EM_H8_300 46 R_ARM_TLS_CALL 91 PT_SUNWSTACK 0x6ffffffb DT_PPC64_NUM 4 R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 557 SHN_AFTER 0xff01 EM_RS08 132 R_IA64_PCREL64LSB 0x4f ELF32_R_INFO(sym,type) (((sym) << 8) + ((type) & 0xff)) SHT_RELR 19 DTF_1_CONFEXP 0x00000002 DT_RPATH 15 DT_RELASZ 8 R_PPC64_GOT_TPREL16_LO_DS 88 R_LARCH_GOT64_PC_HI12 78 R_PPC64_ADDR24 R_PPC_ADDR24 R_TILEGX_IMM16_X0_HW0_TLS_IE 92 R_IA64_REL64LSB 0x6f R_ARC_SDA32_ME 0x1E R_NIOS2_BFD_RELOC_32 12 R_390_TLS_LOAD 37 R_X86_64_SIZE32 32 R_SPARC_PC_HH22 37 ELF64_M_INFO(sym,size) ELF32_M_INFO (sym, size) R_TILEGX_MMSTART_X0 30 _S 0x20 R_PARISC_PCREL16DF 79 EM_CR16 177 SHT_MIPS_RFDESC 0x7000001a R_PARISC_GPREL14WR 91 R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 R_MIPS_TLS_LDM 43 DT_MIPS_MSYM 0x70000007 R_TILEGX_IMM16_X0_HW3 42 R_PARISC_GNU_VTENTRY 232 R_68K_TLS_GD16 26 R_PPC_SECTOFF_HA 36 R_AARCH64_TLSGD_ADR_PAGE21 513 R_RISCV_TLS_TPREL32 10 STT_HP_OPAQUE (STT_LOOS + 0x1) R_PPC_TLSLD 96 R_PPC64_GOT_DTPREL16_DS 91 AT_PHENT 4 R_IA64_IMM22 0x22 ELFOSABI_SYSV 0 R_PARISC_PCREL32 9 R_AARCH64_TLS_TPREL 1030 R_CKCORE_GOT12 30 R_PPC64_PLTGOT16_DS 65 PT_GNU_SFRAME 0x6474e554 R_METAG_HI16_GOTPC 36 EF_SH4AL_DSP 0x6 DT_MIPS_HIDDEN_GOTIDX 0x70000027 PF_HP_MODIFY 0x02000000 R_MIPS16_TLS_GOTTPREL 110 R_LARCH_GNU_VTINHERIT 57 R_PARISC_LTOFF_TP14F 167 R_TILEGX_HW1 10 R_SPARC_REV32 252 R_X86_64_TLSLD 20 R_TILEPRO_TLS_IE_LOAD 65 R_PPC_GOT_TLSGD16_LO 80 R_IA64_LTOFF64I 0x33 R_ARM_JUMP24 29 DT_STRSZ 10 R_PPC64_GLOB_DAT R_PPC_GLOB_DAT R_AARCH64_P32_TLSDESC 187 R_SH_TLS_TPOFF32 151 R_AARCH64_P32_ABS32 1 R_ARC_SDA_LDST 0x13 R_MN10300_TLS_GD 24 R_LARCH_ADD24 49 STB_NUM 3 R_PPC_GOT_DTPREL16_HA 94 R_AARCH64_TLSLD_MOVW_DTPREL_G0 526 R_PPC64_PLTGOT16_HI 54 R_TILEGX_SHAMT_X1 33 R_ARC_8 0x1 R_PPC64_NONE R_PPC_NONE STT_HIOS 12 EF_MIPS_MACH_4010 0x00820000 R_MICROBLAZE_32_PCREL_LO 4 R_LARCH_ABS64_LO20 69 R_IA64_IPLTMSB 0x80 R_RISCV_32_PCREL 57 EF_MIPS_NAN2008 1024 R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 R_AARCH64_ADR_GOT_PAGE 311 R_PPC64_TPREL16_HIGHEST 99 NT_LWPSINFO 17 R_PPC_EMB_BIT_FLD 115 EM_JAVELIN 77 R_TILEGX_IMM8_Y1_TLS_ADD 121 R_MN10300_GOT24 18 AT_SYSINFO_EHDR 33 R_IA64_PCREL21BI 0x79 R_386_PC32 2 SHT_NUM 20 R_PPC_REL32 26 R_OR1K_GOTPC_LO16 13 R_386_TLS_GOTIE 16 R_PARISC_SEGREL64 112 R_M32R_LO16_RELA 41 R_NIOS2_IMM5 5 R_CKCORE_PLT32 16 R_PARISC_LTOFF_FPTR14R 62 SHT_MIPS_RELD 0x70000009 R_TILEGX_TLS_DTPOFF64 107 R_NDS32_RELATIVE 42 R_METAG_RELATIVE 45 OHW_R5KCVTL 0x8 GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002 NT_ARM_PAC_ENABLED_KEYS 0x40a AT_HWCAP3 29 DTF_1_PARINIT 0x00000001 R_ALPHA_TLSGD 29 R_ARM_THM_PC12 54 R_PARISC_PLTOFF14DR 116 R_NIOS2_CALL_LO 44 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 540 SHF_MERGE (1 << 4) NT_S390_CTRS 0x304 process_symbol R_SH_DIR32 1 R_OR1K_TLS_LDO_HI16 26 R_M32R_24_RELA 35 DT_MOVETAB 0x6ffffefe R_LARCH_TLS_GD_HI20 98 R_ARM_GOT_PREL 96 R_AARCH64_LD64_GOTOFF_LO15 310 R_M32R_16 1 SHT_PROGBITS 1 R_MN10300_TLS_DTPMOD 30 SHT_IA_64_UNWIND (SHT_LOPROC + 1) R_OR1K_8 3 NT_MIPS_FP_MODE 0x801 R_TILEPRO_IMM16_X0_TLS_IE 74 SHN_MIPS_SCOMMON 0xff03 R_OR1K_GNU_VTINHERIT 8 R_ARC_32 0x4 GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0) EM_MOXIE 223 R_ARC_TLS_IE_GOT 0x48 R_SPARC_TLS_LE_LOX10 73 GNU_PROPERTY_UINT32_OR_LO 0xb0008000 R_390_GOTOFF16 27 R_ARC_SECTOFF 0xD DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 SHT_PARISC_UNWIND 0x70000001 R_SPARC_SIZE32 86 STB_LOPROC 13 EF_MIPS_MACH_4120 0x00870000 R_LARCH_TLS_DESC64_LO20 117 R_ARC_N32_ME 0x1C R_68K_TLS_LDM32 28 R_TILEPRO_IMM16_X1_HA_PCREL 38 R_X86_64_8 14 R_TILEGX_IMM16_X0_HW1_PCREL 52 R_SH_GOT32 160 R_MN10300_TLS_IE 28 R_ALPHA_LITERAL 4 R_PARISC_PCREL16WF 78 DT_AARCH64_NUM 6 PT_SUNWBSS 0x6ffffffa R_PARISC_DIR21L 2 EM_CYPRESS_M8C 161 EF_SPARC_SUN_US3 0x000800 R_PARISC_FPTR64 64 R_SPARC_TLS_LE_HIX22 72 R_ALPHA_GOTDTPREL 32 ELF_NOTE_FDO "FDO" EM_MCST_ELBRUS 175 R_MICROBLAZE_REL 16 GNU C11 14.2.0 -mtune=generic -march=x86-64 -ggdb3 -std=gnu11 -fPIC -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection DF_1_NOKSYMS 0x00080000 R_PARISC_PLTOFF14WR 115 R_MIPS_PCHI16 64 R_TILEGX_IMM16_X0_HW3_PCREL 56 EF_SH1 0x1 R_TILEPRO_SHAMT_X1 52 R_TILEPRO_16 2 R_MICROBLAZE_PLT_64 15 DF_1_STUB 0x04000000 R_TILEGX_HW0_LAST 13 R_ARM_LDRS_SB_G0 78 NT_S390_TODPREG 0x303 R_TILEPRO_IMM16_X1_GOT_HI 44 R_PPC64_ADDR16_LO R_PPC_ADDR16_LO R_LARCH_SOP_PUSH_GPREL 25 R_LARCH_SUB64 56 NT_S390_VXRS_HIGH 0x30a RHF_NONE 0 R_SPARC_10 30 R_X86_64_16 12 R_LARCH_COPY 4 R_AARCH64_TLSLE_MOVW_TPREL_G0 547 DT_NEEDED 1 SHF_MASKOS 0x0ff00000 NT_ARM_VFP 0x400 MIPS_AFL_ASE_MDMX 0x00000010 EM_NDR1 57 test_workload sighandler workload_fnptr leaf alarm GNU C11 14.2.0 -mtune=generic -march=x86-64 -g -O6 -O0 -std=gnu11 -fstack-protector-all -fPIC -fno-inline -fno-omit-frame-pointer -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection __sig_atomic_t workload__leafloop GNU C11 14.2.0 -mtune=generic -march=x86-64 -g -O6 -O0 -std=gnu11 -fno-omit-frame-pointer -fstack-protector-all -fPIC -fno-inline -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection workload__sqrtloop sqrt rand brstack_foo_ind brstack_bar brstack_foo brstack_bench workload__brstack num_loops buf1 data1 data2 workload__datasym metric_only_len TEP_FIELD_IS_ARRAY display_time is_kthread __writers_futex PERF_BR_ERET no_buffering __ru_inblock_word AGGR_NODE HISTC_ADDR user_freq metric_only readonly pyrf_evlist max_runtime_end lenfunc ru_nivcsw exit_code cmd_inject __ru_nswap_word pyrf_cpu_map__setup_types force mmap_flush tep_print_arg_func tp_getattr pevent pyrf_cpu_map sq_item threads_user_spec nb_add sample_phys_addr pyrf_evlist__mmap nr_hybrid_nodes PERF_BR_EXTEND_ABI ob_refcnt PyCFunction sq_ass_item pyrf_evlist__init pyrf_throttle_event__doc sq_inplace_repeat tp_as_async nb_matrix_multiply m_methods nr_events_printed sq_inplace_concat tp_is_gc TEP_PRINT_INT_ARRAY use_bpf nb_power IS_ERR ignore PERF_BR_NEW_FAULT_INST KWORK_REPORT_TIMEHIST tep_print_flag_sym PERF_COUNT_HW_CACHE_ITLB PERF_BR_SERROR sample_code_page_size nr_unknown_id pyrf_evlist__open mem_free perf_user_event_type work_init sq_repeat aio_offset atom_page_list pyrf_sample_event__doc sq_concat pyrf_sample_event__repr pyrf_cpu_map__length wait_time_max tp_itemsize tp_doc ctl_fd_close __abs_prio HISTC_MEM_SNOOP initproc tep_record PyGetSetDef cpumode tp_bases PERF_COUNT_HW_CPU_CYCLES pyrf_event__type event_list_str aio_nbytes run_count exit_reasons_table decode full_auxtrace hist_column PERF_SAMPLE_TRANSACTION clockid_ns PERF_RECORD_SAMPLE pyrf_comm_event__repr ru_stats cluster tep_read_number setattrofunc PERF_COUNT_HW_STALLED_CYCLES_BACKEND per_pkg PERF_RECORD_LOST_SAMPLES pyrf_throttle_event__type __rb_parent_color PERF_COUNT_HW_MAX PERF_SAMPLE_BRANCH_ANY_SHIFT ru_isrss PERF_TOOL_DURATION_TIME PERF_TOOL_MAX PERF_SAMPLE_CPU nb_inplace_lshift pthread_t arch_syscalls__strerrno_t sample_address cache_mask perf_kvm_stat avg_wait_time arch_strerrno HISTC_TRANSACTION PERF_COUNT_SW_CGROUP_SWITCHES line_size regs_dump ru_msgrcv nr_memory_nodes PERF_SAMPLE_ID getiterfunc HISTC_MEM_LOCKED arch_syscalls__strerrno_function pyrf_read_event__type HISTC_MEM_DCACHELINE nb_floor_divide PERF_SAMPLE_IP aio_lio_opcode PyExc_OSError pyrf__tracepoint perf__methods socket_id evlist__event2evsel comp_mmap_len needs_swap arraylen PERF_COUNT_SW_TASK_CLOCK os_release cgroups is_begin_event pyrf_context_switch_event__doc new_refcnt PyVarObject kernel_callchains tp_richcompare rblist binding PyType_Ready PERF_SAMPLE_CALLCHAIN skippable PERF_COUNT_HW_CACHE_RESULT_ACCESS tp_descr_set needs_auxtrace_mmap iostat_run abort ref_count nb_remainder clockid_res_ns pyrf_cpu_map__delete sample_transaction visitproc strict_freq pyrf_throttle_event__members PyModule_Create2 uid_str total_mem rb_root_cached p_stage_cyc max_branches class_init TEP_FIELD_IS_RELATIVE sched_switch_event BKW_MMAP_EMPTY callstack PERF_RECORD_ITRACE_START softirq pyrf_throttle_event__repr no_aux_samples PERF_SAMPLE_READ TEP_PRINT_SYMBOL trace_event__tp_format_id was_sq_slice ways tep_event_handler_func nr_fields pyrf_event PyMemberDef HISTC_IN_TX AGGR_NONE aggr_get_id cur_refcnt ob_type is_printable_array cpu_desc perf_counts PERF_RECORD_NAMESPACES nr_unknown_events sample_weight PERF_AUXTRACE_ERROR_ITRACE HISTC_MEM_IADDR_SYMBOL walltime_nsecs_stats nbits nr_proc_map_timeout scripts_path_array getter HISTC_COMM PyModuleDef tp_traverse perf_time_interval unit_width ru_data KWORK_TRACE_ENTRY sample_read tep_print_fmt total_aux_lost getattrofunc all_user PyErr_Format aio_fildes nb_and bpf_str PERF_SAMPLE_BRANCH_MAX_SHIFT perf_branch_sample_type_shift HISTC_MEM_BLOCKED pyrf_sample_event__getattro script_fetch_insn PERF_RECORD_FINISHED_INIT PERF_RECORD_HEADER_MAX prev_raw_counts PERF_RECORD_STAT_CONFIG nr_lost_warned snapshot scripting_ops record_opts pyrf_read_event__members hash_entry machine tp_str PERF_SAMPLE_BRANCH_NO_TX_SHIFT PERF_SAMPLE_PERIOD HISTC_TYPE_OFFSET wait_time_min was_sq_ass_slice tep_print_arg_dynarray PERF_BR_IND mean TEP_FIELD_IS_SIGNED nr_numa_nodes ob_base PyTypeObject PERF_SAMPLE_BRANCH_HV_SHIFT tp_alloc kwork_trace_type tracking TEP_PRINT_BITMASK pyrf_read_event__repr raw_size pevsel sq_contains pthread_rwlock_t readpos total_aux_partial pyrf_cpu_map__doc PERF_RECORD_LOST sorted_work_root PERF_BR_UNKNOWN HISTC_MEM_DATA_PAGE_SIZE PERF_TYPE_SOFTWARE all_kernel TEP_PRINT_TYPE ZSTD_CCtx_s tp_setattr PERF_SAMPLE_CODE_PAGE_SIZE PyArg_ParseTupleAndKeywords tp_mro HISTC_SYMBOL_OFFSET errored pyrf_lost_event__type HISTC_SRCLINE_FROM TEP_PRINT_HEX_STR synth mp_ass_subscript sample_identifier TEP_FIELD_IS_FLAG pyrf_thread_map__sequence_methods PERF_RECORD_HEADER_EVENT_TYPE __uint32_t cgroup_list ZSTD_DCtx intlist PERF_COUNT_SW_CPU_MIGRATIONS uses_mmap tp_dictoffset pyrf_cpu_map__type PERF_TYPE_HARDWARE tep_print_arg_string setter work_name PyNumberMethods HISTC_MISPREDICT PyMethodDef tp_finalize aio_buf tp_watched infos_cnt PERF_TOOL_SYSTEM_TIME aiocb tep_print_arg_typecast tp_getset sq_length max_latency tod_ns start_time PERF_COUNT_SW_BPF_OUTPUT tp_clear cpu_aggr_map Py_INCREF get_md BKW_MMAP_RUNNING PERF_BR_MAX class_list __ru_maxrss_word sigev_value br_cntr_nr PERF_BR_IRQ script_spec_register auxtrace_snapshot_on_exit nr_pmu_mappings report_event rb_leftmost cache_lvl HISTC_ADDR_FROM PERF_RECORD_SWITCH_CPU_WIDE pyrf_task_event__type perf_hw_cache_op_id PERF_RECORD_SWITCH PyModuleDef_Base PyUnicode_FromString pyrf_cpu_map__item PERF_BR_UNCOND no_samples HISTC_MEM_TLB HISTC_ABORT nb_bool perf_sample PERF_RECORD_BPF_EVENT nb_inplace_true_divide userpg kwork_class AGGR_MAX __top_cpus_runtime missed_events predicted duration tp_init cstream HISTC_SYMBOL_TO PYGEN_RETURN ob_size KWORK_CLASS_SOFTIRQ nr_auxtrace_errors tp_dict moduledef walltime_run_table tp_as_mapping kwargs setattrfunc PERF_SAMPLE_RAW KWORK_REPORT_RUNTIME PERF_COUNT_HW_INSTRUCTIONS retire_lat walltime_run HISTC_SIMD pathlen ifunc_alias branch_entry process_stat child_event_ops addr_location timerfd auto_merge_stats PyList_New profile_name pyrf_evlist__read_on_cpu trace_seq_fail process_auxtrace_error binaryfunc group_name nr_contended nr_acquired TEP_PRINT_DYNAMIC_ARRAY_LEN hashmap PERF_COUNT_SW_DUMMY am_anext AGGR_CACHE PERF_COUNT_HW_CACHE_OP_MAX pyrf_evsel__type PERF_SAMPLE_WEIGHT m_doc tep_print_arg_type KWORK_CLASS_IRQ ndim affinity sort_list stack_dump vectorcallfunc clock btfs ru_minflt pyrf_lost_event__repr tree tgid _PyObject_New ssizeargfunc __cur_writer KWORK_CLASS_MAX max_runtime time_str PERF_SAMPLE_PHYS_ADDR scripts_array get_tracepoint_field descrsetfunc pyrf_thread_map__setup_types PERF_RECORD_FINISHED_ROUND Py_TYPE KWORK_CLASS_WORKQUEUE is_libpfm_event GNU C11 14.2.0 -mtune=generic -march=x86-64 -g -O2 -O6 -O6 -std=gnu11 -std=gnu11 -fno-strict-overflow -fstack-protector-all -fno-omit-frame-pointer -fstack-protector-all -fPIC -fno-strict-aliasing -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection affinity_mask lock_stat_find aio_reqprio PERF_BR_NEW_ARCH_2 flush_script PERF_RECORD_KSYMBOL PERF_RECORD_HEADER_ATTR PERF_COUNT_HW_CACHE_L1D pyrf_mmap_event__repr rb_right PERF_COUNT_HW_CACHE_L1I ru_utime nb_reserved metric_no_merge unaryfunc m_clear cpu_topology_map TEP_PRINT_DYNAMIC_ARRAY trace_event__tp_format auxtrace_mmap_pages bpf_obj PERF_RECORD_HEADER_FEATURE pyrf_lost_event__doc id_offset PERF_BR_NO_TX btfs_cnt db_id ZSTD_CStream common_fields use_stdio PERF_RECORD_EVENT_UPDATE TEP_PRINT_FUNC reprfunc tep_print_arg_int_array PERF_COUNT_HW_CACHE_RESULT_MISS PERF_COUNT_HW_BRANCH_MISSES stop_read_counter PERF_SAMPLE_WEIGHT_STRUCT pyrf_task_event__repr comp_type pthreads PERF_RECORD_READ nr_caps __sigval_t kwork_work nr_skipped_events loaded PERF_COUNT_HW_CACHE_OP_WRITE PERF_BR_COND_RET stop_script topdown_level PyList_Append PERF_COUNT_HW_REF_CPU_CYCLES cmp_id TEP_FIELD_IS_POINTER evsel__exit __error_code auxtrace_snapshot_opts getattrfunc kwork_class_type metric_events insn_len pyrf_task_event__doc objobjargproc process_throttle PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT pyrf_lost_event__members child_ops HISTC_SYMBOL_IPC process_stat_interval AGGR_SOCKET HISTC_ADDR_TO metric_no_threshold pyrf_mmap_event__members symbols config_terms PERF_RECORD_AUXTRACE_INFO get_key PyLong_FromLong Py_hash_t rb_root tep_print_arg_hex TEP_PRINT_ATOM nb_inplace_power perf_stat_aggr PyObject csv_sep nb_xor unthrottle nb_negative synth_sample_type perf_stat_evsel PERF_COUNT_SW_PAGE_FAULTS_MIN TEP_FIELD_IS_STRING pyrf_evsel__init pyrf_evlist__add slot PyByteArray_FromStringAndSize am_send ptype AGGR_UNSET __ru_ixrss_word max_runtime_start Py_ssize_t nr_lost_events live scripting_max_stack PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT csv_output percore_show_thread m_traverse nb_inplace_multiply PERF_TYPE_MAX uniquified_name PERF_COUNT_SW_EMULATION_FAULTS kwork_top_stat nb_inplace_add TEP_PRINT_OP allocfunc pcpus exit_reasons_isa pyrf_thread_map__init first_sample_time PyType_GenericNew perf_tool_event PERF_SAMPLE_BRANCH_USER_SHIFT nr_tracepoints perf_stat__set_no_csv_summary PERF_SAMPLE_BRANCH_KERNEL_SHIFT PERF_RECORD_CGROUP auxtrace_sample_mode HISTC_TYPE ml_flags tp_new __ru_nivcsw_word nr_trylock nr_sibling_threads m_name atom_list PERF_TYPE_HW_CACHE pid_list pyrf_cpu_map__sequence_methods metric_no_group nr_pmus_with_caps bpf_fd nr_threads_synthesize rusage PyModuleDef_Slot no_inherit_set tep_format_flags ordered_events memory_node perf_tool PERF_COUNT_SW_CPU_CLOCK ignore_missing_thread exit_event_end auxtrace_snapshot_size PERF_RECORD_TIME_CONV perf_kwork exit_event_decode_key all_cpus_bitmap branch_stack PERF_BR_CALL HISTC_MEM_DADDR_DSO timestart bperf_follower_bpf tp_del PERF_COUNT_HW_CACHE_OP_PREFETCH pyrf_evsel__setup_types PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT ru_inblock tep_format_field HISTC_GLOBAL_P_STAGE_CYC ru_ixrss event_oe pyrf_evlist__type infos HISTC_LOCAL_INS_LAT reset_group tp_name event_op _typeobject closure pyrf_context_switch_event__type pyrf_evlist__length max_events combined kernel_is_64_bit nr_acquire nr_cpus_avail tp_as_sequence tp_as_buffer pyrf_evlist__sequence_methods print_mixed_hw_group_error PERF_SAMPLE_ADDR is_end_event tep_print_arg_atom nb_index perf_hw_cache_id _sigev_thread system cpus_aggr_map nr_readlock running_time TEP_PRINT_FIELD use_config_name sample_time_set HISTC_SOCKET raise_event BKW_MMAP_NOTREADY PERF_BR_NEW_ARCH_1 pyrf_evlist__item PERF_BR_NEW_ARCH_3 PERF_BR_NEW_ARCH_4 PERF_BR_NEW_ARCH_5 HISTC_SRCLINE_TO record_size nr_sibling_dies hardware_aware_grouping HISTC_DSO_SIZE TEP_PRINT_FLAGS inlined suboffsets overwrite_mmap AGGR_DIE pyrf_evlist__poll HISTC_LOCAL_P_STAGE_CYC tep_print_arg_bitmask PYGEN_ERROR PyObject_GenericGetAttr nb_true_divide PERF_RECORD_EXIT comp_ratio _Py_IsImmortal pyrf_evlist__delete event_attr_op PERF_COUNT_HW_STALLED_CYCLES_FRONTEND HISTC_PARENT bperf_leader_link_fd sample_data_page_size thread_map__new is_tracepoint tep_field_is_relative cpu_bitmap tp_hash KWORK_REPORT_LATENCY tp_getattro pyrf_comm_event__members event_sample node_delete nr_sibling_cores node_new pyrf_mmap_event__doc m_copy BKW_MMAP_DATA_PENDING tp_methods module tp_handlers nb_inplace_and tep_print_arg_op immediate percore follower_skel ZSTD_DStream raw_data PyExc_ImportError KWORK_CLASS_SCHED total_lost_samples sigev_signo broken sample_cpu pyrf_evsel__doc PERF_RECORD_THROTTLE PERF_COUNT_SW_CONTEXT_SWITCHES bpf_progs kvm_entry_event dont_split_sample_group descrgetfunc SHOW_FEAT_HEADER_FULL_INFO pyrf_evlist__get_pollfd exit_event_begin group_data start_times nb_or perf_kwork_add_work tp_version_tag ctl_fd is_pos pyrf_context_switch_event__repr PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT tp_handler PERF_BR_SYSCALL nb_float forced_leader pevlist KWORK_TRACE_MAX PERF_BR_SYSRET perf_sw_ids kvm_exit_event PERF_RECORD_AUXTRACE_ERROR PERF_SAMPLE_TID PERF_AUXTRACE_ERROR_MAX PERF_RECORD_THREAD_MAP HISTC_SYM_SIZE pid_stat mem_total traverseproc HISTC_SYMBOL context events_stats free_list trace_event_sample_raw PERF_COUNT_HW_CACHE_DTLB tp_vectorcall_offset print_free_counters_hint __next_prio inquiry wait_time_total tp_call ip_callchain nb_invert ml_doc branch_flags TEP_FIELD_IS_LONG ml_name m_index node_cmp nb_inplace_or pyrf_evsel__delete Py_DECREF HISTC_TRACE exclude_GH sort_order tp_as_number cmdline_argv PERF_COUNT_HW_CACHE_MISSES PyAsyncMethods tp_weaklistoffset cluster_id namespace_events PERF_BR_NEW_MAX no_bpf_event KWORK_TRACE_EXIT PyDict_SetItemString ru_nvcsw sample_read_value _sigev_un ml_meth ins_lat TEP_PRINT_STRING perf_env PERF_SAMPLE_REGS_INTR cork_fd cgroup_events tp_basicsize PyUnicode_AsUTF8 HISTC_CGROUP_ID __ru_oublock_word tep_print_arg_symbol pyrf_evlist__setup_types event_key PERF_SAMPLE_STREAM_ID simd_flags show_feature_header trace_kwork_handler no_warn total_aux_collision exit_reasons pyrf_thread_map__length perf_pmu perf_session PySequenceMethods pyrf_mmap_event__type HISTC_MEM_LVL PERF_COUNT_SW_MAX mmap_cpu_mask PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT tp_weaklist caches total_runtime insn_cnt PERF_SAMPLE_REGS_USER TRACE_SEQ__BUFFER_POISONED newfunc PERF_COUNT_SW_PAGE_FAULTS_MAJ hashfunc precise_max lock_stat cpu_cache_level no_hw_idx perf_type_id metric_leader rusage_stats pyrf_read_event__doc nr_events perf_hw_cache_op_result_id annotate2 HISTC_CODE_PAGE_SIZE PyModule_AddObject sample_user_regs evsel__sb_cb_t PERF_COUNT_HW_BRANCH_INSTRUCTIONS richcmpfunc user_stack lock_stat_findnew nr_unprocessable_samples PyFile_FromFd rw_semaphore max_latency_start PyErr_NoMemory trace_vcpu shape PERF_BR_IND_CALL generate_script tp_setattro user_callchains __shared perf_event_sample_format __ru_nsignals_word max_latency_end event_op2 event_op3 event_op4 ssizeobjargproc perf_stat__set_big_num PERF_COUNT_HW_CACHE_MAX tp_vectorcall KWORK_REPORT_TOP tep_event show_feat_hdr bpf_skel __writers caches_cnt pyrf_thread_map__doc zstd_data total_count TEP_PRINT_HEX HISTC_MEM_DADDR_SYMBOL aux_sample nr_atoms bpf_counter_list AGGR_CLUSTER __pad1 __pad2 __pad3 __pad4 SHOW_FEAT_NO_HEADER __ru_msgsnd_word ru_stime sort_key PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT sample_intr_regs getbufferproc total_lost TEP_PRINT_NULL __ru_majflt_word threads_spec __ru_nvcsw_word PERF_SAMPLE_BRANCH_COUNTERS_SHIFT aggr_level rb_node kcore kvm_events_ops am_await HISTC_NR_COLS TEP_FIELD_IS_DYNAMIC PERF_SAMPLE_DATA_PAGE_SIZE trace_seq sendfunc __ru_minflt_word dstream tp_members pyrf_thread_map__delete PyErr_SetFromErrno PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT PyObject_Str mp_length SHOW_FEAT_HEADER KWORK_TRACE_RAISE ru_msgsnd ZSTD_CCtx rb_left perf_sample__sprintf_flags default_metricgroup __builtin_memcpy bpf_counter msr_pmu_type __clockid_t ZSTD_DCtx_s PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT mp_subscript pyrf_cpu_map__init am_aiter PyLong_FromUnsignedLong nb_inplace_xor merged_stat tp_subclasses tep_print_arg bperf_leader_bpf numa_node __rwelision hostname nr_common nr_cpus_online TRACE_SEQ__MEM_ALLOC_FAILED AGGR_GLOBAL freefunc PERF_RECORD_COMM srcline no_inherit raw_samples m_base tep_handle PERF_RECORD_STAT HISTC_DSO_TO HISTC_TIME PERF_BR_NEW_FAULT_ALGN AGGR_THREAD nr_lost_chunks HISTC_GLOBAL_WEIGHT tp_iternext PERF_RECORD_COMPRESSED tep_print_arg_flags __ru_msgrcv_word HISTC_SRCLINE PyModule_GetDict PERF_SAMPLE_BRANCH_COND_SHIFT nb_lshift evsel__parse_sample ordering_requires_timestamps ob_refcnt_split tp_descr_get all_runtime nr_cblocks PERF_BR_RET tp_iter elementsize socket nb_inplace_floor_divide show_callchain tep_function_handler HISTC_CYCLES auxtrace_error_type arch_sym PERF_RECORD_MAX bperf_leader_prog_fd aggr_mode strides tep_print_arg_field core_id pyrf_event__setup_types tp_base PERF_SAMPLE_MAX attr_map nb_rshift auxtrace_snapshot_mode br_cntr_width tep_format PERF_RECORD_HEADER_TRACING_DATA nr_cmdline die_id TEP_FIELD_IS_SYMBOLIC bf_releasebuffer __wrphase_futex ru_stime_usec_stat tep_find_any_field interval_clear releasebufferproc new_type tep_print_parse supported timeend PERF_COUNT_HW_CACHE_NODE PERF_BR_NEW_FAULT_DATA HISTC_LOCAL_WEIGHT nb_inplace_remainder PERF_RECORD_HEADER_BUILD_ID cmdline_group_boundary dirname pyrf_context_switch_event__members PySendResult PERF_RECORD_AUX_OUTPUT_HW_ID event_enable_timer HISTC_DSO thread_idx perf_stat_config default_per_cpu collect_stat ptime ru_nswap m_slots PERF_RECORD_CPU_MAP failed PERF_RECORD_MMAP2 user_requested_cpu_list cgrp nr_aggr comp_ver IS_ERR_OR_NULL nb_absolute PERF_COUNT_HW_BUS_CYCLES aggr_cpu_id pyrf_thread_map PyInit_perf perf_hw_id __return_value ru_idrss match_callstack_filter user_interval PERF_SAMPLE_STACK_USER cyc_cnt PERF_RECORD_USER_TYPE_START sigev_notify PERF_TOOL_NONE json_output pyrf_evsel__open PERF_COUNT_SW_PAGE_FAULTS m_init precise_ip_original cpustr PERF_COUNT_HW_CACHE_REFERENCES pthread_attr_t last_sample_time HISTC_SRCFILE branch_stack_cntr m_size record_switch_events print_cache PERF_TOOL_USER_TIME PERF_RECORD_UNTHROTTLE PERF_SAMPLE_BRANCH_IND_CALL_SHIFT kwork_report_type tp_repr buffer_size tp_cache __readers PERF_BR_COND_CALL PERF_RECORD_FORK ru_nsignals PERF_TYPE_TRACEPOINT per_pkg_mask bf_getbuffer PERF_BR_COND nb_inplace_rshift total_latency ru_oublock tp_dealloc data_src PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT perf__constants null_run bpf_filters pyrf_event__new PyArg_ParseTuple nb_positive process_event metric_id PERF_COUNT_HW_CACHE_RESULT_MAX el_size nr_invalid_chains _Py_Dealloc _Py_NoneStruct initial_delay bpf_object PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT __pthread_rwlock_arch_t record_switch_events_set PyMappingMethods HISTC_SYMBOL_FROM ru_majflt bkw_mmap_state perf_data_file PERF_COUNT_HW_CACHE_BPU ru_display default_interval PERF_SAMPLE_DATA_SRC pyrf_evsel__methods pyrf_evlist__doc PERF_RECORD_AUXTRACE group_pmu_name __ru_isrss_word hybrid_merge nr_cpu_pmu_caps bpf_counter_ops TEP_PRINT_BSTRING in_tx total_time HISTC_THREAD id_pos PERF_COUNT_HW_CACHE_OP_READ open_flags tp_flags nb_multiply PERF_RECORD_STAT_ROUND AGGR_CORE cpu_usage perf_event_type res_stats PERF_SAMPLE_BRANCH_CALL_SHIFT ru_maxrss nb_subtract PERF_RECORD_ID_INDEX HISTC_CPU tail_synthesize hybrid_node kwlist pyrf_task_event__members find_scripts PERF_RECORD_TEXT_POKE period_set PERF_SAMPLE_BRANCH_IN_TX_SHIFT total_invalid_chains ru_utime_usec_stat start_script PERF_TYPE_RAW evsel_str_handler PERF_RECORD_MMAP attr_name TEP_PRINT_CPUMASK cpuid nr_release finished_init HISTC_GLOBAL_INS_LAT auxtrace_sample_opts PyUnicode_FromFormat PERF_SAMPLE_CGROUP PERF_SAMPLE_TIME Py_BuildValue PyErr_SetString pyrf_sample_event__type weak_group aio_sigevent leader_skel pyrf_sample_event__members pyrf_comm_event__doc PERF_COUNT_HW_CACHE_LL selected HISTC_MEM_PHYS_DADDR __ru_idrss_word HISTC_CGROUP process_switch iternextfunc nb_int all_count side_band ternaryfunc HISTC_DSO_FROM PERF_TYPE_BREAKPOINT Py_buffer pyrf_thread_map__type TRACE_SEQ__GOOD PERF_SAMPLE_BRANCH_STACK pyrf_evlist__methods pyrf_evsel pyrf_thread_map__item ctl_fd_ack comp_level pyrf_comm_event__type PyErr_Occurred nb_inplace_matrix_multiply PyBufferProcs PERF_SAMPLE_IDENTIFIER tp_free nb_inplace_subtract aggr_get_id_t __policy PERF_RECORD_AUX pyevent PERF_COUNT_SW_ALIGNMENT_FAULTS combined_sample_type used finished_round PERF_SAMPLE_AUX mispred nb_divmod PYGEN_NEXT objobjproc memory_bsize nr_numa_map cache_regs fd/array.c /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/lib/api /usr/lib/gcc/x86_64-linux-gnu/14/include /usr/include/x86_64-linux-gnu/bits /usr/include/x86_64-linux-gnu/bits/types /usr/include/x86_64-linux-gnu/sys /usr/include /usr/include/x86_64-linux-gnu/gnu /usr/include/linux /usr/include/x86_64-linux-gnu/asm /usr/include/asm-generic stddef.h struct_FILE.h poll.h stdio.h stdlib.h string.h stdc-predef.h libc-header-start.h features.h features-time64.h wordsize.h timesize.h cdefs.h long-double.h stubs.h stubs-64.h stdarg.h typesizes.h __fpos_t.h __mbstate_t.h __fpos64_t.h __FILE.h cookie_io_functions_t.h stdio_lim.h floatn.h floatn-common.h errno.h errno-base.h fcntl.h fcntl-linux.h struct_timespec.h endian.h endianness.h time_t.h struct_stat.h waitflags.h waitstatus.h clock_t.h clockid_t.h timer_t.h stdint-intn.h byteswap.h uintn-identity.h select.h __sigset_t.h struct_timeval.h pthreadtypes.h thread-shared-types.h pthreadtypes-arch.h atomic_wide_counter.h struct_mutex.h struct_rwlock.h alloca.h stdlib-float.h unistd.h posix_opt.h environments.h confname.h getopt_posix.h getopt_core.h unistd_ext.h __locale_t.h strings.h fs/fs.c fs fs/.. /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/include/linux /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/include/asm-generic /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/include/uapi/asm-generic statfs.h pthread.h mount.h assert.h ctype.h syslimits.h posix1_lim.h local_lim.h pthread_stack_min-dynamic.h pthread_stack_min.h posix2_lim.h stdbool.h vfs.h sched.h struct_sched_param.h cpu-set.h time.h struct_tm.h struct_itimerspec.h setjmp.h struct___jmp_buf_tag.h stdint.h wchar.h stdint-uintn.h stdint-least.h ioctl.h ioctls.h ioctl-types.h ttydefaults.h int-ll64.h bitsperlong.h posix_types.h posix_types_64.h debug-internal.h debug.h fs/tracing_path.c dirent.h error_t.h close_range.h tracing_path.h dirent_ext.h fs/cgroup.c stringify.h cpu.c cpu.h debug.c <built-in> ../str_error_r.c core.c /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/lib/perf /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/lib/perf/include/perf /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/lib/perf/include/internal cpumap.c /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/include/asm/../../arch/x86/include/asm atomic.h compiler.h refcount.h cpumap.h threadmap.c threadmap.h evsel.c /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/include/uapi/linux xyarray.h evsel.h perf_event.h mmap.h zalloc.h evlist.c /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/lib/api/fd evlist.h hash.h mmap.c ring_buffer.h math64.h mman.h ../../lib/zalloc.c ../../lib xyarray.c lib.c exec-cmd.c /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/lib/subcmd subcmd-util.h stdio2.h string_fortified.h subcmd-config.h unistd-decl.h stdio2-decl.h compiler_types.h compiler-gcc.h strings_fortified.h select2.h select-decl.h statx-generic.h struct_statx_timestamp.h struct_statx.h stdlib-bsearch.h exec-cmd.h help.c help.h termios.h termios-struct.h termios-c_cc.h termios-c_iflag.h termios-c_oflag.h termios-baud.h termios-c_cflag.h termios-c_lflag.h termios-tcflow.h termios-misc.h pager.c run-command.h sigchain.h signal.h signum-generic.h signum-arch.h sig_atomic_t.h siginfo_t.h __sigval_t.h siginfo-arch.h siginfo-consts.h siginfo-consts-arch.h sigevent_t.h sigevent-consts.h sigaction.h sigcontext.h stack_t.h ucontext.h sigstksz.h ss_flags.h struct_sigstack.h sigthread.h signal_ext.h pager.h parse-options.c parse-options.h kernel.h build_bug.h math.h panic.h run-command.c fcntl2.h wait.h struct_iovec.h falloc.h idtype_t.h sigchain.c subcmd-config.c kallsyms.c /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/lib/symbol kallsyms.h elf.h /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/perf tests/workloads/leafloop.c tests/workloads tests/workloads/.. tests.h tests/workloads/sqrtloop.c mathcalls.h tests/workloads/brstack.c tests/workloads/datasym.c /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/perf/util/python.c /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/perf/util /usr/include/python3.12 /usr/include/python3.12/cpython /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/perf/libperf/include/perf /usr/include/traceevent /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/perf/libapi/include/api/fd /build/linux-p72Zdl/linux-6.11.0/debian/build/tools-perarch/tools/perf/libperf/include/internal err.h trace-event.h pyport.h pytypedefs.h moduleobject.h methodobject.h descrobject.h pybuffer.h pyerrors.h trace-seq.h event-parse.h auxtrace.h time-utils.h sample.h tool.h record.h events_stats.h counts.h env.h addr_location.h aio.h zstd.h compress.h rbtree.h rwsem.h symbol.h branch.h struct_rusage.h rblist.h hist.h target.h kvm-stat.h kwork.h lock-contention.h listobject.h fileobject.h objimpl.h modsupport.h unicodeobject.h longobject.h bytearrayobject.h print_binary.h thread_map.h dictobject.h UUURU 1pPQqQPT p PU I' U VUUU P\ U VUUU 0 P p q 0qQq0 PP P V V P S \ V S \ ې& \ V U T U U V P U V U v p " P S S p UYUUY U 0 0 `U` & U Up U TT QpQ RR UU ,U,5X5~U 1T15Y5~T ),w,5U56w )6 ),U,5X56U )1T15Y56T =Xp X\U 6] x' UVUUVUV TSTTSTS _\\\ TSSS \0 _\\ P]] _\ \ ] \ M \ S V \X_ S V ې& T VU VU ' SU V ې& UV S ] UV ې& V T P P UU TST 0]P] U]U]U] T\T\T\ QVQVQQ 0QP0QP0 0SSS0 PR_ = & & - P^~ - : : J' ( - Pp||~| - : : U]U] T^TT^ Q\UQ\ PSS PVPV PP PSP_T_ P_P_PSPS U ~ T S T S T Q V V Q V P \ P \ P sm P 0 0 ~ ] 7 & Q } S U V ] S _ ] ې& q S P 4 IUI^P_P^U^ QTQ1 B1_\_1_ PQ\^\ MQPQ 1 1 0# 0]}] VV Q s& MQ RePwP ZeP |P & : UVUV T_T_ 0#SP 0|\T 0^~^^ PP UU T T u Uux t Ttx U \ U 0 V S USUS T^T^ Q]Q] PVV pvUv ^ ] U t 3$T PP UU UXU TYT wUw UXU TYT p U x' U \U\U 1 V PPQPRVP0 TtTP0 PP P PSPVP0V USUU v0 v~}~T} ? XYUYZUZZU XYTYY_YYTYZ_ZZTZZT XYQYY\YYQYZ\ZZQZZQ XYRYY^YYRYZ^ZZRZZR XYXYY]YZXZZX YZS XYUYYSYYSZZU XYTYY_YYTYY_ZZT XYQYY\YYQYY\ZZQ WWUWXUXXU WWTWX^XXTXX^XXTXXT WWQWX\XXQXX\XXQXXQ WWRWX]XXRXX]XXRXXR XXS WWUWXSXXSXXU WWTWX^XXTXX^XXT WWQWX\XXQXX\XXQ VVQVWRWWQ VWQ ..U./^//~x//^ ..T.1S11S ..Q.1\11Q11\ ..R.1 ..v .. & //v // & //v // y' 00 c & 00\ 00^ 00\ 00s00U 00V ,-U-.S ,-T-.V ,-Q-.Q -.\ -- [ --Q--Q --R--~ --S --V --0 ,,U,,U ,,T,,T ,,U,,U ,,T,,T ,,0 ;U;M\MRUR\U\\U\ ;T;O]ORTR\T\]T] ;U;M\MRUR\U\\U\ ;T;O]ORTR\T\]T] .IVcsVs|{VV{ BISoSS} |v s Pv s PP .IVcxVV .VRcV BISo|SS} .;t;BSco} U T VVUVVU VVTVVT VVQVVQ VVRVVXVVR VVXVVYVVX 22U22S2@U@ASAB~BBUBB~BVU 22T2@T@@T@A\AB~BBTBB~BVT 22Q2@~@@Q@E~ET~TTVTUvUUVUV~ 22R2@~@@R@V~ 22X2@~@@X@V~ 22Y23}3@Y@@Y@B}BBYBC}CKYKK}KUYUU}UVY 33033~033]~033]\~034]\~Y[44]\~_44 ]\_55]\~Y[55]\~YS55]\ 55]\~YS55]\~YS55]\~Y055]\~Y[56]\~y[66]\~Y[66]\~Y[66]\~1 Y[66]\~1 Y[66]\~Y[67]\~~~77]\~~77]~~~78\~~ 89]~~ 99]~~ 99 ]\~ 9:]\QY::]\~Y::]\~Y[:: ]\~ ::]\ :;\~~ ;;]\~YS;;]\~YP;<]\~Y<< ]\~ << ]\~ << ]\~ <<]\QY<<]\QY[<<]\~Y[<=]\~~~==]\~~[==]\~Y[=>]\~~~>?]\QY^??]\QYP??]\YP??]\ ??]\ ??]\ ?? ]\Q ??]\QY?@]\QYTBB ][BB](CC\~~ CC]\QY[CC]\~_[CC]\~_}CC]\~_[CD ][DD](DD]\~_[EE]\~Y[EE]\~~~EF]\~Y[FF]\~~~FG]\~Y[GG]\~~~GG]\QYTGG]\YGG]\ GG]\ GH\~~ HI]~~ II]~~pII]\QY^II]\~~^II]\~^II]\ II]\~Y[IJ]\~~~JK\~~ KK]\T0KK]\~Y[KK ]~ KK]\~_[KK]\QYTKK]\QYKK]\YKK]\~_SKK]\~Y[KM\~~ MM]~~ MN\~~ NN]~~ NN\~~ NN\~~PNN\~~~NO]\~YSOO]\~SOO\~~ OO]~~ OO]~~[OP]\~Y[PP}x\~Y[PP}x\SY[PP]\SY[PP]\VY[PP]\~1 Y[PP]\~YSPP]\QY^PP\~~ PP]~~ PQ\~~ QQ\~~~QQ]~~~QQ\~~ QR]~~ RR\~~ RR]~~ RS]\~Y[SS]\~~~SS\~~ SS]~~ SS]\QY^ST]\Y^TT ]\^TT\~~ UU]\~0UU\~~ UU]~~ UV\~~ VV]~~ VV]\~~~VV]~~ @B0BC0 @@~@@] @@ g & @A0AA_AB_ AA] AA 3$~" AA\ AA] AA ې& AB] AB I& AB\ AB] AB ې& DE0EE s ~ 8 3%EE s ~ @ 3% EE 6& BB [ BB [ BB & DDS DD [ DD & 23UU 23SUUS 23\UU\ 23}UUQUU} 23 230 230 345999U9::;;=V=>~>@CCCCVCCEFFGRGGGGGKKKVKOOOROOOPPRRSRSSSTTTUV 34~5:~:@~CC~EG~GG~GO~OP~PS~ST~TT~UV~ 34~5:~:@~CC~EG~GG~GO~OP~PS~ST~TT~UV~ 33 s $0)3@ ~0)BB ~0)CK ~0)KK s $0)KU ~0)UV ~0) 3415:1::0:@1CC1EG1GG1GI1IO1OP1PS1ST1TT1UV1 34^55^55S56^66^6:S:>SCCSEFSFG~GGSGISIKSKKSKKSKNSNN~#NOSOOSOP^PRSRS~SSSTTSUVS 55T;<T 6999U9::;CCGIIKKMMNOOPRSSTTUVVV 6:S:;SCCSGISIKSKMSMNSNN~#NNSOOSPRSSSSTTSUVSVVS 77V88V;;VCCVLLv LLPLMv NNv NNPPPv PPv PQPQQv QRVSSv TTv TTPUUv UVVVVv 77PIIPIJPNN~QQ~ 77077~880;;~CC~IJ0LLVLL~LMVNNVPQVQR~SSVTTVUUVUV~VVV 77077_880;;_CC_IJ0LL~LL_LMXNN~PP~PQ_QQ~QQXQQ_QRZSS_SSZTT_UU_UUZUV_VVZ 77077~;;~CC~IJ0LL2LM0NN0PQ2QQ0QR~SS2TT0UU0UV~VV2 77077~;;~CC~IJ0LL~LLQLM~NN~NNQPP~PQ~QQ~QR~SS~TT~UV~VV~ 89R:;0GH0HIRJK0KKRKM0NN0OORPQ0RRRSS0TT0UU0VV0 880:;2GI0JJ0JK2KL0LL2LM0NN0PQ2QQ0RR0SS2TT0UU0VV2 88S 88] 88P88^88] :;] ::R:;~ GH] GH c & HHS HHPHH~ HHPHH~ JJ c & JJS JKRKK~ JK] JKQKK^ KL~ KLS MMr MMU MM 0K' <>SKKSVVS ==~=>V ==S == c & ==U ==S VVp VVU VV J' >?TIIT FG~ FG~ FG0 FFFGRGG NO~ NO~ NO0 NOOOROO RS~ RS~ RS1 RRRSRSS ST~ ST~ ST0 ST 44 44 $ &3$| "44U44 $ &3$| " 44] BC] BC & BC_ CC] CC ې& EE: TU & UVUUVUVUVUVUV U V U V U U V U U V U U V U V U !U!!V!!U!!V!"U""V"#U##V##U##V##U##V#$U$'V'(U((V()U))V))U))V))U))V)*U**V*+U++V++U++U++U++V++U++V TST+S Q\QQ!\!!Q!#\##Q#)\)*Q**\**Q**\*+Q++\ 000 0 0 U 0 U 0 U 0 U 0 U %0%%U%%0%%U%&0&&U&&0&'U''0''U')0))T)*0**U**0**U**0**U**0**U**0**U*+0++T++0 q 2^| 2Q2 ^ | 2 +^++| 2++^ PQ000QQ 0 R##Q$$0'(0))R))0++0++0 ""U""] "" "" @J' ""S))S ""]""X""]))X))] ""\))\ ))\ ))] ))p )) & ""U "" + & ))p )) E & ##U##] ## ## & 0~ $0.~ $0.~ $0.00##0 U] X SSS ]]] \\\ p U & p U & p U & S##S ]##] \##\ ##\ ##] ##p ## & p + & p E & VV SS \\ 00 ]] Ls as P))P S & \ !!S !! & !!Q!!\ !!p !!U !! + & U()U++U S()S++S \()\++\ S () S ++ S T V$%V**V S$%S**S \$%\**\ S $% S ** S U V%%V**V S%%S**S \%%\**\ S %% S ** S U V%&V**V S%&S**S \%&\**\ S %& S ** S U V&&V**V S&&S**S \&&\**\ S && S ** S U V''V**V S''S**S \''\**\ S '' S ** S U ##S**S*+S ## & ** & *+ & ##Q##\**Q**\*+Q++\ ##U ## E & **Q**\ ** & **p ** & *+p ++U *+ + & $$U'(U++U++U++V $$S'(S++S++S $$\'(\++\++\ $$Q'(s++s++s $$R((R++R )*S )* & )*Q**\ )*p **U )* + & U U USUSUSUS TTTTTT TTT SUSS VVV Hv H | L& U L& | & | & | & | & | H& | & | & | v U o& UXU TYT wUw UXU TYT p U x' U ] \ |x \ T \\\U|\\ Q R \_U__\_ s & s & s & s y' 0 V ^X^^ 0QQT00 0 V ^XV^V } 0)p "` } 0)~ "` 0 Z ] } ]]] Z ZZ \]}} }} u \ 0 _ P \\_\ P \UU} ]UP\ | u " U v $ &3 5$| " T ~ v $ &` ~ $ &` | " ] ` \\\ 1 ^^^ UUUUUU TXTTXTTXT QQQQQQ QQ TXT PU + & E & UPu U TPT U UPu TPT U 0 @ USUSUU P USUS USS 11 u,2$7&01 s,2$7& u( ؟s( Qp PP p U & USUS USS 00 u,2$7&01 s,2$7&0 u( ؟s( Qp PPP p U & USU S 1 1 1 1 1 1 1 1 1 ^ ^ ~ ~ ~ ~ 0 PV b& 2 2 P V b& 2 1 P V b& 2 ~ ~ ~ ~ ~ 5U59Y9U 25w59U9:w 2: 2: & 25U59Y9:U A\p \`U :a x' UU Y USTUS 22 USS \ \ U t $ &3$ \ $ &3$T PP UUUTU SU $ &4$[ "SU $ &4$[ "S UUTU UTU UU ,U,5X5~U 1T15Y5~T ),w,5U56w )6 ),U,5X56U )1T15Y56T =Xp X\U 6] x' UVU T\T\ Sv 4$[ "U $ &4$[ "S s t $ &3$ s $ &3$T PP ==U==U ==T==T <=U==U <=T==T <=Q==Q <<U<<U ;<U<<U ;<T<<T ;;U;;U ;;T;;T ;;Q;;Q :;U;;U :;T;;T :;Q;;Q ::U::U ::T::T ::Q::Q 9:U::U 99U99U 99T99T 89U99U 78U88U 78T88T 78Q88Q 78R88R 56U66U 34\44P44\ 33} 4%34} 4%#44} 4%#44} 4% 33P34^ ,-P-4S45P55S --P--P-.P..P..P..P..P..P // 3 // 3 //p //3 #//P 00 6 00 6 00p 006 #00P 00 V 00 V 00p 00V #00P 00 G 00 G 00p 00 G #00P 01 N 01 N 11p 00N #01P 11 `R 11 `R 11p 11`R #11P 11 J 11 J 11p 11J #11P 11 `R 11 `R 11p 11`R #11P 22 C 22 C 22p 22C #22P 22 @@ 22 @@ 22p 22@@ #22P 22 < 22 < 22p 22< #22P 33 8 33 8 33p 338 #33P 33 : 33 : 33p 33: #33P 44\ 44\ UupUUU TPpPT QQ Qu U# Q Q 2U23U ""U"$\$&U&&\&&U ""T"#U#&T "#Q##T#&Q #$|$&U#&&|&&U# $$P$%^&&^&&^ #%S&&S&&S %%P%%Q%% $%]&&]&&] $%]&&]&&] $%P%%\&&P&&\&&\ $$P$$^ $$P$$] $$p 3$@Í " $$_ $$^ $$Q %%] %%] &&]&&] &&] ##| ##Q ##0##s | .. ##s | .. ##S##s~##S &&} &&p &&} #&&P U S U S T U T Q Q s \ s U# s t T T t p t # P &'U'(\((U((\((U((\ &'T'(T &'Q'(Q ''u'(|((U#((|((U#((| ''P'(]((P((]((] ''0''S''s'(S((s((S((S ''^''P'(^((^((^ ((^((^ ((^ '(^ U !S!!U!!S T !U!!T !Q!!T!!Q !!s!!U!!s!!U#!!s !!P!!T!!P!!T ""U""S""U""U""S ""S U S U S T U T Q Q H# P# U S U S T U T Q T Q s \ s U# \ s 0 T 0 R p p # Q U S U U S S USUS TZT QTQ U\U\U\ TSTSTS UU USUUS S USUS TUT QTQ U\U\U\ TSTSTS UU USUUS S @VUVSUS @]T]UT @dQdTQ U U P S P P S P P U P ( U S U U SUS T \ T T T\T\ 0 0P0 U SS T\\ P]P] ^^ P]]] SSS P]]] RRR ^^^ 0P0P00P PUUP UU}(P_U Q_Q__ P P P U U P S P P S U P D' UUUU U U P S P P S UUUU UrtUUU UU U U P S P P S ))U))up))U ))T))T ))Q))Q ))U))U# ))p ))p #))Q ))U ))T ))Q )*U**S**U*+S )*T**U*+T )*Q**T*+Q **s**U#*+s **S **T **Q **p **p #**Q ++U+,U ++T++U+,T ++Q++T+,Q ,,P,,P ,,P ,,U ,,T ,,Q 66U66U 66T66T 66Q66Q [ $ $ N ! $ }& }& 6 %" & & }& ( 0) d) ) ") $6 %j* 'v }& }& 6 z* * + (1 f )\ *s +u ,+ / v %, , , , w RI , ! "#$f %- Y. &Q &q #'0 =(0 2 K)Mq *2 #+2 2 ,` N- .2 3 3 /c 04 4 '5 =5 $ (15 )26 a6 36 ~4v3 5D 66 C 6 70 < 8 7 #9-7 $:- I7 ; <7 !=F >7 %?$ 7 8 @d AY ,B& }& -8 .CA LDs8 YE8 qb ?6O F8 6 8 :: G H8 I)9 J}& : ; -; M; K; Ld M] N C 4 C !-; O P$K QC 6 [ $ " #$ }& }& 6 %" & & }& ( 0) C S v }& }& 6 z* * !+ '"2 ##2 2 D $ %$K D & '()f *- Y. &Q + ",q +-E .4 E / }& E 0qF &1F F Q2 3 CG g 4kG G 5H $ .4 ) ") $6 %6j* (71 8f )9\ *:s +u ,+ /;v %, <, , =, w>RI , .4 '5 =5 $ (?5 )@6 a6 AH ~Bv3 CD D` E6 C 6 F0 < G 7 #H-7 $I- I7 J K7 !LF M7 %N$ 'OMq 7 8 d Y ,P& }& -8 .QA L s8 YR8 qb ?6O S8 6 8 :: T C .4 C !-; UC 6 Vz CI W eX Y2 3 YI q #Z0 =[0 (M NX3 1 \pJ -; +]J P^B ,_J K `K -; !a&K 'b 0c dK }& }& e ~K 8 f)9 g}& : ; -; M; h; id j] k% l mL .4 n L }& %o )p 6L M q rst u vwuN EO MQ xsR $yAS z { 3 |} ~ b S S T #T n 9T aT :V cY c 4 \ xY 8 "^ & * .b <@ G> k8 { [ $ $ N ! Y }& }& 6 %" 0\ & }& ( 0) \ ) ") $6 %j* 'v }& }& 6 z* * + (1 f )\ *s + u , + / v \ , Q] , w!RI , ] '5 =5 $ ("5 )#6 a6 $ %$K &H ~'v3 (D )` *6 ^ 6 +0 < , -2 #.2 2 '^ #/-7 $0- I7 1 27 !3F 47 %5$ '6Mq C^ 8 7d 8Y ,9& }& -8 .:A L;s8 Y<8 qb ?6O =8 6 8 :: >C ] C !-; ^ ?C 6 2 @ AH M B CL ] D L }& %E )F ^ 3 GH I b JS K LS T MN#T On 9T P Q RSTf U- Y. &Q 0V W8 X)9 Y}& : ; 3a oa Z; [d \] a ]&^a a _b =b +b ` }& }b aqF &bF F QcUc CG g ec 3a d & [ $ wc r $ }& }& 6 %" & & }& ( 0) v }& }& 6 z* * + c ~v3 D ` 6 C c 0 < 2 # 2 2 '^ # -7 $ - I7 !7 !"F #7 %$$ '%Mq 7 8 &d 'Y ,(& }& -8 .)A L*s8 Y+8 qb ?6O , e- .2 3 YI /q #00 =10 (M N-3 $ 24 ) "-; $6 %3j* (41 5f )6\ *7s +u ,+ /8v {d 9, , :, w;RI , 24 '5 =5 $ (<5 )=6 a6 >8 6 8 :: ?C 24 C !-; @ A$K BC 6 C DH E8 F)9 G}& : ; -; M; H; Id J] Kd [ $ $ N !$ }& }& 6 %" & & }& ( 0) d) ) ") $6 %j* 'v }& }& 6 z* * + (1 f )\ *s +u ,+ /v %, , , , w RI , " H 8 )9 !}& : ; -; d "; #d $] ;e %d S [ $ $ N ! $ }& }& 6 %" & & }& ( 0) d) ) ") $6 %j* 'v }& }& 6 z* * + (1 f )\ *s +u ,+ /v %, , , , w RI , [e e f [ $ F$ C N !$ }& }& 6 %" & & }& ( 0) d) C !) $K C 6 $ 4 ) "-; $6 %j* 'v }& }& 6 z* * + (1 f )\ *s +u ,+ / v %, , , , w RI , 2 ! "H e # $L 4 % L }& "&0 %' )( f 3 )* + b ,S - .S T /0#T 1n 9T b ?x up l P G 2 L U EP G V ч o< V N r2 X / x` - - {H 7 7t " w + : - I: $ : ^ ]> F v : [ G; [ G ͞ ; , | B 1 R ͭ l : E T pA > w q & ) @ ;H r '; x z bp I 0 x6 ! |? n "L J / ƃ U 4 Y XP ș n 6 P ok 3m y wQ y , . &" ah + U Ҵ tO j h y v& Y ( N N ^U 8 # 7 ,5 ). 7 % 5 =z w * 2G & ] ) aC . C [2 ٨ _ ߌ M m BR ` C ' \ ! U ' M1 J = g M a| 7 {J < " 8 D Dn + T # e! ;$ Rm f 3 T, C r M E < L } S қ !W p | [ v 5 T v> 2 4 9 Lt r y^ YR - ^ : 8 s F/ > Q " o Q% ] u 6\ K fE 2 P JS !7 Oc \ 0` 1 7 gb ! D # ? Q x A : [* N Z ] G ' 9 G d Vg ޗ Q \ l 9 F / ů m ! \o | %[ 7 C 3 C n ;> q Ys Dh ? j+ w e dD xg r ^ IU R E- A W ,0 m _ × s )' l u I G P x q = O- + G k &1 I s7 t 8 & '`q 0 1L >s UX 0c ^X . . hm L' 1 q 0 A pG 0 Y 6 Z ; թ >X $: {Z d > cv n A A 3 Ry ( ҵ m ) Xx d} 0' u [ _ . ҵ . ( 3 H (B Z M G A # L _ tU * Pr #__P $- - 2_ 73 Ag B O4 P Q0 R2 f },V ~o G %l Ѧ _r X f5 * 7v Fw . N @ v &h JG F h X = [ J` d # |} < X Z T2 f 2< 9~ [ ! S c 5 X + k B 5 F8 C c0 wi F^ ( Z- K g ^B M O= Nb ( A MH " { % *" C+ G׆ I$ M O{ SM Z P ^d `> dE i# mb C !ހ _ V u r c c 9 ! C U ) XE _ OZ " 'J m n< o$! p qT r7A 5 Z x Al - l: G" "Dz #e & 'g (8k )j *e{ + -O .3 3] 4kf 5 6V 7D 8s 9 :d ; < = >; ?Ѭ @@ AX B'Z C D E| F G Ht Ir Jej K QH T< W J Z ] gp : ǔ f$ j/ oW pe rm ss u 6 DS Hw O؟ ^ _ `M d i b n o k p y" | }N \ +A p 4l so r K ; a (, 08S 6F A8J MD " # $> %f &3 46 5{ 6G9 7l 8( 9ġ ?;V F^ ]j i>c q, }( <s %u W& Dv IC / / 7. Q $ 8 P > w z ' Ѥ s~ ~ ! "~ # $ %\ &o@ m6 T M ܤ J l o i F z_ } D# ! "9 # $͆ % & (G *q +XM , -f@ .' / 0# 1 2 3x 4@ 5 67 7 8Ò 9Ψ : ; <) =ݒ >o ? @6 A B C D, ET Fn G5 H1 IW J K Q LO MV Np OY Py@ Q RS S; T> UC VJ[ W7 Xu Y ^ ZN [X \ ]j ^k _S `, a bٝ c dS e f g h i} kO l{ mi n Y o pQC qJ t u w yW $ RX ! 3 *C + ,*y -J, / 2 5Ue 8Tl ;K >j AK D F, HW@ O R, U9 X [l ^' aГ d! m_ n! o)& /C \ g z| v\ g 1H xs z< s ܣ h ] f v 1 J T y a m % ; 8; p 7= ? f ; a OY (M 38, FN? - {I s$ (l ,Pk $ M N[ O _ m . G !F " S #@ $k %z &H *J +" ,f 0 1~ 2?. 3 4B 5 8F 9_? P Q5{ R8 SM T2 V Y! \h a3- b-x fiI i$i j0 kDg mu oa pn q s u v w y| /E N k M* 5 e h i$ g <w r . : +w !$ " /!C 05 1Β N % *" C+ G׆ I$ M O{ SM Z P ^d `> dE i# mb C ހ XE 6 B w K ? V R 3 w' r' B O v ,D & _ OZ kK } N NO .T ! $4 & 'd i; "D %* ( , 12 5 8 9@5 :ʌ ; ,a -@ . H /Df 0{ 1A+ 3Y Hy R Wx \D ]q a$ r ( 3r# 7> <b7 A' K P hC tH zj XE OZ J 0 ? # ] E ,& ;` '+ (k ) *S ,< -$ .` / 1 2C} 31 4 ( Y "H $H 7 w ,xX 4y 6Q 7Bu 8 DSQ IA Pq U) V'Y W` Xe !O KJ ?K 4 o { )U *K + ,/ -֜ /zP 0: C % 8Ɖ Ո ( :} C $ #o ' " 5hx C" F5 JA Nbl R"9 Vy Z] d.} gk h i>' lL pi s 1 T$ [ #\ &}8 )P ,4 /;M 2ZH 5D 9 < ? B4b EP H K L!/ O$ R] Uq X \H `LT c͘ gO jtz mI n p/^ r uEB xk yC zJ }Ϣ T 63 9 r ; =& 5 ,R ] B w ~ R }~ & > a u Dd Cp 8H 9 :F =i >o4 ? _1 ` e[[ f- h i $ hi ȟ ~ C ހ XE _ OZ V 4 M /E N j W !J # %+P '. )T +Į -1 /y 1! 3 5O 7z 9f ;t =d ? n A)U C@ J Lۙ N Ph Rm T( V X[Z Z \I ^ c `ZA bc d f hA j l n p rXd t vq xU zX |K ~Z - V S U z 6E vh y W n [ ; 3 H\ z b d { (J bM $8 j UK d Y B E 7Q wm ;| N3 э , p E /6 q :D u Q4 ͕ N# U n , Ɗ XO ` Ej x U , 8 ^ | S m X' a9 11 6y ñ J i O 3 ] 2? F } ? D , W 8 aJ Q W b 0 & ^_ l( > ~ 4o %] t ^/ j ) < wY [ ! Y )4 3! " 9 z s E 3 ܐ .I # > b hN ` _ - t @ 0 k ^ V ,r 6i Q] u- ! )M w ,( 90 q `u G L % { k e G{ ަ I 2 = Y { = \n k +F gy ݱ % aF GL x uK [" + } % @ g vT W Ʉ v* p ce ~ e ˎ O. i _ ]W R qR # W ԋ E] C ހ C ( Ao v +I X c& d) f , ; t k m , P s 4 > 1 @ ] ? ' J N W g n e z Z_ # & * 0 4) 72 : =8 AF D G J N UE a dv h k n q t1 wN z }Y 6 " C . ? M # W 6 * + /@U 0s 4p 5e 9 : > @ CԹ E H J N T W Z ] `. c V ! $ ( ,' /[ 3W 7 ?u B EO H KP N Q T X <B ?&^ @ H I JW K0 Ni R8 ` a bX cN gJ h i j{ m qB u} v wa x {` |H N 0 q X ) M $ $` %^ & 1 r ( 3r# 7> <b7 A' F8, K P bN? hC tH zj C D E h i5{ j8 kM l2 n q! uh { } ~% [ C S s 3- -x iI $i 0 Dg u u a n | 4 M ` C ހ [ ~ # $ .ȼ : As H Pi T/ c n p q / 0 C ހ " . 0M 2 4 66 8 :8 < > @' B$ E (Q * Z r I ` e % j e E " *9 _ ` i] j k l n oп p q tm u v w { | } ~J Ǹ 5 v A P j f j . ' w , n 1 n K o N , { , ch n ' (9 * ' k ` D XE & _ OZ j 5 $ ' ( )ػ *i ,# - .Z /Q : >6 B E K S" T U" V# W X Yַ \X ]k ^ _m c d e f g` + e p ' ) ! "| # $ %" & ' ( ) * + , -} . / 0 1 2 3 4 5C 6a 7r 8^ 9{ : ; <$ =8 > ? @ A C E' F G# H I J K[ L M Nq O P9 Q R S U Vw W X$ Y Z [ \* ] ^ _ ` b cH jk n9 o p{ q} rq sm t u w b 1 . !\ " #- $ %I & 'L ( )R *U + , - . /e 0 1 2 3 4 5 6 7 8 9 : ; <Q = >~ ? @, Al C D F G7 LZ ML N^ QC R S W_ XL \ ] f l # / 0 1v 2 3 4q 5 6 7p 8÷ 9 > ? @ A B C9 D E F G H I JO K LX M ) . /6 0 1 2B 79 8 : >q ? A E FS Gw H I JN K L M N O P= Q S TP U? ˺ 4 6 ) P 0 3M 8 :E ;1 V ' ! " #V $ %I & ' *E + ,= - .$ / 4 :? ;) @( A F{ G H I J Ku Lc M N Sn X Y Z [ oa t u- vk w x^ y z { |o } ~C 6 ) ܸ ? N R % & - / 0 2 3 5 6N 8D 9{ ;l < > ? A B D E G Hb JW K M N| Pt Qr Sj T& V W Y Zz \n ] _ ` b c e fD h: i k lP nC o q r t u w x z {i }_ 8 ) C 0 X & _ @ v W _ } L c 3 > w _ [ a - k ^ o C 6 { u c n ( (FS 0c ^X . . hm L' 1 q 0 A pG 0 Y 6 Z ; թ >X $: {Z d > cv n A ! h ) Xx d} ' l s7 A 3 H A 3 ( ҵ ) Xx d} 0' u [ _ . ҵ . ( 3 H W! v H! T 3 _ M . ҵ . ( : M X G A B L _ tU * % ( C+ EL I$ K O{ Q Z P \! `> b i# k@ 6 DS Hw O؟ ^ _ `M d i b n o k p r s y" | }N +A ( p 4l so r K ? ; a N % ( C+ EL I$ K O{ Q Z P \! `> b i# k@ V xX C J 0 ? # 4y 6Q 7Bu 8 As IA Pq U) V'Y W` Xe M4 _ ` i] j k l n oп p q tm u v w { | } ~J Ǹ 5 v A P j f j . ' w , n 1 n K o N , { , ch n 3 2 E D i h K J a ` f! e! \ [ ] 2! @ D XE & _ OZ j 5 M /E N j i$ g <w r w = (FS /#! 1o 2+ 3t 4 8= U W! dY f h[ jN l} n p r t x y # & * 0 4) 72 : =8 AF D G J N UE ] a dv h k n q t1 wN z }Y 6 4 C " k" ! ( 3r# 7> <b7 A' F8, K P YS ]w bN? hC m؟ tH zj _ V u r c c 9 ! C U ) XE OZ 6 ^ _ `M d i b n o k p y" | }N (FS ' V N? 4 M /E N j i$ g <w r # j# " 2# 4# 5# 8# :# m # pJ v # y# \ ' (9 * ' k ` D XE 6 B w K ? V R 3 w' r' B O v ,D & _ OZ j 5 M4 _ ` i] j k l n oп p q tm u v w { | } ~J Ǹ 5 v A P j f j . ' w , n 1 n K o N , { , ch n G Í $ A ! $O (U H L N ! Y !}& "!}& 6 %" # !}& $ G W % &0) \ v !}& "!}& 6 z* '* (+ ) L !}& "*0 %+ ), ^ 3 -. / b 0S 1 2S T 34#T 5n ɜ 62 C ] C !3a 7 8$K ^ 9C 3a :Y jb ; ~<v3 =D >` ?6 ^ 3a < @ A2 #B2 2 '^ #C-7 $D- I7 E F7 !GF H7 %I$ 'Mq C^ JK0S v 8 Ld MY ,N& !}& -8 .OA LPs8 YQ8 qb ?6O eR 2 3 YI S T b 'UVW8 X)9 Y!}& : ; 3a r Z; [d \] a h_ ]&^a ] '5 3a $ (_5 )`6 ў 8a, wbRI $ , c8 3a 8 :: d e f`Q_ $ ] ) "3a $6 % j* (g1 hf )i\ *js + u , + /kv ' l, Q] m hB [e Ɵ nP E W T Q Í $ $ N ! Y }& }& 6 %" }& ! G W " #0) \ ) " ) $6 % j* ' v }& }& 6 z* $* %+ (&1 'f )(\ *)s +u , + /*v \ +, Q] ,, w-RI ! , ] '5 =5 $ (.5 )/6 a6 0 1$K 2H ~3v3 4D 5` 66 ^ 6 70 < 8 92 #:2 2 '^ #;-7 $<- I7 = >7 !?F @7 %A$ 'Mq C^ BC0S v 8 Dd EY ,F& }& -8 .GA LHs8 YI8 qb ?6O J8 6 8 :: K L M`Q_ C ] C ! -; ^ NC 6 OY jb 2 P QH M R SL ] T L }& %U )V ^ 3 WX Y b ZS [ \S T ]^#T _n 9T `f 'ab c db e ~ 5f 7gp 8h JiT Lj,#k hkj lmn o pquN EO MQ mR $k er 2 3 YI s t b 'uvw x8 y)9 z }& : ; 3a oa {; |d }] a ~h_ &a =b +b }& }b qF &F F QUc CG g ec 3a hB [e A ! $O (U Ɵ Td P d` Í $ Y }& }& 6 %" }& G W 0) v }& }& 6 z* * + 7 ! F 7 $!` %$ '"Mq #2 #$2 2 %0S v &] '5 ' $ ((5 ))6 ў 8*, w+RI , , -$K ~.v3 /D 06 '6 10 < 2 7 #3-7 $4- I7 8 5d 6Y ,7& }& -8 .8A L9s8 Y:8 qb ?6O ;8 '6 8 :: < = >`Q_ $ &] ) "'-; $6 %?j* (@1 Af )B\ *Cs +u ,+ /Dv ' E, Q] F G H C &] C !'-; ^ IC '6 JY Kjb o L* LM On NRx 9Oz }& Pw @ Qe} P :R Sm >Tw BUq }& CV W X_ C '6 Y{ '6 Z [8 \8 ])9 ^}& : ; '-; N _; `d a] a bch_ d&ea f g`z h v ë i jkl m nouN EO MQ kR $pAS q|p ի t E Se Í $ A ! $O (U H L N ! Y !}& "!}& 6 %" # !}& $ G W % &0) \ v !}& "!}& 6 z* '* (+ ) L !}& "*0 % )+ ^ 3 ,- . b /S 0 1S T 23#T 4n ɜ 2 C ] C !3a 5 6$K ^ 7C 3a 8Y jb $ ] ) "3a $6 % j* (91 :f );\ *<s +u ,+ /=v \ >, Q] ?, w@RI $ , ] '5 3a $ (A5 )B6 a6 CH ~Dv3 ED F` G6 ^ 3a < H I2 #J2 2 '^ #K-7 $L- I7 M N7 !OF P7 %Q$ 'RMq C^ ST0S v 8 Ud VY ,W& !}& -8 .XA LYs8 YZ8 qb ?6O [8 3a 8 :: \ ] ^`Q_ hB [e Ɵ i _ ` aʭ b c db K, B E |p g M ̏ Í $ ' Y }& }& 6 %" }& G W 0) Я )9 }& : 4 v }& }& 6 z* !* "+ M ) f #; $d %] a &'h_ (&)a * ~+v3 ,D -` .6 6 6 /0 < 0 12 #22 2 '^ #3-7 $4- I7 5 67 !7F 87 %9$ ':Mq C^ ;<0S v 8 =d >Y ,?& }& -8 .@A LAs8 YB8 qb ?6O C eD E2 3 YI F G`X H IH e J KL L] M L }& %N )O H 3 PQ R b SS T US T VW#T Xn 9T ڳ b 'YZ[\q #]0 =^&_ 3a ` 5 (M NDG C L] C !3a a b$K ^ cC 3a dY jb 2 e fghf i- Y. &Q 0j < $ko l* Lm On nRx 9oz }& pw @ qe} P :r sm >tw Buq }& Cv w x_ C 3a y{ 3a z {8 | } ~`z v ë 15 46 > J hB L] '5 3a $ 8, wRI , 8 3a 8 :: `Q_ $ L] ) "3a $6 (1 f )\ *s + u , + /v , Q] A ! $O (U Ɵ ի P c Í $ o Y }& }& 6 %" }& G W 0) v }& }& 6 z* * + * L On Rx # F 7 > 5 Mq 2 #!2 2 "` 9#z }& $w @ %e} P :& 'm >(w B)q }& N C* + ,_ C c -{ 6 . /8 018 2)9 3}& : p -; 4; 5d 6] a 78h_ 9&:a ; <`z =d >Y ,?& }& -8 .@A LAs8 YB8 qb C v ë DhB E] '5 =5 $ (F5 )G6 ў 8H, wIRI , J K$K L ~Mv3 ND O6 6 6 P0 < Q 7 #R-7 $S- I7 T U7 %V$ C^ WX0S v 8 Y8 6 8 :: Z [ \`Q_ $ E] ) "-; $6 (]1 ^f )_\ *`s + u , + /av b, Q] c dA e! $fO (U g hH M i jL E] k L }& %l )m H 3 no p b qS r sS T tu#T vn ɜ Ɵ t Ѣ Í $ E $ b ?x up l P G 2 L U EP G V C] ч o< V N r2 X / x` - - {H 7 7t " w + : - I: $ : ^ ]> F v : [ G; [ G ͞ ; , | B 1 R ͭ l : E T pA > w q & ) @ ;H r '; x z bp I 0 x6 ! |? n "L J / ƃ U 4 Y XP ș n 6 P ok 3m y wQ y , . &" ah + U Ҵ tO j h y v& Y ( N N ^U 8 # 7 ,5 ). 7 % 5 =z w * 2G & ] ) aC . C [2 ٨ _ ߌ M m BR ` C ' \ ! U ' M1 J = g M a| 7 {J < " 8 D Dn + T # e! ;$ Rm f 3 T, C r M E < L } S қ !W p | [ v 5 T v> 2 4 9 Lt r y^ YR - ^ : 8 s F/ > Q " o Q% ] u 6\ K fE 2 P JS !7 Oc \ 0` 1 7 gb ! D # ? Q x A : [* N Z ] G ' 9 G d Vg ޗ Q \ l 9 F / ů m ! \o %[ 7 C 3 C n ;> q Ys Dh ? j+ w e dD xg r ^ IU R E- A W ,0 m _ × s )' l u I G P x q = O- + G k &1 s7 t V 8 >X ]Z |Y 9C zR R a a` Q MR I *Y ] P !@` $T 'C )Y *EF ` B "5W '\ *D .~_ 6vX >Q B` GXD OZ ] ^LI _&W bX fP j_ rM v;[ zV ~%Z LZ ' (9 * ' k ` D _ V u r c c 9 ! C U ) XE 6 B w K ? V R 3 w' r' B O v ,D & _ OZ j 5 M X b A B L _ tU * Pr #__P $- - 2_ 73 Ag B O4 P Q0 R2 f },V ~o G %l Ѧ _r X WP X T yB X[ ] _ E R _ ] O a xS M W R] 1N HC * 7v Fw . N @ v &h JG F h X = [ J` d # |} < X Z P f 2< 9~ [ ! S c 5 X + k B 5 F8 C c0 wi F^ ( Z- K Y ^B M O= 0 3M :E ;1 V 3O E wZ sQ MT r ( 3r# 7> <b7 A' F8, K P YS ]w bN? hC m؟ tH zj P SU `X R E W A Z \ Db \ Y \Q F dI <Q _S \ V FS -I A X 0_ T M 0T P Q S ^ "b ` !0U "D M /E N k j ,a -@ . H /Df 0{ 1A+ 3Y Hy R Wx \D ]q a$ 6 ^ _ `M d i b n o k p r s y" | }N 0F Z PX ] wF I X R Z Z a &0M 9 V b "Le #j El e f f f k c k j !g "h #Nh $j %&l &#h ' l (d qh h k hi i h fc k d !'j #k $rd %g &g (c f k b g j c d :g "g #c $Bh %k &b 'i (Ml )h *mg +Xg ,i -ed .+i /g 0Nf 1k 2 i 3h 4b 7Zi 8k 9d <c !Zg "e #{e $hf %i &b 'b (b )e *i +>e ,j -h .Li /f 0}i 26h 3k g j &g e 5j !d "i #h $Oc %f &sj 'Yl (c )uf *Cd +f ,g -d .e /c 08i g Jj j zk nk dj c d i !f "Vh %j d le h *d e Zf !g "h #l %Hg *b -tc 0@c 2|g 6b 9i < @Ef Af B!d Ceg Fd Gi Hf k 4c d ) . /6 0 1 2B 79 8 <e >q ? Ci E FS Gw H I JN K L M N O P= Q S TP U? ` B "5W '\ .~_ 6vX >Q B` GXD OZ ] ^LI _&W fP j_ v;[ zV ~%Z LZ 3O E wZ sQ MT ,xX 4y 6Q 7Bu 8 As IA Pq U) V'Y W` Xe _ V u r c c 9 ! C U ) XE 6 B w K ? V R 3 w' r' B O v ,D & _ OZ V C Rt x | y !} 0n 1t 2~ 3z 4t 5v{ 8Z| 9Z{ :uz ;x <|} =l @{ Aq Bl 6r c| n !p "^q %p &[ '| (0 )p * t +y ,{ -3y .Es / 0o 1+x 26x 6N{ 9{ :q ;l =r >z Ps f | u %p Sr } !>y y u s t vl { s v } r #q ~m n ǀ x ){ l An ; ?u p 7| 8 9bs :{ ;pu <x = >pu ?/n @p A"r J Ly Nz Ps Ram T{r Vy XD| Z| ao cp e} g(~ i w k9w mq ow qp sut z<p |dp ~y q n s r m ew { J m gn 't ~ | r d{ Ow z w u >~ l m oy t w -o . { } n " } &~ v { u ';} (yo 8x 9m :t =xx @v A{ Cts FXu I&} Jx K-o Oz P Q~ =t ~ Ry z l C r v (.w * 5u 7v 9q ;p =q ?q AGq Chq E o Gs I)| Kp| MTp Oy Q+ Sz UHo W| Yxv [{ ]r _u ao n jr y 4 M /E N j 6u [ *u Xo x #m %z Im v =N~ >; ?e~ S +I X c& d) f , ; t k m , P R i s 4 > 1 @ ] ? ' J N W g n e " ( Ao v F Ê t x Q ' 1 ; V" T b y # &b e : $7 * 2 9 :ދ ;Ӑ A D$ T US V؏ W X Y Z9 [ \ ] ^Ǎ _ g jN k r t u v١ w xݞ y4 z1 { " u 4 " ˆ ܍ Ȥ z & Ѕ o " 5hx C" F5 JA Nbl R"9 Vy Z] d.} gk h i>' lL pi s hi ȟ ~ ؟ C ހ ' S w V N? 4 M /E N k j r ( 3r# 7> <b7 F8, K hC tH zj xX C _ ` i] j k l n oп p q tm u v w { | } ~J Ǹ 5 v A P j f j . ' w , n 1 n K o N , { , ch n 3 2 E D i h K J a ` f! e! \ [ ] 2! @ R E W A Z \ Db \ Y \Q F dI <Q _S \ V FS -I A X 0_ T M 0T P Q S ^ "b ` C *C + ,*y -J, / 2 5Ue 8Tl ;K >j AK D F, HW@ O R, U9 X [l ^' aГ d! m_ n! o)& J ަ /C \ g z| å l v\ g 1H xs z< s ܣ h ] f v u " 2 ; Ҫ 1 J T y a m % C t [ < { 0 Ь ץ ^ E Ŧ § z ; 8; p 7= ? f ; a OY ҫ L ' K Ĭ X + <) N C ٭ P Q5{ R8 SM T2 V Y! \h a3- b-x fiI i$i j0 kDg mu oa pn q s u v w y| k M* 5 e k R [ " h 6a 7@ 8 H 9Df :{ ;A+ =Y B C D E W Xݩ # j# " 'J 2# 4# 5# 8# :# m # pJ s v # y# ^ _ `M d i b n o k p r s y" | }N )N? / t w 6O -o . hi ȟ ~ ؟ C ހ ' S w V 4 M /E N k j ` B "5W '\ .~_ 6vX >Q B` GXD OZ ] ^LI _&W fP j_ rM v;[ zV ~%Z LZ " $ RI L N !z }& }& 6 %" & }& ( 0) d) v }& }& 6 z* * + L }& " 0 % ) f d ` !A "! $#O (U C! $H ! 3 %& b 'S ( )S T *+#T ,n ɜ P# - ./0f 1- Y. &Q 2 c 34 4 4 '5 3a $ (55 )66 ў 87, w8RI , ~9v3 :D ;` <6 C 3a < = >2 #?2 2 '^ #@-7 $A- I7 B C7 !DF E7 %F$ 'GMq 7 8 Hd IY ,J& }& -8 .KA LLs8 YM8 qb ?6O N8 3a 8 :: O PC 4 C !3a Q R$K SC 3a 8 T)9 U}& : ; 3a # V; Wd X] ;e YZ$ 4 ) "3a $6 %[j* (\1 ]f )^\ *_s +`u ,a+ /bv {d c, , d ee f2 3 YI q #g0 =h0 (M Ne<$ b ՠ up l P G 2 L U EP G V ч o< V N r2 X / x` - - {H 7 7t " w + : - I: $ : ^ ]> F v : [ G; [ G ͞ ; , | B 1 R ͭ l : E T pA > w q & ) @ ;H r '; x z bp I 0 x6 ! |? n "L J / ƃ U 4 Y XP ș n 6 P ok 3m y wQ y , . &" ah + U Ҵ tO j h y v& Y ( N N ^U 8 # 7 ,5 ). 7 % 5 =z w * 2G & ] ) aC . C [2 ٨ _ ߌ M m BR ` C ' \ ! U ' M1 J = g M a| 7 {J < " 8 D Dn + T # e! ;$ Rm f 3 T, C r M E < L } S қ !W p | [ v 5 T v> 2 4 9 Lt r y^ YR - ^ : 8 s F/ > Q " o Q% ] u 6\ K fE 2 P JS !7 Oc \ 0` 1 7 gb ! D # ? Q x A : [* N Z ] G ' 9 G d Vg ޗ Q \ l 9 F / ů m ! \o | %[ 7 C 3 C n ;> q Ys Dh ? j+ w e dD xg r ^ IU R E- A W ,0 m _ × s )' l u I G P x q = O- + G k &1 I s7 t 8 0c ^X . . hm L' 1 q 0 A pG 0 Y 6 Z ; թ >X $: {Z d > cv n A A 3 Ry ( ҵ m ) Xx d} 0' u [ _ . ҵ . ( 3 H M G A # L _ tU * = g< h֏ jg k mV n pQ q>p t uHn w x ysd z { } ~N 2 { u / J - , s < 6_ Q HU e" ϼ 7D >" G 'w b z " W d Y ! } ? < >7 Y ` R ض Z> e c Q ؐ ' . g j # k D Q& r @ _ CF v 6 . df T7 H7 v o Ϻ * x ? v 4 L G $ |6 & N n O l . ? ;3 f L x } J/ Ҫ Z P\ \ qk q I E 1 d 7R A {* 2 ?. :! nv r ي @ z s | ŀ o OP { p & > % ~ - ` `N >z *E { Q k B ] l ^ B ?T &~ ~r Ӹ ܻ K /o X ) ( (\ V \ iF X vg Ih ښ u ;Q ,z 5 < Y* X+ ( C P' x ҕ ~ e 3 k ` ? q 7 u o 0C U %b q b * Rh Z ' * F : S NJ Xk &@ ; ` p J " ?H Y *( N 1 M ɤ z 0 >| U H ( ? ӱ Cx m B r Q 9 3 / i P< XC R / " ) :/ fw 3 ɶ : A ^ v ; ^X GX [ # @ گ + ˙ _ T v q cW o M^ T + ) ܺ a ^i Z ] 7 t t @ ϝ . ` % J > C O $A [? L 9 n ] O m 4 ] @J NO Љ I / Ҿ d V oI @> p m XU - 9 o 1 Z v & ) \\ W < B 4 tU g ~ ! 1 J E o ? & '! I n G ˱ * b b ]V Ke *> % : p t 6 a d }1 ) tV % 0 T T | k jY PX & e , 8 9 1 @ z- @ 8 Dm + ^ | K 9' N I t C SD * 2; ` + } 3 S @ U c W K I Z w 4O ,Z a- / 3 K c A 9 X < U I 4 + | ;b \] d i X W4 a Ĺ y )G = " m' hp M aj S + f 7 q ~ + K ; + Lq w< ң j ut a N Vr # " _s L !J C l b m \3 d n ~> ȃ i +l = | y 5 -3 > O ? < j , ǥ Ά _M i , ۸ fC S oL @ 9 ; z NL 'X aA m - ( L 0` Г " 9 I :V }B 6 C \ , & H O } Y zR 3 -x I l x .i d ( l ; ) EB ܆ O 8 ѹ M 2 u 1 v : p| l ~ g 0w q P i k R # 7 ' ( Cr T 2 |\ ) = U G Q | S _ T : w \} j 5 ^ :a ol ˿ z i Q P 0 ͷ t9 A* / ό p ܍ p ^ & ' mK : < 4 x 0 p nq T 7 n ɦ ! ;Y P x u M ` zS pf a " ( $ ? $ r < 45 K a c W k $ & : E B 5 6A M #8 5 z Q q w :2 y J @ : Ә 0 L W Ht + G EM m 2 Q# { ) D z ;u Z Lz Tv R n T w tF #* h a ]q =9 x a S LK ; 6 Y q & 1 S j E l@ Q \ D r w ` # d | U6 x L V +] ~ H Z 3 A P #2 H ' W 70 w }" d o o Z =g 8 ; Ё đ = # dg Zb ^ > S !9 2X << ӧ c =c 5 o# @ I / , ~ g] ` 5P < Qa v q L w / vh 0 \ R@ s { ? F b A k i n R s D b J, #$ d, \ p a 3 d . ~ ^ u z[ S2 : h yC be yp T ^ e b > [ ! " F t P e `( m p/ G G P - = oW a F- w c s( A " l m { W ~ ) U $ ;\ O: X9 H E 2q , x P ? } 1[ S | , ^ 4 $ ^ K \ I g ) $ 5h g MW ; 6 n JT " D Eb o ) F 1 } 0 e . E N c } 9 M w 5 1 ' n + ! n A H Y / I~ O ~ s d G e+ f ] p~ KQ K R 7 c ; 8 r U Q Ӏ ?$ z Q= > N s U E ; ? qM D m = ʻ 6 ] W g V 5 Y a & Ld p є ^ H s 1 ; ~ ^ o ; } X G % p I q l a) A ` M , * 8 x k: E [8 {K Ж * m T 5 :y f S V i Ů _ c >@ \K fE gX Q & \ > { Q ! H % {Z ݱ i . s j Ͳ B ة /M w O ) i ; %c @% * " m^ V J PN k i Q ެ ;4 r H k B [ #F ' 5 ] - [ ; 6 \ P ʜ C % w D lH Z :s 1 H : FV | } S ~+ Y A ï / ۢ { # , { G M P ճ F j >+ d> 2 = Jp W ڇ e ? 1d 5 h 4 e B} ' L ?l ? [ o5 < l J_ s C Q С 3 m % J U h 2 h $" = * ҂ 8 N 3 \ D )j : 7K ix f A =Z ] 0 ^ z ]` > j W U N fa $ 6 >] x` ި %% I [ $ l ' H X )| U ~c b 9 4 ^ 6k tO ~ . . , { MF $ _ So ٮ v S @ ? s} e S5 KG 5 O C ! _ $W v k y B ( ' o Aw $S L ~ ֫ + [ F a7 7 e eQ [ e = 7 Y {; 3 J + gc ^< p T # : D 0 < gO ; C -7 _ 9 Z ; 6 ; i E , P ` s J K P > M p + f Y < Q f J! . 6 Y ב {E M M 2 8 : = ֹ | R{ 0 ٻ n % % 2 m t Z_ w ! ʍ % Y E OA v Ux J _ I Of Q s! ] ' f l jZ . en B y 0 F { u W 3 n G X hz [ Tl k A F 1~ v$ =f L v G x 9 KR % x) v }0 ݷ } I - -I f ob Uu ' f : jD f y 5 t _ c j H %V I F ] <o ~x m _$ * + e ; W^ a 1 % 6G > 5? aS 'r ' i4 ̋ nA 4 9 K _ *} l? H mN t g г ! ò g [H y p p 3 K _ S k 0 ! 9 r= h s % V) Ƃ d K ] X C x P P y N` ߒ F K ˩ Fv U ! C SE N 7 ] ~ o : ) g w . M r ?` R J c \Z : z L q J M q v pr 7 AD D) K [ l { ~v ) ۛ (4 6U J O 4v O[ g p o_ \ F ]& C LC ( u T ; > > i !h 1B =6 f X - K ^ , { w% G" @ m8 ̽ T [ - ) ( m } d Y 9E Q li [ 1 4 f ̇ c 1 ' } & o QJ , W Ks g I Ͷ % \ w . | 4 | V XY i L | 7: T. [' B ^ '# X/ K V r ro f. _d #_ Q nu E H < 0n 5 G3 q , Y Q "= 2 J ̰ [ # ŗ a ; 5 [ ct M _ T V" h X C f 5 l I 8 3 H 'u 3 t s [I k 0 Z g V 4 L; `T X% ?# Q dR M Og 1 "Q j ! ! a[ 0 5 u a J - `B o | H ? ' s ]! { F (t Ӱ / = @ ( < R 5 P x Z B U Ԅ = & .L >i / l / Y tJ nj 7 V Ļ 6 C o B ) ~ Y #+ )6 ץ c o í t X 0 g6 @ 5 2 6 h G p =8 z S v. ] ; I n g X ]P ^ { j& O . & _ H A 5 g Z ] ' u B t ܟ G u j _ |X y r W a H h x | iG S K n j y f y 3 b O %< y [L s 2 % [ * A C \ d IS h 9 _ Z ? cJ ] j )s y N I Rn r & Q a \ G9 ײ L f & b u Ly X ` ͵ ,T c ' 7e k E ` 7 \ o H 4^ g - 4 . 0 L? r ] ~ l a Q0 9 2 M _ r R C ! ! !0m !ʹ !~ !* !ێ ! !( !: !g ! ! !E !>& ! ! !q !H ! !A ! ! !%1 ! = !( !~ ! !o ! !p !B !q !" ! !x !3 !T ! ! !| !P !+ !b !^; !F ! ! ! !)- !-{ ! !H( !o ! !± !h ! ! !( ! !{ !\ !m ![ !D ! !0. !6, !0) ! ! !Y ! ! ! !u ![ !1 !Ŭ !G ! !> ! !3 !G !< !: ! !T !8 ! ! ! : ! ! !0 !#/ ! !j ! !un !f ! !d* ! ! !" !0 !~ !- !o !d ! !d "Bj " " " " " "! "O " ". "I "* "tT "! "# " N "; " "E ") "R "t "Đ "n " "i% "+ "3 "hh " "v " " " " " " "3 "e{ "s "ͅ "(f " " "ɸ "Ɵ "/ " " "T "s " " " "z " " " "E "m " "{ " " "`~ "O " "8 "i0 " " " " " "J "m "L " " "L " "\ " " " "za " "O "8 " " "~ "w " " " " "P "] " "$ "Uc "w2 " " " ";= " " "7 "i\ "` " "K "P #h #+ #6 # #F #y{ # $ #& #j # :1 B "5W '\ .~_ 6vX >Q B` GXD OZ ] ^LI _&W fP j_ rM v;[ zV ~%Z LZ ' (9 * ' k ` D _ V u r c c 9 ! C U ) XE 6 B w K ? V R 3 w' r' B O v ,D & _ OZ j 5 Q i _ CR + ڭ İ 4 k " x ш !/ "py #g %į & ) @d A3 V M /E N k j P Q5{ R8 SM T2 V Y! \h a3- b-x fiI i$i j0 kDg mu oa pn q s u v w y| k M* 5 e h ) ,-.. --.. /011 4445 4445 )6 66=] BIM 8 [`v~ ~ '.Xc '.Xc '.Bco '.Bco #$ #$ #$ !!## !!!! ()++++ )) $$$%** %%%%** %%%&** &&&'** ''''** !#)) !""" "")) "")) """" "### ####***+ ***+ $$$$%%%%&&'''(++++++ )))* ,,,, ---- .... ..//// //////// 000011 2333UU 2222233333333333 33345::@CCEOOPPTUV 55;<<<<< 6::;GIIKKNOOPRSSTTUVVV 89:;GIJKKLLLLLNNNNOOPPPPQQQQRRSSTTTTVV JJJK MMMMMMMM <<<>VV >???@@IIII 4444PP 444444 @@BB @BBB AAAA AAAA AAABBB AAAAAB BBCCDD BBCC EEEE TTTTTU WWWWWXXX XXXYYY 2: ::Aa Q )6 66=] #### $$$%&&&& &&&& '((((((( ''(((( ''(( '((( g zO _ O @ Q W , pQ 9 R l ( & O H QT % \\ [ ] V [^ O H U % ) [ 5 O H A U % S [ _ @P H k jV % } [ P H W % [ Q H W % [ X Y | Z Z D Z p - 0& C (] 3 R _ j yc ? h H Bi B i B j [ r ; t 6 XQ ju $ ;v / Rv # < uv J v ` p& v iw G X& w & x x py 0[ z G{ Z * { 2 2 { F | 7 X & n 4[ y 8[ 6 - & o $ @ / W # < z J & v n G & - & ` <[ + " M H " S 1 @ O S f g H z @[ H[ ҟ x } p ] M " o A ' . 5 ު @ ) Q ' _ O n ] $ x / # ˬ H " S 2 | ֱ ^ I \ ( / H a 2 b > ~ Ѽ ) & X & S $ / # < J ` & v G & X & X & ) 0 3 X A o Y @& d l { T[ 0 ' W y P[ = - & ~ C P 8 `[ h[ @ ) p ~ C ` & . J = [ @ K Y T o [ | [ `Q [ ` @ 0 ~ C ` ( i Q . / , P8 ~ C 8 7 9 L [ T !Y d p; . n ; . ; _ +< @ k= W x = ? 0 `A nA |A A > A B C C C C C ! D ! 6D ! WD ! xD ! $ D ! 2 D ! A D I L $E ! X EE ! j fE ! u E ! E ! E ! E ! F = HF e F F F F qA F G 4 EG $ WG a : G ] S H ^ 'H f 9H {@ KH w ]H i H y ?I u I S I " I 8 +J J " J ! K /K W K + $ K 4 K 1 @ K O L - ^G L M X L 1 d u x ,M @^ Q Q xO *Q R R ES _S @ & S < U o U d d ) p #Y l Y Z ) \ \ y x] 3 _ Q h w 1i y m G n ] p q | u W 0 u I v c xw % w y = x & <y . jy @ z { a m{ p| y } , ~ J { a n ! O p K } Ȉ L / - M h j h ݑ b w ϖ o > O 5 ( [ " I 6 ̫ T K ) h t | ɷ _ a ( / W p " H ھ $ m 9 ` 4 I - [ p | \ S I , = ( 2 / Z B m { L d Y r J ~ u 3 : H ! 9 z ` f z H 9 x 7 { H V Y X) & + < ^ > m +! 1 ! { C( d $ W+ 5 s/ O I 82 Z N2 ! % o2 l &3 s { 3 46 7 k; +< < EA C a ! KF V 6 F R J F T _ GH E I P L M N N <O R R * U > 4W 5 Z i\ o R` h bj j k ) m > V~ Q w W ` Ix 3 j |y ?{ | ^ o S D c 2 L e! @ b Ő ( } y 0 F ; מ @ K ? * [ i r f g 4 x G ] ] ^ 8 8^ <^ wQ 9 h ; ^ u 3! # J \ k RB S I A ' L u D Q < R < K B_ A 5 Q E J l [ I f y u y 0 ( Y) < 1 ' H " X = $ T X * ? n 7 / / $ / S / L & Q 4 # A # W 5 # m X # { # D^ n T ! 6! P! / _! q! > ! " " ! D + ! V# ! $ " $ ," % 7 J" ' S l" #* " 4* " C " D " " tN " IR # c | !# yg 8# Ji R# j l# p ( # y 3 # :z n # H^ # S # " # : u 8 ʐ m " ! 4 1 @ j o: x / # 5 $ L^ Q $ '$ <$ P$ Y$ N i$ ` x$ Q $ w C $ ? $ $ Z $ o $ $ $ > 2 C Z ! { ! $ ! $ ; ! $ ! $ : ! 2 [ ! A | I X ! j ! u ! ( = e w qA : ] S ^ f . {@ @ R y S " 8 % " W $ _ < % P^ % I &% F =% K% ? Y% k% * y% P % F % n % ? o % c % < % M w % # & X & K %& 8& y > I& 8 b& } {& & # & & & & 8 9 & q & ' 5 ' ' 9 )' ^ G' G! b _' ! u' # ' $ M ' )% a ' % ' )& & ' O' M ' wQ ! ' JQ ( / % ( / .( 92 @( 3 / N( 6 b( {D u( wG ( G ( wH ( H o ( Q m ( 9` ( V U ( Uf b ) r b +) | B) y ~ V) }} n) J ) P ) N * ) N A ) >O ) JP q ) `Q * T , * 1U 0* sW g @* W U Q* /X F g* uX T y* X / * X * Y * 2Z q * Z > * Z * q[ * \ + \ + H] .+ ] _ ?+ A^ P+ ^ b+ _ u+ a + f & + f [ + 8g + g * + h + h b + i , n (, _p 6 >, r Q, Xz q, a{ N , J h , , ϊ , , " ! , S p - !- 8 $ Ǖ " Y$ +- A- X- 5 o- Q `$ n - " - - N - ٗ , - F - K - g a - ș ] . % . 0. ܝ E. k. . . | . m . E . \ . p . Y @ / ( / ( '/ " 7/ o 9/ < E/ b X/ i/ | |/ < " / ^ / N / / / / T b > $ < 0 - 0 . &0 + W <0 b I0 \0 > & = ! ^ ! ! $ ; ! $ ! A I j f ! u ! qA 4 , $ > a : ] S ^ f g0 2 K } y u k 8 F " h p0 hq) y0 xq) 3 < 0 " 0 2 0 ) 0 ? 0 0 * 0 z 0 1 1 1 B 81 < l P1 i1 , 1 ; 1 1 1 1 1 J 2 . )2 A2 T @ T2 I k2 ( T 2 a 2 | Y 2 . 2 2 2 3 3 } 23 p J3 8 I `3 = v3 - 3 G 3 H 3 3 3 4 e $4 `^ .4 X =4 d , O4 $ c4 g& u4 $7 u 4 ' 4 ) 4 D+ [ 4 , 4 U. 4 0 ? 5 02 +5 3 o I5 < y K= 8 = &> " S5 H> e5 9E q5 WE C 5 O 5 P 5 T | 5 X ^ 5 uZ Z Z > g0 Z K 5 ,[ < 5 h[ ^ 5 ] L 6 _ _ ` ` ! $ ?` ! $ `` ! L ` ! j ` ! u ` ! ` ` S a ^ a f ,a >a y a S a " a 8 .b b " X b 1 6 h @ +6 e A 76 f 3 C6 r X6 o6 - ` 6 6 % 6 6 7p 2 6 ip , 6 q 6 5y 7 Q #7 ?7 m P7 "} o7 7 E 7 G I 7 7 q w 7 7 p 7 j 7 g j 8 э E 8 '8 ^ 68 D8 Q8 1 F k8 w f8 . z8 8 } c 8 8 m 8 d 8 \ . 8 1 8 > 9 #9 39 @9 J R9 + c9 _ u9 y ; u 9 % 9 9 9 Q 9 A 9 L 9 9 R _ 9 n 9 T : s 6 : /: K / =: z K: K [: ` j: 8 w: : : : : : : [ : ~ : : s ; ; 5; A I; \; h t; ; ; ^ ; x ` ; G ; m ; $% ;% L% c% ! % ! % ! $ % ; & ! $ "& ! C& = & e & ; & ' (' qA :' L' 4 ' $ ' a : ' ] S P( b( + $ ( ; ( t ; ) < ) < ) - 4< * $ O< 3 j< 5 < 8 < = < XB < BC < 6D 3 < iG = G [ 9 DH T = \ 4= ] I= _ I c= e .e <e \e > e y f u f g0 f K j= `T = Mh = i . = k A = Ok 0 = m c = q a = Cr x = r > ߋ > $> d} 9> O O> R " ]> t 2 l> 4 }> > ُ > T > > ɒ H > > > \ N > i ? ? ? ɛ C 1? C? S? ܡ `? ʢ , o? ? z? u ? 1 ? | ? p) ? 2 z ? ) ? ? ) ? ^ @ ) @ )@ ) 0@ з M@ ) T@ s i@ ʷ) p@ @ ѷ) @ @ ַ) @ Y @ ] @ = @ ſ ) A !A ) (A ? 8A PA fA s |A ) A 5 A ) A ^ \ A @W ` A A p $ ; A A B ; B } AB ` aB Q B 9 P B B @ B Z B + B ` B Í B ^ C ` x C &C @ x 5C H EC VC ` gC |C ` C C C r C _ C _ C @> : C _ C z> ( D @ D _ D > + $D ` } +D X 4D > + @D ZD X eD [ wD [ D > D D D _ D _ J 0_ D 0 .D X D D E E @ /E 1_ .D X 9E ? Z YE ` .D 4_ mE }E +D X E ! E E _ E E 4 E _ E \ F , ` F @_ F \ )F P @F č ` QF @ hF uF :K a G `! . F ` ( F ` F ` 0 X F a F `` 0 F q@ F ` F ` ( F @ 9 G uF ( 8 :K hb G ) F @b ( F $a F a 0 G xb F a F b 0 @" @ %G " Y F pb <G @a ( IG a ( XG @ 9 nG uF / 8 :K d G / F c ( F b F `c 0 H d F b F c 0 G `0 G @c G Y $ @ G $ b G d <G b ( IG c ( G @ _ H uF @9 8 :K he G 9 F @e ( F $d F d 0 G |e Y F d H xe F e 0 ' H & F pe 3H @d ( BH d ( TH UA m mH uF @B :K lf G B > F @f ( F (f F e 0 @Y F hf F e 0 F A 2 * }H * F pf F f ( H xf H A 9 H H pJ B uF J :K g H @K [ H hg H g - lg H xg H -B 9 G L D I g F @g ( F (g F f 0 O jg I ig F f 0 F fB I N I g *I g 4I g :I g CI \Y HI yB , VI , `Y F g ( mI pg xI B I uF [ :K h G P\ v F h ( F h F g 0 CI dY H h *I h F g 0 1 I `1 - h :I h I h hY I h x mI h H h I $C I I 0i : I h J pi S J pY 4 B 4 +J h 2J h 9J tY EJ xY QJ lY bJ sJ pp 3 `7 B @7 J |Y J Vv @r : J h J h @8 B 8 J Y J Y J J v h J i Y J w J x K i !K z :K i LK { cK | zK P} ] J Y Y @ō B `9 K K P 5 Y B 9 9 K \ T Z J Z K K > K c P M L C , K @ȍ K p= L C B "L Ǎ 1L `= >L 7D n [L = B = J Z fL i nL i vL L L `> > .D Z L 0i L (i L L $ j L P L L p D i L ! ɍ M P? Cn \ PF M @? M "M S 4M ` CM 0 . \M ` oM u zM )j M (j Cn @ M ` 0 M M 0" ; :K k 3 p" M M # ; :K k M # 5 # M k :K k M h$ ? 8% M :K k M % ? & & M k M ' 2 M G' 7 M ~' 3 ( x N N 9 z x( c N 'N @ ;N KN - YN oN ~N N N N N O _ 1O 0 SO 0 sO 0 O 0 O O O P P >P WP ` yP p P P M P ) < P `! P # C P $ P `% | Q % Q & { &Q @+ LQ , YQ 5 # {Q 06 K Q 7 Q 8 Q @: ( R p; A R ; A *R < h DR < YR @> wR P? [ R A R pF R G } R G } R H } S H } +S I } JS I `S @L mS M S ? S M S B S N S O S T e S Y S _ S h T pm T 0r %T v 5T { JT F ]T F sT @ O T 4 T Ј T h U P h /U PU xU p U 0 U U p V @ >V 0 jV V V V W 5W Т ZW mW Х W W W W Ъ X 2X `Ŏ FX QX `X vX 0j X D X X N X X X `Ǝ R$ X N Hj Pj X D * Y I Y ,Y p e OY nY J P Y p Y Y J h Y I Y I Y Z 0 H *Z ǎ @ FZ `Z Z ǎ @ Z Z ) Z Z @ V [ 7 &[ : A[ R[ Ȏ d[ r[ @ [ D [ Ɏ @ [ [ P p [ [ \ 3 .\ 8\ O N\ p 9n a\ p E q\ \ `K \ J \ " \ @$ \ ' \ - R `0 \ ʎ \ \ 3 j ] 3 _ "] 6 8] PK \] PJ ] 7 k ] < X ] @8 ] `< L ( ] = = ] `= P^ ؎ 8 ^ `C &^ @̎ 0^ F C^ `؎ N^ ؎ @ \^ ˎ m^ `P ` ^ P ` ^ O ` ^ @O ` ^ N ` ^ N ` _ N ` _ M ` 9_ `M ` Q_ M ` l_ R ` ~_ @R ` _ Q ` _ Q ` _ Q ` _ P ` _ _ @T 0 _ `S _ S ` ) p) ` `ڎ H ` ڎ H ` `َ (` َ H 4` A` PQ R` @ f` `S v` ` 0Y ` ` P^ ] v` ` ` i ` u D ` ` Pm r v` ` k ` x a | a a ` ` Е 1 v` ` -a =a Ѝ Qa Б a q ` q ea ra a C a dj a pj a lj a hj MG 0 A a O a У a `j a p 1 a C 8 a tj -x 6 a 0 b -x @ 3 b *b xj 8 0 2 2b p Fb Kb 6 Wb 0 kb y wb b k b b C ; b j b п E b j b W b b b 0 W c c #c k +c D :c 5 j Sc E ) qc c @ c c 6 c @ c k c c 6 c d d 3 d +d @d Sd +E kd |d d l d @ ^ d d d i d @ d e 7 e 9 p ; 9e 0= Qe \e 0? se 3E K e ( I e J e K e M ? e N e O e Q M e V 7 f `R f 0T 9f @X d Mf ` Bl [ 4 \f \ uf ] f `` f a f a f f Pb g c # g g 'g f f @e :g Hg Ph Zg ag s pg x {g d g P d= g ` P g g H g g : h @ h h @ )h 0 Z 9h Jh ch P J h h h T 0 h h @ c h h ` Q h h h P i -i >i Gi [i fi ~E i i i 0 i i i ` 8 i i i k j j A 3j 9j p 6 Jj 6 Zj ` dj sj m j ` j j 6 j j j o j k @ 3 'k ] >k @ ` Pk $ U `k @ kk : ) ) ~k W k k 9: @k k k k k , k k U P k l C l F l @ (l 6l =l Hl Wl dl U @ ll 7 yl P | l ĸ Hl l l `Î @ l Ď ` kd =a + l l . O . _ l 0 l 0 m 1 :m @3 x Wm 5 ~ vm @7 u m 8 m : m U m m = K m ? ) m n H T ) n H T ) n @I ; (n ?n ) x In Qn \n E pn 0 n 9 n n P 5 n P o 5 #o P =o p d \o < w V o o o n o P+ o E o E p ,o `- 5 yn - 0p @1 Kp 2 ]p ep < 8 p = 3 p `= 3 p = 3 p = 3 p > 3 p `> 3 q > 9 'q > 3 7q ? H Lq p? rq @ q A M q B M q pB M r B M ;r C M \r `C Q }r C P r E r F , r PG r 0I X r I : r I Q s 0J (s J - ?s M % es 0N s O s P s n s S T s T t U 7t W Tt _ k mt 0g t i t m ] t o t s / t | u u ` 3u Gu p [ Vu Ї eu % u u = u u u 7 v l &v P ;v Uv v mv v n v n v P a v ) v ) t v `) e v N v ` v v 0 v ) i w w ~ 'w In 3w ; @w @o Pw ` \w o < bw <o iw j ~w 8 6l v c w `o 2 w w P w w 1 w w s w z w x a x 3x Hx w Zx @T 1 lx T 1 x T 3 x w x 0X 1 x 6l x Y z x pZ x y y y ] 3 "y ] 3 4y ^ 3 Ey @^ 3 ]y ^ 3 ty ^ 9 y _ 5 y @_ 3 y _ 3 y _ 3 y ` 3 y @` \ y ph y Pa z 0b z c 3 #z @c :z d a Ez pi Xz m jz q |z u z y z } z z z { { M *{ M ={ @ M P{ M b{ M u{ 0 M { M { Д M { M { p M | M | M 1| ` M I| M ]| M q| M | P M y | p | p = | | } n !} `n *} @ K} w g} p & } } } } ` } ` ~ ~ ? E 1~ E~ U~ f~ |~ ~ ~ ~ ~ ~ j ~ * 0 8 + : k L U ̜ p Ȝ - ( ? $ c ( ; M @ ` ` r P p [ Հ 0 R @' # @ ` + 5 K e! b P v ( 읏 ~! ȁ ݁ $ 3 $ $ ? # Д$ ( 4 (0+ @ $ Z .+ e $ n $ / 0+ $ ( آ /+ ̂ $ ^ .+ @$ 0$ 0$ . P$ D p$ F Y $ N q $ ^ p$ F $ v @$ W ȃ /+ /+ $ p$ 8 " . $ > $ V $ o /+ P$ F $ ? /+ 0$ 1 袏 p$ V м$ ) p$ > P$ W p/+ c $ P.+ w <H 6 $ 6 .+ 0/+ .+ ƅ /+ х P$ /+ p$ * ` @ p.+ P/+ & Qn 6 @ < D 7 S 1 k 3 @ 3 E xt - ʆ p ׆ 0 " ` > } = ht I # - ) k @& pt Y ) W n 5 o p X ԇ pp S q & s @ @t $ t A u 0 X t @ ] `W ` k y p s ֈ @ t p | ' t [ . j B ( S a p) ) `) p c A 0 $ lj B7 Љ ۉ P L ! W " P o B G ; K F _ ` Q w P L Z L ` 3 ي L @ L * E L Z ' { 1 ; ` ; Q N ̋ c ۋ @ _ 0 o ( 8 I ^ w 0 Ҍ ` p . 0 - : p 5 ` C @ P c ` u P J - I p P H H H ɍ ` @ Ս @ ލ " ' 0 ) + P 3 @ F @ Z = ` X } t X [ Y Y ] H u 5 v 5 `v @ ؎ Ѓ ( / @ I 0) E o 8 F { T f @ 3 1 ` I W " q 6 { F `_ b u @ T ) 8 &F Ő 0F ސ OF # X P @ 8 .- ` 3 rF I ( f Y {F n H n ~ B C H Ǒ ґ oN P Ї C . l y h 2 { d C @ b ) T @ B i _ ǒ ג ; a @ b 0 % 2 j 0) d > M Z c p y g n m @8 y < Y ͓ ד F P 0G G 9 L & M > N U `P 3 l W q C P) b @ԍ ` n ~ ˔ Ȏ ޔ 0 y Ђ ( H @b ( ! ( : 9 @ [ o w P E x ̕ & * C а б > + в R > 0 [ 0 n b ( Y 0) ) | Ŗ M ۖ ` 1 `) D & 3 ; J X I i G t ` q t i ٗ @ } } " D N v H : 1 ߘ 莏 00 a 2 V v `@ 3 @ 3 . @ 4 @ A V C l D o } E W `E W E F I F I @G I ՙ G PJ I J P J P @K P ' K w 4 L P ? `L P M L P ] M P l PM N z N ' O P R ; Ú S ך T I U 4 W X ) < X ? / 0Y x Q Z d [ \ ] p u @^ () ^ ` Y ) a 3 @a ܛ 0c 3 e k `f o @) j & l 8 pm H @n [ Po o p v > x k x k y k py k Μ y k Pz k z | ` ) ` C > V y e x V @ T ĝ \ ҝ F V 1 p B S a й u P D 4 p $ ɞ ֞ 0 9 ) `) @ ! ` 5 ` P K Y \ N o ` I g 0 i Ɵ ԟ E P ( ) ! @ / P H ` j R F a B u d ? e p ] D S ֠ { l + -G M F 0 H X p% ^ u @+ ) P : zG ͡ ( { ١ 0 U V % @ 2 < _ D S _ @ l 0` E ` * d @e Ȣ e Wl j m `) pr ' g > a ` 0 n ( , ) ` L . ٣ e h u 4 E l f u @ ` V c 0 7 Ҥ Y ) ) ) ۤ ! ? ! ? ) " ? < @" ? V " ? " F % i ƥ % i ޥ % i `& i & i * @' i H ' i n ( E p( d ( : Ħ ) k ڦ ) h * 7 * E / + F N P+ i + , @ - y . 5 ʧ . p2 a 3 m P4 6 0 6 P @7 u h 7 ~ `8 9 9 : ר P; ? ; ? ; h = - > E I p> e ? e p? u ? u p@ ʩ `A ] G f R / R _ I S \ ] t pe 1 g q @h Pl $ x) ڪ o p * D 9 @ E L P < d H n j @ } k h = k x g! ǫ ; w z 0 y P ߫ S `z 8 y X { T _ $ H / D ` Z G t @ \ ȑ ά ج 4 ` 7 in ` ; l . B ? X , o P G a* ) + m* b í V* ʭ k* : ҭ l* ح ** + ߭ w* ) P0 % 0 7 * G * r N * V * r _ * g * s @* G x Ў* * G * * r 9n @\ ] ( ͮ P^ y Б @ ( m H m g `n `o pp + u u ʯ z ү ~ i ` 1 ( P G S Z S ` S p Ы s P v ɰ ݑ ݰ ޑ Y 0 ؑ # J ܑ n ԑ B ? G `* $ * $ `* D í * $ ʭ * ҭ * ح * D G `* N * V @* _ (* s * x ;* * 6* g * ͱ ٱ X x {C ` P ǚ h p > P 3 5 I 8 U _ p: q K 3 L 1 @L T ߲ L T M T `M T > M 3 V h P d k ~ 0T U 엏 ij ˳ 䗏 Գ 藏 ۳ ! 2 `{ d @e y $ o E 5 o o D `p E [ p E p q = ~ @q M q = q = r L δ `r = ݴ r | s | `t i t q " Pu r 0 u o @ @v = Q v = c v = y w i pw V w V 0x = ҵ px l x l Py = y ~ z v . z ~ = { D M `{ S b { S s | & P} } L @~ V ~ V L P a 7 O P S o p P ` L ӷ T L ` T = L ^ T p P Ǹ p $ n > P X P l r e 0 l q _ չ P _ " @ D \ g ~ ` 5 @ κ P | Г | P | Д | 7 P | T Е t x P p P U ӻ @ L p ) P E a q v v ȼ f b b 1 Y H 5 Q 0 5 Z p u @ 0 e ƽ p e ֽ ~ 0 3 R P e p 4 m p } ` Ͼ p # 6 p l L Z n ¿ p տ p p q 0 : ? U G u ? G G =6 b $ 5 ` h F V Y p 0 ` m @ P 8 y 3 5 $ < 7 @ U P d m u } p R n P z ` 0 1 3 K ' i 0 3 p 3 ' ) V . p 3 R ! 7 ; P8 l X 8 w > B u @S . pW s `\ d d e 0f < @w F 6l N `x ^ z p 0{ z @ 0 5 p } * ' P : j E Q p _ ` o { @} ` D R p 8 P y } - 6 1 B 8 O G q @ ( x p 4 R 1 1 1 ! 1 1 @ 1 ? 1 N 1 ] 1 n @ 1 `~ 5 1 - ! " g " # ? @$ T ` P d * ( u & J @/ / 3 2 2 " 4 6 7 `9 @; ? P= z > ] H t 0N P i[ v Px * $ (* * G * ( H E O ` \ i @ v H @ A 0 J ; b 2* l _ 8 )p ` 6 # @ k 2 < y d { ` L h ! U a i x @ P 0 t @ M S `O < G W Q X h Y v Z [ \ P] 2 ^ @b z c e { l 0q ' @ > 6 Y r } @v B v w x ] T ~ ) < R p k > І ` Њ t P [ + ` ` % ` S : C Z o Q 蝏 t @ ` P & ` 8 T q @ c p @ : S O U g ~ 6 + `+ @+ $! B P$! %! > @%! &! 7 (! + + N P*! 4 q +! @,! 2! 3! 5! p6! 9! ` 0 + 5 @=! B O =! c p>! { 0?! > p?! F! A! e C! E! C G! 1 J! % K 0L! _ @ + 0 l R! I PS! V! T `W! X! y! 3 z! 3 `z! 1 z! ? * z! H 8 0{! X + j x `! 1 ! 3 ! B 0! + 0! ! ! ! ] C ! + ] k ` @ 8 X P `! : , 3 F ! b Z ! ~ r ~ P! e ! I ! ! z ! ! p! ! * ! * 0 ! : G Y ! f s `! d d p! 8 R9 p @ ( ( ) ! W = I ! s B ! ? S " l (H "+ ` + ҭ #+ $+ ح @ + í "+ ʭ #+ + ~ " G (+ N &+ V (+ C s &+ _ '+ g )+ `&+ C x e(+ 0&+ a(+ Zg ج 3" s 3" ; 3" h { ++ ++ ƅ ++ Z *+ *+ *+ *+ Y *+ *+ *+ z" I Pz" B z" : " ^ W " b 0" j Ѓ" Z ++ ++ ƅ ++ ++ ++ h++ " P++ 0++ " 0" " ` 0" ( 7 E " a P # r `# # 0# L ( # # # / @ # K # l # # x @# X P# # \ E# R 0G# % J# k > S c r @# p # # ! # # L Г# q P# # # g . p# C `# X # k # ~ # # P @# @# # 0# # $ `# B N P# k c # y ~ @# # `# # # p# V # " # ? 8 P# i P # l # # `# # 0# , > N @ ` ` p ` $ J ݍ 0 p $ $ > $ Q P $ , $ m G $ ~ a $ A x `$ $ $ @]$ / p^$ 6 ^$ M _$ M P_$ M _$ L 9 _$ { 8 0 c$ E `d$ = \ d$ A r d$ } f$ Q ph$ ` @ i$ P Pi$ 'y @ { X q$ ps$ ? 8 t$ / [ u$ z v$ w$ y$ z$ , < % I2 P ` % i 81+ >i s r @ 0 $ li rH H1+ h ` X H% PJ% n E K% < `1+ Y 1+ " 1+ $ V b l 1+ _ r a% ! ~ b% v k k% @ H 9n po% \ o% \ 0p% [ p% 5 p% pq% 3 r% D r% 5 R s% a ( m ! ( y ( ( ! `( 2 ` @ P j @ P 2 {% ; = }% ] f Ĥ + @% 9 % E Ȥ P _ H @ x Ф ੍ 2+ D < r % 5 @% % P% ! % 9 p% Q % j @% G ~ % 2+ @% `% % p2+ ए ؤ `% 6 % 5 % @ `% M 2+ X % r @% % `% % % 6 0% % / % O P% l % } % - h . \ P% p% T @ݍ P & p 3 W " ~ + x 3 x 7 @7 , 47 0 (7 ` 7 ; ; c @W d P d > P $ m O dO @N $ D < ' < h I ; h l h h h X @ ( 3 l S 0 s y o `o d o 0 l X 8 8 Y x 8 H Ć x + Æ < Q Æ w Æ Æ ` @ < 4 8 Z ~ 2 `dž [ 0 ` T D R ކ X x ݆ ۆ ؆ Ն ` І = `φ e φ 8 Ά d Ά p ̆ $ \ I ` $ l d L $ ` B e ` ` L H 0 ( 7 ( Y " " * ! $ G # r # # # `# ` 0 ? : a 9 @7 `6 5 5 3 P ! 3 D 2 f 1 ` @@ `S P t M J ' J F H ( e E D B `B T Y [ . [ $ O [ d q ` @ ࣇ \ \ $ # C Ĉ p $ @| D s h g h g x 6 e V x L ` $ P x ʇ @LJ ? Ç h ^ ~ ` \ ` L # < D @ e @Ї ҇ ҇ ҇ d ҇ ҇ * d Q < x އ އ : ݇ a ݇ `ۇ ڇ `ڇ ه ه A ؇ f @ x @ , < ^ ` $ 9 ^ @ T D X ( M t ` ` @ 8 4 d Y p * , + 0 0 0 ; / ` j $ W Q ( I @H 0 @A : 7 ` 7 d 6 0 `4 P @ ঈ 9 p Z ` | \ X + ` H N @ q 4 ` ` @ p % @ H @ k @ < 8 `ň @ň ň < ? Ĉ c ш 8 @Ո ۈ D ۈ 4 @ֈ 8 ܈ , @ ; D V 4 r `݈ @ ` 4 @ 0 | , . 0 I d @ , @ 0 t # ( G , i t T D 1 @ P Q @ u ( ` , T T H x < # I q H I 2 PI H [ T { I ԁ % 3 % | 2 @% < % % % O % % ; 2 D % < \ % r p% O % `% w % p% % % J @% h : % z P 0% Q f % w 1 `% 1 ( `% O % @% % @1 % O % P1 ! @Í 2 % J % h \ p% n 1 w % 1 3 h V J < @@ C G 1 N G `R ] 3 o 6 8 : @ 3 @ `5 P / ! 5 `/ ! @8 @ / : P Q / f < P / / " > / A 0 @E 9 00 N H g P0 @L 0 p0 P 0 0 $ T 0 X ' $ 5 b y K \ )^ m , v 4 * 3U ] Y b] P l N L Z L & 4 / L 3 f 1 > e K _` P d c o ( h A ! U ! o 5 4! >* P! . M c! 0 # x! lN ! D ! P ! ! ; ! x ! Q ! " Z $" G 3" ' c C" % J X" 3 s" ӧ A u# 0 " # 1 " Q " " " Gq X[ " # x e # +# T ?# u N# " : `# [ t# M {# # n # * # # p # # $ 7 n $ .$ =$ _ & O$ _$ \ j o$ k $ P& $ : $ K # $ $ $ W $ $ [ % 0 ! % % 1% - 9% X M% { a% " x x% ' % " % ځ % X- % % } % 8 & & ( _ 9& Qt G& R& ) 7 f& v& = \ & < & ! & = & H O & ? & c & ' 9 ' f %' n { 4' m =' ] O' ܒ N a' v ~ v' ^ ' ( ' =) ' Y ' Y w ' H ' f K ' q 6! 1 8 ( S ( t 9( L P( ) V i( L z( - ( g ( ( ! ( 0E ( Z ( < ) ^ () n G) ; 3 ]) V ? w) 2 * ) N ) 7 ) + ) ) & 3 ) } ) S * * ` (* @ A @* W* < h* @ v* p# * M * ( * > * Q * 5 * P * + X %+ 7 8 ` a 1+ @ @+ A U+ p f+ ` 0 + @ 8 + 0 P + p% + Д + + 0$ c + , `` 8 , | ( /, Pe Y H, 0# Y, \ ] x, % ` , , [ , , Ь V , - _ (- h" q 6- " : O- 0 h ]- m- P% : - O n - - - : n - O . & . ` 0w U ?. 0 ' U. P k. . p . @ . . w @ . ` @ . ]" x . / / s" Y $/ @* :/ N/ L ]/ [ o/ e / / ! / / / / 5 / 0 ` l '0 g =0 R0 o e0 3 y0 P < 0 0 к 0 ' H 0 0 pN 1 Ў 0 %1 P) 61 Z B1 U1 ` i1 }1 P 0 1 1 * 1 b 1 1 2 G 2 22 5" p >2 T K2 V2 B s g2 @ q2 2 2 b! 2 X 2 2 3 & 3 3 03 B3 5 T3 P Z3 P q3 q 3 0 3 o 3 3 o V 3 pY V 3 3 4 ` !4 6 +4 # s 94 @ O4 _4 # { t4 4 o m Q k 4 p 5 4 t O 4 4 4 H 5 4 d 5 @ 5 r ,5 b ;5 ` O G5 @Ŏ [5 `5 t5 @V n 5 5 5 5 ! 5 ( 5 5 6 @ @ 6 % Z p a <6 K6 p$ j ]6 " \ ~6 Y 6 R 6 R 6 ! 3 6 ; O 6 ! t 7 p 7 P' &7 =7 H M7 6 `7 @ @ ' PS# u7 yQ 7 l 7 7 7 Y 7 7 @ 8 * 8 `* + 78 Z M8 q X8 * l8 P F |8 0! l 8 ^ 8 н 5 8 8 8 @ 8 9 % j 19 M9 ` @ Z9 p , 0 i9 z9 9 d# 9 T 9 # B 9 9 9 5 p : %: 9: # B I: @* _: v z: G : : W : T : : ; > ? ; 0; @ M E; Ы o `; n< 0 r; Z |; ; 6 ; * 5 ; @ J ; ( ; O ; s < Z < 0 j ,< ߎ @ D< @ X< P b k< :n < p < < 8 < < P < y < s = p 9= y V= ʎ @ m= ` 8 = = = k = = = > @+ > j %> @ P ` ; 5> A> " Q> p> ` z> c# > " p # 1 > > ` m > n > Pc C > ? " # $? K 6? " p f V? z l? # a {? b ? ` c ? ? p ? ` @ ? ? P @ %@ pd "I @@ ( Q@ ` j@ 7 x@ @ + @ @ @ @ @ 1 A .A KA j WA J mA P P {A A A 7 A F 2 A A ` 9 B h ~ $B <B PB cB tB B @ B Pp k B )U > B B B @ B 6 C @ p "C 5C C NC P B i lC 0 c C t C C i C ގ @ C n V D D ! ; .D C >D nX QD @ [D hD |D D d D _ D f D D E pu" s E ~ !E 5E 3 j DE ZE c kE }E E Q E % E < w [ E u E E F w : $F % GF WF n pF wK D ~F B F ` z F 3 F F c F % G 1G H AG $ UG u R gG pp" s uG G G G G ) G P ; ` $ G ޒ \ G H *H :H pt @ SH bH p yH _ H 02 C H H 6 H m H P I I 5I BI " |) 5 ]I `( xI ` @ I Pk I I d 8 I P% Y I P J $J `g J 8J P RJ _% dJ Y pJ P J J :h &W p b J J J a J h K @F & K UV *K ^ = ?K ^K 9 $ oK f K " / 6 K K p" s K K K K L И L / /L AL VL 3 rL P |L o L L J L t f L " L # Y L ! 6 M e 0 M ` 7 :M gU H TM % kM 9 M M i M M o I M o M M N x N P 1N CN 9 + WN pN X N 0 N s 4 N 8Q N e 8 N N P O )O p Y QO @ fO O ` 9 O 0 & O y O н O ` O O 0 P `" : %P 0 ~ AP ] PP U > dP < P @A P * P P 7 X P @ P @ P y Q $Q @Q Ч! 9 ? TQ % jQ = Q ! Q & Q L Q @% Q p 8 Q ؍ % '% Q @ Q ` R G * 0R =# T NR R} ] aR i wR `! K R R R R = R R # R ^ 8 S ! a O~ 0S PS 5 ]S 0 iS ~S S `; S h d S ! U S @" : : S } S w T Y% q .T 7" LT ` @ M 5 \T qT b T P T p 8 T T I T > U pK \ ,U <U в IU dz > [U + o lU x 4 U H! U j U U \ ? U @ U E" U V 5 .V 0 7 <V } JV * hV @ uV 'Z V 3X ; V `t V V V V @- W !W 1 4W UW @ = nW % t W P M W p t W I W I + U 06 ` W z% K W X _ X # &X P# c 8X ໍ 0 LX _X к xX X @ x h X 1 Ρ S X ! 4 X X R @ Y 'Y :Y LY nY Y @ Y } Y p Y Y < Y + g P? C Y F Y y Z o 1Z n 9Z Р LZ _Z r Q rZ Z % l Z Z U Z Z "$ Z pj [ +[ 6[ [ E[ p4" U N[ d[ o O t[ [ [ " ж [ @* [ P [ г [ V \ Q \ 3 '\ l =\ * P\ ` 8 h\ , z\ 0 S \ @ \ \ 3 ` G \ * \ о ] ] a> { &] 7] `] r] & {] * ] @ ] c ] ] x% ] ] ! Q ^ P" z ^ $ 0^ @ F^ ^^ j^ w^ @B# ^ :k P ^ ^ ^ ` B ^ ^ ۥ _ +_ P p E_ @* [_ t_ _ 7 _ _ q _ ! _ ; B X _ _ t" s ` ` ` `K _ -` @ G @` J U` m` ` P ` |! ` ` ` F F ` ` a %a 8a ` P Qa \ ja a a Б Z a a ! @ a A a b Ȏ @ )b @b @ Sb p jb r \ }b z j # b b b b @* b P c c (c : 8c " $ Fc д ? [c ݍ @ jc ~ c c c ]% c c 2 c ` d _ ` ,d / ?d @ Nd 6 \d @" A pd d d d N d d @ e e -e @ >e 5 Qe 0 w @U @ ge * ye 6 e 8 e Z e % e e r e 3 1 f ` !f p] V 7f Tf ` hf f 5 j f @! 5 f f s i f g g Z ( 7 (g Fg ຍ ^g tg g @> ` g 0 g g g F g g p 0 Y h j" + h p %h 8" 3h d Eh " 6 Oh `/ i gh Ѕ < h 2 h k 3 h $ h 8 h # h : h P i 0 8 -i 0j ?i ? Yi \ ii p ` |i i i f i e i @ i # ^ i j p a ,j ' ?j @ Kj \j yj p : j 7 b j y j H j 0 d j x% 8 j j ` k X "k * -k Bk = ]k 0 pk ` k `A t k k 5 k ཌྷ p k C k 0 k o ` l 6l X Ul sl l 0 l l q C l l l P p m P&# g "m } a @m 0 3 [m S qm | m n# m m m m Q m l O m n +n @ 7 =n ! Tn hn P vn E V n 0 n Q n y n n ` n o л )o @x" :o So lo N @ o ( o ^ o * o | o o _ h p Ke p 4 %p 6p Rp ޮ U cp u ~p @ X p Q l p 0 b p p p R q @ !q (q " & 9q ` @ Qq ! > aq c q @i q @h" j q q м q Y X q ` " q R r S kC !r @ 6 7r ]r W sr r Z . r G 4 r r r ` 3 s l !s 8 .s E i Os ,7 7 ]s os J s 3 l s - s s s p s 葏 t \ S t H :t Rt @ _t * i vt Q t @ t ! 5 t t t ; t u 5u Uu B J ou `A < u #_ u RJ u : u P<" u Q u " 5 v L & v (v :v Fv ` _v pT$ }v v v v @" v p v w T ; w 3w Q ) Rw 0 fw Mf , {w w w ! Z w p0 h w w ` ~ w x " o x Ю M +x ;x G Xx 0 w dx }x 1 x c x h x p * x F x x _ 8 y ! !y ! H =y P Zy hy ` U sy U y y @ y ` y y ` Q y G # z 'z Ez C Xz > jz K + zz z @ 8 z 5 z @3 } z @+ z z l { , #{ @* 9{ ` @ N{ 0 ` d{ ! c { k { { { `! 2 { / J | I | pv" s /| # K| Q Z| u p| | Z E | 3 | + | z | @ | $ } } &} D} l X} q} YQ } } ! 3 } % i } 6 } ` } ~ 3 ~ 0 !~ =~ N~ a~ ~ 0 b ~ ! ~ ~ ~ ) ~ Ɏ @ ~ p V p ( Q ? Z @* m 0W% Y o `Ȏ Z . Ǝ @ : ` K ; ] @ 8 s 1 O s ׀ U $ H 9 U K m h @ Ɂ ` 3 ׁ * } @* ` ! ! ; ` I pc 8 ^ p 6 q P ` * @  0 т ނ Q ( % t X! ̑ P > ( o" Y ; ; U h y > < 4 K J @ H à @ ڃ p ` [ c D J f ` 0% } 0 + Ä 0 X ߄ $ R : M ' S 1 R e `C m z P l @: 9 % х p 8 @ d . K h O a 0 3 t gU ; $ p ц x P" P? L . # F : ! ; T g @ g ~ N j 0 @* ć _ ׇ p# q & q 0 T 0 K L X PZ g u 蘏 " 7 # .% | Ɉ F ߈ @ + ǎ p ) `! . A M P W m m ~ E H eT 0 Ӊ @ێ @ r ` t - ` B ^ 0 x n H P r ֊ `ʎ x P 5 ' ! I 4 I L < j p& q @ l Ц . ϋ I ߋ T ~ < 0 ? \ T V I c { e Č 4" Ό @ 0 ` @ 5 p C F _ r b p @ ܍ @ @! ; . 3 - 5 L | ` z p % ˎ , ` V > @ 6 . m D ~ X k hd . { 0 Ƶ k L " d ɏ ޏ | n o 6 `ˎ H # J _ p p y Q # Ȑ ` @ ێ @ - `W # @ 2 ` > &\ W : 9 p 0 @ 6 % F ʑ = p< k 3 b @ o # > ` P T @ q r > Н ɒ ܒ 0\ l V ; % Z 9 R m V 6 # i 0 2 ȓ _ 8 V ; @ 7 p 1 H ^ { w T 3 Ɣ p ܔ ' b p = $ `" @ S d q u L % R @* ` ɕ & 1 ` ) d 3 8 pq" s E * X j ; ~ ` & 1 Ԗ @ @ P) n 3 C [ Z w x Y V ] i P 6 E W Ǘ ܗ : ` @ # : 5 Z @ 0 c M B e F r| # g pS _ Ә 7 ! ߘ 0$ Y ` @ U / " Y / 9L : _ N g ' c n ` . `" " ' | h ę $ = љ l ! { . $ C @ h Z > j @ z $c i N @ q К ގ @ ` S w" w ) `^ q ; @ H ; r i @ { o > K Û $ ֛ @ k ` $ } $ 7 T b9 5 i w . 3 Ӝ , L ~ <z G B R `W f o w U i% ` ̝ { 0 } 0 i , 0 * I ` U 0 6 p ( > 5 pS @ Ҟ pb & @ Q ? @ S +F @ g n } t p ޟ p 6 ` @ \ 5 6" Z )# 0 Pr M i @ a _ Ѡ ; ! 6 F% ݎ @ * . 9 Q , K c 1 p$ z _ @ + 5 С Q ( p\# Z K g | x = @ K `, ` _ v @* Î 8 P e @ Ţ x Ԣ a 5 `" p " ' A ! Y k i b# 7 ϣ H @Ǝ 8 ` Z O | - # : 9 D P m ~ ) ) i @ & 3 @* Ӥ 1 0 % a pg ` 2 L _ pO n ^ ` C @ D ~ 7 ץ 0 T `* - 0G% B 2 X v % r ~ ` J # Ѧ ` 2 @ # @ 6 @O K q 3 x @ Z EO g \ 0 M d § @ x p | 9 f Q Z ) s < T C C G è B J p `e ! ] C @ ` T L i | p k Ω L ک 4 w w 7 $ * & 9 ߎ @ W i } P! P R H v ڪ 0 3 g - M * ; = G p ] Q a i | JQ ȫ ٫ @G" ' + A 6 Z e | \ U P! D @ J 6 Ŭ % ٬ n J # . ! } ( / % C R W S @ i u f q U V . K O & b : ^ C < p [ p Y Y Ѯ `* p pr" :d . Й 8 ) hQ ? S b f % 9 d 0[ ! > " ˯ 5 < O D ы p! " { 0 0 c G # X V k y p 6 а L $ = Q 9 m + к 2 8 ` { F p ` ^ k o x @ H P F ` 2 \ ձ 3 # ` I 1 ڎ @ C + U P f ? Y | % v P p | Ȳ 8U / `S b 0 C R `` P5 c Z l A < y P [ 0 Ƴ : ߳ C ' { ) E p% > U < 0 g `[ h y [ [ # 0 ̴ f + u ? 0P O j U 0& ^ q & 1 .H | P% B ŵ pa H 0d" v 0 ` @ F 0 _ t % ` @ 0 Ͷ P } 7 { P ɫ ` 7 ` < B 1 ` @ B ] % a ` > w f# V D k 0 5 ȷ ܷ # b X ! p 0 p = A i А b y H c E 6 E ̸ 0 [ + O $ { G I L U @ 5 c 8 q , | 8 * c w ɹ P G Z 0 j E @ y ! | ( 2 t C 0 [ o> v 6 H# 0! ' v ˺ * Q ! j 7 X ` R f pp X » * ֻ S W P 4 P# O ~% r p m ` . ` s @ N ɼ " 6 , 9 0A O ! 5 \ p " X 0# D ν " 0% ~ 0 e 8 $ T 0 < u T 0" k _ | 0 [ 0 8 þ $ ־ `! 5 " e PE Z ) = @ z M p h p x ο U % u ' 5 ( T A _ P Q C h ); p& ? F m R & 3 " ` @ + x D " PT# 1 \ +O g ) g 0 0 @ - Р 5 1 ( E S T b ~ R & 3 H 7u 3 L 5 $ P# M 8 p T @ " 5 ^ ` @ k p% : p 5 L $ = Ї ! п 0 I ' A W L U p X p k C 3 Y h @ " & ' @ O 6 PL N F X h r d + 6 p p v! T# ) ( = 2 T k , y a ^ 9 / F % u Р" ? 7 E / T Z ! 8 h R } P c w [ + `L l D 6 ` s ( . 31 = " z F `Ď W ` d ` w * D i & 3 4 W @ [ 5 ` Y L ^ ` i `! 8 s m v u = j n % 8 L _ n p p * + . 5 k `? u n j 3 E . " T ԍ d r v @ d ) ؎ pn% # @ 0 pu H ^ t ` 2 ! > k 8 ! 0 " `4 O 0 " A < T e 0 ~ 02 $ O P o h 3 c P \ 0 P G @ [ p t -J y p F * _ g% % I ) " L 9 P d O ^ Pl - G > Y N a { 0i f 5 / 0 ! @* % I ) > R f g k R 8 @ q ~ - w U ? N + ! = - W Z _ O # m @ @ @ ; m Po X $ G c ^ X s D f @ , @ =" ! P 2 F L Y j j + | W 1 c P > @ [ & ˧ 7 S _ ! d m 0 P @ `a v pH" * F fJ p T t 0# }% v 5 2 n `, p m " H ` $ 2 ; $ 1 J \ P K n ~ 6 u G @, * } i ( 2 O & 6 j Ї & " 7 $ ! @} B 2 v @ { X h [ F < $ , ) 3 @ @ f ` 7 q Ў k , 9 O c p K O pW < @ } L @ 8 o k PD # pg! > 4 @ \ @! o t ' " = 9 M Y P s p X F # | 9 u ˎ l g! { " 0" N 4 I h W a a ! X F z 0 j + + ] i D T ` e o | # P @z ` @ @ގ @ 9 Y 0 % 5 4 C" V D 0 $ U u" s a r ` " | O @ 0 | <# i 0 . Φ e B - P P a `c% z ! S 9 g% $ : `* * ` / / Я ? W u @ P O G @k ` * ; E 9 N +M a @ w `" Р + @ ್ { 9 5 I % h " p 3 @" 5 @* ` " @ 0 ^ R k ) 5 0 D `) D Z r @j" ~ i = ` Î @ ! | q = D S k m : @ C 6 1 " @" 1 : 3 ) `u z 9 * M r H% n$ 6 + L H )/ N & P 1 2 @ 7 = 9 P < f x @* 8 ` ' Ix C i 1 } K ` ` > q L " A `w 5 l h ~ 4 @ 2 @= ] o$ b R # D a r t И 8 ! T * `^ ] Z 1 # * PT x < L h ^ 6 Ɏ b 8 ) pS ] - ? p X l ( a z T 0 0 v ?" 8 $ ` @ 0 t% F 0: X @ ; S @ m HQ w 0 T ! P& 3 N @ * Z g B E [ ߎ @ o `U p Q d a j 8 0k : N D a M p ? l 6 n X 0C ' 7 >< 0 F B c ^ < " S W ; 0E Z / W > ' 6# Px ; ; I } L c H ~ s i 1 ` k " @l 9 @ n & 4 O ` [ R r - 3 ` a 5 $ E" 6 P i D l ] @ t 5 @ ` Y z N :" $ n 5 * K v m \ o Ѕ S 5 @= 5 . t v 6 H P e ` 5 & 6 P ` { 5 . 3 I [ F a w 0t 0$ 5 % G w @ Z & 1 l `* :" c v" 8" : ` H 3 ( V M h 5 ێ @ `n b ` 0 Ѝ% c7 : t V J K Y o 9" ? | `# X P" s O @* 4 > 99 ; V ) 0 C @g S `^ & b ގ @ y 7 @ P ! T { Î " : 0f . p J ` v Ѝ `! 2 0% z e ` E 8 0 P% @ m% ? F 0 P d" : _ @ z 3 阏 Z ? E S' P V{ k S $ 0 0< C ) [ [ & 6 p J P! % b h ! P 0 f & D U P!# i @ S ~ pd _ 8 ! 0 3 ` G X t @ ` s ્ d _ 4 E U x L i @ F $ ? P `R J e 8 % p \ G % 1 : \ T O " : k G R V 6 : `7 8 / J O _ @# ` s @ # c @ Y f _ q * @* = X z ) U h 6 p @ ` " , 1 u! 5 F ` =" l ~ A 9 8 P 7 @ P * 0c < 0 x H p% G X x # X p 2 D# + D # P T h ( m v 8 ;" G $ p ; & p @ a R j N 4 x * ! `! P Ж Y $ r J 2 ^ F? w c D ) _ A Q 5 / I" H m ! } # j 0 `ǎ @ < h # R ' ~ J [ m `% ` Н = 3 6 C Q " 6 s / " O H М P g Ď @ x p Q B u , o @+ ? 6 # %# b 5 @ @* S g d < @# * ~ M 0 , P = U ێ @ g i t ( ) ! 2 Vn 3 | 9 0 < \ / A N T @* h ;, P D ! \ p7# h @- = p F W P _ vT > & 0 N 5 T 8 > @ T ` u @* > K p m - B 8 F &# \ ǎ @ | P Z ! `6 f w P" 5T 0 " = 6 @S : p I P @ Y @ F o U w Щ ` h " ! z D ( C ` p j / o F U Ъ V d 1 `l @ p Ď @ p + ! 9 T N @ Z в X n Z 9 t P # 5 D @V @ ` V% . ? 7 ` T k o v : 0A# 9 e @M B ` 1 - ` G u Z 6 r ! 0 H # T < Q : S k e 7# > b ^- Z 0f# $ = ` h @ @ ` 8 4 I A \ n ; " 0$ d ` ) = ` J ҆ } d g h ] M 3 C @G @ W @ 2 BK G p c q S 4 P I > @* Y = L & ϐ O g F u Џ R @ ] F # R BW > p K % . 1 " N [P M e p @ 6 Pu! i A 8 XC # q" j S P ; N T X m pc + @ ! # p @ 9 E 0 W R < Z r ,f \ { R ] ~ | 3 y + > P 0F e ` W " { Pi q " 4 L e } j # ػ ? i Q + > H p$ = T D _ i # u Q ZO Q @R # P# B * q F `p$ b @ 0 T @ o R @ k e } qs A & @" < u ! 8 $! 8! j K! / Y! 0S < s! ) : ! t ! ! z ! p7 o ! P& 3 ! ># 1 ! c " F `x @ '" 5 7" N" ! S d" " 8 " p r " ! " " " ^ 8 # d # D %# 7# `H q T# @H b# u {# P j # 4 # pk # # ! d # # $ 0 $ 6 ($ " 4 D$ `@ [$ k q$ 0 |$ $ $ p $ @* $ $ T $ ([ % i $% J =% g 7 X% w B n% & % A % ` % % % % P ] & & L5 @ A 4& X& p& |& 0 & 0 ` & p & V C & P+ M r & & ' @ 6 ' p 5' @! M' Q a' . ] q' ` ' N ' P ' ` ' 0 ' ; ' ' ( # r -( 0 j :( " p` 7 R( ~ [( @ r( ` @ ( :! ( P @ ( ( ( ) k %) @ 6) E) % t `) @| r) F ) 8 ) 0& w ) ) ) 0;" ) : * s V * -* `" : K* p b* 0 " x* * P& 6 * З * a * * + @ + R # tw 4+ @+ p% L+ 0 j ]+ 쎏 s+ + ~ ~ + `I 5 + D 8 + 3 + P} V + `z r + @* , 3 (, 2 7, 9 M, e, W @ x, t9 { , `^ L , , l 8 , \ , P# I - - . 4- D Q- ݎ @ f- {- Q - - ` > - - + - T - < u . . %. 5 :. % I. Y. +z 9 k. |. . . 4x pX . y% 6 . . . 0 / 0 y &/ @ =/ 6 O/ @ ` n/ w/ % e / i / / / 5 / R$ / I 0 0 `_ 8 ,0 U0 " P 5 p0 h" 9 0 $ C 0 ^ C 0 5 0 * Y 8 0 s% 0 @ 0 F 1 1 ` m :1 @* M1 \1 f l1 * 1 vW 1 0 1 Q$ - 1 # r 1 @0 I 1 Ps x 2 2 g N 82 ! 2 R2 "A c2 < s2 2 > 2 ` a 2 = 2 @ 2 $ 2 % B 2 3 # 3 /3 >y 2 I3 ]3 ` t3 `O% 8 3 3 b 3 P 3 3 4 t H 4 . r +4 J4 W4 0: t4 P V 4 4 p X 4 1 4 h% $ 4 % 4 : 5 Y !5 < >5 ` S5 { e j5 5 s 5 5 T 5 i 5 f 6 @ 6 56 8 J6 2 c6 q6 6 ! H 6 6 6 R T 6 h a 6 @ 6 @ 6 7 k A !7 @ .7 0 E7 a h7 7 6 7 7 F 7 j 7 7 8 P 8 p 9 :8 @* k T w 6 ]8 C m8 y8 `7" 8 8 < 8 pK Q 8 m" 8 PW# 8 f R 8 9 Q K 9 )9 <9 > J9 ܍ ]9 0 u9 p# 9 po E 9 0 9 P 9 9 9 % d : Ŏ &: @| ( i ) ;: x G: [: ; h: : : i : : " : B : p a : 6 ; 0k #; \ 2; @ E; 0k! V; 9 s; ; P X ; p c ; ; # y ; ` < 7 < F +< 0 << J< [< s< Є Z < P < S b < < < < < ( @ r < @ = A" (= @= T= S j= * = @ = `\ S = g = `% = ` = = 0 > ! > " a 5> 6 D> Pg G Q> @i ? j> ` |> @* > > P > 0 > > ? ? P 5? * K? = ]? o? T, P V ? ? % D ? 5 `" ? V ? Ď @ @ KN ! '@ ?@ Q@ " І 7 c@ f% J @ , 7 @ # @ R \ @ @# @ @ { @ @ " A > !A 0 :A J = GA aA xA ! Q A A = A P A * A p$ A P B ] y "B 0B qS FB \B ` D pB @ߎ @ B @ 4 Y+ B [ B @ B p B = B P x C '3 (C N% X =C 0 UC s kC I 6 7 C ! 4 C o C C C C @r R 7 C P" : D D 0D " DD \D `m% nD + D D bQ # D ! T D D @* D ` 2 E $ E ! ! %E 8E DE > UE J cE nE " @ E E E F E E z% E F ` 8 'F W *b Xj 8F @ p MF a bF F F @ v F F F" F ! 5 F F - G G F /G A 8 AG \G kG O ' zG `^ 8 G P! G G N G G G H `# t 0H P X MH [ dH ) H @|% O H U ? H $ f H H x H 0 I J .I HI `I 2 TI fI N : |I `" P I p I / I ?Y 0 ( I Ɏ @ I @ *q S X J a 8 $J 9J h KJ \J p lJ @ Q J @+ J W J F% L J # J o J ! K %K Q L 8K GK # F _K ~K K K < K K h K + K `Ɏ @ L >L F RL ~ y @$ / rL Q3 1 L L L * L L P L L @ M )M P& 3 @M m NM aM @ uM R I M I 5 7 hM M M л M 0y M `c M @ N % N W "N `E :N ]N U Y rN * N p C N ? 5B D * N N # ৎ N N O b O U 1O 1 @O } _O vO R O Y O @ l O L O F 1 O d O ]F P T (P PQ 2P z MP U jP ! Q P H P # S P %! P a < P p { P pz m * 0 W P P ( P Q $Q ( ;Q P MQ P Q [Q @* lQ Q @" 9 Q Q j n Q Q g + Q '! Q R &R 4R % . @R fs.c io__init io__fill_buffer io__get_char io__getdelim sysfs__known_mountpoints procfs__known_mountpoints debugfs__known_mountpoints tracefs__known_mountpoints hugetlbfs__known_mountpoints bpf_fs__known_mountpoints fs__sysfs sysfs_init_once fs__init_once init_once.6 fs__procfs procfs_init_once init_once.5 fs__debugfs debugfs_init_once init_once.4 fs__tracefs tracefs_init_once init_once.3 fs__hugetlbfs hugetlbfs_init_once init_once.2 fs__bpf_fs bpf_fs_init_once init_once.1 fs__read_mounts fs__valid_mount fs__check_mounts mem_toupper fs__env_override __PRETTY_FUNCTION__.0 mount_overload filename__read_ull_base sysfs__read_ull_base tracing_path.c tracing_path __tracing_path_set tracing_path_tracefs_mount tracing_path_debugfs_mount cpu.c __base_pr str_error_r.c __libperf_pr cpumap.c atomic_read atomic_set refcount_set refcount_read refcount_inc_not_zero __PRETTY_FUNCTION__.5 refcount_inc __PRETTY_FUNCTION__.6 refcount_sub_and_test __PRETTY_FUNCTION__.4 refcount_dec_and_test perf_cpu_map__refcnt __warned.7 cpu_map__new_sysconf cpu_map__new_sysfs_online cmp_cpu __perf_cpu_map__cpu cpu_map__trim_new __PRETTY_FUNCTION__.3 __warned.2 __warned.1 __perf_cpu_map__nr threadmap.c __PRETTY_FUNCTION__.1 __PRETTY_FUNCTION__.2 perf_thread_map__reset perf_thread_map__delete __warned.3 evsel.c INIT_LIST_HEAD __xyarray__entry xyarray__max_y xyarray__max_x perf_evsel__alloc_mmap sys_perf_event_open get_group_fd empty_cpu_map.1 empty_thread_map.0 perf_evsel__close_fd_cpu perf_evsel__read_group perf_evsel__adjust_values perf_evsel__ioctl perf_evsel__run_ioctl __list_add list_add_tail __list_del __list_del_entry list_del_init hlist_add_head fdarray__available_entries perf_evlist__first __perf_evlist__propagate_maps perf_evlist__purge perf_evlist__id_hash perf_evlist__munmap_filtered perf_evlist__alloc_mmap perf_evsel__set_sid_idx perf_evlist__mmap_cb_get perf_evlist__mmap_cb_mmap perf_evlist__set_mmap_first mmap_per_evsel mmap_per_thread __func__.1 mmap_per_cpu __func__.0 perf_evlist__nr_mmaps mmap.c ring_buffer_read_head ring_buffer_write_tail mul_u64_u32_shr perf_mmap__write_tail perf_mmap__empty overwrite_rb_find_range __func__.2 __perf_mmap__read_init __warned.0 perf_mmap__read read_perf_counter read_timestamp zalloc.c xyarray.c exec-cmd.c report.constprop.0 add_path help.c pretty_print_string_list list_commands_in_dir pager.c wait_for_pager pager_process pager_preexec wait_for_pager_signal forced_pager pager_columns pager_argv spawned_pager parse-options.c option__cmp print_option_help usage_with_options_internal.part.0 opterror.isra.0 get_value run-command.c die.constprop.0 sigchain.c sigchain_push.isra.0 signals subcmd-config.c __tolower __toupper io__get_hex read_to_eol libbpf.c ERR_PTR PTR_ERR IS_ERR IS_ERR_OR_NULL btf_kind btf_vlen btf_kflag btf_is_void btf_is_int btf_is_ptr btf_is_array btf_is_struct btf_is_enum btf_is_enum64 btf_is_typedef btf_is_mod btf_is_func btf_is_func_proto btf_is_var btf_is_datasec btf_is_float btf_is_decl_tag btf_is_type_tag btf_is_any_enum btf_kind_core_compat btf_int_encoding btf_int_bits btf_array btf_enum btf_enum64_value btf_members btf_member_bit_offset btf_member_bitfield_size btf_params btf_var btf_var_secinfos str_has_sfx libbpf_reallocarray libbpf_strlcpy btf_func_linkage libbpf_is_mem_zeroed libbpf_validate_opts libbpf_err libbpf_err_errno libbpf_err_ptr libbpf_ptr str_is_empty is_ldimm64_insn dup_good_fd ensure_good_fd sys_dup3 is_pow_of_2 attach_type_name link_type_name map_type_name prog_type_name initialized.0 min_level.1 __libbpf_pr pr_perm_msg ptr_to_u64 bpf_program__exit insn_is_subprog_call is_call_insn insn_is_pseudo_func bpf_object__init_prog bpf_object__add_programs elf_sym_by_idx elf_sym_str find_member_by_offset find_member_by_name find_struct_ops_kern_types find_ksym_btf_id find_btf_by_prefix_kind bpf_map__is_struct_ops is_valid_st_ops_program bpf_object_adjust_struct_ops_autoload bpf_map__init_kern_struct_ops bpf_object__init_kern_struct_ops_maps init_struct_ops_maps bpf_object__add_map bpf_object_init_struct_ops elf_sec_by_idx elf_sec_name bpf_object__new bpf_object__elf_finish bpf_object__elf_init bpf_object__check_endianness bpf_object__init_license bpf_object__init_kversion bpf_map_type__is_map_in_map find_elf_sec_sz elf_sec_data find_elf_var_sym sys_memfd_create create_placeholder_fd array_map_mmap_sz bpf_map_mmap_sz bpf_map_mmap_resize internal_map_name map_is_mmapable bpf_object__init_internal_map map_fill_btf_type_info bpf_object__init_global_data_maps find_extern_by_name find_extern_by_name_with_len set_kcfg_value_tri set_kcfg_value_str parse_u64 is_kcfg_value_in_range set_kcfg_value_num bpf_object__process_kconfig_line bpf_object__read_kconfig_file bpf_object__read_kconfig_mem bpf_object__init_kconfig_map resolve_func_ptr __btf_kind_str get_map_field_int get_map_field_long pathname_concat build_map_pin_path adjust_ringbuf_sz map_is_ringbuf fill_map_from_def btf_var_linkage_str bpf_object__init_user_btf_map init_arena_map_data bpf_object__init_user_btf_maps bpf_object__init_maps section_have_execinstr elf_sec_hdr starts_with_qmark btf_needs_sanitization bpf_object__sanitize_btf libbpf_needs_btf kernel_needs_btf bpf_object__init_btf compare_vsi_off btf_fixup_datasec bpf_object_fixup_btf prog_needs_vmlinux_btf map_needs_vmlinux_btf obj_needs_vmlinux_btf bpf_object__load_vmlinux_btf bpf_object__sanitize_and_load_btf prog_is_subprog elf_sec_str elf_rel_by_idx is_sec_name_dwarf ignore_elf_section cmp_progs bpf_object__elf_collect sym_is_extern sym_is_subprog find_extern_btf_id find_extern_sec_btf_id find_kcfg_type cmp_externs find_int_btf_id add_dummy_ksym_var bpf_object__collect_externs bpf_object__shndx_is_data bpf_object__shndx_is_maps bpf_object__section_to_libbpf_map_type bpf_program__record_reloc prog_contains_insn find_prog_by_sec_insn bpf_object__collect_prog_relos bpf_get_map_info_from_fdinfo bpf_object_prepare_token bpf_object__probe_loading map_is_reuse_compat bpf_object__reuse_map bpf_object__populate_internal_map map_is_created bpf_object__create_map map_set_def_max_entries bpf_map__destroy init_map_in_map_slots init_prog_array_slots bpf_object_init_prog_arrays bpf_object__create_maps bpf_core_is_flavor_sep load_module_btfs bpf_core_find_cands bpf_core_hash_fn bpf_core_equal_fn find_relo_core bpf_core_resolve_relo bpf_object__relocate_core poison_map_ldimm64 poison_kfunc_call bpf_object__relocate_data adjust_prog_btf_ext_info reloc_prog_func_and_line_info cmp_relo_by_insn_idx find_prog_insn_relo append_subprog_relos bpf_object__append_subprog_code bpf_object__reloc_code bpf_object__relocate_calls bpf_object__free_relocs cmp_relocs bpf_object__sort_relos bpf_prog_assign_exc_cb global_ctx_map need_func_arg_type_fixup clone_func_btf_info bpf_program_fixup_func_info bpf_object__relocate bpf_object__collect_map_relos bpf_object__collect_relos bpf_object__collect_st_ops_relos insn_is_helper_call bpf_object__sanitize_prog libbpf_prepare_prog_load libbpf_find_attach_btf_id bpf_object_load_prog fixup_verifier_log find_prev_line patch_log fixup_log_failed_core_relo fixup_log_missing_map_load fixup_log_missing_kfunc_call bpf_program_record_relos bpf_object__load_progs bpf_object_init_progs find_sec_def bpf_object_open bpf_object_unload bpf_object__sanitize_maps libbpf_kallsyms_parse bpf_object__read_kallsyms_file bpf_object__resolve_ksym_var_btf_id bpf_object__resolve_ksym_func_btf_id bpf_object__resolve_ksyms_btf_id bpf_object__resolve_externs bpf_map_prepare_vdata bpf_object_prepare_struct_ops bpf_object_load make_parent_dir check_path sanitize_pin_path __bpf_program__iter custom_sec_def_cnt custom_sec_defs has_custom_fallback_def last_custom_sec_def_handler_id section_defs attach_kprobe_multi attach_kprobe_session attach_tp attach_raw_tp sec_def_matches libbpf_get_type_names find_struct_ops_map_by_offset libbpf_find_prog_btf_id find_kernel_btf_id map_uses_real_name map_btf_datasec_resize __bpf_map__iter __func__.3 validate_map_op bpf_link__detach_fd bpf_link_perf_detach remove_kprobe_event_legacy remove_uprobe_event_legacy bpf_link_perf_dealloc parse_uint_from_file determine_kprobe_perf_type determine_uprobe_perf_type determine_kprobe_retprobe_bit determine_uprobe_retprobe_bit perf_event_open_probe append_to_file use_debugfs has_debugfs.4 tracefs_path tracefs_kprobe_events tracefs_uprobe_events tracefs_available_filter_functions tracefs_available_filter_functions_addrs gen_kprobe_legacy_event_name index.5 add_kprobe_event_legacy determine_kprobe_perf_type_legacy perf_event_kprobe_open_legacy arch_specific_syscall_pfx avail_func_cmp avail_kallsyms_cb libbpf_available_kallsyms_parse has_available_filter_functions_addrs libbpf_available_kprobes_parse gen_uprobe_legacy_event_name add_uprobe_event_legacy determine_uprobe_perf_type_legacy perf_event_uprobe_open_legacy elf_find_func_offset_from_archive arch_specific_lib_paths resolve_full_path determine_tracepoint_id perf_event_open_tracepoint prefixes.6 bpf_program__attach_btf_id bpf_program_attach_fd bpf_link__detach_struct_ops perf_event_read_simple perf_buffer__free_cpu_buf perf_buffer__open_cpu_buf __perf_buffer__new perf_buffer__process_record perf_buffer__process_records cpus.7 fcpu.8 populate_skeleton_maps populate_skeleton_progs sys_bpf_fd memlock_bumped alloc_zero_tailing_info bpf_map_batch_common bpf_obj_get_next_id nlattr.c libbpf_nla_data libbpf_nla_len nla_attr_minlen nla_next nla_ok nla_type validate_nla nlmsg_len btf.c __bswap_16 __bswap_32 btf_is_union btf_is_composite btf_is_fwd hash_bits btf_void btf_add_type_offs_mem btf_add_type_idx_entry btf_bswap_hdr btf_parse_hdr btf_parse_str_sec btf_type_size btf_bswap_type_base btf_bswap_type_rest btf_parse_type_sec btf_validate_str btf_validate_id btf_validate_type btf_sanity_check determine_ptr_size long_aliases.0 btf_ptr_sz is_host_big_endian btf_type_is_void btf_type_is_void_or_null btf__align_of.localalias btf_find_by_name_kind btf_is_modifiable btf__free.localalias btf_new_empty btf_new btf_find_elf_sections btf_parse_elf btf_parse_raw btf_parse btf_get_raw_data btf_strs_data btf__str_by_offset.localalias btf_invalidate_raw_data btf_ensure_modifiable btf__find_str.localalias btf_add_type_mem btf_type_inc_vlen btf_commit_type btf_rewrite_str btf_add_type btf_dedup_equal_fn btf_dedup_identity_hash_fn validate_type_id btf_add_ref_kind btf_add_composite btf_last_type btf_add_enum_common btf_ext_setup_info btf_ext_setup_func_info btf_ext_setup_line_info btf_ext_setup_core_relos btf_ext_parse_hdr btf_dedup_new btf_dedup_prep btf_dedup_strings btf_dedup_prim_types btf_dedup_struct_types btf_dedup_resolve_fwds btf_dedup_ref_types btf_dedup_compact_types btf_dedup_remap_types btf_dedup_free hash_combine btf_dedup_table_add btf_dedup_hypot_map_add btf_dedup_clear_hypot_map btf_dedup_collision_hash_fn btf_for_each_str_off strs_dedup_remap_str_off btf_hash_common btf_equal_common btf_hash_int_decl_tag btf_equal_int_tag btf_hash_enum btf_equal_enum_members btf_equal_enum64_members btf_equal_enum btf_is_enum_fwd btf_compat_enum btf_hash_struct btf_shallow_equal_struct btf_hash_array btf_equal_array btf_compat_array btf_hash_fnproto btf_equal_fnproto btf_compat_fnproto btf_dedup_prim_type is_type_mapped resolve_type_id resolve_fwd_id btf_fwd_kind btf_dedup_identical_arrays btf_dedup_identical_structs btf_dedup_is_equiv btf_dedup_merge_hypot_map btf_dedup_struct_type btf_dedup_ref_type btf_dedup_fill_unique_names_map btf_dedup_resolve_fwd btf_dedup_remap_type_id btf_add_distilled_type_ids btf_add_distilled_types btf_update_distilled_type_ids libbpf_errno.c libbpf_strerror_table str_error.c netlink.c libbpf_nla_getattr_u8 libbpf_nla_getattr_u16 libbpf_nla_getattr_u32 libbpf_nla_getattr_u64 req_tail nlattr_add nlattr_begin_nested nlattr_end_nested libbpf_netlink_open libbpf_netlink_close netlink_recvmsg alloc_iov libbpf_netlink_recv libbpf_netlink_send_recv parse_genl_family_id libbpf_netlink_resolve_genl_family_id __bpf_set_link_xdp_fd_replace __dump_link_nlmsg get_xdp_info parse_xdp_features clsact_config attach_point_to_config tc_get_tcm_parent tc_qdisc_modify tc_qdisc_create_excl tc_qdisc_delete __bpf_tc_detach __get_tc_info tc_add_fd_and_name bpf_prog_linfo.c dissect_jited_func libbpf_probes.c get_ubuntu_kernel_version get_debian_kernel_version probe_prog_load load_local_storage_btf probe_map_create hashmap.c hashmap_add_entry hashmap_del_entry hashmap_needs_to_grow hashmap_grow hashmap_find_entry btf_dump.c str_hash PREFIXES PREFIX_CNT str_hash_fn str_equal_fn btf_name_of btf_dump_printf btf_dump_resize btf_dump_mark_referenced btf_dump_free_names btf_dump_order_type btf_dump_emit_type btf_dump_add_emit_queue_id btf_dump_is_blacklisted btf_dump_emit_struct_fwd btf_dump_emit_typedef_def btf_dump_emit_missing_aliases btf_dump_emit_enum_def btf_dump_emit_fwd_def btf_dump_emit_struct_def btf_is_struct_packed btf_dump_emit_bit_padding btf_dump_type_name btf_dump_emit_type_decl missing_base_types btf_dump_emit_enum_fwd btf_dump_emit_enum32_val btf_dump_name_dups btf_dump_emit_enum64_val btf_dump_ident_name btf_dump_push_decl_stack_id btf_dump_emit_type_chain btf_dump_emit_mods btf_dump_drop_mods btf_dump_emit_name btf_dump_emit_type_cast btf_dump_resolve_name btf_dump_data_newline btf_dump_data_delim btf_dump_data_pfx btf_dump_unsupported_data btf_dump_get_bitfield_value btf_dump_bitfield_check_zero btf_dump_bitfield_data btf_dump_base_type_check_zero bytecmp.0 ptr_is_aligned btf_dump_int_data btf_dump_float_data btf_dump_var_data btf_dump_dump_type_data btf_dump_array_data btf_dump_struct_data btf_dump_ptr_data btf_dump_get_enum_value btf_dump_enum_data btf_dump_datasec_data btf_dump_type_data_check_overflow btf_dump_type_data_check_zero ringbuf.c ringbuf_free_ring roundup_len ringbuf_process_ring user_ringbuf_unmap_ring user_ringbuf_map user_ringbuf_commit ns_elapsed_timespec strset.c strset_hash_fn strset_equal_fn strset_add_str_mem linker.c init_output_elf add_dst_sec add_new_sym linker_load_obj_file linker_append_sec_data linker_append_elf_syms linker_append_elf_relos linker_append_btf linker_append_btf_ext is_dwarf_sec_name is_ignored_sec add_src_sec linker_sanity_check_elf linker_sanity_check_btf linker_sanity_check_btf_ext linker_fixup_btf linker_sanity_check_elf_symtab linker_sanity_check_elf_relos check_btf_type_id check_btf_str_off init_sec find_dst_sec_by_name secs_match sec_content_is_same extend_sec is_data_sec is_relo_sec linker_append_elf_sym get_sym_by_idx find_glob_sym add_glob_sym glob_sym_btf_matches glob_map_defs_match glob_syms_match btf_is_non_static find_glob_sym_btf find_src_sec_by_name complete_extern_btf_info sym_update_bind sym_update_type sym_update_visibility find_sym_by_name add_btf_ext_rec finalize_btf emit_elf_data_sec finalize_btf_ext emit_btf_ext_data gen_loader.c blob_fd_array_off realloc_insn_buf realloc_data_buf emit emit2 add_data emit_sys_close_blob add_map_fd add_kfunc_btf_fd insn_bytes_to_bpf_size emit_rel_store move_blob2blob move_blob2ctx move_ctx2blob move_stack2blob move_stack2ctx emit_sys_bpf is_simm16 emit_check_err emit_debug debug_regs debug_ret __emit_sys_close emit_sys_close_stack emit_find_attach_target get_ksym_desc emit_bpf_find_by_name_kind emit_bpf_kallsyms_lookup_name emit_relo_kfunc_btf emit_ksym_relo_log emit_relo_ksym_typeless src_reg_mask emit_relo_ksym_btf emit_relo emit_relos cleanup_core_relo cleanup_relos relo_core.c btf_int_offset is_flex_arr core_relo_kind_str core_relo_is_field_based core_relo_is_type_based core_relo_is_enumval_based bpf_core_fields_are_compat bpf_core_match_member bpf_core_spec_match bpf_core_calc_field_relo bpf_core_calc_type_relo bpf_core_calc_enumval_relo bpf_core_calc_relo bpf_core_poison_insn insn_bpf_size_to_bytes bpf_core_names_match bpf_core_enums_match bpf_core_composites_match usdt.c ref_ctr_sysfs_path.1 sanity_check_usdt_elf find_elf_sec_by_name cmp_elf_segs parse_elf_segs parse_vma_segs find_elf_seg find_vma_seg collect_usdt_targets parse_usdt_note parse_usdt_spec bpf_link_usdt_detach bpf_link_usdt_dealloc specs_hash_fn specs_equal_fn allocate_spec_id parse_usdt_arg calc_pt_regs_off reg_map.0 zip.c check_access try_parse_end_of_cd find_cd local_file_header_at_offset get_entry_at_offset elf_find_next_scn_by_type elf_sym_iter_new elf_sym_iter_next elf_get_vername symbol_match elf_sym_offset symbol_cmp features.c probe_kern_prog_name probe_kern_global_data __func__.12 probe_kern_btf strs.11 probe_kern_btf_func strs.10 probe_kern_btf_func_global strs.9 probe_kern_btf_datasec strs.8 probe_kern_btf_qmark_datasec strs.7 probe_kern_btf_float strs.6 probe_kern_btf_decl_tag strs.5 probe_kern_btf_type_tag strs.4 probe_kern_array_mmap probe_kern_exp_attach_type probe_kern_probe_read_kernel probe_prog_bind_map probe_module_btf strs.2 probe_perf_link probe_uprobe_multi_link probe_kern_bpf_cookie probe_kern_btf_enum64 strs.1 probe_kern_arg_ctx_tag strs.0 feature_cache feature_probes btf_iter.c btf_relocate.c btf_relocate_rewrite_type_id cmp_btf_name_size search_btf_name_size btf_mark_embedded_composite_type_ids btf_relocate_map_distilled_base btf_relocate_validate_distilled_base btf_relocate_rewrite_strs builtin-bench.c print_usage collections run_collection bench_usage bench_options bench_format_str sched_benchmarks syscall_benchmarks mem_benchmarks numa_benchmarks futex_benchmarks epoll_benchmarks internals_benchmarks breakpoint_benchmarks uprobe_benchmarks sched-messaging.c sig_handler total_children worker_tab fdpair.part.0 use_pipes ready.part.0 receiver thread_mode receiver.cold sender nr_loops sender.cold bench_sched_message_usage num_groups receiver_contexts sender_contexts bench_sched_messaging.cold sched-pipe.c enter_cgroup cgrp_names cgrps worker_thread parse_two_cgroups bench_sched_pipe_usage sched-seccomp-notify.c bench_seccomp_usage sync_mode bench_sched_seccomp_notify.cold bench_syscall_usage mem-functions.c do_memset_gettimeofday do_memcpy_gettimeofday do_memcpy_cycles cycles_fd do_memset_cycles __bench_mem_function use_cycles size_str bench_mem_common cycle_attr function_str bench_mem_memcpy_usage memset_functions bench_mem_memset_usage futex-hash.c toggle_done thread_lock threads_starting thread_worker futex_flag thread_parent workerfn.cold bench_futex_hash_usage throughput_stats bench_futex_hash.cold futex-wake.c futex1 bench_futex_wake_usage wakeup_stats waketime_stats bench_futex_wake.cold futex-wake-parallel.c blocked_workerfn waking_workerfn barrier nwakes bench_futex_wake_parallel_usage blocked_worker bench_futex_wake_parallel.cold futex-requeue.c futex2 bench_futex_requeue_usage requeued_stats requeuetime_stats bench_futex_requeue.cold futex-lock-pi.c bench_futex_lock_pi_usage global_futex bench_futex_lock_pi.cold epoll-wait.c cmpworker nest_epollfd multiq epollfdp nest_epollfd.cold nonblocking oneshot writerfn __verbose randomize wdone nthreads nfds writerfn.cold bench_epoll_wait_usage noaffinity bench_epoll_wait.cold epoll-ctl.c bench_epoll_ctl_usage all_stats bench_epoll_ctl.cold synthesize.c process_synthesized_event event_count do_run_single_threaded single_iterations run_st run_mt max_threads min_threads multi_iterations kallsyms-parse.c bench_process_symbol find-bit-bench.c use_of_val accumulator outer_iterations inner_iterations inject-buildid.c add_dso nr_dsos data_reader synthesize_mmap bench_id_hdr_size synthesize_sample.isra.0 bench_sample_type synthesize_fork.isra.0 synthesize_attr.isra.0 do_inject_loop evlist-open-close.c bench__create_evlist event_string breakpoint.c active_thread passive_thread thread_options thread_usage bench_breakpoint_thread.cold enable_options enable_usage bench_breakpoint_enable.cold pmu-scan.c nr_pmus results uprobe.c bench_uprobe.isra.0 bench_uprobe_usage baseline.1 previous.0 numa.c do_work parse_nodes_opt parse_cpus_opt alloc_data __bench_numa bench_numa_usage builtin-test.c perf_test__config run_test_child print_test_result.isra.0 finish_test.isra.0 start_test dont_fork sequential generic_tests noploop.c sighandler thloop.c thfunc leafloop.c sqrtloop.c brstack.c brstack_bar brstack_foo brstack_bench datasym.c buf1 tests-scripts.c shell_tests__dir_fd shell_test__run append_script append_scripts_in_dir parse-events.c test__checkevent_pmu_events_alias test__checkevent_genhw test__checkevent_genhw_modifier test__checkevent_raw_pmu test__checkevent_pmu_partial_time_callgraph test__checkevent_pmu test__checkevent_breakpoint_len_w test__checkevent_breakpoint_len test__checkevent_breakpoint_rw test__checkevent_list test__checkevent_breakpoint_w test__checkevent_breakpoint_r test__checkevent_breakpoint_x test__checkevent_breakpoint test__checkevent_symbolic_alias test__checkevent_numeric test__checkevent_numeric_modifier test__checkterms_simple test__checkevent_pmu_events test__pmu_events_alias2 events.0 test_alias test_event test__pmu_events_alias test__alias assert_hw test__leader_sample2 test__checkevent_precise_max_modifier test__group3 test__checkevent_tracepoint_multi test__checkevent_tracepoint_multi_modifier test__checkevent_tracepoint test__checkevent_pmu_name test__checkevent_breakpoint_2_events test__pmu_cpu_valid test__intel_pt_valid test__pmu_cpu_event_valid test__checkevent_raw test__checkevent_raw_modifier test__checkevent_pmu_events_mix test__pmu_events test__checkevent_config_cache test__checkevent_complex_name test__intel_pt test__checkevent_config_num test__checkevent_config_raw test__checkevent_config_symbol test__all_tracepoints test__terms2 test__pmu_events2 test__events_pmu test__events2 test__events assert_hw.constprop.0 test__group1 test__group2 test__group4 test__group5 test__group_gh1 test__group_gh2 test__group_gh3 test__group_gh4 test__leader_sample1 test__pinned_group test__exclusive_group test__checkevent_symbolic_alias_modifier test__checkevent_symbolic_name test__checkevent_exclusive_modifier test__checkevent_exclude_idle_modifier_1 test__checkevent_exclude_idle_modifier test__checkevent_pinned_modifier test__checkevent_exclude_guest_modifier test__checkevent_exclude_host_modifier test__checkevent_symbolic_name_modifier test__checkevent_tracepoint_modifier test__checkevent_symbolic_name_config test__checkevent_breakpoint_w_modifier_name test__checkevent_breakpoint_r_modifier_name test__checkevent_breakpoint_x_modifier_name test__checkevent_breakpoint_modifier_name test__checkevent_breakpoint_w_modifier test__checkevent_breakpoint_r_modifier test__checkevent_breakpoint_x_modifier test__checkevent_breakpoint_modifier test__sym_event_dc test__sym_event_slash test__term_equal_legacy test__term_equal_term test__checkevent_breakpoint_len_rw_modifier test__checkevent_breakpoint_rw_modifier_name test__checkevent_breakpoint_rw_modifier tests__parse_events dso-data.c open_files_cnt test_file.constprop.0 buf_templ.0 test_file.constprop.0.cold test__dso_data test__dso_data_cache new_limit test__dso_data_reopen tests__dso_data store_event store_event.cold test__attr vmlinux-kallsyms.c test__vmlinux_matches_kallsyms_cb2 test__vmlinux_matches_kallsyms ignored_symbols.3 test__vmlinux_matches_kallsyms_cb1 test__vmlinux_matches_kallsyms_cb3 ignored_prefixes.2 ignored_suffixes.1 ignored_matches.0 openat-syscall.c test__openat_syscall_event tests__openat_syscall_event openat-syscall-all-cpus.c test__openat_syscall_event_on_all_cpus tests__openat_syscall_event_on_all_cpus openat-syscall-tp-fields.c test__syscall_openat_tp_fields mmap-basic.c test_stat_user_read test__mmap_user_read_cycles test__mmap_user_read_instr test__basic_mmap tests__basic_mmap perf-record.c test__PERF_RECORD test__PERF_RECORD.cold tests__PERF_RECORD evsel-roundtrip-name.c test__perf_evsel__roundtrip_name_test evsel-tp-sched.c evsel__test_field test__perf_evsel__tp_sched_test fdarray.c test__fdarray__filter test__fdarray__add test__pmu_match test__name_cmp uncore_chas mrvl_ddrs test__name_len test__pmu_event_names test_pmu_get.constprop.0 test__pmu_format tests__pmu pmu-events.c test__parsing test__parsing_callback test__pmu_event_table test__pmu_event_table_core_callback test__pmu_event_table_sys_callback test__parsing_threshold test__parsing_threshold_callback metric_parse_fake test__parsing_fake test__parsing_fake_callback test__aliases test_core_pmu_event_aliases_cb test_pmus compare_pmu_events sys_events uncore_events pmu_events_tests uncore_hisi_ddrc_flux_wcmd unc_cbo_xsnp_response_miss_eviction uncore_hyphen uncore_two_hyph uncore_hisi_l3c_rd_hit_cpipe uncore_imc_free_running_cache_miss uncore_imc_cache_hits sys_ddr_pmu_write_cycles sys_ccn_pmu_read_cycles sys_cmn_pmu_hnf_cache_miss bp_l1_btb_correct bp_l2_btb_correct segment_reg_loads_any dispatch_blocked_any eist_trans l3_cache_rd hists_common.c fake_threads fake_mmap_info fake_symbols perf_syms bash_syms libc_syms kernel_syms hists_link.c __validate_match fake_common_samples __validate_link fake_samples test__hists_link hists_filter.c test__hists_filter hists_output.c test__hists_output test2 test4 test5 add_hist_entries test3 test1 hists_cumulate.c test__hists_cumulate fake_callchains do_test.constprop.0 do_test.constprop.1 python-use.c test__python_use bp_signal.c overflows fd1 fd2 fd3 test_function.isra.0 sig_handler_2 overflows_2 test__bp_signal bp_signal_overflow.c test__bp_signal_overflow bp_account.c detect_cnt the_var test__bp_accounting wp.c test__wp_ro __event.constprop.0 test__wp_wo test__wp_rw test__wp_modify wp_tests task-exit.c exited workload_exec_failed_signal nr_exit test__task_exit sw-clock.c __test__sw_clock_freq mmap-thread-lookup.c thread_fn go_away thread_fn.cold test__mmap_thread_lookup test__mmap_thread_lookup.cold thread-maps-share.c test__thread_maps_share switch-tracking.c compar spin_sleep test__switch_tracking keep-tracking.c find_comm test__keep_tracking code-reading.c comp do_sort_something do_test_code_reading test__code_reading test__code_reading.cold sample-parsing.c samples_same do_test test__sample_parsing parse-no-sample-id-all.c test__parse_no_sample_id_all kmod-path.c test__kmod_path__parse thread-map.c test__thread_map test__thread_map_synthesize test__thread_map_remove topology.c test__session_topology test__session_topology.cold mem.c test__mem test__cpu_map_equal __test__cpu_map_intersect test__cpu_map_merge test__cpu_map_synthesize process_event_mask process_event_cpus process_event_range_cpus test__cpu_map_print tests__cpu_map process_stat_round_event process_stat_config_event test__synthesize_stat_config test__synthesize_stat test__synthesize_stat_round event_update.c process_event_scale test__event_update process_event_unit process_event_name event-times.c test__event_times expr.c test_ids_union test__expr backward-ring-buffer.c test__backward_ring_buffer test__sdt_event is_printable_array.c test__is_printable_array bitmap.c test_bitmap test__bitmap_print perf-hooks.c the_hook sigsegv_handler test__perf_hooks unit_number__scnprintf.c test__unit_number__scnprint mem2node.c test__mem2node test_nodes maps.c failed_cb check_maps_cb check_maps test__maps__merge_in time-utils-test.c test__parse_nsec_time test__perf_time__parse_for_ranges test__time_utils genelf.c test__jit_write_elf x86_code.0 test__jit_write_elf.cold api-io.c setup_test do_test_get_char do_test_get_dec do_test_get_hex test_get_line test__api_io demangle-java-test.c test__demangle_java demangle-ocaml-test.c test__demangle_ocaml pfm.c test__pfm_events test__pfm_group pfm_tests parse-metric.c __compute_metric test__parse_metric pe-file-parsing.c test__pe_file_parsing expand-cgroup.c test_expand_events test__expand_cgroup_events perf-time-to-tsc.c test__tsc_is_supported test__perf_time_to_tsc time_to_tsc_tests dlfilter-test.c system_cmd test__dlfilter_ver test__dlfilter sigtrap.c test_thread sigtrap_handler test__sigtrap event_groups.c test__event_groups configs uncore_pmus symbols.c find_map_cb test_dso subdivided_dso_cb test__symbols util.c test__util dwarf-unwind.c unwind_entry funcs.0 mmap_handler init_live_machine global_unwind_retval arch-tests.c hybrid_tests intel_pt_tests hybrid.c test__hybrid_cache_event test__hybrid_raw2 test__hybrid_hw_event_with_pmu test__hybrid_hw_group_event_2 test__hybrid_group_modifier1 test__hybrid_hw_sw_group_event test__hybrid_sw_hw_group_event test__hybrid_hw_group_event test__hybrid_raw1 test__hybrid_events intel-pt-test.c dump_packet get_pt_caps bp-modify.c bp_1 bp_2 spawn_child.part.0 amd-ibs-via-core-pmu.c sub_tests setup.c annotate.c disasm_line__filter annotate_browser__write annotate_browser__set_percent_color annotate_browser__printf annotate_browser__write_graph ui_browser__set_jumps_percent_color annotate_browser__set_color annotate_browser__refresh annotate_browser__calc_percent annotate_browser__show.constprop.0 __annotate_browser__search_reverse __annotate_browser__search seq.1 annotate_browser__callq.isra.0 symbol__tui_annotate.cold annotate_browser__callq.isra.0.cold annotate-data.c get_member_overhead.isra.0 add_child_entries hists.c hist_browser__check_output_full hist_browser__check_dump_full __hpp_get_period __hpp_get_period_sys __hpp_get_period_us __hpp_get_period_guest_sys __hpp_get_period_guest_us __hpp_get_acc_period do_exit_browser filter_group_entries hist_browser__fprintf_callchain_entry callchain_node__init_have_children_rb_tree hist_browser__hpp_color_overhead_guest_us hist_browser__hpp_color_overhead_guest_sys hist_browser__hpp_color_overhead_us hist_browser__hpp_color_overhead_sys hist_browser__hpp_color_overhead hist_browser__refresh_dimensions hist_browser__show_callchain_entry hists_browser__scnprintf_title do_annotate do_run_script do_annotate_type do_browse_map do_res_sample_script block_hists_browser__title perf_evsel_menu__write hist_entry__init_have_children.part.0 hist_browser__hpp_color_overhead_acc hist_browser__show_callchain_list.part.0 switch_data_file is_input_name_malloced do_switch_data hist_browser__folded_callchain_str.isra.0 hist_browser__show_callchain_graph hist_browser__show_callchain hist_browser__show_entry hists_browser__headers hists_browser__hierarchy_headers hists__filter_entries ui_browser__hists_seek hist_browser__show_hierarchy_entry hist_browser__refresh add_script_opt hist_browser__nr_entries hist_browser__reset do_zoom_thread do_zoom_socket hists_browser__zoom_map.isra.0 callchain_node__set_folding_rb_tree hist_entry__set_folding.part.0 hist_browser__set_folding do_zoom_dso callchain_node__count_rows_rb_tree callchain__count_rows hierarchy_count_rows hist_browser__toggle_fold add_annotate_opt.isra.0 do_toggle_callchain seq.3 __warned.4 evsel__hists_browse top_help.1 report_help.2 help.0 map_browser__write scripts_config header.c ui_browser__argv_write res_sample.c res_sample_config context_len ui__sigwinch ui__need_resize ui__sigcont tty.0 done.1 ui__signal_backtrace ui__signal buf.0 perf_tui__warning perf_tui__error helpline.c tui_helpline__pop tui_helpline__show backlog.0 tui_helpline__push progress.c __tui_progress__init tui_progress__finish tui_progress__update tui_progress__ops nop_helpline__pop nop_helpline__push nop_helpline__show default_helpline_fns null_progress__update null_progress__ops perf_stdio__error perf_stdio__warning perf_eops default_eops hist.c he_get_period he_get_period_sys he_get_period_us he_get_period_guest_sys he_get_period_guest_us he_get_acc_period he_get_raw_nr_events he_get_weight1 he_get_weight2 he_get_weight3 hpp__nop_cmp hpp__equal hpp__header_fn hpp_entry_scnprintf hpp__width_fn he_get_raw_period hpp__sort_overhead_acc __hpp__fmt hpp__sort_overhead hpp__sort_weight3 hpp__sort_weight2 hpp__sort_weight1 hpp__sort_period hpp__sort_samples hpp__sort_overhead_guest_us hpp__sort_overhead_guest_sys hpp__sort_overhead_us hpp__sort_overhead_sys hpp__entry_weight3 hpp__entry_weight2 hpp__entry_weight1 hpp__entry_period hpp__entry_samples hpp__entry_overhead_guest_us hpp__color_overhead_guest_us hpp__entry_overhead_guest_sys hpp__color_overhead_guest_sys hpp__entry_overhead_us hpp__color_overhead_us hpp__entry_overhead_sys hpp__color_overhead_sys hpp__entry_overhead hpp__color_overhead hpp__entry_overhead_acc hpp__color_overhead_acc ipchain__fprintf_graph_line ipchain__fprintf_graph.constprop.0 ipchain__fprintf_graph __callchain__fprintf_graph rem_sq_bracket rem_hits __callchain__fprintf_flat.isra.0 __callchain__fprintf_folded callchain__fprintf_graph.constprop.0 hist_entry_callchain__fprintf.constprop.0 browser.c ui_browser__color_config ui_browser__colorsets __ui_browser__refresh.isra.0 arm64-frame-pointer-unwind-support.c perf_regs_aarch64.c perf_regs_arm.c perf_regs_csky.c perf_regs_loongarch.c perf_regs_mips.c perf_regs_powerpc.c perf_regs_riscv.c perf_regs_s390.c perf_regs_x86.c intel-pt-pkt-decoder.c intel-pt-insn-decoder.c CSWTCH.87 intel-pt-log.c log_buf__close log_buf__write intel_pt_log_open log_name intel_pt_dump_log_on_error intel_pt_log_on_error_size intel-pt-decoder.c intel_pt_get_data p_log intel_pt_get_next_packet intel_pt_scan_for_psb intel_pt_calc_cyc_timestamp intel_pt_calc_tma intel_pt_calc_cyc_cb intel_pt_walk_insn intel_pt_walk_tip intel_pt_fup_event intel_pt_walk_fup intel_pt_ff_cb intel_pt_calc_mtc_timestamp.part.0 intel_pt_calc_tsc_timestamp intel_pt_walk_psbend intel_pt_walk_fup_tip intel_pt_walk_psb intel_pt_walk_tnt intel_pt_walk_trace intel_pt_err_msgs arm-spe-pkt-decoder.c arm_spe_pkt_out_string arm_spe_packet_name idx_name.0 arm-spe-decoder.c seen_idx.0 hisi-ptt-pkt-decoder.c hisi_ptt_print_pkt trace-event-python.c python_flush_script python_generate_script python_process_call_return tuple_new.part.0 __func__.20 get_sample_value_as_tuple __func__.6 regs_map handler_call_die.isra.0 __func__.19 python_process_stat handler_name.15 main_dict __func__.16 python_process_brstacksym python_export_branch_type python_export_evsel python_export_comm_thread python_export_machine python_export_thread python_export_call_path python_export_dso python_export_comm python_export_symbol python_process_stat_interval handler_name.17 __func__.18 python_export_context_switch python_stop_script tables_global main_module set_sym_in_dict python_process_throttle define_field.constprop.0 handler_name.14 __func__.11 python_export_call_return define_value.constprop.0 define_event_symbols.constprop.0.isra.0 cur_field_name python_process_auxtrace_error python_process_switch python_export_sample python_process_callchain __func__.10 python_start_script python_start_script.cold get_perf_sample_dict __func__.4 __func__.8 __func__.5 __func__.7 python_process_tracepoint __func__.13 python_process_event handler_name.2 __func__.9 addr_location.c sym_hist_hash sym_hist_equal FILE__set_percent_color FILE__set_jumps_percent_color FILE__set_color annotation__init_sharded_mutex FILE__write_graph FILE__printf annotation__calc_lines add_basic_block print_summary annotation__config annotation_line__print.isra.0 prev_line.0 __symbol__inc_addr_samples.isra.0 __annotation_line__write block-info.c block_column_width block_total_cycles_pct_sort block_column_header block_range_entry block_cycles_pct_entry block_avg_cycles_entry block_dso_entry block_total_cycles_pct_entry block_cycles_lbr_entry al.0 block_columns block-range.c build-id.c lsdir_bid_tail_filter perf_event__exit_del_thread asnprintf lsdir_bid_head_filter machine__write_buildid_table_cb no_buildid_cache dso__cache_build_id cacheline.c size.0 perf_config_scan_cb config_file_name system_wide.8 collect_config perf_config_from_file.constprop.0 config_linenr config_file_eof var.1 value.0 failed.7 config.6 copyfile.c copyfile_mode_ns ctype.c db-export.c db_export__threads db_ids_from_al db_export__call_path.localalias disasm.c csky__annotate_init csky__associate_ins_ops loongarch__annotate_init loongarch__associate_ins_ops mips__annotate_init mips__associate_ins_ops powerpc__annotate_init powerpc__associate_instruction_ops riscv64__annotate_init riscv64__associate_ins_ops sparc__annotate_init sparc__associate_instruction_ops jump__delete ins__cmp arch__cmp ins__raw_scnprintf mov__scnprintf nop__scnprintf dec__scnprintf jump__scnprintf loongarch_jump__parse loongarch_call__parse s390_call__parse s390_mov__parse arm64_mov__parse arm64__annotate_init arm64__associate_instruction_ops arm__annotate_init arm__associate_instruction_ops lock__delete intel__ins_is_fused s390__annotate_init s390__associate_ins_ops call__scnprintf arch__associate_ins_ops.isra.0 ret_ops s390_call_ops s390_mov_ops x86__annotate_init amd__ins_is_fused dec__parse arm64_mov_ops loongarch_call_ops loongarch_jump_ops symbol__init_regexpr file_lineno sorted.1 architectures lock__scnprintf nop_ops lock_ops lock__parse x86__instructions dec_ops disasm_bpf.c env.c perf_env__read_arch uts.0 find_func_symbol_cb find_any_symbol_cb text_poke_printer perf_event__names perf_mmap__unmap_cb perf_evlist__mmap_cb_idx __evlist__enable.constprop.0 __evlist__disable.constprop.0 tags.2 evlist__prepare_workload.cold evlist__start_workload.cold sideband_evlist.c perf_evlist__poll_thread evsel__no_extra_init evsel__no_extra_fini __open_attr__fprintf find_process.constprop.0 perf_evsel__parse_id_sample.constprop.0.isra.0 evsel__add_modifiers.isra.0 read_pid_stat_field read_stat_field perf_tool_event__tool_names perf_evsel__object evsel__disable_missing_features evsel__hw_cache_stat evsel__compute_deltas.cold evsel__read_counter.cold __evsel__read_on_cpu.cold empty_cpu_map empty_thread_map states.1 prev_state_field.0 evsel__store_ids.cold evsel__open_cpu evsel__open_cpu.cold evsel_fprintf.c comma_fprintf __print_attr__fprintf perf_event_attr_fprintf.c evswitch.c find_bit.c get_current_dir_name.c levenshtein.c memswap.c get_config_terms __parse_events_error__print config_term_shrinked tracepoint_error add_tracepoint_event parse_events__modifier_list config_term_names.2 config_term_common __parse_events_add_numeric config_term_pmu parse_events_add_pmu print-events.c event_symbols_tool event_type_descriptors tracepoint.c perf_regs.c print_binary.c print_insn.c rlimit.c argv_split.c rbtree.c string.c hweight.c smt.c cached.1 cached_result.0 strbuf.c strbuf_addv __match_glob strlist.c strlist__node_delete strlist__node_new strlist__node_cmp strfilter.c get_token strfilter_node__compare strfilter_node__sprint strfilter_node__delete strfilter_node__new top.c usage.c usage_builtin origin.3 debuglink_paths compressions open_dso dso__data_open_cnt dso__data_open cached_io dso__data_open_lock dso_load__error_str.0 dsos.c dsos__hit_all_cb dsos__cmp_long_name_id_short_name __dsos__find_by_longname_id dso__set_basename dsos__fprintf_buildid_cb dsos__fprintf_cb dsos__find_kernel_dso_cb dsos__read_build_ids_cb symbols__sort_name_cmp __read_proc_modules remove_old_maps kcore_mapfn visible_dir_filter do_validate_kcore_modules_cb vmlinux_path__init vmlinux_paths_upd idle_symbols_list.0 map__process_kallsym_symbol maps__split_kallsyms symbols__find_by_name validate_kcore_modules dso__load_kcore binary_type_symtab symbol_fprintf.c map_symbol.c color.c color_config.c metricgroup.c metric_event_cmp mep_delete metric_event_delete mep_new metric_event_new metric_list_cmp metricgroup__topdown_max_level_callback metricgroup__sys_event_iter mep_cmp default_metricgroup_cmp match_metric metricgroup__find_metric_callback parse_ids metricgroup__add_to_mep_groups_callback metricgroup__has_metric_callback metricgroup__add_metric_callback metricgroup__add_metric_sys_event_iter violate_nmi_constraint.0 __add_metric write_branch_stack cpu_cache_level__sort memory_node__sort cpu_cache_level__read print_hybrid_topology print_compressed print_dir_format print_clockid print_cache print_stat print_auxtrace print_branch_stack print_cpu_topology __desc_attr__fprintf print_total_mem print_cpuid print_cpudesc print_nrcpus print_arch print_version print_osrelease print_hostname print_bpf_btf print_mem_topology print_sample_time print_group_desc print_pmu_mappings print_numa_topology print_cmdline perf_file_section__fprintf_info perf_file_section__process write_build_id evlist__prepare_tracepoint_events print_cpu_pmu_caps print_clock_data write_auxtrace check_magic_endian.part.0 write_tracing_data write_stat __event_process_build_id.isra.0 perf_header__read_build_ids build_mem_topology.constprop.0 print_pmu_caps process_total_mem process_clockid process_dir_format process_sample_time process_mem_topology do_read_string process_cpuid process_cpudesc process_arch process_version process_osrelease process_hostname process_cmdline process_pmu_mappings __process_pmu_caps process_cpu_pmu_caps process_hybrid_topology process_nrcpus process_clock_data process_numa_topology process_group_desc process_compressed process_bpf_btf process_cache process_bpf_prog_info read_event_desc process_event_desc print_event_desc process_cpu_topology write_clock_data write_compressed write_bpf_btf write_bpf_prog_info write_dir_format write_clockid write_mem_topology write_sample_time write_total_mem write_nrcpus perf_session__do_write_header feat_writer_cb zero_buf.6 write_pmu_mappings write_numa_topology write_hybrid_topology write_event_desc write_cpu_pmu_caps write_group_desc write_version write_arch write_osrelease write_hostname write_cmdline write_cpudesc write_cpu_topology write_pmu_caps write_cpuid write_cache callchain.c parse_callchain_mode parse_callchain_sort_key add_child add_child.cold free_callchain_node init_callchain_cursor_key callchain_cursor__delete __sort_chain_graph_rel __sort_chain_graph_abs callchain_node_branch_counts_cumul.isra.0 decay_callchain_node append_chain_children append_chain_children.cold __sort_chain_flat __parse_callchain_report_opt merge_chain_branch once_control.1 values.c trace_event_printer trace_event_printer.cold _debug_file redirect_to_stderr pr_debug_wrapper pr_warning_wrapper debug_opts fncache.c fncache_hash machine.c machine__uses_kcore_cb machine__for_each_dso_cb machine_fprintf_cb add_callchain_ip thread_list_cb machine__map_x86_64_entry_trampolines_cb lbr_callchain_add_lbr_ip.constprop.0.isra.0 maps__set_modules_path_dir machine__create_modules machine__create_module lbr_callchain_add_kernel_ip.isra.0 machine__update_thread_pid.part.0 seen.4 machine__get_running_kernel_start.constprop.0 thread__resolve_callchain_sample machine__process_kernel_mmap_event map__start_cmp map__strcmp maps__find_symbol_by_name_cb maps__fprintf_cb __maps__free_maps_by_name.part.0 __maps__insert maps__by_address_index __maps__remove __maps__insert_sorted __maps__fixup_overlap_and_insert pstack.c session.c process_event_synth_tracing_data_stub process_event_synth_attr_stub process_event_stub process_event_sample_stub perf_session__process_compressed_event_stub perf_session__process_compressed_event process_event_time_conv_stub process_stat_round_stub process_stat_stub process_event_stat_config_stub process_event_cpu_map_stub process_event_thread_map_stub process_event_synth_event_update_stub perf_event__event_update_swap perf_event__thread_map_swap perf_event__event_type_swap perf_event__stat_swap perf_event__auxtrace_swap perf_event__tracing_data_swap perf_event__stat_config_swap perf_event__auxtrace_info_swap perf_event__text_poke_swap perf_event__namespaces_swap perf_event__all64_swap reader__mmap perf_session__flush_thread_stack perf_session__warn_about_errors dump_event.part.0 perf_event__time_conv_swap perf_event__cpu_map_swap perf_event__auxtrace_error_swap perf_event__switch_swap perf_event__task_swap perf_event__read_swap perf_event__comm_swap perf_event__mmap2_swap perf_event__mmap_swap process_finished_round_stub process_event_op2_stub regs__printf regs_abi skipn.isra.0 perf_event__stat_round_swap process_event_auxtrace_stub perf_event__itrace_start_swap perf_event__aux_swap perf_event__throttle_swap perf_event__cgroup_swap perf_session__process_user_event perf_session__process_user_event.cold ordered_events__deliver_event perf_event__hdr_attr_swap dump_sample.part.0 machines__deliver_event perf_session__deliver_event process_simple perf_event__swap_ops __perf_session__process_decomp_events reader__read_event s390-sample-raw.c get_counter_name_callback amd-sample-raw.c ibs_fetch_type ibs_op_type cpu_family zen4_ibs_extensions cpu_model data_src_str.0 data_src_str.1 syscalltbl.c syscallcmp syscalltbl_x86_64 ordered-events.c __ordered_events__flush namespaces.c nsinfo__get_nspid perf_ns__names comm.c comm_strs__init _comm_strs comm_str__put.part.0 comm_strs_type_once.0 comm_str__put.part.0.cold comm_strs__findnew.part.0 thread.c thread__prepare_access_maps_cb thread__priv_destructor threads.c key_hash key_equal thread_map.c __thread_map__new_all_cpus thread_map__new_by_pid_str parse-events-flex.c yy_fatal_error.isra.0 modifiers_error.isra.0 parse_events_ensure_buffer_stack parse_events_restart.cold yy_base yy_chk yy_accept yy_def yy_meta yy_ec yy_nxt yy_acclist yy_rule_can_match_eol parse-events-bison.c free_list_evsel yydestruct.isra.0 yyloc_default.0 yypact yycheck yydefact yytable yytranslate yyr2 yypgoto yyr1 yydefgoto yystos perf_pmu__match_ignoring_suffix pmu_uncore_alias_match find_event_callback printed.1 pmu_add_cpu_aliases_map_callback pmu_add_sys_aliases_iter_fn perf_pmu__parse_snapshot.isra.0 perf_pmu__parse_per_pkg.isra.0 perf_pmu__parse_unit.isra.0 perf_pmu__parse_scale.isra.0 update_alias pmu_id perf_pmu_format__load terms.0 is_sysfs_pmu_core perf_pmu__find_alias __pmu_aliases_parse.isra.0 perf_pmu__new_alias pmu_aliases_parse_eager.isra.0 pmu_cpumask pmus.c perf_pmus__print_pmu_events__callback build_format_string pmu_find other_pmus cmp_sevent pmu_read_sysfs.part.0 read_sysfs_all_pmus read_sysfs_core_pmus pmus_cmp perf_pmus__scan_skip_duplicates count.1 perf_pmus__init_supports_extended_type perf_pmus__do_support_extended_type extended_type_once.0 pmu-flex.c perf_pmu_ensure_buffer_stack perf_pmu_restart.cold pmu-bison.c svghelper.c svgfile last_time total_height text.2 turbo_frequency cpu_m.1 buffer.0 trace-event-info.c tracepoint_id_to_path record_file output_fd copy_event_system trace-event-scripting.c flush_script_unsupported process_event_unsupported python_generate_script_unsupported python_start_script_unsupported perl_generate_script_unsupported perl_start_script_unsupported stop_script_unsupported trace-event.c tevent tevent_initialized trace-event-parse.c find_arg_field search_op offset.5 size.6 offset.3 size.4 offset.1 size.2 save_states.0 trace-event-read.c do_read input_fd repipe trace_data_size sort__thread_cmp sort__simd_cmp sort__srcline_from_cmp sort__srcline_to_cmp sort__cpu_cmp sort__cgroup_id_cmp sort__cgroup_cmp sort__socket_cmp hist_entry__socket_filter sort__time_cmp sort__mispredict_cmp sort__cycles_cmp sort__locked_cmp sort__tlb_cmp sort__lvl_cmp sort__snoop_cmp sort__weight_cmp sort__ins_lat_cmp sort__p_stage_cyc_cmp sort__blocked_cmp sort__phys_daddr_cmp sort__data_page_size_cmp sort__code_page_size_cmp sort__abort_cmp sort__in_tx_cmp sort__transaction_cmp sort__sym_size_cmp sort__dso_size_cmp sort__addr_cmp __sort__hpp_cmp __sort__hpp_collapse __sort__hpp_sort repsep_snprintf hist_entry__thread_snprintf hist_entry__srcline_snprintf hist_entry__srcline_from_snprintf hist_entry__srcline_to_snprintf hist_entry__srcfile_snprintf hist_entry__parent_snprintf hist_entry__cpu_snprintf hist_entry__cgroup_id_snprintf hist_entry__socket_snprintf hist_entry__mispredict_snprintf out.2 hist_entry__local_weight_snprintf hist_entry__global_weight_snprintf hist_entry__local_ins_lat_snprintf hist_entry__global_ins_lat_snprintf hist_entry__p_stage_cyc_snprintf hist_entry__global_p_stage_cyc_snprintf hist_entry__phys_daddr_snprintf hist_entry__abort_snprintf out.1 hist_entry__in_tx_snprintf out.0 hist_entry__sym_size_snprintf hist_entry__dso_size_snprintf hist_entry__addr_snprintf hist_entry__type_snprintf hist_entry__comm_snprintf sort__comm_cmp sort__sym_sort sort__parent_cmp sort__srcline_from_init sort__srcline_from_collapse sort__srcline_to_init sort__srcline_to_collapse hist_entry__sym_ipc_snprintf hist_entry__sym_ipc_null_snprintf hist_entry__get_srcfile no_srcfile sort__srcfile_collapse hse_free hist_entry__cgroup_snprintf hist_entry__time_snprintf get_trace_output hist_entry__locked_snprintf hist_entry__tlb_snprintf hist_entry__lvl_snprintf hist_entry__snoop_snprintf hist_entry__blocked_snprintf hist_entry__data_page_size_snprintf hist_entry__code_page_size_snprintf __sort__hpp_header __sort__hpp_entry __sort__hpp_width __sort__hde_cmp __sort__hde_entry hist_entry__thread_filter hist_entry__simd_snprintf hist_entry__dso_to_snprintf hist_entry__cycles_snprintf sort__trace_cmp hist_entry__transaction_snprintf hist_entry__sym_to_filter hist_entry__sym_from_filter hist_entry__sym_filter hist_entry__symoff_snprintf hist_entry__dso_to_filter hist_entry__dso_from_filter hist_entry__dso_filter hpp_free hde_free hist_entry__trace_snprintf hist_entry__addr_from_snprintf hist_entry__sym_from_snprintf sort__comm_collapse sort__comm_sort sort__srcfile_sort sort__type_init sort__symoff_sort sort__type_cmp hist_entry__dso_snprintf hist_entry__dso_daddr_snprintf sort__typeoff_sort __sort_dimension__add_hpp_output __sort__hpp_equal hse_init hist_entry__dso_from_snprintf sort__type_sort sort__type_collapse __sort__hde_width sort__srcline_from_sort sort__srcline_to_sort __sort__hde_header __sort_dimension__add sort__dso_cmp sort__dso_daddr_cmp sort__srcfile_init sort__srcfile_cmp sort__srcline_cmp hist_entry__addr_to_snprintf sort__dso_from_cmp sort__dso_to_cmp sort__addr_from_cmp sort__addr_to_cmp fill_member_name hist_entry__typeoff_snprintf hist_entry__daddr_snprintf hist_entry__daddr_snprintf.cold hist_entry__iaddr_snprintf hist_entry__iaddr_snprintf.cold hist_entry__dcacheline_snprintf hist_entry__dcacheline_snprintf.cold hist_entry__sym_to_snprintf sort__sym_from_cmp sort__sym_to_cmp sort__symoff_cmp sort__srcline_init sort__srcline_collapse sort__srcline_sort __sort__hde_equal __sort__hde_init hpp_sort_dimensions common_sort_dimensions bstack_sort_dimensions memory_sort_dimensions iter_next_nop_entry hist_entry__free hist_entry__zalloc iter_finish_branch_entry iter_finish_cumulative_entry hist_entry__new default_ops iter_prepare_mem_entry iter_next_branch_entry iter_prepare_branch_entry iter_prepare_cumulative_entry iter_next_cumulative_entry hist_entry__sort resort_filtered_entry iter_prepare_normal_entry hists__match_hierarchy.isra.0 iter_add_next_nop_entry iter_add_single_branch_entry hists__apply_filters hists__hierarchy_output_resort hists__remove_entry_filter hists__findnew_entry __hists__add_entry.constprop.0 iter_add_single_mem_entry iter_add_single_normal_entry iter_add_next_cumulative_entry hists__decay_entry hists_evsel__exit hists__link_hierarchy.isra.0 hists__filter_hierarchy iter_finish_mem_entry iter_add_next_branch_entry iter_finish_normal_entry iter_add_single_cumulative_entry hists_evsel__init rm_rf_depth_pat rm_rf_a_kcore_dir kcore_dir_filter nmi_watchdog.0 cpu__get_topology_int get_max_num set_max_cpu_num max_present_cpu_num aggr_cpu_id__cmp set_max_node_num online.0 affinity.c cputopo.c has_die_topology build_cpu_topology topology.0 open_cgroup match_cgroups add_cgroup_name cgroup_list target.c target__error_str rblist.c __rblist__findnew intlist.c intlist__node_cmp intlist__node_new intlist__node_delete vdso.c machine__thread_dso_type_maps_cb vdso_info_init.0 counts.c pkg_id_hash pkg_id_equal evlist__copy_prev_raw_counts.cold zero.0 stat-shadow.c print_nsecs prepare_metric evsel__stat_type find_stat print_stalled_cycles_back print_instructions print_cycles print_stalled_cycles_front print_itlb_miss print_dtlb_miss print_ll_miss print_l1i_miss print_l1d_miss print_cache_miss print_branch_miss last_name.11 last_pmu.10 stat_print_function.9 stat-display.c new_line_std new_line_metric print_metric_json print_metric_csv print_noise_pct print_metric_header print_metricgroup_header_std print_metric_headers aggr_header_csv aggr_header_lens aggr_printout new_line_json print_running new_line_csv print_metricgroup_header_csv print_metric_std print_metric_only_csv print_metric_only print_metric_only_json print_metric_begin.part.0.constprop.0 print_metricgroup_header_json print_counter_aggrdata print_counter num_print_iv.0 aggr_header_std perf_api_probe.c pid.0 srcline.c inline_list__append_record read_addr2line_record addr2line cached.3 style.2 srcline__tree_insert.cold dso__parse_addr_inlines.cold srccode.c srcfile_htab srcfile_list num_srcfiles map_total_sz synthetic-events.c filter_task perf_event__get_ns_link_info perf_record_mmap2__read_build_id cpu_map_data__synthesize perf_event__get_comm_ids.constprop.0 perf_event__walk_cgroup_tree perf_event__synthesize_modules_maps_cb anonstr.1 __event__synthesize_thread.constprop.0 __event__synthesize_thread.isra.0 __perf_event__synthesize_threads synthesize_threads_worker perf_event__synthesize_threads.part.0 check_backup open_file_read cloexec.c perf_flag_probe probed.2 call-path.c rwsem.c thread-stack.c thread_stack__call_return thread_stack__new __thread_stack__flush thread_stack__pop_ks.isra.0 spark.c ticks.0 topdown.c iostat.c stream.c print_stream_callchain.isra.0 print_callchain_pair.isra.0 auxtrace.c get_flags auxtrace_queue_data_cb parse_sym_idx parse_num_or_str addr_filter__to_str find_entire_kern_cb evlist__regroup.isra.0 find_dso_sym print_kern_sym_cb find_kern_sym_cb find_kern_sym __auxtrace_mmap__read auxtrace_queues__add_buffer auxtrace_queues__add_indexed_event auxtrace_error_type_name intel-pt.c intel_pt_evsel_is_auxtrace intel_pt_free_events intel_pt_free intel_pt_alloc_queue intel_pt_findnew_vmcs_info intel_pt_walk_next_insn intel_pt_pgd_ip intel_pt_match_pgd_ip intel_pt_get_guest intel_pt_sample_flags intel_pt_set_pid_tid_cpu intel_pt_event_synth intel_pt_synth_error intel_pt_queue_data intel_pt_perf_config intel_pt_config_div intel_pt_do_synth_pebs_sample pebs_gp_regs intel_pt_get_trace intel_pt_dump.isra.0 intel_pt_dump_sample intel_pt_process_auxtrace_event intel_pt_prep_sample intel_pt_cache_lookup intel_pt_lookahead intel_pt_sync_switch intel_pt_synth_cbr_sample intel_pt_synth_iflag_chg_sample intel_pt_synth_instruction_sample intel_pt_synth_events_sample intel_pt_next_tid intel_pt_synth_cycle_sample intel_pt_synth_branch_sample intel_pt_synth_transaction_sample intel_pt_synth_psb_sample intel_pt_synth_mwait_sample intel_pt_synth_pwre_sample intel_pt_synth_pwrx_sample intel_pt_synth_exstop_sample intel_pt_synth_ptwrite_sample intel_pt_run_decoder intel_pt_process_queues intel_pt_process_event intel_pt_flush intel_pt_synth_events intel_pt_info_fmts intel-bts.c intel_bts_evsel_is_auxtrace intel_bts_free_events intel_bts_event_synth intel_bts_lost intel_bts_synth_branch_sample intel_bts_synth_events intel_bts_setup_queues.constprop.0 intel_bts_synth_error.isra.0 intel_bts_process_queue intel_bts_process_queues intel_bts_process_event intel_bts_flush intel_bts_process_auxtrace_event intel_bts_free intel_bts_info_fmts arm-spe.c arm_spe_evsel_is_auxtrace arm_spe_free_events arm_spe_set_pid_tid_cpu arm_spe_event_synth arm_spe__update_queues.part.0 arm_spe_get_trace arm_spe__synth_instruction_sample arm_spe_dump.isra.0 arm_spe_process_auxtrace_event arm_spe__synth_branch_sample arm_spe__synth_mem_sample arm_spe_run_decoder neoverse_spe arm_spe_process_queues arm_spe_process_event arm_spe_flush arm_spe_free arm_spe_synth_events hisi-ptt.c hisi_ptt_process_event hisi_ptt_flush hisi_ptt_free_events hisi_ptt_evsel_is_auxtrace hisi_ptt_free hisi_ptt_process_auxtrace_event hisi_ptt_pkt_size s390-cpumsf.c s390_cpumsf_free_events s390_cpumsf_flush s390_cpumsf_evsel_is_auxtrace s390_cpumsf_make_event s390_cpumsf__config s390_cpumsf_synth_error.constprop.0 s390_cpumsf_free s390_cpumsf_process_auxtrace_event s390_cpumsf_process_event cs-etm-base.c cs_etm_global_header_fmts cs_ete_priv_fmts cs_etm_priv_fmts cs_etmv4_priv_fmts parse-branch-options.c branch_modes dump-insn.c parse-regs-options.c __parse_regs.isra.0 parse-sublevel-options.c term.c help-unknown-cmd.c levenshtein_compare perf_unknown_cmd_config autocorrect dlfilter.c dlfilter__args dlfilter__attr find_dlfilter dlfilter__al_cleanup dlfilter__insn dlfilter__srcline dlfilter__object_code dlfilter__resolve_ip dlfilter__resolve_address dlfilter__resolve_addr perf_dlfilter_fns list_filters mem-events.c perf_pmu__mem_events_name mem_loads_name mem_stores_name perf_pmu__mem_events_supported.isra.0 tlb_access mem_lvlnum mem_hops snoop_access mem-info.c vsprintf.c units.c time-utils.c percent_slash_split expr-flex.c normalize expr_ensure_buffer_stack expr_restart.cold expr-bison.c handle_id has_pmem has_pmem.0 branch.c clockid.c clockids list_sort.c sharded_mutex.c bpf_map.c symbol-elf.c cmp_offset kcore_copy__process_modules dso__process_kernel_symbol kcore_copy__process_kallsyms copy_bytes rel_cmp elf_read_build_id.constprop.0 dso__load_sym_internal probe-file.c probe_cache__open.constprop.0 probe_cache__load scan_ftrace_readme ftrace_readme_table scanned.0 __probe_file__get_namelist type_to_suffix probe-event.c synthesize_perf_probe_point find_module_name kernel_get_module_map_cb get_text_start_address.constprop.0 open_debuginfo host_machine kprobe_warn_out_range kprobe_blacklist kernel_get_symbol_address_by_name __show_one_line.constprop.0 parse_perf_probe_event_name __synthesize_probe_trace_arg_ref synthesize_probe_trace_arg get_new_event_name.constprop.0 kprobe_blacklist__load.constprop.0 find_alternative_probe_point __show_line_range concat_probe_trace_events find_cached_events __show_perf_probe_events debuginfo_cache_path debuginfo_cache probe-finder.c convert_to_trace_point convert_variable_location copy_variables_cb convert_variable_fields find_inner_scope_cb add_probe_trace_event pubname_search_cb find_best_scope_cb call_probe_finder line_range_search_cb line_range_inline_cb line_range_walk_cb add_available_vars collect_variables_cb probe_point_lazy_walker probe_point_line_walker find_probe_point_lazy probe_point_search_cb probe_point_inline_cb debuginfo__find_probe_location debuginfo__find_probes.part.0 dwarf-aux.c __die_find_inline_cb __die_find_func_rettype_cb __die_search_func_cb __die_search_func_tail_cb __die_find_scope_cb __die_find_variable_cb __die_collect_vars_cb __die_collect_global_vars_cb __die_find_var_addr_cb __die_find_var_reg_cb __die_walk_instances_cb __die_find_member_offset_cb __die_walk_funclines_cb die_find_child.localalias __die_walk_culines_cb __die_find_member_cb die_is_optimized_target.localalias dwarf-regs.c sparc_regstr_tbl powerpc_regstr_tbl arm_regstr_tbl xtensa_regstr_tbl s390_dwarf_regs x86_32_regstr_tbl mips_regstr_tbl x86_64_regstr_tbl loongarch_regstr_tbl aarch64_regstr_tbl debuginfo.c __debuginfo__new offline_callbacks debuginfo_path check_variable pr_debug_location pr_debug_type_name __add_member_cb print_annotated_data_value print_annotated_data_type global_var__add.isra.0 findnew_stack_state.isra.0 delete_members get_global_var_type unwind-libunwind-local.c __dw_read_encoded_value get_dyn_info_list_addr get_proc_name resume access_fpreg put_unwind_info _unwind__get_entries _unwind__finish_access _unwind__flush_access access_reg access_mem _unwind__prepare_access accessors read_unwind_spec_eh_frame_maps_cb find_proc_info unwind-libunwind.c data-convert-json.c output_json_string output_json_key_format.constprop.1 output_json_key_format.constprop.0 output_json_format.constprop.1 output_json_format.constprop.0 output_json_key_format.constprop.2 output_sample_callchain_entry process_sample_event zlib.c lzma.c zstd.c cap.c demangle-cxx.cpp demangle-ocaml.c demangle-java.c __demangle_java_sym demangle-rust.c unescape jitdump.c shd_string_table bnote genelf_debug.c default_comp_unit_header default_debug_line_header standard_opcode_length jmpbuf current_perf_hook bpf-event.c kallsyms_process_symbol synthesize_bpf_prog_name.constprop.0 bpf_event__sb_cb bpf-utils.c bpil_array_desc lookup_path lookup_triplets.constprop.0 cpuinfo_tsc_freq tsc.0 kvm-stat.c msr_event_decode_key ioport_event_decode_key mmio_event_decode_key ioport_event_end msr_event_begin ioport_event_begin mmio_event_begin msr_event_end mmio_event_end exit_events mmio_events ioport_events msr_events svm_exit_reasons vmx_exit_reasons sdt_op_regex sdt_reg_tbl has_perf_metrics.0 find_extra_kernel_maps perf_event__synthesize_extra_kmaps_cb warned_once.0 iio_pmu_count iio_mapping root_ports iostat_metrics iostat_print_metric.cold is_amd.0 x86_64_regoffset_table x86_regidx_table CSWTCH.2 archinsn.c intel_pt_reference intel_pt_parse_snapshot_options intel_pt_snapshot_finish intel_pt_snapshot_start intel_pt_recording_free intel_pt_info_priv_size intel_pt_val_config_term intel_pt_psb_period intel_pt_find_snapshot intel_pt_default_config intel_pt_info_fill intel_pt_recording_options initialized.3 config.2 intel_bts_info_priv_size intel_bts_reference intel_bts_parse_snapshot_options intel_bts_find_snapshot intel_bts_snapshot_finish intel_bts_snapshot_start intel_bts_recording_free intel_bts_info_fill intel_bts_recording_options Context.c perf_sample_srccode perf_set_itrace_options perf_trace_context_common_lock_depth perf_trace_context_common_flags perf_trace_context_common_pc perf_sample_insn perf_sample_srcline moduledef.0 ContextMethods decompress_event map_for_pmu has_last_result.3 last_result.2 has_last_map_search.1 last_map_search.0 pmu_sys_event_tables metricgroups pmu_events__westmereex_default_core pmu_events__westmereep_sp_default_core pmu_events__westmereep_dp_default_core pmu_metrics__tigerlake_default_core pmu_events__tigerlake_default_core pmu_events__tigerlake_uncore_arb pmu_events__tigerlake_uncore_clock pmu_events__tigerlake_uncore_imc_free_running_0 pmu_events__tigerlake_uncore_imc_free_running_1 pmu_metrics__snowridgex_uncore_iio pmu_metrics__snowridgex_uncore_imc pmu_events__snowridgex_default_core pmu_events__snowridgex_uncore_cha pmu_events__snowridgex_uncore_iio pmu_events__snowridgex_uncore_iio_free_running pmu_events__snowridgex_uncore_imc pmu_events__snowridgex_uncore_imc_free_running pmu_events__snowridgex_uncore_irp pmu_events__snowridgex_uncore_m2m pmu_events__snowridgex_uncore_m2pcie pmu_events__snowridgex_uncore_pcu pmu_events__snowridgex_uncore_ubox pmu_metrics__skylakex_default_core pmu_metrics__skylakex_uncore_iio pmu_metrics__skylakex_uncore_imc pmu_events__skylakex_default_core pmu_events__skylakex_uncore_cha pmu_events__skylakex_uncore_iio pmu_events__skylakex_uncore_imc pmu_events__skylakex_uncore_irp pmu_events__skylakex_uncore_m2m pmu_events__skylakex_uncore_m3upi pmu_events__skylakex_uncore_pcu pmu_events__skylakex_uncore_ubox pmu_events__skylakex_uncore_upi pmu_metrics__skylake_default_core pmu_events__skylake_default_core pmu_events__skylake_uncore_arb pmu_events__skylake_uncore_cbox pmu_events__skylake_uncore_cbox_0 pmu_events__silvermont_default_core pmu_metrics__sierraforest_default_core pmu_events__sierraforest_default_core pmu_events__sierraforest_uncore_b2cmi pmu_events__sierraforest_uncore_b2cxl pmu_events__sierraforest_uncore_b2hot pmu_events__sierraforest_uncore_b2upi pmu_events__sierraforest_uncore_cha pmu_events__sierraforest_uncore_chacms pmu_events__sierraforest_uncore_cxlcm pmu_events__sierraforest_uncore_cxldp pmu_events__sierraforest_uncore_iio pmu_events__sierraforest_uncore_imc pmu_events__sierraforest_uncore_irp pmu_events__sierraforest_uncore_mdf pmu_events__sierraforest_uncore_pcu pmu_events__sierraforest_uncore_upi pmu_metrics__sapphirerapids_default_core pmu_events__sapphirerapids_default_core pmu_events__sapphirerapids_uncore_cha pmu_events__sapphirerapids_uncore_cxlcm pmu_events__sapphirerapids_uncore_cxldp pmu_events__sapphirerapids_uncore_iio pmu_events__sapphirerapids_uncore_iio_free_running pmu_events__sapphirerapids_uncore_imc pmu_events__sapphirerapids_uncore_irp pmu_events__sapphirerapids_uncore_m2hbm pmu_events__sapphirerapids_uncore_m2m pmu_events__sapphirerapids_uncore_m2pcie pmu_events__sapphirerapids_uncore_m3upi pmu_events__sapphirerapids_uncore_mchbm pmu_events__sapphirerapids_uncore_mdf pmu_events__sapphirerapids_uncore_pcu pmu_events__sapphirerapids_uncore_ubox pmu_events__sapphirerapids_uncore_upi pmu_metrics__sandybridge_default_core pmu_events__sandybridge_default_core pmu_events__sandybridge_uncore_arb pmu_events__sandybridge_uncore_cbox pmu_metrics__rocketlake_default_core pmu_events__rocketlake_default_core pmu_events__rocketlake_uncore_arb pmu_events__rocketlake_uncore_clock pmu_events__nehalemex_default_core pmu_events__nehalemep_default_core pmu_events__meteorlake_cpu_atom pmu_events__meteorlake_cpu_core pmu_events__meteorlake_uncore_arb pmu_events__meteorlake_uncore_clock pmu_events__meteorlake_uncore_hac_arb pmu_events__meteorlake_uncore_hac_cbo pmu_events__meteorlake_uncore_imc pmu_events__meteorlake_uncore_imc_free_running_0 pmu_events__meteorlake_uncore_imc_free_running_1 pmu_events__lunarlake_cpu_atom pmu_events__lunarlake_cpu_core pmu_events__knightslanding_default_core pmu_events__knightslanding_uncore_cha pmu_events__knightslanding_uncore_edc_eclk pmu_events__knightslanding_uncore_edc_uclk pmu_events__knightslanding_uncore_imc_dclk pmu_events__knightslanding_uncore_imc_uclk pmu_events__knightslanding_uncore_m2pcie pmu_metrics__jaketown_default_core pmu_events__jaketown_default_core pmu_events__jaketown_uncore_cbox pmu_events__jaketown_uncore_ha pmu_events__jaketown_uncore_imc pmu_events__jaketown_uncore_irp pmu_events__jaketown_uncore_pcu pmu_events__jaketown_uncore_qpi pmu_events__jaketown_uncore_r2pcie pmu_events__jaketown_uncore_r3qpi pmu_events__jaketown_uncore_ubox pmu_metrics__ivytown_default_core pmu_events__ivytown_default_core pmu_events__ivytown_uncore_cbox pmu_events__ivytown_uncore_ha pmu_events__ivytown_uncore_imc pmu_events__ivytown_uncore_irp pmu_events__ivytown_uncore_pcu pmu_events__ivytown_uncore_qpi pmu_events__ivytown_uncore_r2pcie pmu_events__ivytown_uncore_r3qpi pmu_events__ivytown_uncore_ubox pmu_metrics__ivybridge_default_core pmu_events__ivybridge_default_core pmu_events__ivybridge_uncore_arb pmu_events__ivybridge_uncore_cbox pmu_metrics__icelakex_default_core pmu_events__icelakex_default_core pmu_events__icelakex_uncore_cha pmu_events__icelakex_uncore_iio pmu_events__icelakex_uncore_iio_free_running pmu_events__icelakex_uncore_imc pmu_events__icelakex_uncore_imc_free_running pmu_events__icelakex_uncore_irp pmu_events__icelakex_uncore_m2m pmu_events__icelakex_uncore_m2pcie pmu_events__icelakex_uncore_m3upi pmu_events__icelakex_uncore_pcu pmu_events__icelakex_uncore_ubox pmu_events__icelakex_uncore_upi pmu_metrics__icelake_default_core pmu_events__icelake_default_core pmu_events__icelake_uncore_arb pmu_events__icelake_uncore_clock pmu_metrics__haswellx_default_core pmu_events__haswellx_default_core pmu_events__haswellx_uncore_cbox pmu_events__haswellx_uncore_ha pmu_events__haswellx_uncore_imc pmu_events__haswellx_uncore_irp pmu_events__haswellx_uncore_pcu pmu_events__haswellx_uncore_qpi pmu_events__haswellx_uncore_r2pcie pmu_events__haswellx_uncore_r3qpi pmu_events__haswellx_uncore_sbox pmu_events__haswellx_uncore_ubox pmu_metrics__haswell_default_core pmu_events__haswell_default_core pmu_events__haswell_uncore_arb pmu_events__haswell_uncore_cbox pmu_events__haswell_uncore_cbox_0 pmu_events__haswell_uncore_clock pmu_events__graniterapids_default_core pmu_events__graniterapids_uncore_b2cmi pmu_events__graniterapids_uncore_b2cxl pmu_events__graniterapids_uncore_b2hot pmu_events__graniterapids_uncore_b2upi pmu_events__graniterapids_uncore_cha pmu_events__graniterapids_uncore_chacms pmu_events__graniterapids_uncore_cxlcm pmu_events__graniterapids_uncore_cxldp pmu_events__graniterapids_uncore_iio pmu_events__graniterapids_uncore_imc pmu_events__graniterapids_uncore_irp pmu_events__graniterapids_uncore_mdf pmu_events__graniterapids_uncore_pcu pmu_events__graniterapids_uncore_upi pmu_metrics__grandridge_default_core pmu_events__grandridge_default_core pmu_events__grandridge_uncore_b2cmi pmu_events__grandridge_uncore_cha pmu_events__grandridge_uncore_chacms pmu_events__grandridge_uncore_iio pmu_events__grandridge_uncore_imc pmu_events__grandridge_uncore_irp pmu_events__grandridge_uncore_pcu pmu_events__goldmontplus_default_core pmu_events__goldmont_default_core pmu_metrics__emeraldrapids_default_core pmu_events__emeraldrapids_default_core pmu_events__emeraldrapids_uncore_cha pmu_events__emeraldrapids_uncore_cxlcm pmu_events__emeraldrapids_uncore_cxldp pmu_events__emeraldrapids_uncore_iio pmu_events__emeraldrapids_uncore_iio_free_running pmu_events__emeraldrapids_uncore_imc pmu_events__emeraldrapids_uncore_irp pmu_events__emeraldrapids_uncore_m2hbm pmu_events__emeraldrapids_uncore_m2m pmu_events__emeraldrapids_uncore_m2pcie pmu_events__emeraldrapids_uncore_m3upi pmu_events__emeraldrapids_uncore_mchbm pmu_events__emeraldrapids_uncore_mdf pmu_events__emeraldrapids_uncore_pcu pmu_events__emeraldrapids_uncore_ubox pmu_events__emeraldrapids_uncore_upi pmu_metrics__elkhartlake_default_core pmu_events__elkhartlake_default_core pmu_metrics__cascadelakex_default_core pmu_metrics__cascadelakex_uncore_iio pmu_metrics__cascadelakex_uncore_imc pmu_events__cascadelakex_default_core pmu_events__cascadelakex_uncore_cha pmu_events__cascadelakex_uncore_iio pmu_events__cascadelakex_uncore_imc pmu_events__cascadelakex_uncore_irp pmu_events__cascadelakex_uncore_m2m pmu_events__cascadelakex_uncore_m3upi pmu_events__cascadelakex_uncore_pcu pmu_events__cascadelakex_uncore_ubox pmu_events__cascadelakex_uncore_upi pmu_metrics__broadwellx_default_core pmu_events__broadwellx_default_core pmu_events__broadwellx_uncore_cbox pmu_events__broadwellx_uncore_ha pmu_events__broadwellx_uncore_imc pmu_events__broadwellx_uncore_irp pmu_events__broadwellx_uncore_pcu pmu_events__broadwellx_uncore_qpi pmu_events__broadwellx_uncore_r2pcie pmu_events__broadwellx_uncore_r3qpi pmu_events__broadwellx_uncore_sbox pmu_events__broadwellx_uncore_ubox pmu_metrics__broadwellde_default_core pmu_events__broadwellde_default_core pmu_events__broadwellde_uncore_cbox pmu_events__broadwellde_uncore_ha pmu_events__broadwellde_uncore_imc pmu_events__broadwellde_uncore_irp pmu_events__broadwellde_uncore_pcu pmu_events__broadwellde_uncore_r2pcie pmu_events__broadwellde_uncore_ubox pmu_metrics__broadwell_default_core pmu_events__broadwell_default_core pmu_events__broadwell_uncore_arb pmu_events__broadwell_uncore_cbox pmu_events__broadwell_uncore_cbox_0 pmu_events__bonnell_default_core pmu_metrics__amdzen5_default_core pmu_events__amdzen5_amd_l3 pmu_events__amdzen5_amd_umc pmu_events__amdzen5_default_core pmu_metrics__amdzen4_default_core pmu_events__amdzen4_amd_df pmu_events__amdzen4_amd_l3 pmu_events__amdzen4_amd_umc pmu_events__amdzen4_default_core pmu_metrics__amdzen3_default_core pmu_events__amdzen3_amd_df pmu_events__amdzen3_amd_l3 pmu_events__amdzen3_default_core pmu_metrics__amdzen2_default_core pmu_events__amdzen2_amd_df pmu_events__amdzen2_amd_l3 pmu_events__amdzen2_default_core pmu_metrics__amdzen1_default_core pmu_events__amdzen1_amd_df pmu_events__amdzen1_amd_l3 pmu_events__amdzen1_default_core pmu_metrics__alderlaken_default_core pmu_events__alderlaken_default_core pmu_events__alderlaken_uncore_arb pmu_events__alderlaken_uncore_clock pmu_events__alderlaken_uncore_imc pmu_events__alderlaken_uncore_imc_free_running_0 pmu_events__alderlaken_uncore_imc_free_running_1 pmu_metrics__alderlake_cpu_atom pmu_metrics__alderlake_cpu_core pmu_metrics__alderlake_default_core pmu_events__alderlake_cpu_atom pmu_events__alderlake_cpu_core pmu_events__alderlake_uncore_arb pmu_events__alderlake_uncore_clock pmu_events__alderlake_uncore_imc pmu_events__alderlake_uncore_imc_free_running_0 pmu_events__alderlake_uncore_imc_free_running_1 pmu_events__test_soc_sys_uncore_sys_ccn_pmu pmu_events__test_soc_sys_uncore_sys_cmn_pmu pmu_events__test_soc_sys_uncore_sys_ddr_pmu pmu_metrics__test_soc_cpu_default_core pmu_events__test_soc_cpu_default_core pmu_events__test_soc_cpu_hisi_sccl_ddrc pmu_events__test_soc_cpu_hisi_sccl_l3c pmu_events__test_soc_cpu_uncore_cbox pmu_events__test_soc_cpu_uncore_imc pmu_events__test_soc_cpu_uncore_imc_free_running crtstuff.c deregister_tm_clones __do_global_dtors_aux completed.0 __do_global_dtors_aux_fini_array_entry frame_dummy __frame_dummy_init_array_entry pyrf_evlist__length pyrf_cpu_map__init kwlist.7 pyrf_cpu_map__length pyrf_cpu_map__item pyrf_evlist__item pyrf_cpu_map__delete pyrf_thread_map__init kwlist.6 pyrf_thread_map__length pyrf_thread_map__item pyrf_thread_map__delete pyrf_context_switch_event__repr pyrf_sample_event__repr pyrf_lost_event__repr pyrf_mmap_event__repr pyrf_sample_event__getattro pyrf_read_event__repr pyrf_throttle_event__repr pyrf_task_event__repr pyrf_comm_event__repr pyrf_evsel__init kwlist.5 pyrf_evsel__open kwlist.4 pyrf_evsel__delete pyrf_evlist__init pyrf_evlist__add pyrf_evlist__poll kwlist.2 pyrf_evlist__delete pyrf_evlist__read_on_cpu kwlist.3 pyrf_event__type pyrf_evlist__get_pollfd pyrf_evlist__open pyrf_evlist__mmap kwlist.1 pyrf__tracepoint kwlist.0 moduledef.8 pyrf_mmap_event__type pyrf_throttle_event__type pyrf_context_switch_event__type pyrf_sample_event__type pyrf_read_event__type pyrf_lost_event__type pyrf_comm_event__type pyrf_task_event__type pyrf_evlist__type pyrf_evsel__type pyrf_thread_map__type pyrf_cpu_map__type perf__constants perf__methods pyrf_evlist__sequence_methods pyrf_evlist__doc pyrf_evlist__methods pyrf_evsel__doc pyrf_evsel__methods pyrf_thread_map__sequence_methods pyrf_thread_map__doc pyrf_cpu_map__sequence_methods pyrf_cpu_map__doc pyrf_context_switch_event__doc pyrf_context_switch_event__members pyrf_sample_event__doc pyrf_sample_event__members pyrf_read_event__doc pyrf_read_event__members pyrf_lost_event__doc pyrf_lost_event__members pyrf_throttle_event__doc pyrf_throttle_event__members pyrf_comm_event__doc pyrf_comm_event__members pyrf_task_event__doc pyrf_task_event__members pyrf_mmap_event__doc pyrf_mmap_event__members __FRAME_END__ perf_evlist__mmap_ops perf_evsel__init strset__find_str probe_fd perf_evlist__read_format bpf_core_calc_relo_insn strset__data get_kernel_version libbpf_add_mem strset__free __perf_evlist__set_leader bpf_core_format_spec __TMC_END__ perf_evsel__read_size perf_evlist__add_pollfd perf_evsel__apply_filter probe_kern_syscall_wrapper __bpf_core_types_match hashmap__capacity libbpf_nla_parse bpf_gen__map_create perf_evlist__alloc_pollfd perf_mmap__munmap usdt_manager_free perf_evsel__free_id perf_evsel__free_fd __bpf_core_types_are_compat parse_cpu_mask_str libbpf__load_raw_btf libbpf_print xyarray__new perf_evsel__alloc_fd bpf_gen__prog_load bpf_gen__init perf_cpu_map__set_nr parse_btf_map_def bpf_gen__record_attach_target zip_archive_find_entry xyarray__reset kernel_supports perf_evsel__close_fd btf__find_by_name_kind_own elf_resolve_syms_offsets bpf_gen__map_freeze bpf_gen__finish perf_cpu_map__is_subset btf_relocate elf_find_func_offset btf_get_kernel_prefix_kind perf_cpu_map__alloc libbpf_ensure_mem btf_field_iter_next btf_type_by_id zip_archive_close btf_field_iter_init preadn _GLOBAL_OFFSET_TABLE_ elf_resolve_pattern_offsets probe_memcg_account hashmap__size bpf_gen__map_update_elem _DYNAMIC xyarray__delete hashmap__init elf_find_func_offset_from_file hashmap__clear bpf_gen__load_btf btf_get_from_fd perf_mmap__init perf_cpu_map__idx atexit libbpf_strerror_r perf_mmap__get bump_rlimit_memlock hashmap_find libbpf_nla_parse_nested bpf_gen__record_extern strset__new writen btf_header bpf_gen__record_relo_core __zfree perf_evlist__id_add parse_cpu_mask_file btf_ext_visit_type_ids perf_mmap__mmap_len bpf_gen__populate_outer_map usdt_manager_attach_usdt bpf_core_parse_spec perf_evsel__alloc_id zip_archive_open __GNU_EH_FRAME_HDR hashmap_insert bpf_core_essential_name_len libperf_print glob_match bpf_core_free_cands perf_mmap__mmap feat_supported perf_evlist__reset_id_hash perf_mmap__read_head hashmap__free bpf_core_patch_insn __dso_handle btf_ext_visit_str_offs hashmap_delete elf_close usdt_manager_new perf_mmap__put elf_open strset__data_size sys_bpf_prog_load perf_mmap__read_self strset__add_str btf_load_into_kernel bpf_core_add_cands hashmap__new perf_evlist__exit bpf_gen__free perf_evlist__init perf_evlist__id_add_fd perf_evlist__go_system_wide perf_thread_map__realloc skip_mods_and_typedefs libbpf_nla_dump_errormsg btf_set_base_btf __bitmap_or perf_event_paranoid_check maps__fixup_end perf_pmu__mem_events_init intel_pt_decoder_free ui_browser__help_window parse_events__is_hardcoded_term insn_get_length auxtrace__dump_auxtrace_sample btf__load_into_kernel libbpf_probe_bpf_map_type perf_evlist__poll evlist__toggle_enable nsinfo__mountns_enter maps__put perf_config_bool lock_stat_find syscalltbl__new btf_dump__dump_type pstack__push evlist__toggle_bkw_mmap ui_browser__reset_index __openat64_2@GLIBC_2.7 dso__data_put_fd suite__hybrid debuginfo__find_line_range perf_event_attr__fprintf strtobool print_symbol_events parse_events_get_lineno addr_map_symbol__exit do_write __perf_hook_desc_record_start pr_stat maps__equal build_id__init __perf_reg_name_mips tui_helpline_fns pmu_events__test_soc_sys evlist_cpu_iterator__end intlist__find arch_evsel__open_strerror dso__set_module_info wait@GLIBC_2.2.5 zstd_fini strdup@GLIBC_2.2.5 perf_event__process_switch hist_iter_branch perf_event__fprintf_task cu_find_lineinfo perf_event__fprintf_namespaces pmu_events_table__for_each_event perf_tool_event__from_str parse_callchain_record _Py_Dealloc dsos__findnew_module_dso dwarf_addrdie@ELFUTILS_0.122 annotate_parse_percent_type parse_clockid user_access_is_supported cpu__get_node PyLong_FromLong arch_evsel__set_sample_weight annotation__update_column_widths perf_pmu__scan_bytes elf64_newehdr@ELFUTILS_1.0 bpf_map__lookup_elem test__amd_ibs_via_core_pmu btf__name_by_offset ui_browser__refresh_dimensions evlist__strerror_mmap dso__data_read_offset getsockname@GLIBC_2.2.5 suite__demangle_java open_svg btf__load_vmlinux_btf dso__needs_decompress tests__symbols branch_type_str map__fprintf_srcline perf_config_scan cond_init_pshared inat_group_table_15_2 parse_events_option evsel__name_is perf_debug_option perf_data__size map__objdump_2mem perf_mem__lck_scnprintf uname@GLIBC_2.2.5 pthread_mutexattr_setpshared@GLIBC_2.34 feof@GLIBC_2.2.5 exit_rwsem ui__question_window dso__set_short_name perf_pmu__is_software PyUnicode_FromFormat evsel__id_hdr_size __perf_reg_ip_riscv reset_fd_limit epoll_ctl@GLIBC_2.3.2 symbols__fixup_duplicate bpf_prog_linfo__lfind_addr_func numa_num_configured_cpus@libnuma_1.2 setup_python_scripting cpu_map__new_data callchain_append machine__is fdopen@GLIBC_2.2.5 sample__resolve_mem perf_singlethreaded parse_events_terms PyModule_Create2 inat_group_table_17_1 hists__filter_by_socket mmap_cpu_mask__duplicate bpf_map_get_fd_by_id_opts machine__process_lost_event symlink@GLIBC_2.2.5 ids__insert dso__fprintf suite__pfm symbol__annotate sort_time pclose@GLIBC_2.2.5 numa_node_to_cpus@libnuma_1.2 arm_spe_process_auxtrace_info dsos__fprintf_buildid select@GLIBC_2.2.5 usage_with_options_msg perf_kwork_add_work __isoc23_strtoul@GLIBC_2.38 memcpy@GLIBC_2.14 evsel__group_desc lsdir db_export__branch_type _find_next_zero_bit pmu_events__amdzen3 thread__find_map_fb btf__new_empty perf_buffer__new_raw raw_field_value workload__noploop gelf_xlatetom@ELFUTILS_1.0 perf_config_system avg_stats svg_interrupt bpf_map__set_key_size bpf_link_create die_is_func_instance print_tool_events bpf_map_create maps__set_unwind_libunwind_ops is_bts_event __isoc99_sscanf@GLIBC_2.7 bpf_btf_load strlist__add evlist__id2sid inline_node__delete record_opts__config rblist__delete pstack__new suite__parse_events dots realloc@GLIBC_2.2.5 evsel_streams__report tep_print_event comm__override ZSTD_initCStream perf_parse_sublevel_options perf_thread_map__pid thread_map__new_by_uid tests__thread_map_synthesize perf_pmu__find_metrics_table _sort__sym_cmp debuginfo__delete compat_auxtrace_mmap__write_tail machine__process_itrace_start_event perf_evlist__enable perf_env__arch_strerrno expr_get_out btf__add_typedef convert_unit_double build_id__mark_dso_hit svg_io_legenda scandirat64@GLIBC_2.15 perf_config_set __perf_reg_sp_csky ignore_callees_regex bpf_program__unload bpf_map__set_max_entries gelf_getverdaux@ELFUTILS_1.0 PyDict_SetItemString thread__new strndup@GLIBC_2.2.5 dso__sort_by_name default_parent_pattern default_branch_sort_order symbol__tty_annotate2 argv_split inat_group_table_26 cpu__get_die_id timestamp__scnprintf_nsec bench_format nsinfo__in_pidns pthread_mutex_destroy@GLIBC_2.2.5 evsel__config callchain_param dwfl_report_begin@ELFUTILS_0.122 intel_pt_pmu_default_config _ITM_deregisterTMCloneTable sort_mem_lvl perf_config_u8 ZSTD_freeCStream SLtt_get_terminfo@SLANG2 show_available_funcs bpf_map_lookup_and_delete_batch die_collect_global_vars cgroup__new hist_browser__init hist_browser__delete suite__bp_signal perf_hpp__set_elide die_find_member inat_escape_table_2_1 auxtrace_queues__add_event btf__free numa_allocate_nodemask@libnuma_1.2 tracefs__configured bpf_program__attach_tcx EVP_DigestUpdate@OPENSSL_3.0.0 debug_display_time kallsyms__is_function tep_get_events_count evlist__enable_evsel evlist__set_tracking_event btf__add_restrict down_read access@GLIBC_2.2.5 __perf_reg_ip_powerpc map_symbol__tui_annotate cpu__max_node bpf_object__load dso__set_build_id bpf_tc_hook_destroy maps__empty perf_stat__skip_metric_event tests__kmod_path__parse tests__event_groups insn_get_immediate cgroupfs_find_mountpoint perf_event__process_tracing_data threads__init parse_events_set_lval evsel__prepare_open hpp__fmt_acc __get_srcline evlist__parse_sample_timestamp events_stats__auxtrace_error_warn dso__decompress_kmodule_path tests__fdarray__filter perf_event__process_lost_samples bpf_prog_linfo__new ioctl@GLIBC_2.2.5 bench_synthesize __ctype_b_loc@GLIBC_2.3 setsockopt@GLIBC_2.2.5 suite__time_utils inat_primary_table dso_to_test sort_mispredict nsinfo__put file__read_maps dwfl_report_end@ELFUTILS_0.122 dump_insn del_perf_probe_events arch__post_process_probe_trace_events PySys_SetArgv argv_free bpf_enable_stats evsel__is_aux_event evlist__valid_sample_type probe_cache__add_entry ring_buffer__poll compat_auxtrace_mmap__read_head perf_buffer__epoll_fd die_get_scopes map__kmaps perf_cpu_map__empty_new dwarf_attr@ELFUTILS_0.122 __build_id_cache__add_s sort_dso_to pmu_metrics__sierraforest evlist__cpu_begin map__find_symbol_by_name_idx perf_can_sample_identifier parse_events_lex pmu_events__test_soc_cpu threads__find print_hwcache_events bpf_map_get_next_id parse_events__delete_buffer pmu_events__emeraldrapids SLsmg_set_color@SLANG2 dsos__findnew_id bpf_object__unpin_programs SLang_getkey@SLANG2 perf_event_mlock_kb_in_pages path__join3 __intel_pt_log_packet setup_sorting fcntl@GLIBC_2.2.5 strncpy@GLIBC_2.2.5 perf_evlist__filter_pollfd perf_env__read_cpu_topology_map btf__resolve_size itrace_parse_synth_opts perf_pmu__warn_invalid_config localtime_r@GLIBC_2.2.5 memmove@GLIBC_2.2.5 intel_pt_insn_desc PyModule_GetDict PyObject_SetAttrString sort_cycles thread__find_symbol_fb procfs__mountpoint evsel__name __assert_fail@GLIBC_2.2.5 perf_hpp_list parse_events_get_lloc evlist__finalize_ctlfd fcntl64@GLIBC_2.28 ui_browser__gotorc_title numa_bitmask_free@libnuma_1.2 evlist__set_tp_filter_pids test__dwarf_unwind dwarf_getsrclines@ELFUTILS_0.122 auxtrace_mmap_params__init tests__keep_tracking auxtrace_record__free __xpg_strerror_r@GLIBC_2.3.4 parse_user_regs bpf_program__fd bpf_fs__configured sort_comm evsel__clone recvmsg@GLIBC_2.2.5 pthread_attr_init@GLIBC_2.2.5 evsel__config_callchain hists__filter_by_dso trace_report bpf_map_update_elem pthread_sigmask@GLIBC_2.32 cond_wait bpf_map_lookup_elem toupper@GLIBC_2.2.5 __sw_hweight32 hists__overhead_width maps__load_first tep_set_page_size bpf_program__type bench_epoll_wait find_core_metrics_table evsel__field intel_pt_log_dump_buf __isoc99_fscanf@GLIBC_2.7 pthread_rwlock_init@GLIBC_2.34 block_info__new pmu_metrics_table__for_each_metric suite__mem2node dso__find_symbol_nocache fdarray__exit callchain_total_hits evlist__stop_sb_thread perf_event__synthesize_stat_events PyMem_RawFree perf_pmu__format_bits perf_pmu__find_events_table perf_event__synthesize_tracing_data db_export__exit thread_stack__event bpf_map__reuse_fd mutex_destroy dlsym@GLIBC_2.34 dwarf_diecu@ELFUTILS_0.122 bpf_map__map_flags scandir64@GLIBC_2.2.5 perf_thread_map__get perf_pmus__find libbpf_strerror bpf_map_get_fd_by_id pmu_events__nehalemex tep_parse_event evlist__can_select_event svg_page_width pmu_name_len_no_suffix bpf_map__initial_value callchain_node__fprintf_value EVP_MD_CTX_new@OPENSSL_3.0.0 perf_thread_map__put aggr_cpu_id__node dso__data_file_size mkstemp64@GLIBC_2.2.5 parse_events_error__exit map__srcline __cxa_finalize@GLIBC_2.2.5 thread_stack__set_trace_nr sort_type perf_session__peek_events _Ux86_64_flush_cache perf_event__process_mmap arch_perf_parse_sample_weight perf_event__synthesize_event_update_unit ptrace@GLIBC_2.2.5 auxtrace_mmap__mmap pmu_events__westmereep_sp bpil_offs_to_addr cgroup__get kvm_reg_events_ops machine__fprintf sysfs__write_int build_id_cache__complement pmu_events__ivytown perf_event__sample_event_size addr_location__exit intel_pt_decode debugfs__configured perf_mmap__read_done dwarf_bitoffset@ELFUTILS_0.143 dso__last_symbol perf_can_comm_exec arch_get_runtimeparam dwarf_diename@ELFUTILS_0.122 mutex_lock tep_read_number perf_data__write get_srcline_split hist_entry__filter evlist__append_tp_filter ui_browser__run insn_get_prefixes trace_seq_do_fprintf __intel_pt_log_insn_no_data hex_width bpf_prog_linfo__lfind dwarf_formref_die@ELFUTILS_0.122 hist_entry__srcline sample_addr_correlates_sym ins__scnprintf rb_first expr_get_lval perf_evsel__enable_cpu annotate_get_insn_location user_ring_buffer__reserve find_core_events_table machine__remove_thread __sched_cpufree@GLIBC_2.7 mem_bswap_64 syscall@GLIBC_2.2.5 hists__total_period evlist__mmap_size bpf_program__log_level insn_init perf_pmu__config_terms evlist__disable_evsel perf_cpu_map__new bpf_btf_get_next_id SLsmg_fill_region@SLANG2 auxtrace__flush_events suite__bp_signal_overflow ann_data_stat libbpf_set_strict_mode perf_event__process_exit pmu_metrics__emeraldrapids perf_session__fprintf_info perf_pmu__scan_file machine__process_aux_output_hw_id_event tests__bp_accounting perf_event__fprintf_stat machine__for_each_thread evsel__store_ids pstack__pop suite__thread_maps_share filename__read_str mount@GLIBC_2.2.5 machine__idle_thread immediate_value_is_supported symbol__restricted_filename bpf_map_freeze debugfs__mountpoint machine__fprintf_dsos_buildid __perf_env__insert_bpf_prog_info inat_group_table_10 maps__find_next_entry strbuf_detach sort_type_offset sort_addr_from auxtrace_regroup_aux_output nsinfo__init __vsnprintf_chk@GLIBC_2.3.4 get_term_dimensions iostat_print_counters bpf_program__attach_kprobe mem_info__put btf__new_empty_split syscalltbl__id_at_idx get_arch_regnum dso__loaded inat_group_tables sort_dso_size __perf_reg_name_loongarch perf_env__read_pmu_mappings synthesize_perf_probe_command perf_cpu_map__read machine__new_kallsyms vcpu_id_str evlist_cpu_iterator__next tep_set_long_size SLsmg_draw_box@SLANG2 copyfile_ns inat_get_group_attribute die_get_varname perf_event__process_namespaces is_mem_loads_aux_event dwarf_onesrcline@ELFUTILS_0.122 intlist__add dso__new_id sigqueue@GLIBC_2.2.5 unlink@GLIBC_2.2.5 hist_entry__collapse hists__link hisi_ptt_pkt_desc expr_id_data__source_count auxtrace_index__process evlist__reset_prev_raw_counts get_bpf_prog_info_linear expr__add_id_val_source_count sort_srcline_to pmu_metrics__icelake parse_events_terms__delete test_attr__open bench_uprobe_trace_printk_ret strncmp@GLIBC_2.2.5 bpf_map__set_autoattach perf_cpu_map__has_any_cpu_or_is_empty symbol__annotate_zero_histogram lzma_end@XZ_5.0 pmu_name_cmp perf_cpu_map__put hists__get_entry block_info__process_sym kvm_exit_trace perf_event__fprintf numa_node_of_cpu@libnuma_1.2 perf_evsel__open tests__api_io expr__strcmp_cpuid_str __symbol__fprintf_symname_offs parse_events_set_out copyfile_mode btf__align_of default_tracepoint_sort_order sort_srcfile bpf_program__attach_freplace bpf_fs__mount auxtrace_parse_snapshot_options srcline_full_filename suite__thread_map errx@GLIBC_2.2.5 thread_stack__sample_late inflateInit2_ perf_evsel__delete pthread_mutex_unlock@GLIBC_2.2.5 parse_events_terms__init pmu_for_each_core_metric perf_event_paranoid bench_kallsyms_parse perf_evsel__mmap fdarray__grow arch_topdown_sample_read evlist__tui_browse_hists bench__runtime add_perf_probe_events die_find_tailfunc pmu_events__amdzen5 ungetc@GLIBC_2.2.5 pmu_metrics__broadwellde _Ux86_64_is_signal_frame evlist__alloc_aggr_stats perf_cpu_map__equal expr_set_extra pthread_mutexattr_destroy@GLIBC_2.34 hists__reset_stats dwarf_getlocations@ELFUTILS_0.157 gmtime@GLIBC_2.2.5 perf_evlist__open perf_event__synthesize_extra_attr __fprintf_chk@GLIBC_2.3.4 maps__remove_maps perf_buffer__consume is_regular_file machine__hit_all_dsos bpf_prog_linfo__free cpu__get_core_id ordered_events__init perf_event__process_event_update btf__fd dso__strerror_load tep_unload_plugins bench_mem_find_bit ftell@GLIBC_2.2.5 arch_perf_header_entry parse_events__scan_buffer perf_counts_values__scale PyUnicode_FromString btf__add_str auxtrace_queues__init_nr dwarf_getlocation@ELFUTILS_0.122 maps__find btf_dump__free ids__new bpf_program__autoload btf__type_by_id PyErr_NoMemory parse_events__add_event arch__choose_best_symbol inat_avx_table_5_1 ui__init pmu_metrics__icelakex bpf_raw_tracepoint_open_opts parse_events__filter_pmu btf__parse perf_pmus__have_event inat_group_table_4 perf_event__process_bpf perf_cpu_map__has perf_event__synthesize_stat_round sort_abort bpf_program__get_type block_range__create cpu_topology__core_wide suite__thread_map_synthesize PyErr_Print btf__add_func_param evsel__taskstate sysctl_perf_event_max_contexts_per_stack mkdir@GLIBC_2.2.5 __memset inat_group_table_24 pmu_events__skylake perf_stat__reset_shadow_stats output_field_add arch__intr_reg_mask suite__hists_output expr_get_lineno probe_cache__delete perf_cap__capable evlist__set_tp_filter __perf_reg_name_powerpc __dsos__add exclude_perf perf_probe_event__copy tracing_events__opendir PyErr_SetString geteuid@GLIBC_2.2.5 evlist__add_wakeup_eventfd ordered_events__queue bpf_program__pin pthread_mutex_lock@GLIBC_2.2.5 perf_color_default_config inat_escape_table_2_3 evlist__reset_aggr_stats perf_pmu__for_each_event thread_map__new_by_tid_str SLsmg_write_string@SLANG2 thread__comm_str expr_lex_init hists__col_len perf_tip cond_destroy cpu_topology__delete read_tracing_data syscalltbl__delete intel_pt_log_disable pthread_once@GLIBC_2.34 svg_highlight_name dso__data_size hisi_ptt_process_auxtrace_info __cxa_demangle@CXXABI_1.3 PyObject_CallObject perf_evlist__next_mmap evlist__findnew_cgroup perf_thread_map__new_dummy strtok@GLIBC_2.2.5 parse_options_subcommand bpf_object__next_program sched_getcpu@GLIBC_2.6 thread__exec_comm machine__thread_exec_comm alarm@GLIBC_2.2.5 arm64_unwind_libunwind_ops intel_pt_decoder_new thread__resolve_callchain tests__syscall_openat_tp_fields parse_events_term__str sort_mem_daddr_sym pmu_metrics__tigerlake dso__symtab_origin block_info__create_report readlink@GLIBC_2.2.5 parse_events_add_tracepoint __stack_chk_fail@GLIBC_2.4 inat_escape_table_3 ui_browser__rb_tree_refresh svg_lbox suite__expr decay_callchain dso__load_sym machine__thread_list pmu_events_map evlist__set_default_cgroup tep_print_fields dwfl_module_addrsym@ELFUTILS_0.127 bpil_addr_to_offs pthread_cond_destroy@GLIBC_2.3.2 perf_pmu_get_extra dso__is_vdso pthread_barrier_init@GLIBC_2.34 perf_evsel__munmap tests__sigtrap perf_pmu_wrap probe_cache__commit gelf_getshdr@ELFUTILS_1.0 suite__mmap_thread_lookup perror@GLIBC_2.2.5 disasm_line__is_valid_local_jump inat_get_avx_attribute sort_sym_ipc_null dwarf_child@ELFUTILS_0.122 poll@GLIBC_2.2.5 tests__bp_signal parse_events_alloc insn_get_displacement disasm_line__free btf__endianness bench_uprobe_trace_printk machine__normalized_is describe_metricgroup strtok_r@GLIBC_2.2.5 perf_counts__delete btf__add_struct build_id_cache__remove_s sighandler_dump_stack dwarf_entrypc@ELFUTILS_0.122 hpp_color_scnprintf pthread_rwlock_destroy@GLIBC_2.34 call_return_processor__free parse_callchain_record_opt perf_hpp_fmt__dup str_error_r pthread_attr_setstacksize@GLIBC_2.34 __longjmp_chk@GLIBC_2.11 dsos__find __ctype_toupper_loc@GLIBC_2.3 pmu_events__broadwellde evlist__strerror_open pthread_join@GLIBC_2.34 have_tracepoints threads__exit evlist__apply_filters perf_event__synthesize_for_pipe memset@GLIBC_2.2.5 sort__setup_elide list_sort btf__load_module_btf expr__add_ref get_percent_color expr_wrap thread_stack__br_sample perf_session__fprintf_dsos_buildid dso__load hist__account_cycles debuginfo__get_text_offset lsdir_no_dot_filter find_source_path sigchain_push_common modules__parse callchain_node__scnprintf_value strfilter__string inat_get_opcode_attribute evsel__hw_cache perf_config_global sscanf@GLIBC_2.2.5 SLkp_define_keysym@SLANG2 libbpf_unregister_prog_handler is_perf_magic __perf_hook_func_test ins__is_call sched_getaffinity@GLIBC_2.3.4 hists__reset_col_len perf_pmus__destroy symbol__new atoi@GLIBC_2.2.5 dwarf_cfi_end@ELFUTILS_0.142 copyfile strbuf_init bpf_object__prev_map hists__collapse_resort machines__fprintf_dsos arch__sample_reg_masks fputs@GLIBC_2.2.5 pmu_events__cascadelakex bpf_link__open memchr_inv bpf_map_get_next_key perf_hpp__is_dynamic_entry dsos__for_each_dso perf_session__cpu_bitmap evsel__source_count parse_events_term__term perf_pmu_set_out pmu_events__alderlake hists__decay_entries dso_id__cmp auxtrace_record__snapshot_finish alphasort64@GLIBC_2.2.5 perf_event__process_stat_event machines__destroy_kernel_maps dso__read_running_kernel_build_id pmu_metrics__alderlake distro_dwarf_types perf_session__findnew bench_syscall_fork kvm_skip_events __ui_browser__line_arrow line_range__init evlist__find_tracepoint_by_id maps__unwind_libunwind_ops bpf_link_get_fd_by_id perf_pmu__switch_to_buffer pmu_metrics__skylake map__clone clock_gettime@GLIBC_2.17 trace_event__register_resolver auxtrace_heap__pop thread__find_cpumode_addr_location tep_set_loglevel sort_srcline_from unit_number__scnprintf regcomp@GLIBC_2.2.5 script_browse intel_pt__strerror machines__for_each_thread perf_config_set__delete call_path__findnew bpf_prog_get_fd_by_id suite__intel_pt pmu_events__jaketown suite__syscall_openat_tp_fields bpf_map__fprintf elf_nextscn@ELFUTILS_1.0 btf_dump__emit_type_decl bpf_map__set_numa_node walltime_nsecs_stats btf__str_by_offset inat_group_table_5 __evlist__add_default_attrs faccessat@GLIBC_2.4 annotate_check_args sysfs__read_str perf_pmu_set_extra send@GLIBC_2.2.5 PyUnicode_FromStringAndSize bpf_obj_get_opts ui_browser__list_head_seek auxtrace__process_event trace_event__init perf_pmus__num_core_pmus evlist__has_amd_ibs hpp_dimension__add_output evlist_streams__delete parse_events__flush_buffer gzgets bench_futex_hash sort_mem_data_page_size parse_intr_regs perf_event__fprintf_stat_round p0 mem2node__node pthread_setspecific@GLIBC_2.34 suite__hists_cumulate perf_event__name usage_with_options machine__load_vmlinux_path elf64_newphdr@ELFUTILS_1.0 parse_events_get_text parse_events_multi_pmu_add_or_add_pmu perf_evsel__mmap_base dwfl_offline_section_address@ELFUTILS_0.122 bpf_prog_get_info_by_fd bpf_link__detach bpf_object__gen_loader gelf_newphdr@ELFUTILS_1.0 __perf_reg_ip_loongarch perf_gtk_handle session_done perf_session__create_kernel_maps btf__add_enum suite__python_use ui_browser__update_nr_entries callchain_branch_counts perf_hpp__init __isoc23_strtoll@GLIBC_2.38 getcwd@GLIBC_2.2.5 pmu_events__knightslanding svg_highlight strfilter__delete __perf_hook_func_record_end gelf_fsize@ELFUTILS_1.0 sort_srcline default_mem_sort_order perf_hpp__is_srcfile_entry sort_global_ins_lat expr_set_in creat64@GLIBC_2.2.5 __strncpy_chk@GLIBC_2.3.4 syscalltbl__strglobmatch_first pthread_mutex_init@GLIBC_2.2.5 getrlimit64@GLIBC_2.2.5 numa_bitmask_setbit@libnuma_1.2 btf__add_datasec_var_info strglobmatch_nocase filename__read_int bpf_program__attach_raw_tracepoint_opts evlist__ctlfd_initialized expr__ctx_free dsos__fprintf expr_realloc btf_ext__get_raw_data tep_print_field warnx@GLIBC_2.2.5 svg_blocked evlist__prepare_workload hist_entry__annotate_data_tty pmu_events__goldmont input_name parse_events_formats_error_string probe_file__get_events perf_event__synthesize_id_sample evlist__valid_read_format sysfs__mount bench_syscall_execve bpf_program__attach_trace_opts suite__code_reading bpf_link__update_map is_event_supported perf_pmu_push_buffer_state vscnprintf svg_close dso__build_id_equal perf_session__has_traces perf_hpp__reset_width sysfs__read_build_id dsos__read_build_ids __test_function dso__reset_find_symbol_cache threads__nr ui_browser__dialog_yesno perf_config_u64 ordered_events__free branch_name bench_syscall_basic perf_pmus__add_test_pmu __gmon_start__ perf_event__process_lost perf_script__meminfo_scnprintf x86_32_unwind_libunwind_ops machine__process_mmap2_event PyList_Append evsel__env perf_hpp_list__prepend_sort_field strlen@GLIBC_2.2.5 sort_simd db_export__init proc_map_timeout perf_hpp__is_trace_entry bpf_map__btf_key_type_id numa_bitmask_clearall@libnuma_1.2 backtrace_symbols@GLIBC_2.2.5 srccode_state_free intel_pt_pkt_name fdarray__delete parse_events__set_leader evsel__is_leader symbol__hists hists__add_entry_block inat_escape_table_1_1 strcpy@GLIBC_2.2.5 dso__set_long_name machine__fprintf_vmlinux_path inat_escape_table_3_3 tests__demangle_java percent_color_fprintf s390_cpumsf_process_auxtrace_info inlines__tree_find perf_event__synthesize_event_update_cpus __ctype_tolower_loc@GLIBC_2.3 expr_get_leng callchain_list__sym_name perf_read_values_display cond_broadcast debuginfo__find_probe_point map__fixup_end bpf_map__set_pin_path unsetenv@GLIBC_2.2.5 hists__output_resort perf_pmu_get_in thread_map__new_by_pid block_info__free_report tests__dlfilter parse_events_lex_destroy rmdir@GLIBC_2.2.5 copy_config_terms pthread_cond_init@GLIBC_2.3.2 perf_can_aux_sample build_id_cache__linkname libbpf_minor_version perf_counts__new expr_get_in annotation__get_branch __perf_reg_sp_riscv perf_stat__print_shadow_stats __perf_reg_name_x86 dso__first_symbol suite__sigtrap perf_event__process_feature reset_dimensions fclose@GLIBC_2.2.5 numa_bitmask_isbitset@libnuma_1.2 machine__delete expr__create_buffer SLsmg_reinit_smg@SLANG2 memchr@GLIBC_2.2.5 test__arch_unwind_sample tests__fdarray__add auxtrace__free_events symbols__fixup_end perf_hpp__is_sym_entry map__fprintf_dsoname_dsoff inat_avx_table_7_2 elf_kind@ELFUTILS_1.0 __bpf_event__print_bpf_prog_info machine__process_aux_event _find_next_bit suite__basic_mmap suite__unit_number__scnprint machines__findnew_guest_code perf_etc_perfconfig tests__attr target__validate bpf_program__name parse_events_set_lloc bench_futex_wake_parallel perf_pmu_lex_init_extra test_attr__init perf_pmu__event_source_devices_fd tep_find_common_field regfree@GLIBC_2.2.5 cap_free maps__find_symbol_by_name perf_env__read_cpuid hist_browser__run SLsmg_write_wrapped_string@SLANG2 dwfl_build_id_find_elf@ELFUTILS_0.130 perf_pmu__open_file_at tests__mem psignal@GLIBC_2.2.5 strfilter__or svg_legenda inat_avx_table_5_3 __vasprintf_chk@GLIBC_2.8 evlist__to_front timestamp__scnprintf_usec perf_tui_eops hists__inc_nr_events __perf_reg_sp_mips perf_config_colorbool parse_events_term__delete inat_group_table_6 suite__cpu_map bpf_map__type pager_in_use subcmd_config evsel__sys_has_perf_metrics kvm_exit_reason evsel__fallback mutex_init_pshared metricgroup__parse_groups _Py_FatalErrorFunc PyArg_ParseTuple kallsyms2elf_type sort_local_weight perf_pmu__delete parse_events_restart tests__pe_file_parsing machine__exit strfilter__new parse_task_states hists__inc_nr_samples dwfl_module_relocation_info@ELFUTILS_0.122 bpf_map__get_next_key pmu_events_table__find_event perf_pmus__pmu_for_pmu_filter perf_hpp__format disasm_line__scnprintf auxtrace__evsel_is_auxtrace setvbuf@GLIBC_2.2.5 leaf ui_browser__write_nstring bpf_map_delete_batch sort_help pthread_mutex_trylock@GLIBC_2.34 socket@GLIBC_2.2.5 callchain_avg_cycles maps__get bench_inject_build_id strbuf_add auxtrace_cache__alloc_entry rb_replace_node bench_uprobe_baseline sort_mem_blocked parse_events_error__handle auxtrace_buffer__drop_data bpf_object__find_map_by_name auxtrace_mmap__munmap __perf_reg_ip_mips epoll_create@GLIBC_2.3.2 procfs__mount perf_event__synthesize_thread_map2 db_export__machine db_export__symbol dso__type_fd kallsyms__parse bpf_program__attach_raw_tracepoint bpf_map__set_map_extra perf_pmu__mem_events_list strstr@GLIBC_2.2.5 auxtrace_cache__lookup scripting_context__update perf_env__purge_cgroups inat_group_table_17 perf_pmu__getcpuid die_find_func_rettype memcpy_orig parse_events_error__contains bpf_program__section_name bpf_program__attach_cgroup cpu__max_cpu kallsyms__get_function_start perf_guest die_get_data_member_location bpf_program__set_ifindex jit_add_debug_info perf_header__has_feat inat_escape_table_1 suite__openat_syscall_event_on_all_cpus dso__free_a2l perf_mem__snp_scnprintf arch_is_branch libbpf_register_prog_handler thread__find_map strreplace_chars bpf_program__attach_sockmap tep_set_flag bench_sched_seccomp_notify tests__hists_output pmu_metrics__test_soc_cpu test_dwarf_unwind__krava_3 bench_mem_memset machine__find_thread __isoc23_vfscanf@GLIBC_2.38 thread__fprintf bpf_map__set_autocreate parse_events_option_new_evlist auxtrace_buffer__put_data strcasestr@GLIBC_2.2.5 suite__pmu pmu_metrics__elkhartlake perf_session__data_offset nsinfo__need_setns pstack__peek inat_get_last_prefix_id perf_event__fprintf_time_conv MEMCPY dwarf_highpc@ELFUTILS_0.122 auxtrace_cache__add perf_pmu__name_from_config metricgroup__print test__bp_modify bpf_map_lookup_elem_flags rm_rf libbpf_bpf_link_type_str suite__perf_evsel__roundtrip_name_test perf_error__unregister strlist__new SLtt_Screen_Rows@SLANG2 sqrt@GLIBC_2.2.5 build_id_cache__kallsyms_path machine__is_lock_function ids__free ui_browser__warning sort_local_ins_lat libbpf_bpf_map_type_str tests__expr elf_getshdrnum@ELFUTILS_1.5 ui__dialog_yesno gettimeofday@GLIBC_2.2.5 fflush@GLIBC_2.2.5 bpf_program__attach build_id_cache__list_build_ids auxtrace_synth_guest_error PyLong_FromUnsignedLongLong sort_sym_size perf_time__percent_parse_str bench_futex_requeue epoll_create1@GLIBC_2.9 test__x86_sample_parsing perf_buffer__buffer perf_evsel__enable_thread evlist__parse_sample mkdtemp@GLIBC_2.2.5 PyRun_SimpleFileExFlags x86__is_amd_cpu numa_num_possible_cpus@libnuma_1.3 perf_mem_events_intel_aux tracefs__mountpoint __perf_reg_sp_x86 intel_pt_find_overlap __ui_browser__vline bpf_map__map_extra sysfs__read_ull thread_map__remove bpf_object__unpin evsel__is_hybrid probe_type_is_available srcline__tree_delete bpf_map__lookup_and_delete_elem perf_env perf_event__process_attr ui_helpline__last_msg suite__pmu_events exit_probe_symbol_maps suite__task_exit _Ux86_64_get_reg suite__hists_filter bpf_program__attach_lsm bpf_prog_get_fd_by_id_opts pthread_exit@GLIBC_2.2.5 sort_global_p_stage_cyc tests__hists_filter perf_thread_map__comm perf_pmu__fake sh_triplets bpf_program__attach_iter btf_dump__dump_type_data workload__datasym sort_dso_from bench_evlist_open_close __perf_reg_sp_powerpc PyInit_perf __symbol__fprintf_symname metricgroup__has_metric btf__add_field sort_cpu strbuf_slopbuf __xpg_basename@GLIBC_2.2.5 perf_pmu__scan_string ui_browser__set_percent_color perf_arch_reg_ip bpf_map__is_internal machine__get_kallsyms_filename log10@GLIBC_2.2.5 maps__find_by_name perf_event__fprintf_comm pthread_rwlock_rdlock@GLIBC_2.34 tracefs__mount evlist__id_hdr_size __memcpy_chk@GLIBC_2.3.4 gelf_getclass@ELFUTILS_1.0 parse_events__modifier_event __perf_reg_ip_s390 die_get_type perf_hpp__setup_hists_formats perf_event__process_aux_output_hw_id debugfs__mount list_commands is_directory dso__new machine__resolve __hist_entry__snprintf SLang_init_tty@SLANG2 bpf_program__set_log_buf parse_events_set_column ZSTD_createCStream callchain_list_counts__printf_value __perf_hook_desc_test debug_peo_args ordered_events__flush_time pthread_cond_wait@GLIBC_2.3.2 dso__synthesize_plt_symbols strchr@GLIBC_2.2.5 bpf_map__ifindex cpu_map__fprintf fdarray__dup_entry_from find_sys_events_table inat_avx_table_5_2 ui_browser__printf dwarf_formblock@ELFUTILS_0.122 exit_event_decode_key stackop_type EVP_MD_CTX_free@OPENSSL_3.0.0 strfilter__and mutex_unlock inat_group_table_7 fread@GLIBC_2.2.5 ui_browser__vprintf tcsetattr@GLIBC_2.2.5 print_events perf_stat__set_no_csv_summary bpf_map__max_entries tests__bp_signal_overflow strim evsel__match_bpf_counter_events evsel__detect_missing_features cmdname_compare machines__set_id_hdr_size add_cmdname gelf_getverdef@ELFUTILS_1.0 parse_events_wrap funlockfile@GLIBC_2.2.5 bpf_map__set_value_size map__fprintf_dsoname parse_events_lex_init_extra SLsmg_draw_hline@SLANG2 sort_global_weight btf__resolve_type down_write dso__new_map callchain_cnode_matched perf_pmus__default_pmu_name die_find_variable_by_addr perf_event__fprintf_stat_config pthread__block_sigwinch run_command rb_last sort_mem_dcacheline user_ring_buffer__discard probe_cache__filter_purge btf__dedup parse_ftrace_printk perf_hpp__set_user_width memdup filename__read_ull probe_file__del_strlist evlist__add_newtp machines__process_guests ins__is_lock perf_pmu__event_source_devices_scnprintf set_term_quiet_input dwarf_decl_line@ELFUTILS_0.143 bpf_object__pin_maps db_export__comm_thread res_sample_init tests__mem2node fdopendir@GLIBC_2.4 bpf_linker__free fdarray__fprintf sort_sym_from cpu__get_max_freq suite__event_update tests__mmap_thread_lookup perf_config__refresh sharded_mutex__delete rb_hierarchy_prev parent_regex callchain_node__make_parent_list tep_set_file_bigendian evlist__valid_sample_id_all ui_browser__argv_seek tracing_data_get ocaml_demangle_sym elf_ndxscn@ELFUTILS_1.0 tests__thread_map_remove global_var_type__tree_delete strspn@GLIBC_2.2.5 machine__resolve_kernel_addr pmu_metrics__haswell _PyObject_New bpf_link_get_info_by_fd bpf_map__key_size gelf_update_phdr@ELFUTILS_1.0 parse_events_get_in perf_event__synth_time_conv annotated_source__purge svg_partial_wakeline machine__map_x86_64_entry_trampolines tp_event_has_id ui_helpline__printf map__find_symbol closedir@GLIBC_2.2.5 dup2@GLIBC_2.2.5 stdout@GLIBC_2.2.5 machine__process_mmap_event btf__set_endianness symbol__fprintf evlist__mmap_ex call_path_root__new suite__session_topology thread_stack__br_sample_late canary_type test_dwarf_unwind__krava_2 bpf_link_update machines__exit tep_load_plugins trace_event__tp_format_id tests__session_topology machine__findnew_vdso perf_pmu__create_placeholder_core_pmu tep_set_local_bigendian dso__next_symbol_by_name evlist__new_default strpbrk@GLIBC_2.2.5 evlist__close_control PyCapsule_GetPointer workload__thloop bpf_object__destroy_skeleton suite__parse_no_sample_id_all suite__symbols __perf_reg_sp_s390 sort_parent ids__union parse_perf_probe_command perf_session__process_events PyArg_ParseTupleAndKeywords tests__synthesize_stat_config get_leaf_frame_caller_aarch64 perf_pmu__convert_scale madvise@GLIBC_2.2.5 perf_session__write_header dso__cmp_id expr_get_text perf_hooks__invoke tests__task_exit bpf_xdp_detach reallocarray@GLIBC_2.26 btf__pointer_size pmu_metrics__ivybridge perf_home_perfconfig inat_escape_table_1_3 tcgetattr@GLIBC_2.2.5 maps__set_addr_space perf_hpp__is_thread_entry disasm_line__new apply_perf_probe_events fdarray__new sysctl__nmi_watchdog_enabled mips_triplets perf_mem_events_amd pmu_events__meteorlake inat_escape_table_3_1 arch_tests libbpf_get_error tests__unit_number__scnprint db_export__dso parse_event_file filename__read_debuglink pmu_metrics__rocketlake expr_lex_destroy symbol__match_symbol_name fetch_current_timestamp maps__copy_from cleanup_perf_probe_events opendir@GLIBC_2.2.5 readdir64@GLIBC_2.2.5 parse_events_error syscalltbl__id perf_pmu_restart suite__dso_data perf_data_file__write comm__new annotation__toggle_full_addr die_get_cfa sample__resolve_bstack perf_event__process_auxtrace setns@GLIBC_2.14 bpf_object__name lock_stat_findnew _Ux86_64_destroy_addr_space inat_group_table_11_2 btf__add_ptr arch_perf_synthesize_sample_weight perf_event__fprintf_switch perf_data__open_dir perf_header__fprintf_info realpath@GLIBC_2.3 perf_env__arch evsel__sw_names _Py_NoneStruct bench_breakpoint_thread suite__thread_map_remove perf_pmus__find_core_pmu nsinfo__is_in_root_namespace inlines__tree_insert btf__base_btf inat_group_table_21_3 perf_hooks__set_hook bench_syscall_getpgid machine__process_cgroup_event rb_prev ZSTD_isError machine__process_lost_samples_event has_kcore_dir perf_thread_map__nr aggr_cpu_id__core nsinfo__nstgid epoll_wait@GLIBC_2.3.2 set_argv_exec_path evlist__set_tp_filter_pid setup_perl_scripting btf__parse_elf ring__map_fd __evlist__combined_sample_type machine__process_event bpf_task_fd_query munmap@GLIBC_2.2.5 perf_session__fprintf_nr_events sort_thread filename__decompress pmu_events__grandridge parse_events__switch_to_buffer perf_event__fprintf_itrace_start syscalltbl_native_max_id perf_evlist__close dwfl_end@ELFUTILS_0.122 bpf_object__pin_programs strpbrk_esc perf_hpp__defined_dynamic_entry tracing_data_put fgetc@GLIBC_2.2.5 evsel__set_config_if_unset machine__process_namespaces_event memcpy_functions cpu__max_present_cpu stderr@GLIBC_2.2.5 suite__bitmap_print SLkp_getkey@SLANG2 perf_evlist__munmap suite__pe_file_parsing __map__kmap dwarf_getlocation_addr@ELFUTILS_0.122 parse_events_parse inat_group_table_8 aggr_cpu_id__equal tests__parse_no_sample_id_all ZSTD_getErrorName fnmatch@GLIBC_2.2.5 kvm_entry_trace dsos__init bpf_link__destroy debug_ordered_events libbpf_probe_bpf_prog_type maps__machine inflate sysctl__read_int set_option_nobuild dsos__find_kernel_dso hists__set_col_len maps__new dso__type hists__filter_by_symbol fchmod@GLIBC_2.2.5 btf__type_cnt qsort_r@GLIBC_2.8 sigfillset@GLIBC_2.2.5 libbpf_major_version PyCallable_Check bpf_program__attach_ksyscall branch_type_name ftruncate64@GLIBC_2.2.5 suite__util strtailcmp evlist__init_trace_event_sample_raw btf__load_from_kernel_by_id_split evsel__hw_cache_op res_sample_browse parse_tag_value __perf_reg_ip_arm64 arch_evsel__hw_name rblist__add_node _find_first_zero_bit debuginfo__find_available_vars_at hist_iter_mem iostat_print_metric perf_env__cpuid pmu_events__broadwell PyErr_Clear perf_pmu__has_format procfs__configured perf_mmap__read_event bpf_map__pin bpf_btf_get_info_by_fd perf_env__nr_cpus_avail rb_first_postorder free_callchain ui__popup_menu suite__backward_ring_buffer itrace_synth_opts__set_default __perf_reg_name_s390 perf_event__synthesize_stat_config wait4@GLIBC_2.2.5 evsel__output_resort_cb __ui_progress__init inat_group_table_15 evlist__set_cb cond_init sysfs__read_xll auxtrace_cache__free_entry libbpf_version_string bpf_map_delete_elem procfs__read_str perf_event__read_stat_config list_available_dlfilters get_tls_callchain_cursor filename__read_build_id call_return_processor__new btf__add_type_tag setrlimit64@GLIBC_2.2.5 fgets@GLIBC_2.2.5 bpf_link__pin evlist__exclude_kernel die_get_typename ui_helpline__fpush PyCapsule_New set_mempolicy@libnuma_1.1 test_dwarf_unwind__krava_1 dwfl_module_getelf@ELFUTILS_0.122 numa_max_node@libnuma_1.1 pager_get_columns zstd_init parse_events_get_column strbuf_addch nsinfo__tgid setup_intlist __evsel__set_sample_bit perf_evlist__add read_all_cgroups arm_triplets perf_config_set__collect perf_pmu_get_leng evlist__copy_prev_raw_counts unshare@GLIBC_2.4 auxtrace_parse_filters btf__new die_get_real_type evlist__id2evsel_strict tests__hists_link bpf_prog_bind_map intlist__findnew annotation_line__next pmu_for_each_core_event perf_data__create_dir symbol__init is_kernel_module perf_pmu__create_buffer user_ring_buffer__submit perf_env__pmu_mappings perf_pmus__print_raw_pmu_events extract_argv0_path tep_find_field event_symbols_sw up_write strlazymatch suite__event_groups svg_box libbpf_bpf_attach_type_str perf_pmu__pathname_fd evlist__enable_non_dummy pmu_events__sierraforest auxtrace_buffer__free gelf_getrel@ELFUTILS_1.0 perf_cpu_map__new_online_cpus rust_is_mangled btf__add_volatile rb_hierarchy_last evlist__force_leader perf_quiet_option die_walk_instances evlist__initialize_ctlfd evsel__intval_common pmu_events__snowridgex perf_event__fprintf_event_update free_config_terms thread__main_thread print_hists_out data1 svg_text nftw64@GLIBC_2.3.3 perf_stat__set_big_num pmu_for_each_sys_metric pmu_events__graniterapids PyDict_New evlist__warn_user_requested_cpus pmu_add_cpu_aliases_table branch_spec_desc perf_data__guest_kallsyms_name tests__maps__merge_in machine__process_ksymbol mlockall@GLIBC_2.2.5 pmu_events_table__num_events tests__synthesize_stat pmu_events__amdzen2 srcline__unknown symbol__tty_annotate run_command_v_opt perf_event__attr_swap evsel__zero_per_pkg lstat64@GLIBC_2.33 sort_transaction lzma_stream_decoder@XZ_5.0 PyInit_perf_trace_context convert_perf_probe_events color_vfprintf evsel__new_idx nsinfo__clear_need_setns suite__dwarf_unwind init_probe_symbol_maps intel_pt_process_auxtrace_info parse_events_pop_buffer_state map__has_symbols perf_can_record_text_poke_events ordered_events__reinit ui__help_window feat_ops intel_pt_get_insn __perf_reg_sp_arm perf_env__set_cmdline pmu_metrics__skylakex error_buf db_export__branch_types dso__data_read_addr svg_running perf_event__fprintf_auxtrace_error fdarray__init perf_pmu_free bpf_xdp_query nr_cgroups thread__set_priv_destructor inat_group_table_24_2 pmu_events__sapphirerapids auxtrace_synth_error thread_params map__load bpf_map__set_type parse_events_terms__exit hist_iter_normal tsc_to_perf_time pmu_metrics__alderlaken bpf_program__attach_uprobe __perf_reg_sp_arm64 hists__reset_column_width show_perf_probe_event c2c_decode_stats build_id_cache__list_all perf_default_config inat_group_table_9 evlist__expand_cgroup perf_pmu__file_exists dwarf_getpubnames@ELFUTILS_0.122 machines__add dwfl_module_build_id@ELFUTILS_0.138 machines__fprintf_dsos_buildid auxtrace_record__options inat_group_table_21 hists__sort_list_width dso__data_close perf_env__nr_pmu_mappings suite__synthesize_stat_round die_get_typename_from_type perf_event__synthesize_extra_kmaps rblist__exit filename__read_xll default_sort_order evlist__id2evsel evsel__free_counts pmu_events__goldmontplus perf_session__dsos_hit_all probe_cache__show_all_caches __perf_reg_ip_x86 intlist__new callchain_param_setup expr_set_out getpgid@GLIBC_2.2.5 probe_cache__find pmu_events__elkhartlake bench_repeat die_is_optimized_target evsel__fprintf perf_event__synthesize_cgroups ins__find suite__fdarray__add perf_event__process_fork bpf_program__attach_xdp hybrid_topology__delete probe_file__del_events bpf_xdp_query_id machine__create_extra_kernel_map __cgroup__find bench_uprobe_empty_ret color_fwrite_lines strcat@GLIBC_2.2.5 expr_alloc expr_parse SLsmg_write_nstring@SLANG2 perf_env__init perf_evsel__threads thread_map__new percent_color_len_snprintf db_export__comm vsnprintf@GLIBC_2.2.5 elf_getscn@ELFUTILS_1.0 perf_pmu_lex_destroy openat64@GLIBC_2.4 bpf_link__update_program Py_Finalize dwarf_haspc@ELFUTILS_0.122 perf_cpu_map__is_empty bpf_object__btf skip_spaces evsel__hw_names thread_map__read_comms sched_setaffinity@GLIBC_2.3.4 field_order htons@GLIBC_2.2.5 PyModule_AddObject btf__add_var _find_first_and_bit setup_browser kvm_entry_event btf_dump__new fstat64@GLIBC_2.33 tests__parse_metric evlist__splice_list_tail arch__fix_tev_from_maps ring__size pthread_attr_destroy@GLIBC_2.2.5 bpf_obj_pin_opts evsel__append_tp_filter hists__fprintf_headers perf_event__synthesize_sample perf_pmu__delete_buffer machine__destroy_kernel_maps bpf_map__get_pin_path cgrp_event_expanded machines__init perf_reg_name dwarf_cu_die@ELFUTILS_0.160 itrace_do_parse_synth_opts perf_event__synthesize_cpu_map suite__perf_hooks exit_event_end insn_get_modrm __perf_session__cache_build_ids libperf_init strlist__entry die_get_member_type event_enable_timer__process expr_free sort_addr_to arch__post_evsel_config strbuf_addf maps__refcnt dwarf_getcfi_elf@ELFUTILS_0.142 btf__find_by_name suite__wp ins__is_ret machine__init suite__event_times perf_pmus__supports_extended_type tep_register_print_string path__join ui__exit auxtrace_record__reference evsel__metric_id pthread_cond_signal@GLIBC_2.3.2 dwarf_aggregate_size@ELFUTILS_0.161 cap_get_proc perf_read_values_init user_ring_buffer__reserve_blocking sort_cgroup_id symsrc__init cacheline_size strlist__delete perf_pmu_lex_init ui_browser__handle_resize bpf_link_get_next_id addr_map_symbol__account_cycles suite__synthesize_stat perf_pmu__caps_parse asprintf@GLIBC_2.2.5 tep_set_function_resolver arm_spe_decode show_probe_trace_events have_ignore_callees parse_events_get_extra SLang_reset_tty@SLANG2 parse_options Py_Initialize pmu_add_sys_aliases machine__delete_threads bpf_map__fd perf_pmu__scan_buffer parse_options_usage arch_evsel__must_be_in_group machine__load_kallsyms elf__needs_adjust_symbols s390_triplets bpf_map_lookup_batch expr_set_lval bpf_map_update_batch nsinfo__realpath bpf_prog_get_next_id setup_fake_machine auxtrace_heap__free comm__str evlist__reset_weak_group bpf_obj_get_info_by_fd getpwuid_r@GLIBC_2.2.5 tui__header_window btf__add_array expr_lex suite__bp_modify write_padded __thread__set_comm inat_group_table_21_1 qsort@GLIBC_2.2.5 exit_event_begin setup_list bpf_linker__finalize db_export__thread block_range__coverage perf_hpp__setup_output_field bpf_program__attach_kprobe_opts evlist__amd_sample_raw addr_location__init mmap64@GLIBC_2.2.5 symbol__annotation_init thread__put auxtrace_parse_sample_options parse_events_push_buffer_state tracepoint_id_to_name get_events_file tep_find_any_field SLsmg_write_char@SLANG2 bpf_program__flags evsel__read_counter bpf_tc_hook_create arm64_triplets aggr_cpu_id__is_empty metricgroup__rblist_exit hists__unlink symbol__calc_percent auxtrace_record__info_fill elf_getshdrstrndx@ELFUTILS_1.5 open_memstream@GLIBC_2.2.5 ui_browser__list_head_refresh abort@GLIBC_2.2.5 btf__add_float inat_avx_tables __symbols__insert tep_get_header_page_size dso__get dwarf_formstring@ELFUTILS_0.122 _ctype vmlinux_path__nr_entries perf_pmu__arch_init die_find_inlinefunc _Ux86_64_create_addr_space tests__jit_write_elf parse_filter_percentage pmu_metrics__haswellx gzopen64@ZLIB_1.2.3.3 dwarf_bytesize@ELFUTILS_0.143 perf_pmu_get_debug arch__is put_events_file map__find_symbol_by_name thread__comm_len _Ux86_64_set_caching_policy convert_unit bench_sched_pipe __sw_hweight8 probe_cache__new annotation__unlock tep_event_fields libbpf_bpf_prog_type_str cgroup_is_v2 __bitmap_intersects ins__is_jump machine__get_kernel_start db_export__call_path bpf_map__set_inner_map_fd __sw_hweight16 parse_events__scan_string hist_browser__new suite__fdarray__filter sort_code_page_size aggr_cpu_id__cluster __sched_cpualloc@GLIBC_2.7 config_exclusive_filename create_perf_stat_counter get_argv_exec_path inat_group_table_10_3 bench__end get_cpuid_0 intel_pt_recording_init getenv@GLIBC_2.2.5 symsrc__destroy hist_browser__init_hpp is_valid_tracepoint elf64_getshdr@ELFUTILS_1.0 perf_stat__print_shadow_stats_metricgroup perf_data__kallsyms_name bpf_object__open_mem strcspn@GLIBC_2.2.5 dso__data_write_cache_addr hists__filter_by_thread evswitch__init syscalltbl__name perf_data__read ferror@GLIBC_2.2.5 gelf_getehdr@ELFUTILS_1.0 strfilter__compare perf_pmu__supports_legacy_cache scripting_max_stack pmu_events__ivybridge __rb_insert_augmented inat_group_table_13 Py_BuildValue intel_bts_recording_init pmu_events__haswellx suite__parse_metric bpf_map__delete_elem perf_top__header_snprintf PyType_GenericNew debug_set_file auxtrace_queues__sample_queue perf_event__synthesize_build_id perf_mmap__push evsel__bitfield_swap_branch_flags evsel__is_function_event dlfilter__cleanup sample__resolve_callchain up_read ring__consume sort_mem_daddr_dso __strcat_chk@GLIBC_2.3.4 parse_events_add_breakpoint evsel__has_leader _find_first_bit setlocale@GLIBC_2.2.5 auxtrace_record__snapshot_start db_export__call_return dwarf_cfi_addrframe@ELFUTILS_0.142 dwarf_getelf@ELFUTILS_0.126 bench_epoll_ctl bench_futex_lock_pi perf_config_int pthread_barrier_wait@GLIBC_2.34 tests__time_utils expr__resolve_id perf_pmu__mem_events_parse strerror@GLIBC_2.2.5 __dso__load_kallsyms debug_data_convert bpf_program__set_autoload PyType_Ready put_tracing_file machines__findnew perf_pmu__lookup suite__kmod_path__parse zfree_srcline maps__for_each_map perf_cpu_map__has_any_cpu tep_get_first_event sort_addr pread64@GLIBC_2.2.5 __rb_hierarchy_next perf_evsel__attr dwarf_offdie@ELFUTILS_0.122 nsinfo__new mem_info__get clearerr@GLIBC_2.2.5 pmu_events__skylakex pmu_metrics__sandybridge parse_events__set_default_name sort_mem_snoop _Ux86_64_dwarf_search_unwind_table perf_event__fprintf_mmap get_branch_type pmu_metrics__sapphirerapids btf_ext__free perf_event__synthesize_features die_is_func_def parse_events_add_cache bpf_map__update_elem hist_entry_iter__add dso__load_vmlinux_path ui_browser__show tep_read_number_field expr_restart parse_saved_cmdline parse_events_get_debug find_data_type thread__init_maps ui_helpline__init suite__dlfilter copyfile_offset hist_entry__transaction_len perf_pmu__have_event bpf_tc_attach symbol__strerror_disassemble cpu_topology__smt_on strreplace block_range__find perf_evlist__set_maps name_to_handle_at@GLIBC_2.14 perf_sample__sprintf_flags auxtrace_queues__process_index dwarf_lineprologueend@ELFUTILS_0.122 writev@GLIBC_2.2.5 MEMSET arch__compare_symbol_names_n ZSTD_flushStream zstd_decompress_stream thread_map__new_str perf_pmu__config __hists__init perf_buffer__buffer_cnt bpf_link_detach hists__output_resort_cb machine__findnew_dso_id bt_convert__perf2json bpf_prog_detach2 perf_usage_string callchain_param_default perf_pmu__match sigemptyset@GLIBC_2.2.5 pthread_attr_setdetachstate@GLIBC_2.2.5 sigaction@GLIBC_2.2.5 memrchr@GLIBC_2.2.5 is_perf_data perf_cpu_map__max bpf_object__open_subskeleton eprintf_time pmu_events__amdzen4 intel_pt_upd_pkt_ctx symbol__validate_sym_arguments tep_list_events thread__find_symbol strdup_esc arm_spe_pkt_name btf__set_fd dwarf_getcfi@ELFUTILS_0.142 expr__flush_buffer backtrace_symbols_fd@GLIBC_2.2.5 perf_event__synthesize_namespaces pmu_events__nehalemep gelf_newehdr@ELFUTILS_1.0 mkdirat@GLIBC_2.4 online_topology create_script_test_suites cmd_test cleanup_sdt_note_list perf_mem_record suite__attr suite__is_printable_array is_executable_file x86_triplets perf_session__auxtrace_error_inc btf__find_str perf_set_multithreaded evlist__find_evsel_by_str bpf_object__detach_skeleton arm_spe_get_packet dso__demangle_sym strtoull@GLIBC_2.2.5 perf_event__fprintf_bpf dwarf_getscopes_die@ELFUTILS_0.122 __isoc23_vsscanf@GLIBC_2.38 bpf_prog_query_opts event_symbols_hw perf_time__parse_str bpf_object__next_map thread_list__delete machines__find __strcpy_chk@GLIBC_2.3.4 annotation_options__init PyObject_IsTrue __rb_erase_color percent_color_snprintf die_match_name pmu_events__haswell evlist__add_aux_dummy sort_dso strcasecmp@GLIBC_2.2.5 tests__thread_maps_share annotated_source__get_line machine__create_kernel_maps pstack__delete expr__has_event get_dwarf_regstr cond_signal perf_evsel__read PyDict_GetItemString asprintf__tp_filter_pids expr__switch_to_buffer perf_event__synthesize_mmap_events sort_sym_ipc parse_events_add_tool synthesize_perf_probe_arg pmu_events__rocketlake perf_evsel__disable svg_time_grid ui_browser__init perf_env__lookup_objdump perf_time__ranges_skip_sample iostat_mode debug_set_display_time get_cpuid libbpf_prog_type_by_name annotation__exit inat_group_table_16_1 inat_group_table_27 events_stats__fprintf perf_pmus__scan elf_newscn@ELFUTILS_1.0 dwarf_getfuncs@ELFUTILS_0.122 __hpp__slsmg_color_printf hist_entry__sym_snprintf perf_header__clear_feat dwarf_filesrc@ELFUTILS_0.122 perf_top__reset_sample_counters default_top_sort_order strbuf_read perf_read_values_destroy perf_pmu__num_events ring__consumer_pos tests__demangle_ocaml bpf_btf_get_fd_by_id filename__has_section perf_hpp__reset_output_field dwfl_module_relocations@ELFUTILS_0.122 sort_mem_tlb pmu_events__icelakex perf_set_singlethreaded __open64_2@GLIBC_2.7 test_generic_metric arch_evlist__add_default_attrs arch__fix_module_text_start expr_id_data__value inat_escape_table_2_2 perf_pmus__find_by_type expr__delete_buffer pmu_events__sandybridge bpf_program__unpin perf_event__fprintf_cgroup bpf_program__log_buf pstack__remove perf_more_info_string elf_strptr@ELFUTILS_1.0 clockid_name ui_browser__hide btf__add_func_proto pmu_uncore_identifier_match popen@GLIBC_2.2.5 dso__fprintf_symbols_by_name tests__amd_ibs_via_core_pmu suite__demangle_ocaml perf_buffer__consume_buffer ui_browser__set_color pmu_metrics__grandridge evlist__fprintf_nr_events evlist__findnew_tracking_event intel_pt_insn_type bpf_prog_detach_opts arch__sym_update read_cgroup_id strcmp@GLIBC_2.2.5 elf_rawdata@ELFUTILS_1.0 maps__addr_space thread__resolve inat_group_table_18 pthread_condattr_destroy@GLIBC_2.2.5 test_dwarf_unwind__compare strtoul@GLIBC_2.2.5 perf_hooks__get_hook btf__parse_split btf__parse_raw pthread_condattr_init@GLIBC_2.2.5 ring_buffer__ring suite__expand_cgroup_events nsinfo__pid init_rwsem bpf_map__numa_node perf_session__fprintf trace_seq_destroy inat_avx_table_4_1 cap_get_flag dso__load_vmlinux get_current_dir_name@GLIBC_2.2.5 bpf_object__close EVP_md5@OPENSSL_3.0.0 map__fixup_start perf_session__peek_event auxtrace_queue_data perf_pmu__for_each_format inlines__tree_delete ring_buffer__add ring_buffer__epoll_fd probe_file__get_rawlist block_info__delete evsel__set_sample_id build_id_cache__cached evsel__alloc_counts perf_pmu_set_debug pipe@GLIBC_2.2.5 tests__backward_ring_buffer metricgroup__copy_metric_events get_target_map perf_mmap__consume disable_buildid_cache evlist__add_sb_event expr_set_lineno dso__find_symbol_by_name _Ux86_64_step inat_group_table_25_1 event_format__fprintf btf__find_by_name_kind bpf_object__open symbol__annotate2 PyBool_FromLong evsel__set_filter bpf_map_lookup_and_delete_elem_flags btf__new_split fputc@GLIBC_2.2.5 calloc@GLIBC_2.2.5 suite__PERF_RECORD event_enable_timer__start eval_flag dso__set_sorted_by_name perf_version_string get_page_size_name dlopen@GLIBC_2.34 threads__for_each_thread ui__lock __asprintf_chk@GLIBC_2.8 dwarf_ranges@ELFUTILS_0.122 libbpf_probe_bpf_helper sysfs__configured machine__process_comm_event PyLong_AsLong thread__delete expr__find_ids perf_event__synthesize_attr sort_socket arch_sdt_arg_parse_op sigchain_pop tests__is_printable_array __pr_warn perf_event__synthesize_event_update_scale perf_pmu_set_lineno gelf_getnote@ELFUTILS_1.3 perf_mem__tlb_scnprintf arch_syscalls__strerrno_function intlist__delete tests__thread_map kallsyms__get_symbol_start __sysconf@GLIBC_2.2.5 tests__code_reading evsel_streams__match machine__findnew_thread pmu_metrics__amdzen2 set_buildid_dir suite__synthesize_stat_config force_pager __getdelim@GLIBC_2.2.5 hist_entry__get_data_type bpf_program__set_autoattach auxtrace_queues__init addr_filters__init bpf_prog_query callchain_cursor_reset auxtrace_queues__free evsel__open_per_cpu auxtrace_record__info_priv_size parse_events_multi_pmu_add __perf_env__insert_btf bpf_map__set_initial_value svg_ubox evsel__find_pmu btf__add_const perf_env__find_bpf_prog_info pthread_rwlock_unlock@GLIBC_2.34 perf_pmu_format__set_value probe_cache__purge perf_env__numa_node hugetlbfs__mount thread__free_stitch_list kill@GLIBC_2.2.5 fscanf@GLIBC_2.2.5 bpf_fs__mountpoint perf_probe_with_var evsel__intval dso__filename_with_chroot bpf_object__pin tracing_path_mount raise@GLIBC_2.2.5 __cxa_atexit@GLIBC_2.2.5 target__parse_uid bpf_link__unpin perf_pmu__cpu_slots_per_cycle fopencookie@GLIBC_2.2.5 perf_event_open_cloexec_flag parse_cgroups perf_hpp__append_sort_keys cgroup__put trace_event__tp_format pthread_cond_broadcast@GLIBC_2.3.2 set_option_flag parse_events_get_out evsel__compute_deltas __perf_reg_name_csky pthread_key_create@GLIBC_2.34 dso__next_symbol _PyTuple_Resize branch_type_count rblist__entry perf_can_record_build_id pmu_events__westmereex bpf_map__pin_path tests__expand_cgroup_events execl_cmd python_scripting_ops parse_events__modifier_group auxtrace_index__auxtrace_event ring__producer_pos expr__subset_of_ids bench_mem_memcpy inat_group_table_26_1 perf_hist_config getsid@GLIBC_2.2.5 aggr_cpu_id__cpu block_info__total_cycles_percent perf_pmu_lex intlist__entry symbol__annotate_zero_histograms parse_events_free fill_callchain_info dso__delete_symbol perf_pmu__warn_invalid_formats map__objdump_2rip gzclose strftime@GLIBC_2.2.5 dwfl_module_getdwarf@ELFUTILS_0.122 round@GLIBC_2.2.5 perf_pmu_alloc PyErr_SetFromErrno cmd_inject __evlist__parse_mmap_pages ru_stats perf_pmu__check_alias svg_cpu_box namespaces__free symbol__disassemble perf_env__raw_arch report__browse_block_hists pthread_barrier_destroy@GLIBC_2.34 __block_info__cmp prctl@GLIBC_2.2.5 auxtrace_cache__remove numa_topology__new __evsel__read_on_cpu perf_pmu__pathname_scnprintf get_dwarf_regnum EVP_DigestInit_ex@OPENSSL_3.0.0 java_demangle_sym evlist__set_id_pos script_fetch_insn inat_group_table_11 expr__del_id sharded_mutex__new expr__add_id_val timerfd_settime@GLIBC_2.8 unknown_type bpf_link__pin_path ZSTD_createDStream bpf_program__attach_tracepoint svg_cstate perf_cpu_map__is_any_cpu_or_is_empty local_unwind_libunwind_ops check_if_command_finished suite__keep_tracking tests__hists_cumulate perf_can_record_cgroup kvm_events_tp maps__find_symbol malloc@GLIBC_2.2.5 iostat_parse btf__add_enum_value parse_events__decode_legacy_cache sort__iaddr_cmp perf_env__exit evlist__uniquify_name expr__get_id ins__is_fused probe_cache__find_by_name dso__is_object_file inat_avx_table_4_2 __sw_hweight64 auxtrace_mmap__read_snapshot btf__add_enum64 symbol__config_symfs mem_bswap_32 pmu_metrics__cascadelakex pmu__name_match file_available tests__switch_tracking hists__add_entry ui__refresh_dimensions perf_pmu__mem_events_num_mem_pmus evlist__add_sched_switch suite__amd_ibs_via_core_pmu multiprobe_event_is_supported perf_event__fprintf_aux perf_event__synthesize_comm pmu_events__lunarlake thread_map__new_event perf_record_cpu_map_data__test_bit expr_get_debug iostat_release __map__is_bpf_prog elf_errmsg@ELFUTILS_1.0 perf_header__set_feat isatty@GLIBC_2.2.5 perf_pmu_set_lval evlist__free_stats arch_fetch_insn rdtsc cmd_bench mem2node__init test__intel_pt_pkt_decoder PyTuple_SetItem bpf_program__insn_cnt test_attr__enabled event_format__print evlist__s390_sample_raw perf_session__dump_kmaps maps__find_ams bpf_object__open_file gzip_is_compressed hist_entry__delete callchain_cursor_append script_spec_register perf_session__read_build_ids bpf_object__attach_skeleton parse_branch_stack perf_stat_process_counter __dso__build_id_filename perf_data__switch exclude_cmds bench_breakpoint_enable gelf_update_ehdr@ELFUTILS_1.0 lzma_code@XZ_5.0 show_available_vars map__contains_symbol bpf_map__attach_struct_ops SLsmg_reset_smg@SLANG2 __isoc23_strtol@GLIBC_2.38 perf_event__process_itrace_start bpf_map__value_size cs_etm__process_auxtrace_info suite__jit_write_elf build_id_cache__add ZSTD_initDStream machine__process_exit_event SLtt_get_screen_size@SLANG2 tests__synthesize_stat_round evsel__newtp_idx sigaddset@GLIBC_2.2.5 pmu_metrics__snowridgex mkpath evlist__cancel_workload riscv32_triplets evlist__start_sb_thread tep_parse_format binary__fprintf perf_hpp_list__init __evsel__hw_cache_type_op_res_name machine__addr_cpumode trace_event__cleanup perf_event__process_mmap2 rust_demangle_sym auxtrace_queues__add_sample dso_id__empty print_tracepoint_events btf__parse_raw_split perf_error__register uprobe_ref_ctr_is_supported suite__sw_clock_freq bpf_object__find_program_by_name btf__distill_base perf_evlist__disable intel_pt_log_set_name evsel__open_per_thread pmu_metrics__amdzen1 evsel__parse_sample ZSTD_freeDStream __vfprintf_chk@GLIBC_2.3.4 perf_pmu__find_event die_get_call_lineno evsel__append_addr_filter tests__util die_find_realfunc sort_mem_locked waitpid@GLIBC_2.2.5 perf_data__open __ui_browser__show_title bpf_program__attach_netfilter lseek64@GLIBC_2.2.5 inat_avx_table_7_3 __isoc23_sscanf@GLIBC_2.38 numa_allocate_cpumask@libnuma_1.2 btf__add_btf bpf_raw_tracepoint_open perf_pmus__scan_core __perf_reg_ip_arm comm__free __perf_reg_name_riscv workload__leafloop kcore_extract__create suite__perf_evsel__tp_sched_test arm_spe_decoder_free evsel__bpf_counter_events expr__parse evlist__ctlfd_ack strglobmatch bench_uprobe_empty machine__findnew_dso build_caches_for_cpu strrchr@GLIBC_2.2.5 bind@GLIBC_2.2.5 ui_browser__input_window events_stats__inc elf_memory@ELFUTILS_1.0 machine__findnew_kernel get_arch_regstr suite__vmlinux_matches_kallsyms clock_getres@GLIBC_2.17 insn_decode bpf_object__destroy_subskeleton maps__nr_maps machine__findnew_guest_code dwarf_lineno@ELFUTILS_0.122 perf_evsel__cpus clear_probe_trace_event sample__fprintf_insn_raw bpf_obj_get bpf_program__autoattach btf__add_type cpu_topology__new expr__ctx_clear addr_filters__exit hist_entry__snprintf_alignment callchain_register_param __ui__info_window SLang_ungetkey@SLANG2 do_realloc_array_as_needed inat_get_escape_attribute evlist__new_dummy pmu_metrics__broadwellx fdarray__poll inat_group_table_25 perf_time__parse_for_ranges_reltime perf_mem_events_find_pmu machine__process_switch_event rb_next svg_fbox perf_session__read_header nsinfo__copy ui_browser__gotorc dwfl_standard_find_debuginfo@ELFUTILS_0.122 bpf_program__attach_usdt evlist__append_tp_filter_pids cgroup__findnew thread_stack__free dwarf_getsrcfiles@ELFUTILS_0.122 machines__create_guest_kernel_maps perf_session__set_id_hdr_size nsinfo__set_in_pidns branch_type_stat_display perf_event__synthesize_auxtrace_info get_filter_desc cu_find_realpath value_color_snprintf perf_pmu_pop_buffer_state suite__openat_syscall_event rm_rf_perf_data evsel__reset_counts hybrid_topology__new die_get_linkage_name __evlist__set_tracepoints_handlers mmap@GLIBC_2.2.5 tep_register_comm auxtrace_record__init evsel__parse_sample_timestamp parse_events_error__init perf_pmu_get_out bench_pmu_scan btf__parse_elf_split probe_file__add_event parse_events_get_lval rblist__remove_node symsrc__possibly_runtime perf_hpp_list__column_register tests__bp_modify perf_pmu__open_file perf_hpp__is_comm_entry evsel__remove_from_group bpf_program__attach_kprobe_multi_opts thread_stack__sample stpcpy@GLIBC_2.2.5 symbol__disassemble_bpf line_range__clear arch__find inat_avx_table_6_3 thread_map__fprintf perf_event__fprintf_cpu_map perf_session__fprintf_dsos __realpath_chk@GLIBC_2.4 debuginfo__find_trace_events inat_group_table_16 evsel__precise_ip_fallback ui_browser__write_graph sort__dcacheline_cmp bpf_tc_query strncasecmp@GLIBC_2.2.5 tests__python_use nsinfo__stat perf_regs_load bench_futex_wake expr_get_extra bpf_linker__add_file perf_pmu__scan_file_at bpf_prog_attach event_type libbpf_set_memlock_rlim evsel__common_field machine__get_current_tid affinity__cleanup bpf_map__is_pinned inat_escape_table_2 bpf_program__attach_uprobe_multi evsel__group_name perf_time__skip_sample perf_probe_event_need_dwarf callchain_merge perf_pid_map_tid hugetlbfs__configured clean_cmdnames sysfs__mountpoint attr_to_script veprintf perf_data__update_dir python_scripting_unsupported_ops inat_avx_table_4_3 annotation_line__add dwarf_bitsize@ELFUTILS_0.143 perf_stat_process_percore SLsmg_init_smg@SLANG2 ui_browser__argv_refresh aggr_cpu_id__socket rewinddir@GLIBC_2.2.5 asprintf_expr_inout_ints parse_line_range_desc tests__vmlinux_matches_kallsyms machine__process_fork_event intel_pt_pkt_desc ordered_events__delete strbuf_grow sysfs__read_bool probe_cache__scan_sdt SLsmg_gotorc@SLANG2 bpf_program__attach_netns perf_hpp__is_sort_entry evlist__parse_control sort_sym hists__delete_entries perf_env__has_pmu_mapping perf_pmu__format_type expr_push_buffer_state dlfilter__new block_hists_tui_browse perf_missing_features bpf_program__set_log_level db_export__evsel perf_buffer__free bpf_program__set_expected_attach_type auxtrace__free bpf_object__find_map_fd_by_name cpu__setup_cpunode_map ui_helpline__current sort_cgroup suite__hists_link PyArg_UnpackTuple tests__x86_sample_parsing pmu_metrics__jaketown insn_get_sib evsel__rawptr c2c_add_stats build_id__is_defined sort_sym_to perf_evlist__delete evsel__output_resort auxtrace_record__read_finish __intel_pt_log_insn die_get_decl_file parse_events_set_in perf_env__find_pmu_cap __map__is_bpf_image perf_mem_events evlist__add_bpf_sb_event fork@GLIBC_2.2.5 hists__add_entry_ops tracing_events__scandir_alphasort bpf_link_get_fd_by_id_opts clear_perf_probe_event mbind@libnuma_1.1 strsep@GLIBC_2.2.5 threads__remove bench_sched_messaging perf_evsel__enable disasm__fprintf thread__set_comm_from_proc perf_mem_events_intel record__parse_freq __perf_reg_sp_loongarch elf_update@ELFUTILS_1.0 expr_lex_init_extra perf_counts__reset cu_walk_functions_at pmu_metrics__amdzen4 perf_hpp_list__register_sort_field metricgroup__parse_groups_test perf_event__process_id_index timerfd_create@GLIBC_2.8 evswitch__discard parse_probe_trace_command filename__write_int btf__add_int copy_to_probe_trace_arg gzip_decompress_to_file perf_config_set__load_file symbol__disassemble_bpf_image pmu_events__alderlaken dso__sorted_by_name pmu_metrics__ivytown bpf_map__inner_map dirfd@GLIBC_2.2.5 bpf_link__disconnect open_trace_file getppid@GLIBC_2.2.5 lzma_is_compressed bpf_linker__new warn@GLIBC_2.2.5 perf_cpu_map__merge execvp@GLIBC_2.2.5 thread_map__has libbpf_find_kernel_btf evlist__reset_stats bench__start bpf_object__open_skeleton perf_can_record_switch_events dwarf_nextcu@ELFUTILS_0.122 perf_evlist__new is_cpu_online __perf_session__new tests__dwarf_unwind bpf_program__get_expected_attach_type tests__perf_hooks regerror@GLIBC_2.2.5 ring_buffer__consume perf_event__synthesize_stat __errno_location@GLIBC_2.2.5 perf_session__register_idle_thread perf_evlist__remove _ITM_registerTMCloneTable suite__sample_parsing perf_env__kernel_is_64_bit map__new2 inat_avx_table_4 perf_session__find_first_evtype btf_ext__raw_data __sigsetjmp@GLIBC_2.2.5 __map__is_ool tep_alloc elf_getident@ELFUTILS_1.0 __dso__inject_id __map__is_kernel aggr_cpu_id__empty cu_get_comp_dir hugetlbfs__mountpoint symbols__delete symbol__annotate_decay_histogram svg_waiting probe_cache_entry__get_event user_ring_buffer__free setup_path cpu_map__snprint arm_spe_decoder_new pthread_mutexattr_init@GLIBC_2.34 btf__add_decl_tag mutex_trylock ui_browser__mark_fused cpu_map__online perf_event__synthesize_attrs dso__kernel_module_get_build_id bpf_program__insns quiet __evsel__get_config_term __memset_chk@GLIBC_2.3.4 ctime@GLIBC_2.2.5 perf_event__fprintf_thread_map sort_in_tx gelf_getsym@ELFUTILS_1.0 perf_mem__lvl_scnprintf dso__find_symbol threads__remove_all_threads __printf_chk@GLIBC_2.3.4 debug_kmaps parse_filter metricgroups__topdown_max_level pwrite64@GLIBC_2.2.5 bpf_object__load_skeleton evlist__create_streams svg_pstate bpf_program__set_type hist_entry__annotate_data_tui evlist__add_dummy perf_event__process_auxtrace_info execve@GLIBC_2.2.5 perf_evlist__mmap perf_session__delete filename__sprintf_build_id probe_file__open addr_filters__parse_bare_filter evlist__add_attrs perf_event__fprintf_text_poke bpf_btf_get_fd_by_id_opts expr__scan_bytes dwarf_linebeginstatement@ELFUTILS_0.122 perf_cpu_map__intersect elf_newdata@ELFUTILS_1.0 perf_event__synthesize_thread_map mkdir_p format_field__intval bpf_map__btf_value_type_id SLtt_set_color@SLANG2 regexec@GLIBC_2.3.4 bpf_object__set_kversion enable_params perf_hpp__is_srcline_entry hist_entry__append_callchain ins__is_nop __perf_env__find_btf die_entrypc auxtrace_buffer__next ring__consume_n map_symbol__annotation_dump _Py_BuildValue_SizeT dirname@GLIBC_2.2.5 die_skip_prologue die_collect_vars hist_entry__tui_annotate metricgroup__lookup color_vsnprintf tui_helpline__set srcline__tree_find rlimit__increase_nofile libapi_set_print memset_orig workload__sqrtloop tep_get_long_size symsrc__has_symtab cpu_aggr_map__new PyByteArray_FromStringAndSize parse_events__shrink_config_terms fopen64@GLIBC_2.2.5 hists__new_col_len start_command perf_session__queue_event parse_callchain_top_opt block_ranges dlclose@GLIBC_2.34 perf_buffer__poll strbuf_release kvm_exit_event synthesize_probe_trace_command machines__find_guest perf_tool_event__to_str intlist__remove PyObject_GetAttrString perf_callchain_config pthread_condattr_setpshared@GLIBC_2.34 pstack__empty event_enable_timer__exit perf_mem_events__record_args dso__data_get_fd bpf_map__unpin perf_event__process_cgroup dso__name_len rblist__init build_id__sprintf hists__get_rotate_entries_in strlist__load mmap_cpu_mask__scnprintf thread_map__new_by_tid parse_events_set_extra auxtrace_heap__add call_path_root__free dlfilter__start bpf_object__unpin_maps ui__getch namespaces__new thread_stack__process arch__normalize_symbol_name callchain_cursor__copy numa_topology__delete suite__mem perf_hpp__reset_sort_width vfprintf@GLIBC_2.2.5 evlist__config inat_escape_table_3_2 nanosleep@GLIBC_2.2.5 evlist__alloc_stats __pr_debug auxtrace_mmap_params__set_idx perf_tool__fill_defaults hists__inc_nr_lost_samples btf__set_pointer_size auxtrace_cache__free bpf_xdp_attach dso__data_write_cache_offs evsel__calc_id_pos dwarf_linesrc@ELFUTILS_0.122 insn_get_opcode ui_browser__refresh parse_events__create_buffer evlist__copy_res_stats dwarf_attr_integrate@ELFUTILS_0.122 perf_header__write_pipe setup_pager symbol_conf __perf_reg_name_arm perf_debuginfod_setup ui_helpline__puts hists__output_recalc_col_len statfs64@GLIBC_2.2.5 flockfile@GLIBC_2.2.5 intel_pt_log_fp __hists__scnprintf_title perf_mem__blk_scnprintf perf_pmu_get_lineno hist_entry__cmp pmu_events__westmereep_dp evsel__is_cache_op_valid config_error_nonbool pmu_metrics__amdzen3 srcline__tree_insert annotation__lock PyList_New __perf_hook_desc_record_end perf_cpu_map__min thread__fork pmu_metrics_table__find dso__put perf_pmu__flush_buffer tests__bitmap_print intel_bts_process_auxtrace_info evlist__append_tp_filter_pid usleep@GLIBC_2.2.5 putenv@GLIBC_2.2.5 gelf_getversym@ELFUTILS_1.0 evlist__parse_event_enable_time tests__sdt_event perf_pmu_parse regs_query_register_offset sysctl__max_stack cpu__get_socket_id evlist__set_selected rb_next_postorder dwarf_lineaddr@ELFUTILS_0.122 pthread_getspecific@GLIBC_2.34 expr__ctx_new btf__add_fwd sort__daddr_cmp elf_getdata@ELFUTILS_1.0 kretprobe_offset_is_supported evlist__start_workload expr_pop_buffer_state elf64_getehdr@ELFUTILS_1.0 find_scripts perf_session__write_buildid_table perf_event__fprintf_mmap2 dwarf_formsdata@ELFUTILS_0.122 SLsmg_vprintf@SLANG2 hists__fprintf bpf_object__kversion dso__delete iostat_list print_sdt_events dwarf_callchain_users PyImport_AppendInittab is_pmu_core strlist__find intel_pt_set_first_timestamp sample__fprintf_insn_asm event_attr_init fwrite@GLIBC_2.2.5 inat_avx_table_5 test_dwarf_unwind__thread __bitmap_clear perf_evsel__close_cpu suite__perf_time_to_tsc ui_helpline__vshow btf__add_enum64_value annotation_options__exit pthread_rwlock_wrlock@GLIBC_2.34 perf_event__process bpf_map__autoattach die_find_variable_at sysfs__sprintf_build_id bpf_map_get_info_by_fd test__intel_pt_hybrid_compat tests__sw_clock_freq db_export__exec_comm perf_pmu_get_column sysctl_perf_event_max_stack intel_pt_insn_name PyImport_AddModule bpf_obj_pin perf_pmu_set_column perf_evlist__nr_groups memcmp@GLIBC_2.2.5 execv_cmd parse_events_realloc iostat_prepare Py_DecodeLocale perf_cpu_map__get PyUnicode_AsUTF8 SLtt_Screen_Cols@SLANG2 ZSTD_compressStream SLsmg_draw_vline@SLANG2 arch__user_reg_mask rb_erase SLtty_set_suspend_state@SLANG2 pmu_events__icelake __perf_reg_name_arm64 sort_local_p_stage_cyc perf_pmu_get_text perl_scripting_unsupported_ops tep_free arch_support_sort_key perf_exe pager_init dwarf_tag@ELFUTILS_0.122 perf_pmu_realloc annotated_data_type__update_samples threads__findnew evlist__create_maps perf_event__process_aux perf_event__synthesize_event_update_name arch__compare_symbol_names mem2node__exit zstd_compress_stream_to_records annotation_config__init perf_pmu_set_in PyTuple_New cpu_isa_init sort_trace bpf_program__set_flags dwarf_hasattr@ELFUTILS_0.122 evlist__get_tracking_event inat_avx_table_6_1 tep_find_event bpf_iter_create inat_group_table_14 bpf_program__attach_netkit affinity__set annotated_data_type__tree_delete die_get_var_range __bitmap_and dso__read_binary_type_filename dsos__exit perf_event__fprintf_aux_output_hw_id dlfilter__do_filter_event btf__add_datasec is_strict_order getrusage@GLIBC_2.2.5 hists__calc_col_len target__strerror parse_synth_opt sort_mem_phys_daddr perf_config_set__new arch_evlist__cmp workload__brstack die_find_child suite__maps__merge_in perf_cpu_map__new_any_cpu probe_event_dry_run pmu_metrics__broadwell perf_event__synthesize_bpf_events PyObject_Str __evsel__reset_sample_bit perf_event__process_build_id getpagesize@GLIBC_2.2.5 pthread_create@GLIBC_2.34 annotate_opts bitmap_scnprintf dwarf_formudata@ELFUTILS_0.122 PyErr_Format hist_entry__inc_addr_samples elf_getphdrnum@ELFUTILS_1.6 random@GLIBC_2.2.5 auxtrace_record__find_snapshot libbpf_attach_type_by_name get_cpuid_str find_sourceline evlist__disable_non_dummy nsinfo__get machine__for_each_kernel_map nsinfo__mountns_exit perf_buffer__buffer_fd bpf_prog_test_run_opts levenshtein putchar@GLIBC_2.2.5 parse_events_set_lineno bpf_program__attach_perf_event_opts perf_event__synthesize_kernel_mmap tests__event_times SLtt_set_cursor_visibility@SLANG2 is_perf_pid_map_name evlist__scnprintf_evsels btf__raw_data scripting_context mem_info__new evsel__leader hists__inc_stats perf_event__fprintf_ksymbol evlist__ctlfd_process perf_atoll addr2line_timeout_ms tracing_path__strerror_open_tp update_stats parse_events_term__num perf_event__process_auxtrace_error map__set_kallsyms_ref_reloc_sym __perf_reg_ip_csky bpf_map_delete_elem_flags __map__is_extra_kernel_map data2 numa_nodes_ptr@libnuma_1.2 ZSTD_decompressStream suite__bp_accounting parse_events_terms__to_strbuf perf_event__process_finished_round perf_evsel__new map__browse expr__add_id bpf_object__btf_fd cpu_cache_level__free mutex_init show_bootconfig_events perf_pmu__auto_merge_stats auxtrace_cache__new stdio__config_color perf_data__close_dir getpid@GLIBC_2.2.5 dsos__hit_all inat_escape_tables perf_evsel__disable_cpu die_walk_lines hist_entry__has_hierarchy_children pmu_events__amdzen1 __perf_hook_func_record_start dwarf_dieoffset@ELFUTILS_0.122 uniq libunwind__arch_reg_id test_objdump_path hist_iter_cumulative use_browser getline@GLIBC_2.2.5 test__hybrid perf_mem_events__loads_ldlat dwfl_begin@ELFUTILS_0.122 annotate_get_basic_blocks memmem@GLIBC_2.2.5 kcore_copy bpf_map__name evlist__find_evsel perf_pmu_get_lval perf_can_record_cpu_wide thread__memcpy sort_mem_iaddr_sym arm_spe_pkt_desc addr_map_symbol__inc_samples elf_end@ELFUTILS_1.0 machine__nr_cpus_avail parse_events_term__clone pthread_attr_setaffinity_np@GLIBC_2.32 die_is_signed_type dso__parse_addr_inlines rblist__find cpu__get_cluster_id powerpc_triplets PyExc_OSError SLkp_init@SLANG2 PyLong_FromUnsignedLong machines__set_comm_exec rb_insert_color pthread__unblock_sigwinch rename@GLIBC_2.2.5 btf__add_func ref_reloc_sym_names bpf_map__set_ifindex bpf_map__set_map_flags expr__get_literal intel_pt_enable_logging bpf_map__autocreate dso__data_status_seen libbpf_num_possible_cpus build_id__mark_dso_hit_ops perf_debug_setup evsel__object_config iostat_print_header_prefix ann_insn_stat inflateEnd suite__sdt_event perf_time__range_alloc sdt_notes__get_count finish_command hists__match perf_event_header__bswap load_command_list inat_avx_table_6 dwarf_frame_cfa@ELFUTILS_0.142 suite__api_io svg_build_topology_map perf_thread_map__new_array SLsmg_refresh@SLANG2 perf_file_header__read auxtrace_buffer__get_data_rw inat_group_table_24_1 perf_evsel__close stdin@GLIBC_2.2.5 dwarf_lineendsequence@ELFUTILS_0.122 dwarf_siblingof@ELFUTILS_0.122 pmu_for_each_sys_event bpf_token_create perf_evlist__next suite__x86_sample_parsing perf_reg_value libbpf_set_print SLang_TT_Read_FD@SLANG2 db_export__switch expr__scan_buffer perf_env__single_address_space parse_opt_verbosity_cb die_get_call_file bpf_object__prev_program test_loop auxtrace_index__write elf_begin@ELFUTILS_1.0 get_sdt_note_list annotation__trylock build_id_cache__origname btf_ext__new gelf_getrela@ELFUTILS_1.0 pmu_events__broadwellx expr_get_column fileno@GLIBC_2.2.5 perf_session__inject_header pmu_events__tigerlake default_diff_sort_order lzma_decompress_to_file perf_tool__process_synth_event shash sh_regstr_tbl user_ring_buffer__new tep_parse_header_page intel_pt_get_packet tests__sample_parsing parse_events_set_debug aggr_cpu_id__global sparc_triplets perf_pmus__print_pmu_events ui_browser__is_current_entry symbol__delete bpf_program__attach_uprobe_opts machine__process_bpf cpu_aggr_map__empty_new intel_pt_fast_forward ordered_events__first_time expr_set_debug __machine__synthesize_threads fseek@GLIBC_2.2.5 pread@GLIBC_2.2.5 aggr_cpu_id__die dso__set_nsinfo symbol__elf_init srand@GLIBC_2.2.5 fetch_kernel_version elf_section_by_name PyObject_GenericGetAttr arch_get_tsc_freq bpf_program__attach_perf_event PyExc_ImportError bpf_program__attach_trace expr_set_column thread__set_namespaces inat_avx_table_6_2 parse_events_get_leng sort__mode parse_branch_str debug_type_profile system_path perf_arch_reg_sp perf_ns__name probe_conf probe_file__open_both getpwnam_r@GLIBC_2.2.5 elf_version@ELFUTILS_1.0 perf_config__exit _Ux86_64_init_remote topdown_sys_has_perf_metrics machine__exit_vdso perf_event__process_ksymbol rel_stddev_stats __evsel__sample_size compare_proc_modules syscalltbl__strglobmatch_next __read_chk@GLIBC_2.4 svg_process chdir@GLIBC_2.2.5 branch_new_type_name help_unknown_cmd suite__switch_tracking __bitmap_weight bsearch@GLIBC_2.2.5 perf_read_values_add_value evsel__set_leader evlist__check_mem_load_aux trace_seq_init print_hists_in perf_event__process_comm scnprintf_pad btf__get_raw_data evlist__print_counters perf_hpp__cancel_cumulate parse_events__scan_bytes __sprintf_chk@GLIBC_2.3.4 die_find_variable_by_reg machines__create_kernel_maps evsel__hw_cache_result perf_header__process_sections machine__create_extra_kernel_maps EVP_DigestFinal_ex@OPENSSL_3.0.0 cxx_demangle_sym rlimit__bump_memlock thread__insert_map perf_read_tsc_conversion ring_buffer__consume_n gelf_getphdr@ELFUTILS_1.0 print_spark fopen@GLIBC_2.2.5 ring__avail_data_size expr__scan_string _find_next_and_bit perf_thread_map__set_pid __snprintf_chk@GLIBC_2.3.4 tests__perf_evsel__tp_sched_test sort_sym_offset perf_event__process_text_poke SLutf8_enable@SLANG2 insn_rip_relative riscv64_triplets affinity__setup perf_hpp__is_dso_entry inat_escape_table_1_2 bpf_program__expected_attach_type perf_hooks__recover die_deref_ptr_type build_id_cache__cachedir svg_wakeline __isoc23_strtoull@GLIBC_2.38 ui__has_annotation PyErr_Occurred die_find_top_inlinefunc perf_event__synthesize_modules bpf_link__fd eventfd@GLIBC_2.7 evlist__sample_id_all graph_dotted_line perf_session__deliver_synth_event exec_cmd_init tests__perf_evsel__roundtrip_name_test __perf_event__synthesize_id_index intel_pt_log_enable evlist__find_tracepoint_by_name btf__add_union parse_events_lex_init socketpair@GLIBC_2.2.5 inat_group_table_18_1 pmu_events__bonnell addr_location__copy PyFile_FromFd perf_data__make_kcore_dir fstatat64@GLIBC_2.33 match_callstack_filter is_in_cmdlist system@GLIBC_2.2.5 tests__event_update btf__relocate strlist__remove SLsmg_set_char_set@SLANG2 pmu_metrics__amdzen5 dso__decompress_kmodule_fd annotate_calc_pcrel map__rip_2objdump iostat_prefix test_attr__ready symbol__annotate_printf dwfl_report_offline@ELFUTILS_0.122 evsel_streams__entry inat_group_table_21_2 thread__comm bpf_map_lookup_and_delete_elem machine__set_current_tid strtod@GLIBC_2.2.5 pmu_events__silvermont db_export__sample bpf_prog_attach_opts ui_helpline__vpush __bitmap_equal bpf_program__set_attach_target bpf_program__set_insns libbpf_find_vmlinux_btf_id thread__get thread__namespaces sample__fprintf_sym sample__fprintf_callchain sysfs__read_int bpf_program__attach_tracepoint_opts machine__for_each_dso __pr_info machine__process_text_poke evlist__combined_branch_type perf_pmu__mem_events_ptr thread_stack__depth die_compare_name dump_trace parse_ftrace_file dso__insert_symbol auxtrace_index__free __intel_pt_log fmemopen@GLIBC_2.22 evlist__event2evsel perf_use_color_default machine__new_host maps__fprintf inat_avx_table_7 ui_browser__rb_tree_seek kcore_extract__delete PyBytes_FromStringAndSize get_tracing_file perf_host bpf_prog_detach btf__load_from_kernel_by_id perf_stat_merge_counters perf_data__close chk_double_cl jit_process cpu_map__snprint_mask .symtab .strtab .shstrtab .note.gnu.build-id .note.package .gnu.hash .dynsym .dynstr .gnu.version .gnu.version_r .rela.dyn .rela.plt .init .plt.got .noinstr.text .fini .rodata .eh_frame_hdr .eh_frame .init_array .fini_array .data.rel.ro .dynamic .got.plt .data .bss .comment .debug_aranges .debug_info .debug_abbrev .debug_line .debug_str .debug_line_str .debug_loclists .debug_macro .debug_rnglists 8 8 $ . \ \ < o H H a F q q a N V V o z c o p p ` r ȡ | B X = = x @> @> " @ p& p& L & L & & & 8b 8 8 4 p p 6 @ Ս ؍ X ߍ N ? / @ [ J (J 0 J % K ` # uP Y / + S = I 0 T 0 Eɕ d Yݕ pv t S % x 8 & ~ VR Nќ