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ELF > ^ @ С @ 8 @ @ @ @ N N p p p P P P 8 8 8 0 0 h h h Std 8 8 8 0 0 Ptd x x x Qtd Rtd /lib64/ld-linux-x86-64.so.2 GNU GNU B\^3R]|PO GNU t ~FDO {"type":"deb","os":"ubuntu","osVersion":"24.10","name":"pciutils","version":"1:3.13.0-1","architecture":"amd64"} 3 3 em * U " M N F = 3 y i % # ! 9 2 ? k x d " __libc_start_main __cxa_finalize __errno_location nanosleep __stack_chk_fail stdout __vfprintf_chk stderr __fprintf_chk fputc exit malloc opterr getopt_long getopt optarg strtol optind realloc __memset_chk strtok __isoc99_sscanf strlen strchr puts fflush __printf_chk putchar free gmtime strftime __snprintf_chk fopen fwrite fclose _ITM_deregisterTMCloneTable __gmon_start__ _ITM_registerTMCloneTable pci_filter_match pci_read_byte pci_find_cap pci_read_long pci_filter_parse_slot pci_alloc pci_filter_init pci_cleanup pci_scan_bus pci_read_word pci_write_word pci_init libpci.so.3 libc.so.6 LIBPCI_3.1 LIBPCI_3.5 LIBPCI_3.8 LIBPCI_3.0 GLIBC_2.7 GLIBC_2.4 GLIBC_2.34 GLIBC_2.2.5 GLIBC_2.3.4 ; P a)| Q e)| \ h)| g `)| r G ii } ii ui ti _ _ t t t 0 p 8 t @ t H s ȟ П ؟ / 3 0 2 h p x Ȟ О ؞ ( 0 8 ! @ " H # P $ X % ` & h ' p ( x ) * + , - . 1 HH HtH 52~ %4~ @ h f h f h f h f h f h f h f h rf h bf h Rf h Bf h 2f h "f h f h f h f h f h f h f h f h f h f h f h rf h bf h Rf h Bf h 2f h "f h f h f h f h f h! f h" f h# f h$ f h% f h& f h' rf h( bf % } f D %{ f D %{ f D %~{ f D %v{ f D %n{ f D %f{ f D %^{ f D %V{ f D %N{ f D %F{ f D %>{ f D %6{ f D %.{ f D %&{ f D % { f D %{ f D %{ f D %{ f D %z f D %z f D %z f D %z f D %z f D %z f D %z f D %z f D %z f D %z f D %z f D %z f D %z f D %z f D %z f D %z f D %~z f D %vz f D %nz f D %fz f D %^z f D %Vz f D %Nz f D UHAWAVAUATSH H dH%( HE1HHHUH-HC@Rz Hu H Ht t/z HJ L%z H E1HHJ HHH~J HrJ y Dž HDž Dž Dž HDž Dž HDž HDž Dž HDž Dž HDž Dž( A$ ( A$ L%I oG HIf@H@ H@ @ @ H L e WctJdb Hbx 1H8SAE 뭃w1VH/x 1ۃ(E D AE 끐o Hx AEH IE_ Hw 1H8AE 9Hw Hc 9 1E1L0HDH HLL4LLH 5 44 84 <4 0u Dž0 HHX@Hu HH HLtHv H HDL<ILxHH4 HH0H H= 4 L L Hu5 L0LHLH HHI9IH HMCHMLI)L? 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U HAUATSHHqHt-Iľ HLAt$ HAŃAAtH1[A\A]]f <H[A\A]]f. UHAVIֺ AUIATI SHLH LFH[@Htt_ HHtj H蛽A:D$ u䋃 A9$ uI Me :f D A9$ t0HHt LK:C tHHu1[A\A]A^] { uLIHff. @ U HAUI ATSHHHtIċ@ Hߍp踻 u1H[A\A]] At$ H߃萻fwӾ H蚼A8E uH tA} u LH1Htr L7{ff. fU HAWAVAUIATI SLH'L ' HLP C pUκLANjC A p A袻S LE̍r2衺S LAƍr2fA苺s LAAsME1L?D LL D A6L AFUfAMe A] AUfAz4AE !<!AE1fAEHL[A\A]A^A_] UHHAWAVAUIATIHzSHHH) H8dH%( HE1H Hǂ HLAƄt>L}LL=oEHLAE HEIE oMAMHEIE(HEdH+%( uH8D[A\A]A^A_]X UHAWAVAUATSHHHuLg@UdH%( HE1M HE1Lu M$$M ' LѺHtL4tHULLHHE HE L}MtHELHHEbtLt3} t?AsE1HEdH+%( uDHHD[A\A]A^A_]H}u=AHEHuLHiҐ H( UHH HXH`HhLpLxt )E)M)U)])e)m)u)}dH%( HH1HE=S4 Dž0 H8HPDž40 H@uHHdH+%( u'fH3 H H0H H߶H U=3 HtSDF H O W APDF APDF APD 1DG H= H f. G W HO ~ WDN H=n DF 1XZff. fU1HAUATL% SHH=H H[HsH;/s H=. 1=SH= 1r%1H=" C Dl f s L1A9HH= 1[A\A]]UHATISH HHHPHXL`Lht#)p)M)U)])e)m)u)}dH%( H81HEH 2 H H( H@Hl H;H01Dž Dž$0 H;L H 諴H3 ^ 贶 @ UHSHH蟵HtH]ÉH= HH %x:%x:%x.%x -> %x:%x:%x.%x %x:%x.%x -> %x:%x.%x Link Negotiated Link Width: %d Available receivers: Rx(%X) - %d, Rx(F) - 6 %s: Fail margin scan full + - Ready Invalid arguments %s +e:co:d: Invalid device ID: %s +r:l:p:t:v:VTg: Margining Ready bit is Clear Error during caps reading Results: Notations: st - steps Voltage Up Down Left Right Receiver = Rx(%X) Error during caps reading. Error Count Limit = %d Parallel Lanes: %d Margining dwell time: %d s Sample Reporting Method: %d Number of Timing Steps: %d Number of Voltage Steps: %d Max Timing Offset: %d Max Voltage Offset: %d Max Lanes: %d Timing [2K Margining - - Lanes [%d ,%d ] Invalid RecNums specified. Invalid lanes specified. ---- Couldn't disable ASPM Rx(%X) - Couldn't run test (%s) Rx(%X) - Grading criteria: EW: pass - %.2f ps EH: pass - %.2f mV , H %5.1f mV (V %5.1f mV - %3dst %s) %Y-%m-%dT%H:%M:%S w Error while saving %s %d,%f, NA,NA,NA, %f,%f,%d,%s, %f,%d,%s NA,NA,NA Rx(%X) - Lane Reversal Using spec only: NAK LIM THR Pass Perfect Link Speed: %d.0 GT/s = Gen %d Unable to allocate %d bytes of memory Links with Lane Margining at the Receiver capabilities: Links not found or you don't have enough privileges. ! Utility requires preliminary preparation of the system. Refer to the pcilmr man page ! Brief usage (see man for all options): pcilmr [--margin] [<common options>] <link port> [<link options>] [<link port> [<link options>] ...] pcilmr --full [<common options>] pcilmr --scan You can specify Downstream or Upstream Port of the Link. Port Specifier: <device/component>: [<domain>:]<bus>:<dev>.<func> Modes: --margin Margin selected Links --full Margin all ready for testing Links in the system (one by one) --scan Scan for Links available for margining Margining options (see man for all options): Common (for all specified links) options: -c Print Device Lane Margining Capabilities only. Do not run margining. Link specific options: -r <recvn>[,<recvn>...] Specify Receivers to select margining targets. Default: all available Receivers (including Retimers). -t <steps> Specify maximum number of steps for Time Margining. -v <steps> Specify maximum number of steps for Voltage Margining. ! Utility requires preliminary preparation of the system. Refer to the pcilmr man page ! Brief usage (see man for all options): pcilmr [--margin] [<common options>] <link port> [<link options>] [<link port> [<link options>] ...] pcilmr --full [<common options>] pcilmr --scan You can specify Downstream or Upstream Port of the Link. Port Specifier: <device/component>: [<domain>:]<bus>:<dev>.<func> Modes: --margin Margin selected Links --full Margin all ready for testing Links in the system (one by one) --scan Scan for Links available for margining Margining options (see man for all options): Common (for all specified links) options: -c Print Device Lane Margining Capabilities only. Do not run margining. Link specific options: -r <recvn>[,<recvn>...] Specify Receivers to select margining targets. Default: all available Receivers (including Retimers). -t <steps> Specify maximum number of steps for Time Margining. -v <steps> Specify maximum number of steps for Voltage Margining. Links not found or you don't have enough privileges. No such PCI device: %s or you don't have enough privileges. Cannot find pair for the specified device: %s Looks like you don't have enough privileges to access Device Configuration Space. Try to run utility as root. Link %s is not ready for margining. Link data rate must be 16 GT/s or 32 GT/s. Downstream Component must be at D0 PM state. %1[1-6]%1[tv]=%f%n%3[%,ps]%n%1[f]%n %1[1-6]%1[tv]=%1[f]%n,%f%n%2[ps%]%n Margining prerequisites are not satisfied (16/32 GT/s, D0) Invalid lanes specified with arguments Invalid receivers specified with arguments Margining statuses: LIM - ErrorCount exceeded Error Count Limit (found device limit) NAK - Device didn't execute last command, so result may be less reliable THR - The set (using the utility options) step threshold has been reached Couldn't disable ASPM on the given Link. Margining Ready bit is Clear. Rx(A) is Intel Ice Lake RC port. Applying next quirks for margining process: - Set MaxVoltageOffset to 12 (120 mV); - Force the use of 'one side is the whole' grading mode. Independent Error Sampler: %d Independent Left and Right Timing Margining: %d Voltage Margining Supported: %d Independent Up and Down Voltage Margining: %d Warning: device uses Lane Reversal. However, utility uses logical lane numbers in arguments and for logging. Warning: Vendor chose not to report the Max Timing Offset. Utility will use its max possible value - 50 (50%% UI). Warning: Vendor chose not to report the Max Voltage Offset. Utility will use its max possible value - 50 (500 mV). - ETA: %3ds Steps: %3d Total ETA: %3dm %2ds Rx(%X) - EW: independent left/right timing margin is not supported: manual setting - the entire margin across the eye is what is reported by one side margining default - calculating EW as double one side result Rx(%X) - EH: independent up and down voltage margining is not supported: default - calculating EH as double one side result Rx(%X) - Attention: Vendor chose not to report the Max Voltage Offset. Utility used its max possible value (500 mV) for calculations of mV. Keep in mind that for voltage results of this receiver only steps values are reliable. Rx(%X) Lane %2d: %s (W %4.1f%% UI - %5.2fps ) (L %4.1f%% UI - %5.2fps - %2dst %s) (R %4.1f%% UI - %5.2fps - %2dst %s) ) (T %4.1f%% UI - %5.2fps - %2dst %s) (U %5.1f mV - %3dst %s) (D %5.1f mV - %3dst %s) %s/lmr_%0*x.%02x.%02x.%x_Rx%X_%s.csv Lane,EW Min,EW Rec,EW,EH Min,EH Rec,EH,Lane Status,Left %% UI,Left ps,Left Steps,Left Status,Right %% UI,Right ps,Right Steps,Right Status,Up mV,Up Steps,Up Status,Down mV,Down Steps,Down Status EW: minimum - %.2f ps; recommended - %.2f ps EH: minimum - %.2f mV; recommended - %.2f mV Rx(%X) - Attention: Vendor chose not to report the Max Timing Offset. Utility used its max possible value (50%% UI) for calculations of %% UI and ps. Keep in mind that for timing results of this receiver only steps values are reliable. ɤpppppppppppppppppppppppppppppppppppppɢpppp\ppp>pܡpppcilmr @O@ @?@ 5@ 3@ .@ .@ 7@㥛 P$@ 2@ "@ I@ Y@ $@; H X0 x hH h 8 , H\ < h X zR x & D $ 4 FJ w ?9*3$" \ ( t = AM Am , 8 AM Ex E [ ( AM Cw P D , l AG BHJD A 4 8 AC DNHD E o E , p E AC DEED{ G ( v AM EJ C U , 8 AC BJEI D $ AH BKr H ( $ I AH FEP$ , P AF FEL A ( d( AC M A h AC C $ $ AJ J K r $ AE DH $ AC BK @ * AC AV A , d 9 EC Pz" A _ _ t t t p t t s ; G n o 0 8 X P o o X o o o P 0 @ P ` p ! ! ! 0! @! P! `! p! ! ! ! ! ! ! ! ! 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