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ELF > p4 @ @ 8 @ @ @ @ 0 0 0 i i P Ы Ы Ы 8 8 8 0 0 h h h Std 8 8 8 0 0 Ptd ` ` ` Qtd Rtd P P /lib64/ld-linux-x86-64.so.2 GNU GNU M?u͈W!gP GNU t ~FDO {"type":"deb","os":"ubuntu","osVersion":"24.10","name":"pciutils","version":"1:3.13.0-1","architecture":"amd64"} A A em 9 r F 1 x U D l V - N = ( [ Q e z k M c " % " 4 " __libc_start_main __cxa_finalize qsort __stack_chk_fail __printf_chk stdout putchar __sprintf_chk realloc __memset_chk memset calloc malloc strcmp getopt optarg optind stderr __fprintf_chk strchr exit fputs fwrite __vsnprintf_chk __vfprintf_chk fputc strncpy free _ITM_deregisterTMCloneTable __gmon_start__ _ITM_registerTMCloneTable pci_free_dev pci_filter_match pci_read_byte pci_set_name_list_path pci_filter_parse_slot pci_alloc pci_filter_init pci_walk_params pci_read_vpd pci_get_string_property pci_cleanup pci_fill_info pci_lookup_method pci_read_block pci_get_dev pci_filter_parse_id pci_get_method_name pci_scan_bus pci_read_word pci_set_param pci_lookup_name pci_init pci_setup_cache kmod_module_get_module kmod_load_resources kmod_unref kmod_module_new_from_lookup kmod_module_get_name kmod_list_next kmod_module_unref_list kmod_module_unref kmod_new libpci.so.3 libkmod.so.2 libc.so.6 LIBKMOD_5 LIBPCI_3.1 LIBPCI_3.5 LIBPCI_3.6 LIBPCI_3.13 LIBPCI_3.8 LIBPCI_3.0 GLIBC_2.4 GLIBC_2.34 GLIBC_2.2.5 GLIBC_2.3.4 k j _ p a)| e)| f)| h)| `)| x ii ui ti P5 5 Ȩ Ш - ب @ U ez d t p ( 0 8 @ H P X ` h p x Ä p ʄ ̈́ ӄ ׄ ȩ ܄ Щ ة ( 0 & 8 - @ 4 H ; P B X F ` J h N p R x V [ ` f j k p u y Ȫ } ت y ( Ѕ 8 ޅ H X h x . ? ȫ p A ȯ Я د , / 8 < > ( 0 8 @ H P X ` h p x Ȯ Ю خ ! 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UHAWAVAUIHwn ATIHSH( HLM|$AO EG dH%( HE1/H ؗ IHu~f D HHtpL9c@uK8 DC<D9 Hn LL1HHEdH+%( HLHH( [A\A]A^A_] D Z u6LLHEdH+%( H( [A\A]A^A_]f D EOEG1HH= LHWm LH1 I Hl LL1H! @ Hm LL1H UHATISH HHHPHXL`Lht#)p)M)U)])e)m)u)}dH%( H81HEH H 5s H( H@HQ H;H01Dž Dž$0 ^ H;L H H3 z P UHAVAUI ATISu H HIT$@IEMt$I]Hz It$8AN DNAfCEF DC z FC z tqV S Av RP1H5L XAF Z8Ct H=L V C 8C r He[A\A]A^]H=M 4 C C He[A\A]A^]þ H=| 1 H=i 1 H=V 1 H= 1 @ U HAWE1AVAAUATA SHH}fE Ab fD;}# A^H} C0 LmAL)KLDKAA?MfEufEʃf H5 j 1 }7D LH5i 11 D t DtωMM̃ u1f D DDt{ HH=/R [A\A]A^A_]d H[A\A]A^A_]UHH56K 1[ A\A]A^A_]P UHAVAUL-% ATISH 0 Xf D H5 <HH= H HH %IH HL H= HtH H= HuI|$ _ID$H HtAH= LOxsH=\ H=M H[H=E H5 E1[A\@ LA]A^] LHߺ [LA\ A]A^] D H 1H:HJ U11HH0 Ht#H+ xBЉ ] H , H=I H1҉Љ ] @ H 1H:HI Q1ff. f UHAUAATASH( H|HtVHPD HP HS(DhH@ H@ HXHtHBH{ HC(t H[A\A]]ÐHC H[A\A]]þ( H=} UHSHHHtH]ÉH=O bf UHAUATSH H ݏ dH%( HE1HtKHCIHu HHPHXHHuLf D HLLL/H[HuHEdH+%( uH [A\A]] @ U1HAWAVAAUATSH(D-? EAIʼnEH& D@$HcH@H HHEE DEE1fD9tAA U yA E1 AE9~͕̋ D9tyuH= EDD1HH#fwwE Eȅ HEH CHtOHHEVHEHP@z HP8RtuH}HHEoHEHH6f D H DHEȅgU̿ 1EEDH5F >HEH BHDH=:d H([A\A]A^A_]ËỦH5d 1 DE DEY H= 1 UHcHHAUAATSHH HHX@HtGAC HH@Hx tC HHt#Hғ D9| S D9~C HHuH[A\A]] HXmff. Hufoi f HreservedG H HH CInternal bug: Accessing non-read configuration byte at position %x memory space, non-prefetchable VF memory space, non-prefetchable allocation behind bridge, non-prefetchable memory allocation behind bridge, prefetchable memory allocation behind bridge, I/O space memory space resource unavailable for use I/O space resource unavailable for use entry unavailable for use, PrimaryProperties should be used Range%d: %016lx-%016lx [size=0x%lx] Valid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds checksum %s, %d byte(s) reserved Unknown %s resource type %02x, will not decode more. Unable to allocate %d bytes of memory Flags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c) Status: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c HyperTransport: Slave or Primary Interface !!! Possibly incomplete decoding Command: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c Link Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x Link Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s IsocEn%c LSEn%c ExtCTL%c 64b%c Link Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c Link Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x Link Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s Link Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c Link Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c Link Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c Feature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c Link Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c Link Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c Error Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c Prefetchable memory behind bridge Upper: %02x-%02x Command: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c Command: WarmRst%c DblEnd%c Link Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c Link Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x Link Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c Link Config: MLWI=%s MLWO=%s LWI=%s LWO=%s HyperTransport: Host or Secondary Interface Link Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c Link Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c Feature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c DpcCap: IntMsgNum %d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c DpcCtl: Trigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c DpcSta: Trigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x Command: DPERE%c ERO%c RBC=%d OST=%d Status: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c MSI: Enable%c Count=%d/%d Maskable%c 64bit%c Masking: %08x Pending: %08x UESta: DLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c ECRC%c UnsupReq%c ACSViol%c UncorrIntErr%c BlockedTLP%c AtomicOpBlocked%c TLPBlockedErr%c PoisonTLPBlocked%c DMWrReqBlocked%c IDECheck%c MisIDETLP%c PCRC_CHECK%c TLPXlatBlocked%c UEMsk: DLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c ECRC%c UnsupReq%c ACSViol%c UncorrIntErr%c BlockedTLP%c AtomicOpBlocked%c TLPBlockedErr%c PoisonTLPBlocked%c DMWrReqBlocked%c IDECheck%c MisIDETLP%c PCRC_CHECK%c TLPXlatBlocked%c UESvrt: DLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c ECRC%c UnsupReq%c ACSViol%c UncorrIntErr%c BlockedTLP%c AtomicOpBlocked%c TLPBlockedErr%c PoisonTLPBlocked%c DMWrReqBlocked%c IDECheck%c MisIDETLP%c PCRC_CHECK%c TLPXlatBlocked%c CESta: RxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c CorrIntErr%c HeaderOF%c CEMsk: RxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c CorrIntErr%c HeaderOF%c AERCap: First Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c MultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c HeaderLog: %08x %08x %08x %08x RootCmd: CERptEn%c NFERptEn%c FERptEn%c RootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsgNum %d Caps: LPEVC=%d RefClk=%s PATEntryBits=%d Port Arbitration Table [%x] <?> Caps: PATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c Ctrl: Enable%c ID=%d ArbSelect=%s TC/VC=%02x Status: NegoPending%c InProgress%c Desc: PortNumber=%02x ComponentID=%02x EltType=%s Addr: %02x:%02x.%d CfgSpace=%08x%08x Desc: TargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c Root Complex Event Collector Endpoint Association AssociatedBusNumbers: %02x-%02x PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c PortCommonModeRestoreTime=%dus L1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c Requester%c Responder%c Root%c Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x Root Complex Internal Link <?> Multi-Function Virtual Channel <?> Root Complex Register Block <?> ACSCap: SrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c DirectTrans%c ACSCtl: SrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c DirectTrans%c Alternative Routing-ID Interpretation (ARI) ARICap: MFVC%c ACS%c, Next Function: %d ARICtl: MFVC%c ACS%c, Function Group: %d Address Translation Service (ATS) ATSCap: Invalidate Queue Depth: %02x ATSCtl: Enable%c, Smallest Translation Unit: %02x Single Root I/O Virtualization (SR-IOV) IOVCap: Migration%c 10BitTagReq%c IntMsgNum %d IOVCtl: Enable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c Function Dependency Link: %02x %08x (%s-bit, %sprefetchable) VF Migration: offset: %08x, BIR: %x Multi-Root I/O Virtualization <?> McastCtl: NumGroups %d, Enable%c McastBAR: IndexPos %d, BaseAddr %016lx McastReceiveVec: %016lx McastBlockAllVec: %016lx McastBlockUntransVec: %016lx McastOverlayBAR: OverlaySize %d PRISta: RF%c UPRGI%c Stopped%c PASID%c Page Request Capacity: %08x, Page Request Allocation: %08x Interrupt vector mode supported Device specific mode supported Steering table in TPH capability structure Steering table in MSI-X table Reserved steering table location Max no snoop latency: %luns LnkCtl3: LnkEquIntrruptEn%c PerformEqu%c Process Address Space ID (PASID) PASIDCap: Exec%c Priv%c, Max PASID Width: %02x PASIDCtl: Enable%c Exec%c Priv%c Vendor=%04x ID=%04x Rev=%d Len=%d CXLCap: Cache%c IO%c Mem%c MemHWInit%c HDMCount %d Viral%c CXLCtl: Cache%c IO%c Mem%c CacheSFCov %d CacheSFGran %d CacheClean%c Viral%c CXLCtl2: DisableCaching%c InitCacheWB&Inval%c InitRst%c RstMemClrEn%c DesiredVolatileHDMStateAfterHotReset%c CXLSta2: ResetComplete%c ResetError%c PMComplete%c Cache Size: %d of unknown unit size (%d) CXLCap3: DefaultVolatile HDM State After: ColdReset%c WarmReset%c HotReset%c HotResetConfigurability%c CXL Extensions DVSEC for Ports CXLPortCtl: UnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c Reserved time scale encoding %x PCIe DVSEC for Flex Bus Port <Wrong length for Revision %d> FBCap: Cache%c IO%c Mem%c 68BFlit%c MltLogDev%c FBCtl: Cache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c FBSta: Cache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c FBModTS: Received FB Data: %06x Block%d: BIR: bar%d, ID: %s, offset: %016lx PCIe DVSEC for Test Capability <?> Lane Margining at the Receiver PortSta: MargReady%c MargSoftReady%c Native PCIe Enclosure Management <?> DOESta: Busy%c IntSta%c Error%c ObjectReady%c IDECap: Lnk=%d Sel=%d FlowThru%c PartHdr%c Aggr%c PCPC%c IDE_KM%c Alg='%s' TCs=%d TeeLim%c %sLinkIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d %sLinkIDE#%d Sta: Status=%s RecvChkFail%c %sSelectiveIDE#%d Cap: RID#=%d %sSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c CFG%c HdrEnc=%s Alg='%s' TC%d ID%d%s %sSelectiveIDE#%d Sta: %s RecvChkFail%c %sSelectiveIDE#%d RID: Valid%c Base=%x Limit=%x SegBase=%x %sSelectiveIDE#%d RID#%d: Valid%c Base=%lx Limit=%lx -6dB de-emphasis, 0dB preshoot -3.5dB de-emphasis, 0dB preshoot -4.4dB de-emphasis, 0dB preshoot -2.5dB de-emphasis, 0dB preshoot 0dB de-emphasis, 1.9dB preshoot 0dB de-emphasis, 2.5dB preshoot -6.0dB de-emphasis, 3.5dB preshoot -3.5dB de-emphasis, 3.5dB preshoot 0dB de-emphasis, 3.5dB preshoot 800-1200mV(full-swing)/400-700mV(half-swing) 200-400mV(full-swing)/100-200mV(half-swing) Link Up - Present and DRS Received Status: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s Command: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s Slot ID: %d slots, First%c, chassis %02x Secondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s Status: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Upstream: Capacity=%u CommitmentLimit=%u Downstream: Capacity=%u CommitmentLimit=%u HyperTransport: Interrupt Discovery and Configuration HyperTransport: Revision ID: %u.%02u HyperTransport: UnitID Clumping HyperTransport: Extended Configuration Space Access HyperTransport: Address Mapping HyperTransport: MSI Mapping Enable%c Fixed%c Mapping Address Base: %016lx HyperTransport: X86 (reserved) BAR=%d offset=%08x size=%08x Debug port: BAR=%d offset=%04x CompactPCI central resource control <?> PCI-Express to PCI/PCI-X Bridge PCI/PCI-X to PCI-Express Bridge (Slot%c) Root Complex Integrated Endpoint DevCap: MaxPayload %d bytes, PhantFunc %d DevCtl: CorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c MaxPayload %d bytes, MaxReadReq %d bytes DevSta: CorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c LnkCap: Port #%d, Speed %s, Width x%d, ASPM %s ClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c LnkDisable%c CommClk%c ExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c LnkSta: Speed %s%s, Width x%d%s TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c Disabled%c CommClk%c ExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c SltCap: AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c SltCtl: Enable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c Control: AttnInd %s, PwrInd %s, Power%c Interlock%c SltSta: Status: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c Changed: MRL%c PresDet%c LinkState%c RootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c RootSta: PME ReqID %04x, PMEStatus%c PMEPending%c DevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c EmergencyPowerReduction %s, EmergencyPowerReductionInit%c DevCtl2: Completion Timeout: %s, TimeoutDis%c IDOReq%c IDOCompl%c LTR%c EmergencyPowerReductionReq%c 10BitTagReq%c OBFF %s, EETLPPrefixBlk%c LnkCap2: Supported Link Speeds: %s, Crosslink%c Retimer%c 2Retimers%c DRS%c LnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c Compliance Preset/De-emphasis: %s LnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c Retimer%c 2Retimers%c CrosslinkRes: %s , DRS%c DownstreamComp: %s MSI-X: Enable%c Count=%d Masked%c Vector table: BAR=%d offset=%08x Enhanced Allocation (EA): NumEntries=%u , secondary=%d, subordinate=%d Entry %u: Enable%c Writable%c EntrySize=%u BAR Equivalent Indicator: Unknown resource behind bridge Prefetchable memory behind bridge !!! Invalid class %04x for header type %02x !!! Unknown header type %02x Control: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c Status: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c Interrupt: pin %c routed to IRQ %d Bus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d !!! Unknown I/O range types %x/%x !!! Unknown memory range types %x/%x !!! Unknown prefetchable memory range types %x/%x Secondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c BridgeCtl: Parity%c SERR%c NoISA%c VGA%c VGA16%c MAbort%c >Reset%c FastB2B%c PriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c Memory window %d: %08x-%08x%s%s BridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c 16-bit legacy interface ports at %04x WARNING: Cannot show hex-dump of the config space Unknown hardware configuration type %s No such PCI access method: %s (see `-A help' for a list) Invalid PCI access parameter syntax: %s Unrecognized PCI access parameter: %s (see `-O help' for a list) Bus mapping mode does not recognize bus topology WARNING: Bus mapping can be reliable only with direct hardware access enabled. Tree: bridge %04x:%02x:%02x.%d: %02x -> %02x-%02x Tree: bridge %04x:%02x:%02x.%d ## %02x:%02x.%d is a bridge from %02x to %02x-%02x !!! Bridge points to invalid primary bus. !!! Bridge points to invalid bus range. <error in resizable BAR: num_bars=%d is out of specification> lspci: libkmod lookup failed: error %d lspci: Unable to initialize libkmod context lspci: Unable to load libkmod resources: error %d Discovered device %04x:%02x:%02x.%d I/O space VF memory space, prefetchable entry unavailable for use /%02x:%02x.%d /%02x.%d %04x: >600W %gW Volatile Non-volatile CDAT DRAM Storage %s: %s (rev %02x) (prog-if %02x [%s] DeviceName: %s Subsystem: %s %s: %0*lx-%0*lx [size=%u%s] [disabled] [%d-bit] " \\ \x%02x Slot: Device: Class: %s SVendor: %s SDevice: %s PhySlot: %s ProgIf: %02x Rev: %02x Driver: %s Module: %s NUMANode: %d DTNode: %s IOMMUGroup: %s -p%02x -r%02x "" "" Read-only Read/write bad good large small Vital Product Data End Product Name: %s fields: [ ] %s: %d byte(s) free Not readable No end tag found x%d Power Management version %d Bridge: PM%c B3%c DUL%c Revision ID: %u.%02u Link Frequency 0: %s Link Frequency 1: %s Bus Number: %02x Link Frequency: %s Downstream Port Containment Source: %04x non- 32-bit 64-bit low-1M type 3 Region %d: I/O ports at %04lx <ignored> <unassigned> [virtual] %08lx (%s, %sprefetchable) [enhanced] <broken-64-bit-slot> Expansion ROM at [disabled by cmd] simple PCI-X non-bridge device Address: %08x Data: %04x Advanced Error Reporting ErrorSrc: ERR_COR: %04x ERR_FATAL/NONFATAL: %04x Virtual Channel ??%d %c%s%c Ctrl: ArbSelect=%s Status: InProgress%c VC%d: Arb: Port Arbitration Table <?> Root Complex Link Link%d: Addr: %08x%08x Config MemMapped 00000000 [none] ff-00 [none] RCiEPBitmap: RCiEP at Device(s): %s %u -%u AssociatedBusNumbers: %s L1 PM Substates <unreadable> L1SubCap: PortTPowerOnTime=<error> PortTPowerOnTime=%dus T_CommonMode=%dus LTR1.2_Threshold=<error> LTR1.2_Threshold=%luns L1SubCtl2: T_PwrOn=<error> T_PwrOn=%dus Precision Time Measurement PTMCap: PTMClockGranularity: Unimplemented Greater than 254ns %huns PTMControl: Enabled%c RootSelected%c PTMEffectiveGranularity: Unknown 32 64 vendor-specific Default =2 =4 =8 insecure reserved no 17:2 25:2 33:2 Capabilities: [%03x v%d <chain looped> Null Power Budgeting <?> Vendor Specific Information: ID=%04x Rev=%d Len=%03x <?> Access Control Services IOVSta: Migration%c Initial VFs: %d, Total VFs: %d, Number of VFs: %d, VF offset: %d, stride: %d, Device ID: %04x Supported Page Size: %08x, System Page Size: %08x Region %d: Memory at Multicast McastCap: MaxGroups %d , WindowSz %d (%d bytes) , ECRCRegen%c (disabled) , BaseAddr %016lx Page Request Interface (PRI) PRICtl: Enable%c Reset%c Physical %s Resizable BAR Dynamic Power Allocation <?> Transaction Processing Hints Extended requester support No steering table available Latency Tolerance Reporting Max snoop latency: %luns Secondary PCI Express LaneErrStat: LaneErr at lane: Protocol Multiplexing <?> LN Requester <?> PCI Express over M_PHY <?> FRS Queueing <?> Readiness Time Reporting <?> Designated Vendor-Specific: : CXL PCIe DVSEC for CXL Devices CXLSta: Viral%c CXLCap2: Cache Size: %08x Cache Size Not Reported <?> Non-CXL Function Map DVSEC FuncMap 0: %08x FuncMap 1: %08x FuncMap 2: %08x FuncMap 3: %08x FuncMap 4: %08x FuncMap 5: %08x FuncMap 6: %08x FuncMap 7: %08x CXLPortSta: PMComplete%c AlternateBus: %02x-%02x AlternateBus: %04x-%04x GPF DVSEC for CXL Ports GPF Phase 1 Timeout: %d%s GPF Phase 2 Timeout: %d%s GPF DVSEC for CXL Devices GPF Phase 2 Duration: %u%s GPF Phase 2 Power: %umW 256BFlit%c PBRFlit%c FBCap2: NOPHint%c FBCtl2: NOPHint%c FBSta2: NOPHintInfo: %x Register Locator DVSEC MLD DVSEC NumLogDevs: %d Unknown ID %04x Virtual Data Link Feature <?> Physical Layer 16.0 GT/s <?> PortCap: Uses Driver%c Hierarchy ID <?> Physical Layer 32.0 GT/s <?> Data Object Exchange DOECap: IntSup%c IntMsgNum %d DOECtl: IntEn%c 41:2 Integrity & Data Encryption IDECtl: FTEn%c [%x] Extended Capability ID %#02x CommonCfg Notify ISR DeviceCfg not supported 2.5GT/s unknown (overdriven) (downgraded) Not Supported Range A Range B Range AB Range BC Range ABC Range BCD Range ABCD Via message Via WAKE# Via message/WAKE# Form Factor Dev Specific Reserved 64byte cachelines 128byte cachelines TPHComp+ ExtTPHComp- TPHComp+ ExtTPHComp+ TPHComp- ExtTPHComp- 50us to 50ms 50us to 100us 1ms to 10ms 16ms to 55ms 65ms to 210ms 260ms to 900ms 1s to 3.5s 4s to 13s 17s to 64s Disabled Via message A Via message B RsvdP 2.5-64GT/s 2.5-32GT/s 2.5-16GT/s 2.5-8GT/s 2.5-5GT/s -6dB -3.5dB 0dB de-emphasis, 0dB preshoot Normal Operating Range unsupported Upstream Port Downstream Port incomplete Link Down - Not Determined Link Down - Not Present Link Down - Present Link Up - Present L0s L1 L0s Capabilities: <access denied> [%02x] <chain broken> AGP version %x.%x CompactPCI hot-swap <?> PCI-X bridge device HyperTransport: Switch HyperTransport: DirectRoute HyperTransport: VCSet HyperTransport: Retry Mode HyperTransport: #%02x VirtIO: %s multiplier=%08x Len=%02x <?> Hot-plug capable AGP3 <?> Secure device <?> Express (v%d) Legacy Endpoint Root Port (Slot%c) , IntMsgNum %d Downstream Port (Slot%c) Root Complex Event Collector Unknown type %d , Latency L0s %s, L1 %s ExtTag%c AttnBtn%c AttnInd%c PwrInd%c RBE%c FLReset%c SlotPowerLimit TEE-IO%c BrConfRtry%c , Exit Latency L0s %s %sL1 %s LnkCtl: ASPM %s; RCB %d bytes, Slot #%d, PowerLimit ; Interlock%c NoCompl%c RootCap: CRSVisible%c , MaxEETLPPrefixes %d FRS%c LN System CLS %s, ARIFwd%c AtomicOpsCap: Routing%c 32bit%c 64bit%c 128bitCAS%c AtomicOpsCtl: ReqEn%c EgressBlck%c , Selectable De-emphasis: %s PBA: BAR=%d offset=%08x SATA HBA v%d.%d BAR%d Offset=%08x InCfgSpace BAR??%d PCI Advanced Features AFCap: TP%c FLR%c AFCtrl: FLR%c AFStatus: TP%c resource behind function not indicated expansion ROM VF-BAR %u PrimaryProperties: [%02x] SecondaryProperties: Base: MaxOffset: Capability ID %#02x [%04x] slow medium fast ?? (prefetchable) I/O behind bridge Memory behind bridge Kernel modules: Physical Slot: %s Device tree node: %s Latency: %d ( %dns min %dns max , Cache Line Size: %d bytes NUMA node: %d IOMMU group: %s Flags: bus master, VGA palette snoop, stepping, fast Back2Back, 66MHz, user-definable features, %s devsel , latency %d , IRQ %d , NUMA node %d , IOMMU group %s BIST is running BIST result: %02x I/O window %d: %08x-%08x%s Secondary status: SERR <access denied to the rest> Kernel driver in use: %s %s %s %02x: --version lspci version 3.13.0 -s: %s -d: %s dump.name help Known PCI access methods: Known PCI access parameters: %-20s %s (%s) Summary of buses: %02x: Entered via %02x:%02x.%d Primary host bus Secondary host bus (?) %02x.%d Bridge to %02x-%02x <overlap bug> <crossing bug> Tree: domain %04x %dMB %dGB %dTB %dPB %dEB <unknown> empty component registers BAR virtualization CXL device registers CPMU registers L0s Enabled L0s L1 Enabled <1us <2us <4us <8us <16us <32us <64us unlimited <64ns <128ns <256ns <512ns On Blink Off conv 66MHz 100MHz 133MHz ?4 ?5 ?6 ?7 200MHz 300MHz 400MHz 500MHz 600MHz 800MHz 1.0GHz 1.2GHz 1.4GHz 1.6GHz [a] [b] [c] [d] [e] Vend 8bit 16bit [2] 32bit 4bit [6] N/C Extended capability Engineering changes Manufacture ID Part number Read-write area Serial number Asset tag Vendor specific System specific CCIN Feature code FRU Network address Firmware version Product specific ... -- \- +- \-[%04x:%02x]- +-[%04x:%02x]- %02x.%x -[%02x]- -[%02x-%02x]- %s BAR %d: current size: , supported: Mapping bus %04x:%02x But it was filtered out. ȯЯ ( @ hP ( p ` #" ""!0!@ ( H 0 h( H 0 X p-12,1+1(?'&&AA@@@@x@p?>>>???z>O>A==<;AOO O OO PPUPINmPBBBBBBHD0DDCCCCCCelllRRlslRRRRRRgl[llllllllll{lollloje\<_E`,`__`lcllwlla`x``____maaaUaIa=a1a`qmemYmMmAm5mlDjDj&jjji/j kkjkjjpjdjXjLj@j4j(j jg|jklkkk l`ԞmPD8(d ؝ϝƝaaaa^aaaaaa̅̅̅̅̅̅̅̅̅̅ ,,,, Config Egress Internal Fixed WRR32 WRR64 WRR128 TWRR128 WRR256 ??6 ??7 Fixed WRR32 WRR64 WRR128 ??4 ??5 ??6 ??7 100ns ?= #<o: 7 d @ w K M G T @ AES-GCM-256-96b @ @ lspci ; ; P@ `X p Щ $ H \ `@ l ` 8 x 0 `` 8 h P 4 i ( `@ l 0 @ @x 0 p < d 0@ zR x & D $ 4 FJ w ?9*3$" \ t } ' VL < kL , $ 2 AC I A ( AC ED K C @ e AC A@ K d Ш $ x \7 AM A" A , t AC FQ G , Ԭ AE BELDv M 4r AL C] 4 $ JC BIIEd F ` ( \ < AC DK C , , AC DV D 0 AF BEGEh F [ , 8 EF FGDk I 4 ػ AE DJK I E < T t AC BGFB K = K E 4 ~ AC DGDC J H , H AC DKv G 0 ( EC FD H C 0 d SL , L H AQ M J 4 | AC HD3 M B 0 AC HKz G 4 E AN DLEF D O 0 AC BLLv D , T 7 AC BJg I , AC HK\ E 8 p AC BJC E N 8 Dx AC FMq H N B U K < , AC DKr K Q O J F I 4 l X 1 AC \ G 0 H 4 @,5 AC Pn A E 4 a EC I A E , , EC FEHZ A D Pz ( \ { AC DD| H $ { AC E F , | AC G D Q 8 $} AC DL K ] K W E < x~ AG BGF D g E E 4 \ H AC FLN J y G EC BK 0 < AC DJD A _ A 8 EH BEGKA E N A ` 0 $ i EC DID H b F $ X < EG k I k E 0 EC BED[ B N A . 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" " " 0" @" P" `" p" " " " " " " " " # # # 0# @# P# `# p# # # # nvbxs:d:tPi:mgp:qkMDQA:GO:H:F: Usage: lspci [<switches>] Basic display modes: -mm Produce machine-readable output (single -m for an obsolete format) -t Show bus tree Display options: -v Be verbose (-vv or -vvv for higher verbosity) -k Show kernel drivers handling each device -x Show hex-dump of the standard part of the config space -xxx Show hex-dump of the whole config space (dangerous; root only) -xxxx Show hex-dump of the 4096-byte extended config space (root only) -b Bus-centric view (addresses and IRQ's as seen by the bus) -D Always show domain numbers -P Display bridge path in addition to bus and device number -PP Display bus path in addition to bus and device number Resolving of device ID's to names: -n Show numeric ID's -nn Show both textual and numeric ID's (names & numbers) -q Query the PCI ID database for unknown ID's via DNS -qq As above, but re-query locally cached entries -Q Query the PCI ID database for all ID's via DNS Selection of devices: -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]] Show only devices in selected slots -d [<vendor>]:[<device>][:<class>] Show only devices with specified ID's Other options: -i <file> Use specified ID database instead of %s -p <file> Look up kernel modules in a given file instead of default modules.pcimap -M Enable `bus mapping' mode (dangerous; root only) PCI access options: -A <method> Use the specified PCI access method (see `-A help' for a list) -O <par>=<val> Set PCI access parameter (see `-O help' for a list) -G Enable PCI access debugging -H <mode> Use direct hardware access (<mode> = 1 or 2) -F <file> Read PCI configuration dump from a given file /usr/lib/debug/.dwz/x86_64-linux-gnu/pciutils.debug pX80Ȝ3ќ"PWiU d23f94f975d3cd8857f9e92183fd67d3eeba50.debug h .shstrtab .interp .note.gnu.property .note.gnu.build-id .note.ABI-tag .note.package .gnu.hash .dynsym .dynstr .gnu.version .gnu.version_r .rela.dyn .rela.plt .init .plt.got .plt.sec .text .fini .rodata .eh_frame_hdr .eh_frame .init_array .fini_array .data.rel.ro .dynamic .data .bss .gnu_debugaltlink .gnu_debuglink 8 8 0 & h h $ 9 G U o 0 0 $ _ X X 0 g o o | o p B X X @ # # # # @' @' # # 0 0 ^] ` ` H H p Ы Ы H . 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